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LTSpice sim

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This commit is contained in:
Frederico Boavida 2025-03-02 17:01:08 +01:00
parent b1ca202d95
commit 7bfe3ca887
5 changed files with 77 additions and 0 deletions
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17
Hardware/sim/IPD60R.asy Normal file
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Version 4
SymbolType BLOCK
RECTANGLE Normal -96 -40 112 40
WINDOW 0 8 -40 Bottom 2
SYMATTR Prefix X
SYMATTR Value IPD60R210PFD7S_L0
SYMATTR ModelFile C:\Users\frede\Downloads\Infineon-Power_CoolMOS_PFD7_MOSFET_600V_Spice-SimulationModels-v03_00-EN\IPD60R.lib
WINDOW 3 8 40 Top 2
PIN -96 0 LEFT 8
PINATTR PinName drain
PINATTR SpiceOrder 1
PIN 112 -16 RIGHT 8
PINATTR PinName gate
PINATTR SpiceOrder 2
PIN 112 16 RIGHT 8
PINATTR PinName source
PINATTR SpiceOrder 3

46
Hardware/sim/precharge_sim.asc Normal file
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Version 4
SHEET 1 880 680
WIRE -32 96 -368 96
WIRE 272 96 -32 96
WIRE -32 128 -32 96
WIRE -368 192 -368 96
WIRE 272 224 272 96
WIRE -32 240 -32 208
WIRE -32 240 -96 240
WIRE 32 240 -32 240
WIRE -32 256 -32 240
WIRE -96 272 -96 240
WIRE 32 368 32 240
WIRE 48 368 32 368
WIRE 272 384 272 288
WIRE 272 384 256 384
WIRE -368 400 -368 272
WIRE -336 400 -368 400
WIRE -96 400 -96 336
WIRE -96 400 -336 400
WIRE -32 400 -32 336
WIRE -32 400 -96 400
WIRE 48 400 -32 400
WIRE -336 432 -336 400
FLAG -336 432 0
SYMBOL voltage -368 176 R0
WINDOW 3 -65 -79 VRight 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 420 1 1ľ 1ľ 2 3 1)
SYMATTR InstName V1
SYMBOL cap 256 224 R0
SYMATTR InstName C1
SYMATTR Value 44ľ
SYMBOL res -48 112 R0
SYMATTR InstName R1
SYMATTR Value 6.6Mega
SYMBOL res -48 240 R0
SYMATTR InstName R2
SYMATTR Value 150k
SYMBOL cap -112 272 R0
SYMATTR InstName C2
SYMATTR Value 3.3ľ
SYMBOL IPD60R 160 384 M0
SYMATTR InstName U1
TEXT -232 504 Left 2 !.tran 0 2 0.7 1m

14
Hardware/sim/precharge_sim.log Normal file
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LTspice 24.0.12 for Windows
Circuit: * C:\Users\frede\OneDrive\Dokumente\Fasttube\FT25\TS-DCDC\Hardware\sim\precharge_sim.asc
Start Time: Sun Mar 2 17:00:25 2025
solver = Normal
Maximum thread count: 8
tnom = 27
temp = 27
method = modified trap
Instance "m:u1:1:r": Length shorter than recommended for a level 1 MOSFET.
Instance "m:u1:1:r": Width narrower than recommended for a level 1 MOSFET.
Instance "m:u1:1:1": Width narrower than recommended for a level 3 MOSFET.
.OP point found by inspection.
Total elapsed time: 0.097 seconds.

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Hardware/sim/precharge_sim.op.raw Normal file
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Hardware/sim/precharge_sim.raw Normal file
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