LTSpice sim
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										17
									
								
								Hardware/sim/IPD60R.asy
									
									
									
									
									
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										17
									
								
								Hardware/sim/IPD60R.asy
									
									
									
									
									
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Version 4
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SymbolType BLOCK
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RECTANGLE Normal -96 -40 112 40
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WINDOW 0 8 -40 Bottom 2
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SYMATTR Prefix X
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SYMATTR Value IPD60R210PFD7S_L0
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SYMATTR ModelFile C:\Users\frede\Downloads\Infineon-Power_CoolMOS_PFD7_MOSFET_600V_Spice-SimulationModels-v03_00-EN\IPD60R.lib
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WINDOW 3 8 40 Top 2
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PIN -96 0 LEFT 8
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PINATTR PinName drain
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PINATTR SpiceOrder 1
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PIN 112 -16 RIGHT 8
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PINATTR PinName gate
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PINATTR SpiceOrder 2
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PIN 112 16 RIGHT 8
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PINATTR PinName source
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PINATTR SpiceOrder 3
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										46
									
								
								Hardware/sim/precharge_sim.asc
									
									
									
									
									
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										46
									
								
								Hardware/sim/precharge_sim.asc
									
									
									
									
									
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Version 4
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SHEET 1 880 680
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WIRE -32 96 -368 96
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WIRE 272 96 -32 96
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WIRE -32 128 -32 96
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WIRE -368 192 -368 96
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WIRE 272 224 272 96
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WIRE -32 240 -32 208
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WIRE -32 240 -96 240
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WIRE 32 240 -32 240
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WIRE -32 256 -32 240
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WIRE -96 272 -96 240
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WIRE 32 368 32 240
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WIRE 48 368 32 368
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WIRE 272 384 272 288
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WIRE 272 384 256 384
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WIRE -368 400 -368 272
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WIRE -336 400 -368 400
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WIRE -96 400 -96 336
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WIRE -96 400 -336 400
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WIRE -32 400 -32 336
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WIRE -32 400 -96 400
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WIRE 48 400 -32 400
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WIRE -336 432 -336 400
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FLAG -336 432 0
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SYMBOL voltage -368 176 R0
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WINDOW 3 -65 -79 VRight 2
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WINDOW 123 0 0 Left 0
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WINDOW 39 0 0 Left 0
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SYMATTR Value PULSE(0 420 1 1<> 1<> 2 3 1)
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SYMATTR InstName V1
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SYMBOL cap 256 224 R0
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SYMATTR InstName C1
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SYMATTR Value 44<34>
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SYMBOL res -48 112 R0
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SYMATTR InstName R1
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SYMATTR Value 6.6Mega
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SYMBOL res -48 240 R0
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SYMATTR InstName R2
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SYMATTR Value 150k
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SYMBOL cap -112 272 R0
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SYMATTR InstName C2
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SYMATTR Value 3.3<EFBFBD>
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SYMBOL IPD60R 160 384 M0
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SYMATTR InstName U1
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TEXT -232 504 Left 2 !.tran 0 2 0.7 1m
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										14
									
								
								Hardware/sim/precharge_sim.log
									
									
									
									
									
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										14
									
								
								Hardware/sim/precharge_sim.log
									
									
									
									
									
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LTspice 24.0.12 for Windows
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Circuit: * C:\Users\frede\OneDrive\Dokumente\Fasttube\FT25\TS-DCDC\Hardware\sim\precharge_sim.asc
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Start Time: Sun Mar  2 17:00:25 2025
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solver = Normal
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Maximum thread count: 8
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tnom = 27
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temp = 27
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method = modified trap
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Instance "m:u1:1:r": Length shorter than recommended for a level 1 MOSFET.
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Instance "m:u1:1:r": Width narrower than recommended for a level 1 MOSFET.
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Instance "m:u1:1:1": Width narrower than recommended for a level 3 MOSFET.
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.OP point found by inspection.
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Total elapsed time: 0.097 seconds.
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								Hardware/sim/precharge_sim.op.raw
									
									
									
									
									
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								Hardware/sim/precharge_sim.raw
									
									
									
									
									
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								Hardware/sim/precharge_sim.raw
									
									
									
									
									
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