992 lines
65 KiB
Plaintext
992 lines
65 KiB
Plaintext
ARM GAS /tmp/ccVidTYQ.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 1
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "stm32f3xx_hal_pwr.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c"
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20 .section .text.HAL_PWR_DeInit,"ax",%progbits
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21 .align 1
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22 .global HAL_PWR_DeInit
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23 .syntax unified
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24 .thumb
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25 .thumb_func
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27 HAL_PWR_DeInit:
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28 .LFB130:
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1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
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3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @file stm32f3xx_hal_pwr.c
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4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @author MCD Application Team
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5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver.
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6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This file provides firmware functions to manage the following
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7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
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8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Initialization/de-initialization functions
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9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Peripheral Control functions
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10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
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12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
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13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @attention
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14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * <h2><center>© Copyright (c) 2016 STMicroelectronics.
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16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * All rights reserved.</center></h2>
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17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license,
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19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the
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20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * License. You may obtain a copy of the License at:
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21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause
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22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
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24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
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27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #include "stm32f3xx_hal.h"
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28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @addtogroup STM32F3xx_HAL_Driver
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30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
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ARM GAS /tmp/ccVidTYQ.s page 2
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31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR
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34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver
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35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
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36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
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39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
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41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
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42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
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43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
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44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
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45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
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46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
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48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
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49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
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53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
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55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
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56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
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57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
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58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
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59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data
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60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted
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61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** write accesses.
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62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
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63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
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64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
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65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
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66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
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68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
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69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values.
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73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
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74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
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76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
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29 .loc 1 76 1 view -0
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30 .cfi_startproc
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31 @ args = 0, pretend = 0, frame = 0
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32 @ frame_needed = 0, uses_anonymous_args = 0
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33 @ link register save eliminated.
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77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
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34 .loc 1 77 3 view .LVU1
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35 0000 044B ldr r3, .L2
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36 0002 1A69 ldr r2, [r3, #16]
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37 0004 42F08052 orr r2, r2, #268435456
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38 0008 1A61 str r2, [r3, #16]
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ARM GAS /tmp/ccVidTYQ.s page 3
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78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
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39 .loc 1 78 3 view .LVU2
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40 000a 1A69 ldr r2, [r3, #16]
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41 000c 22F08052 bic r2, r2, #268435456
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42 0010 1A61 str r2, [r3, #16]
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79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
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43 .loc 1 79 1 is_stmt 0 view .LVU3
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44 0012 7047 bx lr
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45 .L3:
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46 .align 2
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47 .L2:
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48 0014 00100240 .word 1073876992
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49 .cfi_endproc
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50 .LFE130:
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52 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
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53 .align 1
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54 .global HAL_PWR_EnableBkUpAccess
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55 .syntax unified
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56 .thumb
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57 .thumb_func
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59 HAL_PWR_EnableBkUpAccess:
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60 .LFB131:
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80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC
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83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
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84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
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85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
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86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
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87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
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89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
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61 .loc 1 89 1 is_stmt 1 view -0
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62 .cfi_startproc
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63 @ args = 0, pretend = 0, frame = 0
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64 @ frame_needed = 0, uses_anonymous_args = 0
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65 @ link register save eliminated.
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90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP);
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66 .loc 1 90 3 view .LVU5
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67 0000 024A ldr r2, .L5
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68 0002 1368 ldr r3, [r2]
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69 0004 43F48073 orr r3, r3, #256
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70 0008 1360 str r3, [r2]
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91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
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71 .loc 1 91 1 is_stmt 0 view .LVU6
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72 000a 7047 bx lr
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73 .L6:
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74 .align 2
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75 .L5:
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76 000c 00700040 .word 1073770496
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77 .cfi_endproc
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78 .LFE131:
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80 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
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81 .align 1
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82 .global HAL_PWR_DisableBkUpAccess
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83 .syntax unified
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84 .thumb
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ARM GAS /tmp/ccVidTYQ.s page 4
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85 .thumb_func
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87 HAL_PWR_DisableBkUpAccess:
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88 .LFB132:
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92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC
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95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
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96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
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97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
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98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
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99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
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101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
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89 .loc 1 101 1 is_stmt 1 view -0
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90 .cfi_startproc
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91 @ args = 0, pretend = 0, frame = 0
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92 @ frame_needed = 0, uses_anonymous_args = 0
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93 @ link register save eliminated.
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102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP);
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94 .loc 1 102 3 view .LVU8
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95 0000 024A ldr r2, .L8
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96 0002 1368 ldr r3, [r2]
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97 0004 23F48073 bic r3, r3, #256
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98 0008 1360 str r3, [r2]
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103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
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99 .loc 1 103 1 is_stmt 0 view .LVU9
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100 000a 7047 bx lr
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101 .L9:
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102 .align 2
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103 .L8:
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104 000c 00700040 .word 1073770496
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105 .cfi_endproc
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106 .LFE132:
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108 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
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109 .align 1
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110 .global HAL_PWR_EnableWakeUpPin
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111 .syntax unified
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112 .thumb
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113 .thumb_func
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115 HAL_PWR_EnableWakeUpPin:
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116 .LVL0:
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117 .LFB133:
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104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
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106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @}
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107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
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108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
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110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Low Power modes configuration functions
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111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
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112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
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113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
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115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Peripheral Control functions #####
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116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
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117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** WakeUp pin configuration ***
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ARM GAS /tmp/ccVidTYQ.s page 5
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119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================
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120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
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121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
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122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** forced in input pull down configuration and is active on rising edges.
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123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) There are up to three WakeUp pins:
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124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 1 on PA.00.
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125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
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126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 3 on PE.06.
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127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
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128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Main and Backup Regulators configuration ***
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129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================================
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130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
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131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
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132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to
|
||
133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** save battery life.
|
||
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read
|
||
136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** protected to prevent confidential data, such as cryptographic private
|
||
137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** key, from being accessed. The backup SRAM can be erased only through
|
||
138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the Flash interface when a protection level change from level 1 to
|
||
139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** level 0 is requested.
|
||
140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** -@- Refer to the description of Read protection (RDP) in the Flash
|
||
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programming manual.
|
||
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Refer to the datasheets for more details.
|
||
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Low Power modes configuration ***
|
||
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =====================================
|
||
147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The devices feature 3 low-power modes:
|
||
149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
|
||
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator
|
||
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** in low power mode
|
||
152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
|
||
153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Sleep mode ***
|
||
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ==================
|
||
156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
|
||
158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
|
||
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** functions with
|
||
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
|
||
164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||
165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode.
|
||
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Stop mode ***
|
||
168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =================
|
||
169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
|
||
171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||
172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** are preserved.
|
||
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode to minimize the co
|
||
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
|
||
ARM GAS /tmp/ccVidTYQ.s page 6
|
||
|
||
|
||
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN
|
||
177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** function with:
|
||
178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Main regulator ON or
|
||
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Low Power regulator ON.
|
||
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
|
||
181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
|
||
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
|
||
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
|
||
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** when programmed in wakeup mode (the peripheral must be
|
||
186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programmed in wakeup mode and the corresponding interrupt vector
|
||
187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** must be enabled in the NVIC).
|
||
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Standby mode ***
|
||
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ====================
|
||
191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based
|
||
193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
|
||
194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
|
||
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost
|
||
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby
|
||
197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** circuitry.
|
||
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator is OFF.
|
||
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
|
||
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
|
||
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
|
||
204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||
205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
|
||
207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================
|
||
208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
|
||
209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||
210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||
211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode).
|
||
212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||
214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||
216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||
217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||
219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||
220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
|
||
221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||
223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT()
|
||
224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode
|
||
226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
|
||
228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c
|
||
229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling
|
||
230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||
231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the comparator to generate the event.
|
||
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
|
||
ARM GAS /tmp/ccVidTYQ.s page 7
|
||
|
||
|
||
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
|
||
234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality.
|
||
238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
|
||
239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be value of :
|
||
240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
|
||
241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||
244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
118 .loc 1 244 1 is_stmt 1 view -0
|
||
119 .cfi_startproc
|
||
120 @ args = 0, pretend = 0, frame = 0
|
||
121 @ frame_needed = 0, uses_anonymous_args = 0
|
||
122 @ link register save eliminated.
|
||
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
|
||
246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
123 .loc 1 246 3 view .LVU11
|
||
247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Enable the EWUPx pin */
|
||
248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx);
|
||
124 .loc 1 248 3 view .LVU12
|
||
125 0000 024A ldr r2, .L11
|
||
126 0002 5368 ldr r3, [r2, #4]
|
||
127 0004 0343 orrs r3, r3, r0
|
||
128 0006 5360 str r3, [r2, #4]
|
||
249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
129 .loc 1 249 1 is_stmt 0 view .LVU13
|
||
130 0008 7047 bx lr
|
||
131 .L12:
|
||
132 000a 00BF .align 2
|
||
133 .L11:
|
||
134 000c 00700040 .word 1073770496
|
||
135 .cfi_endproc
|
||
136 .LFE133:
|
||
138 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
|
||
139 .align 1
|
||
140 .global HAL_PWR_DisableWakeUpPin
|
||
141 .syntax unified
|
||
142 .thumb
|
||
143 .thumb_func
|
||
145 HAL_PWR_DisableWakeUpPin:
|
||
146 .LVL1:
|
||
147 .LFB134:
|
||
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality.
|
||
253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
|
||
254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be values of :
|
||
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
|
||
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
148 .loc 1 259 1 is_stmt 1 view -0
|
||
149 .cfi_startproc
|
||
ARM GAS /tmp/ccVidTYQ.s page 8
|
||
|
||
|
||
150 @ args = 0, pretend = 0, frame = 0
|
||
151 @ frame_needed = 0, uses_anonymous_args = 0
|
||
152 @ link register save eliminated.
|
||
260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
|
||
261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
153 .loc 1 261 3 view .LVU15
|
||
262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Disable the EWUPx pin */
|
||
263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||
154 .loc 1 263 3 view .LVU16
|
||
155 0000 024A ldr r2, .L14
|
||
156 0002 5368 ldr r3, [r2, #4]
|
||
157 0004 23EA0003 bic r3, r3, r0
|
||
158 0008 5360 str r3, [r2, #4]
|
||
264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
159 .loc 1 264 1 is_stmt 0 view .LVU17
|
||
160 000a 7047 bx lr
|
||
161 .L15:
|
||
162 .align 2
|
||
163 .L14:
|
||
164 000c 00700040 .word 1073770496
|
||
165 .cfi_endproc
|
||
166 .LFE134:
|
||
168 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
|
||
169 .align 1
|
||
170 .global HAL_PWR_EnterSLEEPMode
|
||
171 .syntax unified
|
||
172 .thumb
|
||
173 .thumb_func
|
||
175 HAL_PWR_EnterSLEEPMode:
|
||
176 .LVL2:
|
||
177 .LFB135:
|
||
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters Sleep mode.
|
||
268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||
269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode.
|
||
270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||
272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||
273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note This parameter has no effect in F3 family and is just maintained to
|
||
274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * offer full portability of other STM32 families softwares.
|
||
275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||
276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||
277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the interrupt wake up source.
|
||
278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
178 .loc 1 284 1 is_stmt 1 view -0
|
||
179 .cfi_startproc
|
||
180 @ args = 0, pretend = 0, frame = 0
|
||
181 @ frame_needed = 0, uses_anonymous_args = 0
|
||
182 @ link register save eliminated.
|
||
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
|
||
ARM GAS /tmp/ccVidTYQ.s page 9
|
||
|
||
|
||
286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||
183 .loc 1 286 3 view .LVU19
|
||
287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||
184 .loc 1 289 3 view .LVU20
|
||
185 .loc 1 289 6 is_stmt 0 view .LVU21
|
||
186 0000 064A ldr r2, .L20
|
||
187 0002 1369 ldr r3, [r2, #16]
|
||
188 .loc 1 289 12 view .LVU22
|
||
189 0004 23F00403 bic r3, r3, #4
|
||
190 0008 1361 str r3, [r2, #16]
|
||
290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
|
||
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||
191 .loc 1 292 3 is_stmt 1 view .LVU23
|
||
192 .loc 1 292 5 is_stmt 0 view .LVU24
|
||
193 000a 0129 cmp r1, #1
|
||
194 000c 03D0 beq .L19
|
||
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
|
||
296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
|
||
298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
|
||
300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
|
||
195 .loc 1 300 5 is_stmt 1 view .LVU25
|
||
196 .syntax unified
|
||
197 @ 300 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
198 000e 40BF sev
|
||
199 @ 0 "" 2
|
||
301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
200 .loc 1 301 5 view .LVU26
|
||
201 @ 301 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
202 0010 20BF wfe
|
||
203 @ 0 "" 2
|
||
302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
204 .loc 1 302 5 view .LVU27
|
||
205 @ 302 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
206 0012 20BF wfe
|
||
207 @ 0 "" 2
|
||
303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
208 .loc 1 304 1 is_stmt 0 view .LVU28
|
||
209 .thumb
|
||
210 .syntax unified
|
||
211 0014 7047 bx lr
|
||
212 .L19:
|
||
295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
213 .loc 1 295 5 is_stmt 1 view .LVU29
|
||
214 .syntax unified
|
||
215 @ 295 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
216 0016 30BF wfi
|
||
217 @ 0 "" 2
|
||
218 .thumb
|
||
219 .syntax unified
|
||
ARM GAS /tmp/ccVidTYQ.s page 10
|
||
|
||
|
||
220 0018 7047 bx lr
|
||
221 .L21:
|
||
222 001a 00BF .align 2
|
||
223 .L20:
|
||
224 001c 00ED00E0 .word -536810240
|
||
225 .cfi_endproc
|
||
226 .LFE135:
|
||
228 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
|
||
229 .align 1
|
||
230 .global HAL_PWR_EnterSTOPMode
|
||
231 .syntax unified
|
||
232 .thumb
|
||
233 .thumb_func
|
||
235 HAL_PWR_EnterSTOPMode:
|
||
236 .LVL3:
|
||
237 .LFB136:
|
||
305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STOP mode.
|
||
308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock.
|
||
311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional
|
||
312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode.
|
||
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption
|
||
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * is higher although the startup time is reduced.
|
||
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in STOP mode.
|
||
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
|
||
318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
|
||
319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
|
||
320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
|
||
321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
|
||
322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
|
||
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||
326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
238 .loc 1 326 1 view -0
|
||
239 .cfi_startproc
|
||
240 @ args = 0, pretend = 0, frame = 0
|
||
241 @ frame_needed = 0, uses_anonymous_args = 0
|
||
242 @ link register save eliminated.
|
||
327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** uint32_t tmpreg = 0U;
|
||
243 .loc 1 327 3 view .LVU31
|
||
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
|
||
330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
|
||
244 .loc 1 330 3 view .LVU32
|
||
331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||
245 .loc 1 331 3 view .LVU33
|
||
332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select the regulator state in STOP mode ---------------------------------*/
|
||
334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg = PWR->CR;
|
||
246 .loc 1 334 3 view .LVU34
|
||
247 .loc 1 334 10 is_stmt 0 view .LVU35
|
||
248 0000 0B4A ldr r2, .L26
|
||
ARM GAS /tmp/ccVidTYQ.s page 11
|
||
|
||
|
||
249 0002 1368 ldr r3, [r2]
|
||
250 .LVL4:
|
||
335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */
|
||
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
|
||
251 .loc 1 337 3 is_stmt 1 view .LVU36
|
||
252 .loc 1 337 10 is_stmt 0 view .LVU37
|
||
253 0004 23F00303 bic r3, r3, #3
|
||
254 .LVL5:
|
||
338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set LPDS bit according to Regulator value */
|
||
340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg |= Regulator;
|
||
255 .loc 1 340 3 is_stmt 1 view .LVU38
|
||
256 .loc 1 340 10 is_stmt 0 view .LVU39
|
||
257 0008 0343 orrs r3, r3, r0
|
||
258 .LVL6:
|
||
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Store the new value */
|
||
343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR = tmpreg;
|
||
259 .loc 1 343 3 is_stmt 1 view .LVU40
|
||
260 .loc 1 343 11 is_stmt 0 view .LVU41
|
||
261 000a 1360 str r3, [r2]
|
||
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||
262 .loc 1 346 3 is_stmt 1 view .LVU42
|
||
263 .loc 1 346 6 is_stmt 0 view .LVU43
|
||
264 000c 094A ldr r2, .L26+4
|
||
265 000e 1369 ldr r3, [r2, #16]
|
||
266 .LVL7:
|
||
267 .loc 1 346 12 view .LVU44
|
||
268 0010 43F00403 orr r3, r3, #4
|
||
269 0014 1361 str r3, [r2, #16]
|
||
270 .LVL8:
|
||
347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STOP mode entry --------------------------------------------------*/
|
||
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI)
|
||
271 .loc 1 349 3 is_stmt 1 view .LVU45
|
||
272 .loc 1 349 5 is_stmt 0 view .LVU46
|
||
273 0016 0129 cmp r1, #1
|
||
274 0018 08D0 beq .L25
|
||
350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
|
||
353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
|
||
355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
|
||
357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
|
||
275 .loc 1 357 5 is_stmt 1 view .LVU47
|
||
276 .syntax unified
|
||
277 @ 357 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
278 001a 40BF sev
|
||
279 @ 0 "" 2
|
||
358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
280 .loc 1 358 5 view .LVU48
|
||
281 @ 358 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
ARM GAS /tmp/ccVidTYQ.s page 12
|
||
|
||
|
||
282 001c 20BF wfe
|
||
283 @ 0 "" 2
|
||
359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
|
||
284 .loc 1 359 5 view .LVU49
|
||
285 @ 359 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
286 001e 20BF wfe
|
||
287 @ 0 "" 2
|
||
288 .thumb
|
||
289 .syntax unified
|
||
290 .L24:
|
||
360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||
363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||
291 .loc 1 363 3 view .LVU50
|
||
292 .loc 1 363 6 is_stmt 0 view .LVU51
|
||
293 0020 044A ldr r2, .L26+4
|
||
294 0022 1369 ldr r3, [r2, #16]
|
||
295 .loc 1 363 12 view .LVU52
|
||
296 0024 23F00403 bic r3, r3, #4
|
||
297 0028 1361 str r3, [r2, #16]
|
||
364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
298 .loc 1 364 1 view .LVU53
|
||
299 002a 7047 bx lr
|
||
300 .L25:
|
||
352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
301 .loc 1 352 5 is_stmt 1 view .LVU54
|
||
302 .syntax unified
|
||
303 @ 352 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
304 002c 30BF wfi
|
||
305 @ 0 "" 2
|
||
306 .thumb
|
||
307 .syntax unified
|
||
308 002e F7E7 b .L24
|
||
309 .L27:
|
||
310 .align 2
|
||
311 .L26:
|
||
312 0030 00700040 .word 1073770496
|
||
313 0034 00ED00E0 .word -536810240
|
||
314 .cfi_endproc
|
||
315 .LFE136:
|
||
317 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
|
||
318 .align 1
|
||
319 .global HAL_PWR_EnterSTANDBYMode
|
||
320 .syntax unified
|
||
321 .thumb
|
||
322 .thumb_func
|
||
324 HAL_PWR_EnterSTANDBYMode:
|
||
325 .LFB137:
|
||
365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STANDBY mode.
|
||
368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for:
|
||
369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - Reset pad (still available),
|
||
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - RTC alternate function pins if configured for tamper, time-stamp, RTC
|
||
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out,
|
||
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - WKUP pins if enabled.
|
||
ARM GAS /tmp/ccVidTYQ.s page 13
|
||
|
||
|
||
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
|
||
376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
326 .loc 1 376 1 view -0
|
||
327 .cfi_startproc
|
||
328 @ args = 0, pretend = 0, frame = 0
|
||
329 @ frame_needed = 0, uses_anonymous_args = 0
|
||
330 @ link register save eliminated.
|
||
377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STANDBY mode */
|
||
378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR |= PWR_CR_PDDS;
|
||
331 .loc 1 378 3 view .LVU56
|
||
332 .loc 1 378 6 is_stmt 0 view .LVU57
|
||
333 0000 054A ldr r2, .L29
|
||
334 0002 1368 ldr r3, [r2]
|
||
335 .loc 1 378 11 view .LVU58
|
||
336 0004 43F00203 orr r3, r3, #2
|
||
337 0008 1360 str r3, [r2]
|
||
379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||
338 .loc 1 381 3 is_stmt 1 view .LVU59
|
||
339 .loc 1 381 6 is_stmt 0 view .LVU60
|
||
340 000a 044A ldr r2, .L29+4
|
||
341 000c 1369 ldr r3, [r2, #16]
|
||
342 .loc 1 381 12 view .LVU61
|
||
343 000e 43F00403 orr r3, r3, #4
|
||
344 0012 1361 str r3, [r2, #16]
|
||
382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
|
||
384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #if defined ( __CC_ARM)
|
||
385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __force_stores();
|
||
386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #endif
|
||
387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
|
||
388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
|
||
345 .loc 1 388 3 is_stmt 1 view .LVU62
|
||
346 .syntax unified
|
||
347 @ 388 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
|
||
348 0014 30BF wfi
|
||
349 @ 0 "" 2
|
||
389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
350 .loc 1 389 1 is_stmt 0 view .LVU63
|
||
351 .thumb
|
||
352 .syntax unified
|
||
353 0016 7047 bx lr
|
||
354 .L30:
|
||
355 .align 2
|
||
356 .L29:
|
||
357 0018 00700040 .word 1073770496
|
||
358 001c 00ED00E0 .word -536810240
|
||
359 .cfi_endproc
|
||
360 .LFE137:
|
||
362 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
|
||
363 .align 1
|
||
364 .global HAL_PWR_EnableSleepOnExit
|
||
365 .syntax unified
|
||
366 .thumb
|
||
ARM GAS /tmp/ccVidTYQ.s page 14
|
||
|
||
|
||
367 .thumb_func
|
||
369 HAL_PWR_EnableSleepOnExit:
|
||
370 .LFB138:
|
||
390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||
393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
|
||
395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
|
||
396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * interruptions handling.
|
||
397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
|
||
400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
371 .loc 1 400 1 is_stmt 1 view -0
|
||
372 .cfi_startproc
|
||
373 @ args = 0, pretend = 0, frame = 0
|
||
374 @ frame_needed = 0, uses_anonymous_args = 0
|
||
375 @ link register save eliminated.
|
||
401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||
402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
376 .loc 1 402 3 view .LVU65
|
||
377 0000 024A ldr r2, .L32
|
||
378 0002 1369 ldr r3, [r2, #16]
|
||
379 0004 43F00203 orr r3, r3, #2
|
||
380 0008 1361 str r3, [r2, #16]
|
||
403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
381 .loc 1 403 1 is_stmt 0 view .LVU66
|
||
382 000a 7047 bx lr
|
||
383 .L33:
|
||
384 .align 2
|
||
385 .L32:
|
||
386 000c 00ED00E0 .word -536810240
|
||
387 .cfi_endproc
|
||
388 .LFE138:
|
||
390 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
|
||
391 .align 1
|
||
392 .global HAL_PWR_DisableSleepOnExit
|
||
393 .syntax unified
|
||
394 .thumb
|
||
395 .thumb_func
|
||
397 HAL_PWR_DisableSleepOnExit:
|
||
398 .LFB139:
|
||
404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||
408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
|
||
410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
|
||
413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
399 .loc 1 413 1 is_stmt 1 view -0
|
||
400 .cfi_startproc
|
||
401 @ args = 0, pretend = 0, frame = 0
|
||
402 @ frame_needed = 0, uses_anonymous_args = 0
|
||
ARM GAS /tmp/ccVidTYQ.s page 15
|
||
|
||
|
||
403 @ link register save eliminated.
|
||
414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||
415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
404 .loc 1 415 3 view .LVU68
|
||
405 0000 024A ldr r2, .L35
|
||
406 0002 1369 ldr r3, [r2, #16]
|
||
407 0004 23F00203 bic r3, r3, #2
|
||
408 0008 1361 str r3, [r2, #16]
|
||
416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
409 .loc 1 416 1 is_stmt 0 view .LVU69
|
||
410 000a 7047 bx lr
|
||
411 .L36:
|
||
412 .align 2
|
||
413 .L35:
|
||
414 000c 00ED00E0 .word -536810240
|
||
415 .cfi_endproc
|
||
416 .LFE139:
|
||
418 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
|
||
419 .align 1
|
||
420 .global HAL_PWR_EnableSEVOnPend
|
||
421 .syntax unified
|
||
422 .thumb
|
||
423 .thumb_func
|
||
425 HAL_PWR_EnableSEVOnPend:
|
||
426 .LFB140:
|
||
417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit.
|
||
422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
|
||
424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
|
||
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
427 .loc 1 427 1 is_stmt 1 view -0
|
||
428 .cfi_startproc
|
||
429 @ args = 0, pretend = 0, frame = 0
|
||
430 @ frame_needed = 0, uses_anonymous_args = 0
|
||
431 @ link register save eliminated.
|
||
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
|
||
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
432 .loc 1 429 3 view .LVU71
|
||
433 0000 024A ldr r2, .L38
|
||
434 0002 1369 ldr r3, [r2, #16]
|
||
435 0004 43F01003 orr r3, r3, #16
|
||
436 0008 1361 str r3, [r2, #16]
|
||
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
437 .loc 1 430 1 is_stmt 0 view .LVU72
|
||
438 000a 7047 bx lr
|
||
439 .L39:
|
||
440 .align 2
|
||
441 .L38:
|
||
442 000c 00ED00E0 .word -536810240
|
||
443 .cfi_endproc
|
||
444 .LFE140:
|
||
ARM GAS /tmp/ccVidTYQ.s page 16
|
||
|
||
|
||
446 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
|
||
447 .align 1
|
||
448 .global HAL_PWR_DisableSEVOnPend
|
||
449 .syntax unified
|
||
450 .thumb
|
||
451 .thumb_func
|
||
453 HAL_PWR_DisableSEVOnPend:
|
||
454 .LFB141:
|
||
431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
|
||
433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
|
||
434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit.
|
||
435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
|
||
437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
|
||
438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
|
||
439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
|
||
440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
|
||
455 .loc 1 440 1 is_stmt 1 view -0
|
||
456 .cfi_startproc
|
||
457 @ args = 0, pretend = 0, frame = 0
|
||
458 @ frame_needed = 0, uses_anonymous_args = 0
|
||
459 @ link register save eliminated.
|
||
441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
|
||
442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
460 .loc 1 442 3 view .LVU74
|
||
461 0000 024A ldr r2, .L41
|
||
462 0002 1369 ldr r3, [r2, #16]
|
||
463 0004 23F01003 bic r3, r3, #16
|
||
464 0008 1361 str r3, [r2, #16]
|
||
443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
|
||
465 .loc 1 443 1 is_stmt 0 view .LVU75
|
||
466 000a 7047 bx lr
|
||
467 .L42:
|
||
468 .align 2
|
||
469 .L41:
|
||
470 000c 00ED00E0 .word -536810240
|
||
471 .cfi_endproc
|
||
472 .LFE141:
|
||
474 .text
|
||
475 .Letext0:
|
||
476 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non
|
||
477 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non
|
||
478 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
|
||
479 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
|
||
ARM GAS /tmp/ccVidTYQ.s page 17
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:0000000000000000 stm32f3xx_hal_pwr.c
|
||
/tmp/ccVidTYQ.s:21 .text.HAL_PWR_DeInit:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:27 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit
|
||
/tmp/ccVidTYQ.s:48 .text.HAL_PWR_DeInit:0000000000000014 $d
|
||
/tmp/ccVidTYQ.s:53 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:59 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess
|
||
/tmp/ccVidTYQ.s:76 .text.HAL_PWR_EnableBkUpAccess:000000000000000c $d
|
||
/tmp/ccVidTYQ.s:81 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:87 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess
|
||
/tmp/ccVidTYQ.s:104 .text.HAL_PWR_DisableBkUpAccess:000000000000000c $d
|
||
/tmp/ccVidTYQ.s:109 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:115 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin
|
||
/tmp/ccVidTYQ.s:134 .text.HAL_PWR_EnableWakeUpPin:000000000000000c $d
|
||
/tmp/ccVidTYQ.s:139 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:145 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin
|
||
/tmp/ccVidTYQ.s:164 .text.HAL_PWR_DisableWakeUpPin:000000000000000c $d
|
||
/tmp/ccVidTYQ.s:169 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:175 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode
|
||
/tmp/ccVidTYQ.s:224 .text.HAL_PWR_EnterSLEEPMode:000000000000001c $d
|
||
/tmp/ccVidTYQ.s:229 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:235 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode
|
||
/tmp/ccVidTYQ.s:312 .text.HAL_PWR_EnterSTOPMode:0000000000000030 $d
|
||
/tmp/ccVidTYQ.s:318 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:324 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode
|
||
/tmp/ccVidTYQ.s:357 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d
|
||
/tmp/ccVidTYQ.s:363 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:369 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit
|
||
/tmp/ccVidTYQ.s:386 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d
|
||
/tmp/ccVidTYQ.s:391 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:397 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit
|
||
/tmp/ccVidTYQ.s:414 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d
|
||
/tmp/ccVidTYQ.s:419 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:425 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend
|
||
/tmp/ccVidTYQ.s:442 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d
|
||
/tmp/ccVidTYQ.s:447 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t
|
||
/tmp/ccVidTYQ.s:453 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend
|
||
/tmp/ccVidTYQ.s:470 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d
|
||
|
||
NO UNDEFINED SYMBOLS
|