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866d0642fb
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temporarily implement light gate input latching
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2025-07-08 17:59:53 +02:00 |
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22e24b38b5
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fix debug CAN mapping
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2025-06-23 17:23:41 +02:00 |
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63e3333260
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add debug CAN mapping
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2025-06-20 00:24:12 +02:00 |
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dc8e0c806a
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fix digital inputs pin mapping
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2025-06-20 00:14:40 +02:00 |
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2afdfa8293
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add more error led states and ignore CAN send FIFO full error
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2025-06-20 00:10:21 +02:00 |
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6051e4b993
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Update mappings to newest agreements
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2025-05-25 14:55:18 +02:00 |
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3a8b90acc8
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Ready for install: Switch to CAN1 and add unused PWM IDs for front
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2025-05-15 13:23:56 +02:00 |
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7c50101f9e
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Resolve #4 by running main loop inside timer IRQ and setting it to 1kHz
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2025-05-12 17:46:28 +02:00 |
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3e4cc09120
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Input capture works. off by *2
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2025-05-09 11:44:55 +02:00 |
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778e0ae272
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CAN bus bringup (everything works except PWM output)
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2025-04-24 20:38:24 +02:00 |
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804bb33064
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Add PWM control functionality
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2025-04-20 17:30:52 +02:00 |
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1a517299a0
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Add CAN send logic and DIO mapping
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2025-03-30 11:14:16 +02:00 |
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eb994ad693
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New pin mappings for wiring optimization
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2025-03-29 15:45:20 +01:00 |
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8e62180537
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Remove old signal mapping
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2025-03-29 12:57:28 +01:00 |
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8f6b924865
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Complete new CAN mappings
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2025-03-29 12:56:06 +01:00 |
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298fd8709c
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A few ideas for can mappings
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2025-03-27 20:24:25 +01:00 |
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84b4a487fc
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mappings scaffold
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2025-03-24 20:35:14 +01:00 |
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852ce2fbae
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adc callback reached, llm linker script changes
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2025-03-24 17:19:55 +01:00 |
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f7b04fb8ed
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Still no ADC (Timer 6 worked in Interrupt mode)
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2025-03-18 17:32:57 +01:00 |
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cd50212b39
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Software Scaffold
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2025-03-12 16:29:44 +01:00 |
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