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pdu/Software/Code/Debug/PDU_FT25.list

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PDU_FT25.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00005ce4 08000188 08000188 00001188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000038 08005e6c 08005e6c 00006e6c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08005ea4 08005ea4 0000700c 2**0
CONTENTS
4 .ARM 00000000 08005ea4 08005ea4 0000700c 2**0
CONTENTS
5 .preinit_array 00000000 08005ea4 08005ea4 0000700c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08005ea4 08005ea4 00006ea4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08005ea8 08005ea8 00006ea8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08005eac 00007000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000002ac 2000000c 08005eb8 0000700c 2**2
ALLOC
10 ._user_heap_stack 00000600 200002b8 08005eb8 000072b8 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000700c 2**0
CONTENTS, READONLY
12 .debug_info 00014381 00000000 00000000 0000703c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00002c52 00000000 00000000 0001b3bd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000010e0 00000000 00000000 0001e010 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000d2d 00000000 00000000 0001f0f0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001e4dd 00000000 00000000 0001fe1d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00015c26 00000000 00000000 0003e2fa 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000b7783 00000000 00000000 00053f20 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 0010b6a3 2**0
CONTENTS, READONLY
20 .debug_frame 0000472c 00000000 00000000 0010b6e8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000071 00000000 00000000 0010fe14 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000000c .word 0x2000000c
80001a4: 00000000 .word 0x00000000
80001a8: 08005e54 .word 0x08005e54
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000010 .word 0x20000010
80001c4: 08005e54 .word 0x08005e54
080001c8 <can_init>:
extern uint32_t lastheartbeat;
extern int inhibit_SDC;
void can_init(CAN_HandleTypeDef* hcan){
80001c8: b580 push {r7, lr}
80001ca: b082 sub sp, #8
80001cc: af00 add r7, sp, #0
80001ce: 6078 str r0, [r7, #4]
ftcan_init(hcan);
80001d0: 6878 ldr r0, [r7, #4]
80001d2: f000 f85f bl 8000294 <ftcan_init>
ftcan_add_filter(0x00, 0x00); // no filter
80001d6: 2100 movs r1, #0
80001d8: 2000 movs r0, #0
80001da: f000 f89f bl 800031c <ftcan_add_filter>
}
80001de: bf00 nop
80001e0: 3708 adds r7, #8
80001e2: 46bd mov sp, r7
80001e4: bd80 pop {r7, pc}
...
080001e8 <can_sendloop>:
void can_sendloop(){
80001e8: b580 push {r7, lr}
80001ea: b082 sub sp, #8
80001ec: af00 add r7, sp, #0
//static uint8_t additionaltxcounter = 0;
uint8_t status_data[3];
status_data[0] = update_ports.porta.porta;
80001ee: 4b0c ldr r3, [pc, #48] @ (8000220 <can_sendloop+0x38>)
80001f0: 781b ldrb r3, [r3, #0]
80001f2: 713b strb r3, [r7, #4]
status_data[1] = update_ports.portb.portb;
80001f4: 4b0a ldr r3, [pc, #40] @ (8000220 <can_sendloop+0x38>)
80001f6: 785b ldrb r3, [r3, #1]
80001f8: 717b strb r3, [r7, #5]
status_data[2] = !inhibit_SDC;
80001fa: 4b0a ldr r3, [pc, #40] @ (8000224 <can_sendloop+0x3c>)
80001fc: 681b ldr r3, [r3, #0]
80001fe: 2b00 cmp r3, #0
8000200: bf0c ite eq
8000202: 2301 moveq r3, #1
8000204: 2300 movne r3, #0
8000206: b2db uxtb r3, r3
8000208: 71bb strb r3, [r7, #6]
ftcan_transmit(TX_STATUS_MSG_ID, status_data, 3);
800020a: 1d3b adds r3, r7, #4
800020c: 2203 movs r2, #3
800020e: 4619 mov r1, r3
8000210: 20c9 movs r0, #201 @ 0xc9
8000212: f000 f85f bl 80002d4 <ftcan_transmit>
// TODO: implement transmission of current and voltage measurements
}
8000216: bf00 nop
8000218: 3708 adds r7, #8
800021a: 46bd mov sp, r7
800021c: bd80 pop {r7, pc}
800021e: bf00 nop
8000220: 200002a0 .word 0x200002a0
8000224: 200002a8 .word 0x200002a8
08000228 <ftcan_msg_received_cb>:
void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){
8000228: b580 push {r7, lr}
800022a: b084 sub sp, #16
800022c: af00 add r7, sp, #0
800022e: 4603 mov r3, r0
8000230: 60b9 str r1, [r7, #8]
8000232: 607a str r2, [r7, #4]
8000234: 81fb strh r3, [r7, #14]
canmsg_received = 1;
8000236: 4b13 ldr r3, [pc, #76] @ (8000284 <ftcan_msg_received_cb+0x5c>)
8000238: 2201 movs r2, #1
800023a: 701a strb r2, [r3, #0]
if((id == RX_STATUS_MSG_ID) && (datalen == 3)){
800023c: 89fb ldrh r3, [r7, #14]
800023e: 2bc8 cmp r3, #200 @ 0xc8
8000240: d110 bne.n 8000264 <ftcan_msg_received_cb+0x3c>
8000242: 68bb ldr r3, [r7, #8]
8000244: 2b03 cmp r3, #3
8000246: d10d bne.n 8000264 <ftcan_msg_received_cb+0x3c>
rxstate.iostatus.porta.porta = data[0];
8000248: 687b ldr r3, [r7, #4]
800024a: 781a ldrb r2, [r3, #0]
800024c: 4b0e ldr r3, [pc, #56] @ (8000288 <ftcan_msg_received_cb+0x60>)
800024e: 701a strb r2, [r3, #0]
rxstate.iostatus.portb.portb = data[1];
8000250: 687b ldr r3, [r7, #4]
8000252: 3301 adds r3, #1
8000254: 781a ldrb r2, [r3, #0]
8000256: 4b0c ldr r3, [pc, #48] @ (8000288 <ftcan_msg_received_cb+0x60>)
8000258: 705a strb r2, [r3, #1]
rxstate.checksum = data[2];
800025a: 687b ldr r3, [r7, #4]
800025c: 3302 adds r3, #2
800025e: 781a ldrb r2, [r3, #0]
8000260: 4b09 ldr r3, [pc, #36] @ (8000288 <ftcan_msg_received_cb+0x60>)
8000262: 709a strb r2, [r3, #2]
}
if (id == RX_STATUS_HEARTBEAT){
8000264: 89fb ldrh r3, [r7, #14]
8000266: 2bc7 cmp r3, #199 @ 0xc7
8000268: d107 bne.n 800027a <ftcan_msg_received_cb+0x52>
lastheartbeat = HAL_GetTick();
800026a: f001 f8c5 bl 80013f8 <HAL_GetTick>
800026e: 4603 mov r3, r0
8000270: 4a06 ldr r2, [pc, #24] @ (800028c <ftcan_msg_received_cb+0x64>)
8000272: 6013 str r3, [r2, #0]
inhibit_SDC = 0;
8000274: 4b06 ldr r3, [pc, #24] @ (8000290 <ftcan_msg_received_cb+0x68>)
8000276: 2200 movs r2, #0
8000278: 601a str r2, [r3, #0]
}
}
800027a: bf00 nop
800027c: 3710 adds r7, #16
800027e: 46bd mov sp, r7
8000280: bd80 pop {r7, pc}
8000282: bf00 nop
8000284: 2000002c .word 0x2000002c
8000288: 20000028 .word 0x20000028
800028c: 200002a4 .word 0x200002a4
8000290: 200002a8 .word 0x200002a8
08000294 <ftcan_init>:
#include <string.h>
#if defined(FTCAN_IS_BXCAN)
static CAN_HandleTypeDef *hcan;
HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) {
8000294: b580 push {r7, lr}
8000296: b084 sub sp, #16
8000298: af00 add r7, sp, #0
800029a: 6078 str r0, [r7, #4]
hcan = handle;
800029c: 4a0c ldr r2, [pc, #48] @ (80002d0 <ftcan_init+0x3c>)
800029e: 687b ldr r3, [r7, #4]
80002a0: 6013 str r3, [r2, #0]
HAL_StatusTypeDef status =
HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING);
80002a2: 4b0b ldr r3, [pc, #44] @ (80002d0 <ftcan_init+0x3c>)
80002a4: 681b ldr r3, [r3, #0]
80002a6: 2102 movs r1, #2
80002a8: 4618 mov r0, r3
80002aa: f002 fc8c bl 8002bc6 <HAL_CAN_ActivateNotification>
80002ae: 4603 mov r3, r0
80002b0: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
80002b2: 7bfb ldrb r3, [r7, #15]
80002b4: 2b00 cmp r3, #0
80002b6: d001 beq.n 80002bc <ftcan_init+0x28>
return status;
80002b8: 7bfb ldrb r3, [r7, #15]
80002ba: e005 b.n 80002c8 <ftcan_init+0x34>
}
return HAL_CAN_Start(hcan);
80002bc: 4b04 ldr r3, [pc, #16] @ (80002d0 <ftcan_init+0x3c>)
80002be: 681b ldr r3, [r3, #0]
80002c0: 4618 mov r0, r3
80002c2: f002 fa4a bl 800275a <HAL_CAN_Start>
80002c6: 4603 mov r3, r0
}
80002c8: 4618 mov r0, r3
80002ca: 3710 adds r7, #16
80002cc: 46bd mov sp, r7
80002ce: bd80 pop {r7, pc}
80002d0: 20000030 .word 0x20000030
080002d4 <ftcan_transmit>:
HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data,
size_t datalen) {
80002d4: b580 push {r7, lr}
80002d6: b086 sub sp, #24
80002d8: af00 add r7, sp, #0
80002da: 4603 mov r3, r0
80002dc: 60b9 str r1, [r7, #8]
80002de: 607a str r2, [r7, #4]
80002e0: 81fb strh r3, [r7, #14]
static CAN_TxHeaderTypeDef header;
header.StdId = id;
80002e2: 89fb ldrh r3, [r7, #14]
80002e4: 4a0b ldr r2, [pc, #44] @ (8000314 <ftcan_transmit+0x40>)
80002e6: 6013 str r3, [r2, #0]
header.IDE = CAN_ID_STD;
80002e8: 4b0a ldr r3, [pc, #40] @ (8000314 <ftcan_transmit+0x40>)
80002ea: 2200 movs r2, #0
80002ec: 609a str r2, [r3, #8]
header.RTR = CAN_RTR_DATA;
80002ee: 4b09 ldr r3, [pc, #36] @ (8000314 <ftcan_transmit+0x40>)
80002f0: 2200 movs r2, #0
80002f2: 60da str r2, [r3, #12]
header.DLC = datalen;
80002f4: 4a07 ldr r2, [pc, #28] @ (8000314 <ftcan_transmit+0x40>)
80002f6: 687b ldr r3, [r7, #4]
80002f8: 6113 str r3, [r2, #16]
uint32_t mailbox;
return HAL_CAN_AddTxMessage(hcan, &header, data, &mailbox);
80002fa: 4b07 ldr r3, [pc, #28] @ (8000318 <ftcan_transmit+0x44>)
80002fc: 6818 ldr r0, [r3, #0]
80002fe: f107 0314 add.w r3, r7, #20
8000302: 68ba ldr r2, [r7, #8]
8000304: 4903 ldr r1, [pc, #12] @ (8000314 <ftcan_transmit+0x40>)
8000306: f002 fa6c bl 80027e2 <HAL_CAN_AddTxMessage>
800030a: 4603 mov r3, r0
}
800030c: 4618 mov r0, r3
800030e: 3718 adds r7, #24
8000310: 46bd mov sp, r7
8000312: bd80 pop {r7, pc}
8000314: 20000034 .word 0x20000034
8000318: 20000030 .word 0x20000030
0800031c <ftcan_add_filter>:
HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) {
800031c: b580 push {r7, lr}
800031e: b084 sub sp, #16
8000320: af00 add r7, sp, #0
8000322: 4603 mov r3, r0
8000324: 460a mov r2, r1
8000326: 80fb strh r3, [r7, #6]
8000328: 4613 mov r3, r2
800032a: 80bb strh r3, [r7, #4]
static uint32_t next_filter_no = 0;
static CAN_FilterTypeDef filter;
if (next_filter_no % 2 == 0) {
800032c: 4b26 ldr r3, [pc, #152] @ (80003c8 <ftcan_add_filter+0xac>)
800032e: 681b ldr r3, [r3, #0]
8000330: f003 0301 and.w r3, r3, #1
8000334: 2b00 cmp r3, #0
8000336: d110 bne.n 800035a <ftcan_add_filter+0x3e>
filter.FilterIdHigh = id << 5;
8000338: 88fb ldrh r3, [r7, #6]
800033a: 015b lsls r3, r3, #5
800033c: 4a23 ldr r2, [pc, #140] @ (80003cc <ftcan_add_filter+0xb0>)
800033e: 6013 str r3, [r2, #0]
filter.FilterMaskIdHigh = mask << 5;
8000340: 88bb ldrh r3, [r7, #4]
8000342: 015b lsls r3, r3, #5
8000344: 4a21 ldr r2, [pc, #132] @ (80003cc <ftcan_add_filter+0xb0>)
8000346: 6093 str r3, [r2, #8]
filter.FilterIdLow = id << 5;
8000348: 88fb ldrh r3, [r7, #6]
800034a: 015b lsls r3, r3, #5
800034c: 4a1f ldr r2, [pc, #124] @ (80003cc <ftcan_add_filter+0xb0>)
800034e: 6053 str r3, [r2, #4]
filter.FilterMaskIdLow = mask << 5;
8000350: 88bb ldrh r3, [r7, #4]
8000352: 015b lsls r3, r3, #5
8000354: 4a1d ldr r2, [pc, #116] @ (80003cc <ftcan_add_filter+0xb0>)
8000356: 60d3 str r3, [r2, #12]
8000358: e007 b.n 800036a <ftcan_add_filter+0x4e>
} else {
// Leave high filter untouched from the last configuration
filter.FilterIdLow = id << 5;
800035a: 88fb ldrh r3, [r7, #6]
800035c: 015b lsls r3, r3, #5
800035e: 4a1b ldr r2, [pc, #108] @ (80003cc <ftcan_add_filter+0xb0>)
8000360: 6053 str r3, [r2, #4]
filter.FilterMaskIdLow = mask << 5;
8000362: 88bb ldrh r3, [r7, #4]
8000364: 015b lsls r3, r3, #5
8000366: 4a19 ldr r2, [pc, #100] @ (80003cc <ftcan_add_filter+0xb0>)
8000368: 60d3 str r3, [r2, #12]
}
filter.FilterFIFOAssignment = CAN_FILTER_FIFO0;
800036a: 4b18 ldr r3, [pc, #96] @ (80003cc <ftcan_add_filter+0xb0>)
800036c: 2200 movs r2, #0
800036e: 611a str r2, [r3, #16]
filter.FilterBank = next_filter_no / 2;
8000370: 4b15 ldr r3, [pc, #84] @ (80003c8 <ftcan_add_filter+0xac>)
8000372: 681b ldr r3, [r3, #0]
8000374: 085b lsrs r3, r3, #1
8000376: 4a15 ldr r2, [pc, #84] @ (80003cc <ftcan_add_filter+0xb0>)
8000378: 6153 str r3, [r2, #20]
if (filter.FilterBank > FTCAN_NUM_FILTERS + 1) {
800037a: 4b14 ldr r3, [pc, #80] @ (80003cc <ftcan_add_filter+0xb0>)
800037c: 695b ldr r3, [r3, #20]
800037e: 2b0e cmp r3, #14
8000380: d901 bls.n 8000386 <ftcan_add_filter+0x6a>
return HAL_ERROR;
8000382: 2301 movs r3, #1
8000384: e01c b.n 80003c0 <ftcan_add_filter+0xa4>
}
filter.FilterMode = CAN_FILTERMODE_IDMASK;
8000386: 4b11 ldr r3, [pc, #68] @ (80003cc <ftcan_add_filter+0xb0>)
8000388: 2200 movs r2, #0
800038a: 619a str r2, [r3, #24]
filter.FilterScale = CAN_FILTERSCALE_16BIT;
800038c: 4b0f ldr r3, [pc, #60] @ (80003cc <ftcan_add_filter+0xb0>)
800038e: 2200 movs r2, #0
8000390: 61da str r2, [r3, #28]
filter.FilterActivation = CAN_FILTER_ENABLE;
8000392: 4b0e ldr r3, [pc, #56] @ (80003cc <ftcan_add_filter+0xb0>)
8000394: 2201 movs r2, #1
8000396: 621a str r2, [r3, #32]
// Disable slave filters
// TODO: Some STM32 have multiple CAN peripherals, and one uses the slave
// filter bank
filter.SlaveStartFilterBank = FTCAN_NUM_FILTERS;
8000398: 4b0c ldr r3, [pc, #48] @ (80003cc <ftcan_add_filter+0xb0>)
800039a: 220d movs r2, #13
800039c: 625a str r2, [r3, #36] @ 0x24
HAL_StatusTypeDef status = HAL_CAN_ConfigFilter(hcan, &filter);
800039e: 4b0c ldr r3, [pc, #48] @ (80003d0 <ftcan_add_filter+0xb4>)
80003a0: 681b ldr r3, [r3, #0]
80003a2: 490a ldr r1, [pc, #40] @ (80003cc <ftcan_add_filter+0xb0>)
80003a4: 4618 mov r0, r3
80003a6: f002 f90e bl 80025c6 <HAL_CAN_ConfigFilter>
80003aa: 4603 mov r3, r0
80003ac: 73fb strb r3, [r7, #15]
if (status == HAL_OK) {
80003ae: 7bfb ldrb r3, [r7, #15]
80003b0: 2b00 cmp r3, #0
80003b2: d104 bne.n 80003be <ftcan_add_filter+0xa2>
next_filter_no++;
80003b4: 4b04 ldr r3, [pc, #16] @ (80003c8 <ftcan_add_filter+0xac>)
80003b6: 681b ldr r3, [r3, #0]
80003b8: 3301 adds r3, #1
80003ba: 4a03 ldr r2, [pc, #12] @ (80003c8 <ftcan_add_filter+0xac>)
80003bc: 6013 str r3, [r2, #0]
}
return status;
80003be: 7bfb ldrb r3, [r7, #15]
}
80003c0: 4618 mov r0, r3
80003c2: 3710 adds r7, #16
80003c4: 46bd mov sp, r7
80003c6: bd80 pop {r7, pc}
80003c8: 2000004c .word 0x2000004c
80003cc: 20000050 .word 0x20000050
80003d0: 20000030 .word 0x20000030
080003d4 <HAL_CAN_RxFifo0MsgPendingCallback>:
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) {
80003d4: b580 push {r7, lr}
80003d6: b08c sub sp, #48 @ 0x30
80003d8: af00 add r7, sp, #0
80003da: 6078 str r0, [r7, #4]
if (handle != hcan) {
80003dc: 4b12 ldr r3, [pc, #72] @ (8000428 <HAL_CAN_RxFifo0MsgPendingCallback+0x54>)
80003de: 681b ldr r3, [r3, #0]
80003e0: 687a ldr r2, [r7, #4]
80003e2: 429a cmp r2, r3
80003e4: d117 bne.n 8000416 <HAL_CAN_RxFifo0MsgPendingCallback+0x42>
return;
}
CAN_RxHeaderTypeDef header;
uint8_t data[8];
if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) {
80003e6: 4b10 ldr r3, [pc, #64] @ (8000428 <HAL_CAN_RxFifo0MsgPendingCallback+0x54>)
80003e8: 6818 ldr r0, [r3, #0]
80003ea: f107 030c add.w r3, r7, #12
80003ee: f107 0214 add.w r2, r7, #20
80003f2: 2100 movs r1, #0
80003f4: f002 fac5 bl 8002982 <HAL_CAN_GetRxMessage>
80003f8: 4603 mov r3, r0
80003fa: 2b00 cmp r3, #0
80003fc: d10d bne.n 800041a <HAL_CAN_RxFifo0MsgPendingCallback+0x46>
return;
}
if (header.IDE != CAN_ID_STD) {
80003fe: 69fb ldr r3, [r7, #28]
8000400: 2b00 cmp r3, #0
8000402: d10c bne.n 800041e <HAL_CAN_RxFifo0MsgPendingCallback+0x4a>
return;
}
ftcan_msg_received_cb(header.StdId, header.DLC, data);
8000404: 697b ldr r3, [r7, #20]
8000406: b29b uxth r3, r3
8000408: 6a79 ldr r1, [r7, #36] @ 0x24
800040a: f107 020c add.w r2, r7, #12
800040e: 4618 mov r0, r3
8000410: f7ff ff0a bl 8000228 <ftcan_msg_received_cb>
8000414: e004 b.n 8000420 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
return;
8000416: bf00 nop
8000418: e002 b.n 8000420 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
return;
800041a: bf00 nop
800041c: e000 b.n 8000420 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
return;
800041e: bf00 nop
}
8000420: 3730 adds r7, #48 @ 0x30
8000422: 46bd mov sp, r7
8000424: bd80 pop {r7, pc}
8000426: bf00 nop
8000428: 20000030 .word 0x20000030
0800042c <ChannelControl_init>:
volatile enable_gpios enable;
extern int inhibit_SDC;
extern int prev_epsc_state;
void ChannelControl_init(){
800042c: b580 push {r7, lr}
800042e: af00 add r7, sp, #0
enable.porta.porta = 0;
8000430: 4b08 ldr r3, [pc, #32] @ (8000454 <ChannelControl_init+0x28>)
8000432: 2200 movs r2, #0
8000434: 701a strb r2, [r3, #0]
enable.portb.portb = 0;
8000436: 4b07 ldr r3, [pc, #28] @ (8000454 <ChannelControl_init+0x28>)
8000438: 2200 movs r2, #0
800043a: 705a strb r2, [r3, #1]
enable.portb.alwayson = 1;
800043c: 4a05 ldr r2, [pc, #20] @ (8000454 <ChannelControl_init+0x28>)
800043e: 7853 ldrb r3, [r2, #1]
8000440: f043 0301 orr.w r3, r3, #1
8000444: 7053 strb r3, [r2, #1]
ChannelControl_UpdateGPIOs(enable);
8000446: 4b03 ldr r3, [pc, #12] @ (8000454 <ChannelControl_init+0x28>)
8000448: 8818 ldrh r0, [r3, #0]
800044a: f000 f805 bl 8000458 <ChannelControl_UpdateGPIOs>
}
800044e: bf00 nop
8000450: bd80 pop {r7, pc}
8000452: bf00 nop
8000454: 20000078 .word 0x20000078
08000458 <ChannelControl_UpdateGPIOs>:
void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){
8000458: b580 push {r7, lr}
800045a: b082 sub sp, #8
800045c: af00 add r7, sp, #0
800045e: 80b8 strh r0, [r7, #4]
UpdatePorts.portb.alwayson = 1;
8000460: 797b ldrb r3, [r7, #5]
8000462: f043 0301 orr.w r3, r3, #1
8000466: 717b strb r3, [r7, #5]
if (inhibit_SDC == 1){
8000468: 4b64 ldr r3, [pc, #400] @ (80005fc <ChannelControl_UpdateGPIOs+0x1a4>)
800046a: 681b ldr r3, [r3, #0]
800046c: 2b01 cmp r3, #1
800046e: d109 bne.n 8000484 <ChannelControl_UpdateGPIOs+0x2c>
UpdatePorts.portb.sdc = 0;
8000470: 797b ldrb r3, [r7, #5]
8000472: f36f 0341 bfc r3, #1, #1
8000476: 717b strb r3, [r7, #5]
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, 1);
8000478: 2201 movs r2, #1
800047a: f44f 7100 mov.w r1, #512 @ 0x200
800047e: 4860 ldr r0, [pc, #384] @ (8000600 <ChannelControl_UpdateGPIOs+0x1a8>)
8000480: f003 f9a8 bl 80037d4 <HAL_GPIO_WritePin>
}
HAL_GPIO_WritePin(IN1_GPIO_Port, IN1_Pin, (GPIO_PinState)UpdatePorts.porta.acc_cooling); // Acc-Cooling
8000484: 793b ldrb r3, [r7, #4]
8000486: f3c3 0300 ubfx r3, r3, #0, #1
800048a: b2db uxtb r3, r3
800048c: 461a mov r2, r3
800048e: f44f 7100 mov.w r1, #512 @ 0x200
8000492: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000496: f003 f99d bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN2_GPIO_Port, IN2_Pin, (GPIO_PinState)UpdatePorts.porta.ts_cooling); // TS-Cooling
800049a: 793b ldrb r3, [r7, #4]
800049c: f3c3 0340 ubfx r3, r3, #1, #1
80004a0: b2db uxtb r3, r3
80004a2: 461a mov r2, r3
80004a4: f44f 7180 mov.w r1, #256 @ 0x100
80004a8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80004ac: f003 f992 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN3_GPIO_Port, IN3_Pin, (GPIO_PinState)UpdatePorts.porta.drs); // DRS
80004b0: 793b ldrb r3, [r7, #4]
80004b2: f3c3 0380 ubfx r3, r3, #2, #1
80004b6: b2db uxtb r3, r3
80004b8: 461a mov r2, r3
80004ba: f44f 5180 mov.w r1, #4096 @ 0x1000
80004be: 4851 ldr r0, [pc, #324] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
80004c0: f003 f988 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN4_GPIO_Port, IN4_Pin, (GPIO_PinState)UpdatePorts.porta.acu); // ACU
80004c4: 793b ldrb r3, [r7, #4]
80004c6: f3c3 03c0 ubfx r3, r3, #3, #1
80004ca: b2db uxtb r3, r3
80004cc: 461a mov r2, r3
80004ce: f44f 4100 mov.w r1, #32768 @ 0x8000
80004d2: 484c ldr r0, [pc, #304] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
80004d4: f003 f97e bl 80037d4 <HAL_GPIO_WritePin>
if (prev_epsc_state == 0 && ((UpdatePorts.porta.porta >> 4) & 1) == 1){ // will be replaced by precharge
80004d8: 4b4b ldr r3, [pc, #300] @ (8000608 <ChannelControl_UpdateGPIOs+0x1b0>)
80004da: 681b ldr r3, [r3, #0]
80004dc: 2b00 cmp r3, #0
80004de: d129 bne.n 8000534 <ChannelControl_UpdateGPIOs+0xdc>
80004e0: 793b ldrb r3, [r7, #4]
80004e2: 091b lsrs r3, r3, #4
80004e4: b2db uxtb r3, r3
80004e6: f003 0301 and.w r3, r3, #1
80004ea: 2b00 cmp r3, #0
80004ec: d022 beq.n 8000534 <ChannelControl_UpdateGPIOs+0xdc>
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 1); // precharge activate
80004ee: 2201 movs r2, #1
80004f0: 2180 movs r1, #128 @ 0x80
80004f2: 4843 ldr r0, [pc, #268] @ (8000600 <ChannelControl_UpdateGPIOs+0x1a8>)
80004f4: f003 f96e bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(2000); // contiuosly read precharge voltage
80004f8: f44f 60fa mov.w r0, #2000 @ 0x7d0
80004fc: f000 ff88 bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // if precharge voltage > 95% 24V enable PROFET
8000500: 793b ldrb r3, [r7, #4]
8000502: f3c3 1300 ubfx r3, r3, #4, #1
8000506: b2db uxtb r3, r3
8000508: 461a mov r2, r3
800050a: f44f 4180 mov.w r1, #16384 @ 0x4000
800050e: 483d ldr r0, [pc, #244] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
8000510: f003 f960 bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(100); // after few ms disengage precharge
8000514: 2064 movs r0, #100 @ 0x64
8000516: f000 ff7b bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 0);
800051a: 2200 movs r2, #0
800051c: 2180 movs r1, #128 @ 0x80
800051e: 4838 ldr r0, [pc, #224] @ (8000600 <ChannelControl_UpdateGPIOs+0x1a8>)
8000520: f003 f958 bl 80037d4 <HAL_GPIO_WritePin>
prev_epsc_state = UpdatePorts.porta.epsc;
8000524: 793b ldrb r3, [r7, #4]
8000526: f3c3 1300 ubfx r3, r3, #4, #1
800052a: b2db uxtb r3, r3
800052c: 461a mov r2, r3
800052e: 4b36 ldr r3, [pc, #216] @ (8000608 <ChannelControl_UpdateGPIOs+0x1b0>)
8000530: 601a str r2, [r3, #0]
8000532: e010 b.n 8000556 <ChannelControl_UpdateGPIOs+0xfe>
}
else {
HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc);
8000534: 793b ldrb r3, [r7, #4]
8000536: f3c3 1300 ubfx r3, r3, #4, #1
800053a: b2db uxtb r3, r3
800053c: 461a mov r2, r3
800053e: f44f 4180 mov.w r1, #16384 @ 0x4000
8000542: 4830 ldr r0, [pc, #192] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
8000544: f003 f946 bl 80037d4 <HAL_GPIO_WritePin>
prev_epsc_state = UpdatePorts.porta.epsc;
8000548: 793b ldrb r3, [r7, #4]
800054a: f3c3 1300 ubfx r3, r3, #4, #1
800054e: b2db uxtb r3, r3
8000550: 461a mov r2, r3
8000552: 4b2d ldr r3, [pc, #180] @ (8000608 <ChannelControl_UpdateGPIOs+0x1b0>)
8000554: 601a str r2, [r3, #0]
}
HAL_GPIO_WritePin(IN6_GPIO_Port, IN6_Pin, (GPIO_PinState)UpdatePorts.porta.inverter); // inverter
8000556: 793b ldrb r3, [r7, #4]
8000558: f3c3 1340 ubfx r3, r3, #5, #1
800055c: b2db uxtb r3, r3
800055e: 461a mov r2, r3
8000560: f44f 6180 mov.w r1, #1024 @ 0x400
8000564: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000568: f003 f934 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN7_GPIO_Port, IN7_Pin, (GPIO_PinState)UpdatePorts.porta.lidar); // lidar
800056c: 793b ldrb r3, [r7, #4]
800056e: f3c3 1380 ubfx r3, r3, #6, #1
8000572: b2db uxtb r3, r3
8000574: 461a mov r2, r3
8000576: f44f 7180 mov.w r1, #256 @ 0x100
800057a: 4822 ldr r0, [pc, #136] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
800057c: f003 f92a bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN8_GPIO_Port, IN8_Pin, (GPIO_PinState)UpdatePorts.porta.misc); // MISC
8000580: 793b ldrb r3, [r7, #4]
8000582: f3c3 13c0 ubfx r3, r3, #7, #1
8000586: b2db uxtb r3, r3
8000588: 461a mov r2, r3
800058a: f44f 5100 mov.w r1, #8192 @ 0x2000
800058e: 481d ldr r0, [pc, #116] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
8000590: f003 f920 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN9_GPIO_Port, IN9_Pin, (GPIO_PinState)UpdatePorts.portb.alwayson); // always on -> standardmäßig auf HIGH forcen
8000594: 797b ldrb r3, [r7, #5]
8000596: f3c3 0300 ubfx r3, r3, #0, #1
800059a: b2db uxtb r3, r3
800059c: 461a mov r2, r3
800059e: f44f 6100 mov.w r1, #2048 @ 0x800
80005a2: 4818 ldr r0, [pc, #96] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
80005a4: f003 f916 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN10_GPIO_Port, IN10_Pin, (GPIO_PinState)UpdatePorts.portb.sdc); // SDC -> muss anders controlled werden
80005a8: 797b ldrb r3, [r7, #5]
80005aa: f3c3 0340 ubfx r3, r3, #1, #1
80005ae: b2db uxtb r3, r3
80005b0: 461a mov r2, r3
80005b2: f44f 7100 mov.w r1, #512 @ 0x200
80005b6: 4813 ldr r0, [pc, #76] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
80005b8: f003 f90c bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN11_GPIO_Port, IN11_Pin, (GPIO_PinState)UpdatePorts.portb.ebs1); // EBS 1
80005bc: 797b ldrb r3, [r7, #5]
80005be: f3c3 0380 ubfx r3, r3, #2, #1
80005c2: b2db uxtb r3, r3
80005c4: 461a mov r2, r3
80005c6: 2104 movs r1, #4
80005c8: 480e ldr r0, [pc, #56] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
80005ca: f003 f903 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN12_GPIO_Port, IN12_Pin, (GPIO_PinState)UpdatePorts.portb.ebs2); // EBS 2
80005ce: 797b ldrb r3, [r7, #5]
80005d0: f3c3 03c0 ubfx r3, r3, #3, #1
80005d4: b2db uxtb r3, r3
80005d6: 461a mov r2, r3
80005d8: 2102 movs r1, #2
80005da: 480a ldr r0, [pc, #40] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
80005dc: f003 f8fa bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IN13_GPIO_Port, IN13_Pin, (GPIO_PinState)UpdatePorts.portb.ebs3); // EBS 3
80005e0: 797b ldrb r3, [r7, #5]
80005e2: f3c3 1300 ubfx r3, r3, #4, #1
80005e6: b2db uxtb r3, r3
80005e8: 461a mov r2, r3
80005ea: f44f 6180 mov.w r1, #1024 @ 0x400
80005ee: 4805 ldr r0, [pc, #20] @ (8000604 <ChannelControl_UpdateGPIOs+0x1ac>)
80005f0: f003 f8f0 bl 80037d4 <HAL_GPIO_WritePin>
}
80005f4: bf00 nop
80005f6: 3708 adds r7, #8
80005f8: 46bd mov sp, r7
80005fa: bd80 pop {r7, pc}
80005fc: 200002a8 .word 0x200002a8
8000600: 48000800 .word 0x48000800
8000604: 48000400 .word 0x48000400
8000608: 200002ac .word 0x200002ac
0800060c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800060c: b580 push {r7, lr}
800060e: b082 sub sp, #8
8000610: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000612: f000 fe97 bl 8001344 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000616: f000 f8b9 bl 800078c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800061a: f000 fb47 bl 8000cac <MX_GPIO_Init>
MX_DMA_Init();
800061e: f000 fb13 bl 8000c48 <MX_DMA_Init>
MX_ADC1_Init();
8000622: f000 f90f bl 8000844 <MX_ADC1_Init>
MX_ADC2_Init();
8000626: f000 f9d5 bl 80009d4 <MX_ADC2_Init>
MX_CAN_Init();
800062a: f000 fa6f bl 8000b0c <MX_CAN_Init>
MX_UART4_Init();
800062e: f000 fadb bl 8000be8 <MX_UART4_Init>
MX_TIM6_Init();
8000632: f000 faa1 bl 8000b78 <MX_TIM6_Init>
/* USER CODE BEGIN 2 */
// begin start-up animation
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET);
8000636: 2201 movs r2, #1
8000638: f44f 7100 mov.w r1, #512 @ 0x200
800063c: 484d ldr r0, [pc, #308] @ (8000774 <main+0x168>)
800063e: f003 f8c9 bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(100);
8000642: 2064 movs r0, #100 @ 0x64
8000644: f000 fee4 bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
8000648: 2200 movs r2, #0
800064a: f44f 7100 mov.w r1, #512 @ 0x200
800064e: 4849 ldr r0, [pc, #292] @ (8000774 <main+0x168>)
8000650: f003 f8c0 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET);
8000654: 2201 movs r2, #1
8000656: f44f 7180 mov.w r1, #256 @ 0x100
800065a: 4846 ldr r0, [pc, #280] @ (8000774 <main+0x168>)
800065c: f003 f8ba bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(100);
8000660: 2064 movs r0, #100 @ 0x64
8000662: f000 fed5 bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
8000666: 2200 movs r2, #0
8000668: f44f 7180 mov.w r1, #256 @ 0x100
800066c: 4841 ldr r0, [pc, #260] @ (8000774 <main+0x168>)
800066e: f003 f8b1 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_SET);
8000672: 2201 movs r2, #1
8000674: 2180 movs r1, #128 @ 0x80
8000676: 483f ldr r0, [pc, #252] @ (8000774 <main+0x168>)
8000678: f003 f8ac bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(100);
800067c: 2064 movs r0, #100 @ 0x64
800067e: f000 fec7 bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
8000682: 2200 movs r2, #0
8000684: 2180 movs r1, #128 @ 0x80
8000686: 483b ldr r0, [pc, #236] @ (8000774 <main+0x168>)
8000688: f003 f8a4 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET);
800068c: 2201 movs r2, #1
800068e: 2140 movs r1, #64 @ 0x40
8000690: 4838 ldr r0, [pc, #224] @ (8000774 <main+0x168>)
8000692: f003 f89f bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(100);
8000696: 2064 movs r0, #100 @ 0x64
8000698: f000 feba bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(LED4_GPIO_Port, LED3_Pin, GPIO_PIN_SET);
800069c: 2201 movs r2, #1
800069e: 2180 movs r1, #128 @ 0x80
80006a0: 4834 ldr r0, [pc, #208] @ (8000774 <main+0x168>)
80006a2: f003 f897 bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(100);
80006a6: 2064 movs r0, #100 @ 0x64
80006a8: f000 feb2 bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET);
80006ac: 2201 movs r2, #1
80006ae: f44f 7180 mov.w r1, #256 @ 0x100
80006b2: 4830 ldr r0, [pc, #192] @ (8000774 <main+0x168>)
80006b4: f003 f88e bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(100);
80006b8: 2064 movs r0, #100 @ 0x64
80006ba: f000 fea9 bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET);
80006be: 2201 movs r2, #1
80006c0: f44f 7100 mov.w r1, #512 @ 0x200
80006c4: 482b ldr r0, [pc, #172] @ (8000774 <main+0x168>)
80006c6: f003 f885 bl 80037d4 <HAL_GPIO_WritePin>
HAL_Delay(100);
80006ca: 2064 movs r0, #100 @ 0x64
80006cc: f000 fea0 bl 8001410 <HAL_Delay>
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
80006d0: 2200 movs r2, #0
80006d2: f44f 7100 mov.w r1, #512 @ 0x200
80006d6: 4827 ldr r0, [pc, #156] @ (8000774 <main+0x168>)
80006d8: f003 f87c bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
80006dc: 2200 movs r2, #0
80006de: f44f 7180 mov.w r1, #256 @ 0x100
80006e2: 4824 ldr r0, [pc, #144] @ (8000774 <main+0x168>)
80006e4: f003 f876 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
80006e8: 2200 movs r2, #0
80006ea: 2180 movs r1, #128 @ 0x80
80006ec: 4821 ldr r0, [pc, #132] @ (8000774 <main+0x168>)
80006ee: f003 f871 bl 80037d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_RESET);
80006f2: 2200 movs r2, #0
80006f4: 2140 movs r1, #64 @ 0x40
80006f6: 481f ldr r0, [pc, #124] @ (8000774 <main+0x168>)
80006f8: f003 f86c bl 80037d4 <HAL_GPIO_WritePin>
// end start-up animation
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); // indicates running STM
80006fc: 2201 movs r2, #1
80006fe: 2140 movs r1, #64 @ 0x40
8000700: 481c ldr r0, [pc, #112] @ (8000774 <main+0x168>)
8000702: f003 f867 bl 80037d4 <HAL_GPIO_WritePin>
ChannelControl_init();
8000706: f7ff fe91 bl 800042c <ChannelControl_init>
can_init(&hcan);
800070a: 481b ldr r0, [pc, #108] @ (8000778 <main+0x16c>)
800070c: f7ff fd5c bl 80001c8 <can_init>
// currentMonitor initialisieren
uint32_t lasttick = HAL_GetTick(); // Zeit in ms seit Start
8000710: f000 fe72 bl 80013f8 <HAL_GetTick>
8000714: 6078 str r0, [r7, #4]
inhibit_SDC = 0;
8000716: 4b19 ldr r3, [pc, #100] @ (800077c <main+0x170>)
8000718: 2200 movs r2, #0
800071a: 601a str r2, [r3, #0]
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
if (canmsg_received){
800071c: 4b18 ldr r3, [pc, #96] @ (8000780 <main+0x174>)
800071e: 781b ldrb r3, [r3, #0]
8000720: b2db uxtb r3, r3
8000722: 2b00 cmp r3, #0
8000724: d006 beq.n 8000734 <main+0x128>
canmsg_received = 0;
8000726: 4b16 ldr r3, [pc, #88] @ (8000780 <main+0x174>)
8000728: 2200 movs r2, #0
800072a: 701a strb r2, [r3, #0]
update_ports = rxstate.iostatus;
800072c: 4a15 ldr r2, [pc, #84] @ (8000784 <main+0x178>)
800072e: 4b16 ldr r3, [pc, #88] @ (8000788 <main+0x17c>)
8000730: 881b ldrh r3, [r3, #0]
8000732: 8013 strh r3, [r2, #0]
}
if ((HAL_GetTick() - lasttick) > 100u){
8000734: f000 fe60 bl 80013f8 <HAL_GetTick>
8000738: 4602 mov r2, r0
800073a: 687b ldr r3, [r7, #4]
800073c: 1ad3 subs r3, r2, r3
800073e: 2b64 cmp r3, #100 @ 0x64
8000740: d904 bls.n 800074c <main+0x140>
lasttick = HAL_GetTick();
8000742: f000 fe59 bl 80013f8 <HAL_GetTick>
8000746: 6078 str r0, [r7, #4]
can_sendloop();
8000748: f7ff fd4e bl 80001e8 <can_sendloop>
}
//watchdog (auch Status-LED an schalten)
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (GPIO_PinState)!update_ports.portb.sdc); // indicates open SDC
800074c: 4b0d ldr r3, [pc, #52] @ (8000784 <main+0x178>)
800074e: 785b ldrb r3, [r3, #1]
8000750: f3c3 0340 ubfx r3, r3, #1, #1
8000754: b2db uxtb r3, r3
8000756: f083 0301 eor.w r3, r3, #1
800075a: b2db uxtb r3, r3
800075c: 461a mov r2, r3
800075e: f44f 7100 mov.w r1, #512 @ 0x200
8000762: 4804 ldr r0, [pc, #16] @ (8000774 <main+0x168>)
8000764: f003 f836 bl 80037d4 <HAL_GPIO_WritePin>
// overcurrent check (wenn funktioniert, LED schalten)
ChannelControl_UpdateGPIOs(update_ports);
8000768: 4b06 ldr r3, [pc, #24] @ (8000784 <main+0x178>)
800076a: 8818 ldrh r0, [r3, #0]
800076c: f7ff fe74 bl 8000458 <ChannelControl_UpdateGPIOs>
if (canmsg_received){
8000770: e7d4 b.n 800071c <main+0x110>
8000772: bf00 nop
8000774: 48000800 .word 0x48000800
8000778: 200001a4 .word 0x200001a4
800077c: 200002a8 .word 0x200002a8
8000780: 2000002c .word 0x2000002c
8000784: 200002a0 .word 0x200002a0
8000788: 20000028 .word 0x20000028
0800078c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800078c: b580 push {r7, lr}
800078e: b09c sub sp, #112 @ 0x70
8000790: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000792: f107 0348 add.w r3, r7, #72 @ 0x48
8000796: 2228 movs r2, #40 @ 0x28
8000798: 2100 movs r1, #0
800079a: 4618 mov r0, r3
800079c: f005 fb2d bl 8005dfa <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80007a0: f107 0334 add.w r3, r7, #52 @ 0x34
80007a4: 2200 movs r2, #0
80007a6: 601a str r2, [r3, #0]
80007a8: 605a str r2, [r3, #4]
80007aa: 609a str r2, [r3, #8]
80007ac: 60da str r2, [r3, #12]
80007ae: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
80007b0: 463b mov r3, r7
80007b2: 2234 movs r2, #52 @ 0x34
80007b4: 2100 movs r1, #0
80007b6: 4618 mov r0, r3
80007b8: f005 fb1f bl 8005dfa <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80007bc: 2301 movs r3, #1
80007be: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80007c0: f44f 3380 mov.w r3, #65536 @ 0x10000
80007c4: 64fb str r3, [r7, #76] @ 0x4c
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
80007c6: 2300 movs r3, #0
80007c8: 653b str r3, [r7, #80] @ 0x50
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80007ca: 2301 movs r3, #1
80007cc: 65bb str r3, [r7, #88] @ 0x58
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80007ce: 2302 movs r3, #2
80007d0: 667b str r3, [r7, #100] @ 0x64
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80007d2: f44f 3380 mov.w r3, #65536 @ 0x10000
80007d6: 66bb str r3, [r7, #104] @ 0x68
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
80007d8: f44f 2300 mov.w r3, #524288 @ 0x80000
80007dc: 66fb str r3, [r7, #108] @ 0x6c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80007de: f107 0348 add.w r3, r7, #72 @ 0x48
80007e2: 4618 mov r0, r3
80007e4: f003 f80e bl 8003804 <HAL_RCC_OscConfig>
80007e8: 4603 mov r3, r0
80007ea: 2b00 cmp r3, #0
80007ec: d001 beq.n 80007f2 <SystemClock_Config+0x66>
{
Error_Handler();
80007ee: f000 fae3 bl 8000db8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80007f2: 230f movs r3, #15
80007f4: 637b str r3, [r7, #52] @ 0x34
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
80007f6: 2301 movs r3, #1
80007f8: 63bb str r3, [r7, #56] @ 0x38
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80007fa: 2300 movs r3, #0
80007fc: 63fb str r3, [r7, #60] @ 0x3c
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80007fe: 2300 movs r3, #0
8000800: 643b str r3, [r7, #64] @ 0x40
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000802: 2300 movs r3, #0
8000804: 647b str r3, [r7, #68] @ 0x44
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000806: f107 0334 add.w r3, r7, #52 @ 0x34
800080a: 2100 movs r1, #0
800080c: 4618 mov r0, r3
800080e: f004 f837 bl 8004880 <HAL_RCC_ClockConfig>
8000812: 4603 mov r3, r0
8000814: 2b00 cmp r3, #0
8000816: d001 beq.n 800081c <SystemClock_Config+0x90>
{
Error_Handler();
8000818: f000 face bl 8000db8 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_ADC12;
800081c: 2388 movs r3, #136 @ 0x88
800081e: 603b str r3, [r7, #0]
PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1;
8000820: 2300 movs r3, #0
8000822: 617b str r3, [r7, #20]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1;
8000824: f44f 7380 mov.w r3, #256 @ 0x100
8000828: 627b str r3, [r7, #36] @ 0x24
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
800082a: 463b mov r3, r7
800082c: 4618 mov r0, r3
800082e: f004 fa5f bl 8004cf0 <HAL_RCCEx_PeriphCLKConfig>
8000832: 4603 mov r3, r0
8000834: 2b00 cmp r3, #0
8000836: d001 beq.n 800083c <SystemClock_Config+0xb0>
{
Error_Handler();
8000838: f000 fabe bl 8000db8 <Error_Handler>
}
}
800083c: bf00 nop
800083e: 3770 adds r7, #112 @ 0x70
8000840: 46bd mov sp, r7
8000842: bd80 pop {r7, pc}
08000844 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000844: b580 push {r7, lr}
8000846: b08a sub sp, #40 @ 0x28
8000848: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
800084a: f107 031c add.w r3, r7, #28
800084e: 2200 movs r2, #0
8000850: 601a str r2, [r3, #0]
8000852: 605a str r2, [r3, #4]
8000854: 609a str r2, [r3, #8]
ADC_ChannelConfTypeDef sConfig = {0};
8000856: 1d3b adds r3, r7, #4
8000858: 2200 movs r2, #0
800085a: 601a str r2, [r3, #0]
800085c: 605a str r2, [r3, #4]
800085e: 609a str r2, [r3, #8]
8000860: 60da str r2, [r3, #12]
8000862: 611a str r2, [r3, #16]
8000864: 615a str r2, [r3, #20]
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8000866: 4b5a ldr r3, [pc, #360] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000868: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
800086c: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
800086e: 4b58 ldr r3, [pc, #352] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000870: 2200 movs r2, #0
8000872: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000874: 4b56 ldr r3, [pc, #344] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000876: 2200 movs r2, #0
8000878: 609a str r2, [r3, #8]
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
800087a: 4b55 ldr r3, [pc, #340] @ (80009d0 <MX_ADC1_Init+0x18c>)
800087c: 2201 movs r2, #1
800087e: 611a str r2, [r3, #16]
hadc1.Init.ContinuousConvMode = DISABLE;
8000880: 4b53 ldr r3, [pc, #332] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000882: 2200 movs r2, #0
8000884: 765a strb r2, [r3, #25]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000886: 4b52 ldr r3, [pc, #328] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000888: 2200 movs r2, #0
800088a: f883 2020 strb.w r2, [r3, #32]
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
800088e: 4b50 ldr r3, [pc, #320] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000890: f44f 6280 mov.w r2, #1024 @ 0x400
8000894: 62da str r2, [r3, #44] @ 0x2c
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO;
8000896: 4b4e ldr r3, [pc, #312] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000898: f44f 7250 mov.w r2, #832 @ 0x340
800089c: 629a str r2, [r3, #40] @ 0x28
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800089e: 4b4c ldr r3, [pc, #304] @ (80009d0 <MX_ADC1_Init+0x18c>)
80008a0: 2200 movs r2, #0
80008a2: 60da str r2, [r3, #12]
hadc1.Init.NbrOfConversion = 8;
80008a4: 4b4a ldr r3, [pc, #296] @ (80009d0 <MX_ADC1_Init+0x18c>)
80008a6: 2208 movs r2, #8
80008a8: 61da str r2, [r3, #28]
hadc1.Init.DMAContinuousRequests = ENABLE;
80008aa: 4b49 ldr r3, [pc, #292] @ (80009d0 <MX_ADC1_Init+0x18c>)
80008ac: 2201 movs r2, #1
80008ae: f883 2030 strb.w r2, [r3, #48] @ 0x30
hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
80008b2: 4b47 ldr r3, [pc, #284] @ (80009d0 <MX_ADC1_Init+0x18c>)
80008b4: 2208 movs r2, #8
80008b6: 615a str r2, [r3, #20]
hadc1.Init.LowPowerAutoWait = DISABLE;
80008b8: 4b45 ldr r3, [pc, #276] @ (80009d0 <MX_ADC1_Init+0x18c>)
80008ba: 2200 movs r2, #0
80008bc: 761a strb r2, [r3, #24]
hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
80008be: 4b44 ldr r3, [pc, #272] @ (80009d0 <MX_ADC1_Init+0x18c>)
80008c0: 2200 movs r2, #0
80008c2: 635a str r2, [r3, #52] @ 0x34
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80008c4: 4842 ldr r0, [pc, #264] @ (80009d0 <MX_ADC1_Init+0x18c>)
80008c6: f000 fde5 bl 8001494 <HAL_ADC_Init>
80008ca: 4603 mov r3, r0
80008cc: 2b00 cmp r3, #0
80008ce: d001 beq.n 80008d4 <MX_ADC1_Init+0x90>
{
Error_Handler();
80008d0: f000 fa72 bl 8000db8 <Error_Handler>
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
80008d4: 2300 movs r3, #0
80008d6: 61fb str r3, [r7, #28]
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
80008d8: f107 031c add.w r3, r7, #28
80008dc: 4619 mov r1, r3
80008de: 483c ldr r0, [pc, #240] @ (80009d0 <MX_ADC1_Init+0x18c>)
80008e0: f001 fc4a bl 8002178 <HAL_ADCEx_MultiModeConfigChannel>
80008e4: 4603 mov r3, r0
80008e6: 2b00 cmp r3, #0
80008e8: d001 beq.n 80008ee <MX_ADC1_Init+0xaa>
{
Error_Handler();
80008ea: f000 fa65 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_2;
80008ee: 2302 movs r3, #2
80008f0: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80008f2: 2301 movs r3, #1
80008f4: 60bb str r3, [r7, #8]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
80008f6: 2300 movs r3, #0
80008f8: 613b str r3, [r7, #16]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
80008fa: 2300 movs r3, #0
80008fc: 60fb str r3, [r7, #12]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
80008fe: 2300 movs r3, #0
8000900: 617b str r3, [r7, #20]
sConfig.Offset = 0;
8000902: 2300 movs r3, #0
8000904: 61bb str r3, [r7, #24]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000906: 1d3b adds r3, r7, #4
8000908: 4619 mov r1, r3
800090a: 4831 ldr r0, [pc, #196] @ (80009d0 <MX_ADC1_Init+0x18c>)
800090c: f001 f976 bl 8001bfc <HAL_ADC_ConfigChannel>
8000910: 4603 mov r3, r0
8000912: 2b00 cmp r3, #0
8000914: d001 beq.n 800091a <MX_ADC1_Init+0xd6>
{
Error_Handler();
8000916: f000 fa4f bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
800091a: 2301 movs r3, #1
800091c: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_2;
800091e: 2302 movs r3, #2
8000920: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000922: 1d3b adds r3, r7, #4
8000924: 4619 mov r1, r3
8000926: 482a ldr r0, [pc, #168] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000928: f001 f968 bl 8001bfc <HAL_ADC_ConfigChannel>
800092c: 4603 mov r3, r0
800092e: 2b00 cmp r3, #0
8000930: d001 beq.n 8000936 <MX_ADC1_Init+0xf2>
{
Error_Handler();
8000932: f000 fa41 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_3;
8000936: 2303 movs r3, #3
8000938: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
800093a: 1d3b adds r3, r7, #4
800093c: 4619 mov r1, r3
800093e: 4824 ldr r0, [pc, #144] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000940: f001 f95c bl 8001bfc <HAL_ADC_ConfigChannel>
8000944: 4603 mov r3, r0
8000946: 2b00 cmp r3, #0
8000948: d001 beq.n 800094e <MX_ADC1_Init+0x10a>
{
Error_Handler();
800094a: f000 fa35 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_4;
800094e: 2304 movs r3, #4
8000950: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000952: 1d3b adds r3, r7, #4
8000954: 4619 mov r1, r3
8000956: 481e ldr r0, [pc, #120] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000958: f001 f950 bl 8001bfc <HAL_ADC_ConfigChannel>
800095c: 4603 mov r3, r0
800095e: 2b00 cmp r3, #0
8000960: d001 beq.n 8000966 <MX_ADC1_Init+0x122>
{
Error_Handler();
8000962: f000 fa29 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_5;
8000966: 2305 movs r3, #5
8000968: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
800096a: 1d3b adds r3, r7, #4
800096c: 4619 mov r1, r3
800096e: 4818 ldr r0, [pc, #96] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000970: f001 f944 bl 8001bfc <HAL_ADC_ConfigChannel>
8000974: 4603 mov r3, r0
8000976: 2b00 cmp r3, #0
8000978: d001 beq.n 800097e <MX_ADC1_Init+0x13a>
{
Error_Handler();
800097a: f000 fa1d bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_6;
800097e: 2306 movs r3, #6
8000980: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000982: 1d3b adds r3, r7, #4
8000984: 4619 mov r1, r3
8000986: 4812 ldr r0, [pc, #72] @ (80009d0 <MX_ADC1_Init+0x18c>)
8000988: f001 f938 bl 8001bfc <HAL_ADC_ConfigChannel>
800098c: 4603 mov r3, r0
800098e: 2b00 cmp r3, #0
8000990: d001 beq.n 8000996 <MX_ADC1_Init+0x152>
{
Error_Handler();
8000992: f000 fa11 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_7;
8000996: 2307 movs r3, #7
8000998: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
800099a: 1d3b adds r3, r7, #4
800099c: 4619 mov r1, r3
800099e: 480c ldr r0, [pc, #48] @ (80009d0 <MX_ADC1_Init+0x18c>)
80009a0: f001 f92c bl 8001bfc <HAL_ADC_ConfigChannel>
80009a4: 4603 mov r3, r0
80009a6: 2b00 cmp r3, #0
80009a8: d001 beq.n 80009ae <MX_ADC1_Init+0x16a>
{
Error_Handler();
80009aa: f000 fa05 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_8;
80009ae: 2308 movs r3, #8
80009b0: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80009b2: 1d3b adds r3, r7, #4
80009b4: 4619 mov r1, r3
80009b6: 4806 ldr r0, [pc, #24] @ (80009d0 <MX_ADC1_Init+0x18c>)
80009b8: f001 f920 bl 8001bfc <HAL_ADC_ConfigChannel>
80009bc: 4603 mov r3, r0
80009be: 2b00 cmp r3, #0
80009c0: d001 beq.n 80009c6 <MX_ADC1_Init+0x182>
{
Error_Handler();
80009c2: f000 f9f9 bl 8000db8 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
80009c6: bf00 nop
80009c8: 3728 adds r7, #40 @ 0x28
80009ca: 46bd mov sp, r7
80009cc: bd80 pop {r7, pc}
80009ce: bf00 nop
80009d0: 2000007c .word 0x2000007c
080009d4 <MX_ADC2_Init>:
* @brief ADC2 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC2_Init(void)
{
80009d4: b580 push {r7, lr}
80009d6: b086 sub sp, #24
80009d8: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80009da: 463b mov r3, r7
80009dc: 2200 movs r2, #0
80009de: 601a str r2, [r3, #0]
80009e0: 605a str r2, [r3, #4]
80009e2: 609a str r2, [r3, #8]
80009e4: 60da str r2, [r3, #12]
80009e6: 611a str r2, [r3, #16]
80009e8: 615a str r2, [r3, #20]
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
80009ea: 4b46 ldr r3, [pc, #280] @ (8000b04 <MX_ADC2_Init+0x130>)
80009ec: 4a46 ldr r2, [pc, #280] @ (8000b08 <MX_ADC2_Init+0x134>)
80009ee: 601a str r2, [r3, #0]
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
80009f0: 4b44 ldr r3, [pc, #272] @ (8000b04 <MX_ADC2_Init+0x130>)
80009f2: 2200 movs r2, #0
80009f4: 605a str r2, [r3, #4]
hadc2.Init.Resolution = ADC_RESOLUTION_12B;
80009f6: 4b43 ldr r3, [pc, #268] @ (8000b04 <MX_ADC2_Init+0x130>)
80009f8: 2200 movs r2, #0
80009fa: 609a str r2, [r3, #8]
hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
80009fc: 4b41 ldr r3, [pc, #260] @ (8000b04 <MX_ADC2_Init+0x130>)
80009fe: 2201 movs r2, #1
8000a00: 611a str r2, [r3, #16]
hadc2.Init.ContinuousConvMode = DISABLE;
8000a02: 4b40 ldr r3, [pc, #256] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a04: 2200 movs r2, #0
8000a06: 765a strb r2, [r3, #25]
hadc2.Init.DiscontinuousConvMode = DISABLE;
8000a08: 4b3e ldr r3, [pc, #248] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a0a: 2200 movs r2, #0
8000a0c: f883 2020 strb.w r2, [r3, #32]
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
8000a10: 4b3c ldr r3, [pc, #240] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a12: f44f 6280 mov.w r2, #1024 @ 0x400
8000a16: 62da str r2, [r3, #44] @ 0x2c
hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO;
8000a18: 4b3a ldr r3, [pc, #232] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a1a: f44f 7250 mov.w r2, #832 @ 0x340
8000a1e: 629a str r2, [r3, #40] @ 0x28
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000a20: 4b38 ldr r3, [pc, #224] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a22: 2200 movs r2, #0
8000a24: 60da str r2, [r3, #12]
hadc2.Init.NbrOfConversion = 6;
8000a26: 4b37 ldr r3, [pc, #220] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a28: 2206 movs r2, #6
8000a2a: 61da str r2, [r3, #28]
hadc2.Init.DMAContinuousRequests = ENABLE;
8000a2c: 4b35 ldr r3, [pc, #212] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a2e: 2201 movs r2, #1
8000a30: f883 2030 strb.w r2, [r3, #48] @ 0x30
hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
8000a34: 4b33 ldr r3, [pc, #204] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a36: 2208 movs r2, #8
8000a38: 615a str r2, [r3, #20]
hadc2.Init.LowPowerAutoWait = DISABLE;
8000a3a: 4b32 ldr r3, [pc, #200] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a3c: 2200 movs r2, #0
8000a3e: 761a strb r2, [r3, #24]
hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
8000a40: 4b30 ldr r3, [pc, #192] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a42: 2200 movs r2, #0
8000a44: 635a str r2, [r3, #52] @ 0x34
if (HAL_ADC_Init(&hadc2) != HAL_OK)
8000a46: 482f ldr r0, [pc, #188] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a48: f000 fd24 bl 8001494 <HAL_ADC_Init>
8000a4c: 4603 mov r3, r0
8000a4e: 2b00 cmp r3, #0
8000a50: d001 beq.n 8000a56 <MX_ADC2_Init+0x82>
{
Error_Handler();
8000a52: f000 f9b1 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
8000a56: 2301 movs r3, #1
8000a58: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000a5a: 2301 movs r3, #1
8000a5c: 607b str r3, [r7, #4]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000a5e: 2300 movs r3, #0
8000a60: 60fb str r3, [r7, #12]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
8000a62: 2300 movs r3, #0
8000a64: 60bb str r3, [r7, #8]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8000a66: 2300 movs r3, #0
8000a68: 613b str r3, [r7, #16]
sConfig.Offset = 0;
8000a6a: 2300 movs r3, #0
8000a6c: 617b str r3, [r7, #20]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000a6e: 463b mov r3, r7
8000a70: 4619 mov r1, r3
8000a72: 4824 ldr r0, [pc, #144] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a74: f001 f8c2 bl 8001bfc <HAL_ADC_ConfigChannel>
8000a78: 4603 mov r3, r0
8000a7a: 2b00 cmp r3, #0
8000a7c: d001 beq.n 8000a82 <MX_ADC2_Init+0xae>
{
Error_Handler();
8000a7e: f000 f99b bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_2;
8000a82: 2302 movs r3, #2
8000a84: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000a86: 463b mov r3, r7
8000a88: 4619 mov r1, r3
8000a8a: 481e ldr r0, [pc, #120] @ (8000b04 <MX_ADC2_Init+0x130>)
8000a8c: f001 f8b6 bl 8001bfc <HAL_ADC_ConfigChannel>
8000a90: 4603 mov r3, r0
8000a92: 2b00 cmp r3, #0
8000a94: d001 beq.n 8000a9a <MX_ADC2_Init+0xc6>
{
Error_Handler();
8000a96: f000 f98f bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_3;
8000a9a: 2303 movs r3, #3
8000a9c: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000a9e: 463b mov r3, r7
8000aa0: 4619 mov r1, r3
8000aa2: 4818 ldr r0, [pc, #96] @ (8000b04 <MX_ADC2_Init+0x130>)
8000aa4: f001 f8aa bl 8001bfc <HAL_ADC_ConfigChannel>
8000aa8: 4603 mov r3, r0
8000aaa: 2b00 cmp r3, #0
8000aac: d001 beq.n 8000ab2 <MX_ADC2_Init+0xde>
{
Error_Handler();
8000aae: f000 f983 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_4;
8000ab2: 2304 movs r3, #4
8000ab4: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000ab6: 463b mov r3, r7
8000ab8: 4619 mov r1, r3
8000aba: 4812 ldr r0, [pc, #72] @ (8000b04 <MX_ADC2_Init+0x130>)
8000abc: f001 f89e bl 8001bfc <HAL_ADC_ConfigChannel>
8000ac0: 4603 mov r3, r0
8000ac2: 2b00 cmp r3, #0
8000ac4: d001 beq.n 8000aca <MX_ADC2_Init+0xf6>
{
Error_Handler();
8000ac6: f000 f977 bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_5;
8000aca: 2305 movs r3, #5
8000acc: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000ace: 463b mov r3, r7
8000ad0: 4619 mov r1, r3
8000ad2: 480c ldr r0, [pc, #48] @ (8000b04 <MX_ADC2_Init+0x130>)
8000ad4: f001 f892 bl 8001bfc <HAL_ADC_ConfigChannel>
8000ad8: 4603 mov r3, r0
8000ada: 2b00 cmp r3, #0
8000adc: d001 beq.n 8000ae2 <MX_ADC2_Init+0x10e>
{
Error_Handler();
8000ade: f000 f96b bl 8000db8 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Rank = ADC_REGULAR_RANK_6;
8000ae2: 2306 movs r3, #6
8000ae4: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000ae6: 463b mov r3, r7
8000ae8: 4619 mov r1, r3
8000aea: 4806 ldr r0, [pc, #24] @ (8000b04 <MX_ADC2_Init+0x130>)
8000aec: f001 f886 bl 8001bfc <HAL_ADC_ConfigChannel>
8000af0: 4603 mov r3, r0
8000af2: 2b00 cmp r3, #0
8000af4: d001 beq.n 8000afa <MX_ADC2_Init+0x126>
{
Error_Handler();
8000af6: f000 f95f bl 8000db8 <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
8000afa: bf00 nop
8000afc: 3718 adds r7, #24
8000afe: 46bd mov sp, r7
8000b00: bd80 pop {r7, pc}
8000b02: bf00 nop
8000b04: 200000cc .word 0x200000cc
8000b08: 50000100 .word 0x50000100
08000b0c <MX_CAN_Init>:
* @brief CAN Initialization Function
* @param None
* @retval None
*/
static void MX_CAN_Init(void)
{
8000b0c: b580 push {r7, lr}
8000b0e: af00 add r7, sp, #0
/* USER CODE END CAN_Init 0 */
/* USER CODE BEGIN CAN_Init 1 */
/* USER CODE END CAN_Init 1 */
hcan.Instance = CAN;
8000b10: 4b17 ldr r3, [pc, #92] @ (8000b70 <MX_CAN_Init+0x64>)
8000b12: 4a18 ldr r2, [pc, #96] @ (8000b74 <MX_CAN_Init+0x68>)
8000b14: 601a str r2, [r3, #0]
hcan.Init.Prescaler = 2;
8000b16: 4b16 ldr r3, [pc, #88] @ (8000b70 <MX_CAN_Init+0x64>)
8000b18: 2202 movs r2, #2
8000b1a: 605a str r2, [r3, #4]
hcan.Init.Mode = CAN_MODE_NORMAL;
8000b1c: 4b14 ldr r3, [pc, #80] @ (8000b70 <MX_CAN_Init+0x64>)
8000b1e: 2200 movs r2, #0
8000b20: 609a str r2, [r3, #8]
hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
8000b22: 4b13 ldr r3, [pc, #76] @ (8000b70 <MX_CAN_Init+0x64>)
8000b24: 2200 movs r2, #0
8000b26: 60da str r2, [r3, #12]
hcan.Init.TimeSeg1 = CAN_BS1_13TQ;
8000b28: 4b11 ldr r3, [pc, #68] @ (8000b70 <MX_CAN_Init+0x64>)
8000b2a: f44f 2240 mov.w r2, #786432 @ 0xc0000
8000b2e: 611a str r2, [r3, #16]
hcan.Init.TimeSeg2 = CAN_BS2_2TQ;
8000b30: 4b0f ldr r3, [pc, #60] @ (8000b70 <MX_CAN_Init+0x64>)
8000b32: f44f 1280 mov.w r2, #1048576 @ 0x100000
8000b36: 615a str r2, [r3, #20]
hcan.Init.TimeTriggeredMode = DISABLE;
8000b38: 4b0d ldr r3, [pc, #52] @ (8000b70 <MX_CAN_Init+0x64>)
8000b3a: 2200 movs r2, #0
8000b3c: 761a strb r2, [r3, #24]
hcan.Init.AutoBusOff = DISABLE;
8000b3e: 4b0c ldr r3, [pc, #48] @ (8000b70 <MX_CAN_Init+0x64>)
8000b40: 2200 movs r2, #0
8000b42: 765a strb r2, [r3, #25]
hcan.Init.AutoWakeUp = DISABLE;
8000b44: 4b0a ldr r3, [pc, #40] @ (8000b70 <MX_CAN_Init+0x64>)
8000b46: 2200 movs r2, #0
8000b48: 769a strb r2, [r3, #26]
hcan.Init.AutoRetransmission = DISABLE;
8000b4a: 4b09 ldr r3, [pc, #36] @ (8000b70 <MX_CAN_Init+0x64>)
8000b4c: 2200 movs r2, #0
8000b4e: 76da strb r2, [r3, #27]
hcan.Init.ReceiveFifoLocked = DISABLE;
8000b50: 4b07 ldr r3, [pc, #28] @ (8000b70 <MX_CAN_Init+0x64>)
8000b52: 2200 movs r2, #0
8000b54: 771a strb r2, [r3, #28]
hcan.Init.TransmitFifoPriority = DISABLE;
8000b56: 4b06 ldr r3, [pc, #24] @ (8000b70 <MX_CAN_Init+0x64>)
8000b58: 2200 movs r2, #0
8000b5a: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan) != HAL_OK)
8000b5c: 4804 ldr r0, [pc, #16] @ (8000b70 <MX_CAN_Init+0x64>)
8000b5e: f001 fc37 bl 80023d0 <HAL_CAN_Init>
8000b62: 4603 mov r3, r0
8000b64: 2b00 cmp r3, #0
8000b66: d001 beq.n 8000b6c <MX_CAN_Init+0x60>
{
Error_Handler();
8000b68: f000 f926 bl 8000db8 <Error_Handler>
}
/* USER CODE BEGIN CAN_Init 2 */
/* USER CODE END CAN_Init 2 */
}
8000b6c: bf00 nop
8000b6e: bd80 pop {r7, pc}
8000b70: 200001a4 .word 0x200001a4
8000b74: 40006400 .word 0x40006400
08000b78 <MX_TIM6_Init>:
* @brief TIM6 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM6_Init(void)
{
8000b78: b580 push {r7, lr}
8000b7a: b084 sub sp, #16
8000b7c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_Init 0 */
/* USER CODE END TIM6_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000b7e: 1d3b adds r3, r7, #4
8000b80: 2200 movs r2, #0
8000b82: 601a str r2, [r3, #0]
8000b84: 605a str r2, [r3, #4]
8000b86: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM6_Init 1 */
/* USER CODE END TIM6_Init 1 */
htim6.Instance = TIM6;
8000b88: 4b15 ldr r3, [pc, #84] @ (8000be0 <MX_TIM6_Init+0x68>)
8000b8a: 4a16 ldr r2, [pc, #88] @ (8000be4 <MX_TIM6_Init+0x6c>)
8000b8c: 601a str r2, [r3, #0]
htim6.Init.Prescaler = 400;
8000b8e: 4b14 ldr r3, [pc, #80] @ (8000be0 <MX_TIM6_Init+0x68>)
8000b90: f44f 72c8 mov.w r2, #400 @ 0x190
8000b94: 605a str r2, [r3, #4]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
8000b96: 4b12 ldr r3, [pc, #72] @ (8000be0 <MX_TIM6_Init+0x68>)
8000b98: 2200 movs r2, #0
8000b9a: 609a str r2, [r3, #8]
htim6.Init.Period = 8000-1;
8000b9c: 4b10 ldr r3, [pc, #64] @ (8000be0 <MX_TIM6_Init+0x68>)
8000b9e: f641 723f movw r2, #7999 @ 0x1f3f
8000ba2: 60da str r2, [r3, #12]
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000ba4: 4b0e ldr r3, [pc, #56] @ (8000be0 <MX_TIM6_Init+0x68>)
8000ba6: 2200 movs r2, #0
8000ba8: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
8000baa: 480d ldr r0, [pc, #52] @ (8000be0 <MX_TIM6_Init+0x68>)
8000bac: f004 fa32 bl 8005014 <HAL_TIM_Base_Init>
8000bb0: 4603 mov r3, r0
8000bb2: 2b00 cmp r3, #0
8000bb4: d001 beq.n 8000bba <MX_TIM6_Init+0x42>
{
Error_Handler();
8000bb6: f000 f8ff bl 8000db8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
8000bba: 2320 movs r3, #32
8000bbc: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000bbe: 2300 movs r3, #0
8000bc0: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
8000bc2: 1d3b adds r3, r7, #4
8000bc4: 4619 mov r1, r3
8000bc6: 4806 ldr r0, [pc, #24] @ (8000be0 <MX_TIM6_Init+0x68>)
8000bc8: f004 fc4e bl 8005468 <HAL_TIMEx_MasterConfigSynchronization>
8000bcc: 4603 mov r3, r0
8000bce: 2b00 cmp r3, #0
8000bd0: d001 beq.n 8000bd6 <MX_TIM6_Init+0x5e>
{
Error_Handler();
8000bd2: f000 f8f1 bl 8000db8 <Error_Handler>
}
/* USER CODE BEGIN TIM6_Init 2 */
/* USER CODE END TIM6_Init 2 */
}
8000bd6: bf00 nop
8000bd8: 3710 adds r7, #16
8000bda: 46bd mov sp, r7
8000bdc: bd80 pop {r7, pc}
8000bde: bf00 nop
8000be0: 200001cc .word 0x200001cc
8000be4: 40001000 .word 0x40001000
08000be8 <MX_UART4_Init>:
* @brief UART4 Initialization Function
* @param None
* @retval None
*/
static void MX_UART4_Init(void)
{
8000be8: b580 push {r7, lr}
8000bea: af00 add r7, sp, #0
/* USER CODE END UART4_Init 0 */
/* USER CODE BEGIN UART4_Init 1 */
/* USER CODE END UART4_Init 1 */
huart4.Instance = UART4;
8000bec: 4b14 ldr r3, [pc, #80] @ (8000c40 <MX_UART4_Init+0x58>)
8000bee: 4a15 ldr r2, [pc, #84] @ (8000c44 <MX_UART4_Init+0x5c>)
8000bf0: 601a str r2, [r3, #0]
huart4.Init.BaudRate = 115200;
8000bf2: 4b13 ldr r3, [pc, #76] @ (8000c40 <MX_UART4_Init+0x58>)
8000bf4: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000bf8: 605a str r2, [r3, #4]
huart4.Init.WordLength = UART_WORDLENGTH_8B;
8000bfa: 4b11 ldr r3, [pc, #68] @ (8000c40 <MX_UART4_Init+0x58>)
8000bfc: 2200 movs r2, #0
8000bfe: 609a str r2, [r3, #8]
huart4.Init.StopBits = UART_STOPBITS_1;
8000c00: 4b0f ldr r3, [pc, #60] @ (8000c40 <MX_UART4_Init+0x58>)
8000c02: 2200 movs r2, #0
8000c04: 60da str r2, [r3, #12]
huart4.Init.Parity = UART_PARITY_NONE;
8000c06: 4b0e ldr r3, [pc, #56] @ (8000c40 <MX_UART4_Init+0x58>)
8000c08: 2200 movs r2, #0
8000c0a: 611a str r2, [r3, #16]
huart4.Init.Mode = UART_MODE_TX_RX;
8000c0c: 4b0c ldr r3, [pc, #48] @ (8000c40 <MX_UART4_Init+0x58>)
8000c0e: 220c movs r2, #12
8000c10: 615a str r2, [r3, #20]
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000c12: 4b0b ldr r3, [pc, #44] @ (8000c40 <MX_UART4_Init+0x58>)
8000c14: 2200 movs r2, #0
8000c16: 619a str r2, [r3, #24]
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
8000c18: 4b09 ldr r3, [pc, #36] @ (8000c40 <MX_UART4_Init+0x58>)
8000c1a: 2200 movs r2, #0
8000c1c: 61da str r2, [r3, #28]
huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000c1e: 4b08 ldr r3, [pc, #32] @ (8000c40 <MX_UART4_Init+0x58>)
8000c20: 2200 movs r2, #0
8000c22: 621a str r2, [r3, #32]
huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000c24: 4b06 ldr r3, [pc, #24] @ (8000c40 <MX_UART4_Init+0x58>)
8000c26: 2200 movs r2, #0
8000c28: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart4) != HAL_OK)
8000c2a: 4805 ldr r0, [pc, #20] @ (8000c40 <MX_UART4_Init+0x58>)
8000c2c: f004 fcae bl 800558c <HAL_UART_Init>
8000c30: 4603 mov r3, r0
8000c32: 2b00 cmp r3, #0
8000c34: d001 beq.n 8000c3a <MX_UART4_Init+0x52>
{
Error_Handler();
8000c36: f000 f8bf bl 8000db8 <Error_Handler>
}
/* USER CODE BEGIN UART4_Init 2 */
/* USER CODE END UART4_Init 2 */
}
8000c3a: bf00 nop
8000c3c: bd80 pop {r7, pc}
8000c3e: bf00 nop
8000c40: 20000218 .word 0x20000218
8000c44: 40004c00 .word 0x40004c00
08000c48 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
8000c48: b580 push {r7, lr}
8000c4a: b082 sub sp, #8
8000c4c: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
8000c4e: 4b16 ldr r3, [pc, #88] @ (8000ca8 <MX_DMA_Init+0x60>)
8000c50: 695b ldr r3, [r3, #20]
8000c52: 4a15 ldr r2, [pc, #84] @ (8000ca8 <MX_DMA_Init+0x60>)
8000c54: f043 0301 orr.w r3, r3, #1
8000c58: 6153 str r3, [r2, #20]
8000c5a: 4b13 ldr r3, [pc, #76] @ (8000ca8 <MX_DMA_Init+0x60>)
8000c5c: 695b ldr r3, [r3, #20]
8000c5e: f003 0301 and.w r3, r3, #1
8000c62: 607b str r3, [r7, #4]
8000c64: 687b ldr r3, [r7, #4]
__HAL_RCC_DMA2_CLK_ENABLE();
8000c66: 4b10 ldr r3, [pc, #64] @ (8000ca8 <MX_DMA_Init+0x60>)
8000c68: 695b ldr r3, [r3, #20]
8000c6a: 4a0f ldr r2, [pc, #60] @ (8000ca8 <MX_DMA_Init+0x60>)
8000c6c: f043 0302 orr.w r3, r3, #2
8000c70: 6153 str r3, [r2, #20]
8000c72: 4b0d ldr r3, [pc, #52] @ (8000ca8 <MX_DMA_Init+0x60>)
8000c74: 695b ldr r3, [r3, #20]
8000c76: f003 0302 and.w r3, r3, #2
8000c7a: 603b str r3, [r7, #0]
8000c7c: 683b ldr r3, [r7, #0]
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8000c7e: 2200 movs r2, #0
8000c80: 2100 movs r1, #0
8000c82: 200b movs r0, #11
8000c84: f002 facf bl 8003226 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
8000c88: 200b movs r0, #11
8000c8a: f002 fae8 bl 800325e <HAL_NVIC_EnableIRQ>
/* DMA2_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Channel1_IRQn, 0, 0);
8000c8e: 2200 movs r2, #0
8000c90: 2100 movs r1, #0
8000c92: 2038 movs r0, #56 @ 0x38
8000c94: f002 fac7 bl 8003226 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA2_Channel1_IRQn);
8000c98: 2038 movs r0, #56 @ 0x38
8000c9a: f002 fae0 bl 800325e <HAL_NVIC_EnableIRQ>
}
8000c9e: bf00 nop
8000ca0: 3708 adds r7, #8
8000ca2: 46bd mov sp, r7
8000ca4: bd80 pop {r7, pc}
8000ca6: bf00 nop
8000ca8: 40021000 .word 0x40021000
08000cac <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000cac: b580 push {r7, lr}
8000cae: b08a sub sp, #40 @ 0x28
8000cb0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000cb2: f107 0314 add.w r3, r7, #20
8000cb6: 2200 movs r2, #0
8000cb8: 601a str r2, [r3, #0]
8000cba: 605a str r2, [r3, #4]
8000cbc: 609a str r2, [r3, #8]
8000cbe: 60da str r2, [r3, #12]
8000cc0: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
8000cc2: 4b3a ldr r3, [pc, #232] @ (8000dac <MX_GPIO_Init+0x100>)
8000cc4: 695b ldr r3, [r3, #20]
8000cc6: 4a39 ldr r2, [pc, #228] @ (8000dac <MX_GPIO_Init+0x100>)
8000cc8: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8000ccc: 6153 str r3, [r2, #20]
8000cce: 4b37 ldr r3, [pc, #220] @ (8000dac <MX_GPIO_Init+0x100>)
8000cd0: 695b ldr r3, [r3, #20]
8000cd2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8000cd6: 613b str r3, [r7, #16]
8000cd8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000cda: 4b34 ldr r3, [pc, #208] @ (8000dac <MX_GPIO_Init+0x100>)
8000cdc: 695b ldr r3, [r3, #20]
8000cde: 4a33 ldr r2, [pc, #204] @ (8000dac <MX_GPIO_Init+0x100>)
8000ce0: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8000ce4: 6153 str r3, [r2, #20]
8000ce6: 4b31 ldr r3, [pc, #196] @ (8000dac <MX_GPIO_Init+0x100>)
8000ce8: 695b ldr r3, [r3, #20]
8000cea: f403 2300 and.w r3, r3, #524288 @ 0x80000
8000cee: 60fb str r3, [r7, #12]
8000cf0: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000cf2: 4b2e ldr r3, [pc, #184] @ (8000dac <MX_GPIO_Init+0x100>)
8000cf4: 695b ldr r3, [r3, #20]
8000cf6: 4a2d ldr r2, [pc, #180] @ (8000dac <MX_GPIO_Init+0x100>)
8000cf8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000cfc: 6153 str r3, [r2, #20]
8000cfe: 4b2b ldr r3, [pc, #172] @ (8000dac <MX_GPIO_Init+0x100>)
8000d00: 695b ldr r3, [r3, #20]
8000d02: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000d06: 60bb str r3, [r7, #8]
8000d08: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000d0a: 4b28 ldr r3, [pc, #160] @ (8000dac <MX_GPIO_Init+0x100>)
8000d0c: 695b ldr r3, [r3, #20]
8000d0e: 4a27 ldr r2, [pc, #156] @ (8000dac <MX_GPIO_Init+0x100>)
8000d10: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8000d14: 6153 str r3, [r2, #20]
8000d16: 4b25 ldr r3, [pc, #148] @ (8000dac <MX_GPIO_Init+0x100>)
8000d18: 695b ldr r3, [r3, #20]
8000d1a: f403 2380 and.w r3, r3, #262144 @ 0x40000
8000d1e: 607b str r3, [r7, #4]
8000d20: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin
8000d22: 2200 movs r2, #0
8000d24: f64f 7176 movw r1, #65398 @ 0xff76
8000d28: 4821 ldr r0, [pc, #132] @ (8000db0 <MX_GPIO_Init+0x104>)
8000d2a: f002 fd53 bl 80037d4 <HAL_GPIO_WritePin>
|IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin
|DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin
|IN10_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin, GPIO_PIN_RESET);
8000d2e: 2200 movs r2, #0
8000d30: f44f 7170 mov.w r1, #960 @ 0x3c0
8000d34: 481f ldr r0, [pc, #124] @ (8000db4 <MX_GPIO_Init+0x108>)
8000d36: f002 fd4d bl 80037d4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, IN2_Pin|IN1_Pin|IN6_Pin, GPIO_PIN_RESET);
8000d3a: 2200 movs r2, #0
8000d3c: f44f 61e0 mov.w r1, #1792 @ 0x700
8000d40: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000d44: f002 fd46 bl 80037d4 <HAL_GPIO_WritePin>
/*Configure GPIO pins : IN12_Pin IN11_Pin IN13_Pin IN9_Pin
IN3_Pin IN8_Pin IN5_Pin IN4_Pin
DSEL0_Pin DSEL1_Pin PC_EN_Pin IN7_Pin
IN10_Pin */
GPIO_InitStruct.Pin = IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin
8000d48: f64f 7376 movw r3, #65398 @ 0xff76
8000d4c: 617b str r3, [r7, #20]
|IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin
|DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin
|IN10_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d4e: 2301 movs r3, #1
8000d50: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d52: 2300 movs r3, #0
8000d54: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d56: 2300 movs r3, #0
8000d58: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000d5a: f107 0314 add.w r3, r7, #20
8000d5e: 4619 mov r1, r3
8000d60: 4813 ldr r0, [pc, #76] @ (8000db0 <MX_GPIO_Init+0x104>)
8000d62: f002 fbbd bl 80034e0 <HAL_GPIO_Init>
/*Configure GPIO pins : LED4_Pin LED3_Pin LED2_Pin LED1_Pin */
GPIO_InitStruct.Pin = LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin;
8000d66: f44f 7370 mov.w r3, #960 @ 0x3c0
8000d6a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d6c: 2301 movs r3, #1
8000d6e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d70: 2300 movs r3, #0
8000d72: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d74: 2300 movs r3, #0
8000d76: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000d78: f107 0314 add.w r3, r7, #20
8000d7c: 4619 mov r1, r3
8000d7e: 480d ldr r0, [pc, #52] @ (8000db4 <MX_GPIO_Init+0x108>)
8000d80: f002 fbae bl 80034e0 <HAL_GPIO_Init>
/*Configure GPIO pins : IN2_Pin IN1_Pin IN6_Pin */
GPIO_InitStruct.Pin = IN2_Pin|IN1_Pin|IN6_Pin;
8000d84: f44f 63e0 mov.w r3, #1792 @ 0x700
8000d88: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d8a: 2301 movs r3, #1
8000d8c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d8e: 2300 movs r3, #0
8000d90: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d92: 2300 movs r3, #0
8000d94: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000d96: f107 0314 add.w r3, r7, #20
8000d9a: 4619 mov r1, r3
8000d9c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000da0: f002 fb9e bl 80034e0 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000da4: bf00 nop
8000da6: 3728 adds r7, #40 @ 0x28
8000da8: 46bd mov sp, r7
8000daa: bd80 pop {r7, pc}
8000dac: 40021000 .word 0x40021000
8000db0: 48000400 .word 0x48000400
8000db4: 48000800 .word 0x48000800
08000db8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000db8: b480 push {r7}
8000dba: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000dbc: b672 cpsid i
}
8000dbe: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000dc0: bf00 nop
8000dc2: e7fd b.n 8000dc0 <Error_Handler+0x8>
08000dc4 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000dc4: b480 push {r7}
8000dc6: b083 sub sp, #12
8000dc8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000dca: 4b0f ldr r3, [pc, #60] @ (8000e08 <HAL_MspInit+0x44>)
8000dcc: 699b ldr r3, [r3, #24]
8000dce: 4a0e ldr r2, [pc, #56] @ (8000e08 <HAL_MspInit+0x44>)
8000dd0: f043 0301 orr.w r3, r3, #1
8000dd4: 6193 str r3, [r2, #24]
8000dd6: 4b0c ldr r3, [pc, #48] @ (8000e08 <HAL_MspInit+0x44>)
8000dd8: 699b ldr r3, [r3, #24]
8000dda: f003 0301 and.w r3, r3, #1
8000dde: 607b str r3, [r7, #4]
8000de0: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000de2: 4b09 ldr r3, [pc, #36] @ (8000e08 <HAL_MspInit+0x44>)
8000de4: 69db ldr r3, [r3, #28]
8000de6: 4a08 ldr r2, [pc, #32] @ (8000e08 <HAL_MspInit+0x44>)
8000de8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000dec: 61d3 str r3, [r2, #28]
8000dee: 4b06 ldr r3, [pc, #24] @ (8000e08 <HAL_MspInit+0x44>)
8000df0: 69db ldr r3, [r3, #28]
8000df2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000df6: 603b str r3, [r7, #0]
8000df8: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000dfa: bf00 nop
8000dfc: 370c adds r7, #12
8000dfe: 46bd mov sp, r7
8000e00: f85d 7b04 ldr.w r7, [sp], #4
8000e04: 4770 bx lr
8000e06: bf00 nop
8000e08: 40021000 .word 0x40021000
08000e0c <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8000e0c: b580 push {r7, lr}
8000e0e: b08e sub sp, #56 @ 0x38
8000e10: af00 add r7, sp, #0
8000e12: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000e14: f107 0324 add.w r3, r7, #36 @ 0x24
8000e18: 2200 movs r2, #0
8000e1a: 601a str r2, [r3, #0]
8000e1c: 605a str r2, [r3, #4]
8000e1e: 609a str r2, [r3, #8]
8000e20: 60da str r2, [r3, #12]
8000e22: 611a str r2, [r3, #16]
if(hadc->Instance==ADC1)
8000e24: 687b ldr r3, [r7, #4]
8000e26: 681b ldr r3, [r3, #0]
8000e28: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8000e2c: f040 808f bne.w 8000f4e <HAL_ADC_MspInit+0x142>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
HAL_RCC_ADC12_CLK_ENABLED++;
8000e30: 4b86 ldr r3, [pc, #536] @ (800104c <HAL_ADC_MspInit+0x240>)
8000e32: 681b ldr r3, [r3, #0]
8000e34: 3301 adds r3, #1
8000e36: 4a85 ldr r2, [pc, #532] @ (800104c <HAL_ADC_MspInit+0x240>)
8000e38: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
8000e3a: 4b84 ldr r3, [pc, #528] @ (800104c <HAL_ADC_MspInit+0x240>)
8000e3c: 681b ldr r3, [r3, #0]
8000e3e: 2b01 cmp r3, #1
8000e40: d10b bne.n 8000e5a <HAL_ADC_MspInit+0x4e>
__HAL_RCC_ADC12_CLK_ENABLE();
8000e42: 4b83 ldr r3, [pc, #524] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e44: 695b ldr r3, [r3, #20]
8000e46: 4a82 ldr r2, [pc, #520] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e48: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000e4c: 6153 str r3, [r2, #20]
8000e4e: 4b80 ldr r3, [pc, #512] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e50: 695b ldr r3, [r3, #20]
8000e52: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000e56: 623b str r3, [r7, #32]
8000e58: 6a3b ldr r3, [r7, #32]
}
__HAL_RCC_GPIOC_CLK_ENABLE();
8000e5a: 4b7d ldr r3, [pc, #500] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e5c: 695b ldr r3, [r3, #20]
8000e5e: 4a7c ldr r2, [pc, #496] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e60: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8000e64: 6153 str r3, [r2, #20]
8000e66: 4b7a ldr r3, [pc, #488] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e68: 695b ldr r3, [r3, #20]
8000e6a: f403 2300 and.w r3, r3, #524288 @ 0x80000
8000e6e: 61fb str r3, [r7, #28]
8000e70: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000e72: 4b77 ldr r3, [pc, #476] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e74: 695b ldr r3, [r3, #20]
8000e76: 4a76 ldr r2, [pc, #472] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e78: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000e7c: 6153 str r3, [r2, #20]
8000e7e: 4b74 ldr r3, [pc, #464] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e80: 695b ldr r3, [r3, #20]
8000e82: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000e86: 61bb str r3, [r7, #24]
8000e88: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOF_CLK_ENABLE();
8000e8a: 4b71 ldr r3, [pc, #452] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e8c: 695b ldr r3, [r3, #20]
8000e8e: 4a70 ldr r2, [pc, #448] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e90: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8000e94: 6153 str r3, [r2, #20]
8000e96: 4b6e ldr r3, [pc, #440] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000e98: 695b ldr r3, [r3, #20]
8000e9a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8000e9e: 617b str r3, [r7, #20]
8000ea0: 697b ldr r3, [r7, #20]
PA1 ------> ADC1_IN2
PA2 ------> ADC1_IN3
PA3 ------> ADC1_IN4
PF4 ------> ADC1_IN5
*/
GPIO_InitStruct.Pin = LVMS_Vsense_Pin|IS10_Pin|IS6_Pin;
8000ea2: 2307 movs r3, #7
8000ea4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000ea6: 2303 movs r3, #3
8000ea8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000eaa: 2300 movs r3, #0
8000eac: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000eae: f107 0324 add.w r3, r7, #36 @ 0x24
8000eb2: 4619 mov r1, r3
8000eb4: 4867 ldr r0, [pc, #412] @ (8001054 <HAL_ADC_MspInit+0x248>)
8000eb6: f002 fb13 bl 80034e0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = ASMS_Vsense_Pin|IS1_Pin|IS2_Pin|IS9_Pin;
8000eba: 230f movs r3, #15
8000ebc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000ebe: 2303 movs r3, #3
8000ec0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ec2: 2300 movs r3, #0
8000ec4: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000ec6: f107 0324 add.w r3, r7, #36 @ 0x24
8000eca: 4619 mov r1, r3
8000ecc: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000ed0: f002 fb06 bl 80034e0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = IS11_Pin;
8000ed4: 2310 movs r3, #16
8000ed6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000ed8: 2303 movs r3, #3
8000eda: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000edc: 2300 movs r3, #0
8000ede: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(IS11_GPIO_Port, &GPIO_InitStruct);
8000ee0: f107 0324 add.w r3, r7, #36 @ 0x24
8000ee4: 4619 mov r1, r3
8000ee6: 485c ldr r0, [pc, #368] @ (8001058 <HAL_ADC_MspInit+0x24c>)
8000ee8: f002 fafa bl 80034e0 <HAL_GPIO_Init>
/* ADC1 DMA Init */
/* ADC1 Init */
hdma_adc1.Instance = DMA1_Channel1;
8000eec: 4b5b ldr r3, [pc, #364] @ (800105c <HAL_ADC_MspInit+0x250>)
8000eee: 4a5c ldr r2, [pc, #368] @ (8001060 <HAL_ADC_MspInit+0x254>)
8000ef0: 601a str r2, [r3, #0]
hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
8000ef2: 4b5a ldr r3, [pc, #360] @ (800105c <HAL_ADC_MspInit+0x250>)
8000ef4: 2200 movs r2, #0
8000ef6: 605a str r2, [r3, #4]
hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
8000ef8: 4b58 ldr r3, [pc, #352] @ (800105c <HAL_ADC_MspInit+0x250>)
8000efa: 2200 movs r2, #0
8000efc: 609a str r2, [r3, #8]
hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
8000efe: 4b57 ldr r3, [pc, #348] @ (800105c <HAL_ADC_MspInit+0x250>)
8000f00: 2280 movs r2, #128 @ 0x80
8000f02: 60da str r2, [r3, #12]
hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
8000f04: 4b55 ldr r3, [pc, #340] @ (800105c <HAL_ADC_MspInit+0x250>)
8000f06: f44f 7280 mov.w r2, #256 @ 0x100
8000f0a: 611a str r2, [r3, #16]
hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
8000f0c: 4b53 ldr r3, [pc, #332] @ (800105c <HAL_ADC_MspInit+0x250>)
8000f0e: f44f 6280 mov.w r2, #1024 @ 0x400
8000f12: 615a str r2, [r3, #20]
hdma_adc1.Init.Mode = DMA_CIRCULAR;
8000f14: 4b51 ldr r3, [pc, #324] @ (800105c <HAL_ADC_MspInit+0x250>)
8000f16: 2220 movs r2, #32
8000f18: 619a str r2, [r3, #24]
hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
8000f1a: 4b50 ldr r3, [pc, #320] @ (800105c <HAL_ADC_MspInit+0x250>)
8000f1c: 2200 movs r2, #0
8000f1e: 61da str r2, [r3, #28]
if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
8000f20: 484e ldr r0, [pc, #312] @ (800105c <HAL_ADC_MspInit+0x250>)
8000f22: f002 f9b6 bl 8003292 <HAL_DMA_Init>
8000f26: 4603 mov r3, r0
8000f28: 2b00 cmp r3, #0
8000f2a: d001 beq.n 8000f30 <HAL_ADC_MspInit+0x124>
{
Error_Handler();
8000f2c: f7ff ff44 bl 8000db8 <Error_Handler>
}
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
8000f30: 687b ldr r3, [r7, #4]
8000f32: 4a4a ldr r2, [pc, #296] @ (800105c <HAL_ADC_MspInit+0x250>)
8000f34: 639a str r2, [r3, #56] @ 0x38
8000f36: 4a49 ldr r2, [pc, #292] @ (800105c <HAL_ADC_MspInit+0x250>)
8000f38: 687b ldr r3, [r7, #4]
8000f3a: 6253 str r3, [r2, #36] @ 0x24
/* ADC1 interrupt Init */
HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
8000f3c: 2200 movs r2, #0
8000f3e: 2100 movs r1, #0
8000f40: 2012 movs r0, #18
8000f42: f002 f970 bl 8003226 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
8000f46: 2012 movs r0, #18
8000f48: f002 f989 bl 800325e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
8000f4c: e07a b.n 8001044 <HAL_ADC_MspInit+0x238>
else if(hadc->Instance==ADC2)
8000f4e: 687b ldr r3, [r7, #4]
8000f50: 681b ldr r3, [r3, #0]
8000f52: 4a44 ldr r2, [pc, #272] @ (8001064 <HAL_ADC_MspInit+0x258>)
8000f54: 4293 cmp r3, r2
8000f56: d175 bne.n 8001044 <HAL_ADC_MspInit+0x238>
HAL_RCC_ADC12_CLK_ENABLED++;
8000f58: 4b3c ldr r3, [pc, #240] @ (800104c <HAL_ADC_MspInit+0x240>)
8000f5a: 681b ldr r3, [r3, #0]
8000f5c: 3301 adds r3, #1
8000f5e: 4a3b ldr r2, [pc, #236] @ (800104c <HAL_ADC_MspInit+0x240>)
8000f60: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
8000f62: 4b3a ldr r3, [pc, #232] @ (800104c <HAL_ADC_MspInit+0x240>)
8000f64: 681b ldr r3, [r3, #0]
8000f66: 2b01 cmp r3, #1
8000f68: d10b bne.n 8000f82 <HAL_ADC_MspInit+0x176>
__HAL_RCC_ADC12_CLK_ENABLE();
8000f6a: 4b39 ldr r3, [pc, #228] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000f6c: 695b ldr r3, [r3, #20]
8000f6e: 4a38 ldr r2, [pc, #224] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000f70: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000f74: 6153 str r3, [r2, #20]
8000f76: 4b36 ldr r3, [pc, #216] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000f78: 695b ldr r3, [r3, #20]
8000f7a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000f7e: 613b str r3, [r7, #16]
8000f80: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000f82: 4b33 ldr r3, [pc, #204] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000f84: 695b ldr r3, [r3, #20]
8000f86: 4a32 ldr r2, [pc, #200] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000f88: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8000f8c: 6153 str r3, [r2, #20]
8000f8e: 4b30 ldr r3, [pc, #192] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000f90: 695b ldr r3, [r3, #20]
8000f92: f403 2300 and.w r3, r3, #524288 @ 0x80000
8000f96: 60fb str r3, [r7, #12]
8000f98: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000f9a: 4b2d ldr r3, [pc, #180] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000f9c: 695b ldr r3, [r3, #20]
8000f9e: 4a2c ldr r2, [pc, #176] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000fa0: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000fa4: 6153 str r3, [r2, #20]
8000fa6: 4b2a ldr r3, [pc, #168] @ (8001050 <HAL_ADC_MspInit+0x244>)
8000fa8: 695b ldr r3, [r3, #20]
8000faa: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000fae: 60bb str r3, [r7, #8]
8000fb0: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = IS7_Pin|PC_Read_Pin;
8000fb2: 2318 movs r3, #24
8000fb4: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000fb6: 2303 movs r3, #3
8000fb8: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fba: 2300 movs r3, #0
8000fbc: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000fbe: f107 0324 add.w r3, r7, #36 @ 0x24
8000fc2: 4619 mov r1, r3
8000fc4: 4823 ldr r0, [pc, #140] @ (8001054 <HAL_ADC_MspInit+0x248>)
8000fc6: f002 fa8b bl 80034e0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = IS3_Pin|IS8_Pin|IS4_Pin|IS5_Pin;
8000fca: 23f0 movs r3, #240 @ 0xf0
8000fcc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000fce: 2303 movs r3, #3
8000fd0: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fd2: 2300 movs r3, #0
8000fd4: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000fd6: f107 0324 add.w r3, r7, #36 @ 0x24
8000fda: 4619 mov r1, r3
8000fdc: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000fe0: f002 fa7e bl 80034e0 <HAL_GPIO_Init>
hdma_adc2.Instance = DMA2_Channel1;
8000fe4: 4b20 ldr r3, [pc, #128] @ (8001068 <HAL_ADC_MspInit+0x25c>)
8000fe6: 4a21 ldr r2, [pc, #132] @ (800106c <HAL_ADC_MspInit+0x260>)
8000fe8: 601a str r2, [r3, #0]
hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY;
8000fea: 4b1f ldr r3, [pc, #124] @ (8001068 <HAL_ADC_MspInit+0x25c>)
8000fec: 2200 movs r2, #0
8000fee: 605a str r2, [r3, #4]
hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE;
8000ff0: 4b1d ldr r3, [pc, #116] @ (8001068 <HAL_ADC_MspInit+0x25c>)
8000ff2: 2200 movs r2, #0
8000ff4: 609a str r2, [r3, #8]
hdma_adc2.Init.MemInc = DMA_MINC_ENABLE;
8000ff6: 4b1c ldr r3, [pc, #112] @ (8001068 <HAL_ADC_MspInit+0x25c>)
8000ff8: 2280 movs r2, #128 @ 0x80
8000ffa: 60da str r2, [r3, #12]
hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
8000ffc: 4b1a ldr r3, [pc, #104] @ (8001068 <HAL_ADC_MspInit+0x25c>)
8000ffe: f44f 7280 mov.w r2, #256 @ 0x100
8001002: 611a str r2, [r3, #16]
hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
8001004: 4b18 ldr r3, [pc, #96] @ (8001068 <HAL_ADC_MspInit+0x25c>)
8001006: f44f 6280 mov.w r2, #1024 @ 0x400
800100a: 615a str r2, [r3, #20]
hdma_adc2.Init.Mode = DMA_CIRCULAR;
800100c: 4b16 ldr r3, [pc, #88] @ (8001068 <HAL_ADC_MspInit+0x25c>)
800100e: 2220 movs r2, #32
8001010: 619a str r2, [r3, #24]
hdma_adc2.Init.Priority = DMA_PRIORITY_LOW;
8001012: 4b15 ldr r3, [pc, #84] @ (8001068 <HAL_ADC_MspInit+0x25c>)
8001014: 2200 movs r2, #0
8001016: 61da str r2, [r3, #28]
if (HAL_DMA_Init(&hdma_adc2) != HAL_OK)
8001018: 4813 ldr r0, [pc, #76] @ (8001068 <HAL_ADC_MspInit+0x25c>)
800101a: f002 f93a bl 8003292 <HAL_DMA_Init>
800101e: 4603 mov r3, r0
8001020: 2b00 cmp r3, #0
8001022: d001 beq.n 8001028 <HAL_ADC_MspInit+0x21c>
Error_Handler();
8001024: f7ff fec8 bl 8000db8 <Error_Handler>
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2);
8001028: 687b ldr r3, [r7, #4]
800102a: 4a0f ldr r2, [pc, #60] @ (8001068 <HAL_ADC_MspInit+0x25c>)
800102c: 639a str r2, [r3, #56] @ 0x38
800102e: 4a0e ldr r2, [pc, #56] @ (8001068 <HAL_ADC_MspInit+0x25c>)
8001030: 687b ldr r3, [r7, #4]
8001032: 6253 str r3, [r2, #36] @ 0x24
HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
8001034: 2200 movs r2, #0
8001036: 2100 movs r1, #0
8001038: 2012 movs r0, #18
800103a: f002 f8f4 bl 8003226 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
800103e: 2012 movs r0, #18
8001040: f002 f90d bl 800325e <HAL_NVIC_EnableIRQ>
}
8001044: bf00 nop
8001046: 3738 adds r7, #56 @ 0x38
8001048: 46bd mov sp, r7
800104a: bd80 pop {r7, pc}
800104c: 200002b0 .word 0x200002b0
8001050: 40021000 .word 0x40021000
8001054: 48000800 .word 0x48000800
8001058: 48001400 .word 0x48001400
800105c: 2000011c .word 0x2000011c
8001060: 40020008 .word 0x40020008
8001064: 50000100 .word 0x50000100
8001068: 20000160 .word 0x20000160
800106c: 40020408 .word 0x40020408
08001070 <HAL_CAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
8001070: b580 push {r7, lr}
8001072: b08a sub sp, #40 @ 0x28
8001074: af00 add r7, sp, #0
8001076: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001078: f107 0314 add.w r3, r7, #20
800107c: 2200 movs r2, #0
800107e: 601a str r2, [r3, #0]
8001080: 605a str r2, [r3, #4]
8001082: 609a str r2, [r3, #8]
8001084: 60da str r2, [r3, #12]
8001086: 611a str r2, [r3, #16]
if(hcan->Instance==CAN)
8001088: 687b ldr r3, [r7, #4]
800108a: 681b ldr r3, [r3, #0]
800108c: 4a20 ldr r2, [pc, #128] @ (8001110 <HAL_CAN_MspInit+0xa0>)
800108e: 4293 cmp r3, r2
8001090: d139 bne.n 8001106 <HAL_CAN_MspInit+0x96>
{
/* USER CODE BEGIN CAN_MspInit 0 */
/* USER CODE END CAN_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
8001092: 4b20 ldr r3, [pc, #128] @ (8001114 <HAL_CAN_MspInit+0xa4>)
8001094: 69db ldr r3, [r3, #28]
8001096: 4a1f ldr r2, [pc, #124] @ (8001114 <HAL_CAN_MspInit+0xa4>)
8001098: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
800109c: 61d3 str r3, [r2, #28]
800109e: 4b1d ldr r3, [pc, #116] @ (8001114 <HAL_CAN_MspInit+0xa4>)
80010a0: 69db ldr r3, [r3, #28]
80010a2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80010a6: 613b str r3, [r7, #16]
80010a8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80010aa: 4b1a ldr r3, [pc, #104] @ (8001114 <HAL_CAN_MspInit+0xa4>)
80010ac: 695b ldr r3, [r3, #20]
80010ae: 4a19 ldr r2, [pc, #100] @ (8001114 <HAL_CAN_MspInit+0xa4>)
80010b0: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80010b4: 6153 str r3, [r2, #20]
80010b6: 4b17 ldr r3, [pc, #92] @ (8001114 <HAL_CAN_MspInit+0xa4>)
80010b8: 695b ldr r3, [r3, #20]
80010ba: f403 3300 and.w r3, r3, #131072 @ 0x20000
80010be: 60fb str r3, [r7, #12]
80010c0: 68fb ldr r3, [r7, #12]
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
80010c2: f44f 53c0 mov.w r3, #6144 @ 0x1800
80010c6: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010c8: 2302 movs r3, #2
80010ca: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010cc: 2300 movs r3, #0
80010ce: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80010d0: 2303 movs r3, #3
80010d2: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
80010d4: 2309 movs r3, #9
80010d6: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80010d8: f107 0314 add.w r3, r7, #20
80010dc: 4619 mov r1, r3
80010de: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80010e2: f002 f9fd bl 80034e0 <HAL_GPIO_Init>
/* CAN interrupt Init */
HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0);
80010e6: 2200 movs r2, #0
80010e8: 2100 movs r1, #0
80010ea: 2014 movs r0, #20
80010ec: f002 f89b bl 8003226 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
80010f0: 2014 movs r0, #20
80010f2: f002 f8b4 bl 800325e <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
80010f6: 2200 movs r2, #0
80010f8: 2100 movs r1, #0
80010fa: 2015 movs r0, #21
80010fc: f002 f893 bl 8003226 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
8001100: 2015 movs r0, #21
8001102: f002 f8ac bl 800325e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN CAN_MspInit 1 */
/* USER CODE END CAN_MspInit 1 */
}
}
8001106: bf00 nop
8001108: 3728 adds r7, #40 @ 0x28
800110a: 46bd mov sp, r7
800110c: bd80 pop {r7, pc}
800110e: bf00 nop
8001110: 40006400 .word 0x40006400
8001114: 40021000 .word 0x40021000
08001118 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001118: b580 push {r7, lr}
800111a: b084 sub sp, #16
800111c: af00 add r7, sp, #0
800111e: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM6)
8001120: 687b ldr r3, [r7, #4]
8001122: 681b ldr r3, [r3, #0]
8001124: 4a0d ldr r2, [pc, #52] @ (800115c <HAL_TIM_Base_MspInit+0x44>)
8001126: 4293 cmp r3, r2
8001128: d113 bne.n 8001152 <HAL_TIM_Base_MspInit+0x3a>
{
/* USER CODE BEGIN TIM6_MspInit 0 */
/* USER CODE END TIM6_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM6_CLK_ENABLE();
800112a: 4b0d ldr r3, [pc, #52] @ (8001160 <HAL_TIM_Base_MspInit+0x48>)
800112c: 69db ldr r3, [r3, #28]
800112e: 4a0c ldr r2, [pc, #48] @ (8001160 <HAL_TIM_Base_MspInit+0x48>)
8001130: f043 0310 orr.w r3, r3, #16
8001134: 61d3 str r3, [r2, #28]
8001136: 4b0a ldr r3, [pc, #40] @ (8001160 <HAL_TIM_Base_MspInit+0x48>)
8001138: 69db ldr r3, [r3, #28]
800113a: f003 0310 and.w r3, r3, #16
800113e: 60fb str r3, [r7, #12]
8001140: 68fb ldr r3, [r7, #12]
/* TIM6 interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
8001142: 2200 movs r2, #0
8001144: 2100 movs r1, #0
8001146: 2036 movs r0, #54 @ 0x36
8001148: f002 f86d bl 8003226 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
800114c: 2036 movs r0, #54 @ 0x36
800114e: f002 f886 bl 800325e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM6_MspInit 1 */
/* USER CODE END TIM6_MspInit 1 */
}
}
8001152: bf00 nop
8001154: 3710 adds r7, #16
8001156: 46bd mov sp, r7
8001158: bd80 pop {r7, pc}
800115a: bf00 nop
800115c: 40001000 .word 0x40001000
8001160: 40021000 .word 0x40021000
08001164 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001164: b580 push {r7, lr}
8001166: b08a sub sp, #40 @ 0x28
8001168: af00 add r7, sp, #0
800116a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800116c: f107 0314 add.w r3, r7, #20
8001170: 2200 movs r2, #0
8001172: 601a str r2, [r3, #0]
8001174: 605a str r2, [r3, #4]
8001176: 609a str r2, [r3, #8]
8001178: 60da str r2, [r3, #12]
800117a: 611a str r2, [r3, #16]
if(huart->Instance==UART4)
800117c: 687b ldr r3, [r7, #4]
800117e: 681b ldr r3, [r3, #0]
8001180: 4a17 ldr r2, [pc, #92] @ (80011e0 <HAL_UART_MspInit+0x7c>)
8001182: 4293 cmp r3, r2
8001184: d128 bne.n 80011d8 <HAL_UART_MspInit+0x74>
{
/* USER CODE BEGIN UART4_MspInit 0 */
/* USER CODE END UART4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_UART4_CLK_ENABLE();
8001186: 4b17 ldr r3, [pc, #92] @ (80011e4 <HAL_UART_MspInit+0x80>)
8001188: 69db ldr r3, [r3, #28]
800118a: 4a16 ldr r2, [pc, #88] @ (80011e4 <HAL_UART_MspInit+0x80>)
800118c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8001190: 61d3 str r3, [r2, #28]
8001192: 4b14 ldr r3, [pc, #80] @ (80011e4 <HAL_UART_MspInit+0x80>)
8001194: 69db ldr r3, [r3, #28]
8001196: f403 2300 and.w r3, r3, #524288 @ 0x80000
800119a: 613b str r3, [r7, #16]
800119c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
800119e: 4b11 ldr r3, [pc, #68] @ (80011e4 <HAL_UART_MspInit+0x80>)
80011a0: 695b ldr r3, [r3, #20]
80011a2: 4a10 ldr r2, [pc, #64] @ (80011e4 <HAL_UART_MspInit+0x80>)
80011a4: f443 2300 orr.w r3, r3, #524288 @ 0x80000
80011a8: 6153 str r3, [r2, #20]
80011aa: 4b0e ldr r3, [pc, #56] @ (80011e4 <HAL_UART_MspInit+0x80>)
80011ac: 695b ldr r3, [r3, #20]
80011ae: f403 2300 and.w r3, r3, #524288 @ 0x80000
80011b2: 60fb str r3, [r7, #12]
80011b4: 68fb ldr r3, [r7, #12]
/**UART4 GPIO Configuration
PC10 ------> UART4_TX
PC11 ------> UART4_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
80011b6: f44f 6340 mov.w r3, #3072 @ 0xc00
80011ba: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80011bc: 2302 movs r3, #2
80011be: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011c0: 2300 movs r3, #0
80011c2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80011c4: 2303 movs r3, #3
80011c6: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_UART4;
80011c8: 2305 movs r3, #5
80011ca: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
80011cc: f107 0314 add.w r3, r7, #20
80011d0: 4619 mov r1, r3
80011d2: 4805 ldr r0, [pc, #20] @ (80011e8 <HAL_UART_MspInit+0x84>)
80011d4: f002 f984 bl 80034e0 <HAL_GPIO_Init>
/* USER CODE BEGIN UART4_MspInit 1 */
/* USER CODE END UART4_MspInit 1 */
}
}
80011d8: bf00 nop
80011da: 3728 adds r7, #40 @ 0x28
80011dc: 46bd mov sp, r7
80011de: bd80 pop {r7, pc}
80011e0: 40004c00 .word 0x40004c00
80011e4: 40021000 .word 0x40021000
80011e8: 48000800 .word 0x48000800
080011ec <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80011ec: b480 push {r7}
80011ee: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80011f0: bf00 nop
80011f2: e7fd b.n 80011f0 <NMI_Handler+0x4>
080011f4 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80011f4: b480 push {r7}
80011f6: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80011f8: bf00 nop
80011fa: e7fd b.n 80011f8 <HardFault_Handler+0x4>
080011fc <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80011fc: b480 push {r7}
80011fe: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001200: bf00 nop
8001202: e7fd b.n 8001200 <MemManage_Handler+0x4>
08001204 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001204: b480 push {r7}
8001206: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001208: bf00 nop
800120a: e7fd b.n 8001208 <BusFault_Handler+0x4>
0800120c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
800120c: b480 push {r7}
800120e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001210: bf00 nop
8001212: e7fd b.n 8001210 <UsageFault_Handler+0x4>
08001214 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001214: b480 push {r7}
8001216: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001218: bf00 nop
800121a: 46bd mov sp, r7
800121c: f85d 7b04 ldr.w r7, [sp], #4
8001220: 4770 bx lr
08001222 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001222: b480 push {r7}
8001224: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001226: bf00 nop
8001228: 46bd mov sp, r7
800122a: f85d 7b04 ldr.w r7, [sp], #4
800122e: 4770 bx lr
08001230 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001230: b480 push {r7}
8001232: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001234: bf00 nop
8001236: 46bd mov sp, r7
8001238: f85d 7b04 ldr.w r7, [sp], #4
800123c: 4770 bx lr
0800123e <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
800123e: b580 push {r7, lr}
8001240: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001242: f000 f8c5 bl 80013d0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001246: bf00 nop
8001248: bd80 pop {r7, pc}
...
0800124c <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel1 global interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
800124c: b580 push {r7, lr}
800124e: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc1);
8001250: 4802 ldr r0, [pc, #8] @ (800125c <DMA1_Channel1_IRQHandler+0x10>)
8001252: f002 f865 bl 8003320 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
8001256: bf00 nop
8001258: bd80 pop {r7, pc}
800125a: bf00 nop
800125c: 2000011c .word 0x2000011c
08001260 <ADC1_2_IRQHandler>:
/**
* @brief This function handles ADC1 and ADC2 interrupts.
*/
void ADC1_2_IRQHandler(void)
{
8001260: b580 push {r7, lr}
8001262: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_2_IRQn 0 */
/* USER CODE END ADC1_2_IRQn 0 */
HAL_ADC_IRQHandler(&hadc1);
8001264: 4803 ldr r0, [pc, #12] @ (8001274 <ADC1_2_IRQHandler+0x14>)
8001266: f000 faa7 bl 80017b8 <HAL_ADC_IRQHandler>
HAL_ADC_IRQHandler(&hadc2);
800126a: 4803 ldr r0, [pc, #12] @ (8001278 <ADC1_2_IRQHandler+0x18>)
800126c: f000 faa4 bl 80017b8 <HAL_ADC_IRQHandler>
/* USER CODE BEGIN ADC1_2_IRQn 1 */
/* USER CODE END ADC1_2_IRQn 1 */
}
8001270: bf00 nop
8001272: bd80 pop {r7, pc}
8001274: 2000007c .word 0x2000007c
8001278: 200000cc .word 0x200000cc
0800127c <USB_LP_CAN_RX0_IRQHandler>:
/**
* @brief This function handles USB low priority or CAN_RX0 interrupts.
*/
void USB_LP_CAN_RX0_IRQHandler(void)
{
800127c: b580 push {r7, lr}
800127e: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN_RX0_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
8001280: 4802 ldr r0, [pc, #8] @ (800128c <USB_LP_CAN_RX0_IRQHandler+0x10>)
8001282: f001 fcc6 bl 8002c12 <HAL_CAN_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN_RX0_IRQn 1 */
}
8001286: bf00 nop
8001288: bd80 pop {r7, pc}
800128a: bf00 nop
800128c: 200001a4 .word 0x200001a4
08001290 <CAN_RX1_IRQHandler>:
/**
* @brief This function handles CAN RX1 interrupt.
*/
void CAN_RX1_IRQHandler(void)
{
8001290: b580 push {r7, lr}
8001292: af00 add r7, sp, #0
/* USER CODE BEGIN CAN_RX1_IRQn 0 */
/* USER CODE END CAN_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
8001294: 4802 ldr r0, [pc, #8] @ (80012a0 <CAN_RX1_IRQHandler+0x10>)
8001296: f001 fcbc bl 8002c12 <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN_RX1_IRQn 1 */
/* USER CODE END CAN_RX1_IRQn 1 */
}
800129a: bf00 nop
800129c: bd80 pop {r7, pc}
800129e: bf00 nop
80012a0: 200001a4 .word 0x200001a4
080012a4 <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles Timer 6 interrupt and DAC underrun interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
80012a4: b580 push {r7, lr}
80012a6: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
80012a8: 4802 ldr r0, [pc, #8] @ (80012b4 <TIM6_DAC_IRQHandler+0x10>)
80012aa: f003 ff0a bl 80050c2 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
80012ae: bf00 nop
80012b0: bd80 pop {r7, pc}
80012b2: bf00 nop
80012b4: 200001cc .word 0x200001cc
080012b8 <DMA2_Channel1_IRQHandler>:
/**
* @brief This function handles DMA2 channel1 global interrupt.
*/
void DMA2_Channel1_IRQHandler(void)
{
80012b8: b580 push {r7, lr}
80012ba: af00 add r7, sp, #0
/* USER CODE BEGIN DMA2_Channel1_IRQn 0 */
/* USER CODE END DMA2_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc2);
80012bc: 4802 ldr r0, [pc, #8] @ (80012c8 <DMA2_Channel1_IRQHandler+0x10>)
80012be: f002 f82f bl 8003320 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA2_Channel1_IRQn 1 */
/* USER CODE END DMA2_Channel1_IRQn 1 */
}
80012c2: bf00 nop
80012c4: bd80 pop {r7, pc}
80012c6: bf00 nop
80012c8: 20000160 .word 0x20000160
080012cc <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
80012cc: b480 push {r7}
80012ce: af00 add r7, sp, #0
/* FPU settings --------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80012d0: 4b06 ldr r3, [pc, #24] @ (80012ec <SystemInit+0x20>)
80012d2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80012d6: 4a05 ldr r2, [pc, #20] @ (80012ec <SystemInit+0x20>)
80012d8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80012dc: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80012e0: bf00 nop
80012e2: 46bd mov sp, r7
80012e4: f85d 7b04 ldr.w r7, [sp], #4
80012e8: 4770 bx lr
80012ea: bf00 nop
80012ec: e000ed00 .word 0xe000ed00
080012f0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
80012f0: f8df d034 ldr.w sp, [pc, #52] @ 8001328 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
80012f4: f7ff ffea bl 80012cc <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80012f8: 480c ldr r0, [pc, #48] @ (800132c <LoopForever+0x6>)
ldr r1, =_edata
80012fa: 490d ldr r1, [pc, #52] @ (8001330 <LoopForever+0xa>)
ldr r2, =_sidata
80012fc: 4a0d ldr r2, [pc, #52] @ (8001334 <LoopForever+0xe>)
movs r3, #0
80012fe: 2300 movs r3, #0
b LoopCopyDataInit
8001300: e002 b.n 8001308 <LoopCopyDataInit>
08001302 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001302: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001304: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001306: 3304 adds r3, #4
08001308 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001308: 18c4 adds r4, r0, r3
cmp r4, r1
800130a: 428c cmp r4, r1
bcc CopyDataInit
800130c: d3f9 bcc.n 8001302 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800130e: 4a0a ldr r2, [pc, #40] @ (8001338 <LoopForever+0x12>)
ldr r4, =_ebss
8001310: 4c0a ldr r4, [pc, #40] @ (800133c <LoopForever+0x16>)
movs r3, #0
8001312: 2300 movs r3, #0
b LoopFillZerobss
8001314: e001 b.n 800131a <LoopFillZerobss>
08001316 <FillZerobss>:
FillZerobss:
str r3, [r2]
8001316: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001318: 3204 adds r2, #4
0800131a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800131a: 42a2 cmp r2, r4
bcc FillZerobss
800131c: d3fb bcc.n 8001316 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800131e: f004 fd75 bl 8005e0c <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001322: f7ff f973 bl 800060c <main>
08001326 <LoopForever>:
LoopForever:
b LoopForever
8001326: e7fe b.n 8001326 <LoopForever>
ldr sp, =_estack /* Atollic update: set stack pointer */
8001328: 20008000 .word 0x20008000
ldr r0, =_sdata
800132c: 20000000 .word 0x20000000
ldr r1, =_edata
8001330: 2000000c .word 0x2000000c
ldr r2, =_sidata
8001334: 08005eac .word 0x08005eac
ldr r2, =_sbss
8001338: 2000000c .word 0x2000000c
ldr r4, =_ebss
800133c: 200002b8 .word 0x200002b8
08001340 <CAN_SCE_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001340: e7fe b.n 8001340 <CAN_SCE_IRQHandler>
...
08001344 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001344: b580 push {r7, lr}
8001346: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001348: 4b08 ldr r3, [pc, #32] @ (800136c <HAL_Init+0x28>)
800134a: 681b ldr r3, [r3, #0]
800134c: 4a07 ldr r2, [pc, #28] @ (800136c <HAL_Init+0x28>)
800134e: f043 0310 orr.w r3, r3, #16
8001352: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001354: 2003 movs r0, #3
8001356: f001 ff5b bl 8003210 <HAL_NVIC_SetPriorityGrouping>
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
800135a: 200f movs r0, #15
800135c: f000 f808 bl 8001370 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001360: f7ff fd30 bl 8000dc4 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8001364: 2300 movs r3, #0
}
8001366: 4618 mov r0, r3
8001368: bd80 pop {r7, pc}
800136a: bf00 nop
800136c: 40022000 .word 0x40022000
08001370 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001370: b580 push {r7, lr}
8001372: b082 sub sp, #8
8001374: af00 add r7, sp, #0
8001376: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8001378: 4b12 ldr r3, [pc, #72] @ (80013c4 <HAL_InitTick+0x54>)
800137a: 681a ldr r2, [r3, #0]
800137c: 4b12 ldr r3, [pc, #72] @ (80013c8 <HAL_InitTick+0x58>)
800137e: 781b ldrb r3, [r3, #0]
8001380: 4619 mov r1, r3
8001382: f44f 737a mov.w r3, #1000 @ 0x3e8
8001386: fbb3 f3f1 udiv r3, r3, r1
800138a: fbb2 f3f3 udiv r3, r2, r3
800138e: 4618 mov r0, r3
8001390: f001 ff73 bl 800327a <HAL_SYSTICK_Config>
8001394: 4603 mov r3, r0
8001396: 2b00 cmp r3, #0
8001398: d001 beq.n 800139e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800139a: 2301 movs r3, #1
800139c: e00e b.n 80013bc <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800139e: 687b ldr r3, [r7, #4]
80013a0: 2b0f cmp r3, #15
80013a2: d80a bhi.n 80013ba <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80013a4: 2200 movs r2, #0
80013a6: 6879 ldr r1, [r7, #4]
80013a8: f04f 30ff mov.w r0, #4294967295
80013ac: f001 ff3b bl 8003226 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80013b0: 4a06 ldr r2, [pc, #24] @ (80013cc <HAL_InitTick+0x5c>)
80013b2: 687b ldr r3, [r7, #4]
80013b4: 6013 str r3, [r2, #0]
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80013b6: 2300 movs r3, #0
80013b8: e000 b.n 80013bc <HAL_InitTick+0x4c>
return HAL_ERROR;
80013ba: 2301 movs r3, #1
}
80013bc: 4618 mov r0, r3
80013be: 3708 adds r7, #8
80013c0: 46bd mov sp, r7
80013c2: bd80 pop {r7, pc}
80013c4: 20000000 .word 0x20000000
80013c8: 20000008 .word 0x20000008
80013cc: 20000004 .word 0x20000004
080013d0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80013d0: b480 push {r7}
80013d2: af00 add r7, sp, #0
uwTick += uwTickFreq;
80013d4: 4b06 ldr r3, [pc, #24] @ (80013f0 <HAL_IncTick+0x20>)
80013d6: 781b ldrb r3, [r3, #0]
80013d8: 461a mov r2, r3
80013da: 4b06 ldr r3, [pc, #24] @ (80013f4 <HAL_IncTick+0x24>)
80013dc: 681b ldr r3, [r3, #0]
80013de: 4413 add r3, r2
80013e0: 4a04 ldr r2, [pc, #16] @ (80013f4 <HAL_IncTick+0x24>)
80013e2: 6013 str r3, [r2, #0]
}
80013e4: bf00 nop
80013e6: 46bd mov sp, r7
80013e8: f85d 7b04 ldr.w r7, [sp], #4
80013ec: 4770 bx lr
80013ee: bf00 nop
80013f0: 20000008 .word 0x20000008
80013f4: 200002b4 .word 0x200002b4
080013f8 <HAL_GetTick>:
* @note The function is declared as __Weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80013f8: b480 push {r7}
80013fa: af00 add r7, sp, #0
return uwTick;
80013fc: 4b03 ldr r3, [pc, #12] @ (800140c <HAL_GetTick+0x14>)
80013fe: 681b ldr r3, [r3, #0]
}
8001400: 4618 mov r0, r3
8001402: 46bd mov sp, r7
8001404: f85d 7b04 ldr.w r7, [sp], #4
8001408: 4770 bx lr
800140a: bf00 nop
800140c: 200002b4 .word 0x200002b4
08001410 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001410: b580 push {r7, lr}
8001412: b084 sub sp, #16
8001414: af00 add r7, sp, #0
8001416: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001418: f7ff ffee bl 80013f8 <HAL_GetTick>
800141c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
800141e: 687b ldr r3, [r7, #4]
8001420: 60fb str r3, [r7, #12]
/* Add freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8001422: 68fb ldr r3, [r7, #12]
8001424: f1b3 3fff cmp.w r3, #4294967295
8001428: d005 beq.n 8001436 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
800142a: 4b0a ldr r3, [pc, #40] @ (8001454 <HAL_Delay+0x44>)
800142c: 781b ldrb r3, [r3, #0]
800142e: 461a mov r2, r3
8001430: 68fb ldr r3, [r7, #12]
8001432: 4413 add r3, r2
8001434: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8001436: bf00 nop
8001438: f7ff ffde bl 80013f8 <HAL_GetTick>
800143c: 4602 mov r2, r0
800143e: 68bb ldr r3, [r7, #8]
8001440: 1ad3 subs r3, r2, r3
8001442: 68fa ldr r2, [r7, #12]
8001444: 429a cmp r2, r3
8001446: d8f7 bhi.n 8001438 <HAL_Delay+0x28>
{
}
}
8001448: bf00 nop
800144a: bf00 nop
800144c: 3710 adds r7, #16
800144e: 46bd mov sp, r7
8001450: bd80 pop {r7, pc}
8001452: bf00 nop
8001454: 20000008 .word 0x20000008
08001458 <HAL_ADC_ConvCpltCallback>:
* @brief Conversion complete callback in non blocking mode
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
8001458: b480 push {r7}
800145a: b083 sub sp, #12
800145c: af00 add r7, sp, #0
800145e: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvCpltCallback must be implemented in the user file.
*/
}
8001460: bf00 nop
8001462: 370c adds r7, #12
8001464: 46bd mov sp, r7
8001466: f85d 7b04 ldr.w r7, [sp], #4
800146a: 4770 bx lr
0800146c <HAL_ADC_LevelOutOfWindowCallback>:
* @brief Analog watchdog callback in non blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
{
800146c: b480 push {r7}
800146e: b083 sub sp, #12
8001470: af00 add r7, sp, #0
8001472: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
*/
}
8001474: bf00 nop
8001476: 370c adds r7, #12
8001478: 46bd mov sp, r7
800147a: f85d 7b04 ldr.w r7, [sp], #4
800147e: 4770 bx lr
08001480 <HAL_ADC_ErrorCallback>:
* (ADC conversion with interruption or transfer by DMA)
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
8001480: b480 push {r7}
8001482: b083 sub sp, #12
8001484: af00 add r7, sp, #0
8001486: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
8001488: bf00 nop
800148a: 370c adds r7, #12
800148c: 46bd mov sp, r7
800148e: f85d 7b04 ldr.w r7, [sp], #4
8001492: 4770 bx lr
08001494 <HAL_ADC_Init>:
* without disabling the other ADCs sharing the same common group.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8001494: b580 push {r7, lr}
8001496: b09a sub sp, #104 @ 0x68
8001498: af00 add r7, sp, #0
800149a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800149c: 2300 movs r3, #0
800149e: f887 3067 strb.w r3, [r7, #103] @ 0x67
ADC_Common_TypeDef *tmpADC_Common;
ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
uint32_t tmpCFGR = 0U;
80014a2: 2300 movs r3, #0
80014a4: 663b str r3, [r7, #96] @ 0x60
__IO uint32_t wait_loop_index = 0U;
80014a6: 2300 movs r3, #0
80014a8: 60bb str r3, [r7, #8]
/* Check ADC handle */
if(hadc == NULL)
80014aa: 687b ldr r3, [r7, #4]
80014ac: 2b00 cmp r3, #0
80014ae: d101 bne.n 80014b4 <HAL_ADC_Init+0x20>
{
return HAL_ERROR;
80014b0: 2301 movs r3, #1
80014b2: e172 b.n 800179a <HAL_ADC_Init+0x306>
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
80014b4: 687b ldr r3, [r7, #4]
80014b6: 691b ldr r3, [r3, #16]
80014b8: 2b00 cmp r3, #0
assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
}
}
/* Configuration of ADC core parameters and ADC MSP related parameters */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
80014ba: 687b ldr r3, [r7, #4]
80014bc: 6c1b ldr r3, [r3, #64] @ 0x40
80014be: f003 0310 and.w r3, r3, #16
80014c2: 2b00 cmp r3, #0
80014c4: d176 bne.n 80015b4 <HAL_ADC_Init+0x120>
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
/* - ADC voltage regulator enable */
if (hadc->State == HAL_ADC_STATE_RESET)
80014c6: 687b ldr r3, [r7, #4]
80014c8: 6c1b ldr r3, [r3, #64] @ 0x40
80014ca: 2b00 cmp r3, #0
80014cc: d152 bne.n 8001574 <HAL_ADC_Init+0xe0>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
80014ce: 687b ldr r3, [r7, #4]
80014d0: 2200 movs r2, #0
80014d2: 645a str r2, [r3, #68] @ 0x44
/* Initialize HAL ADC API internal variables */
hadc->InjectionConfig.ChannelCount = 0U;
80014d4: 687b ldr r3, [r7, #4]
80014d6: 2200 movs r2, #0
80014d8: 64da str r2, [r3, #76] @ 0x4c
hadc->InjectionConfig.ContextQueue = 0U;
80014da: 687b ldr r3, [r7, #4]
80014dc: 2200 movs r2, #0
80014de: 649a str r2, [r3, #72] @ 0x48
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
80014e0: 687b ldr r3, [r7, #4]
80014e2: 2200 movs r2, #0
80014e4: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80014e8: 6878 ldr r0, [r7, #4]
80014ea: f7ff fc8f bl 8000e0c <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Enable voltage regulator (if disabled at this step) */
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
80014ee: 687b ldr r3, [r7, #4]
80014f0: 681b ldr r3, [r3, #0]
80014f2: 689b ldr r3, [r3, #8]
80014f4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80014f8: 2b00 cmp r3, #0
80014fa: d13b bne.n 8001574 <HAL_ADC_Init+0xe0>
/* enabling the ADC. This temporization must be implemented by */
/* software and is equal to 10 us in the worst case */
/* process/temperature/power supply. */
/* Disable the ADC (if not already disabled) */
tmp_hal_status = ADC_Disable(hadc);
80014fc: 6878 ldr r0, [r7, #4]
80014fe: f000 ff01 bl 8002304 <ADC_Disable>
8001502: 4603 mov r3, r0
8001504: f887 3067 strb.w r3, [r7, #103] @ 0x67
/* Check if ADC is effectively disabled */
/* Configuration of ADC parameters if previous preliminary actions */
/* are correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
8001508: 687b ldr r3, [r7, #4]
800150a: 6c1b ldr r3, [r3, #64] @ 0x40
800150c: f003 0310 and.w r3, r3, #16
8001510: 2b00 cmp r3, #0
8001512: d12f bne.n 8001574 <HAL_ADC_Init+0xe0>
8001514: f897 3067 ldrb.w r3, [r7, #103] @ 0x67
8001518: 2b00 cmp r3, #0
800151a: d12b bne.n 8001574 <HAL_ADC_Init+0xe0>
(tmp_hal_status == HAL_OK) )
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800151c: 687b ldr r3, [r7, #4]
800151e: 6c1b ldr r3, [r3, #64] @ 0x40
8001520: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8001524: f023 0302 bic.w r3, r3, #2
8001528: f043 0202 orr.w r2, r3, #2
800152c: 687b ldr r3, [r7, #4]
800152e: 641a str r2, [r3, #64] @ 0x40
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set the intermediate state before moving the ADC voltage */
/* regulator to state enable. */
CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
8001530: 687b ldr r3, [r7, #4]
8001532: 681b ldr r3, [r3, #0]
8001534: 689a ldr r2, [r3, #8]
8001536: 687b ldr r3, [r7, #4]
8001538: 681b ldr r3, [r3, #0]
800153a: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000
800153e: 609a str r2, [r3, #8]
/* Set ADVREGEN bits to 0x01U */
SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
8001540: 687b ldr r3, [r7, #4]
8001542: 681b ldr r3, [r3, #0]
8001544: 689a ldr r2, [r3, #8]
8001546: 687b ldr r3, [r7, #4]
8001548: 681b ldr r3, [r3, #0]
800154a: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000
800154e: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time. */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
8001550: 4b94 ldr r3, [pc, #592] @ (80017a4 <HAL_ADC_Init+0x310>)
8001552: 681b ldr r3, [r3, #0]
8001554: 4a94 ldr r2, [pc, #592] @ (80017a8 <HAL_ADC_Init+0x314>)
8001556: fba2 2303 umull r2, r3, r2, r3
800155a: 0c9a lsrs r2, r3, #18
800155c: 4613 mov r3, r2
800155e: 009b lsls r3, r3, #2
8001560: 4413 add r3, r2
8001562: 005b lsls r3, r3, #1
8001564: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
8001566: e002 b.n 800156e <HAL_ADC_Init+0xda>
{
wait_loop_index--;
8001568: 68bb ldr r3, [r7, #8]
800156a: 3b01 subs r3, #1
800156c: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
800156e: 68bb ldr r3, [r7, #8]
8001570: 2b00 cmp r3, #0
8001572: d1f9 bne.n 8001568 <HAL_ADC_Init+0xd4>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
8001574: 687b ldr r3, [r7, #4]
8001576: 681b ldr r3, [r3, #0]
8001578: 689b ldr r3, [r3, #8]
800157a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800157e: 2b00 cmp r3, #0
8001580: d007 beq.n 8001592 <HAL_ADC_Init+0xfe>
HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) )
8001582: 687b ldr r3, [r7, #4]
8001584: 681b ldr r3, [r3, #0]
8001586: 689b ldr r3, [r3, #8]
8001588: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
800158c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8001590: d110 bne.n 80015b4 <HAL_ADC_Init+0x120>
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8001592: 687b ldr r3, [r7, #4]
8001594: 6c1b ldr r3, [r3, #64] @ 0x40
8001596: f023 0312 bic.w r3, r3, #18
800159a: f043 0210 orr.w r2, r3, #16
800159e: 687b ldr r3, [r7, #4]
80015a0: 641a str r2, [r3, #64] @ 0x40
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80015a2: 687b ldr r3, [r7, #4]
80015a4: 6c5b ldr r3, [r3, #68] @ 0x44
80015a6: f043 0201 orr.w r2, r3, #1
80015aa: 687b ldr r3, [r7, #4]
80015ac: 645a str r2, [r3, #68] @ 0x44
tmp_hal_status = HAL_ERROR;
80015ae: 2301 movs r3, #1
80015b0: f887 3067 strb.w r3, [r7, #103] @ 0x67
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
80015b4: 687b ldr r3, [r7, #4]
80015b6: 6c1b ldr r3, [r3, #64] @ 0x40
80015b8: f003 0310 and.w r3, r3, #16
80015bc: 2b00 cmp r3, #0
80015be: f040 80df bne.w 8001780 <HAL_ADC_Init+0x2ec>
80015c2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67
80015c6: 2b00 cmp r3, #0
80015c8: f040 80da bne.w 8001780 <HAL_ADC_Init+0x2ec>
(tmp_hal_status == HAL_OK) &&
(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
80015cc: 687b ldr r3, [r7, #4]
80015ce: 681b ldr r3, [r3, #0]
80015d0: 689b ldr r3, [r3, #8]
80015d2: f003 0304 and.w r3, r3, #4
(tmp_hal_status == HAL_OK) &&
80015d6: 2b00 cmp r3, #0
80015d8: f040 80d2 bne.w 8001780 <HAL_ADC_Init+0x2ec>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
80015dc: 687b ldr r3, [r7, #4]
80015de: 6c1b ldr r3, [r3, #64] @ 0x40
80015e0: f423 7381 bic.w r3, r3, #258 @ 0x102
80015e4: f043 0202 orr.w r2, r3, #2
80015e8: 687b ldr r3, [r7, #4]
80015ea: 641a str r2, [r3, #64] @ 0x40
/* Configuration of common ADC parameters */
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
/* control registers) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
80015ec: 4b6f ldr r3, [pc, #444] @ (80017ac <HAL_ADC_Init+0x318>)
80015ee: 65fb str r3, [r7, #92] @ 0x5c
/* Set handle of the other ADC sharing the same common register */
ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
80015f0: 687b ldr r3, [r7, #4]
80015f2: 681b ldr r3, [r3, #0]
80015f4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80015f8: d102 bne.n 8001600 <HAL_ADC_Init+0x16c>
80015fa: 4b6d ldr r3, [pc, #436] @ (80017b0 <HAL_ADC_Init+0x31c>)
80015fc: 60fb str r3, [r7, #12]
80015fe: e002 b.n 8001606 <HAL_ADC_Init+0x172>
8001600: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8001604: 60fb str r3, [r7, #12]
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode clock configuration */
if ((ADC_IS_ENABLE(hadc) == RESET) &&
8001606: 687b ldr r3, [r7, #4]
8001608: 681b ldr r3, [r3, #0]
800160a: 689b ldr r3, [r3, #8]
800160c: f003 0303 and.w r3, r3, #3
8001610: 2b01 cmp r3, #1
8001612: d108 bne.n 8001626 <HAL_ADC_Init+0x192>
8001614: 687b ldr r3, [r7, #4]
8001616: 681b ldr r3, [r3, #0]
8001618: 681b ldr r3, [r3, #0]
800161a: f003 0301 and.w r3, r3, #1
800161e: 2b01 cmp r3, #1
8001620: d101 bne.n 8001626 <HAL_ADC_Init+0x192>
8001622: 2301 movs r3, #1
8001624: e000 b.n 8001628 <HAL_ADC_Init+0x194>
8001626: 2300 movs r3, #0
8001628: 2b00 cmp r3, #0
800162a: d11c bne.n 8001666 <HAL_ADC_Init+0x1d2>
((tmphadcSharingSameCommonRegister.Instance == NULL) ||
800162c: 68fb ldr r3, [r7, #12]
if ((ADC_IS_ENABLE(hadc) == RESET) &&
800162e: 2b00 cmp r3, #0
8001630: d010 beq.n 8001654 <HAL_ADC_Init+0x1c0>
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
8001632: 68fb ldr r3, [r7, #12]
8001634: 689b ldr r3, [r3, #8]
8001636: f003 0303 and.w r3, r3, #3
800163a: 2b01 cmp r3, #1
800163c: d107 bne.n 800164e <HAL_ADC_Init+0x1ba>
800163e: 68fb ldr r3, [r7, #12]
8001640: 681b ldr r3, [r3, #0]
8001642: f003 0301 and.w r3, r3, #1
8001646: 2b01 cmp r3, #1
8001648: d101 bne.n 800164e <HAL_ADC_Init+0x1ba>
800164a: 2301 movs r3, #1
800164c: e000 b.n 8001650 <HAL_ADC_Init+0x1bc>
800164e: 2300 movs r3, #0
((tmphadcSharingSameCommonRegister.Instance == NULL) ||
8001650: 2b00 cmp r3, #0
8001652: d108 bne.n 8001666 <HAL_ADC_Init+0x1d2>
/* into HAL_ADCEx_MultiModeConfigChannel() ) */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
MODIFY_REG(tmpADC_Common->CCR ,
8001654: 6dfb ldr r3, [r7, #92] @ 0x5c
8001656: 689b ldr r3, [r3, #8]
8001658: f423 3240 bic.w r2, r3, #196608 @ 0x30000
800165c: 687b ldr r3, [r7, #4]
800165e: 685b ldr r3, [r3, #4]
8001660: 431a orrs r2, r3
8001662: 6dfb ldr r3, [r7, #92] @ 0x5c
8001664: 609a str r2, [r3, #8]
/* - external trigger to start conversion */
/* - external trigger polarity */
/* - continuous conversion mode */
/* - overrun */
/* - discontinuous mode */
SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001666: 687b ldr r3, [r7, #4]
8001668: 7e5b ldrb r3, [r3, #25]
800166a: 035b lsls r3, r3, #13
800166c: 687a ldr r2, [r7, #4]
800166e: 6b52 ldr r2, [r2, #52] @ 0x34
8001670: 2a01 cmp r2, #1
8001672: d002 beq.n 800167a <HAL_ADC_Init+0x1e6>
8001674: f44f 5280 mov.w r2, #4096 @ 0x1000
8001678: e000 b.n 800167c <HAL_ADC_Init+0x1e8>
800167a: 2200 movs r2, #0
800167c: 431a orrs r2, r3
800167e: 687b ldr r3, [r7, #4]
8001680: 68db ldr r3, [r3, #12]
8001682: 431a orrs r2, r3
8001684: 687b ldr r3, [r7, #4]
8001686: 689b ldr r3, [r3, #8]
8001688: 4313 orrs r3, r2
800168a: 6e3a ldr r2, [r7, #96] @ 0x60
800168c: 4313 orrs r3, r2
800168e: 663b str r3, [r7, #96] @ 0x60
ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
hadc->Init.DataAlign |
hadc->Init.Resolution );
/* Enable discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8001690: 687b ldr r3, [r7, #4]
8001692: f893 3020 ldrb.w r3, [r3, #32]
8001696: 2b01 cmp r3, #1
8001698: d11b bne.n 80016d2 <HAL_ADC_Init+0x23e>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
800169a: 687b ldr r3, [r7, #4]
800169c: 7e5b ldrb r3, [r3, #25]
800169e: 2b00 cmp r3, #0
80016a0: d109 bne.n 80016b6 <HAL_ADC_Init+0x222>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmpCFGR, ADC_CFGR_DISCEN |
80016a2: 687b ldr r3, [r7, #4]
80016a4: 6a5b ldr r3, [r3, #36] @ 0x24
80016a6: 3b01 subs r3, #1
80016a8: 045a lsls r2, r3, #17
80016aa: 6e3b ldr r3, [r7, #96] @ 0x60
80016ac: 4313 orrs r3, r2
80016ae: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80016b2: 663b str r3, [r7, #96] @ 0x60
80016b4: e00d b.n 80016d2 <HAL_ADC_Init+0x23e>
/* ADC regular group discontinuous was intended to be enabled, */
/* but ADC regular group modes continuous and sequencer discontinuous */
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
80016b6: 687b ldr r3, [r7, #4]
80016b8: 6c1b ldr r3, [r3, #64] @ 0x40
80016ba: f023 0322 bic.w r3, r3, #34 @ 0x22
80016be: f043 0220 orr.w r2, r3, #32
80016c2: 687b ldr r3, [r7, #4]
80016c4: 641a str r2, [r3, #64] @ 0x40
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80016c6: 687b ldr r3, [r7, #4]
80016c8: 6c5b ldr r3, [r3, #68] @ 0x44
80016ca: f043 0201 orr.w r2, r3, #1
80016ce: 687b ldr r3, [r7, #4]
80016d0: 645a str r2, [r3, #68] @ 0x44
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
80016d2: 687b ldr r3, [r7, #4]
80016d4: 6a9b ldr r3, [r3, #40] @ 0x28
80016d6: 2b01 cmp r3, #1
80016d8: d007 beq.n 80016ea <HAL_ADC_Init+0x256>
{
SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) |
80016da: 687b ldr r3, [r7, #4]
80016dc: 6a9a ldr r2, [r3, #40] @ 0x28
80016de: 687b ldr r3, [r7, #4]
80016e0: 6adb ldr r3, [r3, #44] @ 0x2c
80016e2: 4313 orrs r3, r2
80016e4: 6e3a ldr r2, [r7, #96] @ 0x60
80016e6: 4313 orrs r3, r2
80016e8: 663b str r3, [r7, #96] @ 0x60
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular and injected groups: */
/* - DMA continuous request */
/* - LowPowerAutoWait feature */
if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
80016ea: 687b ldr r3, [r7, #4]
80016ec: 681b ldr r3, [r3, #0]
80016ee: 689b ldr r3, [r3, #8]
80016f0: f003 030c and.w r3, r3, #12
80016f4: 2b00 cmp r3, #0
80016f6: d114 bne.n 8001722 <HAL_ADC_Init+0x28e>
{
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY |
80016f8: 687b ldr r3, [r7, #4]
80016fa: 681b ldr r3, [r3, #0]
80016fc: 68db ldr r3, [r3, #12]
80016fe: 687a ldr r2, [r7, #4]
8001700: 6812 ldr r2, [r2, #0]
8001702: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8001706: f023 0302 bic.w r3, r3, #2
800170a: 60d3 str r3, [r2, #12]
ADC_CFGR_DMACFG );
SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
800170c: 687b ldr r3, [r7, #4]
800170e: 7e1b ldrb r3, [r3, #24]
8001710: 039a lsls r2, r3, #14
8001712: 687b ldr r3, [r7, #4]
8001714: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
8001718: 005b lsls r3, r3, #1
800171a: 4313 orrs r3, r2
800171c: 6e3a ldr r2, [r7, #96] @ 0x60
800171e: 4313 orrs r3, r2
8001720: 663b str r3, [r7, #96] @ 0x60
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
}
/* Update ADC configuration register with previous settings */
MODIFY_REG(hadc->Instance->CFGR,
8001722: 687b ldr r3, [r7, #4]
8001724: 681b ldr r3, [r3, #0]
8001726: 68da ldr r2, [r3, #12]
8001728: 4b22 ldr r3, [pc, #136] @ (80017b4 <HAL_ADC_Init+0x320>)
800172a: 4013 ands r3, r2
800172c: 687a ldr r2, [r7, #4]
800172e: 6812 ldr r2, [r2, #0]
8001730: 6e39 ldr r1, [r7, #96] @ 0x60
8001732: 430b orrs r3, r1
8001734: 60d3 str r3, [r2, #12]
/* Parameter "NbrOfConversion" is discarded. */
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
8001736: 687b ldr r3, [r7, #4]
8001738: 691b ldr r3, [r3, #16]
800173a: 2b01 cmp r3, #1
800173c: d10c bne.n 8001758 <HAL_ADC_Init+0x2c4>
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1 ,
800173e: 687b ldr r3, [r7, #4]
8001740: 681b ldr r3, [r3, #0]
8001742: 6b1b ldr r3, [r3, #48] @ 0x30
8001744: f023 010f bic.w r1, r3, #15
8001748: 687b ldr r3, [r7, #4]
800174a: 69db ldr r3, [r3, #28]
800174c: 1e5a subs r2, r3, #1
800174e: 687b ldr r3, [r7, #4]
8001750: 681b ldr r3, [r3, #0]
8001752: 430a orrs r2, r1
8001754: 631a str r2, [r3, #48] @ 0x30
8001756: e007 b.n 8001768 <HAL_ADC_Init+0x2d4>
ADC_SQR1_L ,
(hadc->Init.NbrOfConversion - (uint8_t)1U) );
}
else
{
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
8001758: 687b ldr r3, [r7, #4]
800175a: 681b ldr r3, [r3, #0]
800175c: 6b1a ldr r2, [r3, #48] @ 0x30
800175e: 687b ldr r3, [r7, #4]
8001760: 681b ldr r3, [r3, #0]
8001762: f022 020f bic.w r2, r2, #15
8001766: 631a str r2, [r3, #48] @ 0x30
}
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8001768: 687b ldr r3, [r7, #4]
800176a: 2200 movs r2, #0
800176c: 645a str r2, [r3, #68] @ 0x44
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
800176e: 687b ldr r3, [r7, #4]
8001770: 6c1b ldr r3, [r3, #64] @ 0x40
8001772: f023 0303 bic.w r3, r3, #3
8001776: f043 0201 orr.w r2, r3, #1
800177a: 687b ldr r3, [r7, #4]
800177c: 641a str r2, [r3, #64] @ 0x40
800177e: e00a b.n 8001796 <HAL_ADC_Init+0x302>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8001780: 687b ldr r3, [r7, #4]
8001782: 6c1b ldr r3, [r3, #64] @ 0x40
8001784: f023 0312 bic.w r3, r3, #18
8001788: f043 0210 orr.w r2, r3, #16
800178c: 687b ldr r3, [r7, #4]
800178e: 641a str r2, [r3, #64] @ 0x40
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
tmp_hal_status = HAL_ERROR;
8001790: 2301 movs r3, #1
8001792: f887 3067 strb.w r3, [r7, #103] @ 0x67
}
/* Return function status */
return tmp_hal_status;
8001796: f897 3067 ldrb.w r3, [r7, #103] @ 0x67
}
800179a: 4618 mov r0, r3
800179c: 3768 adds r7, #104 @ 0x68
800179e: 46bd mov sp, r7
80017a0: bd80 pop {r7, pc}
80017a2: bf00 nop
80017a4: 20000000 .word 0x20000000
80017a8: 431bde83 .word 0x431bde83
80017ac: 50000300 .word 0x50000300
80017b0: 50000100 .word 0x50000100
80017b4: fff0c007 .word 0xfff0c007
080017b8 <HAL_ADC_IRQHandler>:
* @brief Handles ADC interrupt request.
* @param hadc ADC handle
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
{
80017b8: b580 push {r7, lr}
80017ba: b088 sub sp, #32
80017bc: af00 add r7, sp, #0
80017be: 6078 str r0, [r7, #4]
uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */
80017c0: 2300 movs r3, #0
80017c2: 61fb str r3, [r7, #28]
ADC_Common_TypeDef *tmpADC_Common;
uint32_t tmp_cfgr = 0x0U;
80017c4: 2300 movs r3, #0
80017c6: 61bb str r3, [r7, #24]
uint32_t tmp_cfgr_jqm = 0x0U;
80017c8: 2300 movs r3, #0
80017ca: 617b str r3, [r7, #20]
uint32_t tmp_isr = hadc->Instance->ISR;
80017cc: 687b ldr r3, [r7, #4]
80017ce: 681b ldr r3, [r3, #0]
80017d0: 681b ldr r3, [r3, #0]
80017d2: 613b str r3, [r7, #16]
uint32_t tmp_ier = hadc->Instance->IER;
80017d4: 687b ldr r3, [r7, #4]
80017d6: 681b ldr r3, [r3, #0]
80017d8: 685b ldr r3, [r3, #4]
80017da: 60fb str r3, [r7, #12]
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
/* ========== Check End of Conversion flag for regular group ========== */
if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
80017dc: 693b ldr r3, [r7, #16]
80017de: f003 0304 and.w r3, r3, #4
80017e2: 2b00 cmp r3, #0
80017e4: d004 beq.n 80017f0 <HAL_ADC_IRQHandler+0x38>
80017e6: 68fb ldr r3, [r7, #12]
80017e8: f003 0304 and.w r3, r3, #4
80017ec: 2b00 cmp r3, #0
80017ee: d109 bne.n 8001804 <HAL_ADC_IRQHandler+0x4c>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
80017f0: 693b ldr r3, [r7, #16]
80017f2: f003 0308 and.w r3, r3, #8
if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
80017f6: 2b00 cmp r3, #0
80017f8: d076 beq.n 80018e8 <HAL_ADC_IRQHandler+0x130>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
80017fa: 68fb ldr r3, [r7, #12]
80017fc: f003 0308 and.w r3, r3, #8
8001800: 2b00 cmp r3, #0
8001802: d071 beq.n 80018e8 <HAL_ADC_IRQHandler+0x130>
{
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8001804: 687b ldr r3, [r7, #4]
8001806: 6c1b ldr r3, [r3, #64] @ 0x40
8001808: f003 0310 and.w r3, r3, #16
800180c: 2b00 cmp r3, #0
800180e: d105 bne.n 800181c <HAL_ADC_IRQHandler+0x64>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8001810: 687b ldr r3, [r7, #4]
8001812: 6c1b ldr r3, [r3, #64] @ 0x40
8001814: f443 7200 orr.w r2, r3, #512 @ 0x200
8001818: 687b ldr r3, [r7, #4]
800181a: 641a str r2, [r3, #64] @ 0x40
}
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
800181c: 4b82 ldr r3, [pc, #520] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
800181e: 689b ldr r3, [r3, #8]
8001820: f003 031f and.w r3, r3, #31
8001824: 2b00 cmp r3, #0
8001826: d010 beq.n 800184a <HAL_ADC_IRQHandler+0x92>
8001828: 4b7f ldr r3, [pc, #508] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
800182a: 689b ldr r3, [r3, #8]
800182c: f003 031f and.w r3, r3, #31
8001830: 2b05 cmp r3, #5
8001832: d00a beq.n 800184a <HAL_ADC_IRQHandler+0x92>
8001834: 4b7c ldr r3, [pc, #496] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
8001836: 689b ldr r3, [r3, #8]
8001838: f003 031f and.w r3, r3, #31
800183c: 2b09 cmp r3, #9
800183e: d004 beq.n 800184a <HAL_ADC_IRQHandler+0x92>
8001840: 687b ldr r3, [r7, #4]
8001842: 681b ldr r3, [r3, #0]
8001844: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8001848: d104 bne.n 8001854 <HAL_ADC_IRQHandler+0x9c>
{
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
800184a: 687b ldr r3, [r7, #4]
800184c: 681b ldr r3, [r3, #0]
800184e: 68db ldr r3, [r3, #12]
8001850: 61bb str r3, [r7, #24]
8001852: e003 b.n 800185c <HAL_ADC_IRQHandler+0xa4>
}
else
{
tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
8001854: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8001858: 68db ldr r3, [r3, #12]
800185a: 61bb str r3, [r7, #24]
}
/* Disable interruption if no further conversion upcoming by regular */
/* external trigger or by continuous mode, */
/* and if scan sequence if completed. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
800185c: 687b ldr r3, [r7, #4]
800185e: 681b ldr r3, [r3, #0]
8001860: 68db ldr r3, [r3, #12]
8001862: f403 6340 and.w r3, r3, #3072 @ 0xc00
8001866: 2b00 cmp r3, #0
8001868: d137 bne.n 80018da <HAL_ADC_IRQHandler+0x122>
(READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) )
800186a: 69bb ldr r3, [r7, #24]
800186c: f403 5300 and.w r3, r3, #8192 @ 0x2000
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8001870: 2b00 cmp r3, #0
8001872: d132 bne.n 80018da <HAL_ADC_IRQHandler+0x122>
{
/* If End of Sequence is reached, disable interrupts */
if((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS)
8001874: 693b ldr r3, [r7, #16]
8001876: f003 0308 and.w r3, r3, #8
800187a: 2b00 cmp r3, #0
800187c: d02d beq.n 80018da <HAL_ADC_IRQHandler+0x122>
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
800187e: 687b ldr r3, [r7, #4]
8001880: 681b ldr r3, [r3, #0]
8001882: 689b ldr r3, [r3, #8]
8001884: f003 0304 and.w r3, r3, #4
8001888: 2b00 cmp r3, #0
800188a: d11a bne.n 80018c2 <HAL_ADC_IRQHandler+0x10a>
{
/* Disable ADC end of sequence conversion interrupt */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
800188c: 687b ldr r3, [r7, #4]
800188e: 681b ldr r3, [r3, #0]
8001890: 685a ldr r2, [r3, #4]
8001892: 687b ldr r3, [r7, #4]
8001894: 681b ldr r3, [r3, #0]
8001896: f022 020c bic.w r2, r2, #12
800189a: 605a str r2, [r3, #4]
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
800189c: 687b ldr r3, [r7, #4]
800189e: 6c1b ldr r3, [r3, #64] @ 0x40
80018a0: f423 7280 bic.w r2, r3, #256 @ 0x100
80018a4: 687b ldr r3, [r7, #4]
80018a6: 641a str r2, [r3, #64] @ 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
80018a8: 687b ldr r3, [r7, #4]
80018aa: 6c1b ldr r3, [r3, #64] @ 0x40
80018ac: f403 5380 and.w r3, r3, #4096 @ 0x1000
80018b0: 2b00 cmp r3, #0
80018b2: d112 bne.n 80018da <HAL_ADC_IRQHandler+0x122>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
80018b4: 687b ldr r3, [r7, #4]
80018b6: 6c1b ldr r3, [r3, #64] @ 0x40
80018b8: f043 0201 orr.w r2, r3, #1
80018bc: 687b ldr r3, [r7, #4]
80018be: 641a str r2, [r3, #64] @ 0x40
80018c0: e00b b.n 80018da <HAL_ADC_IRQHandler+0x122>
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80018c2: 687b ldr r3, [r7, #4]
80018c4: 6c1b ldr r3, [r3, #64] @ 0x40
80018c6: f043 0210 orr.w r2, r3, #16
80018ca: 687b ldr r3, [r7, #4]
80018cc: 641a str r2, [r3, #64] @ 0x40
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80018ce: 687b ldr r3, [r7, #4]
80018d0: 6c5b ldr r3, [r3, #68] @ 0x44
80018d2: f043 0201 orr.w r2, r3, #1
80018d6: 687b ldr r3, [r7, #4]
80018d8: 645a str r2, [r3, #68] @ 0x44
/* from EOC or EOS, possibility to use: */
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
80018da: 6878 ldr r0, [r7, #4]
80018dc: f7ff fdbc bl 8001458 <HAL_ADC_ConvCpltCallback>
/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
/* conversion flags clear induces the release of the preserved */
/* data. */
/* Therefore, if the preserved data value is needed, it must be */
/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
80018e0: 687b ldr r3, [r7, #4]
80018e2: 681b ldr r3, [r3, #0]
80018e4: 220c movs r2, #12
80018e6: 601a str r2, [r3, #0]
}
/* ========== Check End of Conversion flag for injected group ========== */
if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
80018e8: 693b ldr r3, [r7, #16]
80018ea: f003 0320 and.w r3, r3, #32
80018ee: 2b00 cmp r3, #0
80018f0: d004 beq.n 80018fc <HAL_ADC_IRQHandler+0x144>
80018f2: 68fb ldr r3, [r7, #12]
80018f4: f003 0320 and.w r3, r3, #32
80018f8: 2b00 cmp r3, #0
80018fa: d10b bne.n 8001914 <HAL_ADC_IRQHandler+0x15c>
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
80018fc: 693b ldr r3, [r7, #16]
80018fe: f003 0340 and.w r3, r3, #64 @ 0x40
if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
8001902: 2b00 cmp r3, #0
8001904: f000 80a5 beq.w 8001a52 <HAL_ADC_IRQHandler+0x29a>
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
8001908: 68fb ldr r3, [r7, #12]
800190a: f003 0340 and.w r3, r3, #64 @ 0x40
800190e: 2b00 cmp r3, #0
8001910: f000 809f beq.w 8001a52 <HAL_ADC_IRQHandler+0x29a>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
8001914: 687b ldr r3, [r7, #4]
8001916: 6c1b ldr r3, [r3, #64] @ 0x40
8001918: f443 5200 orr.w r2, r3, #8192 @ 0x2000
800191c: 687b ldr r3, [r7, #4]
800191e: 641a str r2, [r3, #64] @ 0x40
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
8001920: 4b41 ldr r3, [pc, #260] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
8001922: 689b ldr r3, [r3, #8]
8001924: f003 031f and.w r3, r3, #31
8001928: 2b00 cmp r3, #0
800192a: d010 beq.n 800194e <HAL_ADC_IRQHandler+0x196>
800192c: 4b3e ldr r3, [pc, #248] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
800192e: 689b ldr r3, [r3, #8]
8001930: f003 031f and.w r3, r3, #31
8001934: 2b05 cmp r3, #5
8001936: d00a beq.n 800194e <HAL_ADC_IRQHandler+0x196>
8001938: 4b3b ldr r3, [pc, #236] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
800193a: 689b ldr r3, [r3, #8]
800193c: f003 031f and.w r3, r3, #31
8001940: 2b09 cmp r3, #9
8001942: d004 beq.n 800194e <HAL_ADC_IRQHandler+0x196>
8001944: 687b ldr r3, [r7, #4]
8001946: 681b ldr r3, [r3, #0]
8001948: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
800194c: d104 bne.n 8001958 <HAL_ADC_IRQHandler+0x1a0>
{
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
800194e: 687b ldr r3, [r7, #4]
8001950: 681b ldr r3, [r3, #0]
8001952: 68db ldr r3, [r3, #12]
8001954: 61bb str r3, [r7, #24]
8001956: e003 b.n 8001960 <HAL_ADC_IRQHandler+0x1a8>
}
else
{
tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
8001958: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
800195c: 68db ldr r3, [r3, #12]
800195e: 61bb str r3, [r7, #24]
/* Disable interruption if no further conversion upcoming by injected */
/* external trigger or by automatic injected conversion with regular */
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
if(ADC_IS_SOFTWARE_START_INJECTED(hadc))
8001960: 687b ldr r3, [r7, #4]
8001962: 681b ldr r3, [r3, #0]
8001964: 6cdb ldr r3, [r3, #76] @ 0x4c
8001966: f003 03c0 and.w r3, r3, #192 @ 0xc0
800196a: 2b00 cmp r3, #0
800196c: d16a bne.n 8001a44 <HAL_ADC_IRQHandler+0x28c>
{
if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) ||
800196e: 69bb ldr r3, [r7, #24]
8001970: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001974: 2b00 cmp r3, #0
8001976: d00b beq.n 8001990 <HAL_ADC_IRQHandler+0x1d8>
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8001978: 687b ldr r3, [r7, #4]
800197a: 681b ldr r3, [r3, #0]
800197c: 68db ldr r3, [r3, #12]
800197e: f403 6340 and.w r3, r3, #3072 @ 0xc00
if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) ||
8001982: 2b00 cmp r3, #0
8001984: d15e bne.n 8001a44 <HAL_ADC_IRQHandler+0x28c>
(READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) )
8001986: 69bb ldr r3, [r7, #24]
8001988: f403 5300 and.w r3, r3, #8192 @ 0x2000
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
800198c: 2b00 cmp r3, #0
800198e: d159 bne.n 8001a44 <HAL_ADC_IRQHandler+0x28c>
{
/* If End of Sequence is reached, disable interrupts */
if((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS)
8001990: 693b ldr r3, [r7, #16]
8001992: f003 0340 and.w r3, r3, #64 @ 0x40
8001996: 2b00 cmp r3, #0
8001998: d054 beq.n 8001a44 <HAL_ADC_IRQHandler+0x28c>
{
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
800199a: 4b23 ldr r3, [pc, #140] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
800199c: 689b ldr r3, [r3, #8]
800199e: f003 031f and.w r3, r3, #31
80019a2: 2b00 cmp r3, #0
80019a4: d010 beq.n 80019c8 <HAL_ADC_IRQHandler+0x210>
80019a6: 4b20 ldr r3, [pc, #128] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
80019a8: 689b ldr r3, [r3, #8]
80019aa: f003 031f and.w r3, r3, #31
80019ae: 2b06 cmp r3, #6
80019b0: d00a beq.n 80019c8 <HAL_ADC_IRQHandler+0x210>
80019b2: 4b1d ldr r3, [pc, #116] @ (8001a28 <HAL_ADC_IRQHandler+0x270>)
80019b4: 689b ldr r3, [r3, #8]
80019b6: f003 031f and.w r3, r3, #31
80019ba: 2b07 cmp r3, #7
80019bc: d004 beq.n 80019c8 <HAL_ADC_IRQHandler+0x210>
80019be: 687b ldr r3, [r7, #4]
80019c0: 681b ldr r3, [r3, #0]
80019c2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80019c6: d104 bne.n 80019d2 <HAL_ADC_IRQHandler+0x21a>
{
tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
80019c8: 687b ldr r3, [r7, #4]
80019ca: 681b ldr r3, [r3, #0]
80019cc: 68db ldr r3, [r3, #12]
80019ce: 617b str r3, [r7, #20]
80019d0: e003 b.n 80019da <HAL_ADC_IRQHandler+0x222>
}
else
{
tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
80019d2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
80019d6: 68db ldr r3, [r3, #12]
80019d8: 617b str r3, [r7, #20]
/* when the last context has been fully processed, JSQR is reset */
/* by the hardware. Even if no injected conversion is planned to come */
/* (queue empty, triggers are ignored), it can start again */
/* immediately after setting a new context (JADSTART is still set). */
/* Therefore, state of HAL ADC injected group is kept to busy. */
if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
80019da: 697b ldr r3, [r7, #20]
80019dc: f403 1300 and.w r3, r3, #2097152 @ 0x200000
80019e0: 2b00 cmp r3, #0
80019e2: d12f bne.n 8001a44 <HAL_ADC_IRQHandler+0x28c>
{
/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
/* JADSTART==0 (no conversion on going) */
if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
80019e4: 687b ldr r3, [r7, #4]
80019e6: 681b ldr r3, [r3, #0]
80019e8: 689b ldr r3, [r3, #8]
80019ea: f003 0308 and.w r3, r3, #8
80019ee: 2b00 cmp r3, #0
80019f0: d11c bne.n 8001a2c <HAL_ADC_IRQHandler+0x274>
{
/* Disable ADC end of sequence conversion interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
80019f2: 687b ldr r3, [r7, #4]
80019f4: 681b ldr r3, [r3, #0]
80019f6: 685a ldr r2, [r3, #4]
80019f8: 687b ldr r3, [r7, #4]
80019fa: 681b ldr r3, [r3, #0]
80019fc: f022 0260 bic.w r2, r2, #96 @ 0x60
8001a00: 605a str r2, [r3, #4]
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
8001a02: 687b ldr r3, [r7, #4]
8001a04: 6c1b ldr r3, [r3, #64] @ 0x40
8001a06: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8001a0a: 687b ldr r3, [r7, #4]
8001a0c: 641a str r2, [r3, #64] @ 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
8001a0e: 687b ldr r3, [r7, #4]
8001a10: 6c1b ldr r3, [r3, #64] @ 0x40
8001a12: f403 7380 and.w r3, r3, #256 @ 0x100
8001a16: 2b00 cmp r3, #0
8001a18: d114 bne.n 8001a44 <HAL_ADC_IRQHandler+0x28c>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8001a1a: 687b ldr r3, [r7, #4]
8001a1c: 6c1b ldr r3, [r3, #64] @ 0x40
8001a1e: f043 0201 orr.w r2, r3, #1
8001a22: 687b ldr r3, [r7, #4]
8001a24: 641a str r2, [r3, #64] @ 0x40
8001a26: e00d b.n 8001a44 <HAL_ADC_IRQHandler+0x28c>
8001a28: 50000300 .word 0x50000300
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001a2c: 687b ldr r3, [r7, #4]
8001a2e: 6c1b ldr r3, [r3, #64] @ 0x40
8001a30: f043 0210 orr.w r2, r3, #16
8001a34: 687b ldr r3, [r7, #4]
8001a36: 641a str r2, [r3, #64] @ 0x40
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001a38: 687b ldr r3, [r7, #4]
8001a3a: 6c5b ldr r3, [r3, #68] @ 0x44
8001a3c: f043 0201 orr.w r2, r3, #1
8001a40: 687b ldr r3, [r7, #4]
8001a42: 645a str r2, [r3, #68] @ 0x44
/* from JEOC or JEOS, possibility to use: */
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->InjectedConvCpltCallback(hadc);
#else
HAL_ADCEx_InjectedConvCpltCallback(hadc);
8001a44: 6878 ldr r0, [r7, #4]
8001a46: f000 f8b1 bl 8001bac <HAL_ADCEx_InjectedConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
8001a4a: 687b ldr r3, [r7, #4]
8001a4c: 681b ldr r3, [r3, #0]
8001a4e: 2260 movs r2, #96 @ 0x60
8001a50: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 1 flag ========== */
if(((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
8001a52: 693b ldr r3, [r7, #16]
8001a54: f003 0380 and.w r3, r3, #128 @ 0x80
8001a58: 2b00 cmp r3, #0
8001a5a: d011 beq.n 8001a80 <HAL_ADC_IRQHandler+0x2c8>
8001a5c: 68fb ldr r3, [r7, #12]
8001a5e: f003 0380 and.w r3, r3, #128 @ 0x80
8001a62: 2b00 cmp r3, #0
8001a64: d00c beq.n 8001a80 <HAL_ADC_IRQHandler+0x2c8>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
8001a66: 687b ldr r3, [r7, #4]
8001a68: 6c1b ldr r3, [r3, #64] @ 0x40
8001a6a: f443 3280 orr.w r2, r3, #65536 @ 0x10000
8001a6e: 687b ldr r3, [r7, #4]
8001a70: 641a str r2, [r3, #64] @ 0x40
/* Level out of window 1 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindowCallback(hadc);
#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
8001a72: 6878 ldr r0, [r7, #4]
8001a74: f7ff fcfa bl 800146c <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
8001a78: 687b ldr r3, [r7, #4]
8001a7a: 681b ldr r3, [r3, #0]
8001a7c: 2280 movs r2, #128 @ 0x80
8001a7e: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 2 flag ========== */
if(((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
8001a80: 693b ldr r3, [r7, #16]
8001a82: f403 7380 and.w r3, r3, #256 @ 0x100
8001a86: 2b00 cmp r3, #0
8001a88: d012 beq.n 8001ab0 <HAL_ADC_IRQHandler+0x2f8>
8001a8a: 68fb ldr r3, [r7, #12]
8001a8c: f403 7380 and.w r3, r3, #256 @ 0x100
8001a90: 2b00 cmp r3, #0
8001a92: d00d beq.n 8001ab0 <HAL_ADC_IRQHandler+0x2f8>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
8001a94: 687b ldr r3, [r7, #4]
8001a96: 6c1b ldr r3, [r3, #64] @ 0x40
8001a98: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8001a9c: 687b ldr r3, [r7, #4]
8001a9e: 641a str r2, [r3, #64] @ 0x40
/* Level out of window 2 callback */
HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
8001aa0: 6878 ldr r0, [r7, #4]
8001aa2: f000 f897 bl 8001bd4 <HAL_ADCEx_LevelOutOfWindow2Callback>
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
8001aa6: 687b ldr r3, [r7, #4]
8001aa8: 681b ldr r3, [r3, #0]
8001aaa: f44f 7280 mov.w r2, #256 @ 0x100
8001aae: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 3 flag ========== */
if(((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
8001ab0: 693b ldr r3, [r7, #16]
8001ab2: f403 7300 and.w r3, r3, #512 @ 0x200
8001ab6: 2b00 cmp r3, #0
8001ab8: d012 beq.n 8001ae0 <HAL_ADC_IRQHandler+0x328>
8001aba: 68fb ldr r3, [r7, #12]
8001abc: f403 7300 and.w r3, r3, #512 @ 0x200
8001ac0: 2b00 cmp r3, #0
8001ac2: d00d beq.n 8001ae0 <HAL_ADC_IRQHandler+0x328>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
8001ac4: 687b ldr r3, [r7, #4]
8001ac6: 6c1b ldr r3, [r3, #64] @ 0x40
8001ac8: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8001acc: 687b ldr r3, [r7, #4]
8001ace: 641a str r2, [r3, #64] @ 0x40
/* Level out of window 3 callback */
HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
8001ad0: 6878 ldr r0, [r7, #4]
8001ad2: f000 f889 bl 8001be8 <HAL_ADCEx_LevelOutOfWindow3Callback>
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
8001ad6: 687b ldr r3, [r7, #4]
8001ad8: 681b ldr r3, [r3, #0]
8001ada: f44f 7200 mov.w r2, #512 @ 0x200
8001ade: 601a str r2, [r3, #0]
}
/* ========== Check Overrun flag ========== */
if(((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
8001ae0: 693b ldr r3, [r7, #16]
8001ae2: f003 0310 and.w r3, r3, #16
8001ae6: 2b00 cmp r3, #0
8001ae8: d03b beq.n 8001b62 <HAL_ADC_IRQHandler+0x3aa>
8001aea: 68fb ldr r3, [r7, #12]
8001aec: f003 0310 and.w r3, r3, #16
8001af0: 2b00 cmp r3, #0
8001af2: d036 beq.n 8001b62 <HAL_ADC_IRQHandler+0x3aa>
/* overrun event is not considered as an error. */
/* (cf ref manual "Managing conversions without using the DMA and */
/* without overrun ") */
/* Exception for usage with DMA overrun event always considered as an */
/* error. */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
8001af4: 687b ldr r3, [r7, #4]
8001af6: 6b5b ldr r3, [r3, #52] @ 0x34
8001af8: 2b01 cmp r3, #1
8001afa: d102 bne.n 8001b02 <HAL_ADC_IRQHandler+0x34a>
{
overrun_error = 1U;
8001afc: 2301 movs r3, #1
8001afe: 61fb str r3, [r7, #28]
8001b00: e019 b.n 8001b36 <HAL_ADC_IRQHandler+0x37e>
else
{
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
/* control registers) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
8001b02: 4b29 ldr r3, [pc, #164] @ (8001ba8 <HAL_ADC_IRQHandler+0x3f0>)
8001b04: 60bb str r3, [r7, #8]
/* Check DMA configuration, depending on MultiMode set or not */
if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
8001b06: 68bb ldr r3, [r7, #8]
8001b08: 689b ldr r3, [r3, #8]
8001b0a: f003 031f and.w r3, r3, #31
8001b0e: 2b00 cmp r3, #0
8001b10: d109 bne.n 8001b26 <HAL_ADC_IRQHandler+0x36e>
{
if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
8001b12: 687b ldr r3, [r7, #4]
8001b14: 681b ldr r3, [r3, #0]
8001b16: 68db ldr r3, [r3, #12]
8001b18: f003 0301 and.w r3, r3, #1
8001b1c: 2b01 cmp r3, #1
8001b1e: d10a bne.n 8001b36 <HAL_ADC_IRQHandler+0x37e>
{
overrun_error = 1U;
8001b20: 2301 movs r3, #1
8001b22: 61fb str r3, [r7, #28]
8001b24: e007 b.n 8001b36 <HAL_ADC_IRQHandler+0x37e>
}
}
else
{
/* MultiMode is enabled, Common Control Register MDMA bits must be checked */
if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
8001b26: 68bb ldr r3, [r7, #8]
8001b28: 689b ldr r3, [r3, #8]
8001b2a: f403 4340 and.w r3, r3, #49152 @ 0xc000
8001b2e: 2b00 cmp r3, #0
8001b30: d001 beq.n 8001b36 <HAL_ADC_IRQHandler+0x37e>
{
overrun_error = 1U;
8001b32: 2301 movs r3, #1
8001b34: 61fb str r3, [r7, #28]
}
}
}
if (overrun_error == 1U)
8001b36: 69fb ldr r3, [r7, #28]
8001b38: 2b01 cmp r3, #1
8001b3a: d10e bne.n 8001b5a <HAL_ADC_IRQHandler+0x3a2>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
8001b3c: 687b ldr r3, [r7, #4]
8001b3e: 6c1b ldr r3, [r3, #64] @ 0x40
8001b40: f443 6280 orr.w r2, r3, #1024 @ 0x400
8001b44: 687b ldr r3, [r7, #4]
8001b46: 641a str r2, [r3, #64] @ 0x40
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
8001b48: 687b ldr r3, [r7, #4]
8001b4a: 6c5b ldr r3, [r3, #68] @ 0x44
8001b4c: f043 0202 orr.w r2, r3, #2
8001b50: 687b ldr r3, [r7, #4]
8001b52: 645a str r2, [r3, #68] @ 0x44
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
8001b54: 6878 ldr r0, [r7, #4]
8001b56: f7ff fc93 bl 8001480 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/* Clear the Overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 681b ldr r3, [r3, #0]
8001b5e: 2210 movs r2, #16
8001b60: 601a str r2, [r3, #0]
}
/* ========== Check Injected context queue overflow flag ========== */
if(((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
8001b62: 693b ldr r3, [r7, #16]
8001b64: f403 6380 and.w r3, r3, #1024 @ 0x400
8001b68: 2b00 cmp r3, #0
8001b6a: d018 beq.n 8001b9e <HAL_ADC_IRQHandler+0x3e6>
8001b6c: 68fb ldr r3, [r7, #12]
8001b6e: f403 6380 and.w r3, r3, #1024 @ 0x400
8001b72: 2b00 cmp r3, #0
8001b74: d013 beq.n 8001b9e <HAL_ADC_IRQHandler+0x3e6>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
8001b76: 687b ldr r3, [r7, #4]
8001b78: 6c1b ldr r3, [r3, #64] @ 0x40
8001b7a: f443 4280 orr.w r2, r3, #16384 @ 0x4000
8001b7e: 687b ldr r3, [r7, #4]
8001b80: 641a str r2, [r3, #64] @ 0x40
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
8001b82: 687b ldr r3, [r7, #4]
8001b84: 6c5b ldr r3, [r3, #68] @ 0x44
8001b86: f043 0208 orr.w r2, r3, #8
8001b8a: 687b ldr r3, [r7, #4]
8001b8c: 645a str r2, [r3, #68] @ 0x44
/* Clear the Injected context queue overflow flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
8001b8e: 687b ldr r3, [r7, #4]
8001b90: 681b ldr r3, [r3, #0]
8001b92: f44f 6280 mov.w r2, #1024 @ 0x400
8001b96: 601a str r2, [r3, #0]
/* Error callback */
HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
8001b98: 6878 ldr r0, [r7, #4]
8001b9a: f000 f811 bl 8001bc0 <HAL_ADCEx_InjectedQueueOverflowCallback>
}
}
8001b9e: bf00 nop
8001ba0: 3720 adds r7, #32
8001ba2: 46bd mov sp, r7
8001ba4: bd80 pop {r7, pc}
8001ba6: bf00 nop
8001ba8: 50000300 .word 0x50000300
08001bac <HAL_ADCEx_InjectedConvCpltCallback>:
* @brief Injected conversion complete callback in non blocking mode
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
{
8001bac: b480 push {r7}
8001bae: b083 sub sp, #12
8001bb0: af00 add r7, sp, #0
8001bb2: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
*/
}
8001bb4: bf00 nop
8001bb6: 370c adds r7, #12
8001bb8: 46bd mov sp, r7
8001bba: f85d 7b04 ldr.w r7, [sp], #4
8001bbe: 4770 bx lr
08001bc0 <HAL_ADCEx_InjectedQueueOverflowCallback>:
contexts).
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
{
8001bc0: b480 push {r7}
8001bc2: b083 sub sp, #12
8001bc4: af00 add r7, sp, #0
8001bc6: 6078 str r0, [r7, #4]
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
in the user file.
*/
}
8001bc8: bf00 nop
8001bca: 370c adds r7, #12
8001bcc: 46bd mov sp, r7
8001bce: f85d 7b04 ldr.w r7, [sp], #4
8001bd2: 4770 bx lr
08001bd4 <HAL_ADCEx_LevelOutOfWindow2Callback>:
* @brief Analog watchdog 2 callback in non blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
{
8001bd4: b480 push {r7}
8001bd6: b083 sub sp, #12
8001bd8: af00 add r7, sp, #0
8001bda: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file.
*/
}
8001bdc: bf00 nop
8001bde: 370c adds r7, #12
8001be0: 46bd mov sp, r7
8001be2: f85d 7b04 ldr.w r7, [sp], #4
8001be6: 4770 bx lr
08001be8 <HAL_ADCEx_LevelOutOfWindow3Callback>:
* @brief Analog watchdog 3 callback in non blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
{
8001be8: b480 push {r7}
8001bea: b083 sub sp, #12
8001bec: af00 add r7, sp, #0
8001bee: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file.
*/
}
8001bf0: bf00 nop
8001bf2: 370c adds r7, #12
8001bf4: 46bd mov sp, r7
8001bf6: f85d 7b04 ldr.w r7, [sp], #4
8001bfa: 4770 bx lr
08001bfc <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8001bfc: b480 push {r7}
8001bfe: b09b sub sp, #108 @ 0x6c
8001c00: af00 add r7, sp, #0
8001c02: 6078 str r0, [r7, #4]
8001c04: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001c06: 2300 movs r3, #0
8001c08: f887 3067 strb.w r3, [r7, #103] @ 0x67
ADC_Common_TypeDef *tmpADC_Common;
ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
uint32_t tmpOffsetShifted;
__IO uint32_t wait_loop_index = 0U;
8001c0c: 2300 movs r3, #0
8001c0e: 60bb str r3, [r7, #8]
{
assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
}
/* Process locked */
__HAL_LOCK(hadc);
8001c10: 687b ldr r3, [r7, #4]
8001c12: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8001c16: 2b01 cmp r3, #1
8001c18: d101 bne.n 8001c1e <HAL_ADC_ConfigChannel+0x22>
8001c1a: 2302 movs r3, #2
8001c1c: e2a1 b.n 8002162 <HAL_ADC_ConfigChannel+0x566>
8001c1e: 687b ldr r3, [r7, #4]
8001c20: 2201 movs r2, #1
8001c22: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
8001c26: 687b ldr r3, [r7, #4]
8001c28: 681b ldr r3, [r3, #0]
8001c2a: 689b ldr r3, [r3, #8]
8001c2c: f003 0304 and.w r3, r3, #4
8001c30: 2b00 cmp r3, #0
8001c32: f040 8285 bne.w 8002140 <HAL_ADC_ConfigChannel+0x544>
{
/* Regular sequence configuration */
/* For Rank 1 to 4U */
if (sConfig->Rank < 5U)
8001c36: 683b ldr r3, [r7, #0]
8001c38: 685b ldr r3, [r3, #4]
8001c3a: 2b04 cmp r3, #4
8001c3c: d81c bhi.n 8001c78 <HAL_ADC_ConfigChannel+0x7c>
{
MODIFY_REG(hadc->Instance->SQR1,
8001c3e: 687b ldr r3, [r7, #4]
8001c40: 681b ldr r3, [r3, #0]
8001c42: 6b19 ldr r1, [r3, #48] @ 0x30
8001c44: 683b ldr r3, [r7, #0]
8001c46: 685a ldr r2, [r3, #4]
8001c48: 4613 mov r3, r2
8001c4a: 005b lsls r3, r3, #1
8001c4c: 4413 add r3, r2
8001c4e: 005b lsls r3, r3, #1
8001c50: 461a mov r2, r3
8001c52: 231f movs r3, #31
8001c54: 4093 lsls r3, r2
8001c56: 43db mvns r3, r3
8001c58: 4019 ands r1, r3
8001c5a: 683b ldr r3, [r7, #0]
8001c5c: 6818 ldr r0, [r3, #0]
8001c5e: 683b ldr r3, [r7, #0]
8001c60: 685a ldr r2, [r3, #4]
8001c62: 4613 mov r3, r2
8001c64: 005b lsls r3, r3, #1
8001c66: 4413 add r3, r2
8001c68: 005b lsls r3, r3, #1
8001c6a: fa00 f203 lsl.w r2, r0, r3
8001c6e: 687b ldr r3, [r7, #4]
8001c70: 681b ldr r3, [r3, #0]
8001c72: 430a orrs r2, r1
8001c74: 631a str r2, [r3, #48] @ 0x30
8001c76: e063 b.n 8001d40 <HAL_ADC_ConfigChannel+0x144>
ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 5 to 9U */
else if (sConfig->Rank < 10U)
8001c78: 683b ldr r3, [r7, #0]
8001c7a: 685b ldr r3, [r3, #4]
8001c7c: 2b09 cmp r3, #9
8001c7e: d81e bhi.n 8001cbe <HAL_ADC_ConfigChannel+0xc2>
{
MODIFY_REG(hadc->Instance->SQR2,
8001c80: 687b ldr r3, [r7, #4]
8001c82: 681b ldr r3, [r3, #0]
8001c84: 6b59 ldr r1, [r3, #52] @ 0x34
8001c86: 683b ldr r3, [r7, #0]
8001c88: 685a ldr r2, [r3, #4]
8001c8a: 4613 mov r3, r2
8001c8c: 005b lsls r3, r3, #1
8001c8e: 4413 add r3, r2
8001c90: 005b lsls r3, r3, #1
8001c92: 3b1e subs r3, #30
8001c94: 221f movs r2, #31
8001c96: fa02 f303 lsl.w r3, r2, r3
8001c9a: 43db mvns r3, r3
8001c9c: 4019 ands r1, r3
8001c9e: 683b ldr r3, [r7, #0]
8001ca0: 6818 ldr r0, [r3, #0]
8001ca2: 683b ldr r3, [r7, #0]
8001ca4: 685a ldr r2, [r3, #4]
8001ca6: 4613 mov r3, r2
8001ca8: 005b lsls r3, r3, #1
8001caa: 4413 add r3, r2
8001cac: 005b lsls r3, r3, #1
8001cae: 3b1e subs r3, #30
8001cb0: fa00 f203 lsl.w r2, r0, r3
8001cb4: 687b ldr r3, [r7, #4]
8001cb6: 681b ldr r3, [r3, #0]
8001cb8: 430a orrs r2, r1
8001cba: 635a str r2, [r3, #52] @ 0x34
8001cbc: e040 b.n 8001d40 <HAL_ADC_ConfigChannel+0x144>
ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 10 to 14U */
else if (sConfig->Rank < 15U)
8001cbe: 683b ldr r3, [r7, #0]
8001cc0: 685b ldr r3, [r3, #4]
8001cc2: 2b0e cmp r3, #14
8001cc4: d81e bhi.n 8001d04 <HAL_ADC_ConfigChannel+0x108>
{
MODIFY_REG(hadc->Instance->SQR3 ,
8001cc6: 687b ldr r3, [r7, #4]
8001cc8: 681b ldr r3, [r3, #0]
8001cca: 6b99 ldr r1, [r3, #56] @ 0x38
8001ccc: 683b ldr r3, [r7, #0]
8001cce: 685a ldr r2, [r3, #4]
8001cd0: 4613 mov r3, r2
8001cd2: 005b lsls r3, r3, #1
8001cd4: 4413 add r3, r2
8001cd6: 005b lsls r3, r3, #1
8001cd8: 3b3c subs r3, #60 @ 0x3c
8001cda: 221f movs r2, #31
8001cdc: fa02 f303 lsl.w r3, r2, r3
8001ce0: 43db mvns r3, r3
8001ce2: 4019 ands r1, r3
8001ce4: 683b ldr r3, [r7, #0]
8001ce6: 6818 ldr r0, [r3, #0]
8001ce8: 683b ldr r3, [r7, #0]
8001cea: 685a ldr r2, [r3, #4]
8001cec: 4613 mov r3, r2
8001cee: 005b lsls r3, r3, #1
8001cf0: 4413 add r3, r2
8001cf2: 005b lsls r3, r3, #1
8001cf4: 3b3c subs r3, #60 @ 0x3c
8001cf6: fa00 f203 lsl.w r2, r0, r3
8001cfa: 687b ldr r3, [r7, #4]
8001cfc: 681b ldr r3, [r3, #0]
8001cfe: 430a orrs r2, r1
8001d00: 639a str r2, [r3, #56] @ 0x38
8001d02: e01d b.n 8001d40 <HAL_ADC_ConfigChannel+0x144>
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 15 to 16U */
else
{
MODIFY_REG(hadc->Instance->SQR4 ,
8001d04: 687b ldr r3, [r7, #4]
8001d06: 681b ldr r3, [r3, #0]
8001d08: 6bd9 ldr r1, [r3, #60] @ 0x3c
8001d0a: 683b ldr r3, [r7, #0]
8001d0c: 685a ldr r2, [r3, #4]
8001d0e: 4613 mov r3, r2
8001d10: 005b lsls r3, r3, #1
8001d12: 4413 add r3, r2
8001d14: 005b lsls r3, r3, #1
8001d16: 3b5a subs r3, #90 @ 0x5a
8001d18: 221f movs r2, #31
8001d1a: fa02 f303 lsl.w r3, r2, r3
8001d1e: 43db mvns r3, r3
8001d20: 4019 ands r1, r3
8001d22: 683b ldr r3, [r7, #0]
8001d24: 6818 ldr r0, [r3, #0]
8001d26: 683b ldr r3, [r7, #0]
8001d28: 685a ldr r2, [r3, #4]
8001d2a: 4613 mov r3, r2
8001d2c: 005b lsls r3, r3, #1
8001d2e: 4413 add r3, r2
8001d30: 005b lsls r3, r3, #1
8001d32: 3b5a subs r3, #90 @ 0x5a
8001d34: fa00 f203 lsl.w r2, r0, r3
8001d38: 687b ldr r3, [r7, #4]
8001d3a: 681b ldr r3, [r3, #0]
8001d3c: 430a orrs r2, r1
8001d3e: 63da str r2, [r3, #60] @ 0x3c
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
8001d40: 687b ldr r3, [r7, #4]
8001d42: 681b ldr r3, [r3, #0]
8001d44: 689b ldr r3, [r3, #8]
8001d46: f003 030c and.w r3, r3, #12
8001d4a: 2b00 cmp r3, #0
8001d4c: f040 80e5 bne.w 8001f1a <HAL_ADC_ConfigChannel+0x31e>
{
/* Channel sampling time configuration */
/* For channels 10 to 18U */
if (sConfig->Channel >= ADC_CHANNEL_10)
8001d50: 683b ldr r3, [r7, #0]
8001d52: 681b ldr r3, [r3, #0]
8001d54: 2b09 cmp r3, #9
8001d56: d91c bls.n 8001d92 <HAL_ADC_ConfigChannel+0x196>
{
MODIFY_REG(hadc->Instance->SMPR2 ,
8001d58: 687b ldr r3, [r7, #4]
8001d5a: 681b ldr r3, [r3, #0]
8001d5c: 6999 ldr r1, [r3, #24]
8001d5e: 683b ldr r3, [r7, #0]
8001d60: 681a ldr r2, [r3, #0]
8001d62: 4613 mov r3, r2
8001d64: 005b lsls r3, r3, #1
8001d66: 4413 add r3, r2
8001d68: 3b1e subs r3, #30
8001d6a: 2207 movs r2, #7
8001d6c: fa02 f303 lsl.w r3, r2, r3
8001d70: 43db mvns r3, r3
8001d72: 4019 ands r1, r3
8001d74: 683b ldr r3, [r7, #0]
8001d76: 6898 ldr r0, [r3, #8]
8001d78: 683b ldr r3, [r7, #0]
8001d7a: 681a ldr r2, [r3, #0]
8001d7c: 4613 mov r3, r2
8001d7e: 005b lsls r3, r3, #1
8001d80: 4413 add r3, r2
8001d82: 3b1e subs r3, #30
8001d84: fa00 f203 lsl.w r2, r0, r3
8001d88: 687b ldr r3, [r7, #4]
8001d8a: 681b ldr r3, [r3, #0]
8001d8c: 430a orrs r2, r1
8001d8e: 619a str r2, [r3, #24]
8001d90: e019 b.n 8001dc6 <HAL_ADC_ConfigChannel+0x1ca>
ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) ,
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
else /* For channels 1 to 9U */
{
MODIFY_REG(hadc->Instance->SMPR1 ,
8001d92: 687b ldr r3, [r7, #4]
8001d94: 681b ldr r3, [r3, #0]
8001d96: 6959 ldr r1, [r3, #20]
8001d98: 683b ldr r3, [r7, #0]
8001d9a: 681a ldr r2, [r3, #0]
8001d9c: 4613 mov r3, r2
8001d9e: 005b lsls r3, r3, #1
8001da0: 4413 add r3, r2
8001da2: 2207 movs r2, #7
8001da4: fa02 f303 lsl.w r3, r2, r3
8001da8: 43db mvns r3, r3
8001daa: 4019 ands r1, r3
8001dac: 683b ldr r3, [r7, #0]
8001dae: 6898 ldr r0, [r3, #8]
8001db0: 683b ldr r3, [r7, #0]
8001db2: 681a ldr r2, [r3, #0]
8001db4: 4613 mov r3, r2
8001db6: 005b lsls r3, r3, #1
8001db8: 4413 add r3, r2
8001dba: fa00 f203 lsl.w r2, r0, r3
8001dbe: 687b ldr r3, [r7, #4]
8001dc0: 681b ldr r3, [r3, #0]
8001dc2: 430a orrs r2, r1
8001dc4: 615a str r2, [r3, #20]
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset in function of the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
/* to 0. */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
8001dc6: 683b ldr r3, [r7, #0]
8001dc8: 695a ldr r2, [r3, #20]
8001dca: 687b ldr r3, [r7, #4]
8001dcc: 681b ldr r3, [r3, #0]
8001dce: 68db ldr r3, [r3, #12]
8001dd0: 08db lsrs r3, r3, #3
8001dd2: f003 0303 and.w r3, r3, #3
8001dd6: 005b lsls r3, r3, #1
8001dd8: fa02 f303 lsl.w r3, r2, r3
8001ddc: 663b str r3, [r7, #96] @ 0x60
/* Configure the selected offset register: */
/* - Enable offset */
/* - Set channel number */
/* - Set offset value */
switch (sConfig->OffsetNumber)
8001dde: 683b ldr r3, [r7, #0]
8001de0: 691b ldr r3, [r3, #16]
8001de2: 3b01 subs r3, #1
8001de4: 2b03 cmp r3, #3
8001de6: d84f bhi.n 8001e88 <HAL_ADC_ConfigChannel+0x28c>
8001de8: a201 add r2, pc, #4 @ (adr r2, 8001df0 <HAL_ADC_ConfigChannel+0x1f4>)
8001dea: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001dee: bf00 nop
8001df0: 08001e01 .word 0x08001e01
8001df4: 08001e23 .word 0x08001e23
8001df8: 08001e45 .word 0x08001e45
8001dfc: 08001e67 .word 0x08001e67
{
case ADC_OFFSET_1:
/* Configure offset register 1U */
MODIFY_REG(hadc->Instance->OFR1 ,
8001e00: 687b ldr r3, [r7, #4]
8001e02: 681b ldr r3, [r3, #0]
8001e04: 6e1a ldr r2, [r3, #96] @ 0x60
8001e06: 4b9c ldr r3, [pc, #624] @ (8002078 <HAL_ADC_ConfigChannel+0x47c>)
8001e08: 4013 ands r3, r2
8001e0a: 683a ldr r2, [r7, #0]
8001e0c: 6812 ldr r2, [r2, #0]
8001e0e: 0691 lsls r1, r2, #26
8001e10: 6e3a ldr r2, [r7, #96] @ 0x60
8001e12: 430a orrs r2, r1
8001e14: 431a orrs r2, r3
8001e16: 687b ldr r3, [r7, #4]
8001e18: 681b ldr r3, [r3, #0]
8001e1a: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
8001e1e: 661a str r2, [r3, #96] @ 0x60
ADC_OFR1_OFFSET1_CH |
ADC_OFR1_OFFSET1 ,
ADC_OFR1_OFFSET1_EN |
ADC_OFR_CHANNEL(sConfig->Channel) |
tmpOffsetShifted );
break;
8001e20: e07b b.n 8001f1a <HAL_ADC_ConfigChannel+0x31e>
case ADC_OFFSET_2:
/* Configure offset register 2U */
MODIFY_REG(hadc->Instance->OFR2 ,
8001e22: 687b ldr r3, [r7, #4]
8001e24: 681b ldr r3, [r3, #0]
8001e26: 6e5a ldr r2, [r3, #100] @ 0x64
8001e28: 4b93 ldr r3, [pc, #588] @ (8002078 <HAL_ADC_ConfigChannel+0x47c>)
8001e2a: 4013 ands r3, r2
8001e2c: 683a ldr r2, [r7, #0]
8001e2e: 6812 ldr r2, [r2, #0]
8001e30: 0691 lsls r1, r2, #26
8001e32: 6e3a ldr r2, [r7, #96] @ 0x60
8001e34: 430a orrs r2, r1
8001e36: 431a orrs r2, r3
8001e38: 687b ldr r3, [r7, #4]
8001e3a: 681b ldr r3, [r3, #0]
8001e3c: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
8001e40: 665a str r2, [r3, #100] @ 0x64
ADC_OFR2_OFFSET2_CH |
ADC_OFR2_OFFSET2 ,
ADC_OFR2_OFFSET2_EN |
ADC_OFR_CHANNEL(sConfig->Channel) |
tmpOffsetShifted );
break;
8001e42: e06a b.n 8001f1a <HAL_ADC_ConfigChannel+0x31e>
case ADC_OFFSET_3:
/* Configure offset register 3U */
MODIFY_REG(hadc->Instance->OFR3 ,
8001e44: 687b ldr r3, [r7, #4]
8001e46: 681b ldr r3, [r3, #0]
8001e48: 6e9a ldr r2, [r3, #104] @ 0x68
8001e4a: 4b8b ldr r3, [pc, #556] @ (8002078 <HAL_ADC_ConfigChannel+0x47c>)
8001e4c: 4013 ands r3, r2
8001e4e: 683a ldr r2, [r7, #0]
8001e50: 6812 ldr r2, [r2, #0]
8001e52: 0691 lsls r1, r2, #26
8001e54: 6e3a ldr r2, [r7, #96] @ 0x60
8001e56: 430a orrs r2, r1
8001e58: 431a orrs r2, r3
8001e5a: 687b ldr r3, [r7, #4]
8001e5c: 681b ldr r3, [r3, #0]
8001e5e: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
8001e62: 669a str r2, [r3, #104] @ 0x68
ADC_OFR3_OFFSET3_CH |
ADC_OFR3_OFFSET3 ,
ADC_OFR3_OFFSET3_EN |
ADC_OFR_CHANNEL(sConfig->Channel) |
tmpOffsetShifted );
break;
8001e64: e059 b.n 8001f1a <HAL_ADC_ConfigChannel+0x31e>
case ADC_OFFSET_4:
/* Configure offset register 4U */
MODIFY_REG(hadc->Instance->OFR4 ,
8001e66: 687b ldr r3, [r7, #4]
8001e68: 681b ldr r3, [r3, #0]
8001e6a: 6eda ldr r2, [r3, #108] @ 0x6c
8001e6c: 4b82 ldr r3, [pc, #520] @ (8002078 <HAL_ADC_ConfigChannel+0x47c>)
8001e6e: 4013 ands r3, r2
8001e70: 683a ldr r2, [r7, #0]
8001e72: 6812 ldr r2, [r2, #0]
8001e74: 0691 lsls r1, r2, #26
8001e76: 6e3a ldr r2, [r7, #96] @ 0x60
8001e78: 430a orrs r2, r1
8001e7a: 431a orrs r2, r3
8001e7c: 687b ldr r3, [r7, #4]
8001e7e: 681b ldr r3, [r3, #0]
8001e80: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
8001e84: 66da str r2, [r3, #108] @ 0x6c
ADC_OFR4_OFFSET4_CH |
ADC_OFR4_OFFSET4 ,
ADC_OFR4_OFFSET4_EN |
ADC_OFR_CHANNEL(sConfig->Channel) |
tmpOffsetShifted );
break;
8001e86: e048 b.n 8001f1a <HAL_ADC_ConfigChannel+0x31e>
/* Case ADC_OFFSET_NONE */
default :
/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
/* enabled. If this is the case, offset OFRx is disabled. */
if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
8001e88: 687b ldr r3, [r7, #4]
8001e8a: 681b ldr r3, [r3, #0]
8001e8c: 6e1b ldr r3, [r3, #96] @ 0x60
8001e8e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8001e92: 683b ldr r3, [r7, #0]
8001e94: 681b ldr r3, [r3, #0]
8001e96: 069b lsls r3, r3, #26
8001e98: 429a cmp r2, r3
8001e9a: d107 bne.n 8001eac <HAL_ADC_ConfigChannel+0x2b0>
{
/* Disable offset OFR1*/
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
8001e9c: 687b ldr r3, [r7, #4]
8001e9e: 681b ldr r3, [r3, #0]
8001ea0: 6e1a ldr r2, [r3, #96] @ 0x60
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 681b ldr r3, [r3, #0]
8001ea6: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
8001eaa: 661a str r2, [r3, #96] @ 0x60
}
if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
8001eac: 687b ldr r3, [r7, #4]
8001eae: 681b ldr r3, [r3, #0]
8001eb0: 6e5b ldr r3, [r3, #100] @ 0x64
8001eb2: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8001eb6: 683b ldr r3, [r7, #0]
8001eb8: 681b ldr r3, [r3, #0]
8001eba: 069b lsls r3, r3, #26
8001ebc: 429a cmp r2, r3
8001ebe: d107 bne.n 8001ed0 <HAL_ADC_ConfigChannel+0x2d4>
{
/* Disable offset OFR2*/
CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
8001ec0: 687b ldr r3, [r7, #4]
8001ec2: 681b ldr r3, [r3, #0]
8001ec4: 6e5a ldr r2, [r3, #100] @ 0x64
8001ec6: 687b ldr r3, [r7, #4]
8001ec8: 681b ldr r3, [r3, #0]
8001eca: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
8001ece: 665a str r2, [r3, #100] @ 0x64
}
if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
8001ed0: 687b ldr r3, [r7, #4]
8001ed2: 681b ldr r3, [r3, #0]
8001ed4: 6e9b ldr r3, [r3, #104] @ 0x68
8001ed6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8001eda: 683b ldr r3, [r7, #0]
8001edc: 681b ldr r3, [r3, #0]
8001ede: 069b lsls r3, r3, #26
8001ee0: 429a cmp r2, r3
8001ee2: d107 bne.n 8001ef4 <HAL_ADC_ConfigChannel+0x2f8>
{
/* Disable offset OFR3*/
CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
8001ee4: 687b ldr r3, [r7, #4]
8001ee6: 681b ldr r3, [r3, #0]
8001ee8: 6e9a ldr r2, [r3, #104] @ 0x68
8001eea: 687b ldr r3, [r7, #4]
8001eec: 681b ldr r3, [r3, #0]
8001eee: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
8001ef2: 669a str r2, [r3, #104] @ 0x68
}
if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
8001ef4: 687b ldr r3, [r7, #4]
8001ef6: 681b ldr r3, [r3, #0]
8001ef8: 6edb ldr r3, [r3, #108] @ 0x6c
8001efa: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8001efe: 683b ldr r3, [r7, #0]
8001f00: 681b ldr r3, [r3, #0]
8001f02: 069b lsls r3, r3, #26
8001f04: 429a cmp r2, r3
8001f06: d107 bne.n 8001f18 <HAL_ADC_ConfigChannel+0x31c>
{
/* Disable offset OFR4*/
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
8001f08: 687b ldr r3, [r7, #4]
8001f0a: 681b ldr r3, [r3, #0]
8001f0c: 6eda ldr r2, [r3, #108] @ 0x6c
8001f0e: 687b ldr r3, [r7, #4]
8001f10: 681b ldr r3, [r3, #0]
8001f12: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
8001f16: 66da str r2, [r3, #108] @ 0x6c
}
break;
8001f18: bf00 nop
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
if (ADC_IS_ENABLE(hadc) == RESET)
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 681b ldr r3, [r3, #0]
8001f1e: 689b ldr r3, [r3, #8]
8001f20: f003 0303 and.w r3, r3, #3
8001f24: 2b01 cmp r3, #1
8001f26: d108 bne.n 8001f3a <HAL_ADC_ConfigChannel+0x33e>
8001f28: 687b ldr r3, [r7, #4]
8001f2a: 681b ldr r3, [r3, #0]
8001f2c: 681b ldr r3, [r3, #0]
8001f2e: f003 0301 and.w r3, r3, #1
8001f32: 2b01 cmp r3, #1
8001f34: d101 bne.n 8001f3a <HAL_ADC_ConfigChannel+0x33e>
8001f36: 2301 movs r3, #1
8001f38: e000 b.n 8001f3c <HAL_ADC_ConfigChannel+0x340>
8001f3a: 2300 movs r3, #0
8001f3c: 2b00 cmp r3, #0
8001f3e: f040 810a bne.w 8002156 <HAL_ADC_ConfigChannel+0x55a>
{
/* Configuration of differential mode */
if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
8001f42: 683b ldr r3, [r7, #0]
8001f44: 68db ldr r3, [r3, #12]
8001f46: 2b01 cmp r3, #1
8001f48: d00f beq.n 8001f6a <HAL_ADC_ConfigChannel+0x36e>
{
/* Disable differential mode (default mode: single-ended) */
CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
8001f4a: 687b ldr r3, [r7, #4]
8001f4c: 681b ldr r3, [r3, #0]
8001f4e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0
8001f52: 683b ldr r3, [r7, #0]
8001f54: 681b ldr r3, [r3, #0]
8001f56: 2201 movs r2, #1
8001f58: fa02 f303 lsl.w r3, r2, r3
8001f5c: 43da mvns r2, r3
8001f5e: 687b ldr r3, [r7, #4]
8001f60: 681b ldr r3, [r3, #0]
8001f62: 400a ands r2, r1
8001f64: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
8001f68: e049 b.n 8001ffe <HAL_ADC_ConfigChannel+0x402>
}
else
{
/* Enable differential mode */
SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
8001f6a: 687b ldr r3, [r7, #4]
8001f6c: 681b ldr r3, [r3, #0]
8001f6e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0
8001f72: 683b ldr r3, [r7, #0]
8001f74: 681b ldr r3, [r3, #0]
8001f76: 2201 movs r2, #1
8001f78: 409a lsls r2, r3
8001f7a: 687b ldr r3, [r7, #4]
8001f7c: 681b ldr r3, [r3, #0]
8001f7e: 430a orrs r2, r1
8001f80: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
/* Channel sampling time configuration (channel ADC_INx +1 */
/* corresponding to differential negative input). */
/* For channels 10 to 18U */
if (sConfig->Channel >= ADC_CHANNEL_10)
8001f84: 683b ldr r3, [r7, #0]
8001f86: 681b ldr r3, [r3, #0]
8001f88: 2b09 cmp r3, #9
8001f8a: d91c bls.n 8001fc6 <HAL_ADC_ConfigChannel+0x3ca>
{
MODIFY_REG(hadc->Instance->SMPR2,
8001f8c: 687b ldr r3, [r7, #4]
8001f8e: 681b ldr r3, [r3, #0]
8001f90: 6999 ldr r1, [r3, #24]
8001f92: 683b ldr r3, [r7, #0]
8001f94: 681a ldr r2, [r3, #0]
8001f96: 4613 mov r3, r2
8001f98: 005b lsls r3, r3, #1
8001f9a: 4413 add r3, r2
8001f9c: 3b1b subs r3, #27
8001f9e: 2207 movs r2, #7
8001fa0: fa02 f303 lsl.w r3, r2, r3
8001fa4: 43db mvns r3, r3
8001fa6: 4019 ands r1, r3
8001fa8: 683b ldr r3, [r7, #0]
8001faa: 6898 ldr r0, [r3, #8]
8001fac: 683b ldr r3, [r7, #0]
8001fae: 681a ldr r2, [r3, #0]
8001fb0: 4613 mov r3, r2
8001fb2: 005b lsls r3, r3, #1
8001fb4: 4413 add r3, r2
8001fb6: 3b1b subs r3, #27
8001fb8: fa00 f203 lsl.w r2, r0, r3
8001fbc: 687b ldr r3, [r7, #4]
8001fbe: 681b ldr r3, [r3, #0]
8001fc0: 430a orrs r2, r1
8001fc2: 619a str r2, [r3, #24]
8001fc4: e01b b.n 8001ffe <HAL_ADC_ConfigChannel+0x402>
ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) ,
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) );
}
else /* For channels 1 to 9U */
{
MODIFY_REG(hadc->Instance->SMPR1,
8001fc6: 687b ldr r3, [r7, #4]
8001fc8: 681b ldr r3, [r3, #0]
8001fca: 6959 ldr r1, [r3, #20]
8001fcc: 683b ldr r3, [r7, #0]
8001fce: 681b ldr r3, [r3, #0]
8001fd0: 1c5a adds r2, r3, #1
8001fd2: 4613 mov r3, r2
8001fd4: 005b lsls r3, r3, #1
8001fd6: 4413 add r3, r2
8001fd8: 2207 movs r2, #7
8001fda: fa02 f303 lsl.w r3, r2, r3
8001fde: 43db mvns r3, r3
8001fe0: 4019 ands r1, r3
8001fe2: 683b ldr r3, [r7, #0]
8001fe4: 6898 ldr r0, [r3, #8]
8001fe6: 683b ldr r3, [r7, #0]
8001fe8: 681b ldr r3, [r3, #0]
8001fea: 1c5a adds r2, r3, #1
8001fec: 4613 mov r3, r2
8001fee: 005b lsls r3, r3, #1
8001ff0: 4413 add r3, r2
8001ff2: fa00 f203 lsl.w r2, r0, r3
8001ff6: 687b ldr r3, [r7, #4]
8001ff8: 681b ldr r3, [r3, #0]
8001ffa: 430a orrs r2, r1
8001ffc: 615a str r2, [r3, #20]
/* Configuration of common ADC parameters */
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
/* control registers) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
8001ffe: 4b1f ldr r3, [pc, #124] @ (800207c <HAL_ADC_ConfigChannel+0x480>)
8002000: 65fb str r3, [r7, #92] @ 0x5c
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
8002002: 683b ldr r3, [r7, #0]
8002004: 681b ldr r3, [r3, #0]
8002006: 2b10 cmp r3, #16
8002008: d105 bne.n 8002016 <HAL_ADC_ConfigChannel+0x41a>
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
800200a: 6dfb ldr r3, [r7, #92] @ 0x5c
800200c: 689b ldr r3, [r3, #8]
800200e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
8002012: 2b00 cmp r3, #0
8002014: d015 beq.n 8002042 <HAL_ADC_ConfigChannel+0x446>
( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
8002016: 683b ldr r3, [r7, #0]
8002018: 681b ldr r3, [r3, #0]
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
800201a: 2b11 cmp r3, #17
800201c: d105 bne.n 800202a <HAL_ADC_ConfigChannel+0x42e>
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
800201e: 6dfb ldr r3, [r7, #92] @ 0x5c
8002020: 689b ldr r3, [r3, #8]
8002022: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
8002026: 2b00 cmp r3, #0
8002028: d00b beq.n 8002042 <HAL_ADC_ConfigChannel+0x446>
( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
800202a: 683b ldr r3, [r7, #0]
800202c: 681b ldr r3, [r3, #0]
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
800202e: 2b12 cmp r3, #18
8002030: f040 8091 bne.w 8002156 <HAL_ADC_ConfigChannel+0x55a>
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
8002034: 6dfb ldr r3, [r7, #92] @ 0x5c
8002036: 689b ldr r3, [r3, #8]
8002038: f403 0380 and.w r3, r3, #4194304 @ 0x400000
( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
800203c: 2b00 cmp r3, #0
800203e: f040 808a bne.w 8002156 <HAL_ADC_ConfigChannel+0x55a>
)
{
/* Configuration of common ADC parameters (continuation) */
/* Set handle of the other ADC sharing the same common register */
ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
8002042: 687b ldr r3, [r7, #4]
8002044: 681b ldr r3, [r3, #0]
8002046: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
800204a: d102 bne.n 8002052 <HAL_ADC_ConfigChannel+0x456>
800204c: 4b0c ldr r3, [pc, #48] @ (8002080 <HAL_ADC_ConfigChannel+0x484>)
800204e: 60fb str r3, [r7, #12]
8002050: e002 b.n 8002058 <HAL_ADC_ConfigChannel+0x45c>
8002052: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8002056: 60fb str r3, [r7, #12]
/* Software is allowed to change common parameters only when all ADCs */
/* of the common group are disabled. */
if ((ADC_IS_ENABLE(hadc) == RESET) &&
8002058: 687b ldr r3, [r7, #4]
800205a: 681b ldr r3, [r3, #0]
800205c: 689b ldr r3, [r3, #8]
800205e: f003 0303 and.w r3, r3, #3
8002062: 2b01 cmp r3, #1
8002064: d10e bne.n 8002084 <HAL_ADC_ConfigChannel+0x488>
8002066: 687b ldr r3, [r7, #4]
8002068: 681b ldr r3, [r3, #0]
800206a: 681b ldr r3, [r3, #0]
800206c: f003 0301 and.w r3, r3, #1
8002070: 2b01 cmp r3, #1
8002072: d107 bne.n 8002084 <HAL_ADC_ConfigChannel+0x488>
8002074: 2301 movs r3, #1
8002076: e006 b.n 8002086 <HAL_ADC_ConfigChannel+0x48a>
8002078: 83fff000 .word 0x83fff000
800207c: 50000300 .word 0x50000300
8002080: 50000100 .word 0x50000100
8002084: 2300 movs r3, #0
8002086: 2b00 cmp r3, #0
8002088: d150 bne.n 800212c <HAL_ADC_ConfigChannel+0x530>
( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
800208a: 68fb ldr r3, [r7, #12]
if ((ADC_IS_ENABLE(hadc) == RESET) &&
800208c: 2b00 cmp r3, #0
800208e: d010 beq.n 80020b2 <HAL_ADC_ConfigChannel+0x4b6>
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
8002090: 68fb ldr r3, [r7, #12]
8002092: 689b ldr r3, [r3, #8]
8002094: f003 0303 and.w r3, r3, #3
8002098: 2b01 cmp r3, #1
800209a: d107 bne.n 80020ac <HAL_ADC_ConfigChannel+0x4b0>
800209c: 68fb ldr r3, [r7, #12]
800209e: 681b ldr r3, [r3, #0]
80020a0: f003 0301 and.w r3, r3, #1
80020a4: 2b01 cmp r3, #1
80020a6: d101 bne.n 80020ac <HAL_ADC_ConfigChannel+0x4b0>
80020a8: 2301 movs r3, #1
80020aa: e000 b.n 80020ae <HAL_ADC_ConfigChannel+0x4b2>
80020ac: 2300 movs r3, #0
( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
80020ae: 2b00 cmp r3, #0
80020b0: d13c bne.n 800212c <HAL_ADC_ConfigChannel+0x530>
{
/* If Channel_16 is selected, enable Temp. sensor measurement path */
/* Note: Temp. sensor internal channels available on ADC1 only */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
80020b2: 683b ldr r3, [r7, #0]
80020b4: 681b ldr r3, [r3, #0]
80020b6: 2b10 cmp r3, #16
80020b8: d11d bne.n 80020f6 <HAL_ADC_ConfigChannel+0x4fa>
80020ba: 687b ldr r3, [r7, #4]
80020bc: 681b ldr r3, [r3, #0]
80020be: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80020c2: d118 bne.n 80020f6 <HAL_ADC_ConfigChannel+0x4fa>
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
80020c4: 6dfb ldr r3, [r7, #92] @ 0x5c
80020c6: 689b ldr r3, [r3, #8]
80020c8: f443 0200 orr.w r2, r3, #8388608 @ 0x800000
80020cc: 6dfb ldr r3, [r7, #92] @ 0x5c
80020ce: 609a str r2, [r3, #8]
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
80020d0: 4b27 ldr r3, [pc, #156] @ (8002170 <HAL_ADC_ConfigChannel+0x574>)
80020d2: 681b ldr r3, [r3, #0]
80020d4: 4a27 ldr r2, [pc, #156] @ (8002174 <HAL_ADC_ConfigChannel+0x578>)
80020d6: fba2 2303 umull r2, r3, r2, r3
80020da: 0c9a lsrs r2, r3, #18
80020dc: 4613 mov r3, r2
80020de: 009b lsls r3, r3, #2
80020e0: 4413 add r3, r2
80020e2: 005b lsls r3, r3, #1
80020e4: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
80020e6: e002 b.n 80020ee <HAL_ADC_ConfigChannel+0x4f2>
{
wait_loop_index--;
80020e8: 68bb ldr r3, [r7, #8]
80020ea: 3b01 subs r3, #1
80020ec: 60bb str r3, [r7, #8]
while(wait_loop_index != 0U)
80020ee: 68bb ldr r3, [r7, #8]
80020f0: 2b00 cmp r3, #0
80020f2: d1f9 bne.n 80020e8 <HAL_ADC_ConfigChannel+0x4ec>
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
80020f4: e02e b.n 8002154 <HAL_ADC_ConfigChannel+0x558>
}
}
/* If Channel_17 is selected, enable VBAT measurement path */
/* Note: VBAT internal channels available on ADC1 only */
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
80020f6: 683b ldr r3, [r7, #0]
80020f8: 681b ldr r3, [r3, #0]
80020fa: 2b11 cmp r3, #17
80020fc: d10b bne.n 8002116 <HAL_ADC_ConfigChannel+0x51a>
80020fe: 687b ldr r3, [r7, #4]
8002100: 681b ldr r3, [r3, #0]
8002102: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002106: d106 bne.n 8002116 <HAL_ADC_ConfigChannel+0x51a>
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
8002108: 6dfb ldr r3, [r7, #92] @ 0x5c
800210a: 689b ldr r3, [r3, #8]
800210c: f043 7280 orr.w r2, r3, #16777216 @ 0x1000000
8002110: 6dfb ldr r3, [r7, #92] @ 0x5c
8002112: 609a str r2, [r3, #8]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
8002114: e01e b.n 8002154 <HAL_ADC_ConfigChannel+0x558>
}
/* If Channel_18 is selected, enable VREFINT measurement path */
/* Note: VrefInt internal channels available on all ADCs, but only */
/* one ADC is allowed to be connected to VrefInt at the same */
/* time. */
else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
8002116: 683b ldr r3, [r7, #0]
8002118: 681b ldr r3, [r3, #0]
800211a: 2b12 cmp r3, #18
800211c: d11a bne.n 8002154 <HAL_ADC_ConfigChannel+0x558>
{
SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
800211e: 6dfb ldr r3, [r7, #92] @ 0x5c
8002120: 689b ldr r3, [r3, #8]
8002122: f443 0280 orr.w r2, r3, #4194304 @ 0x400000
8002126: 6dfb ldr r3, [r7, #92] @ 0x5c
8002128: 609a str r2, [r3, #8]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
800212a: e013 b.n 8002154 <HAL_ADC_ConfigChannel+0x558>
/* enabled and other ADC of the common group are enabled, internal */
/* measurement paths cannot be enabled. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
800212c: 687b ldr r3, [r7, #4]
800212e: 6c1b ldr r3, [r3, #64] @ 0x40
8002130: f043 0220 orr.w r2, r3, #32
8002134: 687b ldr r3, [r7, #4]
8002136: 641a str r2, [r3, #64] @ 0x40
tmp_hal_status = HAL_ERROR;
8002138: 2301 movs r3, #1
800213a: f887 3067 strb.w r3, [r7, #103] @ 0x67
800213e: e00a b.n 8002156 <HAL_ADC_ConfigChannel+0x55a>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002140: 687b ldr r3, [r7, #4]
8002142: 6c1b ldr r3, [r3, #64] @ 0x40
8002144: f043 0220 orr.w r2, r3, #32
8002148: 687b ldr r3, [r7, #4]
800214a: 641a str r2, [r3, #64] @ 0x40
tmp_hal_status = HAL_ERROR;
800214c: 2301 movs r3, #1
800214e: f887 3067 strb.w r3, [r7, #103] @ 0x67
8002152: e000 b.n 8002156 <HAL_ADC_ConfigChannel+0x55a>
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
8002154: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002156: 687b ldr r3, [r7, #4]
8002158: 2200 movs r2, #0
800215a: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Return function status */
return tmp_hal_status;
800215e: f897 3067 ldrb.w r3, [r7, #103] @ 0x67
}
8002162: 4618 mov r0, r3
8002164: 376c adds r7, #108 @ 0x6c
8002166: 46bd mov sp, r7
8002168: f85d 7b04 ldr.w r7, [sp], #4
800216c: 4770 bx lr
800216e: bf00 nop
8002170: 20000000 .word 0x20000000
8002174: 431bde83 .word 0x431bde83
08002178 <HAL_ADCEx_MultiModeConfigChannel>:
* @param hadc ADC handle
* @param multimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
{
8002178: b480 push {r7}
800217a: b099 sub sp, #100 @ 0x64
800217c: af00 add r7, sp, #0
800217e: 6078 str r0, [r7, #4]
8002180: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002182: 2300 movs r3, #0
8002184: f887 305f strb.w r3, [r7, #95] @ 0x5f
assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
}
/* Set handle of the other ADC sharing the same common register */
ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
8002188: 687b ldr r3, [r7, #4]
800218a: 681b ldr r3, [r3, #0]
800218c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002190: d102 bne.n 8002198 <HAL_ADCEx_MultiModeConfigChannel+0x20>
8002192: 4b5a ldr r3, [pc, #360] @ (80022fc <HAL_ADCEx_MultiModeConfigChannel+0x184>)
8002194: 60bb str r3, [r7, #8]
8002196: e002 b.n 800219e <HAL_ADCEx_MultiModeConfigChannel+0x26>
8002198: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
800219c: 60bb str r3, [r7, #8]
if (tmphadcSharingSameCommonRegister.Instance == NULL)
800219e: 68bb ldr r3, [r7, #8]
80021a0: 2b00 cmp r3, #0
80021a2: d101 bne.n 80021a8 <HAL_ADCEx_MultiModeConfigChannel+0x30>
{
/* Return function status */
return HAL_ERROR;
80021a4: 2301 movs r3, #1
80021a6: e0a2 b.n 80022ee <HAL_ADCEx_MultiModeConfigChannel+0x176>
}
/* Process locked */
__HAL_LOCK(hadc);
80021a8: 687b ldr r3, [r7, #4]
80021aa: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80021ae: 2b01 cmp r3, #1
80021b0: d101 bne.n 80021b6 <HAL_ADCEx_MultiModeConfigChannel+0x3e>
80021b2: 2302 movs r3, #2
80021b4: e09b b.n 80022ee <HAL_ADCEx_MultiModeConfigChannel+0x176>
80021b6: 687b ldr r3, [r7, #4]
80021b8: 2201 movs r2, #1
80021ba: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
80021be: 687b ldr r3, [r7, #4]
80021c0: 681b ldr r3, [r3, #0]
80021c2: 689b ldr r3, [r3, #8]
80021c4: f003 0304 and.w r3, r3, #4
80021c8: 2b00 cmp r3, #0
80021ca: d17f bne.n 80022cc <HAL_ADCEx_MultiModeConfigChannel+0x154>
&& (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) )
80021cc: 68bb ldr r3, [r7, #8]
80021ce: 689b ldr r3, [r3, #8]
80021d0: f003 0304 and.w r3, r3, #4
80021d4: 2b00 cmp r3, #0
80021d6: d179 bne.n 80022cc <HAL_ADCEx_MultiModeConfigChannel+0x154>
{
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
/* control registers) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
80021d8: 4b49 ldr r3, [pc, #292] @ (8002300 <HAL_ADCEx_MultiModeConfigChannel+0x188>)
80021da: 65bb str r3, [r7, #88] @ 0x58
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if(multimode->Mode != ADC_MODE_INDEPENDENT)
80021dc: 683b ldr r3, [r7, #0]
80021de: 681b ldr r3, [r3, #0]
80021e0: 2b00 cmp r3, #0
80021e2: d040 beq.n 8002266 <HAL_ADCEx_MultiModeConfigChannel+0xee>
{
/* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
/* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
/* - DMA access mode */
MODIFY_REG(tmpADC_Common->CCR ,
80021e4: 6dbb ldr r3, [r7, #88] @ 0x58
80021e6: 689b ldr r3, [r3, #8]
80021e8: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80021ec: 683b ldr r3, [r7, #0]
80021ee: 6859 ldr r1, [r3, #4]
80021f0: 687b ldr r3, [r7, #4]
80021f2: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
80021f6: 035b lsls r3, r3, #13
80021f8: 430b orrs r3, r1
80021fa: 431a orrs r2, r3
80021fc: 6dbb ldr r3, [r7, #88] @ 0x58
80021fe: 609a str r2, [r3, #8]
/* parameters, their setting is bypassed without error reporting */
/* (as it can be the expected behaviour in case of intended action */
/* to update parameter above (which fulfills the ADC state */
/* condition: no conversion on going on group regular) */
/* on the fly). */
if ((ADC_IS_ENABLE(hadc) == RESET) &&
8002200: 687b ldr r3, [r7, #4]
8002202: 681b ldr r3, [r3, #0]
8002204: 689b ldr r3, [r3, #8]
8002206: f003 0303 and.w r3, r3, #3
800220a: 2b01 cmp r3, #1
800220c: d108 bne.n 8002220 <HAL_ADCEx_MultiModeConfigChannel+0xa8>
800220e: 687b ldr r3, [r7, #4]
8002210: 681b ldr r3, [r3, #0]
8002212: 681b ldr r3, [r3, #0]
8002214: f003 0301 and.w r3, r3, #1
8002218: 2b01 cmp r3, #1
800221a: d101 bne.n 8002220 <HAL_ADCEx_MultiModeConfigChannel+0xa8>
800221c: 2301 movs r3, #1
800221e: e000 b.n 8002222 <HAL_ADCEx_MultiModeConfigChannel+0xaa>
8002220: 2300 movs r3, #0
8002222: 2b00 cmp r3, #0
8002224: d15c bne.n 80022e0 <HAL_ADCEx_MultiModeConfigChannel+0x168>
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
8002226: 68bb ldr r3, [r7, #8]
8002228: 689b ldr r3, [r3, #8]
800222a: f003 0303 and.w r3, r3, #3
800222e: 2b01 cmp r3, #1
8002230: d107 bne.n 8002242 <HAL_ADCEx_MultiModeConfigChannel+0xca>
8002232: 68bb ldr r3, [r7, #8]
8002234: 681b ldr r3, [r3, #0]
8002236: f003 0301 and.w r3, r3, #1
800223a: 2b01 cmp r3, #1
800223c: d101 bne.n 8002242 <HAL_ADCEx_MultiModeConfigChannel+0xca>
800223e: 2301 movs r3, #1
8002240: e000 b.n 8002244 <HAL_ADCEx_MultiModeConfigChannel+0xcc>
8002242: 2300 movs r3, #0
if ((ADC_IS_ENABLE(hadc) == RESET) &&
8002244: 2b00 cmp r3, #0
8002246: d14b bne.n 80022e0 <HAL_ADCEx_MultiModeConfigChannel+0x168>
{
MODIFY_REG(tmpADC_Common->CCR ,
8002248: 6dbb ldr r3, [r7, #88] @ 0x58
800224a: 689b ldr r3, [r3, #8]
800224c: f423 6371 bic.w r3, r3, #3856 @ 0xf10
8002250: f023 030f bic.w r3, r3, #15
8002254: 683a ldr r2, [r7, #0]
8002256: 6811 ldr r1, [r2, #0]
8002258: 683a ldr r2, [r7, #0]
800225a: 6892 ldr r2, [r2, #8]
800225c: 430a orrs r2, r1
800225e: 431a orrs r2, r3
8002260: 6dbb ldr r3, [r7, #88] @ 0x58
8002262: 609a str r2, [r3, #8]
if(multimode->Mode != ADC_MODE_INDEPENDENT)
8002264: e03c b.n 80022e0 <HAL_ADCEx_MultiModeConfigChannel+0x168>
multimode->TwoSamplingDelay );
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
8002266: 6dbb ldr r3, [r7, #88] @ 0x58
8002268: 689b ldr r3, [r3, #8]
800226a: f423 4260 bic.w r2, r3, #57344 @ 0xe000
800226e: 6dbb ldr r3, [r7, #88] @ 0x58
8002270: 609a str r2, [r3, #8]
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if ((ADC_IS_ENABLE(hadc) == RESET) &&
8002272: 687b ldr r3, [r7, #4]
8002274: 681b ldr r3, [r3, #0]
8002276: 689b ldr r3, [r3, #8]
8002278: f003 0303 and.w r3, r3, #3
800227c: 2b01 cmp r3, #1
800227e: d108 bne.n 8002292 <HAL_ADCEx_MultiModeConfigChannel+0x11a>
8002280: 687b ldr r3, [r7, #4]
8002282: 681b ldr r3, [r3, #0]
8002284: 681b ldr r3, [r3, #0]
8002286: f003 0301 and.w r3, r3, #1
800228a: 2b01 cmp r3, #1
800228c: d101 bne.n 8002292 <HAL_ADCEx_MultiModeConfigChannel+0x11a>
800228e: 2301 movs r3, #1
8002290: e000 b.n 8002294 <HAL_ADCEx_MultiModeConfigChannel+0x11c>
8002292: 2300 movs r3, #0
8002294: 2b00 cmp r3, #0
8002296: d123 bne.n 80022e0 <HAL_ADCEx_MultiModeConfigChannel+0x168>
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
8002298: 68bb ldr r3, [r7, #8]
800229a: 689b ldr r3, [r3, #8]
800229c: f003 0303 and.w r3, r3, #3
80022a0: 2b01 cmp r3, #1
80022a2: d107 bne.n 80022b4 <HAL_ADCEx_MultiModeConfigChannel+0x13c>
80022a4: 68bb ldr r3, [r7, #8]
80022a6: 681b ldr r3, [r3, #0]
80022a8: f003 0301 and.w r3, r3, #1
80022ac: 2b01 cmp r3, #1
80022ae: d101 bne.n 80022b4 <HAL_ADCEx_MultiModeConfigChannel+0x13c>
80022b0: 2301 movs r3, #1
80022b2: e000 b.n 80022b6 <HAL_ADCEx_MultiModeConfigChannel+0x13e>
80022b4: 2300 movs r3, #0
if ((ADC_IS_ENABLE(hadc) == RESET) &&
80022b6: 2b00 cmp r3, #0
80022b8: d112 bne.n 80022e0 <HAL_ADCEx_MultiModeConfigChannel+0x168>
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY);
80022ba: 6dbb ldr r3, [r7, #88] @ 0x58
80022bc: 689b ldr r3, [r3, #8]
80022be: f423 6371 bic.w r3, r3, #3856 @ 0xf10
80022c2: f023 030f bic.w r3, r3, #15
80022c6: 6dba ldr r2, [r7, #88] @ 0x58
80022c8: 6093 str r3, [r2, #8]
if(multimode->Mode != ADC_MODE_INDEPENDENT)
80022ca: e009 b.n 80022e0 <HAL_ADCEx_MultiModeConfigChannel+0x168>
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80022cc: 687b ldr r3, [r7, #4]
80022ce: 6c1b ldr r3, [r3, #64] @ 0x40
80022d0: f043 0220 orr.w r2, r3, #32
80022d4: 687b ldr r3, [r7, #4]
80022d6: 641a str r2, [r3, #64] @ 0x40
tmp_hal_status = HAL_ERROR;
80022d8: 2301 movs r3, #1
80022da: f887 305f strb.w r3, [r7, #95] @ 0x5f
80022de: e000 b.n 80022e2 <HAL_ADCEx_MultiModeConfigChannel+0x16a>
if(multimode->Mode != ADC_MODE_INDEPENDENT)
80022e0: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80022e2: 687b ldr r3, [r7, #4]
80022e4: 2200 movs r2, #0
80022e6: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Return function status */
return tmp_hal_status;
80022ea: f897 305f ldrb.w r3, [r7, #95] @ 0x5f
}
80022ee: 4618 mov r0, r3
80022f0: 3764 adds r7, #100 @ 0x64
80022f2: 46bd mov sp, r7
80022f4: f85d 7b04 ldr.w r7, [sp], #4
80022f8: 4770 bx lr
80022fa: bf00 nop
80022fc: 50000100 .word 0x50000100
8002300: 50000300 .word 0x50000300
08002304 <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
{
8002304: b580 push {r7, lr}
8002306: b084 sub sp, #16
8002308: af00 add r7, sp, #0
800230a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
800230c: 2300 movs r3, #0
800230e: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if (ADC_IS_ENABLE(hadc) != RESET )
8002310: 687b ldr r3, [r7, #4]
8002312: 681b ldr r3, [r3, #0]
8002314: 689b ldr r3, [r3, #8]
8002316: f003 0303 and.w r3, r3, #3
800231a: 2b01 cmp r3, #1
800231c: d108 bne.n 8002330 <ADC_Disable+0x2c>
800231e: 687b ldr r3, [r7, #4]
8002320: 681b ldr r3, [r3, #0]
8002322: 681b ldr r3, [r3, #0]
8002324: f003 0301 and.w r3, r3, #1
8002328: 2b01 cmp r3, #1
800232a: d101 bne.n 8002330 <ADC_Disable+0x2c>
800232c: 2301 movs r3, #1
800232e: e000 b.n 8002332 <ADC_Disable+0x2e>
8002330: 2300 movs r3, #0
8002332: 2b00 cmp r3, #0
8002334: d047 beq.n 80023c6 <ADC_Disable+0xc2>
{
/* Check if conditions to disable the ADC are fulfilled */
if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
8002336: 687b ldr r3, [r7, #4]
8002338: 681b ldr r3, [r3, #0]
800233a: 689b ldr r3, [r3, #8]
800233c: f003 030d and.w r3, r3, #13
8002340: 2b01 cmp r3, #1
8002342: d10f bne.n 8002364 <ADC_Disable+0x60>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
8002344: 687b ldr r3, [r7, #4]
8002346: 681b ldr r3, [r3, #0]
8002348: 689a ldr r2, [r3, #8]
800234a: 687b ldr r3, [r7, #4]
800234c: 681b ldr r3, [r3, #0]
800234e: f042 0202 orr.w r2, r2, #2
8002352: 609a str r2, [r3, #8]
8002354: 687b ldr r3, [r7, #4]
8002356: 681b ldr r3, [r3, #0]
8002358: 2203 movs r2, #3
800235a: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
tickstart = HAL_GetTick();
800235c: f7ff f84c bl 80013f8 <HAL_GetTick>
8002360: 60f8 str r0, [r7, #12]
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
8002362: e029 b.n 80023b8 <ADC_Disable+0xb4>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002364: 687b ldr r3, [r7, #4]
8002366: 6c1b ldr r3, [r3, #64] @ 0x40
8002368: f043 0210 orr.w r2, r3, #16
800236c: 687b ldr r3, [r7, #4]
800236e: 641a str r2, [r3, #64] @ 0x40
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002370: 687b ldr r3, [r7, #4]
8002372: 6c5b ldr r3, [r3, #68] @ 0x44
8002374: f043 0201 orr.w r2, r3, #1
8002378: 687b ldr r3, [r7, #4]
800237a: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
800237c: 2301 movs r3, #1
800237e: e023 b.n 80023c8 <ADC_Disable+0xc4>
{
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8002380: f7ff f83a bl 80013f8 <HAL_GetTick>
8002384: 4602 mov r2, r0
8002386: 68fb ldr r3, [r7, #12]
8002388: 1ad3 subs r3, r2, r3
800238a: 2b02 cmp r3, #2
800238c: d914 bls.n 80023b8 <ADC_Disable+0xb4>
{
/* New check to avoid false timeout detection in case of preemption */
if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
800238e: 687b ldr r3, [r7, #4]
8002390: 681b ldr r3, [r3, #0]
8002392: 689b ldr r3, [r3, #8]
8002394: f003 0301 and.w r3, r3, #1
8002398: 2b01 cmp r3, #1
800239a: d10d bne.n 80023b8 <ADC_Disable+0xb4>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800239c: 687b ldr r3, [r7, #4]
800239e: 6c1b ldr r3, [r3, #64] @ 0x40
80023a0: f043 0210 orr.w r2, r3, #16
80023a4: 687b ldr r3, [r7, #4]
80023a6: 641a str r2, [r3, #64] @ 0x40
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80023a8: 687b ldr r3, [r7, #4]
80023aa: 6c5b ldr r3, [r3, #68] @ 0x44
80023ac: f043 0201 orr.w r2, r3, #1
80023b0: 687b ldr r3, [r7, #4]
80023b2: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
80023b4: 2301 movs r3, #1
80023b6: e007 b.n 80023c8 <ADC_Disable+0xc4>
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
80023b8: 687b ldr r3, [r7, #4]
80023ba: 681b ldr r3, [r3, #0]
80023bc: 689b ldr r3, [r3, #8]
80023be: f003 0301 and.w r3, r3, #1
80023c2: 2b01 cmp r3, #1
80023c4: d0dc beq.n 8002380 <ADC_Disable+0x7c>
}
}
}
/* Return HAL status */
return HAL_OK;
80023c6: 2300 movs r3, #0
}
80023c8: 4618 mov r0, r3
80023ca: 3710 adds r7, #16
80023cc: 46bd mov sp, r7
80023ce: bd80 pop {r7, pc}
080023d0 <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
80023d0: b580 push {r7, lr}
80023d2: b084 sub sp, #16
80023d4: af00 add r7, sp, #0
80023d6: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
80023d8: 687b ldr r3, [r7, #4]
80023da: 2b00 cmp r3, #0
80023dc: d101 bne.n 80023e2 <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
80023de: 2301 movs r3, #1
80023e0: e0ed b.n 80025be <HAL_CAN_Init+0x1ee>
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
}
#else
if (hcan->State == HAL_CAN_STATE_RESET)
80023e2: 687b ldr r3, [r7, #4]
80023e4: f893 3020 ldrb.w r3, [r3, #32]
80023e8: b2db uxtb r3, r3
80023ea: 2b00 cmp r3, #0
80023ec: d102 bne.n 80023f4 <HAL_CAN_Init+0x24>
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
80023ee: 6878 ldr r0, [r7, #4]
80023f0: f7fe fe3e bl 8001070 <HAL_CAN_MspInit>
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
80023f4: 687b ldr r3, [r7, #4]
80023f6: 681b ldr r3, [r3, #0]
80023f8: 681a ldr r2, [r3, #0]
80023fa: 687b ldr r3, [r7, #4]
80023fc: 681b ldr r3, [r3, #0]
80023fe: f042 0201 orr.w r2, r2, #1
8002402: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002404: f7fe fff8 bl 80013f8 <HAL_GetTick>
8002408: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
800240a: e012 b.n 8002432 <HAL_CAN_Init+0x62>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
800240c: f7fe fff4 bl 80013f8 <HAL_GetTick>
8002410: 4602 mov r2, r0
8002412: 68fb ldr r3, [r7, #12]
8002414: 1ad3 subs r3, r2, r3
8002416: 2b0a cmp r3, #10
8002418: d90b bls.n 8002432 <HAL_CAN_Init+0x62>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
800241a: 687b ldr r3, [r7, #4]
800241c: 6a5b ldr r3, [r3, #36] @ 0x24
800241e: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8002422: 687b ldr r3, [r7, #4]
8002424: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8002426: 687b ldr r3, [r7, #4]
8002428: 2205 movs r2, #5
800242a: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
800242e: 2301 movs r3, #1
8002430: e0c5 b.n 80025be <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8002432: 687b ldr r3, [r7, #4]
8002434: 681b ldr r3, [r3, #0]
8002436: 685b ldr r3, [r3, #4]
8002438: f003 0301 and.w r3, r3, #1
800243c: 2b00 cmp r3, #0
800243e: d0e5 beq.n 800240c <HAL_CAN_Init+0x3c>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
8002440: 687b ldr r3, [r7, #4]
8002442: 681b ldr r3, [r3, #0]
8002444: 681a ldr r2, [r3, #0]
8002446: 687b ldr r3, [r7, #4]
8002448: 681b ldr r3, [r3, #0]
800244a: f022 0202 bic.w r2, r2, #2
800244e: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002450: f7fe ffd2 bl 80013f8 <HAL_GetTick>
8002454: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8002456: e012 b.n 800247e <HAL_CAN_Init+0xae>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8002458: f7fe ffce bl 80013f8 <HAL_GetTick>
800245c: 4602 mov r2, r0
800245e: 68fb ldr r3, [r7, #12]
8002460: 1ad3 subs r3, r2, r3
8002462: 2b0a cmp r3, #10
8002464: d90b bls.n 800247e <HAL_CAN_Init+0xae>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8002466: 687b ldr r3, [r7, #4]
8002468: 6a5b ldr r3, [r3, #36] @ 0x24
800246a: f443 3200 orr.w r2, r3, #131072 @ 0x20000
800246e: 687b ldr r3, [r7, #4]
8002470: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8002472: 687b ldr r3, [r7, #4]
8002474: 2205 movs r2, #5
8002476: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
800247a: 2301 movs r3, #1
800247c: e09f b.n 80025be <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
800247e: 687b ldr r3, [r7, #4]
8002480: 681b ldr r3, [r3, #0]
8002482: 685b ldr r3, [r3, #4]
8002484: f003 0302 and.w r3, r3, #2
8002488: 2b00 cmp r3, #0
800248a: d1e5 bne.n 8002458 <HAL_CAN_Init+0x88>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
800248c: 687b ldr r3, [r7, #4]
800248e: 7e1b ldrb r3, [r3, #24]
8002490: 2b01 cmp r3, #1
8002492: d108 bne.n 80024a6 <HAL_CAN_Init+0xd6>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8002494: 687b ldr r3, [r7, #4]
8002496: 681b ldr r3, [r3, #0]
8002498: 681a ldr r2, [r3, #0]
800249a: 687b ldr r3, [r7, #4]
800249c: 681b ldr r3, [r3, #0]
800249e: f042 0280 orr.w r2, r2, #128 @ 0x80
80024a2: 601a str r2, [r3, #0]
80024a4: e007 b.n 80024b6 <HAL_CAN_Init+0xe6>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
80024a6: 687b ldr r3, [r7, #4]
80024a8: 681b ldr r3, [r3, #0]
80024aa: 681a ldr r2, [r3, #0]
80024ac: 687b ldr r3, [r7, #4]
80024ae: 681b ldr r3, [r3, #0]
80024b0: f022 0280 bic.w r2, r2, #128 @ 0x80
80024b4: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
80024b6: 687b ldr r3, [r7, #4]
80024b8: 7e5b ldrb r3, [r3, #25]
80024ba: 2b01 cmp r3, #1
80024bc: d108 bne.n 80024d0 <HAL_CAN_Init+0x100>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
80024be: 687b ldr r3, [r7, #4]
80024c0: 681b ldr r3, [r3, #0]
80024c2: 681a ldr r2, [r3, #0]
80024c4: 687b ldr r3, [r7, #4]
80024c6: 681b ldr r3, [r3, #0]
80024c8: f042 0240 orr.w r2, r2, #64 @ 0x40
80024cc: 601a str r2, [r3, #0]
80024ce: e007 b.n 80024e0 <HAL_CAN_Init+0x110>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
80024d0: 687b ldr r3, [r7, #4]
80024d2: 681b ldr r3, [r3, #0]
80024d4: 681a ldr r2, [r3, #0]
80024d6: 687b ldr r3, [r7, #4]
80024d8: 681b ldr r3, [r3, #0]
80024da: f022 0240 bic.w r2, r2, #64 @ 0x40
80024de: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
80024e0: 687b ldr r3, [r7, #4]
80024e2: 7e9b ldrb r3, [r3, #26]
80024e4: 2b01 cmp r3, #1
80024e6: d108 bne.n 80024fa <HAL_CAN_Init+0x12a>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
80024e8: 687b ldr r3, [r7, #4]
80024ea: 681b ldr r3, [r3, #0]
80024ec: 681a ldr r2, [r3, #0]
80024ee: 687b ldr r3, [r7, #4]
80024f0: 681b ldr r3, [r3, #0]
80024f2: f042 0220 orr.w r2, r2, #32
80024f6: 601a str r2, [r3, #0]
80024f8: e007 b.n 800250a <HAL_CAN_Init+0x13a>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
80024fa: 687b ldr r3, [r7, #4]
80024fc: 681b ldr r3, [r3, #0]
80024fe: 681a ldr r2, [r3, #0]
8002500: 687b ldr r3, [r7, #4]
8002502: 681b ldr r3, [r3, #0]
8002504: f022 0220 bic.w r2, r2, #32
8002508: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
800250a: 687b ldr r3, [r7, #4]
800250c: 7edb ldrb r3, [r3, #27]
800250e: 2b01 cmp r3, #1
8002510: d108 bne.n 8002524 <HAL_CAN_Init+0x154>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8002512: 687b ldr r3, [r7, #4]
8002514: 681b ldr r3, [r3, #0]
8002516: 681a ldr r2, [r3, #0]
8002518: 687b ldr r3, [r7, #4]
800251a: 681b ldr r3, [r3, #0]
800251c: f022 0210 bic.w r2, r2, #16
8002520: 601a str r2, [r3, #0]
8002522: e007 b.n 8002534 <HAL_CAN_Init+0x164>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8002524: 687b ldr r3, [r7, #4]
8002526: 681b ldr r3, [r3, #0]
8002528: 681a ldr r2, [r3, #0]
800252a: 687b ldr r3, [r7, #4]
800252c: 681b ldr r3, [r3, #0]
800252e: f042 0210 orr.w r2, r2, #16
8002532: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
8002534: 687b ldr r3, [r7, #4]
8002536: 7f1b ldrb r3, [r3, #28]
8002538: 2b01 cmp r3, #1
800253a: d108 bne.n 800254e <HAL_CAN_Init+0x17e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
800253c: 687b ldr r3, [r7, #4]
800253e: 681b ldr r3, [r3, #0]
8002540: 681a ldr r2, [r3, #0]
8002542: 687b ldr r3, [r7, #4]
8002544: 681b ldr r3, [r3, #0]
8002546: f042 0208 orr.w r2, r2, #8
800254a: 601a str r2, [r3, #0]
800254c: e007 b.n 800255e <HAL_CAN_Init+0x18e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
800254e: 687b ldr r3, [r7, #4]
8002550: 681b ldr r3, [r3, #0]
8002552: 681a ldr r2, [r3, #0]
8002554: 687b ldr r3, [r7, #4]
8002556: 681b ldr r3, [r3, #0]
8002558: f022 0208 bic.w r2, r2, #8
800255c: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
800255e: 687b ldr r3, [r7, #4]
8002560: 7f5b ldrb r3, [r3, #29]
8002562: 2b01 cmp r3, #1
8002564: d108 bne.n 8002578 <HAL_CAN_Init+0x1a8>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8002566: 687b ldr r3, [r7, #4]
8002568: 681b ldr r3, [r3, #0]
800256a: 681a ldr r2, [r3, #0]
800256c: 687b ldr r3, [r7, #4]
800256e: 681b ldr r3, [r3, #0]
8002570: f042 0204 orr.w r2, r2, #4
8002574: 601a str r2, [r3, #0]
8002576: e007 b.n 8002588 <HAL_CAN_Init+0x1b8>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8002578: 687b ldr r3, [r7, #4]
800257a: 681b ldr r3, [r3, #0]
800257c: 681a ldr r2, [r3, #0]
800257e: 687b ldr r3, [r7, #4]
8002580: 681b ldr r3, [r3, #0]
8002582: f022 0204 bic.w r2, r2, #4
8002586: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
8002588: 687b ldr r3, [r7, #4]
800258a: 689a ldr r2, [r3, #8]
800258c: 687b ldr r3, [r7, #4]
800258e: 68db ldr r3, [r3, #12]
8002590: 431a orrs r2, r3
8002592: 687b ldr r3, [r7, #4]
8002594: 691b ldr r3, [r3, #16]
8002596: 431a orrs r2, r3
8002598: 687b ldr r3, [r7, #4]
800259a: 695b ldr r3, [r3, #20]
800259c: ea42 0103 orr.w r1, r2, r3
80025a0: 687b ldr r3, [r7, #4]
80025a2: 685b ldr r3, [r3, #4]
80025a4: 1e5a subs r2, r3, #1
80025a6: 687b ldr r3, [r7, #4]
80025a8: 681b ldr r3, [r3, #0]
80025aa: 430a orrs r2, r1
80025ac: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
80025ae: 687b ldr r3, [r7, #4]
80025b0: 2200 movs r2, #0
80025b2: 625a str r2, [r3, #36] @ 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
80025b4: 687b ldr r3, [r7, #4]
80025b6: 2201 movs r2, #1
80025b8: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
80025bc: 2300 movs r3, #0
}
80025be: 4618 mov r0, r3
80025c0: 3710 adds r7, #16
80025c2: 46bd mov sp, r7
80025c4: bd80 pop {r7, pc}
080025c6 <HAL_CAN_ConfigFilter>:
* @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
{
80025c6: b480 push {r7}
80025c8: b087 sub sp, #28
80025ca: af00 add r7, sp, #0
80025cc: 6078 str r0, [r7, #4]
80025ce: 6039 str r1, [r7, #0]
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
80025d0: 687b ldr r3, [r7, #4]
80025d2: 681b ldr r3, [r3, #0]
80025d4: 617b str r3, [r7, #20]
HAL_CAN_StateTypeDef state = hcan->State;
80025d6: 687b ldr r3, [r7, #4]
80025d8: f893 3020 ldrb.w r3, [r3, #32]
80025dc: 74fb strb r3, [r7, #19]
if ((state == HAL_CAN_STATE_READY) ||
80025de: 7cfb ldrb r3, [r7, #19]
80025e0: 2b01 cmp r3, #1
80025e2: d003 beq.n 80025ec <HAL_CAN_ConfigFilter+0x26>
80025e4: 7cfb ldrb r3, [r7, #19]
80025e6: 2b02 cmp r3, #2
80025e8: f040 80aa bne.w 8002740 <HAL_CAN_ConfigFilter+0x17a>
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
80025ec: 697b ldr r3, [r7, #20]
80025ee: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200
80025f2: f043 0201 orr.w r2, r3, #1
80025f6: 697b ldr r3, [r7, #20]
80025f8: f8c3 2200 str.w r2, [r3, #512] @ 0x200
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
80025fc: 683b ldr r3, [r7, #0]
80025fe: 695b ldr r3, [r3, #20]
8002600: f003 031f and.w r3, r3, #31
8002604: 2201 movs r2, #1
8002606: fa02 f303 lsl.w r3, r2, r3
800260a: 60fb str r3, [r7, #12]
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
800260c: 697b ldr r3, [r7, #20]
800260e: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c
8002612: 68fb ldr r3, [r7, #12]
8002614: 43db mvns r3, r3
8002616: 401a ands r2, r3
8002618: 697b ldr r3, [r7, #20]
800261a: f8c3 221c str.w r2, [r3, #540] @ 0x21c
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
800261e: 683b ldr r3, [r7, #0]
8002620: 69db ldr r3, [r3, #28]
8002622: 2b00 cmp r3, #0
8002624: d123 bne.n 800266e <HAL_CAN_ConfigFilter+0xa8>
{
/* 16-bit scale for the filter */
CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
8002626: 697b ldr r3, [r7, #20]
8002628: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c
800262c: 68fb ldr r3, [r7, #12]
800262e: 43db mvns r3, r3
8002630: 401a ands r2, r3
8002632: 697b ldr r3, [r7, #20]
8002634: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8002638: 683b ldr r3, [r7, #0]
800263a: 68db ldr r3, [r3, #12]
800263c: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
800263e: 683b ldr r3, [r7, #0]
8002640: 685b ldr r3, [r3, #4]
8002642: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8002644: 683a ldr r2, [r7, #0]
8002646: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8002648: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
800264a: 697b ldr r3, [r7, #20]
800264c: 3248 adds r2, #72 @ 0x48
800264e: f843 1032 str.w r1, [r3, r2, lsl #3]
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8002652: 683b ldr r3, [r7, #0]
8002654: 689b ldr r3, [r3, #8]
8002656: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
8002658: 683b ldr r3, [r7, #0]
800265a: 681b ldr r3, [r3, #0]
800265c: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
800265e: 683b ldr r3, [r7, #0]
8002660: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8002662: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8002664: 6979 ldr r1, [r7, #20]
8002666: 3348 adds r3, #72 @ 0x48
8002668: 00db lsls r3, r3, #3
800266a: 440b add r3, r1
800266c: 605a str r2, [r3, #4]
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
800266e: 683b ldr r3, [r7, #0]
8002670: 69db ldr r3, [r3, #28]
8002672: 2b01 cmp r3, #1
8002674: d122 bne.n 80026bc <HAL_CAN_ConfigFilter+0xf6>
{
/* 32-bit scale for the filter */
SET_BIT(can_ip->FS1R, filternbrbitpos);
8002676: 697b ldr r3, [r7, #20]
8002678: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c
800267c: 68fb ldr r3, [r7, #12]
800267e: 431a orrs r2, r3
8002680: 697b ldr r3, [r7, #20]
8002682: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* 32-bit identifier or First 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8002686: 683b ldr r3, [r7, #0]
8002688: 681b ldr r3, [r3, #0]
800268a: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
800268c: 683b ldr r3, [r7, #0]
800268e: 685b ldr r3, [r3, #4]
8002690: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8002692: 683a ldr r2, [r7, #0]
8002694: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8002696: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8002698: 697b ldr r3, [r7, #20]
800269a: 3248 adds r2, #72 @ 0x48
800269c: f843 1032 str.w r1, [r3, r2, lsl #3]
/* 32-bit mask or Second 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
80026a0: 683b ldr r3, [r7, #0]
80026a2: 689b ldr r3, [r3, #8]
80026a4: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
80026a6: 683b ldr r3, [r7, #0]
80026a8: 68db ldr r3, [r3, #12]
80026aa: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
80026ac: 683b ldr r3, [r7, #0]
80026ae: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
80026b0: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
80026b2: 6979 ldr r1, [r7, #20]
80026b4: 3348 adds r3, #72 @ 0x48
80026b6: 00db lsls r3, r3, #3
80026b8: 440b add r3, r1
80026ba: 605a str r2, [r3, #4]
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
80026bc: 683b ldr r3, [r7, #0]
80026be: 699b ldr r3, [r3, #24]
80026c0: 2b00 cmp r3, #0
80026c2: d109 bne.n 80026d8 <HAL_CAN_ConfigFilter+0x112>
{
/* Id/Mask mode for the filter*/
CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
80026c4: 697b ldr r3, [r7, #20]
80026c6: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
80026ca: 68fb ldr r3, [r7, #12]
80026cc: 43db mvns r3, r3
80026ce: 401a ands r2, r3
80026d0: 697b ldr r3, [r7, #20]
80026d2: f8c3 2204 str.w r2, [r3, #516] @ 0x204
80026d6: e007 b.n 80026e8 <HAL_CAN_ConfigFilter+0x122>
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/* Identifier list mode for the filter*/
SET_BIT(can_ip->FM1R, filternbrbitpos);
80026d8: 697b ldr r3, [r7, #20]
80026da: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
80026de: 68fb ldr r3, [r7, #12]
80026e0: 431a orrs r2, r3
80026e2: 697b ldr r3, [r7, #20]
80026e4: f8c3 2204 str.w r2, [r3, #516] @ 0x204
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
80026e8: 683b ldr r3, [r7, #0]
80026ea: 691b ldr r3, [r3, #16]
80026ec: 2b00 cmp r3, #0
80026ee: d109 bne.n 8002704 <HAL_CAN_ConfigFilter+0x13e>
{
/* FIFO 0 assignation for the filter */
CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
80026f0: 697b ldr r3, [r7, #20]
80026f2: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214
80026f6: 68fb ldr r3, [r7, #12]
80026f8: 43db mvns r3, r3
80026fa: 401a ands r2, r3
80026fc: 697b ldr r3, [r7, #20]
80026fe: f8c3 2214 str.w r2, [r3, #532] @ 0x214
8002702: e007 b.n 8002714 <HAL_CAN_ConfigFilter+0x14e>
}
else
{
/* FIFO 1 assignation for the filter */
SET_BIT(can_ip->FFA1R, filternbrbitpos);
8002704: 697b ldr r3, [r7, #20]
8002706: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214
800270a: 68fb ldr r3, [r7, #12]
800270c: 431a orrs r2, r3
800270e: 697b ldr r3, [r7, #20]
8002710: f8c3 2214 str.w r2, [r3, #532] @ 0x214
}
/* Filter activation */
if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
8002714: 683b ldr r3, [r7, #0]
8002716: 6a1b ldr r3, [r3, #32]
8002718: 2b01 cmp r3, #1
800271a: d107 bne.n 800272c <HAL_CAN_ConfigFilter+0x166>
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
800271c: 697b ldr r3, [r7, #20]
800271e: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c
8002722: 68fb ldr r3, [r7, #12]
8002724: 431a orrs r2, r3
8002726: 697b ldr r3, [r7, #20]
8002728: f8c3 221c str.w r2, [r3, #540] @ 0x21c
}
/* Leave the initialisation mode for the filter */
CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
800272c: 697b ldr r3, [r7, #20]
800272e: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200
8002732: f023 0201 bic.w r2, r3, #1
8002736: 697b ldr r3, [r7, #20]
8002738: f8c3 2200 str.w r2, [r3, #512] @ 0x200
/* Return function status */
return HAL_OK;
800273c: 2300 movs r3, #0
800273e: e006 b.n 800274e <HAL_CAN_ConfigFilter+0x188>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8002740: 687b ldr r3, [r7, #4]
8002742: 6a5b ldr r3, [r3, #36] @ 0x24
8002744: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8002748: 687b ldr r3, [r7, #4]
800274a: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
800274c: 2301 movs r3, #1
}
}
800274e: 4618 mov r0, r3
8002750: 371c adds r7, #28
8002752: 46bd mov sp, r7
8002754: f85d 7b04 ldr.w r7, [sp], #4
8002758: 4770 bx lr
0800275a <HAL_CAN_Start>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
800275a: b580 push {r7, lr}
800275c: b084 sub sp, #16
800275e: af00 add r7, sp, #0
8002760: 6078 str r0, [r7, #4]
uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
8002762: 687b ldr r3, [r7, #4]
8002764: f893 3020 ldrb.w r3, [r3, #32]
8002768: b2db uxtb r3, r3
800276a: 2b01 cmp r3, #1
800276c: d12e bne.n 80027cc <HAL_CAN_Start+0x72>
{
/* Change CAN peripheral state */
hcan->State = HAL_CAN_STATE_LISTENING;
800276e: 687b ldr r3, [r7, #4]
8002770: 2202 movs r2, #2
8002772: f883 2020 strb.w r2, [r3, #32]
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8002776: 687b ldr r3, [r7, #4]
8002778: 681b ldr r3, [r3, #0]
800277a: 681a ldr r2, [r3, #0]
800277c: 687b ldr r3, [r7, #4]
800277e: 681b ldr r3, [r3, #0]
8002780: f022 0201 bic.w r2, r2, #1
8002784: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002786: f7fe fe37 bl 80013f8 <HAL_GetTick>
800278a: 60f8 str r0, [r7, #12]
/* Wait the acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
800278c: e012 b.n 80027b4 <HAL_CAN_Start+0x5a>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
800278e: f7fe fe33 bl 80013f8 <HAL_GetTick>
8002792: 4602 mov r2, r0
8002794: 68fb ldr r3, [r7, #12]
8002796: 1ad3 subs r3, r2, r3
8002798: 2b0a cmp r3, #10
800279a: d90b bls.n 80027b4 <HAL_CAN_Start+0x5a>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
800279c: 687b ldr r3, [r7, #4]
800279e: 6a5b ldr r3, [r3, #36] @ 0x24
80027a0: f443 3200 orr.w r2, r3, #131072 @ 0x20000
80027a4: 687b ldr r3, [r7, #4]
80027a6: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
80027a8: 687b ldr r3, [r7, #4]
80027aa: 2205 movs r2, #5
80027ac: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
80027b0: 2301 movs r3, #1
80027b2: e012 b.n 80027da <HAL_CAN_Start+0x80>
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
80027b4: 687b ldr r3, [r7, #4]
80027b6: 681b ldr r3, [r3, #0]
80027b8: 685b ldr r3, [r3, #4]
80027ba: f003 0301 and.w r3, r3, #1
80027be: 2b00 cmp r3, #0
80027c0: d1e5 bne.n 800278e <HAL_CAN_Start+0x34>
}
}
/* Reset the CAN ErrorCode */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
80027c2: 687b ldr r3, [r7, #4]
80027c4: 2200 movs r2, #0
80027c6: 625a str r2, [r3, #36] @ 0x24
/* Return function status */
return HAL_OK;
80027c8: 2300 movs r3, #0
80027ca: e006 b.n 80027da <HAL_CAN_Start+0x80>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
80027cc: 687b ldr r3, [r7, #4]
80027ce: 6a5b ldr r3, [r3, #36] @ 0x24
80027d0: f443 2200 orr.w r2, r3, #524288 @ 0x80000
80027d4: 687b ldr r3, [r7, #4]
80027d6: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80027d8: 2301 movs r3, #1
}
}
80027da: 4618 mov r0, r3
80027dc: 3710 adds r7, #16
80027de: 46bd mov sp, r7
80027e0: bd80 pop {r7, pc}
080027e2 <HAL_CAN_AddTxMessage>:
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox)
{
80027e2: b480 push {r7}
80027e4: b089 sub sp, #36 @ 0x24
80027e6: af00 add r7, sp, #0
80027e8: 60f8 str r0, [r7, #12]
80027ea: 60b9 str r1, [r7, #8]
80027ec: 607a str r2, [r7, #4]
80027ee: 603b str r3, [r7, #0]
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
80027f0: 68fb ldr r3, [r7, #12]
80027f2: f893 3020 ldrb.w r3, [r3, #32]
80027f6: 77fb strb r3, [r7, #31]
uint32_t tsr = READ_REG(hcan->Instance->TSR);
80027f8: 68fb ldr r3, [r7, #12]
80027fa: 681b ldr r3, [r3, #0]
80027fc: 689b ldr r3, [r3, #8]
80027fe: 61bb str r3, [r7, #24]
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
8002800: 7ffb ldrb r3, [r7, #31]
8002802: 2b01 cmp r3, #1
8002804: d003 beq.n 800280e <HAL_CAN_AddTxMessage+0x2c>
8002806: 7ffb ldrb r3, [r7, #31]
8002808: 2b02 cmp r3, #2
800280a: f040 80ad bne.w 8002968 <HAL_CAN_AddTxMessage+0x186>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
800280e: 69bb ldr r3, [r7, #24]
8002810: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8002814: 2b00 cmp r3, #0
8002816: d10a bne.n 800282e <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME1) != 0U) ||
8002818: 69bb ldr r3, [r7, #24]
800281a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
if (((tsr & CAN_TSR_TME0) != 0U) ||
800281e: 2b00 cmp r3, #0
8002820: d105 bne.n 800282e <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME2) != 0U))
8002822: 69bb ldr r3, [r7, #24]
8002824: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
((tsr & CAN_TSR_TME1) != 0U) ||
8002828: 2b00 cmp r3, #0
800282a: f000 8095 beq.w 8002958 <HAL_CAN_AddTxMessage+0x176>
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
800282e: 69bb ldr r3, [r7, #24]
8002830: 0e1b lsrs r3, r3, #24
8002832: f003 0303 and.w r3, r3, #3
8002836: 617b str r3, [r7, #20]
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
8002838: 2201 movs r2, #1
800283a: 697b ldr r3, [r7, #20]
800283c: 409a lsls r2, r3
800283e: 683b ldr r3, [r7, #0]
8002840: 601a str r2, [r3, #0]
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
8002842: 68bb ldr r3, [r7, #8]
8002844: 689b ldr r3, [r3, #8]
8002846: 2b00 cmp r3, #0
8002848: d10d bne.n 8002866 <HAL_CAN_AddTxMessage+0x84>
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
800284a: 68bb ldr r3, [r7, #8]
800284c: 681b ldr r3, [r3, #0]
800284e: 055a lsls r2, r3, #21
pHeader->RTR);
8002850: 68bb ldr r3, [r7, #8]
8002852: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8002854: 68f9 ldr r1, [r7, #12]
8002856: 6809 ldr r1, [r1, #0]
8002858: 431a orrs r2, r3
800285a: 697b ldr r3, [r7, #20]
800285c: 3318 adds r3, #24
800285e: 011b lsls r3, r3, #4
8002860: 440b add r3, r1
8002862: 601a str r2, [r3, #0]
8002864: e00f b.n 8002886 <HAL_CAN_AddTxMessage+0xa4>
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8002866: 68bb ldr r3, [r7, #8]
8002868: 685b ldr r3, [r3, #4]
800286a: 00da lsls r2, r3, #3
pHeader->IDE |
800286c: 68bb ldr r3, [r7, #8]
800286e: 689b ldr r3, [r3, #8]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8002870: 431a orrs r2, r3
pHeader->RTR);
8002872: 68bb ldr r3, [r7, #8]
8002874: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8002876: 68f9 ldr r1, [r7, #12]
8002878: 6809 ldr r1, [r1, #0]
pHeader->IDE |
800287a: 431a orrs r2, r3
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
800287c: 697b ldr r3, [r7, #20]
800287e: 3318 adds r3, #24
8002880: 011b lsls r3, r3, #4
8002882: 440b add r3, r1
8002884: 601a str r2, [r3, #0]
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
8002886: 68fb ldr r3, [r7, #12]
8002888: 6819 ldr r1, [r3, #0]
800288a: 68bb ldr r3, [r7, #8]
800288c: 691a ldr r2, [r3, #16]
800288e: 697b ldr r3, [r7, #20]
8002890: 3318 adds r3, #24
8002892: 011b lsls r3, r3, #4
8002894: 440b add r3, r1
8002896: 3304 adds r3, #4
8002898: 601a str r2, [r3, #0]
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
800289a: 68bb ldr r3, [r7, #8]
800289c: 7d1b ldrb r3, [r3, #20]
800289e: 2b01 cmp r3, #1
80028a0: d111 bne.n 80028c6 <HAL_CAN_AddTxMessage+0xe4>
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
80028a2: 68fb ldr r3, [r7, #12]
80028a4: 681a ldr r2, [r3, #0]
80028a6: 697b ldr r3, [r7, #20]
80028a8: 3318 adds r3, #24
80028aa: 011b lsls r3, r3, #4
80028ac: 4413 add r3, r2
80028ae: 3304 adds r3, #4
80028b0: 681b ldr r3, [r3, #0]
80028b2: 68fa ldr r2, [r7, #12]
80028b4: 6811 ldr r1, [r2, #0]
80028b6: f443 7280 orr.w r2, r3, #256 @ 0x100
80028ba: 697b ldr r3, [r7, #20]
80028bc: 3318 adds r3, #24
80028be: 011b lsls r3, r3, #4
80028c0: 440b add r3, r1
80028c2: 3304 adds r3, #4
80028c4: 601a str r2, [r3, #0]
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
80028c6: 687b ldr r3, [r7, #4]
80028c8: 3307 adds r3, #7
80028ca: 781b ldrb r3, [r3, #0]
80028cc: 061a lsls r2, r3, #24
80028ce: 687b ldr r3, [r7, #4]
80028d0: 3306 adds r3, #6
80028d2: 781b ldrb r3, [r3, #0]
80028d4: 041b lsls r3, r3, #16
80028d6: 431a orrs r2, r3
80028d8: 687b ldr r3, [r7, #4]
80028da: 3305 adds r3, #5
80028dc: 781b ldrb r3, [r3, #0]
80028de: 021b lsls r3, r3, #8
80028e0: 4313 orrs r3, r2
80028e2: 687a ldr r2, [r7, #4]
80028e4: 3204 adds r2, #4
80028e6: 7812 ldrb r2, [r2, #0]
80028e8: 4610 mov r0, r2
80028ea: 68fa ldr r2, [r7, #12]
80028ec: 6811 ldr r1, [r2, #0]
80028ee: ea43 0200 orr.w r2, r3, r0
80028f2: 697b ldr r3, [r7, #20]
80028f4: 011b lsls r3, r3, #4
80028f6: 440b add r3, r1
80028f8: f503 73c6 add.w r3, r3, #396 @ 0x18c
80028fc: 601a str r2, [r3, #0]
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
80028fe: 687b ldr r3, [r7, #4]
8002900: 3303 adds r3, #3
8002902: 781b ldrb r3, [r3, #0]
8002904: 061a lsls r2, r3, #24
8002906: 687b ldr r3, [r7, #4]
8002908: 3302 adds r3, #2
800290a: 781b ldrb r3, [r3, #0]
800290c: 041b lsls r3, r3, #16
800290e: 431a orrs r2, r3
8002910: 687b ldr r3, [r7, #4]
8002912: 3301 adds r3, #1
8002914: 781b ldrb r3, [r3, #0]
8002916: 021b lsls r3, r3, #8
8002918: 4313 orrs r3, r2
800291a: 687a ldr r2, [r7, #4]
800291c: 7812 ldrb r2, [r2, #0]
800291e: 4610 mov r0, r2
8002920: 68fa ldr r2, [r7, #12]
8002922: 6811 ldr r1, [r2, #0]
8002924: ea43 0200 orr.w r2, r3, r0
8002928: 697b ldr r3, [r7, #20]
800292a: 011b lsls r3, r3, #4
800292c: 440b add r3, r1
800292e: f503 73c4 add.w r3, r3, #392 @ 0x188
8002932: 601a str r2, [r3, #0]
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
8002934: 68fb ldr r3, [r7, #12]
8002936: 681a ldr r2, [r3, #0]
8002938: 697b ldr r3, [r7, #20]
800293a: 3318 adds r3, #24
800293c: 011b lsls r3, r3, #4
800293e: 4413 add r3, r2
8002940: 681b ldr r3, [r3, #0]
8002942: 68fa ldr r2, [r7, #12]
8002944: 6811 ldr r1, [r2, #0]
8002946: f043 0201 orr.w r2, r3, #1
800294a: 697b ldr r3, [r7, #20]
800294c: 3318 adds r3, #24
800294e: 011b lsls r3, r3, #4
8002950: 440b add r3, r1
8002952: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
8002954: 2300 movs r3, #0
8002956: e00e b.n 8002976 <HAL_CAN_AddTxMessage+0x194>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8002958: 68fb ldr r3, [r7, #12]
800295a: 6a5b ldr r3, [r3, #36] @ 0x24
800295c: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
8002960: 68fb ldr r3, [r7, #12]
8002962: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8002964: 2301 movs r3, #1
8002966: e006 b.n 8002976 <HAL_CAN_AddTxMessage+0x194>
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8002968: 68fb ldr r3, [r7, #12]
800296a: 6a5b ldr r3, [r3, #36] @ 0x24
800296c: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8002970: 68fb ldr r3, [r7, #12]
8002972: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8002974: 2301 movs r3, #1
}
}
8002976: 4618 mov r0, r3
8002978: 3724 adds r7, #36 @ 0x24
800297a: 46bd mov sp, r7
800297c: f85d 7b04 ldr.w r7, [sp], #4
8002980: 4770 bx lr
08002982 <HAL_CAN_GetRxMessage>:
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
8002982: b480 push {r7}
8002984: b087 sub sp, #28
8002986: af00 add r7, sp, #0
8002988: 60f8 str r0, [r7, #12]
800298a: 60b9 str r1, [r7, #8]
800298c: 607a str r2, [r7, #4]
800298e: 603b str r3, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
8002990: 68fb ldr r3, [r7, #12]
8002992: f893 3020 ldrb.w r3, [r3, #32]
8002996: 75fb strb r3, [r7, #23]
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
8002998: 7dfb ldrb r3, [r7, #23]
800299a: 2b01 cmp r3, #1
800299c: d003 beq.n 80029a6 <HAL_CAN_GetRxMessage+0x24>
800299e: 7dfb ldrb r3, [r7, #23]
80029a0: 2b02 cmp r3, #2
80029a2: f040 8103 bne.w 8002bac <HAL_CAN_GetRxMessage+0x22a>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
80029a6: 68bb ldr r3, [r7, #8]
80029a8: 2b00 cmp r3, #0
80029aa: d10e bne.n 80029ca <HAL_CAN_GetRxMessage+0x48>
{
/* Check that the Rx FIFO 0 is not empty */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
80029ac: 68fb ldr r3, [r7, #12]
80029ae: 681b ldr r3, [r3, #0]
80029b0: 68db ldr r3, [r3, #12]
80029b2: f003 0303 and.w r3, r3, #3
80029b6: 2b00 cmp r3, #0
80029b8: d116 bne.n 80029e8 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80029ba: 68fb ldr r3, [r7, #12]
80029bc: 6a5b ldr r3, [r3, #36] @ 0x24
80029be: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80029c2: 68fb ldr r3, [r7, #12]
80029c4: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80029c6: 2301 movs r3, #1
80029c8: e0f7 b.n 8002bba <HAL_CAN_GetRxMessage+0x238>
}
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
80029ca: 68fb ldr r3, [r7, #12]
80029cc: 681b ldr r3, [r3, #0]
80029ce: 691b ldr r3, [r3, #16]
80029d0: f003 0303 and.w r3, r3, #3
80029d4: 2b00 cmp r3, #0
80029d6: d107 bne.n 80029e8 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80029d8: 68fb ldr r3, [r7, #12]
80029da: 6a5b ldr r3, [r3, #36] @ 0x24
80029dc: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80029e0: 68fb ldr r3, [r7, #12]
80029e2: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80029e4: 2301 movs r3, #1
80029e6: e0e8 b.n 8002bba <HAL_CAN_GetRxMessage+0x238>
}
}
/* Get the header */
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
80029e8: 68fb ldr r3, [r7, #12]
80029ea: 681a ldr r2, [r3, #0]
80029ec: 68bb ldr r3, [r7, #8]
80029ee: 331b adds r3, #27
80029f0: 011b lsls r3, r3, #4
80029f2: 4413 add r3, r2
80029f4: 681b ldr r3, [r3, #0]
80029f6: f003 0204 and.w r2, r3, #4
80029fa: 687b ldr r3, [r7, #4]
80029fc: 609a str r2, [r3, #8]
if (pHeader->IDE == CAN_ID_STD)
80029fe: 687b ldr r3, [r7, #4]
8002a00: 689b ldr r3, [r3, #8]
8002a02: 2b00 cmp r3, #0
8002a04: d10c bne.n 8002a20 <HAL_CAN_GetRxMessage+0x9e>
{
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
8002a06: 68fb ldr r3, [r7, #12]
8002a08: 681a ldr r2, [r3, #0]
8002a0a: 68bb ldr r3, [r7, #8]
8002a0c: 331b adds r3, #27
8002a0e: 011b lsls r3, r3, #4
8002a10: 4413 add r3, r2
8002a12: 681b ldr r3, [r3, #0]
8002a14: 0d5b lsrs r3, r3, #21
8002a16: f3c3 020a ubfx r2, r3, #0, #11
8002a1a: 687b ldr r3, [r7, #4]
8002a1c: 601a str r2, [r3, #0]
8002a1e: e00b b.n 8002a38 <HAL_CAN_GetRxMessage+0xb6>
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
8002a20: 68fb ldr r3, [r7, #12]
8002a22: 681a ldr r2, [r3, #0]
8002a24: 68bb ldr r3, [r7, #8]
8002a26: 331b adds r3, #27
8002a28: 011b lsls r3, r3, #4
8002a2a: 4413 add r3, r2
8002a2c: 681b ldr r3, [r3, #0]
8002a2e: 08db lsrs r3, r3, #3
8002a30: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
8002a34: 687b ldr r3, [r7, #4]
8002a36: 605a str r2, [r3, #4]
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
8002a38: 68fb ldr r3, [r7, #12]
8002a3a: 681a ldr r2, [r3, #0]
8002a3c: 68bb ldr r3, [r7, #8]
8002a3e: 331b adds r3, #27
8002a40: 011b lsls r3, r3, #4
8002a42: 4413 add r3, r2
8002a44: 681b ldr r3, [r3, #0]
8002a46: f003 0202 and.w r2, r3, #2
8002a4a: 687b ldr r3, [r7, #4]
8002a4c: 60da str r2, [r3, #12]
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
8002a4e: 68fb ldr r3, [r7, #12]
8002a50: 681a ldr r2, [r3, #0]
8002a52: 68bb ldr r3, [r7, #8]
8002a54: 331b adds r3, #27
8002a56: 011b lsls r3, r3, #4
8002a58: 4413 add r3, r2
8002a5a: 3304 adds r3, #4
8002a5c: 681b ldr r3, [r3, #0]
8002a5e: f003 0308 and.w r3, r3, #8
8002a62: 2b00 cmp r3, #0
8002a64: d003 beq.n 8002a6e <HAL_CAN_GetRxMessage+0xec>
{
/* Truncate DLC to 8 if received field is over range */
pHeader->DLC = 8U;
8002a66: 687b ldr r3, [r7, #4]
8002a68: 2208 movs r2, #8
8002a6a: 611a str r2, [r3, #16]
8002a6c: e00b b.n 8002a86 <HAL_CAN_GetRxMessage+0x104>
}
else
{
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
8002a6e: 68fb ldr r3, [r7, #12]
8002a70: 681a ldr r2, [r3, #0]
8002a72: 68bb ldr r3, [r7, #8]
8002a74: 331b adds r3, #27
8002a76: 011b lsls r3, r3, #4
8002a78: 4413 add r3, r2
8002a7a: 3304 adds r3, #4
8002a7c: 681b ldr r3, [r3, #0]
8002a7e: f003 020f and.w r2, r3, #15
8002a82: 687b ldr r3, [r7, #4]
8002a84: 611a str r2, [r3, #16]
}
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
8002a86: 68fb ldr r3, [r7, #12]
8002a88: 681a ldr r2, [r3, #0]
8002a8a: 68bb ldr r3, [r7, #8]
8002a8c: 331b adds r3, #27
8002a8e: 011b lsls r3, r3, #4
8002a90: 4413 add r3, r2
8002a92: 3304 adds r3, #4
8002a94: 681b ldr r3, [r3, #0]
8002a96: 0a1b lsrs r3, r3, #8
8002a98: b2da uxtb r2, r3
8002a9a: 687b ldr r3, [r7, #4]
8002a9c: 619a str r2, [r3, #24]
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
8002a9e: 68fb ldr r3, [r7, #12]
8002aa0: 681a ldr r2, [r3, #0]
8002aa2: 68bb ldr r3, [r7, #8]
8002aa4: 331b adds r3, #27
8002aa6: 011b lsls r3, r3, #4
8002aa8: 4413 add r3, r2
8002aaa: 3304 adds r3, #4
8002aac: 681b ldr r3, [r3, #0]
8002aae: 0c1b lsrs r3, r3, #16
8002ab0: b29a uxth r2, r3
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 615a str r2, [r3, #20]
/* Get the data */
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
8002ab6: 68fb ldr r3, [r7, #12]
8002ab8: 681a ldr r2, [r3, #0]
8002aba: 68bb ldr r3, [r7, #8]
8002abc: 011b lsls r3, r3, #4
8002abe: 4413 add r3, r2
8002ac0: f503 73dc add.w r3, r3, #440 @ 0x1b8
8002ac4: 681b ldr r3, [r3, #0]
8002ac6: b2da uxtb r2, r3
8002ac8: 683b ldr r3, [r7, #0]
8002aca: 701a strb r2, [r3, #0]
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
8002acc: 68fb ldr r3, [r7, #12]
8002ace: 681a ldr r2, [r3, #0]
8002ad0: 68bb ldr r3, [r7, #8]
8002ad2: 011b lsls r3, r3, #4
8002ad4: 4413 add r3, r2
8002ad6: f503 73dc add.w r3, r3, #440 @ 0x1b8
8002ada: 681b ldr r3, [r3, #0]
8002adc: 0a1a lsrs r2, r3, #8
8002ade: 683b ldr r3, [r7, #0]
8002ae0: 3301 adds r3, #1
8002ae2: b2d2 uxtb r2, r2
8002ae4: 701a strb r2, [r3, #0]
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
8002ae6: 68fb ldr r3, [r7, #12]
8002ae8: 681a ldr r2, [r3, #0]
8002aea: 68bb ldr r3, [r7, #8]
8002aec: 011b lsls r3, r3, #4
8002aee: 4413 add r3, r2
8002af0: f503 73dc add.w r3, r3, #440 @ 0x1b8
8002af4: 681b ldr r3, [r3, #0]
8002af6: 0c1a lsrs r2, r3, #16
8002af8: 683b ldr r3, [r7, #0]
8002afa: 3302 adds r3, #2
8002afc: b2d2 uxtb r2, r2
8002afe: 701a strb r2, [r3, #0]
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
8002b00: 68fb ldr r3, [r7, #12]
8002b02: 681a ldr r2, [r3, #0]
8002b04: 68bb ldr r3, [r7, #8]
8002b06: 011b lsls r3, r3, #4
8002b08: 4413 add r3, r2
8002b0a: f503 73dc add.w r3, r3, #440 @ 0x1b8
8002b0e: 681b ldr r3, [r3, #0]
8002b10: 0e1a lsrs r2, r3, #24
8002b12: 683b ldr r3, [r7, #0]
8002b14: 3303 adds r3, #3
8002b16: b2d2 uxtb r2, r2
8002b18: 701a strb r2, [r3, #0]
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
8002b1a: 68fb ldr r3, [r7, #12]
8002b1c: 681a ldr r2, [r3, #0]
8002b1e: 68bb ldr r3, [r7, #8]
8002b20: 011b lsls r3, r3, #4
8002b22: 4413 add r3, r2
8002b24: f503 73de add.w r3, r3, #444 @ 0x1bc
8002b28: 681a ldr r2, [r3, #0]
8002b2a: 683b ldr r3, [r7, #0]
8002b2c: 3304 adds r3, #4
8002b2e: b2d2 uxtb r2, r2
8002b30: 701a strb r2, [r3, #0]
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
8002b32: 68fb ldr r3, [r7, #12]
8002b34: 681a ldr r2, [r3, #0]
8002b36: 68bb ldr r3, [r7, #8]
8002b38: 011b lsls r3, r3, #4
8002b3a: 4413 add r3, r2
8002b3c: f503 73de add.w r3, r3, #444 @ 0x1bc
8002b40: 681b ldr r3, [r3, #0]
8002b42: 0a1a lsrs r2, r3, #8
8002b44: 683b ldr r3, [r7, #0]
8002b46: 3305 adds r3, #5
8002b48: b2d2 uxtb r2, r2
8002b4a: 701a strb r2, [r3, #0]
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
8002b4c: 68fb ldr r3, [r7, #12]
8002b4e: 681a ldr r2, [r3, #0]
8002b50: 68bb ldr r3, [r7, #8]
8002b52: 011b lsls r3, r3, #4
8002b54: 4413 add r3, r2
8002b56: f503 73de add.w r3, r3, #444 @ 0x1bc
8002b5a: 681b ldr r3, [r3, #0]
8002b5c: 0c1a lsrs r2, r3, #16
8002b5e: 683b ldr r3, [r7, #0]
8002b60: 3306 adds r3, #6
8002b62: b2d2 uxtb r2, r2
8002b64: 701a strb r2, [r3, #0]
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
8002b66: 68fb ldr r3, [r7, #12]
8002b68: 681a ldr r2, [r3, #0]
8002b6a: 68bb ldr r3, [r7, #8]
8002b6c: 011b lsls r3, r3, #4
8002b6e: 4413 add r3, r2
8002b70: f503 73de add.w r3, r3, #444 @ 0x1bc
8002b74: 681b ldr r3, [r3, #0]
8002b76: 0e1a lsrs r2, r3, #24
8002b78: 683b ldr r3, [r7, #0]
8002b7a: 3307 adds r3, #7
8002b7c: b2d2 uxtb r2, r2
8002b7e: 701a strb r2, [r3, #0]
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
8002b80: 68bb ldr r3, [r7, #8]
8002b82: 2b00 cmp r3, #0
8002b84: d108 bne.n 8002b98 <HAL_CAN_GetRxMessage+0x216>
{
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
8002b86: 68fb ldr r3, [r7, #12]
8002b88: 681b ldr r3, [r3, #0]
8002b8a: 68da ldr r2, [r3, #12]
8002b8c: 68fb ldr r3, [r7, #12]
8002b8e: 681b ldr r3, [r3, #0]
8002b90: f042 0220 orr.w r2, r2, #32
8002b94: 60da str r2, [r3, #12]
8002b96: e007 b.n 8002ba8 <HAL_CAN_GetRxMessage+0x226>
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
8002b98: 68fb ldr r3, [r7, #12]
8002b9a: 681b ldr r3, [r3, #0]
8002b9c: 691a ldr r2, [r3, #16]
8002b9e: 68fb ldr r3, [r7, #12]
8002ba0: 681b ldr r3, [r3, #0]
8002ba2: f042 0220 orr.w r2, r2, #32
8002ba6: 611a str r2, [r3, #16]
}
/* Return function status */
return HAL_OK;
8002ba8: 2300 movs r3, #0
8002baa: e006 b.n 8002bba <HAL_CAN_GetRxMessage+0x238>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8002bac: 68fb ldr r3, [r7, #12]
8002bae: 6a5b ldr r3, [r3, #36] @ 0x24
8002bb0: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8002bb4: 68fb ldr r3, [r7, #12]
8002bb6: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8002bb8: 2301 movs r3, #1
}
}
8002bba: 4618 mov r0, r3
8002bbc: 371c adds r7, #28
8002bbe: 46bd mov sp, r7
8002bc0: f85d 7b04 ldr.w r7, [sp], #4
8002bc4: 4770 bx lr
08002bc6 <HAL_CAN_ActivateNotification>:
* @param ActiveITs indicates which interrupts will be enabled.
* This parameter can be any combination of @arg CAN_Interrupts.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
8002bc6: b480 push {r7}
8002bc8: b085 sub sp, #20
8002bca: af00 add r7, sp, #0
8002bcc: 6078 str r0, [r7, #4]
8002bce: 6039 str r1, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
8002bd0: 687b ldr r3, [r7, #4]
8002bd2: f893 3020 ldrb.w r3, [r3, #32]
8002bd6: 73fb strb r3, [r7, #15]
/* Check function parameters */
assert_param(IS_CAN_IT(ActiveITs));
if ((state == HAL_CAN_STATE_READY) ||
8002bd8: 7bfb ldrb r3, [r7, #15]
8002bda: 2b01 cmp r3, #1
8002bdc: d002 beq.n 8002be4 <HAL_CAN_ActivateNotification+0x1e>
8002bde: 7bfb ldrb r3, [r7, #15]
8002be0: 2b02 cmp r3, #2
8002be2: d109 bne.n 8002bf8 <HAL_CAN_ActivateNotification+0x32>
(state == HAL_CAN_STATE_LISTENING))
{
/* Enable the selected interrupts */
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
8002be4: 687b ldr r3, [r7, #4]
8002be6: 681b ldr r3, [r3, #0]
8002be8: 6959 ldr r1, [r3, #20]
8002bea: 687b ldr r3, [r7, #4]
8002bec: 681b ldr r3, [r3, #0]
8002bee: 683a ldr r2, [r7, #0]
8002bf0: 430a orrs r2, r1
8002bf2: 615a str r2, [r3, #20]
/* Return function status */
return HAL_OK;
8002bf4: 2300 movs r3, #0
8002bf6: e006 b.n 8002c06 <HAL_CAN_ActivateNotification+0x40>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8002bf8: 687b ldr r3, [r7, #4]
8002bfa: 6a5b ldr r3, [r3, #36] @ 0x24
8002bfc: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8002c00: 687b ldr r3, [r7, #4]
8002c02: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8002c04: 2301 movs r3, #1
}
}
8002c06: 4618 mov r0, r3
8002c08: 3714 adds r7, #20
8002c0a: 46bd mov sp, r7
8002c0c: f85d 7b04 ldr.w r7, [sp], #4
8002c10: 4770 bx lr
08002c12 <HAL_CAN_IRQHandler>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
8002c12: b580 push {r7, lr}
8002c14: b08a sub sp, #40 @ 0x28
8002c16: af00 add r7, sp, #0
8002c18: 6078 str r0, [r7, #4]
uint32_t errorcode = HAL_CAN_ERROR_NONE;
8002c1a: 2300 movs r3, #0
8002c1c: 627b str r3, [r7, #36] @ 0x24
uint32_t interrupts = READ_REG(hcan->Instance->IER);
8002c1e: 687b ldr r3, [r7, #4]
8002c20: 681b ldr r3, [r3, #0]
8002c22: 695b ldr r3, [r3, #20]
8002c24: 623b str r3, [r7, #32]
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
8002c26: 687b ldr r3, [r7, #4]
8002c28: 681b ldr r3, [r3, #0]
8002c2a: 685b ldr r3, [r3, #4]
8002c2c: 61fb str r3, [r7, #28]
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
8002c2e: 687b ldr r3, [r7, #4]
8002c30: 681b ldr r3, [r3, #0]
8002c32: 689b ldr r3, [r3, #8]
8002c34: 61bb str r3, [r7, #24]
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
8002c36: 687b ldr r3, [r7, #4]
8002c38: 681b ldr r3, [r3, #0]
8002c3a: 68db ldr r3, [r3, #12]
8002c3c: 617b str r3, [r7, #20]
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
8002c3e: 687b ldr r3, [r7, #4]
8002c40: 681b ldr r3, [r3, #0]
8002c42: 691b ldr r3, [r3, #16]
8002c44: 613b str r3, [r7, #16]
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
8002c46: 687b ldr r3, [r7, #4]
8002c48: 681b ldr r3, [r3, #0]
8002c4a: 699b ldr r3, [r3, #24]
8002c4c: 60fb str r3, [r7, #12]
/* Transmit Mailbox empty interrupt management *****************************/
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
8002c4e: 6a3b ldr r3, [r7, #32]
8002c50: f003 0301 and.w r3, r3, #1
8002c54: 2b00 cmp r3, #0
8002c56: d07c beq.n 8002d52 <HAL_CAN_IRQHandler+0x140>
{
/* Transmit Mailbox 0 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
8002c58: 69bb ldr r3, [r7, #24]
8002c5a: f003 0301 and.w r3, r3, #1
8002c5e: 2b00 cmp r3, #0
8002c60: d023 beq.n 8002caa <HAL_CAN_IRQHandler+0x98>
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
8002c62: 687b ldr r3, [r7, #4]
8002c64: 681b ldr r3, [r3, #0]
8002c66: 2201 movs r2, #1
8002c68: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
8002c6a: 69bb ldr r3, [r7, #24]
8002c6c: f003 0302 and.w r3, r3, #2
8002c70: 2b00 cmp r3, #0
8002c72: d003 beq.n 8002c7c <HAL_CAN_IRQHandler+0x6a>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
8002c74: 6878 ldr r0, [r7, #4]
8002c76: f000 f983 bl 8002f80 <HAL_CAN_TxMailbox0CompleteCallback>
8002c7a: e016 b.n 8002caa <HAL_CAN_IRQHandler+0x98>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST0) != 0U)
8002c7c: 69bb ldr r3, [r7, #24]
8002c7e: f003 0304 and.w r3, r3, #4
8002c82: 2b00 cmp r3, #0
8002c84: d004 beq.n 8002c90 <HAL_CAN_IRQHandler+0x7e>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
8002c86: 6a7b ldr r3, [r7, #36] @ 0x24
8002c88: f443 6300 orr.w r3, r3, #2048 @ 0x800
8002c8c: 627b str r3, [r7, #36] @ 0x24
8002c8e: e00c b.n 8002caa <HAL_CAN_IRQHandler+0x98>
}
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
8002c90: 69bb ldr r3, [r7, #24]
8002c92: f003 0308 and.w r3, r3, #8
8002c96: 2b00 cmp r3, #0
8002c98: d004 beq.n 8002ca4 <HAL_CAN_IRQHandler+0x92>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
8002c9a: 6a7b ldr r3, [r7, #36] @ 0x24
8002c9c: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8002ca0: 627b str r3, [r7, #36] @ 0x24
8002ca2: e002 b.n 8002caa <HAL_CAN_IRQHandler+0x98>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
8002ca4: 6878 ldr r0, [r7, #4]
8002ca6: f000 f989 bl 8002fbc <HAL_CAN_TxMailbox0AbortCallback>
}
}
}
/* Transmit Mailbox 1 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
8002caa: 69bb ldr r3, [r7, #24]
8002cac: f403 7380 and.w r3, r3, #256 @ 0x100
8002cb0: 2b00 cmp r3, #0
8002cb2: d024 beq.n 8002cfe <HAL_CAN_IRQHandler+0xec>
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
8002cb4: 687b ldr r3, [r7, #4]
8002cb6: 681b ldr r3, [r3, #0]
8002cb8: f44f 7280 mov.w r2, #256 @ 0x100
8002cbc: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
8002cbe: 69bb ldr r3, [r7, #24]
8002cc0: f403 7300 and.w r3, r3, #512 @ 0x200
8002cc4: 2b00 cmp r3, #0
8002cc6: d003 beq.n 8002cd0 <HAL_CAN_IRQHandler+0xbe>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
8002cc8: 6878 ldr r0, [r7, #4]
8002cca: f000 f963 bl 8002f94 <HAL_CAN_TxMailbox1CompleteCallback>
8002cce: e016 b.n 8002cfe <HAL_CAN_IRQHandler+0xec>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST1) != 0U)
8002cd0: 69bb ldr r3, [r7, #24]
8002cd2: f403 6380 and.w r3, r3, #1024 @ 0x400
8002cd6: 2b00 cmp r3, #0
8002cd8: d004 beq.n 8002ce4 <HAL_CAN_IRQHandler+0xd2>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
8002cda: 6a7b ldr r3, [r7, #36] @ 0x24
8002cdc: f443 5300 orr.w r3, r3, #8192 @ 0x2000
8002ce0: 627b str r3, [r7, #36] @ 0x24
8002ce2: e00c b.n 8002cfe <HAL_CAN_IRQHandler+0xec>
}
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
8002ce4: 69bb ldr r3, [r7, #24]
8002ce6: f403 6300 and.w r3, r3, #2048 @ 0x800
8002cea: 2b00 cmp r3, #0
8002cec: d004 beq.n 8002cf8 <HAL_CAN_IRQHandler+0xe6>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
8002cee: 6a7b ldr r3, [r7, #36] @ 0x24
8002cf0: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8002cf4: 627b str r3, [r7, #36] @ 0x24
8002cf6: e002 b.n 8002cfe <HAL_CAN_IRQHandler+0xec>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
8002cf8: 6878 ldr r0, [r7, #4]
8002cfa: f000 f969 bl 8002fd0 <HAL_CAN_TxMailbox1AbortCallback>
}
}
}
/* Transmit Mailbox 2 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
8002cfe: 69bb ldr r3, [r7, #24]
8002d00: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002d04: 2b00 cmp r3, #0
8002d06: d024 beq.n 8002d52 <HAL_CAN_IRQHandler+0x140>
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
8002d08: 687b ldr r3, [r7, #4]
8002d0a: 681b ldr r3, [r3, #0]
8002d0c: f44f 3280 mov.w r2, #65536 @ 0x10000
8002d10: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
8002d12: 69bb ldr r3, [r7, #24]
8002d14: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002d18: 2b00 cmp r3, #0
8002d1a: d003 beq.n 8002d24 <HAL_CAN_IRQHandler+0x112>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
8002d1c: 6878 ldr r0, [r7, #4]
8002d1e: f000 f943 bl 8002fa8 <HAL_CAN_TxMailbox2CompleteCallback>
8002d22: e016 b.n 8002d52 <HAL_CAN_IRQHandler+0x140>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST2) != 0U)
8002d24: 69bb ldr r3, [r7, #24]
8002d26: f403 2380 and.w r3, r3, #262144 @ 0x40000
8002d2a: 2b00 cmp r3, #0
8002d2c: d004 beq.n 8002d38 <HAL_CAN_IRQHandler+0x126>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
8002d2e: 6a7b ldr r3, [r7, #36] @ 0x24
8002d30: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8002d34: 627b str r3, [r7, #36] @ 0x24
8002d36: e00c b.n 8002d52 <HAL_CAN_IRQHandler+0x140>
}
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
8002d38: 69bb ldr r3, [r7, #24]
8002d3a: f403 2300 and.w r3, r3, #524288 @ 0x80000
8002d3e: 2b00 cmp r3, #0
8002d40: d004 beq.n 8002d4c <HAL_CAN_IRQHandler+0x13a>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
8002d42: 6a7b ldr r3, [r7, #36] @ 0x24
8002d44: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002d48: 627b str r3, [r7, #36] @ 0x24
8002d4a: e002 b.n 8002d52 <HAL_CAN_IRQHandler+0x140>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
8002d4c: 6878 ldr r0, [r7, #4]
8002d4e: f000 f949 bl 8002fe4 <HAL_CAN_TxMailbox2AbortCallback>
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
8002d52: 6a3b ldr r3, [r7, #32]
8002d54: f003 0308 and.w r3, r3, #8
8002d58: 2b00 cmp r3, #0
8002d5a: d00c beq.n 8002d76 <HAL_CAN_IRQHandler+0x164>
{
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
8002d5c: 697b ldr r3, [r7, #20]
8002d5e: f003 0310 and.w r3, r3, #16
8002d62: 2b00 cmp r3, #0
8002d64: d007 beq.n 8002d76 <HAL_CAN_IRQHandler+0x164>
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
8002d66: 6a7b ldr r3, [r7, #36] @ 0x24
8002d68: f443 7300 orr.w r3, r3, #512 @ 0x200
8002d6c: 627b str r3, [r7, #36] @ 0x24
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
8002d6e: 687b ldr r3, [r7, #4]
8002d70: 681b ldr r3, [r3, #0]
8002d72: 2210 movs r2, #16
8002d74: 60da str r2, [r3, #12]
}
}
/* Receive FIFO 0 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
8002d76: 6a3b ldr r3, [r7, #32]
8002d78: f003 0304 and.w r3, r3, #4
8002d7c: 2b00 cmp r3, #0
8002d7e: d00b beq.n 8002d98 <HAL_CAN_IRQHandler+0x186>
{
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
8002d80: 697b ldr r3, [r7, #20]
8002d82: f003 0308 and.w r3, r3, #8
8002d86: 2b00 cmp r3, #0
8002d88: d006 beq.n 8002d98 <HAL_CAN_IRQHandler+0x186>
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
8002d8a: 687b ldr r3, [r7, #4]
8002d8c: 681b ldr r3, [r3, #0]
8002d8e: 2208 movs r2, #8
8002d90: 60da str r2, [r3, #12]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
8002d92: 6878 ldr r0, [r7, #4]
8002d94: f000 f930 bl 8002ff8 <HAL_CAN_RxFifo0FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
8002d98: 6a3b ldr r3, [r7, #32]
8002d9a: f003 0302 and.w r3, r3, #2
8002d9e: 2b00 cmp r3, #0
8002da0: d009 beq.n 8002db6 <HAL_CAN_IRQHandler+0x1a4>
{
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
8002da2: 687b ldr r3, [r7, #4]
8002da4: 681b ldr r3, [r3, #0]
8002da6: 68db ldr r3, [r3, #12]
8002da8: f003 0303 and.w r3, r3, #3
8002dac: 2b00 cmp r3, #0
8002dae: d002 beq.n 8002db6 <HAL_CAN_IRQHandler+0x1a4>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
8002db0: 6878 ldr r0, [r7, #4]
8002db2: f7fd fb0f bl 80003d4 <HAL_CAN_RxFifo0MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
8002db6: 6a3b ldr r3, [r7, #32]
8002db8: f003 0340 and.w r3, r3, #64 @ 0x40
8002dbc: 2b00 cmp r3, #0
8002dbe: d00c beq.n 8002dda <HAL_CAN_IRQHandler+0x1c8>
{
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
8002dc0: 693b ldr r3, [r7, #16]
8002dc2: f003 0310 and.w r3, r3, #16
8002dc6: 2b00 cmp r3, #0
8002dc8: d007 beq.n 8002dda <HAL_CAN_IRQHandler+0x1c8>
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
8002dca: 6a7b ldr r3, [r7, #36] @ 0x24
8002dcc: f443 6380 orr.w r3, r3, #1024 @ 0x400
8002dd0: 627b str r3, [r7, #36] @ 0x24
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
8002dd2: 687b ldr r3, [r7, #4]
8002dd4: 681b ldr r3, [r3, #0]
8002dd6: 2210 movs r2, #16
8002dd8: 611a str r2, [r3, #16]
}
}
/* Receive FIFO 1 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
8002dda: 6a3b ldr r3, [r7, #32]
8002ddc: f003 0320 and.w r3, r3, #32
8002de0: 2b00 cmp r3, #0
8002de2: d00b beq.n 8002dfc <HAL_CAN_IRQHandler+0x1ea>
{
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
8002de4: 693b ldr r3, [r7, #16]
8002de6: f003 0308 and.w r3, r3, #8
8002dea: 2b00 cmp r3, #0
8002dec: d006 beq.n 8002dfc <HAL_CAN_IRQHandler+0x1ea>
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
8002dee: 687b ldr r3, [r7, #4]
8002df0: 681b ldr r3, [r3, #0]
8002df2: 2208 movs r2, #8
8002df4: 611a str r2, [r3, #16]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
8002df6: 6878 ldr r0, [r7, #4]
8002df8: f000 f912 bl 8003020 <HAL_CAN_RxFifo1FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
8002dfc: 6a3b ldr r3, [r7, #32]
8002dfe: f003 0310 and.w r3, r3, #16
8002e02: 2b00 cmp r3, #0
8002e04: d009 beq.n 8002e1a <HAL_CAN_IRQHandler+0x208>
{
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
8002e06: 687b ldr r3, [r7, #4]
8002e08: 681b ldr r3, [r3, #0]
8002e0a: 691b ldr r3, [r3, #16]
8002e0c: f003 0303 and.w r3, r3, #3
8002e10: 2b00 cmp r3, #0
8002e12: d002 beq.n 8002e1a <HAL_CAN_IRQHandler+0x208>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
8002e14: 6878 ldr r0, [r7, #4]
8002e16: f000 f8f9 bl 800300c <HAL_CAN_RxFifo1MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
8002e1a: 6a3b ldr r3, [r7, #32]
8002e1c: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002e20: 2b00 cmp r3, #0
8002e22: d00b beq.n 8002e3c <HAL_CAN_IRQHandler+0x22a>
{
if ((msrflags & CAN_MSR_SLAKI) != 0U)
8002e24: 69fb ldr r3, [r7, #28]
8002e26: f003 0310 and.w r3, r3, #16
8002e2a: 2b00 cmp r3, #0
8002e2c: d006 beq.n 8002e3c <HAL_CAN_IRQHandler+0x22a>
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
8002e2e: 687b ldr r3, [r7, #4]
8002e30: 681b ldr r3, [r3, #0]
8002e32: 2210 movs r2, #16
8002e34: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->SleepCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
8002e36: 6878 ldr r0, [r7, #4]
8002e38: f000 f8fc bl 8003034 <HAL_CAN_SleepCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
if ((interrupts & CAN_IT_WAKEUP) != 0U)
8002e3c: 6a3b ldr r3, [r7, #32]
8002e3e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002e42: 2b00 cmp r3, #0
8002e44: d00b beq.n 8002e5e <HAL_CAN_IRQHandler+0x24c>
{
if ((msrflags & CAN_MSR_WKUI) != 0U)
8002e46: 69fb ldr r3, [r7, #28]
8002e48: f003 0308 and.w r3, r3, #8
8002e4c: 2b00 cmp r3, #0
8002e4e: d006 beq.n 8002e5e <HAL_CAN_IRQHandler+0x24c>
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
8002e50: 687b ldr r3, [r7, #4]
8002e52: 681b ldr r3, [r3, #0]
8002e54: 2208 movs r2, #8
8002e56: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->WakeUpFromRxMsgCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
8002e58: 6878 ldr r0, [r7, #4]
8002e5a: f000 f8f5 bl 8003048 <HAL_CAN_WakeUpFromRxMsgCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
if ((interrupts & CAN_IT_ERROR) != 0U)
8002e5e: 6a3b ldr r3, [r7, #32]
8002e60: f403 4300 and.w r3, r3, #32768 @ 0x8000
8002e64: 2b00 cmp r3, #0
8002e66: d07b beq.n 8002f60 <HAL_CAN_IRQHandler+0x34e>
{
if ((msrflags & CAN_MSR_ERRI) != 0U)
8002e68: 69fb ldr r3, [r7, #28]
8002e6a: f003 0304 and.w r3, r3, #4
8002e6e: 2b00 cmp r3, #0
8002e70: d072 beq.n 8002f58 <HAL_CAN_IRQHandler+0x346>
{
/* Check Error Warning Flag */
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
8002e72: 6a3b ldr r3, [r7, #32]
8002e74: f403 7380 and.w r3, r3, #256 @ 0x100
8002e78: 2b00 cmp r3, #0
8002e7a: d008 beq.n 8002e8e <HAL_CAN_IRQHandler+0x27c>
((esrflags & CAN_ESR_EWGF) != 0U))
8002e7c: 68fb ldr r3, [r7, #12]
8002e7e: f003 0301 and.w r3, r3, #1
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
8002e82: 2b00 cmp r3, #0
8002e84: d003 beq.n 8002e8e <HAL_CAN_IRQHandler+0x27c>
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
8002e86: 6a7b ldr r3, [r7, #36] @ 0x24
8002e88: f043 0301 orr.w r3, r3, #1
8002e8c: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Warning Flag as read-only */
}
/* Check Error Passive Flag */
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8002e8e: 6a3b ldr r3, [r7, #32]
8002e90: f403 7300 and.w r3, r3, #512 @ 0x200
8002e94: 2b00 cmp r3, #0
8002e96: d008 beq.n 8002eaa <HAL_CAN_IRQHandler+0x298>
((esrflags & CAN_ESR_EPVF) != 0U))
8002e98: 68fb ldr r3, [r7, #12]
8002e9a: f003 0302 and.w r3, r3, #2
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8002e9e: 2b00 cmp r3, #0
8002ea0: d003 beq.n 8002eaa <HAL_CAN_IRQHandler+0x298>
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
8002ea2: 6a7b ldr r3, [r7, #36] @ 0x24
8002ea4: f043 0302 orr.w r3, r3, #2
8002ea8: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Passive Flag as read-only */
}
/* Check Bus-off Flag */
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
8002eaa: 6a3b ldr r3, [r7, #32]
8002eac: f403 6380 and.w r3, r3, #1024 @ 0x400
8002eb0: 2b00 cmp r3, #0
8002eb2: d008 beq.n 8002ec6 <HAL_CAN_IRQHandler+0x2b4>
((esrflags & CAN_ESR_BOFF) != 0U))
8002eb4: 68fb ldr r3, [r7, #12]
8002eb6: f003 0304 and.w r3, r3, #4
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
8002eba: 2b00 cmp r3, #0
8002ebc: d003 beq.n 8002ec6 <HAL_CAN_IRQHandler+0x2b4>
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
8002ebe: 6a7b ldr r3, [r7, #36] @ 0x24
8002ec0: f043 0304 orr.w r3, r3, #4
8002ec4: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Bus-Off as read-only */
}
/* Check Last Error Code Flag */
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
8002ec6: 6a3b ldr r3, [r7, #32]
8002ec8: f403 6300 and.w r3, r3, #2048 @ 0x800
8002ecc: 2b00 cmp r3, #0
8002ece: d043 beq.n 8002f58 <HAL_CAN_IRQHandler+0x346>
((esrflags & CAN_ESR_LEC) != 0U))
8002ed0: 68fb ldr r3, [r7, #12]
8002ed2: f003 0370 and.w r3, r3, #112 @ 0x70
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
8002ed6: 2b00 cmp r3, #0
8002ed8: d03e beq.n 8002f58 <HAL_CAN_IRQHandler+0x346>
{
switch (esrflags & CAN_ESR_LEC)
8002eda: 68fb ldr r3, [r7, #12]
8002edc: f003 0370 and.w r3, r3, #112 @ 0x70
8002ee0: 2b60 cmp r3, #96 @ 0x60
8002ee2: d02b beq.n 8002f3c <HAL_CAN_IRQHandler+0x32a>
8002ee4: 2b60 cmp r3, #96 @ 0x60
8002ee6: d82e bhi.n 8002f46 <HAL_CAN_IRQHandler+0x334>
8002ee8: 2b50 cmp r3, #80 @ 0x50
8002eea: d022 beq.n 8002f32 <HAL_CAN_IRQHandler+0x320>
8002eec: 2b50 cmp r3, #80 @ 0x50
8002eee: d82a bhi.n 8002f46 <HAL_CAN_IRQHandler+0x334>
8002ef0: 2b40 cmp r3, #64 @ 0x40
8002ef2: d019 beq.n 8002f28 <HAL_CAN_IRQHandler+0x316>
8002ef4: 2b40 cmp r3, #64 @ 0x40
8002ef6: d826 bhi.n 8002f46 <HAL_CAN_IRQHandler+0x334>
8002ef8: 2b30 cmp r3, #48 @ 0x30
8002efa: d010 beq.n 8002f1e <HAL_CAN_IRQHandler+0x30c>
8002efc: 2b30 cmp r3, #48 @ 0x30
8002efe: d822 bhi.n 8002f46 <HAL_CAN_IRQHandler+0x334>
8002f00: 2b10 cmp r3, #16
8002f02: d002 beq.n 8002f0a <HAL_CAN_IRQHandler+0x2f8>
8002f04: 2b20 cmp r3, #32
8002f06: d005 beq.n 8002f14 <HAL_CAN_IRQHandler+0x302>
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
/* Set CAN error code to CRC error */
errorcode |= HAL_CAN_ERROR_CRC;
break;
default:
break;
8002f08: e01d b.n 8002f46 <HAL_CAN_IRQHandler+0x334>
errorcode |= HAL_CAN_ERROR_STF;
8002f0a: 6a7b ldr r3, [r7, #36] @ 0x24
8002f0c: f043 0308 orr.w r3, r3, #8
8002f10: 627b str r3, [r7, #36] @ 0x24
break;
8002f12: e019 b.n 8002f48 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_FOR;
8002f14: 6a7b ldr r3, [r7, #36] @ 0x24
8002f16: f043 0310 orr.w r3, r3, #16
8002f1a: 627b str r3, [r7, #36] @ 0x24
break;
8002f1c: e014 b.n 8002f48 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_ACK;
8002f1e: 6a7b ldr r3, [r7, #36] @ 0x24
8002f20: f043 0320 orr.w r3, r3, #32
8002f24: 627b str r3, [r7, #36] @ 0x24
break;
8002f26: e00f b.n 8002f48 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BR;
8002f28: 6a7b ldr r3, [r7, #36] @ 0x24
8002f2a: f043 0340 orr.w r3, r3, #64 @ 0x40
8002f2e: 627b str r3, [r7, #36] @ 0x24
break;
8002f30: e00a b.n 8002f48 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BD;
8002f32: 6a7b ldr r3, [r7, #36] @ 0x24
8002f34: f043 0380 orr.w r3, r3, #128 @ 0x80
8002f38: 627b str r3, [r7, #36] @ 0x24
break;
8002f3a: e005 b.n 8002f48 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_CRC;
8002f3c: 6a7b ldr r3, [r7, #36] @ 0x24
8002f3e: f443 7380 orr.w r3, r3, #256 @ 0x100
8002f42: 627b str r3, [r7, #36] @ 0x24
break;
8002f44: e000 b.n 8002f48 <HAL_CAN_IRQHandler+0x336>
break;
8002f46: bf00 nop
}
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
8002f48: 687b ldr r3, [r7, #4]
8002f4a: 681b ldr r3, [r3, #0]
8002f4c: 699a ldr r2, [r3, #24]
8002f4e: 687b ldr r3, [r7, #4]
8002f50: 681b ldr r3, [r3, #0]
8002f52: f022 0270 bic.w r2, r2, #112 @ 0x70
8002f56: 619a str r2, [r3, #24]
}
}
/* Clear ERRI Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
8002f58: 687b ldr r3, [r7, #4]
8002f5a: 681b ldr r3, [r3, #0]
8002f5c: 2204 movs r2, #4
8002f5e: 605a str r2, [r3, #4]
}
/* Call the Error call Back in case of Errors */
if (errorcode != HAL_CAN_ERROR_NONE)
8002f60: 6a7b ldr r3, [r7, #36] @ 0x24
8002f62: 2b00 cmp r3, #0
8002f64: d008 beq.n 8002f78 <HAL_CAN_IRQHandler+0x366>
{
/* Update error code in handle */
hcan->ErrorCode |= errorcode;
8002f66: 687b ldr r3, [r7, #4]
8002f68: 6a5a ldr r2, [r3, #36] @ 0x24
8002f6a: 6a7b ldr r3, [r7, #36] @ 0x24
8002f6c: 431a orrs r2, r3
8002f6e: 687b ldr r3, [r7, #4]
8002f70: 625a str r2, [r3, #36] @ 0x24
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->ErrorCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
8002f72: 6878 ldr r0, [r7, #4]
8002f74: f000 f872 bl 800305c <HAL_CAN_ErrorCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
8002f78: bf00 nop
8002f7a: 3728 adds r7, #40 @ 0x28
8002f7c: 46bd mov sp, r7
8002f7e: bd80 pop {r7, pc}
08002f80 <HAL_CAN_TxMailbox0CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
8002f80: b480 push {r7}
8002f82: b083 sub sp, #12
8002f84: af00 add r7, sp, #0
8002f86: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
user file
*/
}
8002f88: bf00 nop
8002f8a: 370c adds r7, #12
8002f8c: 46bd mov sp, r7
8002f8e: f85d 7b04 ldr.w r7, [sp], #4
8002f92: 4770 bx lr
08002f94 <HAL_CAN_TxMailbox1CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
8002f94: b480 push {r7}
8002f96: b083 sub sp, #12
8002f98: af00 add r7, sp, #0
8002f9a: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
user file
*/
}
8002f9c: bf00 nop
8002f9e: 370c adds r7, #12
8002fa0: 46bd mov sp, r7
8002fa2: f85d 7b04 ldr.w r7, [sp], #4
8002fa6: 4770 bx lr
08002fa8 <HAL_CAN_TxMailbox2CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
8002fa8: b480 push {r7}
8002faa: b083 sub sp, #12
8002fac: af00 add r7, sp, #0
8002fae: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
user file
*/
}
8002fb0: bf00 nop
8002fb2: 370c adds r7, #12
8002fb4: 46bd mov sp, r7
8002fb6: f85d 7b04 ldr.w r7, [sp], #4
8002fba: 4770 bx lr
08002fbc <HAL_CAN_TxMailbox0AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
8002fbc: b480 push {r7}
8002fbe: b083 sub sp, #12
8002fc0: af00 add r7, sp, #0
8002fc2: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
user file
*/
}
8002fc4: bf00 nop
8002fc6: 370c adds r7, #12
8002fc8: 46bd mov sp, r7
8002fca: f85d 7b04 ldr.w r7, [sp], #4
8002fce: 4770 bx lr
08002fd0 <HAL_CAN_TxMailbox1AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
8002fd0: b480 push {r7}
8002fd2: b083 sub sp, #12
8002fd4: af00 add r7, sp, #0
8002fd6: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
user file
*/
}
8002fd8: bf00 nop
8002fda: 370c adds r7, #12
8002fdc: 46bd mov sp, r7
8002fde: f85d 7b04 ldr.w r7, [sp], #4
8002fe2: 4770 bx lr
08002fe4 <HAL_CAN_TxMailbox2AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
8002fe4: b480 push {r7}
8002fe6: b083 sub sp, #12
8002fe8: af00 add r7, sp, #0
8002fea: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
user file
*/
}
8002fec: bf00 nop
8002fee: 370c adds r7, #12
8002ff0: 46bd mov sp, r7
8002ff2: f85d 7b04 ldr.w r7, [sp], #4
8002ff6: 4770 bx lr
08002ff8 <HAL_CAN_RxFifo0FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
8002ff8: b480 push {r7}
8002ffa: b083 sub sp, #12
8002ffc: af00 add r7, sp, #0
8002ffe: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
file
*/
}
8003000: bf00 nop
8003002: 370c adds r7, #12
8003004: 46bd mov sp, r7
8003006: f85d 7b04 ldr.w r7, [sp], #4
800300a: 4770 bx lr
0800300c <HAL_CAN_RxFifo1MsgPendingCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
800300c: b480 push {r7}
800300e: b083 sub sp, #12
8003010: af00 add r7, sp, #0
8003012: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
user file
*/
}
8003014: bf00 nop
8003016: 370c adds r7, #12
8003018: 46bd mov sp, r7
800301a: f85d 7b04 ldr.w r7, [sp], #4
800301e: 4770 bx lr
08003020 <HAL_CAN_RxFifo1FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
8003020: b480 push {r7}
8003022: b083 sub sp, #12
8003024: af00 add r7, sp, #0
8003026: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
file
*/
}
8003028: bf00 nop
800302a: 370c adds r7, #12
800302c: 46bd mov sp, r7
800302e: f85d 7b04 ldr.w r7, [sp], #4
8003032: 4770 bx lr
08003034 <HAL_CAN_SleepCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
8003034: b480 push {r7}
8003036: b083 sub sp, #12
8003038: af00 add r7, sp, #0
800303a: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_SleepCallback could be implemented in the user file
*/
}
800303c: bf00 nop
800303e: 370c adds r7, #12
8003040: 46bd mov sp, r7
8003042: f85d 7b04 ldr.w r7, [sp], #4
8003046: 4770 bx lr
08003048 <HAL_CAN_WakeUpFromRxMsgCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
8003048: b480 push {r7}
800304a: b083 sub sp, #12
800304c: af00 add r7, sp, #0
800304e: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
user file
*/
}
8003050: bf00 nop
8003052: 370c adds r7, #12
8003054: 46bd mov sp, r7
8003056: f85d 7b04 ldr.w r7, [sp], #4
800305a: 4770 bx lr
0800305c <HAL_CAN_ErrorCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
800305c: b480 push {r7}
800305e: b083 sub sp, #12
8003060: af00 add r7, sp, #0
8003062: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
8003064: bf00 nop
8003066: 370c adds r7, #12
8003068: 46bd mov sp, r7
800306a: f85d 7b04 ldr.w r7, [sp], #4
800306e: 4770 bx lr
08003070 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003070: b480 push {r7}
8003072: b085 sub sp, #20
8003074: af00 add r7, sp, #0
8003076: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003078: 687b ldr r3, [r7, #4]
800307a: f003 0307 and.w r3, r3, #7
800307e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8003080: 4b0c ldr r3, [pc, #48] @ (80030b4 <__NVIC_SetPriorityGrouping+0x44>)
8003082: 68db ldr r3, [r3, #12]
8003084: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8003086: 68ba ldr r2, [r7, #8]
8003088: f64f 03ff movw r3, #63743 @ 0xf8ff
800308c: 4013 ands r3, r2
800308e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8003090: 68fb ldr r3, [r7, #12]
8003092: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8003094: 68bb ldr r3, [r7, #8]
8003096: 4313 orrs r3, r2
reg_value = (reg_value |
8003098: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
800309c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80030a0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80030a2: 4a04 ldr r2, [pc, #16] @ (80030b4 <__NVIC_SetPriorityGrouping+0x44>)
80030a4: 68bb ldr r3, [r7, #8]
80030a6: 60d3 str r3, [r2, #12]
}
80030a8: bf00 nop
80030aa: 3714 adds r7, #20
80030ac: 46bd mov sp, r7
80030ae: f85d 7b04 ldr.w r7, [sp], #4
80030b2: 4770 bx lr
80030b4: e000ed00 .word 0xe000ed00
080030b8 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80030b8: b480 push {r7}
80030ba: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80030bc: 4b04 ldr r3, [pc, #16] @ (80030d0 <__NVIC_GetPriorityGrouping+0x18>)
80030be: 68db ldr r3, [r3, #12]
80030c0: 0a1b lsrs r3, r3, #8
80030c2: f003 0307 and.w r3, r3, #7
}
80030c6: 4618 mov r0, r3
80030c8: 46bd mov sp, r7
80030ca: f85d 7b04 ldr.w r7, [sp], #4
80030ce: 4770 bx lr
80030d0: e000ed00 .word 0xe000ed00
080030d4 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80030d4: b480 push {r7}
80030d6: b083 sub sp, #12
80030d8: af00 add r7, sp, #0
80030da: 4603 mov r3, r0
80030dc: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80030de: f997 3007 ldrsb.w r3, [r7, #7]
80030e2: 2b00 cmp r3, #0
80030e4: db0b blt.n 80030fe <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80030e6: 79fb ldrb r3, [r7, #7]
80030e8: f003 021f and.w r2, r3, #31
80030ec: 4907 ldr r1, [pc, #28] @ (800310c <__NVIC_EnableIRQ+0x38>)
80030ee: f997 3007 ldrsb.w r3, [r7, #7]
80030f2: 095b lsrs r3, r3, #5
80030f4: 2001 movs r0, #1
80030f6: fa00 f202 lsl.w r2, r0, r2
80030fa: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
80030fe: bf00 nop
8003100: 370c adds r7, #12
8003102: 46bd mov sp, r7
8003104: f85d 7b04 ldr.w r7, [sp], #4
8003108: 4770 bx lr
800310a: bf00 nop
800310c: e000e100 .word 0xe000e100
08003110 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003110: b480 push {r7}
8003112: b083 sub sp, #12
8003114: af00 add r7, sp, #0
8003116: 4603 mov r3, r0
8003118: 6039 str r1, [r7, #0]
800311a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800311c: f997 3007 ldrsb.w r3, [r7, #7]
8003120: 2b00 cmp r3, #0
8003122: db0a blt.n 800313a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003124: 683b ldr r3, [r7, #0]
8003126: b2da uxtb r2, r3
8003128: 490c ldr r1, [pc, #48] @ (800315c <__NVIC_SetPriority+0x4c>)
800312a: f997 3007 ldrsb.w r3, [r7, #7]
800312e: 0112 lsls r2, r2, #4
8003130: b2d2 uxtb r2, r2
8003132: 440b add r3, r1
8003134: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8003138: e00a b.n 8003150 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800313a: 683b ldr r3, [r7, #0]
800313c: b2da uxtb r2, r3
800313e: 4908 ldr r1, [pc, #32] @ (8003160 <__NVIC_SetPriority+0x50>)
8003140: 79fb ldrb r3, [r7, #7]
8003142: f003 030f and.w r3, r3, #15
8003146: 3b04 subs r3, #4
8003148: 0112 lsls r2, r2, #4
800314a: b2d2 uxtb r2, r2
800314c: 440b add r3, r1
800314e: 761a strb r2, [r3, #24]
}
8003150: bf00 nop
8003152: 370c adds r7, #12
8003154: 46bd mov sp, r7
8003156: f85d 7b04 ldr.w r7, [sp], #4
800315a: 4770 bx lr
800315c: e000e100 .word 0xe000e100
8003160: e000ed00 .word 0xe000ed00
08003164 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003164: b480 push {r7}
8003166: b089 sub sp, #36 @ 0x24
8003168: af00 add r7, sp, #0
800316a: 60f8 str r0, [r7, #12]
800316c: 60b9 str r1, [r7, #8]
800316e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003170: 68fb ldr r3, [r7, #12]
8003172: f003 0307 and.w r3, r3, #7
8003176: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8003178: 69fb ldr r3, [r7, #28]
800317a: f1c3 0307 rsb r3, r3, #7
800317e: 2b04 cmp r3, #4
8003180: bf28 it cs
8003182: 2304 movcs r3, #4
8003184: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8003186: 69fb ldr r3, [r7, #28]
8003188: 3304 adds r3, #4
800318a: 2b06 cmp r3, #6
800318c: d902 bls.n 8003194 <NVIC_EncodePriority+0x30>
800318e: 69fb ldr r3, [r7, #28]
8003190: 3b03 subs r3, #3
8003192: e000 b.n 8003196 <NVIC_EncodePriority+0x32>
8003194: 2300 movs r3, #0
8003196: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003198: f04f 32ff mov.w r2, #4294967295
800319c: 69bb ldr r3, [r7, #24]
800319e: fa02 f303 lsl.w r3, r2, r3
80031a2: 43da mvns r2, r3
80031a4: 68bb ldr r3, [r7, #8]
80031a6: 401a ands r2, r3
80031a8: 697b ldr r3, [r7, #20]
80031aa: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80031ac: f04f 31ff mov.w r1, #4294967295
80031b0: 697b ldr r3, [r7, #20]
80031b2: fa01 f303 lsl.w r3, r1, r3
80031b6: 43d9 mvns r1, r3
80031b8: 687b ldr r3, [r7, #4]
80031ba: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80031bc: 4313 orrs r3, r2
);
}
80031be: 4618 mov r0, r3
80031c0: 3724 adds r7, #36 @ 0x24
80031c2: 46bd mov sp, r7
80031c4: f85d 7b04 ldr.w r7, [sp], #4
80031c8: 4770 bx lr
...
080031cc <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80031cc: b580 push {r7, lr}
80031ce: b082 sub sp, #8
80031d0: af00 add r7, sp, #0
80031d2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80031d4: 687b ldr r3, [r7, #4]
80031d6: 3b01 subs r3, #1
80031d8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80031dc: d301 bcc.n 80031e2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80031de: 2301 movs r3, #1
80031e0: e00f b.n 8003202 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80031e2: 4a0a ldr r2, [pc, #40] @ (800320c <SysTick_Config+0x40>)
80031e4: 687b ldr r3, [r7, #4]
80031e6: 3b01 subs r3, #1
80031e8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80031ea: 210f movs r1, #15
80031ec: f04f 30ff mov.w r0, #4294967295
80031f0: f7ff ff8e bl 8003110 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80031f4: 4b05 ldr r3, [pc, #20] @ (800320c <SysTick_Config+0x40>)
80031f6: 2200 movs r2, #0
80031f8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80031fa: 4b04 ldr r3, [pc, #16] @ (800320c <SysTick_Config+0x40>)
80031fc: 2207 movs r2, #7
80031fe: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8003200: 2300 movs r3, #0
}
8003202: 4618 mov r0, r3
8003204: 3708 adds r7, #8
8003206: 46bd mov sp, r7
8003208: bd80 pop {r7, pc}
800320a: bf00 nop
800320c: e000e010 .word 0xe000e010
08003210 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003210: b580 push {r7, lr}
8003212: b082 sub sp, #8
8003214: af00 add r7, sp, #0
8003216: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003218: 6878 ldr r0, [r7, #4]
800321a: f7ff ff29 bl 8003070 <__NVIC_SetPriorityGrouping>
}
800321e: bf00 nop
8003220: 3708 adds r7, #8
8003222: 46bd mov sp, r7
8003224: bd80 pop {r7, pc}
08003226 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003226: b580 push {r7, lr}
8003228: b086 sub sp, #24
800322a: af00 add r7, sp, #0
800322c: 4603 mov r3, r0
800322e: 60b9 str r1, [r7, #8]
8003230: 607a str r2, [r7, #4]
8003232: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8003234: 2300 movs r3, #0
8003236: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8003238: f7ff ff3e bl 80030b8 <__NVIC_GetPriorityGrouping>
800323c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800323e: 687a ldr r2, [r7, #4]
8003240: 68b9 ldr r1, [r7, #8]
8003242: 6978 ldr r0, [r7, #20]
8003244: f7ff ff8e bl 8003164 <NVIC_EncodePriority>
8003248: 4602 mov r2, r0
800324a: f997 300f ldrsb.w r3, [r7, #15]
800324e: 4611 mov r1, r2
8003250: 4618 mov r0, r3
8003252: f7ff ff5d bl 8003110 <__NVIC_SetPriority>
}
8003256: bf00 nop
8003258: 3718 adds r7, #24
800325a: 46bd mov sp, r7
800325c: bd80 pop {r7, pc}
0800325e <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800325e: b580 push {r7, lr}
8003260: b082 sub sp, #8
8003262: af00 add r7, sp, #0
8003264: 4603 mov r3, r0
8003266: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8003268: f997 3007 ldrsb.w r3, [r7, #7]
800326c: 4618 mov r0, r3
800326e: f7ff ff31 bl 80030d4 <__NVIC_EnableIRQ>
}
8003272: bf00 nop
8003274: 3708 adds r7, #8
8003276: 46bd mov sp, r7
8003278: bd80 pop {r7, pc}
0800327a <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800327a: b580 push {r7, lr}
800327c: b082 sub sp, #8
800327e: af00 add r7, sp, #0
8003280: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8003282: 6878 ldr r0, [r7, #4]
8003284: f7ff ffa2 bl 80031cc <SysTick_Config>
8003288: 4603 mov r3, r0
}
800328a: 4618 mov r0, r3
800328c: 3708 adds r7, #8
800328e: 46bd mov sp, r7
8003290: bd80 pop {r7, pc}
08003292 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8003292: b580 push {r7, lr}
8003294: b084 sub sp, #16
8003296: af00 add r7, sp, #0
8003298: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
800329a: 2300 movs r3, #0
800329c: 60fb str r3, [r7, #12]
/* Check the DMA handle allocation */
if(NULL == hdma)
800329e: 687b ldr r3, [r7, #4]
80032a0: 2b00 cmp r3, #0
80032a2: d101 bne.n 80032a8 <HAL_DMA_Init+0x16>
{
return HAL_ERROR;
80032a4: 2301 movs r3, #1
80032a6: e037 b.n 8003318 <HAL_DMA_Init+0x86>
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
80032a8: 687b ldr r3, [r7, #4]
80032aa: 2202 movs r2, #2
80032ac: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Get the CR register value */
tmp = hdma->Instance->CCR;
80032b0: 687b ldr r3, [r7, #4]
80032b2: 681b ldr r3, [r3, #0]
80032b4: 681b ldr r3, [r3, #0]
80032b6: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
80032b8: 68fb ldr r3, [r7, #12]
80032ba: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
80032be: f023 0330 bic.w r3, r3, #48 @ 0x30
80032c2: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
80032c4: 687b ldr r3, [r7, #4]
80032c6: 685a ldr r2, [r3, #4]
hdma->Init.PeriphInc | hdma->Init.MemInc |
80032c8: 687b ldr r3, [r7, #4]
80032ca: 689b ldr r3, [r3, #8]
tmp |= hdma->Init.Direction |
80032cc: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
80032ce: 687b ldr r3, [r7, #4]
80032d0: 68db ldr r3, [r3, #12]
80032d2: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80032d4: 687b ldr r3, [r7, #4]
80032d6: 691b ldr r3, [r3, #16]
hdma->Init.PeriphInc | hdma->Init.MemInc |
80032d8: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80032da: 687b ldr r3, [r7, #4]
80032dc: 695b ldr r3, [r3, #20]
80032de: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
80032e0: 687b ldr r3, [r7, #4]
80032e2: 699b ldr r3, [r3, #24]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80032e4: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
80032e6: 687b ldr r3, [r7, #4]
80032e8: 69db ldr r3, [r3, #28]
80032ea: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
80032ec: 68fa ldr r2, [r7, #12]
80032ee: 4313 orrs r3, r2
80032f0: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
80032f2: 687b ldr r3, [r7, #4]
80032f4: 681b ldr r3, [r3, #0]
80032f6: 68fa ldr r2, [r7, #12]
80032f8: 601a str r2, [r3, #0]
/* Initialize DmaBaseAddress and ChannelIndex parameters used
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
DMA_CalcBaseAndBitshift(hdma);
80032fa: 6878 ldr r0, [r7, #4]
80032fc: f000 f8b4 bl 8003468 <DMA_CalcBaseAndBitshift>
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8003300: 687b ldr r3, [r7, #4]
8003302: 2200 movs r2, #0
8003304: 639a str r2, [r3, #56] @ 0x38
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8003306: 687b ldr r3, [r7, #4]
8003308: 2201 movs r2, #1
800330a: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
800330e: 687b ldr r3, [r7, #4]
8003310: 2200 movs r2, #0
8003312: f883 2020 strb.w r2, [r3, #32]
return HAL_OK;
8003316: 2300 movs r3, #0
}
8003318: 4618 mov r0, r3
800331a: 3710 adds r7, #16
800331c: 46bd mov sp, r7
800331e: bd80 pop {r7, pc}
08003320 <HAL_DMA_IRQHandler>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
8003320: b580 push {r7, lr}
8003322: b084 sub sp, #16
8003324: af00 add r7, sp, #0
8003326: 6078 str r0, [r7, #4]
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
8003328: 687b ldr r3, [r7, #4]
800332a: 6bdb ldr r3, [r3, #60] @ 0x3c
800332c: 681b ldr r3, [r3, #0]
800332e: 60fb str r3, [r7, #12]
uint32_t source_it = hdma->Instance->CCR;
8003330: 687b ldr r3, [r7, #4]
8003332: 681b ldr r3, [r3, #0]
8003334: 681b ldr r3, [r3, #0]
8003336: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
8003338: 687b ldr r3, [r7, #4]
800333a: 6c1b ldr r3, [r3, #64] @ 0x40
800333c: 2204 movs r2, #4
800333e: 409a lsls r2, r3
8003340: 68fb ldr r3, [r7, #12]
8003342: 4013 ands r3, r2
8003344: 2b00 cmp r3, #0
8003346: d024 beq.n 8003392 <HAL_DMA_IRQHandler+0x72>
8003348: 68bb ldr r3, [r7, #8]
800334a: f003 0304 and.w r3, r3, #4
800334e: 2b00 cmp r3, #0
8003350: d01f beq.n 8003392 <HAL_DMA_IRQHandler+0x72>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8003352: 687b ldr r3, [r7, #4]
8003354: 681b ldr r3, [r3, #0]
8003356: 681b ldr r3, [r3, #0]
8003358: f003 0320 and.w r3, r3, #32
800335c: 2b00 cmp r3, #0
800335e: d107 bne.n 8003370 <HAL_DMA_IRQHandler+0x50>
{
/* Disable the half transfer interrupt */
hdma->Instance->CCR &= ~DMA_IT_HT;
8003360: 687b ldr r3, [r7, #4]
8003362: 681b ldr r3, [r3, #0]
8003364: 681a ldr r2, [r3, #0]
8003366: 687b ldr r3, [r7, #4]
8003368: 681b ldr r3, [r3, #0]
800336a: f022 0204 bic.w r2, r2, #4
800336e: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
8003370: 687b ldr r3, [r7, #4]
8003372: 6c1a ldr r2, [r3, #64] @ 0x40
8003374: 687b ldr r3, [r7, #4]
8003376: 6bdb ldr r3, [r3, #60] @ 0x3c
8003378: 2104 movs r1, #4
800337a: fa01 f202 lsl.w r2, r1, r2
800337e: 605a str r2, [r3, #4]
/* DMA peripheral state is not updated in Half Transfer */
/* State is updated only in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
8003380: 687b ldr r3, [r7, #4]
8003382: 6adb ldr r3, [r3, #44] @ 0x2c
8003384: 2b00 cmp r3, #0
8003386: d06a beq.n 800345e <HAL_DMA_IRQHandler+0x13e>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
8003388: 687b ldr r3, [r7, #4]
800338a: 6adb ldr r3, [r3, #44] @ 0x2c
800338c: 6878 ldr r0, [r7, #4]
800338e: 4798 blx r3
if(hdma->XferHalfCpltCallback != NULL)
8003390: e065 b.n 800345e <HAL_DMA_IRQHandler+0x13e>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
8003392: 687b ldr r3, [r7, #4]
8003394: 6c1b ldr r3, [r3, #64] @ 0x40
8003396: 2202 movs r2, #2
8003398: 409a lsls r2, r3
800339a: 68fb ldr r3, [r7, #12]
800339c: 4013 ands r3, r2
800339e: 2b00 cmp r3, #0
80033a0: d02c beq.n 80033fc <HAL_DMA_IRQHandler+0xdc>
80033a2: 68bb ldr r3, [r7, #8]
80033a4: f003 0302 and.w r3, r3, #2
80033a8: 2b00 cmp r3, #0
80033aa: d027 beq.n 80033fc <HAL_DMA_IRQHandler+0xdc>
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
80033ac: 687b ldr r3, [r7, #4]
80033ae: 681b ldr r3, [r3, #0]
80033b0: 681b ldr r3, [r3, #0]
80033b2: f003 0320 and.w r3, r3, #32
80033b6: 2b00 cmp r3, #0
80033b8: d10b bne.n 80033d2 <HAL_DMA_IRQHandler+0xb2>
{
/* Disable the transfer complete & transfer error interrupts */
/* if the DMA mode is not CIRCULAR */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
80033ba: 687b ldr r3, [r7, #4]
80033bc: 681b ldr r3, [r3, #0]
80033be: 681a ldr r2, [r3, #0]
80033c0: 687b ldr r3, [r7, #4]
80033c2: 681b ldr r3, [r3, #0]
80033c4: f022 020a bic.w r2, r2, #10
80033c8: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80033ca: 687b ldr r3, [r7, #4]
80033cc: 2201 movs r2, #1
80033ce: f883 2021 strb.w r2, [r3, #33] @ 0x21
}
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
80033d2: 687b ldr r3, [r7, #4]
80033d4: 6c1a ldr r2, [r3, #64] @ 0x40
80033d6: 687b ldr r3, [r7, #4]
80033d8: 6bdb ldr r3, [r3, #60] @ 0x3c
80033da: 2102 movs r1, #2
80033dc: fa01 f202 lsl.w r2, r1, r2
80033e0: 605a str r2, [r3, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80033e2: 687b ldr r3, [r7, #4]
80033e4: 2200 movs r2, #0
80033e6: f883 2020 strb.w r2, [r3, #32]
if(hdma->XferCpltCallback != NULL)
80033ea: 687b ldr r3, [r7, #4]
80033ec: 6a9b ldr r3, [r3, #40] @ 0x28
80033ee: 2b00 cmp r3, #0
80033f0: d035 beq.n 800345e <HAL_DMA_IRQHandler+0x13e>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
80033f2: 687b ldr r3, [r7, #4]
80033f4: 6a9b ldr r3, [r3, #40] @ 0x28
80033f6: 6878 ldr r0, [r7, #4]
80033f8: 4798 blx r3
if(hdma->XferCpltCallback != NULL)
80033fa: e030 b.n 800345e <HAL_DMA_IRQHandler+0x13e>
}
}
/* Transfer Error Interrupt management ***************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
80033fc: 687b ldr r3, [r7, #4]
80033fe: 6c1b ldr r3, [r3, #64] @ 0x40
8003400: 2208 movs r2, #8
8003402: 409a lsls r2, r3
8003404: 68fb ldr r3, [r7, #12]
8003406: 4013 ands r3, r2
8003408: 2b00 cmp r3, #0
800340a: d028 beq.n 800345e <HAL_DMA_IRQHandler+0x13e>
800340c: 68bb ldr r3, [r7, #8]
800340e: f003 0308 and.w r3, r3, #8
8003412: 2b00 cmp r3, #0
8003414: d023 beq.n 800345e <HAL_DMA_IRQHandler+0x13e>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Then, disable all DMA interrupts */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
8003416: 687b ldr r3, [r7, #4]
8003418: 681b ldr r3, [r3, #0]
800341a: 681a ldr r2, [r3, #0]
800341c: 687b ldr r3, [r7, #4]
800341e: 681b ldr r3, [r3, #0]
8003420: f022 020e bic.w r2, r2, #14
8003424: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
8003426: 687b ldr r3, [r7, #4]
8003428: 6c1a ldr r2, [r3, #64] @ 0x40
800342a: 687b ldr r3, [r7, #4]
800342c: 6bdb ldr r3, [r3, #60] @ 0x3c
800342e: 2101 movs r1, #1
8003430: fa01 f202 lsl.w r2, r1, r2
8003434: 605a str r2, [r3, #4]
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
8003436: 687b ldr r3, [r7, #4]
8003438: 2201 movs r2, #1
800343a: 639a str r2, [r3, #56] @ 0x38
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800343c: 687b ldr r3, [r7, #4]
800343e: 2201 movs r2, #1
8003440: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003444: 687b ldr r3, [r7, #4]
8003446: 2200 movs r2, #0
8003448: f883 2020 strb.w r2, [r3, #32]
if(hdma->XferErrorCallback != NULL)
800344c: 687b ldr r3, [r7, #4]
800344e: 6b1b ldr r3, [r3, #48] @ 0x30
8003450: 2b00 cmp r3, #0
8003452: d004 beq.n 800345e <HAL_DMA_IRQHandler+0x13e>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
8003454: 687b ldr r3, [r7, #4]
8003456: 6b1b ldr r3, [r3, #48] @ 0x30
8003458: 6878 ldr r0, [r7, #4]
800345a: 4798 blx r3
}
}
}
800345c: e7ff b.n 800345e <HAL_DMA_IRQHandler+0x13e>
800345e: bf00 nop
8003460: 3710 adds r7, #16
8003462: 46bd mov sp, r7
8003464: bd80 pop {r7, pc}
...
08003468 <DMA_CalcBaseAndBitshift>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
{
8003468: b480 push {r7}
800346a: b083 sub sp, #12
800346c: af00 add r7, sp, #0
800346e: 6078 str r0, [r7, #4]
#if defined (DMA2)
/* calculation of the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
8003470: 687b ldr r3, [r7, #4]
8003472: 681b ldr r3, [r3, #0]
8003474: 461a mov r2, r3
8003476: 4b14 ldr r3, [pc, #80] @ (80034c8 <DMA_CalcBaseAndBitshift+0x60>)
8003478: 429a cmp r2, r3
800347a: d80f bhi.n 800349c <DMA_CalcBaseAndBitshift+0x34>
{
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
800347c: 687b ldr r3, [r7, #4]
800347e: 681b ldr r3, [r3, #0]
8003480: 461a mov r2, r3
8003482: 4b12 ldr r3, [pc, #72] @ (80034cc <DMA_CalcBaseAndBitshift+0x64>)
8003484: 4413 add r3, r2
8003486: 4a12 ldr r2, [pc, #72] @ (80034d0 <DMA_CalcBaseAndBitshift+0x68>)
8003488: fba2 2303 umull r2, r3, r2, r3
800348c: 091b lsrs r3, r3, #4
800348e: 009a lsls r2, r3, #2
8003490: 687b ldr r3, [r7, #4]
8003492: 641a str r2, [r3, #64] @ 0x40
hdma->DmaBaseAddress = DMA1;
8003494: 687b ldr r3, [r7, #4]
8003496: 4a0f ldr r2, [pc, #60] @ (80034d4 <DMA_CalcBaseAndBitshift+0x6c>)
8003498: 63da str r2, [r3, #60] @ 0x3c
/* calculation of the channel index */
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
#endif
}
800349a: e00e b.n 80034ba <DMA_CalcBaseAndBitshift+0x52>
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
800349c: 687b ldr r3, [r7, #4]
800349e: 681b ldr r3, [r3, #0]
80034a0: 461a mov r2, r3
80034a2: 4b0d ldr r3, [pc, #52] @ (80034d8 <DMA_CalcBaseAndBitshift+0x70>)
80034a4: 4413 add r3, r2
80034a6: 4a0a ldr r2, [pc, #40] @ (80034d0 <DMA_CalcBaseAndBitshift+0x68>)
80034a8: fba2 2303 umull r2, r3, r2, r3
80034ac: 091b lsrs r3, r3, #4
80034ae: 009a lsls r2, r3, #2
80034b0: 687b ldr r3, [r7, #4]
80034b2: 641a str r2, [r3, #64] @ 0x40
hdma->DmaBaseAddress = DMA2;
80034b4: 687b ldr r3, [r7, #4]
80034b6: 4a09 ldr r2, [pc, #36] @ (80034dc <DMA_CalcBaseAndBitshift+0x74>)
80034b8: 63da str r2, [r3, #60] @ 0x3c
}
80034ba: bf00 nop
80034bc: 370c adds r7, #12
80034be: 46bd mov sp, r7
80034c0: f85d 7b04 ldr.w r7, [sp], #4
80034c4: 4770 bx lr
80034c6: bf00 nop
80034c8: 40020407 .word 0x40020407
80034cc: bffdfff8 .word 0xbffdfff8
80034d0: cccccccd .word 0xcccccccd
80034d4: 40020000 .word 0x40020000
80034d8: bffdfbf8 .word 0xbffdfbf8
80034dc: 40020400 .word 0x40020400
080034e0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80034e0: b480 push {r7}
80034e2: b087 sub sp, #28
80034e4: af00 add r7, sp, #0
80034e6: 6078 str r0, [r7, #4]
80034e8: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80034ea: 2300 movs r3, #0
80034ec: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80034ee: e154 b.n 800379a <HAL_GPIO_Init+0x2ba>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
80034f0: 683b ldr r3, [r7, #0]
80034f2: 681a ldr r2, [r3, #0]
80034f4: 2101 movs r1, #1
80034f6: 697b ldr r3, [r7, #20]
80034f8: fa01 f303 lsl.w r3, r1, r3
80034fc: 4013 ands r3, r2
80034fe: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8003500: 68fb ldr r3, [r7, #12]
8003502: 2b00 cmp r3, #0
8003504: f000 8146 beq.w 8003794 <HAL_GPIO_Init+0x2b4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8003508: 683b ldr r3, [r7, #0]
800350a: 685b ldr r3, [r3, #4]
800350c: f003 0303 and.w r3, r3, #3
8003510: 2b01 cmp r3, #1
8003512: d005 beq.n 8003520 <HAL_GPIO_Init+0x40>
8003514: 683b ldr r3, [r7, #0]
8003516: 685b ldr r3, [r3, #4]
8003518: f003 0303 and.w r3, r3, #3
800351c: 2b02 cmp r3, #2
800351e: d130 bne.n 8003582 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8003520: 687b ldr r3, [r7, #4]
8003522: 689b ldr r3, [r3, #8]
8003524: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
8003526: 697b ldr r3, [r7, #20]
8003528: 005b lsls r3, r3, #1
800352a: 2203 movs r2, #3
800352c: fa02 f303 lsl.w r3, r2, r3
8003530: 43db mvns r3, r3
8003532: 693a ldr r2, [r7, #16]
8003534: 4013 ands r3, r2
8003536: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8003538: 683b ldr r3, [r7, #0]
800353a: 68da ldr r2, [r3, #12]
800353c: 697b ldr r3, [r7, #20]
800353e: 005b lsls r3, r3, #1
8003540: fa02 f303 lsl.w r3, r2, r3
8003544: 693a ldr r2, [r7, #16]
8003546: 4313 orrs r3, r2
8003548: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800354a: 687b ldr r3, [r7, #4]
800354c: 693a ldr r2, [r7, #16]
800354e: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8003550: 687b ldr r3, [r7, #4]
8003552: 685b ldr r3, [r3, #4]
8003554: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8003556: 2201 movs r2, #1
8003558: 697b ldr r3, [r7, #20]
800355a: fa02 f303 lsl.w r3, r2, r3
800355e: 43db mvns r3, r3
8003560: 693a ldr r2, [r7, #16]
8003562: 4013 ands r3, r2
8003564: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8003566: 683b ldr r3, [r7, #0]
8003568: 685b ldr r3, [r3, #4]
800356a: 091b lsrs r3, r3, #4
800356c: f003 0201 and.w r2, r3, #1
8003570: 697b ldr r3, [r7, #20]
8003572: fa02 f303 lsl.w r3, r2, r3
8003576: 693a ldr r2, [r7, #16]
8003578: 4313 orrs r3, r2
800357a: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
800357c: 687b ldr r3, [r7, #4]
800357e: 693a ldr r2, [r7, #16]
8003580: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8003582: 683b ldr r3, [r7, #0]
8003584: 685b ldr r3, [r3, #4]
8003586: f003 0303 and.w r3, r3, #3
800358a: 2b03 cmp r3, #3
800358c: d017 beq.n 80035be <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
800358e: 687b ldr r3, [r7, #4]
8003590: 68db ldr r3, [r3, #12]
8003592: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8003594: 697b ldr r3, [r7, #20]
8003596: 005b lsls r3, r3, #1
8003598: 2203 movs r2, #3
800359a: fa02 f303 lsl.w r3, r2, r3
800359e: 43db mvns r3, r3
80035a0: 693a ldr r2, [r7, #16]
80035a2: 4013 ands r3, r2
80035a4: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80035a6: 683b ldr r3, [r7, #0]
80035a8: 689a ldr r2, [r3, #8]
80035aa: 697b ldr r3, [r7, #20]
80035ac: 005b lsls r3, r3, #1
80035ae: fa02 f303 lsl.w r3, r2, r3
80035b2: 693a ldr r2, [r7, #16]
80035b4: 4313 orrs r3, r2
80035b6: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80035b8: 687b ldr r3, [r7, #4]
80035ba: 693a ldr r2, [r7, #16]
80035bc: 60da str r2, [r3, #12]
}
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80035be: 683b ldr r3, [r7, #0]
80035c0: 685b ldr r3, [r3, #4]
80035c2: f003 0303 and.w r3, r3, #3
80035c6: 2b02 cmp r3, #2
80035c8: d123 bne.n 8003612 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
80035ca: 697b ldr r3, [r7, #20]
80035cc: 08da lsrs r2, r3, #3
80035ce: 687b ldr r3, [r7, #4]
80035d0: 3208 adds r2, #8
80035d2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80035d6: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
80035d8: 697b ldr r3, [r7, #20]
80035da: f003 0307 and.w r3, r3, #7
80035de: 009b lsls r3, r3, #2
80035e0: 220f movs r2, #15
80035e2: fa02 f303 lsl.w r3, r2, r3
80035e6: 43db mvns r3, r3
80035e8: 693a ldr r2, [r7, #16]
80035ea: 4013 ands r3, r2
80035ec: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
80035ee: 683b ldr r3, [r7, #0]
80035f0: 691a ldr r2, [r3, #16]
80035f2: 697b ldr r3, [r7, #20]
80035f4: f003 0307 and.w r3, r3, #7
80035f8: 009b lsls r3, r3, #2
80035fa: fa02 f303 lsl.w r3, r2, r3
80035fe: 693a ldr r2, [r7, #16]
8003600: 4313 orrs r3, r2
8003602: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8003604: 697b ldr r3, [r7, #20]
8003606: 08da lsrs r2, r3, #3
8003608: 687b ldr r3, [r7, #4]
800360a: 3208 adds r2, #8
800360c: 6939 ldr r1, [r7, #16]
800360e: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8003612: 687b ldr r3, [r7, #4]
8003614: 681b ldr r3, [r3, #0]
8003616: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8003618: 697b ldr r3, [r7, #20]
800361a: 005b lsls r3, r3, #1
800361c: 2203 movs r2, #3
800361e: fa02 f303 lsl.w r3, r2, r3
8003622: 43db mvns r3, r3
8003624: 693a ldr r2, [r7, #16]
8003626: 4013 ands r3, r2
8003628: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
800362a: 683b ldr r3, [r7, #0]
800362c: 685b ldr r3, [r3, #4]
800362e: f003 0203 and.w r2, r3, #3
8003632: 697b ldr r3, [r7, #20]
8003634: 005b lsls r3, r3, #1
8003636: fa02 f303 lsl.w r3, r2, r3
800363a: 693a ldr r2, [r7, #16]
800363c: 4313 orrs r3, r2
800363e: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8003640: 687b ldr r3, [r7, #4]
8003642: 693a ldr r2, [r7, #16]
8003644: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8003646: 683b ldr r3, [r7, #0]
8003648: 685b ldr r3, [r3, #4]
800364a: f403 3340 and.w r3, r3, #196608 @ 0x30000
800364e: 2b00 cmp r3, #0
8003650: f000 80a0 beq.w 8003794 <HAL_GPIO_Init+0x2b4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8003654: 4b58 ldr r3, [pc, #352] @ (80037b8 <HAL_GPIO_Init+0x2d8>)
8003656: 699b ldr r3, [r3, #24]
8003658: 4a57 ldr r2, [pc, #348] @ (80037b8 <HAL_GPIO_Init+0x2d8>)
800365a: f043 0301 orr.w r3, r3, #1
800365e: 6193 str r3, [r2, #24]
8003660: 4b55 ldr r3, [pc, #340] @ (80037b8 <HAL_GPIO_Init+0x2d8>)
8003662: 699b ldr r3, [r3, #24]
8003664: f003 0301 and.w r3, r3, #1
8003668: 60bb str r3, [r7, #8]
800366a: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
800366c: 4a53 ldr r2, [pc, #332] @ (80037bc <HAL_GPIO_Init+0x2dc>)
800366e: 697b ldr r3, [r7, #20]
8003670: 089b lsrs r3, r3, #2
8003672: 3302 adds r3, #2
8003674: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003678: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
800367a: 697b ldr r3, [r7, #20]
800367c: f003 0303 and.w r3, r3, #3
8003680: 009b lsls r3, r3, #2
8003682: 220f movs r2, #15
8003684: fa02 f303 lsl.w r3, r2, r3
8003688: 43db mvns r3, r3
800368a: 693a ldr r2, [r7, #16]
800368c: 4013 ands r3, r2
800368e: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8003690: 687b ldr r3, [r7, #4]
8003692: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8003696: d019 beq.n 80036cc <HAL_GPIO_Init+0x1ec>
8003698: 687b ldr r3, [r7, #4]
800369a: 4a49 ldr r2, [pc, #292] @ (80037c0 <HAL_GPIO_Init+0x2e0>)
800369c: 4293 cmp r3, r2
800369e: d013 beq.n 80036c8 <HAL_GPIO_Init+0x1e8>
80036a0: 687b ldr r3, [r7, #4]
80036a2: 4a48 ldr r2, [pc, #288] @ (80037c4 <HAL_GPIO_Init+0x2e4>)
80036a4: 4293 cmp r3, r2
80036a6: d00d beq.n 80036c4 <HAL_GPIO_Init+0x1e4>
80036a8: 687b ldr r3, [r7, #4]
80036aa: 4a47 ldr r2, [pc, #284] @ (80037c8 <HAL_GPIO_Init+0x2e8>)
80036ac: 4293 cmp r3, r2
80036ae: d007 beq.n 80036c0 <HAL_GPIO_Init+0x1e0>
80036b0: 687b ldr r3, [r7, #4]
80036b2: 4a46 ldr r2, [pc, #280] @ (80037cc <HAL_GPIO_Init+0x2ec>)
80036b4: 4293 cmp r3, r2
80036b6: d101 bne.n 80036bc <HAL_GPIO_Init+0x1dc>
80036b8: 2304 movs r3, #4
80036ba: e008 b.n 80036ce <HAL_GPIO_Init+0x1ee>
80036bc: 2305 movs r3, #5
80036be: e006 b.n 80036ce <HAL_GPIO_Init+0x1ee>
80036c0: 2303 movs r3, #3
80036c2: e004 b.n 80036ce <HAL_GPIO_Init+0x1ee>
80036c4: 2302 movs r3, #2
80036c6: e002 b.n 80036ce <HAL_GPIO_Init+0x1ee>
80036c8: 2301 movs r3, #1
80036ca: e000 b.n 80036ce <HAL_GPIO_Init+0x1ee>
80036cc: 2300 movs r3, #0
80036ce: 697a ldr r2, [r7, #20]
80036d0: f002 0203 and.w r2, r2, #3
80036d4: 0092 lsls r2, r2, #2
80036d6: 4093 lsls r3, r2
80036d8: 693a ldr r2, [r7, #16]
80036da: 4313 orrs r3, r2
80036dc: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
80036de: 4937 ldr r1, [pc, #220] @ (80037bc <HAL_GPIO_Init+0x2dc>)
80036e0: 697b ldr r3, [r7, #20]
80036e2: 089b lsrs r3, r3, #2
80036e4: 3302 adds r3, #2
80036e6: 693a ldr r2, [r7, #16]
80036e8: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80036ec: 4b38 ldr r3, [pc, #224] @ (80037d0 <HAL_GPIO_Init+0x2f0>)
80036ee: 689b ldr r3, [r3, #8]
80036f0: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80036f2: 68fb ldr r3, [r7, #12]
80036f4: 43db mvns r3, r3
80036f6: 693a ldr r2, [r7, #16]
80036f8: 4013 ands r3, r2
80036fa: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
80036fc: 683b ldr r3, [r7, #0]
80036fe: 685b ldr r3, [r3, #4]
8003700: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003704: 2b00 cmp r3, #0
8003706: d003 beq.n 8003710 <HAL_GPIO_Init+0x230>
{
temp |= iocurrent;
8003708: 693a ldr r2, [r7, #16]
800370a: 68fb ldr r3, [r7, #12]
800370c: 4313 orrs r3, r2
800370e: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8003710: 4a2f ldr r2, [pc, #188] @ (80037d0 <HAL_GPIO_Init+0x2f0>)
8003712: 693b ldr r3, [r7, #16]
8003714: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8003716: 4b2e ldr r3, [pc, #184] @ (80037d0 <HAL_GPIO_Init+0x2f0>)
8003718: 68db ldr r3, [r3, #12]
800371a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800371c: 68fb ldr r3, [r7, #12]
800371e: 43db mvns r3, r3
8003720: 693a ldr r2, [r7, #16]
8003722: 4013 ands r3, r2
8003724: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8003726: 683b ldr r3, [r7, #0]
8003728: 685b ldr r3, [r3, #4]
800372a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800372e: 2b00 cmp r3, #0
8003730: d003 beq.n 800373a <HAL_GPIO_Init+0x25a>
{
temp |= iocurrent;
8003732: 693a ldr r2, [r7, #16]
8003734: 68fb ldr r3, [r7, #12]
8003736: 4313 orrs r3, r2
8003738: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
800373a: 4a25 ldr r2, [pc, #148] @ (80037d0 <HAL_GPIO_Init+0x2f0>)
800373c: 693b ldr r3, [r7, #16]
800373e: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8003740: 4b23 ldr r3, [pc, #140] @ (80037d0 <HAL_GPIO_Init+0x2f0>)
8003742: 685b ldr r3, [r3, #4]
8003744: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003746: 68fb ldr r3, [r7, #12]
8003748: 43db mvns r3, r3
800374a: 693a ldr r2, [r7, #16]
800374c: 4013 ands r3, r2
800374e: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8003750: 683b ldr r3, [r7, #0]
8003752: 685b ldr r3, [r3, #4]
8003754: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003758: 2b00 cmp r3, #0
800375a: d003 beq.n 8003764 <HAL_GPIO_Init+0x284>
{
temp |= iocurrent;
800375c: 693a ldr r2, [r7, #16]
800375e: 68fb ldr r3, [r7, #12]
8003760: 4313 orrs r3, r2
8003762: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8003764: 4a1a ldr r2, [pc, #104] @ (80037d0 <HAL_GPIO_Init+0x2f0>)
8003766: 693b ldr r3, [r7, #16]
8003768: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
800376a: 4b19 ldr r3, [pc, #100] @ (80037d0 <HAL_GPIO_Init+0x2f0>)
800376c: 681b ldr r3, [r3, #0]
800376e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003770: 68fb ldr r3, [r7, #12]
8003772: 43db mvns r3, r3
8003774: 693a ldr r2, [r7, #16]
8003776: 4013 ands r3, r2
8003778: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
800377a: 683b ldr r3, [r7, #0]
800377c: 685b ldr r3, [r3, #4]
800377e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003782: 2b00 cmp r3, #0
8003784: d003 beq.n 800378e <HAL_GPIO_Init+0x2ae>
{
temp |= iocurrent;
8003786: 693a ldr r2, [r7, #16]
8003788: 68fb ldr r3, [r7, #12]
800378a: 4313 orrs r3, r2
800378c: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
800378e: 4a10 ldr r2, [pc, #64] @ (80037d0 <HAL_GPIO_Init+0x2f0>)
8003790: 693b ldr r3, [r7, #16]
8003792: 6013 str r3, [r2, #0]
}
}
position++;
8003794: 697b ldr r3, [r7, #20]
8003796: 3301 adds r3, #1
8003798: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
800379a: 683b ldr r3, [r7, #0]
800379c: 681a ldr r2, [r3, #0]
800379e: 697b ldr r3, [r7, #20]
80037a0: fa22 f303 lsr.w r3, r2, r3
80037a4: 2b00 cmp r3, #0
80037a6: f47f aea3 bne.w 80034f0 <HAL_GPIO_Init+0x10>
}
}
80037aa: bf00 nop
80037ac: bf00 nop
80037ae: 371c adds r7, #28
80037b0: 46bd mov sp, r7
80037b2: f85d 7b04 ldr.w r7, [sp], #4
80037b6: 4770 bx lr
80037b8: 40021000 .word 0x40021000
80037bc: 40010000 .word 0x40010000
80037c0: 48000400 .word 0x48000400
80037c4: 48000800 .word 0x48000800
80037c8: 48000c00 .word 0x48000c00
80037cc: 48001000 .word 0x48001000
80037d0: 40010400 .word 0x40010400
080037d4 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80037d4: b480 push {r7}
80037d6: b083 sub sp, #12
80037d8: af00 add r7, sp, #0
80037da: 6078 str r0, [r7, #4]
80037dc: 460b mov r3, r1
80037de: 807b strh r3, [r7, #2]
80037e0: 4613 mov r3, r2
80037e2: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80037e4: 787b ldrb r3, [r7, #1]
80037e6: 2b00 cmp r3, #0
80037e8: d003 beq.n 80037f2 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
80037ea: 887a ldrh r2, [r7, #2]
80037ec: 687b ldr r3, [r7, #4]
80037ee: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
80037f0: e002 b.n 80037f8 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
80037f2: 887a ldrh r2, [r7, #2]
80037f4: 687b ldr r3, [r7, #4]
80037f6: 629a str r2, [r3, #40] @ 0x28
}
80037f8: bf00 nop
80037fa: 370c adds r7, #12
80037fc: 46bd mov sp, r7
80037fe: f85d 7b04 ldr.w r7, [sp], #4
8003802: 4770 bx lr
08003804 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8003804: b580 push {r7, lr}
8003806: f5ad 7d00 sub.w sp, sp, #512 @ 0x200
800380a: af00 add r7, sp, #0
800380c: f507 7300 add.w r3, r7, #512 @ 0x200
8003810: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003814: 6018 str r0, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
uint32_t pll_config2;
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8003816: f507 7300 add.w r3, r7, #512 @ 0x200
800381a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800381e: 681b ldr r3, [r3, #0]
8003820: 2b00 cmp r3, #0
8003822: d102 bne.n 800382a <HAL_RCC_OscConfig+0x26>
{
return HAL_ERROR;
8003824: 2301 movs r3, #1
8003826: f001 b823 b.w 8004870 <HAL_RCC_OscConfig+0x106c>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800382a: f507 7300 add.w r3, r7, #512 @ 0x200
800382e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003832: 681b ldr r3, [r3, #0]
8003834: 681b ldr r3, [r3, #0]
8003836: f003 0301 and.w r3, r3, #1
800383a: 2b00 cmp r3, #0
800383c: f000 817d beq.w 8003b3a <HAL_RCC_OscConfig+0x336>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8003840: 4bbc ldr r3, [pc, #752] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003842: 685b ldr r3, [r3, #4]
8003844: f003 030c and.w r3, r3, #12
8003848: 2b04 cmp r3, #4
800384a: d00c beq.n 8003866 <HAL_RCC_OscConfig+0x62>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
800384c: 4bb9 ldr r3, [pc, #740] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
800384e: 685b ldr r3, [r3, #4]
8003850: f003 030c and.w r3, r3, #12
8003854: 2b08 cmp r3, #8
8003856: d15c bne.n 8003912 <HAL_RCC_OscConfig+0x10e>
8003858: 4bb6 ldr r3, [pc, #728] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
800385a: 685b ldr r3, [r3, #4]
800385c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003860: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003864: d155 bne.n 8003912 <HAL_RCC_OscConfig+0x10e>
8003866: f44f 3300 mov.w r3, #131072 @ 0x20000
800386a: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800386e: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0
8003872: fa93 f3a3 rbit r3, r3
8003876: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
800387a: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800387e: fab3 f383 clz r3, r3
8003882: b2db uxtb r3, r3
8003884: 095b lsrs r3, r3, #5
8003886: b2db uxtb r3, r3
8003888: f043 0301 orr.w r3, r3, #1
800388c: b2db uxtb r3, r3
800388e: 2b01 cmp r3, #1
8003890: d102 bne.n 8003898 <HAL_RCC_OscConfig+0x94>
8003892: 4ba8 ldr r3, [pc, #672] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003894: 681b ldr r3, [r3, #0]
8003896: e015 b.n 80038c4 <HAL_RCC_OscConfig+0xc0>
8003898: f44f 3300 mov.w r3, #131072 @ 0x20000
800389c: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80038a0: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8
80038a4: fa93 f3a3 rbit r3, r3
80038a8: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4
80038ac: f44f 3300 mov.w r3, #131072 @ 0x20000
80038b0: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0
80038b4: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0
80038b8: fa93 f3a3 rbit r3, r3
80038bc: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc
80038c0: 4b9c ldr r3, [pc, #624] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
80038c2: 6a5b ldr r3, [r3, #36] @ 0x24
80038c4: f44f 3200 mov.w r2, #131072 @ 0x20000
80038c8: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8
80038cc: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8
80038d0: fa92 f2a2 rbit r2, r2
80038d4: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4
return result;
80038d8: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4
80038dc: fab2 f282 clz r2, r2
80038e0: b2d2 uxtb r2, r2
80038e2: f042 0220 orr.w r2, r2, #32
80038e6: b2d2 uxtb r2, r2
80038e8: f002 021f and.w r2, r2, #31
80038ec: 2101 movs r1, #1
80038ee: fa01 f202 lsl.w r2, r1, r2
80038f2: 4013 ands r3, r2
80038f4: 2b00 cmp r3, #0
80038f6: f000 811f beq.w 8003b38 <HAL_RCC_OscConfig+0x334>
80038fa: f507 7300 add.w r3, r7, #512 @ 0x200
80038fe: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003902: 681b ldr r3, [r3, #0]
8003904: 685b ldr r3, [r3, #4]
8003906: 2b00 cmp r3, #0
8003908: f040 8116 bne.w 8003b38 <HAL_RCC_OscConfig+0x334>
{
return HAL_ERROR;
800390c: 2301 movs r3, #1
800390e: f000 bfaf b.w 8004870 <HAL_RCC_OscConfig+0x106c>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8003912: f507 7300 add.w r3, r7, #512 @ 0x200
8003916: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800391a: 681b ldr r3, [r3, #0]
800391c: 685b ldr r3, [r3, #4]
800391e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003922: d106 bne.n 8003932 <HAL_RCC_OscConfig+0x12e>
8003924: 4b83 ldr r3, [pc, #524] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003926: 681b ldr r3, [r3, #0]
8003928: 4a82 ldr r2, [pc, #520] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
800392a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800392e: 6013 str r3, [r2, #0]
8003930: e036 b.n 80039a0 <HAL_RCC_OscConfig+0x19c>
8003932: f507 7300 add.w r3, r7, #512 @ 0x200
8003936: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800393a: 681b ldr r3, [r3, #0]
800393c: 685b ldr r3, [r3, #4]
800393e: 2b00 cmp r3, #0
8003940: d10c bne.n 800395c <HAL_RCC_OscConfig+0x158>
8003942: 4b7c ldr r3, [pc, #496] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003944: 681b ldr r3, [r3, #0]
8003946: 4a7b ldr r2, [pc, #492] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003948: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800394c: 6013 str r3, [r2, #0]
800394e: 4b79 ldr r3, [pc, #484] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003950: 681b ldr r3, [r3, #0]
8003952: 4a78 ldr r2, [pc, #480] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003954: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8003958: 6013 str r3, [r2, #0]
800395a: e021 b.n 80039a0 <HAL_RCC_OscConfig+0x19c>
800395c: f507 7300 add.w r3, r7, #512 @ 0x200
8003960: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003964: 681b ldr r3, [r3, #0]
8003966: 685b ldr r3, [r3, #4]
8003968: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
800396c: d10c bne.n 8003988 <HAL_RCC_OscConfig+0x184>
800396e: 4b71 ldr r3, [pc, #452] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003970: 681b ldr r3, [r3, #0]
8003972: 4a70 ldr r2, [pc, #448] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003974: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8003978: 6013 str r3, [r2, #0]
800397a: 4b6e ldr r3, [pc, #440] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
800397c: 681b ldr r3, [r3, #0]
800397e: 4a6d ldr r2, [pc, #436] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003980: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003984: 6013 str r3, [r2, #0]
8003986: e00b b.n 80039a0 <HAL_RCC_OscConfig+0x19c>
8003988: 4b6a ldr r3, [pc, #424] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
800398a: 681b ldr r3, [r3, #0]
800398c: 4a69 ldr r2, [pc, #420] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
800398e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003992: 6013 str r3, [r2, #0]
8003994: 4b67 ldr r3, [pc, #412] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003996: 681b ldr r3, [r3, #0]
8003998: 4a66 ldr r2, [pc, #408] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
800399a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800399e: 6013 str r3, [r2, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
/* Configure the HSE predivision factor --------------------------------*/
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
80039a0: 4b64 ldr r3, [pc, #400] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
80039a2: 6adb ldr r3, [r3, #44] @ 0x2c
80039a4: f023 020f bic.w r2, r3, #15
80039a8: f507 7300 add.w r3, r7, #512 @ 0x200
80039ac: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80039b0: 681b ldr r3, [r3, #0]
80039b2: 689b ldr r3, [r3, #8]
80039b4: 495f ldr r1, [pc, #380] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
80039b6: 4313 orrs r3, r2
80039b8: 62cb str r3, [r1, #44] @ 0x2c
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80039ba: f507 7300 add.w r3, r7, #512 @ 0x200
80039be: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80039c2: 681b ldr r3, [r3, #0]
80039c4: 685b ldr r3, [r3, #4]
80039c6: 2b00 cmp r3, #0
80039c8: d059 beq.n 8003a7e <HAL_RCC_OscConfig+0x27a>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80039ca: f7fd fd15 bl 80013f8 <HAL_GetTick>
80039ce: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80039d2: e00a b.n 80039ea <HAL_RCC_OscConfig+0x1e6>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80039d4: f7fd fd10 bl 80013f8 <HAL_GetTick>
80039d8: 4602 mov r2, r0
80039da: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80039de: 1ad3 subs r3, r2, r3
80039e0: 2b64 cmp r3, #100 @ 0x64
80039e2: d902 bls.n 80039ea <HAL_RCC_OscConfig+0x1e6>
{
return HAL_TIMEOUT;
80039e4: 2303 movs r3, #3
80039e6: f000 bf43 b.w 8004870 <HAL_RCC_OscConfig+0x106c>
80039ea: f44f 3300 mov.w r3, #131072 @ 0x20000
80039ee: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80039f2: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0
80039f6: fa93 f3a3 rbit r3, r3
80039fa: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc
return result;
80039fe: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8003a02: fab3 f383 clz r3, r3
8003a06: b2db uxtb r3, r3
8003a08: 095b lsrs r3, r3, #5
8003a0a: b2db uxtb r3, r3
8003a0c: f043 0301 orr.w r3, r3, #1
8003a10: b2db uxtb r3, r3
8003a12: 2b01 cmp r3, #1
8003a14: d102 bne.n 8003a1c <HAL_RCC_OscConfig+0x218>
8003a16: 4b47 ldr r3, [pc, #284] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003a18: 681b ldr r3, [r3, #0]
8003a1a: e015 b.n 8003a48 <HAL_RCC_OscConfig+0x244>
8003a1c: f44f 3300 mov.w r3, #131072 @ 0x20000
8003a20: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003a24: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8
8003a28: fa93 f3a3 rbit r3, r3
8003a2c: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4
8003a30: f44f 3300 mov.w r3, #131072 @ 0x20000
8003a34: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0
8003a38: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0
8003a3c: fa93 f3a3 rbit r3, r3
8003a40: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc
8003a44: 4b3b ldr r3, [pc, #236] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003a46: 6a5b ldr r3, [r3, #36] @ 0x24
8003a48: f44f 3200 mov.w r2, #131072 @ 0x20000
8003a4c: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8
8003a50: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8
8003a54: fa92 f2a2 rbit r2, r2
8003a58: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4
return result;
8003a5c: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4
8003a60: fab2 f282 clz r2, r2
8003a64: b2d2 uxtb r2, r2
8003a66: f042 0220 orr.w r2, r2, #32
8003a6a: b2d2 uxtb r2, r2
8003a6c: f002 021f and.w r2, r2, #31
8003a70: 2101 movs r1, #1
8003a72: fa01 f202 lsl.w r2, r1, r2
8003a76: 4013 ands r3, r2
8003a78: 2b00 cmp r3, #0
8003a7a: d0ab beq.n 80039d4 <HAL_RCC_OscConfig+0x1d0>
8003a7c: e05d b.n 8003b3a <HAL_RCC_OscConfig+0x336>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8003a7e: f7fd fcbb bl 80013f8 <HAL_GetTick>
8003a82: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8003a86: e00a b.n 8003a9e <HAL_RCC_OscConfig+0x29a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8003a88: f7fd fcb6 bl 80013f8 <HAL_GetTick>
8003a8c: 4602 mov r2, r0
8003a8e: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8003a92: 1ad3 subs r3, r2, r3
8003a94: 2b64 cmp r3, #100 @ 0x64
8003a96: d902 bls.n 8003a9e <HAL_RCC_OscConfig+0x29a>
{
return HAL_TIMEOUT;
8003a98: 2303 movs r3, #3
8003a9a: f000 bee9 b.w 8004870 <HAL_RCC_OscConfig+0x106c>
8003a9e: f44f 3300 mov.w r3, #131072 @ 0x20000
8003aa2: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003aa6: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0
8003aaa: fa93 f3a3 rbit r3, r3
8003aae: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac
return result;
8003ab2: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8003ab6: fab3 f383 clz r3, r3
8003aba: b2db uxtb r3, r3
8003abc: 095b lsrs r3, r3, #5
8003abe: b2db uxtb r3, r3
8003ac0: f043 0301 orr.w r3, r3, #1
8003ac4: b2db uxtb r3, r3
8003ac6: 2b01 cmp r3, #1
8003ac8: d102 bne.n 8003ad0 <HAL_RCC_OscConfig+0x2cc>
8003aca: 4b1a ldr r3, [pc, #104] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003acc: 681b ldr r3, [r3, #0]
8003ace: e015 b.n 8003afc <HAL_RCC_OscConfig+0x2f8>
8003ad0: f44f 3300 mov.w r3, #131072 @ 0x20000
8003ad4: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003ad8: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8
8003adc: fa93 f3a3 rbit r3, r3
8003ae0: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4
8003ae4: f44f 3300 mov.w r3, #131072 @ 0x20000
8003ae8: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0
8003aec: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0
8003af0: fa93 f3a3 rbit r3, r3
8003af4: f8c7 319c str.w r3, [r7, #412] @ 0x19c
8003af8: 4b0e ldr r3, [pc, #56] @ (8003b34 <HAL_RCC_OscConfig+0x330>)
8003afa: 6a5b ldr r3, [r3, #36] @ 0x24
8003afc: f44f 3200 mov.w r2, #131072 @ 0x20000
8003b00: f8c7 2198 str.w r2, [r7, #408] @ 0x198
8003b04: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198
8003b08: fa92 f2a2 rbit r2, r2
8003b0c: f8c7 2194 str.w r2, [r7, #404] @ 0x194
return result;
8003b10: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194
8003b14: fab2 f282 clz r2, r2
8003b18: b2d2 uxtb r2, r2
8003b1a: f042 0220 orr.w r2, r2, #32
8003b1e: b2d2 uxtb r2, r2
8003b20: f002 021f and.w r2, r2, #31
8003b24: 2101 movs r1, #1
8003b26: fa01 f202 lsl.w r2, r1, r2
8003b2a: 4013 ands r3, r2
8003b2c: 2b00 cmp r3, #0
8003b2e: d1ab bne.n 8003a88 <HAL_RCC_OscConfig+0x284>
8003b30: e003 b.n 8003b3a <HAL_RCC_OscConfig+0x336>
8003b32: bf00 nop
8003b34: 40021000 .word 0x40021000
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003b38: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8003b3a: f507 7300 add.w r3, r7, #512 @ 0x200
8003b3e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003b42: 681b ldr r3, [r3, #0]
8003b44: 681b ldr r3, [r3, #0]
8003b46: f003 0302 and.w r3, r3, #2
8003b4a: 2b00 cmp r3, #0
8003b4c: f000 817d beq.w 8003e4a <HAL_RCC_OscConfig+0x646>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8003b50: 4ba6 ldr r3, [pc, #664] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003b52: 685b ldr r3, [r3, #4]
8003b54: f003 030c and.w r3, r3, #12
8003b58: 2b00 cmp r3, #0
8003b5a: d00b beq.n 8003b74 <HAL_RCC_OscConfig+0x370>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8003b5c: 4ba3 ldr r3, [pc, #652] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003b5e: 685b ldr r3, [r3, #4]
8003b60: f003 030c and.w r3, r3, #12
8003b64: 2b08 cmp r3, #8
8003b66: d172 bne.n 8003c4e <HAL_RCC_OscConfig+0x44a>
8003b68: 4ba0 ldr r3, [pc, #640] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003b6a: 685b ldr r3, [r3, #4]
8003b6c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003b70: 2b00 cmp r3, #0
8003b72: d16c bne.n 8003c4e <HAL_RCC_OscConfig+0x44a>
8003b74: 2302 movs r3, #2
8003b76: f8c7 3190 str.w r3, [r7, #400] @ 0x190
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003b7a: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190
8003b7e: fa93 f3a3 rbit r3, r3
8003b82: f8c7 318c str.w r3, [r7, #396] @ 0x18c
return result;
8003b86: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8003b8a: fab3 f383 clz r3, r3
8003b8e: b2db uxtb r3, r3
8003b90: 095b lsrs r3, r3, #5
8003b92: b2db uxtb r3, r3
8003b94: f043 0301 orr.w r3, r3, #1
8003b98: b2db uxtb r3, r3
8003b9a: 2b01 cmp r3, #1
8003b9c: d102 bne.n 8003ba4 <HAL_RCC_OscConfig+0x3a0>
8003b9e: 4b93 ldr r3, [pc, #588] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003ba0: 681b ldr r3, [r3, #0]
8003ba2: e013 b.n 8003bcc <HAL_RCC_OscConfig+0x3c8>
8003ba4: 2302 movs r3, #2
8003ba6: f8c7 3188 str.w r3, [r7, #392] @ 0x188
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003baa: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188
8003bae: fa93 f3a3 rbit r3, r3
8003bb2: f8c7 3184 str.w r3, [r7, #388] @ 0x184
8003bb6: 2302 movs r3, #2
8003bb8: f8c7 3180 str.w r3, [r7, #384] @ 0x180
8003bbc: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180
8003bc0: fa93 f3a3 rbit r3, r3
8003bc4: f8c7 317c str.w r3, [r7, #380] @ 0x17c
8003bc8: 4b88 ldr r3, [pc, #544] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003bca: 6a5b ldr r3, [r3, #36] @ 0x24
8003bcc: 2202 movs r2, #2
8003bce: f8c7 2178 str.w r2, [r7, #376] @ 0x178
8003bd2: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178
8003bd6: fa92 f2a2 rbit r2, r2
8003bda: f8c7 2174 str.w r2, [r7, #372] @ 0x174
return result;
8003bde: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174
8003be2: fab2 f282 clz r2, r2
8003be6: b2d2 uxtb r2, r2
8003be8: f042 0220 orr.w r2, r2, #32
8003bec: b2d2 uxtb r2, r2
8003bee: f002 021f and.w r2, r2, #31
8003bf2: 2101 movs r1, #1
8003bf4: fa01 f202 lsl.w r2, r1, r2
8003bf8: 4013 ands r3, r2
8003bfa: 2b00 cmp r3, #0
8003bfc: d00a beq.n 8003c14 <HAL_RCC_OscConfig+0x410>
8003bfe: f507 7300 add.w r3, r7, #512 @ 0x200
8003c02: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003c06: 681b ldr r3, [r3, #0]
8003c08: 691b ldr r3, [r3, #16]
8003c0a: 2b01 cmp r3, #1
8003c0c: d002 beq.n 8003c14 <HAL_RCC_OscConfig+0x410>
{
return HAL_ERROR;
8003c0e: 2301 movs r3, #1
8003c10: f000 be2e b.w 8004870 <HAL_RCC_OscConfig+0x106c>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003c14: 4b75 ldr r3, [pc, #468] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003c16: 681b ldr r3, [r3, #0]
8003c18: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8003c1c: f507 7300 add.w r3, r7, #512 @ 0x200
8003c20: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003c24: 681b ldr r3, [r3, #0]
8003c26: 695b ldr r3, [r3, #20]
8003c28: 21f8 movs r1, #248 @ 0xf8
8003c2a: f8c7 1170 str.w r1, [r7, #368] @ 0x170
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003c2e: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170
8003c32: fa91 f1a1 rbit r1, r1
8003c36: f8c7 116c str.w r1, [r7, #364] @ 0x16c
return result;
8003c3a: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c
8003c3e: fab1 f181 clz r1, r1
8003c42: b2c9 uxtb r1, r1
8003c44: 408b lsls r3, r1
8003c46: 4969 ldr r1, [pc, #420] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003c48: 4313 orrs r3, r2
8003c4a: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8003c4c: e0fd b.n 8003e4a <HAL_RCC_OscConfig+0x646>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8003c4e: f507 7300 add.w r3, r7, #512 @ 0x200
8003c52: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003c56: 681b ldr r3, [r3, #0]
8003c58: 691b ldr r3, [r3, #16]
8003c5a: 2b00 cmp r3, #0
8003c5c: f000 8088 beq.w 8003d70 <HAL_RCC_OscConfig+0x56c>
8003c60: 2301 movs r3, #1
8003c62: f8c7 3168 str.w r3, [r7, #360] @ 0x168
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003c66: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168
8003c6a: fa93 f3a3 rbit r3, r3
8003c6e: f8c7 3164 str.w r3, [r7, #356] @ 0x164
return result;
8003c72: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8003c76: fab3 f383 clz r3, r3
8003c7a: b2db uxtb r3, r3
8003c7c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8003c80: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8003c84: 009b lsls r3, r3, #2
8003c86: 461a mov r2, r3
8003c88: 2301 movs r3, #1
8003c8a: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003c8c: f7fd fbb4 bl 80013f8 <HAL_GetTick>
8003c90: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003c94: e00a b.n 8003cac <HAL_RCC_OscConfig+0x4a8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8003c96: f7fd fbaf bl 80013f8 <HAL_GetTick>
8003c9a: 4602 mov r2, r0
8003c9c: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8003ca0: 1ad3 subs r3, r2, r3
8003ca2: 2b02 cmp r3, #2
8003ca4: d902 bls.n 8003cac <HAL_RCC_OscConfig+0x4a8>
{
return HAL_TIMEOUT;
8003ca6: 2303 movs r3, #3
8003ca8: f000 bde2 b.w 8004870 <HAL_RCC_OscConfig+0x106c>
8003cac: 2302 movs r3, #2
8003cae: f8c7 3160 str.w r3, [r7, #352] @ 0x160
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003cb2: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160
8003cb6: fa93 f3a3 rbit r3, r3
8003cba: f8c7 315c str.w r3, [r7, #348] @ 0x15c
return result;
8003cbe: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003cc2: fab3 f383 clz r3, r3
8003cc6: b2db uxtb r3, r3
8003cc8: 095b lsrs r3, r3, #5
8003cca: b2db uxtb r3, r3
8003ccc: f043 0301 orr.w r3, r3, #1
8003cd0: b2db uxtb r3, r3
8003cd2: 2b01 cmp r3, #1
8003cd4: d102 bne.n 8003cdc <HAL_RCC_OscConfig+0x4d8>
8003cd6: 4b45 ldr r3, [pc, #276] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003cd8: 681b ldr r3, [r3, #0]
8003cda: e013 b.n 8003d04 <HAL_RCC_OscConfig+0x500>
8003cdc: 2302 movs r3, #2
8003cde: f8c7 3158 str.w r3, [r7, #344] @ 0x158
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003ce2: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158
8003ce6: fa93 f3a3 rbit r3, r3
8003cea: f8c7 3154 str.w r3, [r7, #340] @ 0x154
8003cee: 2302 movs r3, #2
8003cf0: f8c7 3150 str.w r3, [r7, #336] @ 0x150
8003cf4: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150
8003cf8: fa93 f3a3 rbit r3, r3
8003cfc: f8c7 314c str.w r3, [r7, #332] @ 0x14c
8003d00: 4b3a ldr r3, [pc, #232] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003d02: 6a5b ldr r3, [r3, #36] @ 0x24
8003d04: 2202 movs r2, #2
8003d06: f8c7 2148 str.w r2, [r7, #328] @ 0x148
8003d0a: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148
8003d0e: fa92 f2a2 rbit r2, r2
8003d12: f8c7 2144 str.w r2, [r7, #324] @ 0x144
return result;
8003d16: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144
8003d1a: fab2 f282 clz r2, r2
8003d1e: b2d2 uxtb r2, r2
8003d20: f042 0220 orr.w r2, r2, #32
8003d24: b2d2 uxtb r2, r2
8003d26: f002 021f and.w r2, r2, #31
8003d2a: 2101 movs r1, #1
8003d2c: fa01 f202 lsl.w r2, r1, r2
8003d30: 4013 ands r3, r2
8003d32: 2b00 cmp r3, #0
8003d34: d0af beq.n 8003c96 <HAL_RCC_OscConfig+0x492>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003d36: 4b2d ldr r3, [pc, #180] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003d38: 681b ldr r3, [r3, #0]
8003d3a: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8003d3e: f507 7300 add.w r3, r7, #512 @ 0x200
8003d42: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003d46: 681b ldr r3, [r3, #0]
8003d48: 695b ldr r3, [r3, #20]
8003d4a: 21f8 movs r1, #248 @ 0xf8
8003d4c: f8c7 1140 str.w r1, [r7, #320] @ 0x140
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003d50: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140
8003d54: fa91 f1a1 rbit r1, r1
8003d58: f8c7 113c str.w r1, [r7, #316] @ 0x13c
return result;
8003d5c: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c
8003d60: fab1 f181 clz r1, r1
8003d64: b2c9 uxtb r1, r1
8003d66: 408b lsls r3, r1
8003d68: 4920 ldr r1, [pc, #128] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003d6a: 4313 orrs r3, r2
8003d6c: 600b str r3, [r1, #0]
8003d6e: e06c b.n 8003e4a <HAL_RCC_OscConfig+0x646>
8003d70: 2301 movs r3, #1
8003d72: f8c7 3138 str.w r3, [r7, #312] @ 0x138
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003d76: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138
8003d7a: fa93 f3a3 rbit r3, r3
8003d7e: f8c7 3134 str.w r3, [r7, #308] @ 0x134
return result;
8003d82: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8003d86: fab3 f383 clz r3, r3
8003d8a: b2db uxtb r3, r3
8003d8c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8003d90: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8003d94: 009b lsls r3, r3, #2
8003d96: 461a mov r2, r3
8003d98: 2300 movs r3, #0
8003d9a: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003d9c: f7fd fb2c bl 80013f8 <HAL_GetTick>
8003da0: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8003da4: e00a b.n 8003dbc <HAL_RCC_OscConfig+0x5b8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8003da6: f7fd fb27 bl 80013f8 <HAL_GetTick>
8003daa: 4602 mov r2, r0
8003dac: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8003db0: 1ad3 subs r3, r2, r3
8003db2: 2b02 cmp r3, #2
8003db4: d902 bls.n 8003dbc <HAL_RCC_OscConfig+0x5b8>
{
return HAL_TIMEOUT;
8003db6: 2303 movs r3, #3
8003db8: f000 bd5a b.w 8004870 <HAL_RCC_OscConfig+0x106c>
8003dbc: 2302 movs r3, #2
8003dbe: f8c7 3130 str.w r3, [r7, #304] @ 0x130
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003dc2: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130
8003dc6: fa93 f3a3 rbit r3, r3
8003dca: f8c7 312c str.w r3, [r7, #300] @ 0x12c
return result;
8003dce: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8003dd2: fab3 f383 clz r3, r3
8003dd6: b2db uxtb r3, r3
8003dd8: 095b lsrs r3, r3, #5
8003dda: b2db uxtb r3, r3
8003ddc: f043 0301 orr.w r3, r3, #1
8003de0: b2db uxtb r3, r3
8003de2: 2b01 cmp r3, #1
8003de4: d104 bne.n 8003df0 <HAL_RCC_OscConfig+0x5ec>
8003de6: 4b01 ldr r3, [pc, #4] @ (8003dec <HAL_RCC_OscConfig+0x5e8>)
8003de8: 681b ldr r3, [r3, #0]
8003dea: e015 b.n 8003e18 <HAL_RCC_OscConfig+0x614>
8003dec: 40021000 .word 0x40021000
8003df0: 2302 movs r3, #2
8003df2: f8c7 3128 str.w r3, [r7, #296] @ 0x128
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003df6: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128
8003dfa: fa93 f3a3 rbit r3, r3
8003dfe: f8c7 3124 str.w r3, [r7, #292] @ 0x124
8003e02: 2302 movs r3, #2
8003e04: f8c7 3120 str.w r3, [r7, #288] @ 0x120
8003e08: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120
8003e0c: fa93 f3a3 rbit r3, r3
8003e10: f8c7 311c str.w r3, [r7, #284] @ 0x11c
8003e14: 4bc8 ldr r3, [pc, #800] @ (8004138 <HAL_RCC_OscConfig+0x934>)
8003e16: 6a5b ldr r3, [r3, #36] @ 0x24
8003e18: 2202 movs r2, #2
8003e1a: f8c7 2118 str.w r2, [r7, #280] @ 0x118
8003e1e: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118
8003e22: fa92 f2a2 rbit r2, r2
8003e26: f8c7 2114 str.w r2, [r7, #276] @ 0x114
return result;
8003e2a: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114
8003e2e: fab2 f282 clz r2, r2
8003e32: b2d2 uxtb r2, r2
8003e34: f042 0220 orr.w r2, r2, #32
8003e38: b2d2 uxtb r2, r2
8003e3a: f002 021f and.w r2, r2, #31
8003e3e: 2101 movs r1, #1
8003e40: fa01 f202 lsl.w r2, r1, r2
8003e44: 4013 ands r3, r2
8003e46: 2b00 cmp r3, #0
8003e48: d1ad bne.n 8003da6 <HAL_RCC_OscConfig+0x5a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003e4a: f507 7300 add.w r3, r7, #512 @ 0x200
8003e4e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003e52: 681b ldr r3, [r3, #0]
8003e54: 681b ldr r3, [r3, #0]
8003e56: f003 0308 and.w r3, r3, #8
8003e5a: 2b00 cmp r3, #0
8003e5c: f000 8110 beq.w 8004080 <HAL_RCC_OscConfig+0x87c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8003e60: f507 7300 add.w r3, r7, #512 @ 0x200
8003e64: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8003e68: 681b ldr r3, [r3, #0]
8003e6a: 699b ldr r3, [r3, #24]
8003e6c: 2b00 cmp r3, #0
8003e6e: d079 beq.n 8003f64 <HAL_RCC_OscConfig+0x760>
8003e70: 2301 movs r3, #1
8003e72: f8c7 3110 str.w r3, [r7, #272] @ 0x110
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003e76: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110
8003e7a: fa93 f3a3 rbit r3, r3
8003e7e: f8c7 310c str.w r3, [r7, #268] @ 0x10c
return result;
8003e82: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8003e86: fab3 f383 clz r3, r3
8003e8a: b2db uxtb r3, r3
8003e8c: 461a mov r2, r3
8003e8e: 4bab ldr r3, [pc, #684] @ (800413c <HAL_RCC_OscConfig+0x938>)
8003e90: 4413 add r3, r2
8003e92: 009b lsls r3, r3, #2
8003e94: 461a mov r2, r3
8003e96: 2301 movs r3, #1
8003e98: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003e9a: f7fd faad bl 80013f8 <HAL_GetTick>
8003e9e: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8003ea2: e00a b.n 8003eba <HAL_RCC_OscConfig+0x6b6>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8003ea4: f7fd faa8 bl 80013f8 <HAL_GetTick>
8003ea8: 4602 mov r2, r0
8003eaa: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8003eae: 1ad3 subs r3, r2, r3
8003eb0: 2b02 cmp r3, #2
8003eb2: d902 bls.n 8003eba <HAL_RCC_OscConfig+0x6b6>
{
return HAL_TIMEOUT;
8003eb4: 2303 movs r3, #3
8003eb6: f000 bcdb b.w 8004870 <HAL_RCC_OscConfig+0x106c>
8003eba: 2302 movs r3, #2
8003ebc: f8c7 3108 str.w r3, [r7, #264] @ 0x108
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003ec0: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108
8003ec4: fa93 f3a3 rbit r3, r3
8003ec8: f8c7 3104 str.w r3, [r7, #260] @ 0x104
8003ecc: f507 7300 add.w r3, r7, #512 @ 0x200
8003ed0: f5a3 7380 sub.w r3, r3, #256 @ 0x100
8003ed4: 2202 movs r2, #2
8003ed6: 601a str r2, [r3, #0]
8003ed8: f507 7300 add.w r3, r7, #512 @ 0x200
8003edc: f5a3 7380 sub.w r3, r3, #256 @ 0x100
8003ee0: 681b ldr r3, [r3, #0]
8003ee2: fa93 f2a3 rbit r2, r3
8003ee6: f507 7300 add.w r3, r7, #512 @ 0x200
8003eea: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8003eee: 601a str r2, [r3, #0]
8003ef0: f507 7300 add.w r3, r7, #512 @ 0x200
8003ef4: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8003ef8: 2202 movs r2, #2
8003efa: 601a str r2, [r3, #0]
8003efc: f507 7300 add.w r3, r7, #512 @ 0x200
8003f00: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8003f04: 681b ldr r3, [r3, #0]
8003f06: fa93 f2a3 rbit r2, r3
8003f0a: f507 7300 add.w r3, r7, #512 @ 0x200
8003f0e: f5a3 7386 sub.w r3, r3, #268 @ 0x10c
8003f12: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8003f14: 4b88 ldr r3, [pc, #544] @ (8004138 <HAL_RCC_OscConfig+0x934>)
8003f16: 6a5a ldr r2, [r3, #36] @ 0x24
8003f18: f507 7300 add.w r3, r7, #512 @ 0x200
8003f1c: f5a3 7388 sub.w r3, r3, #272 @ 0x110
8003f20: 2102 movs r1, #2
8003f22: 6019 str r1, [r3, #0]
8003f24: f507 7300 add.w r3, r7, #512 @ 0x200
8003f28: f5a3 7388 sub.w r3, r3, #272 @ 0x110
8003f2c: 681b ldr r3, [r3, #0]
8003f2e: fa93 f1a3 rbit r1, r3
8003f32: f507 7300 add.w r3, r7, #512 @ 0x200
8003f36: f5a3 738a sub.w r3, r3, #276 @ 0x114
8003f3a: 6019 str r1, [r3, #0]
return result;
8003f3c: f507 7300 add.w r3, r7, #512 @ 0x200
8003f40: f5a3 738a sub.w r3, r3, #276 @ 0x114
8003f44: 681b ldr r3, [r3, #0]
8003f46: fab3 f383 clz r3, r3
8003f4a: b2db uxtb r3, r3
8003f4c: f043 0360 orr.w r3, r3, #96 @ 0x60
8003f50: b2db uxtb r3, r3
8003f52: f003 031f and.w r3, r3, #31
8003f56: 2101 movs r1, #1
8003f58: fa01 f303 lsl.w r3, r1, r3
8003f5c: 4013 ands r3, r2
8003f5e: 2b00 cmp r3, #0
8003f60: d0a0 beq.n 8003ea4 <HAL_RCC_OscConfig+0x6a0>
8003f62: e08d b.n 8004080 <HAL_RCC_OscConfig+0x87c>
8003f64: f507 7300 add.w r3, r7, #512 @ 0x200
8003f68: f5a3 738c sub.w r3, r3, #280 @ 0x118
8003f6c: 2201 movs r2, #1
8003f6e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003f70: f507 7300 add.w r3, r7, #512 @ 0x200
8003f74: f5a3 738c sub.w r3, r3, #280 @ 0x118
8003f78: 681b ldr r3, [r3, #0]
8003f7a: fa93 f2a3 rbit r2, r3
8003f7e: f507 7300 add.w r3, r7, #512 @ 0x200
8003f82: f5a3 738e sub.w r3, r3, #284 @ 0x11c
8003f86: 601a str r2, [r3, #0]
return result;
8003f88: f507 7300 add.w r3, r7, #512 @ 0x200
8003f8c: f5a3 738e sub.w r3, r3, #284 @ 0x11c
8003f90: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8003f92: fab3 f383 clz r3, r3
8003f96: b2db uxtb r3, r3
8003f98: 461a mov r2, r3
8003f9a: 4b68 ldr r3, [pc, #416] @ (800413c <HAL_RCC_OscConfig+0x938>)
8003f9c: 4413 add r3, r2
8003f9e: 009b lsls r3, r3, #2
8003fa0: 461a mov r2, r3
8003fa2: 2300 movs r3, #0
8003fa4: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003fa6: f7fd fa27 bl 80013f8 <HAL_GetTick>
8003faa: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8003fae: e00a b.n 8003fc6 <HAL_RCC_OscConfig+0x7c2>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8003fb0: f7fd fa22 bl 80013f8 <HAL_GetTick>
8003fb4: 4602 mov r2, r0
8003fb6: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8003fba: 1ad3 subs r3, r2, r3
8003fbc: 2b02 cmp r3, #2
8003fbe: d902 bls.n 8003fc6 <HAL_RCC_OscConfig+0x7c2>
{
return HAL_TIMEOUT;
8003fc0: 2303 movs r3, #3
8003fc2: f000 bc55 b.w 8004870 <HAL_RCC_OscConfig+0x106c>
8003fc6: f507 7300 add.w r3, r7, #512 @ 0x200
8003fca: f5a3 7390 sub.w r3, r3, #288 @ 0x120
8003fce: 2202 movs r2, #2
8003fd0: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003fd2: f507 7300 add.w r3, r7, #512 @ 0x200
8003fd6: f5a3 7390 sub.w r3, r3, #288 @ 0x120
8003fda: 681b ldr r3, [r3, #0]
8003fdc: fa93 f2a3 rbit r2, r3
8003fe0: f507 7300 add.w r3, r7, #512 @ 0x200
8003fe4: f5a3 7392 sub.w r3, r3, #292 @ 0x124
8003fe8: 601a str r2, [r3, #0]
8003fea: f507 7300 add.w r3, r7, #512 @ 0x200
8003fee: f5a3 7394 sub.w r3, r3, #296 @ 0x128
8003ff2: 2202 movs r2, #2
8003ff4: 601a str r2, [r3, #0]
8003ff6: f507 7300 add.w r3, r7, #512 @ 0x200
8003ffa: f5a3 7394 sub.w r3, r3, #296 @ 0x128
8003ffe: 681b ldr r3, [r3, #0]
8004000: fa93 f2a3 rbit r2, r3
8004004: f507 7300 add.w r3, r7, #512 @ 0x200
8004008: f5a3 7396 sub.w r3, r3, #300 @ 0x12c
800400c: 601a str r2, [r3, #0]
800400e: f507 7300 add.w r3, r7, #512 @ 0x200
8004012: f5a3 7398 sub.w r3, r3, #304 @ 0x130
8004016: 2202 movs r2, #2
8004018: 601a str r2, [r3, #0]
800401a: f507 7300 add.w r3, r7, #512 @ 0x200
800401e: f5a3 7398 sub.w r3, r3, #304 @ 0x130
8004022: 681b ldr r3, [r3, #0]
8004024: fa93 f2a3 rbit r2, r3
8004028: f507 7300 add.w r3, r7, #512 @ 0x200
800402c: f5a3 739a sub.w r3, r3, #308 @ 0x134
8004030: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8004032: 4b41 ldr r3, [pc, #260] @ (8004138 <HAL_RCC_OscConfig+0x934>)
8004034: 6a5a ldr r2, [r3, #36] @ 0x24
8004036: f507 7300 add.w r3, r7, #512 @ 0x200
800403a: f5a3 739c sub.w r3, r3, #312 @ 0x138
800403e: 2102 movs r1, #2
8004040: 6019 str r1, [r3, #0]
8004042: f507 7300 add.w r3, r7, #512 @ 0x200
8004046: f5a3 739c sub.w r3, r3, #312 @ 0x138
800404a: 681b ldr r3, [r3, #0]
800404c: fa93 f1a3 rbit r1, r3
8004050: f507 7300 add.w r3, r7, #512 @ 0x200
8004054: f5a3 739e sub.w r3, r3, #316 @ 0x13c
8004058: 6019 str r1, [r3, #0]
return result;
800405a: f507 7300 add.w r3, r7, #512 @ 0x200
800405e: f5a3 739e sub.w r3, r3, #316 @ 0x13c
8004062: 681b ldr r3, [r3, #0]
8004064: fab3 f383 clz r3, r3
8004068: b2db uxtb r3, r3
800406a: f043 0360 orr.w r3, r3, #96 @ 0x60
800406e: b2db uxtb r3, r3
8004070: f003 031f and.w r3, r3, #31
8004074: 2101 movs r1, #1
8004076: fa01 f303 lsl.w r3, r1, r3
800407a: 4013 ands r3, r2
800407c: 2b00 cmp r3, #0
800407e: d197 bne.n 8003fb0 <HAL_RCC_OscConfig+0x7ac>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8004080: f507 7300 add.w r3, r7, #512 @ 0x200
8004084: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8004088: 681b ldr r3, [r3, #0]
800408a: 681b ldr r3, [r3, #0]
800408c: f003 0304 and.w r3, r3, #4
8004090: 2b00 cmp r3, #0
8004092: f000 81a1 beq.w 80043d8 <HAL_RCC_OscConfig+0xbd4>
{
FlagStatus pwrclkchanged = RESET;
8004096: 2300 movs r3, #0
8004098: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800409c: 4b26 ldr r3, [pc, #152] @ (8004138 <HAL_RCC_OscConfig+0x934>)
800409e: 69db ldr r3, [r3, #28]
80040a0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80040a4: 2b00 cmp r3, #0
80040a6: d116 bne.n 80040d6 <HAL_RCC_OscConfig+0x8d2>
{
__HAL_RCC_PWR_CLK_ENABLE();
80040a8: 4b23 ldr r3, [pc, #140] @ (8004138 <HAL_RCC_OscConfig+0x934>)
80040aa: 69db ldr r3, [r3, #28]
80040ac: 4a22 ldr r2, [pc, #136] @ (8004138 <HAL_RCC_OscConfig+0x934>)
80040ae: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80040b2: 61d3 str r3, [r2, #28]
80040b4: 4b20 ldr r3, [pc, #128] @ (8004138 <HAL_RCC_OscConfig+0x934>)
80040b6: 69db ldr r3, [r3, #28]
80040b8: f003 5280 and.w r2, r3, #268435456 @ 0x10000000
80040bc: f507 7300 add.w r3, r7, #512 @ 0x200
80040c0: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
80040c4: 601a str r2, [r3, #0]
80040c6: f507 7300 add.w r3, r7, #512 @ 0x200
80040ca: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
80040ce: 681b ldr r3, [r3, #0]
pwrclkchanged = SET;
80040d0: 2301 movs r3, #1
80040d2: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80040d6: 4b1a ldr r3, [pc, #104] @ (8004140 <HAL_RCC_OscConfig+0x93c>)
80040d8: 681b ldr r3, [r3, #0]
80040da: f403 7380 and.w r3, r3, #256 @ 0x100
80040de: 2b00 cmp r3, #0
80040e0: d11a bne.n 8004118 <HAL_RCC_OscConfig+0x914>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80040e2: 4b17 ldr r3, [pc, #92] @ (8004140 <HAL_RCC_OscConfig+0x93c>)
80040e4: 681b ldr r3, [r3, #0]
80040e6: 4a16 ldr r2, [pc, #88] @ (8004140 <HAL_RCC_OscConfig+0x93c>)
80040e8: f443 7380 orr.w r3, r3, #256 @ 0x100
80040ec: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80040ee: f7fd f983 bl 80013f8 <HAL_GetTick>
80040f2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80040f6: e009 b.n 800410c <HAL_RCC_OscConfig+0x908>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80040f8: f7fd f97e bl 80013f8 <HAL_GetTick>
80040fc: 4602 mov r2, r0
80040fe: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8004102: 1ad3 subs r3, r2, r3
8004104: 2b64 cmp r3, #100 @ 0x64
8004106: d901 bls.n 800410c <HAL_RCC_OscConfig+0x908>
{
return HAL_TIMEOUT;
8004108: 2303 movs r3, #3
800410a: e3b1 b.n 8004870 <HAL_RCC_OscConfig+0x106c>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800410c: 4b0c ldr r3, [pc, #48] @ (8004140 <HAL_RCC_OscConfig+0x93c>)
800410e: 681b ldr r3, [r3, #0]
8004110: f403 7380 and.w r3, r3, #256 @ 0x100
8004114: 2b00 cmp r3, #0
8004116: d0ef beq.n 80040f8 <HAL_RCC_OscConfig+0x8f4>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8004118: f507 7300 add.w r3, r7, #512 @ 0x200
800411c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8004120: 681b ldr r3, [r3, #0]
8004122: 68db ldr r3, [r3, #12]
8004124: 2b01 cmp r3, #1
8004126: d10d bne.n 8004144 <HAL_RCC_OscConfig+0x940>
8004128: 4b03 ldr r3, [pc, #12] @ (8004138 <HAL_RCC_OscConfig+0x934>)
800412a: 6a1b ldr r3, [r3, #32]
800412c: 4a02 ldr r2, [pc, #8] @ (8004138 <HAL_RCC_OscConfig+0x934>)
800412e: f043 0301 orr.w r3, r3, #1
8004132: 6213 str r3, [r2, #32]
8004134: e03c b.n 80041b0 <HAL_RCC_OscConfig+0x9ac>
8004136: bf00 nop
8004138: 40021000 .word 0x40021000
800413c: 10908120 .word 0x10908120
8004140: 40007000 .word 0x40007000
8004144: f507 7300 add.w r3, r7, #512 @ 0x200
8004148: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800414c: 681b ldr r3, [r3, #0]
800414e: 68db ldr r3, [r3, #12]
8004150: 2b00 cmp r3, #0
8004152: d10c bne.n 800416e <HAL_RCC_OscConfig+0x96a>
8004154: 4bc1 ldr r3, [pc, #772] @ (800445c <HAL_RCC_OscConfig+0xc58>)
8004156: 6a1b ldr r3, [r3, #32]
8004158: 4ac0 ldr r2, [pc, #768] @ (800445c <HAL_RCC_OscConfig+0xc58>)
800415a: f023 0301 bic.w r3, r3, #1
800415e: 6213 str r3, [r2, #32]
8004160: 4bbe ldr r3, [pc, #760] @ (800445c <HAL_RCC_OscConfig+0xc58>)
8004162: 6a1b ldr r3, [r3, #32]
8004164: 4abd ldr r2, [pc, #756] @ (800445c <HAL_RCC_OscConfig+0xc58>)
8004166: f023 0304 bic.w r3, r3, #4
800416a: 6213 str r3, [r2, #32]
800416c: e020 b.n 80041b0 <HAL_RCC_OscConfig+0x9ac>
800416e: f507 7300 add.w r3, r7, #512 @ 0x200
8004172: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8004176: 681b ldr r3, [r3, #0]
8004178: 68db ldr r3, [r3, #12]
800417a: 2b05 cmp r3, #5
800417c: d10c bne.n 8004198 <HAL_RCC_OscConfig+0x994>
800417e: 4bb7 ldr r3, [pc, #732] @ (800445c <HAL_RCC_OscConfig+0xc58>)
8004180: 6a1b ldr r3, [r3, #32]
8004182: 4ab6 ldr r2, [pc, #728] @ (800445c <HAL_RCC_OscConfig+0xc58>)
8004184: f043 0304 orr.w r3, r3, #4
8004188: 6213 str r3, [r2, #32]
800418a: 4bb4 ldr r3, [pc, #720] @ (800445c <HAL_RCC_OscConfig+0xc58>)
800418c: 6a1b ldr r3, [r3, #32]
800418e: 4ab3 ldr r2, [pc, #716] @ (800445c <HAL_RCC_OscConfig+0xc58>)
8004190: f043 0301 orr.w r3, r3, #1
8004194: 6213 str r3, [r2, #32]
8004196: e00b b.n 80041b0 <HAL_RCC_OscConfig+0x9ac>
8004198: 4bb0 ldr r3, [pc, #704] @ (800445c <HAL_RCC_OscConfig+0xc58>)
800419a: 6a1b ldr r3, [r3, #32]
800419c: 4aaf ldr r2, [pc, #700] @ (800445c <HAL_RCC_OscConfig+0xc58>)
800419e: f023 0301 bic.w r3, r3, #1
80041a2: 6213 str r3, [r2, #32]
80041a4: 4bad ldr r3, [pc, #692] @ (800445c <HAL_RCC_OscConfig+0xc58>)
80041a6: 6a1b ldr r3, [r3, #32]
80041a8: 4aac ldr r2, [pc, #688] @ (800445c <HAL_RCC_OscConfig+0xc58>)
80041aa: f023 0304 bic.w r3, r3, #4
80041ae: 6213 str r3, [r2, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80041b0: f507 7300 add.w r3, r7, #512 @ 0x200
80041b4: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80041b8: 681b ldr r3, [r3, #0]
80041ba: 68db ldr r3, [r3, #12]
80041bc: 2b00 cmp r3, #0
80041be: f000 8081 beq.w 80042c4 <HAL_RCC_OscConfig+0xac0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80041c2: f7fd f919 bl 80013f8 <HAL_GetTick>
80041c6: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80041ca: e00b b.n 80041e4 <HAL_RCC_OscConfig+0x9e0>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80041cc: f7fd f914 bl 80013f8 <HAL_GetTick>
80041d0: 4602 mov r2, r0
80041d2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80041d6: 1ad3 subs r3, r2, r3
80041d8: f241 3288 movw r2, #5000 @ 0x1388
80041dc: 4293 cmp r3, r2
80041de: d901 bls.n 80041e4 <HAL_RCC_OscConfig+0x9e0>
{
return HAL_TIMEOUT;
80041e0: 2303 movs r3, #3
80041e2: e345 b.n 8004870 <HAL_RCC_OscConfig+0x106c>
80041e4: f507 7300 add.w r3, r7, #512 @ 0x200
80041e8: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
80041ec: 2202 movs r2, #2
80041ee: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80041f0: f507 7300 add.w r3, r7, #512 @ 0x200
80041f4: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
80041f8: 681b ldr r3, [r3, #0]
80041fa: fa93 f2a3 rbit r2, r3
80041fe: f507 7300 add.w r3, r7, #512 @ 0x200
8004202: f5a3 73a2 sub.w r3, r3, #324 @ 0x144
8004206: 601a str r2, [r3, #0]
8004208: f507 7300 add.w r3, r7, #512 @ 0x200
800420c: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
8004210: 2202 movs r2, #2
8004212: 601a str r2, [r3, #0]
8004214: f507 7300 add.w r3, r7, #512 @ 0x200
8004218: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
800421c: 681b ldr r3, [r3, #0]
800421e: fa93 f2a3 rbit r2, r3
8004222: f507 7300 add.w r3, r7, #512 @ 0x200
8004226: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
800422a: 601a str r2, [r3, #0]
return result;
800422c: f507 7300 add.w r3, r7, #512 @ 0x200
8004230: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
8004234: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004236: fab3 f383 clz r3, r3
800423a: b2db uxtb r3, r3
800423c: 095b lsrs r3, r3, #5
800423e: b2db uxtb r3, r3
8004240: f043 0302 orr.w r3, r3, #2
8004244: b2db uxtb r3, r3
8004246: 2b02 cmp r3, #2
8004248: d102 bne.n 8004250 <HAL_RCC_OscConfig+0xa4c>
800424a: 4b84 ldr r3, [pc, #528] @ (800445c <HAL_RCC_OscConfig+0xc58>)
800424c: 6a1b ldr r3, [r3, #32]
800424e: e013 b.n 8004278 <HAL_RCC_OscConfig+0xa74>
8004250: f507 7300 add.w r3, r7, #512 @ 0x200
8004254: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
8004258: 2202 movs r2, #2
800425a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800425c: f507 7300 add.w r3, r7, #512 @ 0x200
8004260: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
8004264: 681b ldr r3, [r3, #0]
8004266: fa93 f2a3 rbit r2, r3
800426a: f507 7300 add.w r3, r7, #512 @ 0x200
800426e: f5a3 73aa sub.w r3, r3, #340 @ 0x154
8004272: 601a str r2, [r3, #0]
8004274: 4b79 ldr r3, [pc, #484] @ (800445c <HAL_RCC_OscConfig+0xc58>)
8004276: 6a5b ldr r3, [r3, #36] @ 0x24
8004278: f507 7200 add.w r2, r7, #512 @ 0x200
800427c: f5a2 72ac sub.w r2, r2, #344 @ 0x158
8004280: 2102 movs r1, #2
8004282: 6011 str r1, [r2, #0]
8004284: f507 7200 add.w r2, r7, #512 @ 0x200
8004288: f5a2 72ac sub.w r2, r2, #344 @ 0x158
800428c: 6812 ldr r2, [r2, #0]
800428e: fa92 f1a2 rbit r1, r2
8004292: f507 7200 add.w r2, r7, #512 @ 0x200
8004296: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
800429a: 6011 str r1, [r2, #0]
return result;
800429c: f507 7200 add.w r2, r7, #512 @ 0x200
80042a0: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
80042a4: 6812 ldr r2, [r2, #0]
80042a6: fab2 f282 clz r2, r2
80042aa: b2d2 uxtb r2, r2
80042ac: f042 0240 orr.w r2, r2, #64 @ 0x40
80042b0: b2d2 uxtb r2, r2
80042b2: f002 021f and.w r2, r2, #31
80042b6: 2101 movs r1, #1
80042b8: fa01 f202 lsl.w r2, r1, r2
80042bc: 4013 ands r3, r2
80042be: 2b00 cmp r3, #0
80042c0: d084 beq.n 80041cc <HAL_RCC_OscConfig+0x9c8>
80042c2: e07f b.n 80043c4 <HAL_RCC_OscConfig+0xbc0>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80042c4: f7fd f898 bl 80013f8 <HAL_GetTick>
80042c8: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80042cc: e00b b.n 80042e6 <HAL_RCC_OscConfig+0xae2>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80042ce: f7fd f893 bl 80013f8 <HAL_GetTick>
80042d2: 4602 mov r2, r0
80042d4: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80042d8: 1ad3 subs r3, r2, r3
80042da: f241 3288 movw r2, #5000 @ 0x1388
80042de: 4293 cmp r3, r2
80042e0: d901 bls.n 80042e6 <HAL_RCC_OscConfig+0xae2>
{
return HAL_TIMEOUT;
80042e2: 2303 movs r3, #3
80042e4: e2c4 b.n 8004870 <HAL_RCC_OscConfig+0x106c>
80042e6: f507 7300 add.w r3, r7, #512 @ 0x200
80042ea: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
80042ee: 2202 movs r2, #2
80042f0: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80042f2: f507 7300 add.w r3, r7, #512 @ 0x200
80042f6: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
80042fa: 681b ldr r3, [r3, #0]
80042fc: fa93 f2a3 rbit r2, r3
8004300: f507 7300 add.w r3, r7, #512 @ 0x200
8004304: f5a3 73b2 sub.w r3, r3, #356 @ 0x164
8004308: 601a str r2, [r3, #0]
800430a: f507 7300 add.w r3, r7, #512 @ 0x200
800430e: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
8004312: 2202 movs r2, #2
8004314: 601a str r2, [r3, #0]
8004316: f507 7300 add.w r3, r7, #512 @ 0x200
800431a: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
800431e: 681b ldr r3, [r3, #0]
8004320: fa93 f2a3 rbit r2, r3
8004324: f507 7300 add.w r3, r7, #512 @ 0x200
8004328: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
800432c: 601a str r2, [r3, #0]
return result;
800432e: f507 7300 add.w r3, r7, #512 @ 0x200
8004332: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
8004336: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8004338: fab3 f383 clz r3, r3
800433c: b2db uxtb r3, r3
800433e: 095b lsrs r3, r3, #5
8004340: b2db uxtb r3, r3
8004342: f043 0302 orr.w r3, r3, #2
8004346: b2db uxtb r3, r3
8004348: 2b02 cmp r3, #2
800434a: d102 bne.n 8004352 <HAL_RCC_OscConfig+0xb4e>
800434c: 4b43 ldr r3, [pc, #268] @ (800445c <HAL_RCC_OscConfig+0xc58>)
800434e: 6a1b ldr r3, [r3, #32]
8004350: e013 b.n 800437a <HAL_RCC_OscConfig+0xb76>
8004352: f507 7300 add.w r3, r7, #512 @ 0x200
8004356: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
800435a: 2202 movs r2, #2
800435c: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800435e: f507 7300 add.w r3, r7, #512 @ 0x200
8004362: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
8004366: 681b ldr r3, [r3, #0]
8004368: fa93 f2a3 rbit r2, r3
800436c: f507 7300 add.w r3, r7, #512 @ 0x200
8004370: f5a3 73ba sub.w r3, r3, #372 @ 0x174
8004374: 601a str r2, [r3, #0]
8004376: 4b39 ldr r3, [pc, #228] @ (800445c <HAL_RCC_OscConfig+0xc58>)
8004378: 6a5b ldr r3, [r3, #36] @ 0x24
800437a: f507 7200 add.w r2, r7, #512 @ 0x200
800437e: f5a2 72bc sub.w r2, r2, #376 @ 0x178
8004382: 2102 movs r1, #2
8004384: 6011 str r1, [r2, #0]
8004386: f507 7200 add.w r2, r7, #512 @ 0x200
800438a: f5a2 72bc sub.w r2, r2, #376 @ 0x178
800438e: 6812 ldr r2, [r2, #0]
8004390: fa92 f1a2 rbit r1, r2
8004394: f507 7200 add.w r2, r7, #512 @ 0x200
8004398: f5a2 72be sub.w r2, r2, #380 @ 0x17c
800439c: 6011 str r1, [r2, #0]
return result;
800439e: f507 7200 add.w r2, r7, #512 @ 0x200
80043a2: f5a2 72be sub.w r2, r2, #380 @ 0x17c
80043a6: 6812 ldr r2, [r2, #0]
80043a8: fab2 f282 clz r2, r2
80043ac: b2d2 uxtb r2, r2
80043ae: f042 0240 orr.w r2, r2, #64 @ 0x40
80043b2: b2d2 uxtb r2, r2
80043b4: f002 021f and.w r2, r2, #31
80043b8: 2101 movs r1, #1
80043ba: fa01 f202 lsl.w r2, r1, r2
80043be: 4013 ands r3, r2
80043c0: 2b00 cmp r3, #0
80043c2: d184 bne.n 80042ce <HAL_RCC_OscConfig+0xaca>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80043c4: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff
80043c8: 2b01 cmp r3, #1
80043ca: d105 bne.n 80043d8 <HAL_RCC_OscConfig+0xbd4>
{
__HAL_RCC_PWR_CLK_DISABLE();
80043cc: 4b23 ldr r3, [pc, #140] @ (800445c <HAL_RCC_OscConfig+0xc58>)
80043ce: 69db ldr r3, [r3, #28]
80043d0: 4a22 ldr r2, [pc, #136] @ (800445c <HAL_RCC_OscConfig+0xc58>)
80043d2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80043d6: 61d3 str r3, [r2, #28]
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80043d8: f507 7300 add.w r3, r7, #512 @ 0x200
80043dc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80043e0: 681b ldr r3, [r3, #0]
80043e2: 69db ldr r3, [r3, #28]
80043e4: 2b00 cmp r3, #0
80043e6: f000 8242 beq.w 800486e <HAL_RCC_OscConfig+0x106a>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80043ea: 4b1c ldr r3, [pc, #112] @ (800445c <HAL_RCC_OscConfig+0xc58>)
80043ec: 685b ldr r3, [r3, #4]
80043ee: f003 030c and.w r3, r3, #12
80043f2: 2b08 cmp r3, #8
80043f4: f000 8213 beq.w 800481e <HAL_RCC_OscConfig+0x101a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80043f8: f507 7300 add.w r3, r7, #512 @ 0x200
80043fc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8004400: 681b ldr r3, [r3, #0]
8004402: 69db ldr r3, [r3, #28]
8004404: 2b02 cmp r3, #2
8004406: f040 8162 bne.w 80046ce <HAL_RCC_OscConfig+0xeca>
800440a: f507 7300 add.w r3, r7, #512 @ 0x200
800440e: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
8004412: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8004416: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004418: f507 7300 add.w r3, r7, #512 @ 0x200
800441c: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
8004420: 681b ldr r3, [r3, #0]
8004422: fa93 f2a3 rbit r2, r3
8004426: f507 7300 add.w r3, r7, #512 @ 0x200
800442a: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
800442e: 601a str r2, [r3, #0]
return result;
8004430: f507 7300 add.w r3, r7, #512 @ 0x200
8004434: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
8004438: 681b ldr r3, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800443a: fab3 f383 clz r3, r3
800443e: b2db uxtb r3, r3
8004440: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8004444: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8004448: 009b lsls r3, r3, #2
800444a: 461a mov r2, r3
800444c: 2300 movs r3, #0
800444e: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004450: f7fc ffd2 bl 80013f8 <HAL_GetTick>
8004454: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004458: e00c b.n 8004474 <HAL_RCC_OscConfig+0xc70>
800445a: bf00 nop
800445c: 40021000 .word 0x40021000
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8004460: f7fc ffca bl 80013f8 <HAL_GetTick>
8004464: 4602 mov r2, r0
8004466: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
800446a: 1ad3 subs r3, r2, r3
800446c: 2b02 cmp r3, #2
800446e: d901 bls.n 8004474 <HAL_RCC_OscConfig+0xc70>
{
return HAL_TIMEOUT;
8004470: 2303 movs r3, #3
8004472: e1fd b.n 8004870 <HAL_RCC_OscConfig+0x106c>
8004474: f507 7300 add.w r3, r7, #512 @ 0x200
8004478: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
800447c: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8004480: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004482: f507 7300 add.w r3, r7, #512 @ 0x200
8004486: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
800448a: 681b ldr r3, [r3, #0]
800448c: fa93 f2a3 rbit r2, r3
8004490: f507 7300 add.w r3, r7, #512 @ 0x200
8004494: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
8004498: 601a str r2, [r3, #0]
return result;
800449a: f507 7300 add.w r3, r7, #512 @ 0x200
800449e: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
80044a2: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80044a4: fab3 f383 clz r3, r3
80044a8: b2db uxtb r3, r3
80044aa: 095b lsrs r3, r3, #5
80044ac: b2db uxtb r3, r3
80044ae: f043 0301 orr.w r3, r3, #1
80044b2: b2db uxtb r3, r3
80044b4: 2b01 cmp r3, #1
80044b6: d102 bne.n 80044be <HAL_RCC_OscConfig+0xcba>
80044b8: 4bb0 ldr r3, [pc, #704] @ (800477c <HAL_RCC_OscConfig+0xf78>)
80044ba: 681b ldr r3, [r3, #0]
80044bc: e027 b.n 800450e <HAL_RCC_OscConfig+0xd0a>
80044be: f507 7300 add.w r3, r7, #512 @ 0x200
80044c2: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
80044c6: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80044ca: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80044cc: f507 7300 add.w r3, r7, #512 @ 0x200
80044d0: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
80044d4: 681b ldr r3, [r3, #0]
80044d6: fa93 f2a3 rbit r2, r3
80044da: f507 7300 add.w r3, r7, #512 @ 0x200
80044de: f5a3 73ca sub.w r3, r3, #404 @ 0x194
80044e2: 601a str r2, [r3, #0]
80044e4: f507 7300 add.w r3, r7, #512 @ 0x200
80044e8: f5a3 73cc sub.w r3, r3, #408 @ 0x198
80044ec: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80044f0: 601a str r2, [r3, #0]
80044f2: f507 7300 add.w r3, r7, #512 @ 0x200
80044f6: f5a3 73cc sub.w r3, r3, #408 @ 0x198
80044fa: 681b ldr r3, [r3, #0]
80044fc: fa93 f2a3 rbit r2, r3
8004500: f507 7300 add.w r3, r7, #512 @ 0x200
8004504: f5a3 73ce sub.w r3, r3, #412 @ 0x19c
8004508: 601a str r2, [r3, #0]
800450a: 4b9c ldr r3, [pc, #624] @ (800477c <HAL_RCC_OscConfig+0xf78>)
800450c: 6a5b ldr r3, [r3, #36] @ 0x24
800450e: f507 7200 add.w r2, r7, #512 @ 0x200
8004512: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
8004516: f04f 7100 mov.w r1, #33554432 @ 0x2000000
800451a: 6011 str r1, [r2, #0]
800451c: f507 7200 add.w r2, r7, #512 @ 0x200
8004520: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
8004524: 6812 ldr r2, [r2, #0]
8004526: fa92 f1a2 rbit r1, r2
800452a: f507 7200 add.w r2, r7, #512 @ 0x200
800452e: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
8004532: 6011 str r1, [r2, #0]
return result;
8004534: f507 7200 add.w r2, r7, #512 @ 0x200
8004538: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
800453c: 6812 ldr r2, [r2, #0]
800453e: fab2 f282 clz r2, r2
8004542: b2d2 uxtb r2, r2
8004544: f042 0220 orr.w r2, r2, #32
8004548: b2d2 uxtb r2, r2
800454a: f002 021f and.w r2, r2, #31
800454e: 2101 movs r1, #1
8004550: fa01 f202 lsl.w r2, r1, r2
8004554: 4013 ands r3, r2
8004556: 2b00 cmp r3, #0
8004558: d182 bne.n 8004460 <HAL_RCC_OscConfig+0xc5c>
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
#else
/* Configure the main PLL clock source and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
800455a: 4b88 ldr r3, [pc, #544] @ (800477c <HAL_RCC_OscConfig+0xf78>)
800455c: 685b ldr r3, [r3, #4]
800455e: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8004562: f507 7300 add.w r3, r7, #512 @ 0x200
8004566: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800456a: 681b ldr r3, [r3, #0]
800456c: 6a59 ldr r1, [r3, #36] @ 0x24
800456e: f507 7300 add.w r3, r7, #512 @ 0x200
8004572: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8004576: 681b ldr r3, [r3, #0]
8004578: 6a1b ldr r3, [r3, #32]
800457a: 430b orrs r3, r1
800457c: 497f ldr r1, [pc, #508] @ (800477c <HAL_RCC_OscConfig+0xf78>)
800457e: 4313 orrs r3, r2
8004580: 604b str r3, [r1, #4]
8004582: f507 7300 add.w r3, r7, #512 @ 0x200
8004586: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
800458a: f04f 7280 mov.w r2, #16777216 @ 0x1000000
800458e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004590: f507 7300 add.w r3, r7, #512 @ 0x200
8004594: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
8004598: 681b ldr r3, [r3, #0]
800459a: fa93 f2a3 rbit r2, r3
800459e: f507 7300 add.w r3, r7, #512 @ 0x200
80045a2: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
80045a6: 601a str r2, [r3, #0]
return result;
80045a8: f507 7300 add.w r3, r7, #512 @ 0x200
80045ac: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
80045b0: 681b ldr r3, [r3, #0]
RCC_OscInitStruct->PLL.PLLMUL);
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80045b2: fab3 f383 clz r3, r3
80045b6: b2db uxtb r3, r3
80045b8: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
80045bc: f503 1384 add.w r3, r3, #1081344 @ 0x108000
80045c0: 009b lsls r3, r3, #2
80045c2: 461a mov r2, r3
80045c4: 2301 movs r3, #1
80045c6: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80045c8: f7fc ff16 bl 80013f8 <HAL_GetTick>
80045cc: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80045d0: e009 b.n 80045e6 <HAL_RCC_OscConfig+0xde2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80045d2: f7fc ff11 bl 80013f8 <HAL_GetTick>
80045d6: 4602 mov r2, r0
80045d8: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80045dc: 1ad3 subs r3, r2, r3
80045de: 2b02 cmp r3, #2
80045e0: d901 bls.n 80045e6 <HAL_RCC_OscConfig+0xde2>
{
return HAL_TIMEOUT;
80045e2: 2303 movs r3, #3
80045e4: e144 b.n 8004870 <HAL_RCC_OscConfig+0x106c>
80045e6: f507 7300 add.w r3, r7, #512 @ 0x200
80045ea: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
80045ee: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80045f2: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80045f4: f507 7300 add.w r3, r7, #512 @ 0x200
80045f8: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
80045fc: 681b ldr r3, [r3, #0]
80045fe: fa93 f2a3 rbit r2, r3
8004602: f507 7300 add.w r3, r7, #512 @ 0x200
8004606: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
800460a: 601a str r2, [r3, #0]
return result;
800460c: f507 7300 add.w r3, r7, #512 @ 0x200
8004610: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
8004614: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8004616: fab3 f383 clz r3, r3
800461a: b2db uxtb r3, r3
800461c: 095b lsrs r3, r3, #5
800461e: b2db uxtb r3, r3
8004620: f043 0301 orr.w r3, r3, #1
8004624: b2db uxtb r3, r3
8004626: 2b01 cmp r3, #1
8004628: d102 bne.n 8004630 <HAL_RCC_OscConfig+0xe2c>
800462a: 4b54 ldr r3, [pc, #336] @ (800477c <HAL_RCC_OscConfig+0xf78>)
800462c: 681b ldr r3, [r3, #0]
800462e: e027 b.n 8004680 <HAL_RCC_OscConfig+0xe7c>
8004630: f507 7300 add.w r3, r7, #512 @ 0x200
8004634: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
8004638: f04f 7200 mov.w r2, #33554432 @ 0x2000000
800463c: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800463e: f507 7300 add.w r3, r7, #512 @ 0x200
8004642: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
8004646: 681b ldr r3, [r3, #0]
8004648: fa93 f2a3 rbit r2, r3
800464c: f507 7300 add.w r3, r7, #512 @ 0x200
8004650: f5a3 73de sub.w r3, r3, #444 @ 0x1bc
8004654: 601a str r2, [r3, #0]
8004656: f507 7300 add.w r3, r7, #512 @ 0x200
800465a: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
800465e: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8004662: 601a str r2, [r3, #0]
8004664: f507 7300 add.w r3, r7, #512 @ 0x200
8004668: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
800466c: 681b ldr r3, [r3, #0]
800466e: fa93 f2a3 rbit r2, r3
8004672: f507 7300 add.w r3, r7, #512 @ 0x200
8004676: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4
800467a: 601a str r2, [r3, #0]
800467c: 4b3f ldr r3, [pc, #252] @ (800477c <HAL_RCC_OscConfig+0xf78>)
800467e: 6a5b ldr r3, [r3, #36] @ 0x24
8004680: f507 7200 add.w r2, r7, #512 @ 0x200
8004684: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
8004688: f04f 7100 mov.w r1, #33554432 @ 0x2000000
800468c: 6011 str r1, [r2, #0]
800468e: f507 7200 add.w r2, r7, #512 @ 0x200
8004692: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
8004696: 6812 ldr r2, [r2, #0]
8004698: fa92 f1a2 rbit r1, r2
800469c: f507 7200 add.w r2, r7, #512 @ 0x200
80046a0: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
80046a4: 6011 str r1, [r2, #0]
return result;
80046a6: f507 7200 add.w r2, r7, #512 @ 0x200
80046aa: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
80046ae: 6812 ldr r2, [r2, #0]
80046b0: fab2 f282 clz r2, r2
80046b4: b2d2 uxtb r2, r2
80046b6: f042 0220 orr.w r2, r2, #32
80046ba: b2d2 uxtb r2, r2
80046bc: f002 021f and.w r2, r2, #31
80046c0: 2101 movs r1, #1
80046c2: fa01 f202 lsl.w r2, r1, r2
80046c6: 4013 ands r3, r2
80046c8: 2b00 cmp r3, #0
80046ca: d082 beq.n 80045d2 <HAL_RCC_OscConfig+0xdce>
80046cc: e0cf b.n 800486e <HAL_RCC_OscConfig+0x106a>
80046ce: f507 7300 add.w r3, r7, #512 @ 0x200
80046d2: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
80046d6: f04f 7280 mov.w r2, #16777216 @ 0x1000000
80046da: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80046dc: f507 7300 add.w r3, r7, #512 @ 0x200
80046e0: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
80046e4: 681b ldr r3, [r3, #0]
80046e6: fa93 f2a3 rbit r2, r3
80046ea: f507 7300 add.w r3, r7, #512 @ 0x200
80046ee: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
80046f2: 601a str r2, [r3, #0]
return result;
80046f4: f507 7300 add.w r3, r7, #512 @ 0x200
80046f8: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
80046fc: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80046fe: fab3 f383 clz r3, r3
8004702: b2db uxtb r3, r3
8004704: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8004708: f503 1384 add.w r3, r3, #1081344 @ 0x108000
800470c: 009b lsls r3, r3, #2
800470e: 461a mov r2, r3
8004710: 2300 movs r3, #0
8004712: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004714: f7fc fe70 bl 80013f8 <HAL_GetTick>
8004718: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800471c: e009 b.n 8004732 <HAL_RCC_OscConfig+0xf2e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800471e: f7fc fe6b bl 80013f8 <HAL_GetTick>
8004722: 4602 mov r2, r0
8004724: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8004728: 1ad3 subs r3, r2, r3
800472a: 2b02 cmp r3, #2
800472c: d901 bls.n 8004732 <HAL_RCC_OscConfig+0xf2e>
{
return HAL_TIMEOUT;
800472e: 2303 movs r3, #3
8004730: e09e b.n 8004870 <HAL_RCC_OscConfig+0x106c>
8004732: f507 7300 add.w r3, r7, #512 @ 0x200
8004736: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
800473a: f04f 7200 mov.w r2, #33554432 @ 0x2000000
800473e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004740: f507 7300 add.w r3, r7, #512 @ 0x200
8004744: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
8004748: 681b ldr r3, [r3, #0]
800474a: fa93 f2a3 rbit r2, r3
800474e: f507 7300 add.w r3, r7, #512 @ 0x200
8004752: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
8004756: 601a str r2, [r3, #0]
return result;
8004758: f507 7300 add.w r3, r7, #512 @ 0x200
800475c: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
8004760: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004762: fab3 f383 clz r3, r3
8004766: b2db uxtb r3, r3
8004768: 095b lsrs r3, r3, #5
800476a: b2db uxtb r3, r3
800476c: f043 0301 orr.w r3, r3, #1
8004770: b2db uxtb r3, r3
8004772: 2b01 cmp r3, #1
8004774: d104 bne.n 8004780 <HAL_RCC_OscConfig+0xf7c>
8004776: 4b01 ldr r3, [pc, #4] @ (800477c <HAL_RCC_OscConfig+0xf78>)
8004778: 681b ldr r3, [r3, #0]
800477a: e029 b.n 80047d0 <HAL_RCC_OscConfig+0xfcc>
800477c: 40021000 .word 0x40021000
8004780: f507 7300 add.w r3, r7, #512 @ 0x200
8004784: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
8004788: f04f 7200 mov.w r2, #33554432 @ 0x2000000
800478c: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800478e: f507 7300 add.w r3, r7, #512 @ 0x200
8004792: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
8004796: 681b ldr r3, [r3, #0]
8004798: fa93 f2a3 rbit r2, r3
800479c: f507 7300 add.w r3, r7, #512 @ 0x200
80047a0: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4
80047a4: 601a str r2, [r3, #0]
80047a6: f507 7300 add.w r3, r7, #512 @ 0x200
80047aa: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
80047ae: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80047b2: 601a str r2, [r3, #0]
80047b4: f507 7300 add.w r3, r7, #512 @ 0x200
80047b8: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
80047bc: 681b ldr r3, [r3, #0]
80047be: fa93 f2a3 rbit r2, r3
80047c2: f507 7300 add.w r3, r7, #512 @ 0x200
80047c6: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec
80047ca: 601a str r2, [r3, #0]
80047cc: 4b2b ldr r3, [pc, #172] @ (800487c <HAL_RCC_OscConfig+0x1078>)
80047ce: 6a5b ldr r3, [r3, #36] @ 0x24
80047d0: f507 7200 add.w r2, r7, #512 @ 0x200
80047d4: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
80047d8: f04f 7100 mov.w r1, #33554432 @ 0x2000000
80047dc: 6011 str r1, [r2, #0]
80047de: f507 7200 add.w r2, r7, #512 @ 0x200
80047e2: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
80047e6: 6812 ldr r2, [r2, #0]
80047e8: fa92 f1a2 rbit r1, r2
80047ec: f507 7200 add.w r2, r7, #512 @ 0x200
80047f0: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
80047f4: 6011 str r1, [r2, #0]
return result;
80047f6: f507 7200 add.w r2, r7, #512 @ 0x200
80047fa: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
80047fe: 6812 ldr r2, [r2, #0]
8004800: fab2 f282 clz r2, r2
8004804: b2d2 uxtb r2, r2
8004806: f042 0220 orr.w r2, r2, #32
800480a: b2d2 uxtb r2, r2
800480c: f002 021f and.w r2, r2, #31
8004810: 2101 movs r1, #1
8004812: fa01 f202 lsl.w r2, r1, r2
8004816: 4013 ands r3, r2
8004818: 2b00 cmp r3, #0
800481a: d180 bne.n 800471e <HAL_RCC_OscConfig+0xf1a>
800481c: e027 b.n 800486e <HAL_RCC_OscConfig+0x106a>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
800481e: f507 7300 add.w r3, r7, #512 @ 0x200
8004822: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8004826: 681b ldr r3, [r3, #0]
8004828: 69db ldr r3, [r3, #28]
800482a: 2b01 cmp r3, #1
800482c: d101 bne.n 8004832 <HAL_RCC_OscConfig+0x102e>
{
return HAL_ERROR;
800482e: 2301 movs r3, #1
8004830: e01e b.n 8004870 <HAL_RCC_OscConfig+0x106c>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8004832: 4b12 ldr r3, [pc, #72] @ (800487c <HAL_RCC_OscConfig+0x1078>)
8004834: 685b ldr r3, [r3, #4]
8004836: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4
pll_config2 = RCC->CFGR2;
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
#else
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800483a: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
800483e: f403 3280 and.w r2, r3, #65536 @ 0x10000
8004842: f507 7300 add.w r3, r7, #512 @ 0x200
8004846: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800484a: 681b ldr r3, [r3, #0]
800484c: 6a1b ldr r3, [r3, #32]
800484e: 429a cmp r2, r3
8004850: d10b bne.n 800486a <HAL_RCC_OscConfig+0x1066>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8004852: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
8004856: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
800485a: f507 7300 add.w r3, r7, #512 @ 0x200
800485e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8004862: 681b ldr r3, [r3, #0]
8004864: 6a5b ldr r3, [r3, #36] @ 0x24
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8004866: 429a cmp r2, r3
8004868: d001 beq.n 800486e <HAL_RCC_OscConfig+0x106a>
#endif
{
return HAL_ERROR;
800486a: 2301 movs r3, #1
800486c: e000 b.n 8004870 <HAL_RCC_OscConfig+0x106c>
}
}
}
}
return HAL_OK;
800486e: 2300 movs r3, #0
}
8004870: 4618 mov r0, r3
8004872: f507 7700 add.w r7, r7, #512 @ 0x200
8004876: 46bd mov sp, r7
8004878: bd80 pop {r7, pc}
800487a: bf00 nop
800487c: 40021000 .word 0x40021000
08004880 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8004880: b580 push {r7, lr}
8004882: b09e sub sp, #120 @ 0x78
8004884: af00 add r7, sp, #0
8004886: 6078 str r0, [r7, #4]
8004888: 6039 str r1, [r7, #0]
uint32_t tickstart = 0U;
800488a: 2300 movs r3, #0
800488c: 677b str r3, [r7, #116] @ 0x74
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
800488e: 687b ldr r3, [r7, #4]
8004890: 2b00 cmp r3, #0
8004892: d101 bne.n 8004898 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8004894: 2301 movs r3, #1
8004896: e162 b.n 8004b5e <HAL_RCC_ClockConfig+0x2de>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8004898: 4b90 ldr r3, [pc, #576] @ (8004adc <HAL_RCC_ClockConfig+0x25c>)
800489a: 681b ldr r3, [r3, #0]
800489c: f003 0307 and.w r3, r3, #7
80048a0: 683a ldr r2, [r7, #0]
80048a2: 429a cmp r2, r3
80048a4: d910 bls.n 80048c8 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80048a6: 4b8d ldr r3, [pc, #564] @ (8004adc <HAL_RCC_ClockConfig+0x25c>)
80048a8: 681b ldr r3, [r3, #0]
80048aa: f023 0207 bic.w r2, r3, #7
80048ae: 498b ldr r1, [pc, #556] @ (8004adc <HAL_RCC_ClockConfig+0x25c>)
80048b0: 683b ldr r3, [r7, #0]
80048b2: 4313 orrs r3, r2
80048b4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80048b6: 4b89 ldr r3, [pc, #548] @ (8004adc <HAL_RCC_ClockConfig+0x25c>)
80048b8: 681b ldr r3, [r3, #0]
80048ba: f003 0307 and.w r3, r3, #7
80048be: 683a ldr r2, [r7, #0]
80048c0: 429a cmp r2, r3
80048c2: d001 beq.n 80048c8 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
80048c4: 2301 movs r3, #1
80048c6: e14a b.n 8004b5e <HAL_RCC_ClockConfig+0x2de>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80048c8: 687b ldr r3, [r7, #4]
80048ca: 681b ldr r3, [r3, #0]
80048cc: f003 0302 and.w r3, r3, #2
80048d0: 2b00 cmp r3, #0
80048d2: d008 beq.n 80048e6 <HAL_RCC_ClockConfig+0x66>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80048d4: 4b82 ldr r3, [pc, #520] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
80048d6: 685b ldr r3, [r3, #4]
80048d8: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80048dc: 687b ldr r3, [r7, #4]
80048de: 689b ldr r3, [r3, #8]
80048e0: 497f ldr r1, [pc, #508] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
80048e2: 4313 orrs r3, r2
80048e4: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80048e6: 687b ldr r3, [r7, #4]
80048e8: 681b ldr r3, [r3, #0]
80048ea: f003 0301 and.w r3, r3, #1
80048ee: 2b00 cmp r3, #0
80048f0: f000 80dc beq.w 8004aac <HAL_RCC_ClockConfig+0x22c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80048f4: 687b ldr r3, [r7, #4]
80048f6: 685b ldr r3, [r3, #4]
80048f8: 2b01 cmp r3, #1
80048fa: d13c bne.n 8004976 <HAL_RCC_ClockConfig+0xf6>
80048fc: f44f 3300 mov.w r3, #131072 @ 0x20000
8004900: 673b str r3, [r7, #112] @ 0x70
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004902: 6f3b ldr r3, [r7, #112] @ 0x70
8004904: fa93 f3a3 rbit r3, r3
8004908: 66fb str r3, [r7, #108] @ 0x6c
return result;
800490a: 6efb ldr r3, [r7, #108] @ 0x6c
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800490c: fab3 f383 clz r3, r3
8004910: b2db uxtb r3, r3
8004912: 095b lsrs r3, r3, #5
8004914: b2db uxtb r3, r3
8004916: f043 0301 orr.w r3, r3, #1
800491a: b2db uxtb r3, r3
800491c: 2b01 cmp r3, #1
800491e: d102 bne.n 8004926 <HAL_RCC_ClockConfig+0xa6>
8004920: 4b6f ldr r3, [pc, #444] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
8004922: 681b ldr r3, [r3, #0]
8004924: e00f b.n 8004946 <HAL_RCC_ClockConfig+0xc6>
8004926: f44f 3300 mov.w r3, #131072 @ 0x20000
800492a: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800492c: 6ebb ldr r3, [r7, #104] @ 0x68
800492e: fa93 f3a3 rbit r3, r3
8004932: 667b str r3, [r7, #100] @ 0x64
8004934: f44f 3300 mov.w r3, #131072 @ 0x20000
8004938: 663b str r3, [r7, #96] @ 0x60
800493a: 6e3b ldr r3, [r7, #96] @ 0x60
800493c: fa93 f3a3 rbit r3, r3
8004940: 65fb str r3, [r7, #92] @ 0x5c
8004942: 4b67 ldr r3, [pc, #412] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
8004944: 6a5b ldr r3, [r3, #36] @ 0x24
8004946: f44f 3200 mov.w r2, #131072 @ 0x20000
800494a: 65ba str r2, [r7, #88] @ 0x58
800494c: 6dba ldr r2, [r7, #88] @ 0x58
800494e: fa92 f2a2 rbit r2, r2
8004952: 657a str r2, [r7, #84] @ 0x54
return result;
8004954: 6d7a ldr r2, [r7, #84] @ 0x54
8004956: fab2 f282 clz r2, r2
800495a: b2d2 uxtb r2, r2
800495c: f042 0220 orr.w r2, r2, #32
8004960: b2d2 uxtb r2, r2
8004962: f002 021f and.w r2, r2, #31
8004966: 2101 movs r1, #1
8004968: fa01 f202 lsl.w r2, r1, r2
800496c: 4013 ands r3, r2
800496e: 2b00 cmp r3, #0
8004970: d17b bne.n 8004a6a <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8004972: 2301 movs r3, #1
8004974: e0f3 b.n 8004b5e <HAL_RCC_ClockConfig+0x2de>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8004976: 687b ldr r3, [r7, #4]
8004978: 685b ldr r3, [r3, #4]
800497a: 2b02 cmp r3, #2
800497c: d13c bne.n 80049f8 <HAL_RCC_ClockConfig+0x178>
800497e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8004982: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004984: 6d3b ldr r3, [r7, #80] @ 0x50
8004986: fa93 f3a3 rbit r3, r3
800498a: 64fb str r3, [r7, #76] @ 0x4c
return result;
800498c: 6cfb ldr r3, [r7, #76] @ 0x4c
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800498e: fab3 f383 clz r3, r3
8004992: b2db uxtb r3, r3
8004994: 095b lsrs r3, r3, #5
8004996: b2db uxtb r3, r3
8004998: f043 0301 orr.w r3, r3, #1
800499c: b2db uxtb r3, r3
800499e: 2b01 cmp r3, #1
80049a0: d102 bne.n 80049a8 <HAL_RCC_ClockConfig+0x128>
80049a2: 4b4f ldr r3, [pc, #316] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
80049a4: 681b ldr r3, [r3, #0]
80049a6: e00f b.n 80049c8 <HAL_RCC_ClockConfig+0x148>
80049a8: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80049ac: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80049ae: 6cbb ldr r3, [r7, #72] @ 0x48
80049b0: fa93 f3a3 rbit r3, r3
80049b4: 647b str r3, [r7, #68] @ 0x44
80049b6: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80049ba: 643b str r3, [r7, #64] @ 0x40
80049bc: 6c3b ldr r3, [r7, #64] @ 0x40
80049be: fa93 f3a3 rbit r3, r3
80049c2: 63fb str r3, [r7, #60] @ 0x3c
80049c4: 4b46 ldr r3, [pc, #280] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
80049c6: 6a5b ldr r3, [r3, #36] @ 0x24
80049c8: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80049cc: 63ba str r2, [r7, #56] @ 0x38
80049ce: 6bba ldr r2, [r7, #56] @ 0x38
80049d0: fa92 f2a2 rbit r2, r2
80049d4: 637a str r2, [r7, #52] @ 0x34
return result;
80049d6: 6b7a ldr r2, [r7, #52] @ 0x34
80049d8: fab2 f282 clz r2, r2
80049dc: b2d2 uxtb r2, r2
80049de: f042 0220 orr.w r2, r2, #32
80049e2: b2d2 uxtb r2, r2
80049e4: f002 021f and.w r2, r2, #31
80049e8: 2101 movs r1, #1
80049ea: fa01 f202 lsl.w r2, r1, r2
80049ee: 4013 ands r3, r2
80049f0: 2b00 cmp r3, #0
80049f2: d13a bne.n 8004a6a <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
80049f4: 2301 movs r3, #1
80049f6: e0b2 b.n 8004b5e <HAL_RCC_ClockConfig+0x2de>
80049f8: 2302 movs r3, #2
80049fa: 633b str r3, [r7, #48] @ 0x30
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80049fc: 6b3b ldr r3, [r7, #48] @ 0x30
80049fe: fa93 f3a3 rbit r3, r3
8004a02: 62fb str r3, [r7, #44] @ 0x2c
return result;
8004a04: 6afb ldr r3, [r7, #44] @ 0x2c
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8004a06: fab3 f383 clz r3, r3
8004a0a: b2db uxtb r3, r3
8004a0c: 095b lsrs r3, r3, #5
8004a0e: b2db uxtb r3, r3
8004a10: f043 0301 orr.w r3, r3, #1
8004a14: b2db uxtb r3, r3
8004a16: 2b01 cmp r3, #1
8004a18: d102 bne.n 8004a20 <HAL_RCC_ClockConfig+0x1a0>
8004a1a: 4b31 ldr r3, [pc, #196] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
8004a1c: 681b ldr r3, [r3, #0]
8004a1e: e00d b.n 8004a3c <HAL_RCC_ClockConfig+0x1bc>
8004a20: 2302 movs r3, #2
8004a22: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004a24: 6abb ldr r3, [r7, #40] @ 0x28
8004a26: fa93 f3a3 rbit r3, r3
8004a2a: 627b str r3, [r7, #36] @ 0x24
8004a2c: 2302 movs r3, #2
8004a2e: 623b str r3, [r7, #32]
8004a30: 6a3b ldr r3, [r7, #32]
8004a32: fa93 f3a3 rbit r3, r3
8004a36: 61fb str r3, [r7, #28]
8004a38: 4b29 ldr r3, [pc, #164] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
8004a3a: 6a5b ldr r3, [r3, #36] @ 0x24
8004a3c: 2202 movs r2, #2
8004a3e: 61ba str r2, [r7, #24]
8004a40: 69ba ldr r2, [r7, #24]
8004a42: fa92 f2a2 rbit r2, r2
8004a46: 617a str r2, [r7, #20]
return result;
8004a48: 697a ldr r2, [r7, #20]
8004a4a: fab2 f282 clz r2, r2
8004a4e: b2d2 uxtb r2, r2
8004a50: f042 0220 orr.w r2, r2, #32
8004a54: b2d2 uxtb r2, r2
8004a56: f002 021f and.w r2, r2, #31
8004a5a: 2101 movs r1, #1
8004a5c: fa01 f202 lsl.w r2, r1, r2
8004a60: 4013 ands r3, r2
8004a62: 2b00 cmp r3, #0
8004a64: d101 bne.n 8004a6a <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8004a66: 2301 movs r3, #1
8004a68: e079 b.n 8004b5e <HAL_RCC_ClockConfig+0x2de>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8004a6a: 4b1d ldr r3, [pc, #116] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
8004a6c: 685b ldr r3, [r3, #4]
8004a6e: f023 0203 bic.w r2, r3, #3
8004a72: 687b ldr r3, [r7, #4]
8004a74: 685b ldr r3, [r3, #4]
8004a76: 491a ldr r1, [pc, #104] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
8004a78: 4313 orrs r3, r2
8004a7a: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004a7c: f7fc fcbc bl 80013f8 <HAL_GetTick>
8004a80: 6778 str r0, [r7, #116] @ 0x74
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004a82: e00a b.n 8004a9a <HAL_RCC_ClockConfig+0x21a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8004a84: f7fc fcb8 bl 80013f8 <HAL_GetTick>
8004a88: 4602 mov r2, r0
8004a8a: 6f7b ldr r3, [r7, #116] @ 0x74
8004a8c: 1ad3 subs r3, r2, r3
8004a8e: f241 3288 movw r2, #5000 @ 0x1388
8004a92: 4293 cmp r3, r2
8004a94: d901 bls.n 8004a9a <HAL_RCC_ClockConfig+0x21a>
{
return HAL_TIMEOUT;
8004a96: 2303 movs r3, #3
8004a98: e061 b.n 8004b5e <HAL_RCC_ClockConfig+0x2de>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004a9a: 4b11 ldr r3, [pc, #68] @ (8004ae0 <HAL_RCC_ClockConfig+0x260>)
8004a9c: 685b ldr r3, [r3, #4]
8004a9e: f003 020c and.w r2, r3, #12
8004aa2: 687b ldr r3, [r7, #4]
8004aa4: 685b ldr r3, [r3, #4]
8004aa6: 009b lsls r3, r3, #2
8004aa8: 429a cmp r2, r3
8004aaa: d1eb bne.n 8004a84 <HAL_RCC_ClockConfig+0x204>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8004aac: 4b0b ldr r3, [pc, #44] @ (8004adc <HAL_RCC_ClockConfig+0x25c>)
8004aae: 681b ldr r3, [r3, #0]
8004ab0: f003 0307 and.w r3, r3, #7
8004ab4: 683a ldr r2, [r7, #0]
8004ab6: 429a cmp r2, r3
8004ab8: d214 bcs.n 8004ae4 <HAL_RCC_ClockConfig+0x264>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004aba: 4b08 ldr r3, [pc, #32] @ (8004adc <HAL_RCC_ClockConfig+0x25c>)
8004abc: 681b ldr r3, [r3, #0]
8004abe: f023 0207 bic.w r2, r3, #7
8004ac2: 4906 ldr r1, [pc, #24] @ (8004adc <HAL_RCC_ClockConfig+0x25c>)
8004ac4: 683b ldr r3, [r7, #0]
8004ac6: 4313 orrs r3, r2
8004ac8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8004aca: 4b04 ldr r3, [pc, #16] @ (8004adc <HAL_RCC_ClockConfig+0x25c>)
8004acc: 681b ldr r3, [r3, #0]
8004ace: f003 0307 and.w r3, r3, #7
8004ad2: 683a ldr r2, [r7, #0]
8004ad4: 429a cmp r2, r3
8004ad6: d005 beq.n 8004ae4 <HAL_RCC_ClockConfig+0x264>
{
return HAL_ERROR;
8004ad8: 2301 movs r3, #1
8004ada: e040 b.n 8004b5e <HAL_RCC_ClockConfig+0x2de>
8004adc: 40022000 .word 0x40022000
8004ae0: 40021000 .word 0x40021000
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004ae4: 687b ldr r3, [r7, #4]
8004ae6: 681b ldr r3, [r3, #0]
8004ae8: f003 0304 and.w r3, r3, #4
8004aec: 2b00 cmp r3, #0
8004aee: d008 beq.n 8004b02 <HAL_RCC_ClockConfig+0x282>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8004af0: 4b1d ldr r3, [pc, #116] @ (8004b68 <HAL_RCC_ClockConfig+0x2e8>)
8004af2: 685b ldr r3, [r3, #4]
8004af4: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8004af8: 687b ldr r3, [r7, #4]
8004afa: 68db ldr r3, [r3, #12]
8004afc: 491a ldr r1, [pc, #104] @ (8004b68 <HAL_RCC_ClockConfig+0x2e8>)
8004afe: 4313 orrs r3, r2
8004b00: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8004b02: 687b ldr r3, [r7, #4]
8004b04: 681b ldr r3, [r3, #0]
8004b06: f003 0308 and.w r3, r3, #8
8004b0a: 2b00 cmp r3, #0
8004b0c: d009 beq.n 8004b22 <HAL_RCC_ClockConfig+0x2a2>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8004b0e: 4b16 ldr r3, [pc, #88] @ (8004b68 <HAL_RCC_ClockConfig+0x2e8>)
8004b10: 685b ldr r3, [r3, #4]
8004b12: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8004b16: 687b ldr r3, [r7, #4]
8004b18: 691b ldr r3, [r3, #16]
8004b1a: 00db lsls r3, r3, #3
8004b1c: 4912 ldr r1, [pc, #72] @ (8004b68 <HAL_RCC_ClockConfig+0x2e8>)
8004b1e: 4313 orrs r3, r2
8004b20: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8004b22: f000 f829 bl 8004b78 <HAL_RCC_GetSysClockFreq>
8004b26: 4601 mov r1, r0
8004b28: 4b0f ldr r3, [pc, #60] @ (8004b68 <HAL_RCC_ClockConfig+0x2e8>)
8004b2a: 685b ldr r3, [r3, #4]
8004b2c: f003 03f0 and.w r3, r3, #240 @ 0xf0
8004b30: 22f0 movs r2, #240 @ 0xf0
8004b32: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004b34: 693a ldr r2, [r7, #16]
8004b36: fa92 f2a2 rbit r2, r2
8004b3a: 60fa str r2, [r7, #12]
return result;
8004b3c: 68fa ldr r2, [r7, #12]
8004b3e: fab2 f282 clz r2, r2
8004b42: b2d2 uxtb r2, r2
8004b44: 40d3 lsrs r3, r2
8004b46: 4a09 ldr r2, [pc, #36] @ (8004b6c <HAL_RCC_ClockConfig+0x2ec>)
8004b48: 5cd3 ldrb r3, [r2, r3]
8004b4a: fa21 f303 lsr.w r3, r1, r3
8004b4e: 4a08 ldr r2, [pc, #32] @ (8004b70 <HAL_RCC_ClockConfig+0x2f0>)
8004b50: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (uwTickPrio);
8004b52: 4b08 ldr r3, [pc, #32] @ (8004b74 <HAL_RCC_ClockConfig+0x2f4>)
8004b54: 681b ldr r3, [r3, #0]
8004b56: 4618 mov r0, r3
8004b58: f7fc fc0a bl 8001370 <HAL_InitTick>
return HAL_OK;
8004b5c: 2300 movs r3, #0
}
8004b5e: 4618 mov r0, r3
8004b60: 3778 adds r7, #120 @ 0x78
8004b62: 46bd mov sp, r7
8004b64: bd80 pop {r7, pc}
8004b66: bf00 nop
8004b68: 40021000 .word 0x40021000
8004b6c: 08005e6c .word 0x08005e6c
8004b70: 20000000 .word 0x20000000
8004b74: 20000004 .word 0x20000004
08004b78 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8004b78: b480 push {r7}
8004b7a: b08b sub sp, #44 @ 0x2c
8004b7c: af00 add r7, sp, #0
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8004b7e: 2300 movs r3, #0
8004b80: 61fb str r3, [r7, #28]
8004b82: 2300 movs r3, #0
8004b84: 61bb str r3, [r7, #24]
8004b86: 2300 movs r3, #0
8004b88: 627b str r3, [r7, #36] @ 0x24
8004b8a: 2300 movs r3, #0
8004b8c: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
8004b8e: 2300 movs r3, #0
8004b90: 623b str r3, [r7, #32]
tmpreg = RCC->CFGR;
8004b92: 4b29 ldr r3, [pc, #164] @ (8004c38 <HAL_RCC_GetSysClockFreq+0xc0>)
8004b94: 685b ldr r3, [r3, #4]
8004b96: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8004b98: 69fb ldr r3, [r7, #28]
8004b9a: f003 030c and.w r3, r3, #12
8004b9e: 2b04 cmp r3, #4
8004ba0: d002 beq.n 8004ba8 <HAL_RCC_GetSysClockFreq+0x30>
8004ba2: 2b08 cmp r3, #8
8004ba4: d003 beq.n 8004bae <HAL_RCC_GetSysClockFreq+0x36>
8004ba6: e03c b.n 8004c22 <HAL_RCC_GetSysClockFreq+0xaa>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8004ba8: 4b24 ldr r3, [pc, #144] @ (8004c3c <HAL_RCC_GetSysClockFreq+0xc4>)
8004baa: 623b str r3, [r7, #32]
break;
8004bac: e03c b.n 8004c28 <HAL_RCC_GetSysClockFreq+0xb0>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
8004bae: 69fb ldr r3, [r7, #28]
8004bb0: f403 1370 and.w r3, r3, #3932160 @ 0x3c0000
8004bb4: f44f 1270 mov.w r2, #3932160 @ 0x3c0000
8004bb8: 60ba str r2, [r7, #8]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004bba: 68ba ldr r2, [r7, #8]
8004bbc: fa92 f2a2 rbit r2, r2
8004bc0: 607a str r2, [r7, #4]
return result;
8004bc2: 687a ldr r2, [r7, #4]
8004bc4: fab2 f282 clz r2, r2
8004bc8: b2d2 uxtb r2, r2
8004bca: 40d3 lsrs r3, r2
8004bcc: 4a1c ldr r2, [pc, #112] @ (8004c40 <HAL_RCC_GetSysClockFreq+0xc8>)
8004bce: 5cd3 ldrb r3, [r2, r3]
8004bd0: 617b str r3, [r7, #20]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
8004bd2: 4b19 ldr r3, [pc, #100] @ (8004c38 <HAL_RCC_GetSysClockFreq+0xc0>)
8004bd4: 6adb ldr r3, [r3, #44] @ 0x2c
8004bd6: f003 030f and.w r3, r3, #15
8004bda: 220f movs r2, #15
8004bdc: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004bde: 693a ldr r2, [r7, #16]
8004be0: fa92 f2a2 rbit r2, r2
8004be4: 60fa str r2, [r7, #12]
return result;
8004be6: 68fa ldr r2, [r7, #12]
8004be8: fab2 f282 clz r2, r2
8004bec: b2d2 uxtb r2, r2
8004bee: 40d3 lsrs r3, r2
8004bf0: 4a14 ldr r2, [pc, #80] @ (8004c44 <HAL_RCC_GetSysClockFreq+0xcc>)
8004bf2: 5cd3 ldrb r3, [r2, r3]
8004bf4: 61bb str r3, [r7, #24]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
8004bf6: 69fb ldr r3, [r7, #28]
8004bf8: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004bfc: 2b00 cmp r3, #0
8004bfe: d008 beq.n 8004c12 <HAL_RCC_GetSysClockFreq+0x9a>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8004c00: 4a0e ldr r2, [pc, #56] @ (8004c3c <HAL_RCC_GetSysClockFreq+0xc4>)
8004c02: 69bb ldr r3, [r7, #24]
8004c04: fbb2 f2f3 udiv r2, r2, r3
8004c08: 697b ldr r3, [r7, #20]
8004c0a: fb02 f303 mul.w r3, r2, r3
8004c0e: 627b str r3, [r7, #36] @ 0x24
8004c10: e004 b.n 8004c1c <HAL_RCC_GetSysClockFreq+0xa4>
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
8004c12: 697b ldr r3, [r7, #20]
8004c14: 4a0c ldr r2, [pc, #48] @ (8004c48 <HAL_RCC_GetSysClockFreq+0xd0>)
8004c16: fb02 f303 mul.w r3, r2, r3
8004c1a: 627b str r3, [r7, #36] @ 0x24
{
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
}
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
sysclockfreq = pllclk;
8004c1c: 6a7b ldr r3, [r7, #36] @ 0x24
8004c1e: 623b str r3, [r7, #32]
break;
8004c20: e002 b.n 8004c28 <HAL_RCC_GetSysClockFreq+0xb0>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8004c22: 4b0a ldr r3, [pc, #40] @ (8004c4c <HAL_RCC_GetSysClockFreq+0xd4>)
8004c24: 623b str r3, [r7, #32]
break;
8004c26: bf00 nop
}
}
return sysclockfreq;
8004c28: 6a3b ldr r3, [r7, #32]
}
8004c2a: 4618 mov r0, r3
8004c2c: 372c adds r7, #44 @ 0x2c
8004c2e: 46bd mov sp, r7
8004c30: f85d 7b04 ldr.w r7, [sp], #4
8004c34: 4770 bx lr
8004c36: bf00 nop
8004c38: 40021000 .word 0x40021000
8004c3c: 00f42400 .word 0x00f42400
8004c40: 08005e84 .word 0x08005e84
8004c44: 08005e94 .word 0x08005e94
8004c48: 003d0900 .word 0x003d0900
8004c4c: 007a1200 .word 0x007a1200
08004c50 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8004c50: b480 push {r7}
8004c52: af00 add r7, sp, #0
return SystemCoreClock;
8004c54: 4b03 ldr r3, [pc, #12] @ (8004c64 <HAL_RCC_GetHCLKFreq+0x14>)
8004c56: 681b ldr r3, [r3, #0]
}
8004c58: 4618 mov r0, r3
8004c5a: 46bd mov sp, r7
8004c5c: f85d 7b04 ldr.w r7, [sp], #4
8004c60: 4770 bx lr
8004c62: bf00 nop
8004c64: 20000000 .word 0x20000000
08004c68 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8004c68: b580 push {r7, lr}
8004c6a: b082 sub sp, #8
8004c6c: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
8004c6e: f7ff ffef bl 8004c50 <HAL_RCC_GetHCLKFreq>
8004c72: 4601 mov r1, r0
8004c74: 4b0b ldr r3, [pc, #44] @ (8004ca4 <HAL_RCC_GetPCLK1Freq+0x3c>)
8004c76: 685b ldr r3, [r3, #4]
8004c78: f403 63e0 and.w r3, r3, #1792 @ 0x700
8004c7c: f44f 62e0 mov.w r2, #1792 @ 0x700
8004c80: 607a str r2, [r7, #4]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004c82: 687a ldr r2, [r7, #4]
8004c84: fa92 f2a2 rbit r2, r2
8004c88: 603a str r2, [r7, #0]
return result;
8004c8a: 683a ldr r2, [r7, #0]
8004c8c: fab2 f282 clz r2, r2
8004c90: b2d2 uxtb r2, r2
8004c92: 40d3 lsrs r3, r2
8004c94: 4a04 ldr r2, [pc, #16] @ (8004ca8 <HAL_RCC_GetPCLK1Freq+0x40>)
8004c96: 5cd3 ldrb r3, [r2, r3]
8004c98: fa21 f303 lsr.w r3, r1, r3
}
8004c9c: 4618 mov r0, r3
8004c9e: 3708 adds r7, #8
8004ca0: 46bd mov sp, r7
8004ca2: bd80 pop {r7, pc}
8004ca4: 40021000 .word 0x40021000
8004ca8: 08005e7c .word 0x08005e7c
08004cac <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8004cac: b580 push {r7, lr}
8004cae: b082 sub sp, #8
8004cb0: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
8004cb2: f7ff ffcd bl 8004c50 <HAL_RCC_GetHCLKFreq>
8004cb6: 4601 mov r1, r0
8004cb8: 4b0b ldr r3, [pc, #44] @ (8004ce8 <HAL_RCC_GetPCLK2Freq+0x3c>)
8004cba: 685b ldr r3, [r3, #4]
8004cbc: f403 5360 and.w r3, r3, #14336 @ 0x3800
8004cc0: f44f 5260 mov.w r2, #14336 @ 0x3800
8004cc4: 607a str r2, [r7, #4]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004cc6: 687a ldr r2, [r7, #4]
8004cc8: fa92 f2a2 rbit r2, r2
8004ccc: 603a str r2, [r7, #0]
return result;
8004cce: 683a ldr r2, [r7, #0]
8004cd0: fab2 f282 clz r2, r2
8004cd4: b2d2 uxtb r2, r2
8004cd6: 40d3 lsrs r3, r2
8004cd8: 4a04 ldr r2, [pc, #16] @ (8004cec <HAL_RCC_GetPCLK2Freq+0x40>)
8004cda: 5cd3 ldrb r3, [r2, r3]
8004cdc: fa21 f303 lsr.w r3, r1, r3
}
8004ce0: 4618 mov r0, r3
8004ce2: 3708 adds r7, #8
8004ce4: 46bd mov sp, r7
8004ce6: bd80 pop {r7, pc}
8004ce8: 40021000 .word 0x40021000
8004cec: 08005e7c .word 0x08005e7c
08004cf0 <HAL_RCCEx_PeriphCLKConfig>:
* When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8004cf0: b580 push {r7, lr}
8004cf2: b092 sub sp, #72 @ 0x48
8004cf4: af00 add r7, sp, #0
8004cf6: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8004cf8: 2300 movs r3, #0
8004cfa: 643b str r3, [r7, #64] @ 0x40
uint32_t temp_reg = 0U;
8004cfc: 2300 movs r3, #0
8004cfe: 63fb str r3, [r7, #60] @ 0x3c
FlagStatus pwrclkchanged = RESET;
8004d00: 2300 movs r3, #0
8004d02: f887 3047 strb.w r3, [r7, #71] @ 0x47
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*---------------------------- RTC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8004d06: 687b ldr r3, [r7, #4]
8004d08: 681b ldr r3, [r3, #0]
8004d0a: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004d0e: 2b00 cmp r3, #0
8004d10: f000 80d4 beq.w 8004ebc <HAL_RCCEx_PeriphCLKConfig+0x1cc>
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8004d14: 4b4e ldr r3, [pc, #312] @ (8004e50 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004d16: 69db ldr r3, [r3, #28]
8004d18: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004d1c: 2b00 cmp r3, #0
8004d1e: d10e bne.n 8004d3e <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004d20: 4b4b ldr r3, [pc, #300] @ (8004e50 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004d22: 69db ldr r3, [r3, #28]
8004d24: 4a4a ldr r2, [pc, #296] @ (8004e50 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004d26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004d2a: 61d3 str r3, [r2, #28]
8004d2c: 4b48 ldr r3, [pc, #288] @ (8004e50 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004d2e: 69db ldr r3, [r3, #28]
8004d30: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004d34: 60bb str r3, [r7, #8]
8004d36: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8004d38: 2301 movs r3, #1
8004d3a: f887 3047 strb.w r3, [r7, #71] @ 0x47
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004d3e: 4b45 ldr r3, [pc, #276] @ (8004e54 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8004d40: 681b ldr r3, [r3, #0]
8004d42: f403 7380 and.w r3, r3, #256 @ 0x100
8004d46: 2b00 cmp r3, #0
8004d48: d118 bne.n 8004d7c <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8004d4a: 4b42 ldr r3, [pc, #264] @ (8004e54 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8004d4c: 681b ldr r3, [r3, #0]
8004d4e: 4a41 ldr r2, [pc, #260] @ (8004e54 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8004d50: f443 7380 orr.w r3, r3, #256 @ 0x100
8004d54: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8004d56: f7fc fb4f bl 80013f8 <HAL_GetTick>
8004d5a: 6438 str r0, [r7, #64] @ 0x40
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004d5c: e008 b.n 8004d70 <HAL_RCCEx_PeriphCLKConfig+0x80>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004d5e: f7fc fb4b bl 80013f8 <HAL_GetTick>
8004d62: 4602 mov r2, r0
8004d64: 6c3b ldr r3, [r7, #64] @ 0x40
8004d66: 1ad3 subs r3, r2, r3
8004d68: 2b64 cmp r3, #100 @ 0x64
8004d6a: d901 bls.n 8004d70 <HAL_RCCEx_PeriphCLKConfig+0x80>
{
return HAL_TIMEOUT;
8004d6c: 2303 movs r3, #3
8004d6e: e14b b.n 8005008 <HAL_RCCEx_PeriphCLKConfig+0x318>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8004d70: 4b38 ldr r3, [pc, #224] @ (8004e54 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8004d72: 681b ldr r3, [r3, #0]
8004d74: f403 7380 and.w r3, r3, #256 @ 0x100
8004d78: 2b00 cmp r3, #0
8004d7a: d0f0 beq.n 8004d5e <HAL_RCCEx_PeriphCLKConfig+0x6e>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8004d7c: 4b34 ldr r3, [pc, #208] @ (8004e50 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004d7e: 6a1b ldr r3, [r3, #32]
8004d80: f403 7340 and.w r3, r3, #768 @ 0x300
8004d84: 63fb str r3, [r7, #60] @ 0x3c
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8004d86: 6bfb ldr r3, [r7, #60] @ 0x3c
8004d88: 2b00 cmp r3, #0
8004d8a: f000 8084 beq.w 8004e96 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
8004d8e: 687b ldr r3, [r7, #4]
8004d90: 685b ldr r3, [r3, #4]
8004d92: f403 7340 and.w r3, r3, #768 @ 0x300
8004d96: 6bfa ldr r2, [r7, #60] @ 0x3c
8004d98: 429a cmp r2, r3
8004d9a: d07c beq.n 8004e96 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8004d9c: 4b2c ldr r3, [pc, #176] @ (8004e50 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004d9e: 6a1b ldr r3, [r3, #32]
8004da0: f423 7340 bic.w r3, r3, #768 @ 0x300
8004da4: 63fb str r3, [r7, #60] @ 0x3c
8004da6: f44f 3380 mov.w r3, #65536 @ 0x10000
8004daa: 633b str r3, [r7, #48] @ 0x30
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004dac: 6b3b ldr r3, [r7, #48] @ 0x30
8004dae: fa93 f3a3 rbit r3, r3
8004db2: 62fb str r3, [r7, #44] @ 0x2c
return result;
8004db4: 6afb ldr r3, [r7, #44] @ 0x2c
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8004db6: fab3 f383 clz r3, r3
8004dba: b2db uxtb r3, r3
8004dbc: 461a mov r2, r3
8004dbe: 4b26 ldr r3, [pc, #152] @ (8004e58 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8004dc0: 4413 add r3, r2
8004dc2: 009b lsls r3, r3, #2
8004dc4: 461a mov r2, r3
8004dc6: 2301 movs r3, #1
8004dc8: 6013 str r3, [r2, #0]
8004dca: f44f 3380 mov.w r3, #65536 @ 0x10000
8004dce: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004dd0: 6bbb ldr r3, [r7, #56] @ 0x38
8004dd2: fa93 f3a3 rbit r3, r3
8004dd6: 637b str r3, [r7, #52] @ 0x34
return result;
8004dd8: 6b7b ldr r3, [r7, #52] @ 0x34
__HAL_RCC_BACKUPRESET_RELEASE();
8004dda: fab3 f383 clz r3, r3
8004dde: b2db uxtb r3, r3
8004de0: 461a mov r2, r3
8004de2: 4b1d ldr r3, [pc, #116] @ (8004e58 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8004de4: 4413 add r3, r2
8004de6: 009b lsls r3, r3, #2
8004de8: 461a mov r2, r3
8004dea: 2300 movs r3, #0
8004dec: 6013 str r3, [r2, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8004dee: 4a18 ldr r2, [pc, #96] @ (8004e50 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004df0: 6bfb ldr r3, [r7, #60] @ 0x3c
8004df2: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8004df4: 6bfb ldr r3, [r7, #60] @ 0x3c
8004df6: f003 0301 and.w r3, r3, #1
8004dfa: 2b00 cmp r3, #0
8004dfc: d04b beq.n 8004e96 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004dfe: f7fc fafb bl 80013f8 <HAL_GetTick>
8004e02: 6438 str r0, [r7, #64] @ 0x40
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004e04: e00a b.n 8004e1c <HAL_RCCEx_PeriphCLKConfig+0x12c>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004e06: f7fc faf7 bl 80013f8 <HAL_GetTick>
8004e0a: 4602 mov r2, r0
8004e0c: 6c3b ldr r3, [r7, #64] @ 0x40
8004e0e: 1ad3 subs r3, r2, r3
8004e10: f241 3288 movw r2, #5000 @ 0x1388
8004e14: 4293 cmp r3, r2
8004e16: d901 bls.n 8004e1c <HAL_RCCEx_PeriphCLKConfig+0x12c>
{
return HAL_TIMEOUT;
8004e18: 2303 movs r3, #3
8004e1a: e0f5 b.n 8005008 <HAL_RCCEx_PeriphCLKConfig+0x318>
8004e1c: 2302 movs r3, #2
8004e1e: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004e20: 6abb ldr r3, [r7, #40] @ 0x28
8004e22: fa93 f3a3 rbit r3, r3
8004e26: 627b str r3, [r7, #36] @ 0x24
8004e28: 2302 movs r3, #2
8004e2a: 623b str r3, [r7, #32]
8004e2c: 6a3b ldr r3, [r7, #32]
8004e2e: fa93 f3a3 rbit r3, r3
8004e32: 61fb str r3, [r7, #28]
return result;
8004e34: 69fb ldr r3, [r7, #28]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004e36: fab3 f383 clz r3, r3
8004e3a: b2db uxtb r3, r3
8004e3c: 095b lsrs r3, r3, #5
8004e3e: b2db uxtb r3, r3
8004e40: f043 0302 orr.w r3, r3, #2
8004e44: b2db uxtb r3, r3
8004e46: 2b02 cmp r3, #2
8004e48: d108 bne.n 8004e5c <HAL_RCCEx_PeriphCLKConfig+0x16c>
8004e4a: 4b01 ldr r3, [pc, #4] @ (8004e50 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8004e4c: 6a1b ldr r3, [r3, #32]
8004e4e: e00d b.n 8004e6c <HAL_RCCEx_PeriphCLKConfig+0x17c>
8004e50: 40021000 .word 0x40021000
8004e54: 40007000 .word 0x40007000
8004e58: 10908100 .word 0x10908100
8004e5c: 2302 movs r3, #2
8004e5e: 61bb str r3, [r7, #24]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8004e60: 69bb ldr r3, [r7, #24]
8004e62: fa93 f3a3 rbit r3, r3
8004e66: 617b str r3, [r7, #20]
8004e68: 4b69 ldr r3, [pc, #420] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004e6a: 6a5b ldr r3, [r3, #36] @ 0x24
8004e6c: 2202 movs r2, #2
8004e6e: 613a str r2, [r7, #16]
8004e70: 693a ldr r2, [r7, #16]
8004e72: fa92 f2a2 rbit r2, r2
8004e76: 60fa str r2, [r7, #12]
return result;
8004e78: 68fa ldr r2, [r7, #12]
8004e7a: fab2 f282 clz r2, r2
8004e7e: b2d2 uxtb r2, r2
8004e80: f042 0240 orr.w r2, r2, #64 @ 0x40
8004e84: b2d2 uxtb r2, r2
8004e86: f002 021f and.w r2, r2, #31
8004e8a: 2101 movs r1, #1
8004e8c: fa01 f202 lsl.w r2, r1, r2
8004e90: 4013 ands r3, r2
8004e92: 2b00 cmp r3, #0
8004e94: d0b7 beq.n 8004e06 <HAL_RCCEx_PeriphCLKConfig+0x116>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8004e96: 4b5e ldr r3, [pc, #376] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004e98: 6a1b ldr r3, [r3, #32]
8004e9a: f423 7240 bic.w r2, r3, #768 @ 0x300
8004e9e: 687b ldr r3, [r7, #4]
8004ea0: 685b ldr r3, [r3, #4]
8004ea2: 495b ldr r1, [pc, #364] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004ea4: 4313 orrs r3, r2
8004ea6: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8004ea8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
8004eac: 2b01 cmp r3, #1
8004eae: d105 bne.n 8004ebc <HAL_RCCEx_PeriphCLKConfig+0x1cc>
{
__HAL_RCC_PWR_CLK_DISABLE();
8004eb0: 4b57 ldr r3, [pc, #348] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004eb2: 69db ldr r3, [r3, #28]
8004eb4: 4a56 ldr r2, [pc, #344] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004eb6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8004eba: 61d3 str r3, [r2, #28]
}
}
/*------------------------------- USART1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8004ebc: 687b ldr r3, [r7, #4]
8004ebe: 681b ldr r3, [r3, #0]
8004ec0: f003 0301 and.w r3, r3, #1
8004ec4: 2b00 cmp r3, #0
8004ec6: d008 beq.n 8004eda <HAL_RCCEx_PeriphCLKConfig+0x1ea>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8004ec8: 4b51 ldr r3, [pc, #324] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004eca: 6b1b ldr r3, [r3, #48] @ 0x30
8004ecc: f023 0203 bic.w r2, r3, #3
8004ed0: 687b ldr r3, [r7, #4]
8004ed2: 689b ldr r3, [r3, #8]
8004ed4: 494e ldr r1, [pc, #312] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004ed6: 4313 orrs r3, r2
8004ed8: 630b str r3, [r1, #48] @ 0x30
}
#if defined(RCC_CFGR3_USART2SW)
/*----------------------------- USART2 Configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8004eda: 687b ldr r3, [r7, #4]
8004edc: 681b ldr r3, [r3, #0]
8004ede: f003 0302 and.w r3, r3, #2
8004ee2: 2b00 cmp r3, #0
8004ee4: d008 beq.n 8004ef8 <HAL_RCCEx_PeriphCLKConfig+0x208>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8004ee6: 4b4a ldr r3, [pc, #296] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004ee8: 6b1b ldr r3, [r3, #48] @ 0x30
8004eea: f423 3240 bic.w r2, r3, #196608 @ 0x30000
8004eee: 687b ldr r3, [r7, #4]
8004ef0: 68db ldr r3, [r3, #12]
8004ef2: 4947 ldr r1, [pc, #284] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004ef4: 4313 orrs r3, r2
8004ef6: 630b str r3, [r1, #48] @ 0x30
}
#endif /* RCC_CFGR3_USART2SW */
#if defined(RCC_CFGR3_USART3SW)
/*------------------------------ USART3 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8004ef8: 687b ldr r3, [r7, #4]
8004efa: 681b ldr r3, [r3, #0]
8004efc: f003 0304 and.w r3, r3, #4
8004f00: 2b00 cmp r3, #0
8004f02: d008 beq.n 8004f16 <HAL_RCCEx_PeriphCLKConfig+0x226>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8004f04: 4b42 ldr r3, [pc, #264] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f06: 6b1b ldr r3, [r3, #48] @ 0x30
8004f08: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
8004f0c: 687b ldr r3, [r7, #4]
8004f0e: 691b ldr r3, [r3, #16]
8004f10: 493f ldr r1, [pc, #252] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f12: 4313 orrs r3, r2
8004f14: 630b str r3, [r1, #48] @ 0x30
}
#endif /* RCC_CFGR3_USART3SW */
/*------------------------------ I2C1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8004f16: 687b ldr r3, [r7, #4]
8004f18: 681b ldr r3, [r3, #0]
8004f1a: f003 0320 and.w r3, r3, #32
8004f1e: 2b00 cmp r3, #0
8004f20: d008 beq.n 8004f34 <HAL_RCCEx_PeriphCLKConfig+0x244>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8004f22: 4b3b ldr r3, [pc, #236] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f24: 6b1b ldr r3, [r3, #48] @ 0x30
8004f26: f023 0210 bic.w r2, r3, #16
8004f2a: 687b ldr r3, [r7, #4]
8004f2c: 69db ldr r3, [r3, #28]
8004f2e: 4938 ldr r1, [pc, #224] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f30: 4313 orrs r3, r2
8004f32: 630b str r3, [r1, #48] @ 0x30
#if defined(STM32F302xE) || defined(STM32F303xE)\
|| defined(STM32F302xC) || defined(STM32F303xC)\
|| defined(STM32F302x8) \
|| defined(STM32F373xC)
/*------------------------------ USB Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8004f34: 687b ldr r3, [r7, #4]
8004f36: 681b ldr r3, [r3, #0]
8004f38: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004f3c: 2b00 cmp r3, #0
8004f3e: d008 beq.n 8004f52 <HAL_RCCEx_PeriphCLKConfig+0x262>
{
/* Check the parameters */
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
8004f40: 4b33 ldr r3, [pc, #204] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f42: 685b ldr r3, [r3, #4]
8004f44: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
8004f48: 687b ldr r3, [r7, #4]
8004f4a: 6b1b ldr r3, [r3, #48] @ 0x30
8004f4c: 4930 ldr r1, [pc, #192] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f4e: 4313 orrs r3, r2
8004f50: 604b str r3, [r1, #4]
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
|| defined(STM32F373xC) || defined(STM32F378xx)
/*------------------------------ I2C2 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8004f52: 687b ldr r3, [r7, #4]
8004f54: 681b ldr r3, [r3, #0]
8004f56: f003 0340 and.w r3, r3, #64 @ 0x40
8004f5a: 2b00 cmp r3, #0
8004f5c: d008 beq.n 8004f70 <HAL_RCCEx_PeriphCLKConfig+0x280>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8004f5e: 4b2c ldr r3, [pc, #176] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f60: 6b1b ldr r3, [r3, #48] @ 0x30
8004f62: f023 0220 bic.w r2, r3, #32
8004f66: 687b ldr r3, [r7, #4]
8004f68: 6a1b ldr r3, [r3, #32]
8004f6a: 4929 ldr r1, [pc, #164] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f6c: 4313 orrs r3, r2
8004f6e: 630b str r3, [r1, #48] @ 0x30
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
/*------------------------------ UART4 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8004f70: 687b ldr r3, [r7, #4]
8004f72: 681b ldr r3, [r3, #0]
8004f74: f003 0308 and.w r3, r3, #8
8004f78: 2b00 cmp r3, #0
8004f7a: d008 beq.n 8004f8e <HAL_RCCEx_PeriphCLKConfig+0x29e>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8004f7c: 4b24 ldr r3, [pc, #144] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f7e: 6b1b ldr r3, [r3, #48] @ 0x30
8004f80: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8004f84: 687b ldr r3, [r7, #4]
8004f86: 695b ldr r3, [r3, #20]
8004f88: 4921 ldr r1, [pc, #132] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f8a: 4313 orrs r3, r2
8004f8c: 630b str r3, [r1, #48] @ 0x30
}
/*------------------------------ UART5 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8004f8e: 687b ldr r3, [r7, #4]
8004f90: 681b ldr r3, [r3, #0]
8004f92: f003 0310 and.w r3, r3, #16
8004f96: 2b00 cmp r3, #0
8004f98: d008 beq.n 8004fac <HAL_RCCEx_PeriphCLKConfig+0x2bc>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
8004f9a: 4b1d ldr r3, [pc, #116] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004f9c: 6b1b ldr r3, [r3, #48] @ 0x30
8004f9e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8004fa2: 687b ldr r3, [r7, #4]
8004fa4: 699b ldr r3, [r3, #24]
8004fa6: 491a ldr r1, [pc, #104] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004fa8: 4313 orrs r3, r2
8004faa: 630b str r3, [r1, #48] @ 0x30
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/*------------------------------ I2S Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
8004fac: 687b ldr r3, [r7, #4]
8004fae: 681b ldr r3, [r3, #0]
8004fb0: f403 7300 and.w r3, r3, #512 @ 0x200
8004fb4: 2b00 cmp r3, #0
8004fb6: d008 beq.n 8004fca <HAL_RCCEx_PeriphCLKConfig+0x2da>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8004fb8: 4b15 ldr r3, [pc, #84] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004fba: 685b ldr r3, [r3, #4]
8004fbc: f423 0200 bic.w r2, r3, #8388608 @ 0x800000
8004fc0: 687b ldr r3, [r7, #4]
8004fc2: 6a9b ldr r3, [r3, #40] @ 0x28
8004fc4: 4912 ldr r1, [pc, #72] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004fc6: 4313 orrs r3, r2
8004fc8: 604b str r3, [r1, #4]
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
/*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
8004fca: 687b ldr r3, [r7, #4]
8004fcc: 681b ldr r3, [r3, #0]
8004fce: f003 0380 and.w r3, r3, #128 @ 0x80
8004fd2: 2b00 cmp r3, #0
8004fd4: d008 beq.n 8004fe8 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
{
/* Check the parameters */
assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
/* Configure the ADC12 clock source */
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
8004fd6: 4b0e ldr r3, [pc, #56] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004fd8: 6adb ldr r3, [r3, #44] @ 0x2c
8004fda: f423 72f8 bic.w r2, r3, #496 @ 0x1f0
8004fde: 687b ldr r3, [r7, #4]
8004fe0: 6a5b ldr r3, [r3, #36] @ 0x24
8004fe2: 490b ldr r1, [pc, #44] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004fe4: 4313 orrs r3, r2
8004fe6: 62cb str r3, [r1, #44] @ 0x2c
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/*------------------------------ TIM1 clock Configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
8004fe8: 687b ldr r3, [r7, #4]
8004fea: 681b ldr r3, [r3, #0]
8004fec: f403 5380 and.w r3, r3, #4096 @ 0x1000
8004ff0: 2b00 cmp r3, #0
8004ff2: d008 beq.n 8005006 <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
/* Configure the TIM1 clock source */
__HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
8004ff4: 4b06 ldr r3, [pc, #24] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8004ff6: 6b1b ldr r3, [r3, #48] @ 0x30
8004ff8: f423 7280 bic.w r2, r3, #256 @ 0x100
8004ffc: 687b ldr r3, [r7, #4]
8004ffe: 6adb ldr r3, [r3, #44] @ 0x2c
8005000: 4903 ldr r1, [pc, #12] @ (8005010 <HAL_RCCEx_PeriphCLKConfig+0x320>)
8005002: 4313 orrs r3, r2
8005004: 630b str r3, [r1, #48] @ 0x30
__HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
}
#endif /* STM32F303xE || STM32F398xx */
return HAL_OK;
8005006: 2300 movs r3, #0
}
8005008: 4618 mov r0, r3
800500a: 3748 adds r7, #72 @ 0x48
800500c: 46bd mov sp, r7
800500e: bd80 pop {r7, pc}
8005010: 40021000 .word 0x40021000
08005014 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8005014: b580 push {r7, lr}
8005016: b082 sub sp, #8
8005018: af00 add r7, sp, #0
800501a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800501c: 687b ldr r3, [r7, #4]
800501e: 2b00 cmp r3, #0
8005020: d101 bne.n 8005026 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8005022: 2301 movs r3, #1
8005024: e049 b.n 80050ba <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8005026: 687b ldr r3, [r7, #4]
8005028: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
800502c: b2db uxtb r3, r3
800502e: 2b00 cmp r3, #0
8005030: d106 bne.n 8005040 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8005032: 687b ldr r3, [r7, #4]
8005034: 2200 movs r2, #0
8005036: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
800503a: 6878 ldr r0, [r7, #4]
800503c: f7fc f86c bl 8001118 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8005040: 687b ldr r3, [r7, #4]
8005042: 2202 movs r2, #2
8005044: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8005048: 687b ldr r3, [r7, #4]
800504a: 681a ldr r2, [r3, #0]
800504c: 687b ldr r3, [r7, #4]
800504e: 3304 adds r3, #4
8005050: 4619 mov r1, r3
8005052: 4610 mov r0, r2
8005054: f000 f986 bl 8005364 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8005058: 687b ldr r3, [r7, #4]
800505a: 2201 movs r2, #1
800505c: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005060: 687b ldr r3, [r7, #4]
8005062: 2201 movs r2, #1
8005064: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005068: 687b ldr r3, [r7, #4]
800506a: 2201 movs r2, #1
800506c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005070: 687b ldr r3, [r7, #4]
8005072: 2201 movs r2, #1
8005074: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005078: 687b ldr r3, [r7, #4]
800507a: 2201 movs r2, #1
800507c: f883 2041 strb.w r2, [r3, #65] @ 0x41
8005080: 687b ldr r3, [r7, #4]
8005082: 2201 movs r2, #1
8005084: f883 2042 strb.w r2, [r3, #66] @ 0x42
8005088: 687b ldr r3, [r7, #4]
800508a: 2201 movs r2, #1
800508c: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8005090: 687b ldr r3, [r7, #4]
8005092: 2201 movs r2, #1
8005094: f883 2044 strb.w r2, [r3, #68] @ 0x44
8005098: 687b ldr r3, [r7, #4]
800509a: 2201 movs r2, #1
800509c: f883 2045 strb.w r2, [r3, #69] @ 0x45
80050a0: 687b ldr r3, [r7, #4]
80050a2: 2201 movs r2, #1
80050a4: f883 2046 strb.w r2, [r3, #70] @ 0x46
80050a8: 687b ldr r3, [r7, #4]
80050aa: 2201 movs r2, #1
80050ac: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80050b0: 687b ldr r3, [r7, #4]
80050b2: 2201 movs r2, #1
80050b4: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
80050b8: 2300 movs r3, #0
}
80050ba: 4618 mov r0, r3
80050bc: 3708 adds r7, #8
80050be: 46bd mov sp, r7
80050c0: bd80 pop {r7, pc}
080050c2 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
80050c2: b580 push {r7, lr}
80050c4: b082 sub sp, #8
80050c6: af00 add r7, sp, #0
80050c8: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
80050ca: 687b ldr r3, [r7, #4]
80050cc: 681b ldr r3, [r3, #0]
80050ce: 691b ldr r3, [r3, #16]
80050d0: f003 0302 and.w r3, r3, #2
80050d4: 2b02 cmp r3, #2
80050d6: d122 bne.n 800511e <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
80050d8: 687b ldr r3, [r7, #4]
80050da: 681b ldr r3, [r3, #0]
80050dc: 68db ldr r3, [r3, #12]
80050de: f003 0302 and.w r3, r3, #2
80050e2: 2b02 cmp r3, #2
80050e4: d11b bne.n 800511e <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
80050e6: 687b ldr r3, [r7, #4]
80050e8: 681b ldr r3, [r3, #0]
80050ea: f06f 0202 mvn.w r2, #2
80050ee: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
80050f0: 687b ldr r3, [r7, #4]
80050f2: 2201 movs r2, #1
80050f4: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
80050f6: 687b ldr r3, [r7, #4]
80050f8: 681b ldr r3, [r3, #0]
80050fa: 699b ldr r3, [r3, #24]
80050fc: f003 0303 and.w r3, r3, #3
8005100: 2b00 cmp r3, #0
8005102: d003 beq.n 800510c <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005104: 6878 ldr r0, [r7, #4]
8005106: f000 f90f bl 8005328 <HAL_TIM_IC_CaptureCallback>
800510a: e005 b.n 8005118 <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800510c: 6878 ldr r0, [r7, #4]
800510e: f000 f901 bl 8005314 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005112: 6878 ldr r0, [r7, #4]
8005114: f000 f912 bl 800533c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8005118: 687b ldr r3, [r7, #4]
800511a: 2200 movs r2, #0
800511c: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
800511e: 687b ldr r3, [r7, #4]
8005120: 681b ldr r3, [r3, #0]
8005122: 691b ldr r3, [r3, #16]
8005124: f003 0304 and.w r3, r3, #4
8005128: 2b04 cmp r3, #4
800512a: d122 bne.n 8005172 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
800512c: 687b ldr r3, [r7, #4]
800512e: 681b ldr r3, [r3, #0]
8005130: 68db ldr r3, [r3, #12]
8005132: f003 0304 and.w r3, r3, #4
8005136: 2b04 cmp r3, #4
8005138: d11b bne.n 8005172 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
800513a: 687b ldr r3, [r7, #4]
800513c: 681b ldr r3, [r3, #0]
800513e: f06f 0204 mvn.w r2, #4
8005142: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8005144: 687b ldr r3, [r7, #4]
8005146: 2202 movs r2, #2
8005148: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
800514a: 687b ldr r3, [r7, #4]
800514c: 681b ldr r3, [r3, #0]
800514e: 699b ldr r3, [r3, #24]
8005150: f403 7340 and.w r3, r3, #768 @ 0x300
8005154: 2b00 cmp r3, #0
8005156: d003 beq.n 8005160 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005158: 6878 ldr r0, [r7, #4]
800515a: f000 f8e5 bl 8005328 <HAL_TIM_IC_CaptureCallback>
800515e: e005 b.n 800516c <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005160: 6878 ldr r0, [r7, #4]
8005162: f000 f8d7 bl 8005314 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005166: 6878 ldr r0, [r7, #4]
8005168: f000 f8e8 bl 800533c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800516c: 687b ldr r3, [r7, #4]
800516e: 2200 movs r2, #0
8005170: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8005172: 687b ldr r3, [r7, #4]
8005174: 681b ldr r3, [r3, #0]
8005176: 691b ldr r3, [r3, #16]
8005178: f003 0308 and.w r3, r3, #8
800517c: 2b08 cmp r3, #8
800517e: d122 bne.n 80051c6 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8005180: 687b ldr r3, [r7, #4]
8005182: 681b ldr r3, [r3, #0]
8005184: 68db ldr r3, [r3, #12]
8005186: f003 0308 and.w r3, r3, #8
800518a: 2b08 cmp r3, #8
800518c: d11b bne.n 80051c6 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
800518e: 687b ldr r3, [r7, #4]
8005190: 681b ldr r3, [r3, #0]
8005192: f06f 0208 mvn.w r2, #8
8005196: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8005198: 687b ldr r3, [r7, #4]
800519a: 2204 movs r2, #4
800519c: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
800519e: 687b ldr r3, [r7, #4]
80051a0: 681b ldr r3, [r3, #0]
80051a2: 69db ldr r3, [r3, #28]
80051a4: f003 0303 and.w r3, r3, #3
80051a8: 2b00 cmp r3, #0
80051aa: d003 beq.n 80051b4 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80051ac: 6878 ldr r0, [r7, #4]
80051ae: f000 f8bb bl 8005328 <HAL_TIM_IC_CaptureCallback>
80051b2: e005 b.n 80051c0 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80051b4: 6878 ldr r0, [r7, #4]
80051b6: f000 f8ad bl 8005314 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80051ba: 6878 ldr r0, [r7, #4]
80051bc: f000 f8be bl 800533c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80051c0: 687b ldr r3, [r7, #4]
80051c2: 2200 movs r2, #0
80051c4: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
80051c6: 687b ldr r3, [r7, #4]
80051c8: 681b ldr r3, [r3, #0]
80051ca: 691b ldr r3, [r3, #16]
80051cc: f003 0310 and.w r3, r3, #16
80051d0: 2b10 cmp r3, #16
80051d2: d122 bne.n 800521a <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
80051d4: 687b ldr r3, [r7, #4]
80051d6: 681b ldr r3, [r3, #0]
80051d8: 68db ldr r3, [r3, #12]
80051da: f003 0310 and.w r3, r3, #16
80051de: 2b10 cmp r3, #16
80051e0: d11b bne.n 800521a <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
80051e2: 687b ldr r3, [r7, #4]
80051e4: 681b ldr r3, [r3, #0]
80051e6: f06f 0210 mvn.w r2, #16
80051ea: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
80051ec: 687b ldr r3, [r7, #4]
80051ee: 2208 movs r2, #8
80051f0: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
80051f2: 687b ldr r3, [r7, #4]
80051f4: 681b ldr r3, [r3, #0]
80051f6: 69db ldr r3, [r3, #28]
80051f8: f403 7340 and.w r3, r3, #768 @ 0x300
80051fc: 2b00 cmp r3, #0
80051fe: d003 beq.n 8005208 <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005200: 6878 ldr r0, [r7, #4]
8005202: f000 f891 bl 8005328 <HAL_TIM_IC_CaptureCallback>
8005206: e005 b.n 8005214 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005208: 6878 ldr r0, [r7, #4]
800520a: f000 f883 bl 8005314 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800520e: 6878 ldr r0, [r7, #4]
8005210: f000 f894 bl 800533c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8005214: 687b ldr r3, [r7, #4]
8005216: 2200 movs r2, #0
8005218: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
800521a: 687b ldr r3, [r7, #4]
800521c: 681b ldr r3, [r3, #0]
800521e: 691b ldr r3, [r3, #16]
8005220: f003 0301 and.w r3, r3, #1
8005224: 2b01 cmp r3, #1
8005226: d10e bne.n 8005246 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8005228: 687b ldr r3, [r7, #4]
800522a: 681b ldr r3, [r3, #0]
800522c: 68db ldr r3, [r3, #12]
800522e: f003 0301 and.w r3, r3, #1
8005232: 2b01 cmp r3, #1
8005234: d107 bne.n 8005246 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8005236: 687b ldr r3, [r7, #4]
8005238: 681b ldr r3, [r3, #0]
800523a: f06f 0201 mvn.w r2, #1
800523e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8005240: 6878 ldr r0, [r7, #4]
8005242: f000 f85d bl 8005300 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8005246: 687b ldr r3, [r7, #4]
8005248: 681b ldr r3, [r3, #0]
800524a: 691b ldr r3, [r3, #16]
800524c: f003 0380 and.w r3, r3, #128 @ 0x80
8005250: 2b80 cmp r3, #128 @ 0x80
8005252: d10e bne.n 8005272 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8005254: 687b ldr r3, [r7, #4]
8005256: 681b ldr r3, [r3, #0]
8005258: 68db ldr r3, [r3, #12]
800525a: f003 0380 and.w r3, r3, #128 @ 0x80
800525e: 2b80 cmp r3, #128 @ 0x80
8005260: d107 bne.n 8005272 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8005262: 687b ldr r3, [r7, #4]
8005264: 681b ldr r3, [r3, #0]
8005266: f06f 0280 mvn.w r2, #128 @ 0x80
800526a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
800526c: 6878 ldr r0, [r7, #4]
800526e: f000 f979 bl 8005564 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
#if defined(TIM_BDTR_BK2E)
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
8005272: 687b ldr r3, [r7, #4]
8005274: 681b ldr r3, [r3, #0]
8005276: 691b ldr r3, [r3, #16]
8005278: f403 7380 and.w r3, r3, #256 @ 0x100
800527c: f5b3 7f80 cmp.w r3, #256 @ 0x100
8005280: d10e bne.n 80052a0 <HAL_TIM_IRQHandler+0x1de>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8005282: 687b ldr r3, [r7, #4]
8005284: 681b ldr r3, [r3, #0]
8005286: 68db ldr r3, [r3, #12]
8005288: f003 0380 and.w r3, r3, #128 @ 0x80
800528c: 2b80 cmp r3, #128 @ 0x80
800528e: d107 bne.n 80052a0 <HAL_TIM_IRQHandler+0x1de>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8005290: 687b ldr r3, [r7, #4]
8005292: 681b ldr r3, [r3, #0]
8005294: f46f 7280 mvn.w r2, #256 @ 0x100
8005298: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
800529a: 6878 ldr r0, [r7, #4]
800529c: f000 f96c bl 8005578 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
#endif /* TIM_BDTR_BK2E */
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
80052a0: 687b ldr r3, [r7, #4]
80052a2: 681b ldr r3, [r3, #0]
80052a4: 691b ldr r3, [r3, #16]
80052a6: f003 0340 and.w r3, r3, #64 @ 0x40
80052aa: 2b40 cmp r3, #64 @ 0x40
80052ac: d10e bne.n 80052cc <HAL_TIM_IRQHandler+0x20a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
80052ae: 687b ldr r3, [r7, #4]
80052b0: 681b ldr r3, [r3, #0]
80052b2: 68db ldr r3, [r3, #12]
80052b4: f003 0340 and.w r3, r3, #64 @ 0x40
80052b8: 2b40 cmp r3, #64 @ 0x40
80052ba: d107 bne.n 80052cc <HAL_TIM_IRQHandler+0x20a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
80052bc: 687b ldr r3, [r7, #4]
80052be: 681b ldr r3, [r3, #0]
80052c0: f06f 0240 mvn.w r2, #64 @ 0x40
80052c4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80052c6: 6878 ldr r0, [r7, #4]
80052c8: f000 f842 bl 8005350 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
80052cc: 687b ldr r3, [r7, #4]
80052ce: 681b ldr r3, [r3, #0]
80052d0: 691b ldr r3, [r3, #16]
80052d2: f003 0320 and.w r3, r3, #32
80052d6: 2b20 cmp r3, #32
80052d8: d10e bne.n 80052f8 <HAL_TIM_IRQHandler+0x236>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
80052da: 687b ldr r3, [r7, #4]
80052dc: 681b ldr r3, [r3, #0]
80052de: 68db ldr r3, [r3, #12]
80052e0: f003 0320 and.w r3, r3, #32
80052e4: 2b20 cmp r3, #32
80052e6: d107 bne.n 80052f8 <HAL_TIM_IRQHandler+0x236>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
80052e8: 687b ldr r3, [r7, #4]
80052ea: 681b ldr r3, [r3, #0]
80052ec: f06f 0220 mvn.w r2, #32
80052f0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
80052f2: 6878 ldr r0, [r7, #4]
80052f4: f000 f92c bl 8005550 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
80052f8: bf00 nop
80052fa: 3708 adds r7, #8
80052fc: 46bd mov sp, r7
80052fe: bd80 pop {r7, pc}
08005300 <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8005300: b480 push {r7}
8005302: b083 sub sp, #12
8005304: af00 add r7, sp, #0
8005306: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
8005308: bf00 nop
800530a: 370c adds r7, #12
800530c: 46bd mov sp, r7
800530e: f85d 7b04 ldr.w r7, [sp], #4
8005312: 4770 bx lr
08005314 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8005314: b480 push {r7}
8005316: b083 sub sp, #12
8005318: af00 add r7, sp, #0
800531a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
800531c: bf00 nop
800531e: 370c adds r7, #12
8005320: 46bd mov sp, r7
8005322: f85d 7b04 ldr.w r7, [sp], #4
8005326: 4770 bx lr
08005328 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8005328: b480 push {r7}
800532a: b083 sub sp, #12
800532c: af00 add r7, sp, #0
800532e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8005330: bf00 nop
8005332: 370c adds r7, #12
8005334: 46bd mov sp, r7
8005336: f85d 7b04 ldr.w r7, [sp], #4
800533a: 4770 bx lr
0800533c <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
800533c: b480 push {r7}
800533e: b083 sub sp, #12
8005340: af00 add r7, sp, #0
8005342: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8005344: bf00 nop
8005346: 370c adds r7, #12
8005348: 46bd mov sp, r7
800534a: f85d 7b04 ldr.w r7, [sp], #4
800534e: 4770 bx lr
08005350 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8005350: b480 push {r7}
8005352: b083 sub sp, #12
8005354: af00 add r7, sp, #0
8005356: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8005358: bf00 nop
800535a: 370c adds r7, #12
800535c: 46bd mov sp, r7
800535e: f85d 7b04 ldr.w r7, [sp], #4
8005362: 4770 bx lr
08005364 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8005364: b480 push {r7}
8005366: b085 sub sp, #20
8005368: af00 add r7, sp, #0
800536a: 6078 str r0, [r7, #4]
800536c: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800536e: 687b ldr r3, [r7, #4]
8005370: 681b ldr r3, [r3, #0]
8005372: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8005374: 687b ldr r3, [r7, #4]
8005376: 4a36 ldr r2, [pc, #216] @ (8005450 <TIM_Base_SetConfig+0xec>)
8005378: 4293 cmp r3, r2
800537a: d00b beq.n 8005394 <TIM_Base_SetConfig+0x30>
800537c: 687b ldr r3, [r7, #4]
800537e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005382: d007 beq.n 8005394 <TIM_Base_SetConfig+0x30>
8005384: 687b ldr r3, [r7, #4]
8005386: 4a33 ldr r2, [pc, #204] @ (8005454 <TIM_Base_SetConfig+0xf0>)
8005388: 4293 cmp r3, r2
800538a: d003 beq.n 8005394 <TIM_Base_SetConfig+0x30>
800538c: 687b ldr r3, [r7, #4]
800538e: 4a32 ldr r2, [pc, #200] @ (8005458 <TIM_Base_SetConfig+0xf4>)
8005390: 4293 cmp r3, r2
8005392: d108 bne.n 80053a6 <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8005394: 68fb ldr r3, [r7, #12]
8005396: f023 0370 bic.w r3, r3, #112 @ 0x70
800539a: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
800539c: 683b ldr r3, [r7, #0]
800539e: 685b ldr r3, [r3, #4]
80053a0: 68fa ldr r2, [r7, #12]
80053a2: 4313 orrs r3, r2
80053a4: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80053a6: 687b ldr r3, [r7, #4]
80053a8: 4a29 ldr r2, [pc, #164] @ (8005450 <TIM_Base_SetConfig+0xec>)
80053aa: 4293 cmp r3, r2
80053ac: d017 beq.n 80053de <TIM_Base_SetConfig+0x7a>
80053ae: 687b ldr r3, [r7, #4]
80053b0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80053b4: d013 beq.n 80053de <TIM_Base_SetConfig+0x7a>
80053b6: 687b ldr r3, [r7, #4]
80053b8: 4a26 ldr r2, [pc, #152] @ (8005454 <TIM_Base_SetConfig+0xf0>)
80053ba: 4293 cmp r3, r2
80053bc: d00f beq.n 80053de <TIM_Base_SetConfig+0x7a>
80053be: 687b ldr r3, [r7, #4]
80053c0: 4a25 ldr r2, [pc, #148] @ (8005458 <TIM_Base_SetConfig+0xf4>)
80053c2: 4293 cmp r3, r2
80053c4: d00b beq.n 80053de <TIM_Base_SetConfig+0x7a>
80053c6: 687b ldr r3, [r7, #4]
80053c8: 4a24 ldr r2, [pc, #144] @ (800545c <TIM_Base_SetConfig+0xf8>)
80053ca: 4293 cmp r3, r2
80053cc: d007 beq.n 80053de <TIM_Base_SetConfig+0x7a>
80053ce: 687b ldr r3, [r7, #4]
80053d0: 4a23 ldr r2, [pc, #140] @ (8005460 <TIM_Base_SetConfig+0xfc>)
80053d2: 4293 cmp r3, r2
80053d4: d003 beq.n 80053de <TIM_Base_SetConfig+0x7a>
80053d6: 687b ldr r3, [r7, #4]
80053d8: 4a22 ldr r2, [pc, #136] @ (8005464 <TIM_Base_SetConfig+0x100>)
80053da: 4293 cmp r3, r2
80053dc: d108 bne.n 80053f0 <TIM_Base_SetConfig+0x8c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
80053de: 68fb ldr r3, [r7, #12]
80053e0: f423 7340 bic.w r3, r3, #768 @ 0x300
80053e4: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80053e6: 683b ldr r3, [r7, #0]
80053e8: 68db ldr r3, [r3, #12]
80053ea: 68fa ldr r2, [r7, #12]
80053ec: 4313 orrs r3, r2
80053ee: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80053f0: 68fb ldr r3, [r7, #12]
80053f2: f023 0280 bic.w r2, r3, #128 @ 0x80
80053f6: 683b ldr r3, [r7, #0]
80053f8: 695b ldr r3, [r3, #20]
80053fa: 4313 orrs r3, r2
80053fc: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80053fe: 687b ldr r3, [r7, #4]
8005400: 68fa ldr r2, [r7, #12]
8005402: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8005404: 683b ldr r3, [r7, #0]
8005406: 689a ldr r2, [r3, #8]
8005408: 687b ldr r3, [r7, #4]
800540a: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
800540c: 683b ldr r3, [r7, #0]
800540e: 681a ldr r2, [r3, #0]
8005410: 687b ldr r3, [r7, #4]
8005412: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8005414: 687b ldr r3, [r7, #4]
8005416: 4a0e ldr r2, [pc, #56] @ (8005450 <TIM_Base_SetConfig+0xec>)
8005418: 4293 cmp r3, r2
800541a: d00b beq.n 8005434 <TIM_Base_SetConfig+0xd0>
800541c: 687b ldr r3, [r7, #4]
800541e: 4a0f ldr r2, [pc, #60] @ (800545c <TIM_Base_SetConfig+0xf8>)
8005420: 4293 cmp r3, r2
8005422: d007 beq.n 8005434 <TIM_Base_SetConfig+0xd0>
8005424: 687b ldr r3, [r7, #4]
8005426: 4a0e ldr r2, [pc, #56] @ (8005460 <TIM_Base_SetConfig+0xfc>)
8005428: 4293 cmp r3, r2
800542a: d003 beq.n 8005434 <TIM_Base_SetConfig+0xd0>
800542c: 687b ldr r3, [r7, #4]
800542e: 4a0d ldr r2, [pc, #52] @ (8005464 <TIM_Base_SetConfig+0x100>)
8005430: 4293 cmp r3, r2
8005432: d103 bne.n 800543c <TIM_Base_SetConfig+0xd8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8005434: 683b ldr r3, [r7, #0]
8005436: 691a ldr r2, [r3, #16]
8005438: 687b ldr r3, [r7, #4]
800543a: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800543c: 687b ldr r3, [r7, #4]
800543e: 2201 movs r2, #1
8005440: 615a str r2, [r3, #20]
}
8005442: bf00 nop
8005444: 3714 adds r7, #20
8005446: 46bd mov sp, r7
8005448: f85d 7b04 ldr.w r7, [sp], #4
800544c: 4770 bx lr
800544e: bf00 nop
8005450: 40012c00 .word 0x40012c00
8005454: 40000400 .word 0x40000400
8005458: 40000800 .word 0x40000800
800545c: 40014000 .word 0x40014000
8005460: 40014400 .word 0x40014400
8005464: 40014800 .word 0x40014800
08005468 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8005468: b480 push {r7}
800546a: b085 sub sp, #20
800546c: af00 add r7, sp, #0
800546e: 6078 str r0, [r7, #4]
8005470: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8005472: 687b ldr r3, [r7, #4]
8005474: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005478: 2b01 cmp r3, #1
800547a: d101 bne.n 8005480 <HAL_TIMEx_MasterConfigSynchronization+0x18>
800547c: 2302 movs r3, #2
800547e: e059 b.n 8005534 <HAL_TIMEx_MasterConfigSynchronization+0xcc>
8005480: 687b ldr r3, [r7, #4]
8005482: 2201 movs r2, #1
8005484: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8005488: 687b ldr r3, [r7, #4]
800548a: 2202 movs r2, #2
800548c: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8005490: 687b ldr r3, [r7, #4]
8005492: 681b ldr r3, [r3, #0]
8005494: 685b ldr r3, [r3, #4]
8005496: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8005498: 687b ldr r3, [r7, #4]
800549a: 681b ldr r3, [r3, #0]
800549c: 689b ldr r3, [r3, #8]
800549e: 60bb str r3, [r7, #8]
#if defined(TIM_CR2_MMS2)
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80054a0: 687b ldr r3, [r7, #4]
80054a2: 681b ldr r3, [r3, #0]
80054a4: 4a26 ldr r2, [pc, #152] @ (8005540 <HAL_TIMEx_MasterConfigSynchronization+0xd8>)
80054a6: 4293 cmp r3, r2
80054a8: d108 bne.n 80054bc <HAL_TIMEx_MasterConfigSynchronization+0x54>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
80054aa: 68fb ldr r3, [r7, #12]
80054ac: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
80054b0: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
80054b2: 683b ldr r3, [r7, #0]
80054b4: 685b ldr r3, [r3, #4]
80054b6: 68fa ldr r2, [r7, #12]
80054b8: 4313 orrs r3, r2
80054ba: 60fb str r3, [r7, #12]
}
#endif /* TIM_CR2_MMS2 */
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80054bc: 68fb ldr r3, [r7, #12]
80054be: f023 0370 bic.w r3, r3, #112 @ 0x70
80054c2: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80054c4: 683b ldr r3, [r7, #0]
80054c6: 681b ldr r3, [r3, #0]
80054c8: 68fa ldr r2, [r7, #12]
80054ca: 4313 orrs r3, r2
80054cc: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80054ce: 687b ldr r3, [r7, #4]
80054d0: 681b ldr r3, [r3, #0]
80054d2: 68fa ldr r2, [r7, #12]
80054d4: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80054d6: 687b ldr r3, [r7, #4]
80054d8: 681b ldr r3, [r3, #0]
80054da: 4a19 ldr r2, [pc, #100] @ (8005540 <HAL_TIMEx_MasterConfigSynchronization+0xd8>)
80054dc: 4293 cmp r3, r2
80054de: d013 beq.n 8005508 <HAL_TIMEx_MasterConfigSynchronization+0xa0>
80054e0: 687b ldr r3, [r7, #4]
80054e2: 681b ldr r3, [r3, #0]
80054e4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80054e8: d00e beq.n 8005508 <HAL_TIMEx_MasterConfigSynchronization+0xa0>
80054ea: 687b ldr r3, [r7, #4]
80054ec: 681b ldr r3, [r3, #0]
80054ee: 4a15 ldr r2, [pc, #84] @ (8005544 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
80054f0: 4293 cmp r3, r2
80054f2: d009 beq.n 8005508 <HAL_TIMEx_MasterConfigSynchronization+0xa0>
80054f4: 687b ldr r3, [r7, #4]
80054f6: 681b ldr r3, [r3, #0]
80054f8: 4a13 ldr r2, [pc, #76] @ (8005548 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
80054fa: 4293 cmp r3, r2
80054fc: d004 beq.n 8005508 <HAL_TIMEx_MasterConfigSynchronization+0xa0>
80054fe: 687b ldr r3, [r7, #4]
8005500: 681b ldr r3, [r3, #0]
8005502: 4a12 ldr r2, [pc, #72] @ (800554c <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
8005504: 4293 cmp r3, r2
8005506: d10c bne.n 8005522 <HAL_TIMEx_MasterConfigSynchronization+0xba>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8005508: 68bb ldr r3, [r7, #8]
800550a: f023 0380 bic.w r3, r3, #128 @ 0x80
800550e: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8005510: 683b ldr r3, [r7, #0]
8005512: 689b ldr r3, [r3, #8]
8005514: 68ba ldr r2, [r7, #8]
8005516: 4313 orrs r3, r2
8005518: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800551a: 687b ldr r3, [r7, #4]
800551c: 681b ldr r3, [r3, #0]
800551e: 68ba ldr r2, [r7, #8]
8005520: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8005522: 687b ldr r3, [r7, #4]
8005524: 2201 movs r2, #1
8005526: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
800552a: 687b ldr r3, [r7, #4]
800552c: 2200 movs r2, #0
800552e: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8005532: 2300 movs r3, #0
}
8005534: 4618 mov r0, r3
8005536: 3714 adds r7, #20
8005538: 46bd mov sp, r7
800553a: f85d 7b04 ldr.w r7, [sp], #4
800553e: 4770 bx lr
8005540: 40012c00 .word 0x40012c00
8005544: 40000400 .word 0x40000400
8005548: 40000800 .word 0x40000800
800554c: 40014000 .word 0x40014000
08005550 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8005550: b480 push {r7}
8005552: b083 sub sp, #12
8005554: af00 add r7, sp, #0
8005556: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8005558: bf00 nop
800555a: 370c adds r7, #12
800555c: 46bd mov sp, r7
800555e: f85d 7b04 ldr.w r7, [sp], #4
8005562: 4770 bx lr
08005564 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8005564: b480 push {r7}
8005566: b083 sub sp, #12
8005568: af00 add r7, sp, #0
800556a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
800556c: bf00 nop
800556e: 370c adds r7, #12
8005570: 46bd mov sp, r7
8005572: f85d 7b04 ldr.w r7, [sp], #4
8005576: 4770 bx lr
08005578 <HAL_TIMEx_Break2Callback>:
* @brief Hall Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
8005578: b480 push {r7}
800557a: b083 sub sp, #12
800557c: af00 add r7, sp, #0
800557e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8005580: bf00 nop
8005582: 370c adds r7, #12
8005584: 46bd mov sp, r7
8005586: f85d 7b04 ldr.w r7, [sp], #4
800558a: 4770 bx lr
0800558c <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
800558c: b580 push {r7, lr}
800558e: b082 sub sp, #8
8005590: af00 add r7, sp, #0
8005592: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8005594: 687b ldr r3, [r7, #4]
8005596: 2b00 cmp r3, #0
8005598: d101 bne.n 800559e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800559a: 2301 movs r3, #1
800559c: e040 b.n 8005620 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
800559e: 687b ldr r3, [r7, #4]
80055a0: 6fdb ldr r3, [r3, #124] @ 0x7c
80055a2: 2b00 cmp r3, #0
80055a4: d106 bne.n 80055b4 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80055a6: 687b ldr r3, [r7, #4]
80055a8: 2200 movs r2, #0
80055aa: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80055ae: 6878 ldr r0, [r7, #4]
80055b0: f7fb fdd8 bl 8001164 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80055b4: 687b ldr r3, [r7, #4]
80055b6: 2224 movs r2, #36 @ 0x24
80055b8: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
80055ba: 687b ldr r3, [r7, #4]
80055bc: 681b ldr r3, [r3, #0]
80055be: 681a ldr r2, [r3, #0]
80055c0: 687b ldr r3, [r7, #4]
80055c2: 681b ldr r3, [r3, #0]
80055c4: f022 0201 bic.w r2, r2, #1
80055c8: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
80055ca: 6878 ldr r0, [r7, #4]
80055cc: f000 f82c bl 8005628 <UART_SetConfig>
80055d0: 4603 mov r3, r0
80055d2: 2b01 cmp r3, #1
80055d4: d101 bne.n 80055da <HAL_UART_Init+0x4e>
{
return HAL_ERROR;
80055d6: 2301 movs r3, #1
80055d8: e022 b.n 8005620 <HAL_UART_Init+0x94>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80055da: 687b ldr r3, [r7, #4]
80055dc: 6a5b ldr r3, [r3, #36] @ 0x24
80055de: 2b00 cmp r3, #0
80055e0: d002 beq.n 80055e8 <HAL_UART_Init+0x5c>
{
UART_AdvFeatureConfig(huart);
80055e2: 6878 ldr r0, [r7, #4]
80055e4: f000 f9f4 bl 80059d0 <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80055e8: 687b ldr r3, [r7, #4]
80055ea: 681b ldr r3, [r3, #0]
80055ec: 685a ldr r2, [r3, #4]
80055ee: 687b ldr r3, [r7, #4]
80055f0: 681b ldr r3, [r3, #0]
80055f2: f422 4290 bic.w r2, r2, #18432 @ 0x4800
80055f6: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80055f8: 687b ldr r3, [r7, #4]
80055fa: 681b ldr r3, [r3, #0]
80055fc: 689a ldr r2, [r3, #8]
80055fe: 687b ldr r3, [r7, #4]
8005600: 681b ldr r3, [r3, #0]
8005602: f022 022a bic.w r2, r2, #42 @ 0x2a
8005606: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8005608: 687b ldr r3, [r7, #4]
800560a: 681b ldr r3, [r3, #0]
800560c: 681a ldr r2, [r3, #0]
800560e: 687b ldr r3, [r7, #4]
8005610: 681b ldr r3, [r3, #0]
8005612: f042 0201 orr.w r2, r2, #1
8005616: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8005618: 6878 ldr r0, [r7, #4]
800561a: f000 fa7b bl 8005b14 <UART_CheckIdleState>
800561e: 4603 mov r3, r0
}
8005620: 4618 mov r0, r3
8005622: 3708 adds r7, #8
8005624: 46bd mov sp, r7
8005626: bd80 pop {r7, pc}
08005628 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8005628: b580 push {r7, lr}
800562a: b088 sub sp, #32
800562c: af00 add r7, sp, #0
800562e: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8005630: 2300 movs r3, #0
8005632: 77bb strb r3, [r7, #30]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8005634: 687b ldr r3, [r7, #4]
8005636: 689a ldr r2, [r3, #8]
8005638: 687b ldr r3, [r7, #4]
800563a: 691b ldr r3, [r3, #16]
800563c: 431a orrs r2, r3
800563e: 687b ldr r3, [r7, #4]
8005640: 695b ldr r3, [r3, #20]
8005642: 431a orrs r2, r3
8005644: 687b ldr r3, [r7, #4]
8005646: 69db ldr r3, [r3, #28]
8005648: 4313 orrs r3, r2
800564a: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
800564c: 687b ldr r3, [r7, #4]
800564e: 681b ldr r3, [r3, #0]
8005650: 681b ldr r3, [r3, #0]
8005652: f423 4316 bic.w r3, r3, #38400 @ 0x9600
8005656: f023 030c bic.w r3, r3, #12
800565a: 687a ldr r2, [r7, #4]
800565c: 6812 ldr r2, [r2, #0]
800565e: 6979 ldr r1, [r7, #20]
8005660: 430b orrs r3, r1
8005662: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8005664: 687b ldr r3, [r7, #4]
8005666: 681b ldr r3, [r3, #0]
8005668: 685b ldr r3, [r3, #4]
800566a: f423 5140 bic.w r1, r3, #12288 @ 0x3000
800566e: 687b ldr r3, [r7, #4]
8005670: 68da ldr r2, [r3, #12]
8005672: 687b ldr r3, [r7, #4]
8005674: 681b ldr r3, [r3, #0]
8005676: 430a orrs r2, r1
8005678: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
800567a: 687b ldr r3, [r7, #4]
800567c: 699b ldr r3, [r3, #24]
800567e: 617b str r3, [r7, #20]
tmpreg |= huart->Init.OneBitSampling;
8005680: 687b ldr r3, [r7, #4]
8005682: 6a1b ldr r3, [r3, #32]
8005684: 697a ldr r2, [r7, #20]
8005686: 4313 orrs r3, r2
8005688: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
800568a: 687b ldr r3, [r7, #4]
800568c: 681b ldr r3, [r3, #0]
800568e: 689b ldr r3, [r3, #8]
8005690: f423 6130 bic.w r1, r3, #2816 @ 0xb00
8005694: 687b ldr r3, [r7, #4]
8005696: 681b ldr r3, [r3, #0]
8005698: 697a ldr r2, [r7, #20]
800569a: 430a orrs r2, r1
800569c: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
800569e: 687b ldr r3, [r7, #4]
80056a0: 681b ldr r3, [r3, #0]
80056a2: 4aa7 ldr r2, [pc, #668] @ (8005940 <UART_SetConfig+0x318>)
80056a4: 4293 cmp r3, r2
80056a6: d120 bne.n 80056ea <UART_SetConfig+0xc2>
80056a8: 4ba6 ldr r3, [pc, #664] @ (8005944 <UART_SetConfig+0x31c>)
80056aa: 6b1b ldr r3, [r3, #48] @ 0x30
80056ac: f003 0303 and.w r3, r3, #3
80056b0: 2b03 cmp r3, #3
80056b2: d817 bhi.n 80056e4 <UART_SetConfig+0xbc>
80056b4: a201 add r2, pc, #4 @ (adr r2, 80056bc <UART_SetConfig+0x94>)
80056b6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80056ba: bf00 nop
80056bc: 080056cd .word 0x080056cd
80056c0: 080056d9 .word 0x080056d9
80056c4: 080056df .word 0x080056df
80056c8: 080056d3 .word 0x080056d3
80056cc: 2301 movs r3, #1
80056ce: 77fb strb r3, [r7, #31]
80056d0: e0b5 b.n 800583e <UART_SetConfig+0x216>
80056d2: 2302 movs r3, #2
80056d4: 77fb strb r3, [r7, #31]
80056d6: e0b2 b.n 800583e <UART_SetConfig+0x216>
80056d8: 2304 movs r3, #4
80056da: 77fb strb r3, [r7, #31]
80056dc: e0af b.n 800583e <UART_SetConfig+0x216>
80056de: 2308 movs r3, #8
80056e0: 77fb strb r3, [r7, #31]
80056e2: e0ac b.n 800583e <UART_SetConfig+0x216>
80056e4: 2310 movs r3, #16
80056e6: 77fb strb r3, [r7, #31]
80056e8: e0a9 b.n 800583e <UART_SetConfig+0x216>
80056ea: 687b ldr r3, [r7, #4]
80056ec: 681b ldr r3, [r3, #0]
80056ee: 4a96 ldr r2, [pc, #600] @ (8005948 <UART_SetConfig+0x320>)
80056f0: 4293 cmp r3, r2
80056f2: d124 bne.n 800573e <UART_SetConfig+0x116>
80056f4: 4b93 ldr r3, [pc, #588] @ (8005944 <UART_SetConfig+0x31c>)
80056f6: 6b1b ldr r3, [r3, #48] @ 0x30
80056f8: f403 3340 and.w r3, r3, #196608 @ 0x30000
80056fc: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
8005700: d011 beq.n 8005726 <UART_SetConfig+0xfe>
8005702: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
8005706: d817 bhi.n 8005738 <UART_SetConfig+0x110>
8005708: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
800570c: d011 beq.n 8005732 <UART_SetConfig+0x10a>
800570e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8005712: d811 bhi.n 8005738 <UART_SetConfig+0x110>
8005714: 2b00 cmp r3, #0
8005716: d003 beq.n 8005720 <UART_SetConfig+0xf8>
8005718: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800571c: d006 beq.n 800572c <UART_SetConfig+0x104>
800571e: e00b b.n 8005738 <UART_SetConfig+0x110>
8005720: 2300 movs r3, #0
8005722: 77fb strb r3, [r7, #31]
8005724: e08b b.n 800583e <UART_SetConfig+0x216>
8005726: 2302 movs r3, #2
8005728: 77fb strb r3, [r7, #31]
800572a: e088 b.n 800583e <UART_SetConfig+0x216>
800572c: 2304 movs r3, #4
800572e: 77fb strb r3, [r7, #31]
8005730: e085 b.n 800583e <UART_SetConfig+0x216>
8005732: 2308 movs r3, #8
8005734: 77fb strb r3, [r7, #31]
8005736: e082 b.n 800583e <UART_SetConfig+0x216>
8005738: 2310 movs r3, #16
800573a: 77fb strb r3, [r7, #31]
800573c: e07f b.n 800583e <UART_SetConfig+0x216>
800573e: 687b ldr r3, [r7, #4]
8005740: 681b ldr r3, [r3, #0]
8005742: 4a82 ldr r2, [pc, #520] @ (800594c <UART_SetConfig+0x324>)
8005744: 4293 cmp r3, r2
8005746: d124 bne.n 8005792 <UART_SetConfig+0x16a>
8005748: 4b7e ldr r3, [pc, #504] @ (8005944 <UART_SetConfig+0x31c>)
800574a: 6b1b ldr r3, [r3, #48] @ 0x30
800574c: f403 2340 and.w r3, r3, #786432 @ 0xc0000
8005750: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
8005754: d011 beq.n 800577a <UART_SetConfig+0x152>
8005756: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
800575a: d817 bhi.n 800578c <UART_SetConfig+0x164>
800575c: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
8005760: d011 beq.n 8005786 <UART_SetConfig+0x15e>
8005762: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
8005766: d811 bhi.n 800578c <UART_SetConfig+0x164>
8005768: 2b00 cmp r3, #0
800576a: d003 beq.n 8005774 <UART_SetConfig+0x14c>
800576c: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8005770: d006 beq.n 8005780 <UART_SetConfig+0x158>
8005772: e00b b.n 800578c <UART_SetConfig+0x164>
8005774: 2300 movs r3, #0
8005776: 77fb strb r3, [r7, #31]
8005778: e061 b.n 800583e <UART_SetConfig+0x216>
800577a: 2302 movs r3, #2
800577c: 77fb strb r3, [r7, #31]
800577e: e05e b.n 800583e <UART_SetConfig+0x216>
8005780: 2304 movs r3, #4
8005782: 77fb strb r3, [r7, #31]
8005784: e05b b.n 800583e <UART_SetConfig+0x216>
8005786: 2308 movs r3, #8
8005788: 77fb strb r3, [r7, #31]
800578a: e058 b.n 800583e <UART_SetConfig+0x216>
800578c: 2310 movs r3, #16
800578e: 77fb strb r3, [r7, #31]
8005790: e055 b.n 800583e <UART_SetConfig+0x216>
8005792: 687b ldr r3, [r7, #4]
8005794: 681b ldr r3, [r3, #0]
8005796: 4a6e ldr r2, [pc, #440] @ (8005950 <UART_SetConfig+0x328>)
8005798: 4293 cmp r3, r2
800579a: d124 bne.n 80057e6 <UART_SetConfig+0x1be>
800579c: 4b69 ldr r3, [pc, #420] @ (8005944 <UART_SetConfig+0x31c>)
800579e: 6b1b ldr r3, [r3, #48] @ 0x30
80057a0: f403 1340 and.w r3, r3, #3145728 @ 0x300000
80057a4: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000
80057a8: d011 beq.n 80057ce <UART_SetConfig+0x1a6>
80057aa: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000
80057ae: d817 bhi.n 80057e0 <UART_SetConfig+0x1b8>
80057b0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
80057b4: d011 beq.n 80057da <UART_SetConfig+0x1b2>
80057b6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
80057ba: d811 bhi.n 80057e0 <UART_SetConfig+0x1b8>
80057bc: 2b00 cmp r3, #0
80057be: d003 beq.n 80057c8 <UART_SetConfig+0x1a0>
80057c0: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80057c4: d006 beq.n 80057d4 <UART_SetConfig+0x1ac>
80057c6: e00b b.n 80057e0 <UART_SetConfig+0x1b8>
80057c8: 2300 movs r3, #0
80057ca: 77fb strb r3, [r7, #31]
80057cc: e037 b.n 800583e <UART_SetConfig+0x216>
80057ce: 2302 movs r3, #2
80057d0: 77fb strb r3, [r7, #31]
80057d2: e034 b.n 800583e <UART_SetConfig+0x216>
80057d4: 2304 movs r3, #4
80057d6: 77fb strb r3, [r7, #31]
80057d8: e031 b.n 800583e <UART_SetConfig+0x216>
80057da: 2308 movs r3, #8
80057dc: 77fb strb r3, [r7, #31]
80057de: e02e b.n 800583e <UART_SetConfig+0x216>
80057e0: 2310 movs r3, #16
80057e2: 77fb strb r3, [r7, #31]
80057e4: e02b b.n 800583e <UART_SetConfig+0x216>
80057e6: 687b ldr r3, [r7, #4]
80057e8: 681b ldr r3, [r3, #0]
80057ea: 4a5a ldr r2, [pc, #360] @ (8005954 <UART_SetConfig+0x32c>)
80057ec: 4293 cmp r3, r2
80057ee: d124 bne.n 800583a <UART_SetConfig+0x212>
80057f0: 4b54 ldr r3, [pc, #336] @ (8005944 <UART_SetConfig+0x31c>)
80057f2: 6b1b ldr r3, [r3, #48] @ 0x30
80057f4: f403 0340 and.w r3, r3, #12582912 @ 0xc00000
80057f8: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
80057fc: d011 beq.n 8005822 <UART_SetConfig+0x1fa>
80057fe: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
8005802: d817 bhi.n 8005834 <UART_SetConfig+0x20c>
8005804: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
8005808: d011 beq.n 800582e <UART_SetConfig+0x206>
800580a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
800580e: d811 bhi.n 8005834 <UART_SetConfig+0x20c>
8005810: 2b00 cmp r3, #0
8005812: d003 beq.n 800581c <UART_SetConfig+0x1f4>
8005814: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8005818: d006 beq.n 8005828 <UART_SetConfig+0x200>
800581a: e00b b.n 8005834 <UART_SetConfig+0x20c>
800581c: 2300 movs r3, #0
800581e: 77fb strb r3, [r7, #31]
8005820: e00d b.n 800583e <UART_SetConfig+0x216>
8005822: 2302 movs r3, #2
8005824: 77fb strb r3, [r7, #31]
8005826: e00a b.n 800583e <UART_SetConfig+0x216>
8005828: 2304 movs r3, #4
800582a: 77fb strb r3, [r7, #31]
800582c: e007 b.n 800583e <UART_SetConfig+0x216>
800582e: 2308 movs r3, #8
8005830: 77fb strb r3, [r7, #31]
8005832: e004 b.n 800583e <UART_SetConfig+0x216>
8005834: 2310 movs r3, #16
8005836: 77fb strb r3, [r7, #31]
8005838: e001 b.n 800583e <UART_SetConfig+0x216>
800583a: 2310 movs r3, #16
800583c: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
800583e: 687b ldr r3, [r7, #4]
8005840: 69db ldr r3, [r3, #28]
8005842: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8005846: d15b bne.n 8005900 <UART_SetConfig+0x2d8>
{
switch (clocksource)
8005848: 7ffb ldrb r3, [r7, #31]
800584a: 2b08 cmp r3, #8
800584c: d827 bhi.n 800589e <UART_SetConfig+0x276>
800584e: a201 add r2, pc, #4 @ (adr r2, 8005854 <UART_SetConfig+0x22c>)
8005850: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005854: 08005879 .word 0x08005879
8005858: 08005881 .word 0x08005881
800585c: 08005889 .word 0x08005889
8005860: 0800589f .word 0x0800589f
8005864: 0800588f .word 0x0800588f
8005868: 0800589f .word 0x0800589f
800586c: 0800589f .word 0x0800589f
8005870: 0800589f .word 0x0800589f
8005874: 08005897 .word 0x08005897
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8005878: f7ff f9f6 bl 8004c68 <HAL_RCC_GetPCLK1Freq>
800587c: 61b8 str r0, [r7, #24]
break;
800587e: e013 b.n 80058a8 <UART_SetConfig+0x280>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8005880: f7ff fa14 bl 8004cac <HAL_RCC_GetPCLK2Freq>
8005884: 61b8 str r0, [r7, #24]
break;
8005886: e00f b.n 80058a8 <UART_SetConfig+0x280>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8005888: 4b33 ldr r3, [pc, #204] @ (8005958 <UART_SetConfig+0x330>)
800588a: 61bb str r3, [r7, #24]
break;
800588c: e00c b.n 80058a8 <UART_SetConfig+0x280>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800588e: f7ff f973 bl 8004b78 <HAL_RCC_GetSysClockFreq>
8005892: 61b8 str r0, [r7, #24]
break;
8005894: e008 b.n 80058a8 <UART_SetConfig+0x280>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8005896: f44f 4300 mov.w r3, #32768 @ 0x8000
800589a: 61bb str r3, [r7, #24]
break;
800589c: e004 b.n 80058a8 <UART_SetConfig+0x280>
default:
pclk = 0U;
800589e: 2300 movs r3, #0
80058a0: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
80058a2: 2301 movs r3, #1
80058a4: 77bb strb r3, [r7, #30]
break;
80058a6: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
80058a8: 69bb ldr r3, [r7, #24]
80058aa: 2b00 cmp r3, #0
80058ac: f000 8082 beq.w 80059b4 <UART_SetConfig+0x38c>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
80058b0: 69bb ldr r3, [r7, #24]
80058b2: 005a lsls r2, r3, #1
80058b4: 687b ldr r3, [r7, #4]
80058b6: 685b ldr r3, [r3, #4]
80058b8: 085b lsrs r3, r3, #1
80058ba: 441a add r2, r3
80058bc: 687b ldr r3, [r7, #4]
80058be: 685b ldr r3, [r3, #4]
80058c0: fbb2 f3f3 udiv r3, r2, r3
80058c4: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80058c6: 693b ldr r3, [r7, #16]
80058c8: 2b0f cmp r3, #15
80058ca: d916 bls.n 80058fa <UART_SetConfig+0x2d2>
80058cc: 693b ldr r3, [r7, #16]
80058ce: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80058d2: d212 bcs.n 80058fa <UART_SetConfig+0x2d2>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
80058d4: 693b ldr r3, [r7, #16]
80058d6: b29b uxth r3, r3
80058d8: f023 030f bic.w r3, r3, #15
80058dc: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
80058de: 693b ldr r3, [r7, #16]
80058e0: 085b lsrs r3, r3, #1
80058e2: b29b uxth r3, r3
80058e4: f003 0307 and.w r3, r3, #7
80058e8: b29a uxth r2, r3
80058ea: 89fb ldrh r3, [r7, #14]
80058ec: 4313 orrs r3, r2
80058ee: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
80058f0: 687b ldr r3, [r7, #4]
80058f2: 681b ldr r3, [r3, #0]
80058f4: 89fa ldrh r2, [r7, #14]
80058f6: 60da str r2, [r3, #12]
80058f8: e05c b.n 80059b4 <UART_SetConfig+0x38c>
}
else
{
ret = HAL_ERROR;
80058fa: 2301 movs r3, #1
80058fc: 77bb strb r3, [r7, #30]
80058fe: e059 b.n 80059b4 <UART_SetConfig+0x38c>
}
}
}
else
{
switch (clocksource)
8005900: 7ffb ldrb r3, [r7, #31]
8005902: 2b08 cmp r3, #8
8005904: d835 bhi.n 8005972 <UART_SetConfig+0x34a>
8005906: a201 add r2, pc, #4 @ (adr r2, 800590c <UART_SetConfig+0x2e4>)
8005908: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800590c: 08005931 .word 0x08005931
8005910: 08005939 .word 0x08005939
8005914: 0800595d .word 0x0800595d
8005918: 08005973 .word 0x08005973
800591c: 08005963 .word 0x08005963
8005920: 08005973 .word 0x08005973
8005924: 08005973 .word 0x08005973
8005928: 08005973 .word 0x08005973
800592c: 0800596b .word 0x0800596b
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8005930: f7ff f99a bl 8004c68 <HAL_RCC_GetPCLK1Freq>
8005934: 61b8 str r0, [r7, #24]
break;
8005936: e021 b.n 800597c <UART_SetConfig+0x354>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8005938: f7ff f9b8 bl 8004cac <HAL_RCC_GetPCLK2Freq>
800593c: 61b8 str r0, [r7, #24]
break;
800593e: e01d b.n 800597c <UART_SetConfig+0x354>
8005940: 40013800 .word 0x40013800
8005944: 40021000 .word 0x40021000
8005948: 40004400 .word 0x40004400
800594c: 40004800 .word 0x40004800
8005950: 40004c00 .word 0x40004c00
8005954: 40005000 .word 0x40005000
8005958: 007a1200 .word 0x007a1200
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
800595c: 4b1b ldr r3, [pc, #108] @ (80059cc <UART_SetConfig+0x3a4>)
800595e: 61bb str r3, [r7, #24]
break;
8005960: e00c b.n 800597c <UART_SetConfig+0x354>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8005962: f7ff f909 bl 8004b78 <HAL_RCC_GetSysClockFreq>
8005966: 61b8 str r0, [r7, #24]
break;
8005968: e008 b.n 800597c <UART_SetConfig+0x354>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
800596a: f44f 4300 mov.w r3, #32768 @ 0x8000
800596e: 61bb str r3, [r7, #24]
break;
8005970: e004 b.n 800597c <UART_SetConfig+0x354>
default:
pclk = 0U;
8005972: 2300 movs r3, #0
8005974: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
8005976: 2301 movs r3, #1
8005978: 77bb strb r3, [r7, #30]
break;
800597a: bf00 nop
}
if (pclk != 0U)
800597c: 69bb ldr r3, [r7, #24]
800597e: 2b00 cmp r3, #0
8005980: d018 beq.n 80059b4 <UART_SetConfig+0x38c>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
8005982: 687b ldr r3, [r7, #4]
8005984: 685b ldr r3, [r3, #4]
8005986: 085a lsrs r2, r3, #1
8005988: 69bb ldr r3, [r7, #24]
800598a: 441a add r2, r3
800598c: 687b ldr r3, [r7, #4]
800598e: 685b ldr r3, [r3, #4]
8005990: fbb2 f3f3 udiv r3, r2, r3
8005994: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8005996: 693b ldr r3, [r7, #16]
8005998: 2b0f cmp r3, #15
800599a: d909 bls.n 80059b0 <UART_SetConfig+0x388>
800599c: 693b ldr r3, [r7, #16]
800599e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80059a2: d205 bcs.n 80059b0 <UART_SetConfig+0x388>
{
huart->Instance->BRR = (uint16_t)usartdiv;
80059a4: 693b ldr r3, [r7, #16]
80059a6: b29a uxth r2, r3
80059a8: 687b ldr r3, [r7, #4]
80059aa: 681b ldr r3, [r3, #0]
80059ac: 60da str r2, [r3, #12]
80059ae: e001 b.n 80059b4 <UART_SetConfig+0x38c>
}
else
{
ret = HAL_ERROR;
80059b0: 2301 movs r3, #1
80059b2: 77bb strb r3, [r7, #30]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
80059b4: 687b ldr r3, [r7, #4]
80059b6: 2200 movs r2, #0
80059b8: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
80059ba: 687b ldr r3, [r7, #4]
80059bc: 2200 movs r2, #0
80059be: 66da str r2, [r3, #108] @ 0x6c
return ret;
80059c0: 7fbb ldrb r3, [r7, #30]
}
80059c2: 4618 mov r0, r3
80059c4: 3720 adds r7, #32
80059c6: 46bd mov sp, r7
80059c8: bd80 pop {r7, pc}
80059ca: bf00 nop
80059cc: 007a1200 .word 0x007a1200
080059d0 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
80059d0: b480 push {r7}
80059d2: b083 sub sp, #12
80059d4: af00 add r7, sp, #0
80059d6: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
80059d8: 687b ldr r3, [r7, #4]
80059da: 6a5b ldr r3, [r3, #36] @ 0x24
80059dc: f003 0301 and.w r3, r3, #1
80059e0: 2b00 cmp r3, #0
80059e2: d00a beq.n 80059fa <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
80059e4: 687b ldr r3, [r7, #4]
80059e6: 681b ldr r3, [r3, #0]
80059e8: 685b ldr r3, [r3, #4]
80059ea: f423 3100 bic.w r1, r3, #131072 @ 0x20000
80059ee: 687b ldr r3, [r7, #4]
80059f0: 6a9a ldr r2, [r3, #40] @ 0x28
80059f2: 687b ldr r3, [r7, #4]
80059f4: 681b ldr r3, [r3, #0]
80059f6: 430a orrs r2, r1
80059f8: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
80059fa: 687b ldr r3, [r7, #4]
80059fc: 6a5b ldr r3, [r3, #36] @ 0x24
80059fe: f003 0302 and.w r3, r3, #2
8005a02: 2b00 cmp r3, #0
8005a04: d00a beq.n 8005a1c <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8005a06: 687b ldr r3, [r7, #4]
8005a08: 681b ldr r3, [r3, #0]
8005a0a: 685b ldr r3, [r3, #4]
8005a0c: f423 3180 bic.w r1, r3, #65536 @ 0x10000
8005a10: 687b ldr r3, [r7, #4]
8005a12: 6ada ldr r2, [r3, #44] @ 0x2c
8005a14: 687b ldr r3, [r7, #4]
8005a16: 681b ldr r3, [r3, #0]
8005a18: 430a orrs r2, r1
8005a1a: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8005a1c: 687b ldr r3, [r7, #4]
8005a1e: 6a5b ldr r3, [r3, #36] @ 0x24
8005a20: f003 0304 and.w r3, r3, #4
8005a24: 2b00 cmp r3, #0
8005a26: d00a beq.n 8005a3e <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8005a28: 687b ldr r3, [r7, #4]
8005a2a: 681b ldr r3, [r3, #0]
8005a2c: 685b ldr r3, [r3, #4]
8005a2e: f423 2180 bic.w r1, r3, #262144 @ 0x40000
8005a32: 687b ldr r3, [r7, #4]
8005a34: 6b1a ldr r2, [r3, #48] @ 0x30
8005a36: 687b ldr r3, [r7, #4]
8005a38: 681b ldr r3, [r3, #0]
8005a3a: 430a orrs r2, r1
8005a3c: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8005a3e: 687b ldr r3, [r7, #4]
8005a40: 6a5b ldr r3, [r3, #36] @ 0x24
8005a42: f003 0308 and.w r3, r3, #8
8005a46: 2b00 cmp r3, #0
8005a48: d00a beq.n 8005a60 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8005a4a: 687b ldr r3, [r7, #4]
8005a4c: 681b ldr r3, [r3, #0]
8005a4e: 685b ldr r3, [r3, #4]
8005a50: f423 4100 bic.w r1, r3, #32768 @ 0x8000
8005a54: 687b ldr r3, [r7, #4]
8005a56: 6b5a ldr r2, [r3, #52] @ 0x34
8005a58: 687b ldr r3, [r7, #4]
8005a5a: 681b ldr r3, [r3, #0]
8005a5c: 430a orrs r2, r1
8005a5e: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8005a60: 687b ldr r3, [r7, #4]
8005a62: 6a5b ldr r3, [r3, #36] @ 0x24
8005a64: f003 0310 and.w r3, r3, #16
8005a68: 2b00 cmp r3, #0
8005a6a: d00a beq.n 8005a82 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8005a6c: 687b ldr r3, [r7, #4]
8005a6e: 681b ldr r3, [r3, #0]
8005a70: 689b ldr r3, [r3, #8]
8005a72: f423 5180 bic.w r1, r3, #4096 @ 0x1000
8005a76: 687b ldr r3, [r7, #4]
8005a78: 6b9a ldr r2, [r3, #56] @ 0x38
8005a7a: 687b ldr r3, [r7, #4]
8005a7c: 681b ldr r3, [r3, #0]
8005a7e: 430a orrs r2, r1
8005a80: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8005a82: 687b ldr r3, [r7, #4]
8005a84: 6a5b ldr r3, [r3, #36] @ 0x24
8005a86: f003 0320 and.w r3, r3, #32
8005a8a: 2b00 cmp r3, #0
8005a8c: d00a beq.n 8005aa4 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8005a8e: 687b ldr r3, [r7, #4]
8005a90: 681b ldr r3, [r3, #0]
8005a92: 689b ldr r3, [r3, #8]
8005a94: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8005a98: 687b ldr r3, [r7, #4]
8005a9a: 6bda ldr r2, [r3, #60] @ 0x3c
8005a9c: 687b ldr r3, [r7, #4]
8005a9e: 681b ldr r3, [r3, #0]
8005aa0: 430a orrs r2, r1
8005aa2: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8005aa4: 687b ldr r3, [r7, #4]
8005aa6: 6a5b ldr r3, [r3, #36] @ 0x24
8005aa8: f003 0340 and.w r3, r3, #64 @ 0x40
8005aac: 2b00 cmp r3, #0
8005aae: d01a beq.n 8005ae6 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8005ab0: 687b ldr r3, [r7, #4]
8005ab2: 681b ldr r3, [r3, #0]
8005ab4: 685b ldr r3, [r3, #4]
8005ab6: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
8005aba: 687b ldr r3, [r7, #4]
8005abc: 6c1a ldr r2, [r3, #64] @ 0x40
8005abe: 687b ldr r3, [r7, #4]
8005ac0: 681b ldr r3, [r3, #0]
8005ac2: 430a orrs r2, r1
8005ac4: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8005ac6: 687b ldr r3, [r7, #4]
8005ac8: 6c1b ldr r3, [r3, #64] @ 0x40
8005aca: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8005ace: d10a bne.n 8005ae6 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8005ad0: 687b ldr r3, [r7, #4]
8005ad2: 681b ldr r3, [r3, #0]
8005ad4: 685b ldr r3, [r3, #4]
8005ad6: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8005ada: 687b ldr r3, [r7, #4]
8005adc: 6c5a ldr r2, [r3, #68] @ 0x44
8005ade: 687b ldr r3, [r7, #4]
8005ae0: 681b ldr r3, [r3, #0]
8005ae2: 430a orrs r2, r1
8005ae4: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8005ae6: 687b ldr r3, [r7, #4]
8005ae8: 6a5b ldr r3, [r3, #36] @ 0x24
8005aea: f003 0380 and.w r3, r3, #128 @ 0x80
8005aee: 2b00 cmp r3, #0
8005af0: d00a beq.n 8005b08 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8005af2: 687b ldr r3, [r7, #4]
8005af4: 681b ldr r3, [r3, #0]
8005af6: 685b ldr r3, [r3, #4]
8005af8: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8005afc: 687b ldr r3, [r7, #4]
8005afe: 6c9a ldr r2, [r3, #72] @ 0x48
8005b00: 687b ldr r3, [r7, #4]
8005b02: 681b ldr r3, [r3, #0]
8005b04: 430a orrs r2, r1
8005b06: 605a str r2, [r3, #4]
}
}
8005b08: bf00 nop
8005b0a: 370c adds r7, #12
8005b0c: 46bd mov sp, r7
8005b0e: f85d 7b04 ldr.w r7, [sp], #4
8005b12: 4770 bx lr
08005b14 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8005b14: b580 push {r7, lr}
8005b16: b098 sub sp, #96 @ 0x60
8005b18: af02 add r7, sp, #8
8005b1a: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005b1c: 687b ldr r3, [r7, #4]
8005b1e: 2200 movs r2, #0
8005b20: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8005b24: f7fb fc68 bl 80013f8 <HAL_GetTick>
8005b28: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8005b2a: 687b ldr r3, [r7, #4]
8005b2c: 681b ldr r3, [r3, #0]
8005b2e: 681b ldr r3, [r3, #0]
8005b30: f003 0308 and.w r3, r3, #8
8005b34: 2b08 cmp r3, #8
8005b36: d12e bne.n 8005b96 <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8005b38: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8005b3c: 9300 str r3, [sp, #0]
8005b3e: 6d7b ldr r3, [r7, #84] @ 0x54
8005b40: 2200 movs r2, #0
8005b42: f44f 1100 mov.w r1, #2097152 @ 0x200000
8005b46: 6878 ldr r0, [r7, #4]
8005b48: f000 f88c bl 8005c64 <UART_WaitOnFlagUntilTimeout>
8005b4c: 4603 mov r3, r0
8005b4e: 2b00 cmp r3, #0
8005b50: d021 beq.n 8005b96 <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
8005b52: 687b ldr r3, [r7, #4]
8005b54: 681b ldr r3, [r3, #0]
8005b56: 63bb str r3, [r7, #56] @ 0x38
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005b58: 6bbb ldr r3, [r7, #56] @ 0x38
8005b5a: e853 3f00 ldrex r3, [r3]
8005b5e: 637b str r3, [r7, #52] @ 0x34
return(result);
8005b60: 6b7b ldr r3, [r7, #52] @ 0x34
8005b62: f023 0380 bic.w r3, r3, #128 @ 0x80
8005b66: 653b str r3, [r7, #80] @ 0x50
8005b68: 687b ldr r3, [r7, #4]
8005b6a: 681b ldr r3, [r3, #0]
8005b6c: 461a mov r2, r3
8005b6e: 6d3b ldr r3, [r7, #80] @ 0x50
8005b70: 647b str r3, [r7, #68] @ 0x44
8005b72: 643a str r2, [r7, #64] @ 0x40
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005b74: 6c39 ldr r1, [r7, #64] @ 0x40
8005b76: 6c7a ldr r2, [r7, #68] @ 0x44
8005b78: e841 2300 strex r3, r2, [r1]
8005b7c: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8005b7e: 6bfb ldr r3, [r7, #60] @ 0x3c
8005b80: 2b00 cmp r3, #0
8005b82: d1e6 bne.n 8005b52 <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
8005b84: 687b ldr r3, [r7, #4]
8005b86: 2220 movs r2, #32
8005b88: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
8005b8a: 687b ldr r3, [r7, #4]
8005b8c: 2200 movs r2, #0
8005b8e: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8005b92: 2303 movs r3, #3
8005b94: e062 b.n 8005c5c <UART_CheckIdleState+0x148>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8005b96: 687b ldr r3, [r7, #4]
8005b98: 681b ldr r3, [r3, #0]
8005b9a: 681b ldr r3, [r3, #0]
8005b9c: f003 0304 and.w r3, r3, #4
8005ba0: 2b04 cmp r3, #4
8005ba2: d149 bne.n 8005c38 <UART_CheckIdleState+0x124>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8005ba4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8005ba8: 9300 str r3, [sp, #0]
8005baa: 6d7b ldr r3, [r7, #84] @ 0x54
8005bac: 2200 movs r2, #0
8005bae: f44f 0180 mov.w r1, #4194304 @ 0x400000
8005bb2: 6878 ldr r0, [r7, #4]
8005bb4: f000 f856 bl 8005c64 <UART_WaitOnFlagUntilTimeout>
8005bb8: 4603 mov r3, r0
8005bba: 2b00 cmp r3, #0
8005bbc: d03c beq.n 8005c38 <UART_CheckIdleState+0x124>
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8005bbe: 687b ldr r3, [r7, #4]
8005bc0: 681b ldr r3, [r3, #0]
8005bc2: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005bc4: 6a7b ldr r3, [r7, #36] @ 0x24
8005bc6: e853 3f00 ldrex r3, [r3]
8005bca: 623b str r3, [r7, #32]
return(result);
8005bcc: 6a3b ldr r3, [r7, #32]
8005bce: f423 7390 bic.w r3, r3, #288 @ 0x120
8005bd2: 64fb str r3, [r7, #76] @ 0x4c
8005bd4: 687b ldr r3, [r7, #4]
8005bd6: 681b ldr r3, [r3, #0]
8005bd8: 461a mov r2, r3
8005bda: 6cfb ldr r3, [r7, #76] @ 0x4c
8005bdc: 633b str r3, [r7, #48] @ 0x30
8005bde: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005be0: 6af9 ldr r1, [r7, #44] @ 0x2c
8005be2: 6b3a ldr r2, [r7, #48] @ 0x30
8005be4: e841 2300 strex r3, r2, [r1]
8005be8: 62bb str r3, [r7, #40] @ 0x28
return(result);
8005bea: 6abb ldr r3, [r7, #40] @ 0x28
8005bec: 2b00 cmp r3, #0
8005bee: d1e6 bne.n 8005bbe <UART_CheckIdleState+0xaa>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005bf0: 687b ldr r3, [r7, #4]
8005bf2: 681b ldr r3, [r3, #0]
8005bf4: 3308 adds r3, #8
8005bf6: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005bf8: 693b ldr r3, [r7, #16]
8005bfa: e853 3f00 ldrex r3, [r3]
8005bfe: 60fb str r3, [r7, #12]
return(result);
8005c00: 68fb ldr r3, [r7, #12]
8005c02: f023 0301 bic.w r3, r3, #1
8005c06: 64bb str r3, [r7, #72] @ 0x48
8005c08: 687b ldr r3, [r7, #4]
8005c0a: 681b ldr r3, [r3, #0]
8005c0c: 3308 adds r3, #8
8005c0e: 6cba ldr r2, [r7, #72] @ 0x48
8005c10: 61fa str r2, [r7, #28]
8005c12: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005c14: 69b9 ldr r1, [r7, #24]
8005c16: 69fa ldr r2, [r7, #28]
8005c18: e841 2300 strex r3, r2, [r1]
8005c1c: 617b str r3, [r7, #20]
return(result);
8005c1e: 697b ldr r3, [r7, #20]
8005c20: 2b00 cmp r3, #0
8005c22: d1e5 bne.n 8005bf0 <UART_CheckIdleState+0xdc>
huart->RxState = HAL_UART_STATE_READY;
8005c24: 687b ldr r3, [r7, #4]
8005c26: 2220 movs r2, #32
8005c28: f8c3 2080 str.w r2, [r3, #128] @ 0x80
__HAL_UNLOCK(huart);
8005c2c: 687b ldr r3, [r7, #4]
8005c2e: 2200 movs r2, #0
8005c30: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8005c34: 2303 movs r3, #3
8005c36: e011 b.n 8005c5c <UART_CheckIdleState+0x148>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8005c38: 687b ldr r3, [r7, #4]
8005c3a: 2220 movs r2, #32
8005c3c: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
8005c3e: 687b ldr r3, [r7, #4]
8005c40: 2220 movs r2, #32
8005c42: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005c46: 687b ldr r3, [r7, #4]
8005c48: 2200 movs r2, #0
8005c4a: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
8005c4c: 687b ldr r3, [r7, #4]
8005c4e: 2200 movs r2, #0
8005c50: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
8005c52: 687b ldr r3, [r7, #4]
8005c54: 2200 movs r2, #0
8005c56: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
8005c5a: 2300 movs r3, #0
}
8005c5c: 4618 mov r0, r3
8005c5e: 3758 adds r7, #88 @ 0x58
8005c60: 46bd mov sp, r7
8005c62: bd80 pop {r7, pc}
08005c64 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8005c64: b580 push {r7, lr}
8005c66: b084 sub sp, #16
8005c68: af00 add r7, sp, #0
8005c6a: 60f8 str r0, [r7, #12]
8005c6c: 60b9 str r1, [r7, #8]
8005c6e: 603b str r3, [r7, #0]
8005c70: 4613 mov r3, r2
8005c72: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8005c74: e049 b.n 8005d0a <UART_WaitOnFlagUntilTimeout+0xa6>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8005c76: 69bb ldr r3, [r7, #24]
8005c78: f1b3 3fff cmp.w r3, #4294967295
8005c7c: d045 beq.n 8005d0a <UART_WaitOnFlagUntilTimeout+0xa6>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8005c7e: f7fb fbbb bl 80013f8 <HAL_GetTick>
8005c82: 4602 mov r2, r0
8005c84: 683b ldr r3, [r7, #0]
8005c86: 1ad3 subs r3, r2, r3
8005c88: 69ba ldr r2, [r7, #24]
8005c8a: 429a cmp r2, r3
8005c8c: d302 bcc.n 8005c94 <UART_WaitOnFlagUntilTimeout+0x30>
8005c8e: 69bb ldr r3, [r7, #24]
8005c90: 2b00 cmp r3, #0
8005c92: d101 bne.n 8005c98 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8005c94: 2303 movs r3, #3
8005c96: e048 b.n 8005d2a <UART_WaitOnFlagUntilTimeout+0xc6>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
8005c98: 68fb ldr r3, [r7, #12]
8005c9a: 681b ldr r3, [r3, #0]
8005c9c: 681b ldr r3, [r3, #0]
8005c9e: f003 0304 and.w r3, r3, #4
8005ca2: 2b00 cmp r3, #0
8005ca4: d031 beq.n 8005d0a <UART_WaitOnFlagUntilTimeout+0xa6>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8005ca6: 68fb ldr r3, [r7, #12]
8005ca8: 681b ldr r3, [r3, #0]
8005caa: 69db ldr r3, [r3, #28]
8005cac: f003 0308 and.w r3, r3, #8
8005cb0: 2b08 cmp r3, #8
8005cb2: d110 bne.n 8005cd6 <UART_WaitOnFlagUntilTimeout+0x72>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8005cb4: 68fb ldr r3, [r7, #12]
8005cb6: 681b ldr r3, [r3, #0]
8005cb8: 2208 movs r2, #8
8005cba: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8005cbc: 68f8 ldr r0, [r7, #12]
8005cbe: f000 f838 bl 8005d32 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8005cc2: 68fb ldr r3, [r7, #12]
8005cc4: 2208 movs r2, #8
8005cc6: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8005cca: 68fb ldr r3, [r7, #12]
8005ccc: 2200 movs r2, #0
8005cce: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
8005cd2: 2301 movs r3, #1
8005cd4: e029 b.n 8005d2a <UART_WaitOnFlagUntilTimeout+0xc6>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8005cd6: 68fb ldr r3, [r7, #12]
8005cd8: 681b ldr r3, [r3, #0]
8005cda: 69db ldr r3, [r3, #28]
8005cdc: f403 6300 and.w r3, r3, #2048 @ 0x800
8005ce0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8005ce4: d111 bne.n 8005d0a <UART_WaitOnFlagUntilTimeout+0xa6>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8005ce6: 68fb ldr r3, [r7, #12]
8005ce8: 681b ldr r3, [r3, #0]
8005cea: f44f 6200 mov.w r2, #2048 @ 0x800
8005cee: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8005cf0: 68f8 ldr r0, [r7, #12]
8005cf2: f000 f81e bl 8005d32 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8005cf6: 68fb ldr r3, [r7, #12]
8005cf8: 2220 movs r2, #32
8005cfa: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
8005cfe: 68fb ldr r3, [r7, #12]
8005d00: 2200 movs r2, #0
8005d02: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
8005d06: 2303 movs r3, #3
8005d08: e00f b.n 8005d2a <UART_WaitOnFlagUntilTimeout+0xc6>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8005d0a: 68fb ldr r3, [r7, #12]
8005d0c: 681b ldr r3, [r3, #0]
8005d0e: 69da ldr r2, [r3, #28]
8005d10: 68bb ldr r3, [r7, #8]
8005d12: 4013 ands r3, r2
8005d14: 68ba ldr r2, [r7, #8]
8005d16: 429a cmp r2, r3
8005d18: bf0c ite eq
8005d1a: 2301 moveq r3, #1
8005d1c: 2300 movne r3, #0
8005d1e: b2db uxtb r3, r3
8005d20: 461a mov r2, r3
8005d22: 79fb ldrb r3, [r7, #7]
8005d24: 429a cmp r2, r3
8005d26: d0a6 beq.n 8005c76 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8005d28: 2300 movs r3, #0
}
8005d2a: 4618 mov r0, r3
8005d2c: 3710 adds r7, #16
8005d2e: 46bd mov sp, r7
8005d30: bd80 pop {r7, pc}
08005d32 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8005d32: b480 push {r7}
8005d34: b095 sub sp, #84 @ 0x54
8005d36: af00 add r7, sp, #0
8005d38: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8005d3a: 687b ldr r3, [r7, #4]
8005d3c: 681b ldr r3, [r3, #0]
8005d3e: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005d40: 6b7b ldr r3, [r7, #52] @ 0x34
8005d42: e853 3f00 ldrex r3, [r3]
8005d46: 633b str r3, [r7, #48] @ 0x30
return(result);
8005d48: 6b3b ldr r3, [r7, #48] @ 0x30
8005d4a: f423 7390 bic.w r3, r3, #288 @ 0x120
8005d4e: 64fb str r3, [r7, #76] @ 0x4c
8005d50: 687b ldr r3, [r7, #4]
8005d52: 681b ldr r3, [r3, #0]
8005d54: 461a mov r2, r3
8005d56: 6cfb ldr r3, [r7, #76] @ 0x4c
8005d58: 643b str r3, [r7, #64] @ 0x40
8005d5a: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005d5c: 6bf9 ldr r1, [r7, #60] @ 0x3c
8005d5e: 6c3a ldr r2, [r7, #64] @ 0x40
8005d60: e841 2300 strex r3, r2, [r1]
8005d64: 63bb str r3, [r7, #56] @ 0x38
return(result);
8005d66: 6bbb ldr r3, [r7, #56] @ 0x38
8005d68: 2b00 cmp r3, #0
8005d6a: d1e6 bne.n 8005d3a <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005d6c: 687b ldr r3, [r7, #4]
8005d6e: 681b ldr r3, [r3, #0]
8005d70: 3308 adds r3, #8
8005d72: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005d74: 6a3b ldr r3, [r7, #32]
8005d76: e853 3f00 ldrex r3, [r3]
8005d7a: 61fb str r3, [r7, #28]
return(result);
8005d7c: 69fb ldr r3, [r7, #28]
8005d7e: f023 0301 bic.w r3, r3, #1
8005d82: 64bb str r3, [r7, #72] @ 0x48
8005d84: 687b ldr r3, [r7, #4]
8005d86: 681b ldr r3, [r3, #0]
8005d88: 3308 adds r3, #8
8005d8a: 6cba ldr r2, [r7, #72] @ 0x48
8005d8c: 62fa str r2, [r7, #44] @ 0x2c
8005d8e: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005d90: 6ab9 ldr r1, [r7, #40] @ 0x28
8005d92: 6afa ldr r2, [r7, #44] @ 0x2c
8005d94: e841 2300 strex r3, r2, [r1]
8005d98: 627b str r3, [r7, #36] @ 0x24
return(result);
8005d9a: 6a7b ldr r3, [r7, #36] @ 0x24
8005d9c: 2b00 cmp r3, #0
8005d9e: d1e5 bne.n 8005d6c <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8005da0: 687b ldr r3, [r7, #4]
8005da2: 6e1b ldr r3, [r3, #96] @ 0x60
8005da4: 2b01 cmp r3, #1
8005da6: d118 bne.n 8005dda <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005da8: 687b ldr r3, [r7, #4]
8005daa: 681b ldr r3, [r3, #0]
8005dac: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005dae: 68fb ldr r3, [r7, #12]
8005db0: e853 3f00 ldrex r3, [r3]
8005db4: 60bb str r3, [r7, #8]
return(result);
8005db6: 68bb ldr r3, [r7, #8]
8005db8: f023 0310 bic.w r3, r3, #16
8005dbc: 647b str r3, [r7, #68] @ 0x44
8005dbe: 687b ldr r3, [r7, #4]
8005dc0: 681b ldr r3, [r3, #0]
8005dc2: 461a mov r2, r3
8005dc4: 6c7b ldr r3, [r7, #68] @ 0x44
8005dc6: 61bb str r3, [r7, #24]
8005dc8: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005dca: 6979 ldr r1, [r7, #20]
8005dcc: 69ba ldr r2, [r7, #24]
8005dce: e841 2300 strex r3, r2, [r1]
8005dd2: 613b str r3, [r7, #16]
return(result);
8005dd4: 693b ldr r3, [r7, #16]
8005dd6: 2b00 cmp r3, #0
8005dd8: d1e6 bne.n 8005da8 <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005dda: 687b ldr r3, [r7, #4]
8005ddc: 2220 movs r2, #32
8005dde: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005de2: 687b ldr r3, [r7, #4]
8005de4: 2200 movs r2, #0
8005de6: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8005de8: 687b ldr r3, [r7, #4]
8005dea: 2200 movs r2, #0
8005dec: 669a str r2, [r3, #104] @ 0x68
}
8005dee: bf00 nop
8005df0: 3754 adds r7, #84 @ 0x54
8005df2: 46bd mov sp, r7
8005df4: f85d 7b04 ldr.w r7, [sp], #4
8005df8: 4770 bx lr
08005dfa <memset>:
8005dfa: 4402 add r2, r0
8005dfc: 4603 mov r3, r0
8005dfe: 4293 cmp r3, r2
8005e00: d100 bne.n 8005e04 <memset+0xa>
8005e02: 4770 bx lr
8005e04: f803 1b01 strb.w r1, [r3], #1
8005e08: e7f9 b.n 8005dfe <memset+0x4>
...
08005e0c <__libc_init_array>:
8005e0c: b570 push {r4, r5, r6, lr}
8005e0e: 4d0d ldr r5, [pc, #52] @ (8005e44 <__libc_init_array+0x38>)
8005e10: 4c0d ldr r4, [pc, #52] @ (8005e48 <__libc_init_array+0x3c>)
8005e12: 1b64 subs r4, r4, r5
8005e14: 10a4 asrs r4, r4, #2
8005e16: 2600 movs r6, #0
8005e18: 42a6 cmp r6, r4
8005e1a: d109 bne.n 8005e30 <__libc_init_array+0x24>
8005e1c: 4d0b ldr r5, [pc, #44] @ (8005e4c <__libc_init_array+0x40>)
8005e1e: 4c0c ldr r4, [pc, #48] @ (8005e50 <__libc_init_array+0x44>)
8005e20: f000 f818 bl 8005e54 <_init>
8005e24: 1b64 subs r4, r4, r5
8005e26: 10a4 asrs r4, r4, #2
8005e28: 2600 movs r6, #0
8005e2a: 42a6 cmp r6, r4
8005e2c: d105 bne.n 8005e3a <__libc_init_array+0x2e>
8005e2e: bd70 pop {r4, r5, r6, pc}
8005e30: f855 3b04 ldr.w r3, [r5], #4
8005e34: 4798 blx r3
8005e36: 3601 adds r6, #1
8005e38: e7ee b.n 8005e18 <__libc_init_array+0xc>
8005e3a: f855 3b04 ldr.w r3, [r5], #4
8005e3e: 4798 blx r3
8005e40: 3601 adds r6, #1
8005e42: e7f2 b.n 8005e2a <__libc_init_array+0x1e>
8005e44: 08005ea4 .word 0x08005ea4
8005e48: 08005ea4 .word 0x08005ea4
8005e4c: 08005ea4 .word 0x08005ea4
8005e50: 08005ea8 .word 0x08005ea8
08005e54 <_init>:
8005e54: b5f8 push {r3, r4, r5, r6, r7, lr}
8005e56: bf00 nop
8005e58: bcf8 pop {r3, r4, r5, r6, r7}
8005e5a: bc08 pop {r3}
8005e5c: 469e mov lr, r3
8005e5e: 4770 bx lr
08005e60 <_fini>:
8005e60: b5f8 push {r3, r4, r5, r6, r7, lr}
8005e62: bf00 nop
8005e64: bcf8 pop {r3, r4, r5, r6, r7}
8005e66: bc08 pop {r3}
8005e68: 469e mov lr, r3
8005e6a: 4770 bx lr
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