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implemented working epsc precharge and current monitoring

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This commit is contained in:
Janek Herm
2025-03-21 16:37:37 +01:00
parent 26aa408e96
commit 9ca69a2494
114 changed files with 16855 additions and 13200 deletions
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2
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
View File

@ -56,7 +56,7 @@
*/
#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F3xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\

5
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
View File

@ -4853,7 +4853,10 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
/* control registers) */

37
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
View File

@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
(+++) Configure CAN pins as alternate function open-drain
(+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
* @brief Configuration functions.
*
* @brief Configuration functions.
*
@verbatim
==============================================================================
##### Configuration functions #####
@ -954,8 +955,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
* @brief Control functions
*
* @brief Control functions
*
@verbatim
==============================================================================
##### Control functions #####
@ -1127,7 +1128,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@ -1143,15 +1143,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
count++;
/* Check if timeout is reached */
if (count > timeout)
if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
} while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@ -1592,8 +1591,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
*
* @brief Interrupts management
*
@verbatim
==============================================================================
##### Interrupts management #####
@ -2058,8 +2057,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
* @brief CAN Callback functions
*
* @brief CAN Callback functions
*
@verbatim
==============================================================================
##### Callback functions #####
@ -2308,8 +2307,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
* @brief CAN Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####

88
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
View File

@ -309,10 +309,42 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
}
/**
/**
* @brief Enables the MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Disables the MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
@ -321,38 +353,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00U;
MPU->RASR = 0x00U;
}
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
/* Apply configuration */
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */

511
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c
View File

@ -3,61 +3,61 @@
* @file stm32f3xx_hal_dma.c
* @author MCD Application Team
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
*
* This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
@verbatim
==============================================================================
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
==============================================================================
[..]
(#) Enable and configure the peripheral to be connected to the DMA Channel
(except for internal SRAM / FLASH memories: no initialization is
(except for internal SRAM / FLASH memories: no initialization is
necessary). Please refer to Reference manual for connection between peripherals
and DMA requests .
(#) For a given Channel, program the required configuration through the following parameters:
Transfer Direction, Source and Destination data formats,
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
(#) For a given Channel, program the required configuration through the following parameters:
Transfer Direction, Source and Destination data formats,
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
using HAL_DMA_Init() function.
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
(#) Use HAL_DMA_Abort() function to abort the current transfer
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
*** Polling mode IO operation ***
=================================
[..]
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
=================================
[..]
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
address and destination address and the Length of data to be transferred
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
case a fixed Timeout can be configured by User depending from his application.
*** Interrupt mode IO operation ***
===================================
*** Interrupt mode IO operation ***
===================================
[..]
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
Source address and destination address and the Length of data to be transferred.
In this case the DMA interrupt is configured
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
Source address and destination address and the Length of data to be transferred.
In this case the DMA interrupt is configured
(+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e a member of DMA handle structure).
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e a member of DMA handle structure).
*** DMA HAL driver macros list ***
=============================================
=============================================
[..]
Below the list of most used macros in DMA HAL driver.
[..]
(@) You can refer to the DMA HAL driver header file for more useful macros
[..]
(@) You can refer to the DMA HAL driver header file for more useful macros
@endverbatim
******************************************************************************
@ -71,7 +71,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@ -108,41 +108,41 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
===============================================================================
[..]
This section provides functions allowing to initialize the DMA Channel source
and destination addresses, incrementation and data sizes, transfer direction,
and destination addresses, incrementation and data sizes, transfer direction,
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
[..]
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
reference manual.
reference manual.
@endverbatim
* @{
*/
/**
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
{
uint32_t tmp = 0U;
/* Check the DMA handle allocation */
if(NULL == hdma)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
@ -152,18 +152,18 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Get the CR register value */
tmp = hdma->Instance->CCR;
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
hdma->Init.PeriphInc | hdma->Init.MemInc |
@ -171,28 +171,28 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
hdma->Init.Mode | hdma->Init.Priority;
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
/* Initialize DmaBaseAddress and ChannelIndex parameters used
hdma->Instance->CCR = tmp;
/* Initialize DmaBaseAddress and ChannelIndex parameters used
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
DMA_CalcBaseAndBitshift(hdma);
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
return HAL_OK;
}
}
/**
* @brief DeInitialize the DMA peripheral
* @brief DeInitialize the DMA peripheral
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
@ -202,7 +202,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -217,11 +217,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Reset DMA Channel peripheral address register */
hdma->Instance->CPAR = 0U;
/* Reset DMA Channel memory address register */
hdma->Instance->CMAR = 0U;
/* Get DMA Base Address */
/* Get DMA Base Address */
DMA_CalcBaseAndBitshift(hdma);
/* Clear all flags */
@ -249,20 +249,20 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
* @}
*/
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @brief I/O operation functions
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @brief I/O operation functions
*
@verbatim
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and Start DMA transfer
(+) Configure the source, destination address and data length and
(+) Configure the source, destination address and data length and
Start DMA transfer with interrupt
(+) Abort DMA transfer
(+) Poll for transfer complete
(+) Handle DMA interrupt request
(+) Handle DMA interrupt request
@endverbatim
* @{
@ -271,7 +271,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/**
* @brief Start the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@ -279,46 +279,46 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the Peripheral */
hdma->Instance->CCR |= DMA_CCR_EN;
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the Peripheral */
hdma->Instance->CCR |= DMA_CCR_EN;
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Remain BUSY */
status = HAL_BUSY;
}
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return status;
}
/* Remain BUSY */
status = HAL_BUSY;
}
return status;
}
/**
* @brief Start the DMA Transfer with interrupt enabled.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@ -326,53 +326,53 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete, & transfer error interrupts */
/* Half transfer interrupt is optional: enable it only if associated callback is available */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete, & transfer error interrupts */
/* Half transfer interrupt is optional: enable it only if associated callback is available */
if(NULL != hdma->XferHalfCpltCallback )
{
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
}
else
{
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
hdma->Instance->CCR &= ~DMA_IT_HT;
}
/* Enable the Peripheral */
hdma->Instance->CCR |= DMA_CCR_EN;
else
{
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
hdma->Instance->CCR &= ~DMA_IT_HT;
}
/* Enable the Peripheral */
hdma->Instance->CCR |= DMA_CCR_EN;
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Remain BUSY */
status = HAL_BUSY;
}
return status;
}
}
return status;
}
/**
* @brief Abort the DMA Transfer.
@ -382,33 +382,39 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
if(NULL == hdma)
{
return HAL_ERROR;
}
if(hdma->State != HAL_DMA_STATE_BUSY)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
else
{
/* Disable DMA IT */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
/* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
}
/* Change the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
@ -419,39 +425,38 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
status = HAL_ERROR;
}
else
{
{
/* Disable DMA IT */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
/* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Call User Abort callback */
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
}
}
}
return status;
}
@ -460,7 +465,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
* @brief Polling for transfer complete.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CompleteLevel Specifies the DMA level complete.
* @param CompleteLevel Specifies the DMA level complete.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@ -468,7 +473,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
{
uint32_t temp;
uint32_t tickstart = 0U;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
@ -476,14 +481,14 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Polling mode not supported in circular mode */
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Get the level transfer complete flag */
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
@ -502,23 +507,23 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
while(RESET == (hdma->DmaBaseAddress->ISR & temp))
{
if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
{
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma->State= HAL_DMA_STATE_READY;
hdma->State= HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
return HAL_ERROR;
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
@ -526,7 +531,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
@ -543,18 +548,18 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
/* The selected Channelx EN bit is cleared (DMA is disabled and
/* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY;
}
else
{
{
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
}
/* Process unlocked */
__HAL_UNLOCK(hdma);
__HAL_UNLOCK(hdma);
return HAL_OK;
}
@ -562,90 +567,90 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
/**
* @brief Handle DMA interrupt request.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t source_it = hdma->Instance->CCR;
/* Half Transfer Complete Interrupt management ******************************/
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
hdma->Instance->CCR &= ~DMA_IT_HT;
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
/* DMA peripheral state is not updated in Half Transfer */
/* State is updated only in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
hdma->Instance->CCR &= ~DMA_IT_HT;
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
/* DMA peripheral state is not updated in Half Transfer */
/* State is updated only in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
}
/* Transfer Complete Interrupt management ***********************************/
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the transfer complete & transfer error interrupts */
/* if the DMA mode is not CIRCULAR */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
}
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
}
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the transfer complete & transfer error interrupts */
/* if the DMA mode is not CIRCULAR */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
}
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
}
}
/* Transfer Error Interrupt management ***************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
{
/* When a DMA transfer error occurs */
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Then, disable all DMA interrupts */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
__HAL_UNLOCK(hdma);
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
}
/**
* @brief Register callbacks
@ -653,17 +658,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA Stream.
* @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback pointer to private callback function which has pointer to
* @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
@ -671,32 +676,32 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback;
break;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback;
break;
break;
default:
status = HAL_ERROR;
break;
break;
}
}
else
{
status = HAL_ERROR;
}
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
@ -707,14 +712,14 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
* @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
*/
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
@ -722,39 +727,39 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL;
break;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL;
break;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL;
break;
break;
case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
break;
break;
default:
status = HAL_ERROR;
break;
break;
}
}
else
{
status = HAL_ERROR;
}
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
@ -763,12 +768,12 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
*/
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
@verbatim
===============================================================================
##### State and Errors functions #####
===============================================================================
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DMA state
@ -776,12 +781,12 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
@endverbatim
* @{
*/
*/
/**
* @brief Returns the DMA state.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
@ -815,7 +820,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
/**
* @brief Set the DMA Transfer parameters.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@ -823,18 +828,18 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Clear all flags */
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
}
@ -843,7 +848,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
{
/* Configure DMA Channel source address */
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
@ -852,7 +857,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/**
* @brief Set the DMA base address and channel index depending on DMA instance
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* the configuration information for the specified DMA Stream.
* @retval None
*/
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
@ -865,7 +870,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
}
else
else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
@ -891,7 +896,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
/**
* @}
*/
/**
* @}
*/

4
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c
View File

@ -64,7 +64,7 @@
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@ -75,7 +75,7 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().

222
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
View File

@ -3,27 +3,27 @@
* @file stm32f3xx_hal_flash_ex.c
* @author MCD Application Team
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following
*
* This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* + Extended Initialization/de-initialization functions
* + Extended I/O operation functions
* + Extended Peripheral Control functions
*
* + Extended Peripheral Control functions
*
@verbatim
==============================================================================
##### Flash peripheral extended features #####
==============================================================================
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure and program the FLASH memory
[..] This driver provides functions to configure and program the FLASH memory
of all STM32F3xxx devices. It includes
(++) Set/Reset the write protection
(++) Program the user Option Bytes
(++) Get the Read protection Level
@endverbatim
******************************************************************************
* @attention
@ -84,7 +84,7 @@ extern FLASH_ProcessTypeDef pFlash;
*/
/**
* @}
*/
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@ -113,37 +113,37 @@ static uint8_t FLASH_OB_GetUser(void);
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
* @{
*/
/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
* @brief FLASH Memory Erasing functions
*
@verbatim
*
@verbatim
==============================================================================
##### FLASH Erasing Programming functions #####
##### FLASH Erasing Programming functions #####
==============================================================================
[..] The FLASH Memory Erasing functions, includes the following functions:
(+) HAL_FLASHEx_Erase: return only when erase has been done
(+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback
(+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback
is called with parameter 0xFFFFFFFF
[..] Any operation of erase should follow these steps:
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
program memory access.
(#) Call the desired function to erase page.
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
(recommended to protect the FLASH memory against possible unwanted operation).
@endverbatim
* @{
*/
/**
* @brief Perform a mass erase or erase the specified FLASH memory pages
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
@ -173,10 +173,10 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
{
/*Mass erase to be done*/
FLASH_MassErase();
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
}
@ -187,27 +187,27 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* Check the parameters */
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
/* Page Erase requested on address located on bank1 */
/* Wait for last operation to be completed */
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
/* Erase page by page to be done*/
for(address = pEraseInit->PageAddress;
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
address += FLASH_PAGE_SIZE)
{
FLASH_PageErase(address);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
if (status != HAL_OK)
{
/* In case of error, stop erase procedure and return the faulty address */
@ -247,7 +247,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
@ -285,13 +285,13 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
* @brief Option Bytes Programming functions
*
@verbatim
*
@verbatim
==============================================================================
##### Option Bytes Programming functions #####
==============================================================================
##### Option Bytes Programming functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
This subsection provides a set of functions allowing to control the FLASH
option bytes operations.
@endverbatim
@ -463,7 +463,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
{
uint32_t value = 0U;
if (DATAAdress == OB_DATA_ADDRESS_DATA0)
{
/* Get value programmed in OB USER Data0 */
@ -474,7 +474,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
/* Get value programmed in OB USER Data1 */
value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
}
return value;
}
@ -491,7 +491,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
*/
/**
* @brief Full erase of FLASH memory Bank
* @brief Full erase of FLASH memory Bank
*
* @retval None
*/
@ -507,14 +507,14 @@ static void FLASH_MassErase(void)
/**
* @brief Enable the write protection of the desired pages
* @note An option byte erase is done automatically in this function.
* @note When the memory read protection level is selected (RDP level = 1),
* @note An option byte erase is done automatically in this function.
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash page i if
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WriteProtectPage specifies the page(s) to be write protected.
* The value of this parameter depend on device used within the same series
* @retval HAL status
* The value of this parameter depend on device used within the same series
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
{
@ -529,42 +529,42 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
#if defined(OB_WRP3_WRP3)
uint16_t WRP3_Data = 0xFFFFU;
#endif /* OB_WRP3_WRP3 */
/* Check the parameters */
assert_param(IS_OB_WRP(WriteProtectPage));
/* Get current write protected pages and the new pages to be protected ******/
WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
#if defined(OB_WRP_PAGES0TO15MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
#endif /* OB_WRP_PAGES0TO31MASK */
#if defined(OB_WRP_PAGES16TO31MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
#endif /* OB_WRP_PAGES32TO63MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
#endif /* OB_WRP_PAGES32TO47MASK */
#if defined(OB_WRP_PAGES48TO127MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
#endif /* OB_WRP_PAGES48TO63MASK */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* To be able to write again option byte, need to perform a option byte erase */
status = HAL_FLASHEx_OBErase();
if (status == HAL_OK)
if (status == HAL_OK)
{
/* Enable write protection */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
@ -573,7 +573,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
if(WRP0_Data != 0xFFU)
{
OB->WRP0 &= WRP0_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
@ -583,7 +583,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
if((status == HAL_OK) && (WRP1_Data != 0xFFU))
{
OB->WRP1 &= WRP1_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
@ -593,7 +593,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
if((status == HAL_OK) && (WRP2_Data != 0xFFU))
{
OB->WRP2 &= WRP2_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
@ -603,7 +603,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
if((status == HAL_OK) && (WRP3_Data != 0xFFU))
{
OB->WRP3 &= WRP3_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
@ -613,20 +613,20 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
}
return status;
}
/**
* @brief Disable the write protection of the desired pages
* @note An option byte erase is done automatically in this function.
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash page i if
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @note An option byte erase is done automatically in this function.
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash page i if
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WriteProtectPage specifies the page(s) to be write unprotected.
* The value of this parameter depend on device used within the same series
* @retval HAL status
* The value of this parameter depend on device used within the same series
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
{
@ -641,7 +641,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
#if defined(OB_WRP3_WRP3)
uint16_t WRP3_Data = 0xFFFFU;
#endif /* OB_WRP3_WRP3 */
/* Check the parameters */
assert_param(IS_OB_WRP(WriteProtectPage));
@ -651,41 +651,41 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
#if defined(OB_WRP_PAGES0TO15MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
#endif /* OB_WRP_PAGES0TO31MASK */
#if defined(OB_WRP_PAGES16TO31MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
#endif /* OB_WRP_PAGES32TO63MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
#endif /* OB_WRP_PAGES32TO47MASK */
#if defined(OB_WRP_PAGES48TO127MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
#endif /* OB_WRP_PAGES48TO63MASK */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* To be able to write again option byte, need to perform a option byte erase */
status = HAL_FLASHEx_OBErase();
if (status == HAL_OK)
if (status == HAL_OK)
{
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
#if defined(OB_WRP0_WRP0)
if(WRP0_Data != 0xFFU)
{
OB->WRP0 |= WRP0_Data;
OB->WRP0 = WRP0_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
@ -694,8 +694,8 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
#if defined(OB_WRP1_WRP1)
if((status == HAL_OK) && (WRP1_Data != 0xFFU))
{
OB->WRP1 |= WRP1_Data;
OB->WRP1 = WRP1_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
@ -704,8 +704,8 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
#if defined(OB_WRP2_WRP2)
if((status == HAL_OK) && (WRP2_Data != 0xFFU))
{
OB->WRP2 |= WRP2_Data;
OB->WRP2 = WRP2_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
@ -714,8 +714,8 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
#if defined(OB_WRP3_WRP3)
if((status == HAL_OK) && (WRP3_Data != 0xFFU))
{
OB->WRP3 |= WRP3_Data;
OB->WRP3 = WRP3_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
}
@ -741,18 +741,18 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* If the previous operation is completed, proceed to erase the option bytes */
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
SET_BIT(FLASH->CR, FLASH_CR_STRT);
@ -767,26 +767,26 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
{
/* Enable the Option Bytes Programming operation */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
WRITE_REG(OB->RDP, ReadProtectLevel);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
}
return status;
}
/**
* @brief Program the FLASH User Option Byte.
* @brief Program the FLASH User Option Byte.
* @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
* @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
* And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
* And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
@ -806,15 +806,15 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Enable the Option Bytes Programming operation */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
OB->USER = (UserConfig | 0x08U);
#else
@ -827,44 +827,44 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
return status;
return status;
}
/**
* @brief Programs a half word at a specified Option Byte Data address.
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
* (system reset will occur)
* Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
* @param Address specifies the address to be programmed.
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
* @param Data specifies the data to be programmed.
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Check the parameters */
assert_param(IS_OB_DATA_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Enables the Option Bytes Programming operation */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
*(__IO uint16_t*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
@ -893,7 +893,7 @@ static uint32_t FLASH_OB_GetWRP(void)
static uint32_t FLASH_OB_GetRDP(void)
{
uint32_t tmp_reg = 0U;
/* Read RDP level bits */
#if defined(FLASH_OBR_RDPRT)
tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
@ -913,7 +913,7 @@ static uint32_t FLASH_OB_GetRDP(void)
{
return OB_RDP_LEVEL_0;
}
else
else
{
return OB_RDP_LEVEL_1;
}
@ -922,8 +922,8 @@ static uint32_t FLASH_OB_GetRDP(void)
/**
* @brief Return the FLASH User Option Byte value.
* @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
* And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
* And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
*/
static uint8_t FLASH_OB_GetUser(void)
{
@ -950,8 +950,8 @@ static uint8_t FLASH_OB_GetUser(void)
/**
* @brief Erase the specified FLASH memory page
* @param PageAddress FLASH page to erase
* The value of this parameter depend on device used within the same series
*
* The value of this parameter depend on device used within the same series
*
* @retval None
*/
void FLASH_PageErase(uint32_t PageAddress)

2
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
View File

@ -458,7 +458,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* until the next reset.
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
* @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)

508
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
View File

@ -90,7 +90,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@ -156,7 +156,7 @@
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
(++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
@ -214,7 +214,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@ -608,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
@ -1115,6 +1120,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@ -1138,18 +1144,39 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_WRITE);
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
xfermode = I2C_AUTOEND_MODE;
}
if (hi2c->XferSize > 0U)
{
/* Preload TX register */
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
hi2c->XferSize--;
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
I2C_GENERATE_START_WRITE);
}
else
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
I2C_GENERATE_START_WRITE);
}
@ -1261,7 +1288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_READ);
}
@ -1352,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
uint32_t Timeout)
{
uint32_t tickstart;
uint16_t tmpXferCount;
HAL_StatusTypeDef error;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@ -1378,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Preload TX data if no stretch enable */
if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{
@ -1399,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
hi2c->XferCount--;
}
/* Wait until ADDR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@ -1410,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
return HAL_ERROR;
}
@ -1422,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
return HAL_ERROR;
}
@ -1445,31 +1486,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Wait until AF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
if (error != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
tmpXferCount = hi2c->XferCount;
if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
{
/* Reset ErrorCode to NONE */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
else
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
}
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Clear AF flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Wait until STOP flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
else
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
return HAL_ERROR;
/* Clear AF flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Wait until STOP flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Clear STOP flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
/* Clear STOP flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
@ -1672,7 +1730,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
if (hi2c->XferSize > 0U)
{
/* Preload TX register */
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
hi2c->XferSize--;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
I2C_GENERATE_START_WRITE);
}
else
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
I2C_GENERATE_START_WRITE);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -1732,7 +1809,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
hi2c->XferSize = 1U;
xfermode = I2C_RELOAD_MODE;
}
else
@ -1895,6 +1972,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
uint32_t sizetoxfer = 0U;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@ -1927,6 +2005,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
xfermode = I2C_AUTOEND_MODE;
}
if (hi2c->XferSize > 0U)
{
/* Preload TX register */
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
sizetoxfer = hi2c->XferSize;
hi2c->XferCount--;
hi2c->XferSize--;
}
if (hi2c->XferSize > 0U)
{
if (hi2c->hdmatx != NULL)
@ -1942,8 +2034,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
(uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
@ -1964,7 +2056,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
xfermode, I2C_GENERATE_START_WRITE);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@ -2003,7 +2096,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
I2C_GENERATE_START_WRITE);
/* Process Unlocked */
@ -2065,7 +2158,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
hi2c->XferSize = 1U;
xfermode = I2C_RELOAD_MODE;
}
else
@ -2159,11 +2252,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
}
return HAL_OK;
@ -2612,7 +2705,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_READ);
}
@ -2650,7 +2743,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
hi2c->XferSize = 1U;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
}
@ -2728,6 +2821,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->XferSize = 0U;
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@ -2849,11 +2943,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
}
@ -3259,22 +3353,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
/* Check if the maximum allowed number of trials has been reached */
if (I2C_Trials == Trials)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
/* Increment Trials */
I2C_Trials++;
} while (I2C_Trials < Trials);
@ -3313,6 +3391,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@ -3344,6 +3423,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
xfermode = hi2c->XferOptions;
}
if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
(XferOptions == I2C_FIRST_AND_LAST_FRAME)))
{
/* Preload TX register */
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
sizetoxfer = hi2c->XferSize;
hi2c->XferCount--;
hi2c->XferSize--;
}
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
@ -3365,7 +3459,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
}
/* Send Slave Address and set NBYTES to write */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
}
else
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -3405,6 +3506,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
HAL_StatusTypeDef dmaxferstatus;
uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@ -3436,6 +3538,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
xfermode = hi2c->XferOptions;
}
if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
(XferOptions == I2C_FIRST_AND_LAST_FRAME)))
{
/* Preload TX register */
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
sizetoxfer = hi2c->XferSize;
hi2c->XferCount--;
hi2c->XferSize--;
}
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
@ -3471,8 +3588,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
(uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
@ -3492,7 +3609,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address and set NBYTES to write */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
}
else
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@ -3531,8 +3655,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_GENERATE_START_WRITE);
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
}
else
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -3795,11 +3925,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
}
return HAL_OK;
@ -4434,7 +4564,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
}
/**
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
* @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@ -4443,7 +4573,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
if (hi2c->Mode == HAL_I2C_MODE_MASTER)
HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
{
/* Process Locked */
__HAL_LOCK(hi2c);
@ -4842,17 +4974,22 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
hi2c->XferSize--;
hi2c->XferCount--;
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
if (hi2c->XferCount != 0U)
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
hi2c->XferSize--;
hi2c->XferCount--;
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
@ -4863,7 +5000,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
hi2c->XferSize = 1U;
}
else
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
@ -5018,7 +5163,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
{
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
hi2c->XferSize = 1U;
}
else
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@ -5039,6 +5192,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Disable Interrupt related to address step */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
direction = I2C_GENERATE_START_READ;
@ -5046,7 +5205,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
hi2c->XferSize = 1U;
}
else
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
@ -5103,9 +5270,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@ -5268,7 +5434,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
hi2c->XferSize = 1U;
}
else
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
xfermode = I2C_RELOAD_MODE;
}
else
@ -5405,6 +5579,9 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Disable Interrupt related to address step */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
/* Enable only Error interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
@ -5413,7 +5590,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
hi2c->XferSize = 1U;
}
else
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@ -5447,6 +5632,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Disable Interrupt related to address step */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
/* Enable only Error and NACK interrupt for data transfer */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
direction = I2C_GENERATE_START_READ;
@ -5454,7 +5645,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
hi2c->XferSize = 1U;
}
else
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
@ -5524,9 +5723,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@ -6125,6 +6323,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
uint32_t tmpoptions = hi2c->XferOptions;
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
@ -6141,6 +6340,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else if (tmpstate == HAL_I2C_STATE_LISTEN)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_NONE;
}
else
{
/* Do nothing */
@ -6207,6 +6411,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
}
}
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@ -6624,7 +6879,15 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
/* Set the XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Errata workaround 170323 */
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
hi2c->XferSize = 1U;
}
else
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
}
else
{
@ -6735,6 +6998,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
@ -6846,16 +7115,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
HAL_StatusTypeDef status = HAL_OK;
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
status = HAL_ERROR;
}
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
@ -6863,19 +7134,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
return HAL_OK;
status = HAL_OK;
}
else
/* Check a no-acknowledge have been detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
}
else
{
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@ -6889,12 +7155,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
status = HAL_ERROR;
}
else
{
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
{
@ -6904,11 +7174,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
status = HAL_ERROR;
}
}
}
return HAL_OK;
return status;
}
/**
@ -7103,13 +7373,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
@ -7136,13 +7406,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
@ -7158,7 +7428,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT))
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;

3
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
View File

@ -283,6 +283,9 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
/* Check the parameters */
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Prevent unused argument(s) compilation warning */
UNUSED(Regulator);
/* Clear SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

11
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
View File

@ -891,7 +891,10 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
/* Prevent unused argument(s) compilation warning */
UNUSED(RCC_MCOx);
/* Configure the MCO1 pin in alternate function mode */
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
@ -977,8 +980,8 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_Pos];
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
{
@ -1097,7 +1100,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)

10
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
View File

@ -1247,12 +1247,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> RCC_CFGR2_ADC1PRES_Pos) & 0xFU];
}
}
#else /* RCC_CFGR_ADCPRE */
/* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U);
frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> RCC_CFGR_ADCPRE_Pos) + 1U) * 2U);
#endif /* RCC_CFGR2_ADC1PRES */
break;
}
@ -1274,7 +1274,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> RCC_CFGR2_ADCPRE12_Pos) & 0xF];
}
}
break;
@ -1297,7 +1297,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> RCC_CFGR2_ADCPRE34_Pos) & 0xF];
}
}
break;
@ -1480,7 +1480,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Get the current SDADC source */
srcclk = __HAL_RCC_GET_SDADC_SOURCE();
/* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */
frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF];
frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> RCC_CFGR_SDPRE_Pos) & 0xF];
break;
}
#endif /* RCC_CFGR_SDPRE */

134
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
View File

@ -894,7 +894,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@ -986,7 +986,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@ -1065,7 +1065,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@ -1227,7 +1227,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@ -1657,7 +1657,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@ -1736,7 +1736,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@ -1897,7 +1897,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@ -2141,7 +2141,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
@ -2225,7 +2225,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@ -2313,7 +2313,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@ -2389,7 +2389,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Set the TIM channel state */
@ -2544,7 +2544,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Disable the Input Capture channel */
@ -3841,13 +3841,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
uint32_t itsource = htim->Instance->DIER;
uint32_t itflag = htim->Instance->SR;
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@ -3875,11 +3878,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@ -3905,11 +3908,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@ -3935,11 +3938,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@ -3965,11 +3968,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@ -3978,11 +3981,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
@ -3992,9 +3995,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
#if defined(TIM_BDTR_BK2E)
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@ -4006,11 +4009,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
#endif /* TIM_BDTR_BK2E */
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
@ -4019,11 +4022,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
@ -4583,7 +4586,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@ -7004,6 +7008,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
}
}
/**
@ -7018,11 +7029,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@ -7093,11 +7105,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@ -7126,7 +7139,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
@ -7171,11 +7183,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@ -7247,11 +7260,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@ -7311,11 +7325,12 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@ -7366,11 +7381,12 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@ -7555,9 +7571,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC1E;
tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
/* Select the Input */
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
@ -7645,9 +7661,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
@ -7684,9 +7700,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
@ -7728,9 +7744,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC3E;
tmpccmr2 = TIMx->CCMR2;
tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC3S;
@ -7776,9 +7792,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC4E;
tmpccmr2 = TIMx->CCMR2;
tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;

36
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
View File

@ -837,7 +837,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@ -1083,17 +1083,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
(+) Start the Complementary Input Capture measurement.
(+) Stop the Complementary Input Capture.
(+) Start the Complementary Input Capture and enable interrupts.
(+) Stop the Complementary Input Capture and disable interrupts.
(+) Start the Complementary Input Capture and enable DMA transfers.
(+) Stop the Complementary Input Capture and disable DMA transfers.
(+) Start the Complementary One Pulse generation.
(+) Stop the Complementary One Pulse.
(+) Start the Complementary One Pulse and enable interrupts.
(+) Stop the Complementary One Pulse and disable interrupts.
@endverbatim
* @{
*/
@ -1319,7 +1308,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@ -2260,7 +2249,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/**
* @brief Hall commutation changed callback in non-blocking mode
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@ -2274,7 +2263,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
*/
}
/**
* @brief Hall commutation changed half complete callback in non-blocking mode
* @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@ -2289,7 +2278,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
}
/**
* @brief Hall Break detection callback in non-blocking mode
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@ -2305,7 +2294,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
#if defined(TIM_BDTR_BK2E)
/**
* @brief Hall Break2 detection callback in non blocking mode
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
@ -2457,15 +2446,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
}
}
else
{
/* nothing to do */
@ -2534,13 +2514,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
{
uint32_t tmp;
tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
/* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
}
/**
* @}

111
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c
View File

@ -105,7 +105,7 @@
[..]
Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
weak function.
HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@ -127,10 +127,10 @@
[..]
By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
all callbacks are set to the corresponding weak functions:
examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
reset to the legacy weak functions in the HAL_UART_Init()
and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@ -147,7 +147,7 @@
[..]
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
and weak callbacks are used.
@endverbatim
@ -191,8 +191,8 @@
/** @addtogroup UART_Private_Functions
* @{
*/
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@ -330,17 +330,19 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
__HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
@ -395,17 +397,19 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
__HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* In half-duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
@ -481,17 +485,19 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
__HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* In LIN mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
@ -565,17 +571,19 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
__HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* In multiprocessor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register. */
@ -678,7 +686,7 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User UART Callback
* To be used instead of the weak predefined callback
* To be used to override the weak predefined callback
* @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
* HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
* callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
@ -926,10 +934,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_READY)
if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = pCallback;
}
@ -940,9 +945,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(huart);
return status;
}
@ -956,10 +958,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_READY)
if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
}
@ -970,8 +969,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(huart);
return status;
}
@ -3012,6 +3009,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
{
@ -3033,13 +3037,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
{
@ -3165,24 +3162,24 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
return HAL_TIMEOUT;
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
huart->ErrorCode = HAL_UART_ERROR_ORE;
huart->ErrorCode = HAL_UART_ERROR_ORE;
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_ERROR;
return HAL_ERROR;
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{

44
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c
View File

@ -193,17 +193,19 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
@ -597,7 +599,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
HAL_StatusTypeDef status = HAL_OK;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
@ -611,24 +613,20 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_IT(huart, pData, Size);
(void)UART_Start_Receive_IT(huart, pData, Size);
/* Check Rx process has been successfully started */
if (status == HAL_OK)
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
/* In case of errors already pending when reception is started,
Interrupts may have already been raised and lead to reception abortion.
(Overrun error for instance).
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
status = HAL_ERROR;
}
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
/* In case of errors already pending when reception is started,
Interrupts may have already been raised and lead to reception abortion.
(Overrun error for instance).
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
status = HAL_ERROR;
}
return status;
@ -724,7 +722,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
* @param huart UART handle.
* @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
*/
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
{
/* Return Rx Event type value, as stored in UART handle */
return (huart->RxEventType);