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implemented working epsc precharge and current monitoring

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This commit is contained in:
Janek Herm 2025-03-21 16:37:37 +01:00
parent 26aa408e96
commit 9ca69a2494
114 changed files with 16855 additions and 13200 deletions
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2
Hardware/FT25_PDU.kicad_pcb
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@ -7414,7 +7414,7 @@
)
(fp_arc
(start 0 2.2)
(mid 0.050001 2.250001)
(mid 0.05 2.25)
(end 0 2.300001)
(stroke
(width 0.1)

2
Hardware/bom/ibom.html
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2
Software/Code/.mxproject
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4
Software/Code/Core/Inc/can_communication.h
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@ -19,9 +19,9 @@
#define CUR_CHANNELS_2_ID 0xCB
#define CUR_CHANNELS_3_ID 0xCC
#define CUR_CHANNELS_4_ID 0xCD
//#define LV_SENS_ID 0xCE // not used
#define ERROR_ID 0xCE
typedef struct { // TODO: add error-codes
typedef struct {
enable_gpios iostatus;
uint8_t checksum;
} rx_status_frame;

11
Software/Code/Core/Inc/current_monitoring.h
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@ -11,19 +11,18 @@
#include "stm32f3xx_hal.h"
// convert ADC quants to V
#define ADC_V_FACTOR (3.3f / 4096) // 3.3V / 12bit
#define ADC_V_FACTOR (3.3f / 4095) // 3.3V / 12bit
// scale to LV by divider to mV
#define LV_SENSE_FACTOR (1e3 * (ADC_V_FACTOR * ((12.f + 1.8f) / 1.8f)))
#define PC_VSENSE_FACTOR (1e3 * (ADC_V_FACTOR * ((100.f + 10.f) / 10.f)));
#define LV_SENSE_FACTOR (1e3 * (ADC_V_FACTOR * ((12.f + 1.8f) / 1.8f))) // scaled with voltage divider
// convert ADC quants to I_S in mA
#define CURR_SENSE_IS_FACTOR_9A (ADC_V_FACTOR / 1.2f) // 3.3V / 12bit / 1.2kOhm
#define CURR_SENSE_IS_FACTOR_4_5A (ADC_V_FACTOR / 1.f)
#define CURR_SENSE_IS_FACTOR_1A (ADC_V_FACTOR / 4.f)
// convert ADC quants to I_L in mA
#define CURR_SENSE_FACTOR_1A (300 * CURR_SENSE_IS_FACTOR) // typical current sense ratio (datasheet PROFET)
#define CURR_SENSE_FACTOR_4_5A (1500 * CURR_SENSE_IS_FACTOR)
#define CURR_SENSE_FACTOR_9A (3900 * CURR_SENSE_IS_FACTOR)
#define CURR_SENSE_FACTOR_1A (300 * CURR_SENSE_IS_FACTOR_1A) // typical current sense ratio (datasheet PROFET)
#define CURR_SENSE_FACTOR_4_5A (1500 * CURR_SENSE_IS_FACTOR_4_5A)
#define CURR_SENSE_FACTOR_9A (3900 * CURR_SENSE_IS_FACTOR_9A)
typedef struct {
uint16_t acc_cooling;

17
Software/Code/Core/Inc/plausibility_check.h Normal file
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@ -0,0 +1,17 @@
/*
* plausibility_check.h
*
* Created on: Mar 18, 2025
* Author: janek
*/
#ifndef INC_PLAUSIBILITY_CHECK_H_
#define INC_PLAUSIBILITY_CHECK_H_
#include "current_monitoring.h"
#include "channel_control.h"
#include "can_communication.h"
void check_plausibility();
#endif /* INC_PLAUSIBILITY_CHECK_H_ */

1
Software/Code/Core/Inc/stm32f3xx_hal_conf.h
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@ -165,6 +165,7 @@
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SDADC_REGISTER_CALLBACKS 0U /* SDADC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */

46
Software/Code/Core/Src/can_communication.c
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@ -8,10 +8,13 @@
#include "can_communication.h"
#include "channel_control.h"
#include "current_monitoring.h"
#include "plausibility_check.h"
rx_status_frame rxstate = {};
volatile uint8_t canmsg_received = 0;
extern enable_gpios update_ports;
extern current_measurements current_measurements_adc_val;
extern uint8_t error_data[16];
extern uint32_t lastheartbeat;
@ -67,7 +70,7 @@ void can_sendloop(){
data[5] = current_measurements_adc_val.ebs3 & 0xFF;
data[6] = current_measurements_adc_val.drs >> 8;
data[7] = current_measurements_adc_val.drs & 0xFF;
ftcan_transmit(CUR_CHANNLES_3_ID, data, 8);
ftcan_transmit(CUR_CHANNELS_3_ID, data, 8);
break;
case 3:
@ -77,17 +80,54 @@ void can_sendloop(){
data[3] = current_measurements_adc_val.lvms_v & 0xFF;
data[4] = current_measurements_adc_val.asms_v >> 8;
data[5] = current_measurements_adc_val.asms_v & 0xFF;
data[6] = 0x01; // not used (transmits 313)
data[7] = 0x39; // not used (transmits 313)
data[6] = current_measurements_adc_val.epsc_precharge >> 8; // not used (transmits 313)
data[7] = current_measurements_adc_val.epsc_precharge & 0xFF; // not used (transmits 313)
ftcan_transmit(CUR_CHANNELS_4_ID, data, 8);
break;
default:
break;
}
additionaltxcounter = (additionaltxcounter + 1) % 4;
}
void can_error_report(){
static int error_loop = 0;
uint8_t data[8];
switch (error_loop){
case 0: // 1 = error 0 = no error
data[0] = error_data[0]; // SDC-Status
data[1] = error_data[1]; // power draw critical (550W)
data[2] = error_data[2]; // power limit (> 600W)
data[3] = error_data[3]; // acc-cooling false OFF
data[4] = error_data[4]; // ts-cooling false OFF
data[5] = error_data[5]; // drs false OFF
data[6] = error_data[6]; // acu false OFF
data[7] = error_data[7]; // epsc false OFF
ftcan_transmit(ERROR_ID, data, 8);
break;
case 1: // 3 = error 2 = no error
data[8] = error_data[8]; // inverter false OFF
data[9] = error_data[9]; // lidar false OFF
data[10] = error_data[10]; // misc false OFF
data[11] = error_data[11]; // always on false OFF
data[12] = error_data[12]; // sdc false OFF
data[13] = error_data[13]; // ebs1 false OFF
data[14] = error_data[14]; // ebs2 false OFF
data[15] = error_data[15]; // ebs3 false OFF
ftcan_transmit(ERROR_ID, data, 8);
break;
default:
break;
}
error_loop = (error_loop + 1) % 2;
}
void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){
canmsg_received = 1;
if((id == RX_STATUS_MSG_ID) && (datalen == 3)){

43
Software/Code/Core/Src/channel_control.c
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@ -6,42 +6,51 @@
*/
#include "channel_control.h"
#include "current_monitoring.h"
#include "main.h"
volatile enable_gpios enable;
extern enable_gpios update_ports;
extern current_measurements current_measurements_adc_val;
extern int inhibit_SDC;
extern int prev_epsc_state;
volatile int prev_epsc_state;
void ChannelControl_init(){
enable.porta.porta = 0;
enable.portb.portb = 0;
enable.portb.alwayson = 1;
ChannelControl_UpdateGPIOs(enable);
update_ports.porta.porta = 0;
update_ports.portb.portb = 0;
update_ports.portb.alwayson = 1;
ChannelControl_UpdateGPIOs(update_ports);
prev_epsc_state = 0;
}
void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){
UpdatePorts.portb.alwayson = 1;
if (inhibit_SDC == 1){
UpdatePorts.portb.sdc = 0;
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, 1);
}
HAL_GPIO_WritePin(IN1_GPIO_Port, IN1_Pin, (GPIO_PinState)UpdatePorts.porta.acc_cooling); // Acc-Cooling
HAL_GPIO_WritePin(IN1_GPIO_Port, IN1_Pin, (GPIO_PinState)UpdatePorts.porta.acc_cooling); // Acc-Cooling
HAL_GPIO_WritePin(IN2_GPIO_Port, IN2_Pin, (GPIO_PinState)UpdatePorts.porta.ts_cooling); // TS-Cooling
HAL_GPIO_WritePin(IN3_GPIO_Port, IN3_Pin, (GPIO_PinState)UpdatePorts.porta.drs); // DRS
HAL_GPIO_WritePin(IN4_GPIO_Port, IN4_Pin, (GPIO_PinState)UpdatePorts.porta.acu); // ACU
if (prev_epsc_state == 0 && ((UpdatePorts.porta.porta >> 4) & 1) == 1){ // will be replaced by precharge
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 1); // precharge activate
HAL_Delay(2000); // contiuosly read precharge voltage
HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // if precharge voltage > 95% 24V enable PROFET
HAL_Delay(100); // after few ms disengage precharge
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 0);
prev_epsc_state = UpdatePorts.porta.epsc;
HAL_GPIO_WritePin(IN3_GPIO_Port, IN3_Pin, (GPIO_PinState)UpdatePorts.porta.drs); // DRS
HAL_GPIO_WritePin(IN4_GPIO_Port, IN4_Pin, (GPIO_PinState)UpdatePorts.porta.acu); // ACU
if (prev_epsc_state == 0 && UpdatePorts.porta.epsc == 1){
HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 1); // enable precharge
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 1);
if (current_measurements_adc_val.epsc_precharge >= (0.95f * current_measurements_adc_val.asms_v)) { // precharge complete
HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // switch PROFET
HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // disengage precharge
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, 0);
prev_epsc_state = UpdatePorts.porta.epsc;
}
}
else {
if ((prev_epsc_state == 1 && UpdatePorts.porta.epsc == 0) || (prev_epsc_state == UpdatePorts.porta.epsc)){
HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // ensure precharge is disabled, when not needed or stopped
HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc);
prev_epsc_state = UpdatePorts.porta.epsc;
}
HAL_GPIO_WritePin(IN6_GPIO_Port, IN6_Pin, (GPIO_PinState)UpdatePorts.porta.inverter); // inverter
HAL_GPIO_WritePin(IN7_GPIO_Port, IN7_Pin, (GPIO_PinState)UpdatePorts.porta.lidar); // lidar
HAL_GPIO_WritePin(IN8_GPIO_Port, IN8_Pin, (GPIO_PinState)UpdatePorts.porta.misc); // MISC

41
Software/Code/Core/Src/current_monitoring.c
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@ -7,14 +7,15 @@
#include "current_monitoring.h"
#include "main.h"
#include "plausibility_check.h"
volatile union adc1_channels {
struct {
uint16_t isense11; // ebs1, ebs2, ebs3 (DSEL0, DSEL1)
uint16_t lvms_vsense; // LVMS-Vsense
uint16_t isense1; // acc-cooling
uint16_t isense2; // ts-cooling
uint16_t isense9; // always on
uint16_t isense11; // ebs1, ebs2, ebs3 (DSEL0, DSEL1)
uint16_t asms_vsense; // ASMS-Vsense
uint16_t isense10; // sdc
uint16_t isense6; // inverter
@ -48,8 +49,8 @@ void current_monitor_init(ADC_HandleTypeDef* hadc1, ADC_HandleTypeDef* hadc2, TI
adc1 = hadc1;
adc2 = hadc2;
HAL_TIM_Base_Start(trigtim);
HAL_ADC_Start_DMA(hadc1, (uint32_t*)adc_channels1.adcbuffer, 6);
HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 5);
HAL_ADC_Start_DMA(hadc1, (uint32_t*)adc_channels1.adcbuffer, 8);
HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 6);
}
uint8_t current_monitor_checklimits() {return 0;} // TODO: implement properly
@ -57,38 +58,40 @@ uint8_t current_monitor_checklimits() {return 0;} // TODO: implement properly
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) {
if (hadc == adc1){
if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_RESET){
current_measurement_adc_val.ebs1 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
current_measurements_adc_val.ebs1 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
valve2 = GPIO_PIN_SET;
}
if (valve2 == GPIO_PIN_SET && valve3 == GPIO_PIN_RESET){
current_measurement_adc_val.ebs2 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
current_measurements_adc_val.ebs2 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
valve2 = GPIO_PIN_RESET;
valve3 = GPIO_PIN_SET;
}
if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_SET){
current_measurement_adc_val.ebs3 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
current_measurements_adc_val.ebs3 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
valve3 = GPIO_PIN_RESET;
}
}
else {
current_measurement_adc_val.lvms_v = adc_channels1.adcbank1.lvms_vsense * LV_SENSE_FACTOR;
current_measurement_adc_val.acc_cooling = adc_channels1.adcbank1.isense1 * CURR_SENSE_FACTOR_9A;
current_measurement_adc_val.ts_cooling = adc_channels1.adcbank1.isense2 * CURR_SENSE_FACTOR_9A;
current_measurement_adc_val.alwayson = adc_channels1.adcbank1.isense9 * CURR_SENSE_FACTOR_9A;
current_measurement_adc_val.asms_v = adc_channels1.adcbank1.asms_vsense * LV_SENSE_FACTOR;
current_measurement_adc_val.sdc = adc_channels1.adcbank1.isense10 * CURR_SENSE_FACTOR_4_5A;
current_measurement_adc_val.inverter = adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_9A;
current_measurements_adc_val.lvms_v = adc_channels1.adcbank1.lvms_vsense * LV_SENSE_FACTOR;
current_measurements_adc_val.acc_cooling = adc_channels1.adcbank1.isense1 * CURR_SENSE_FACTOR_9A;
current_measurements_adc_val.ts_cooling = adc_channels1.adcbank1.isense2 * CURR_SENSE_FACTOR_9A;
current_measurements_adc_val.alwayson = adc_channels1.adcbank1.isense9 * CURR_SENSE_FACTOR_9A;
current_measurements_adc_val.asms_v = adc_channels1.adcbank1.asms_vsense * LV_SENSE_FACTOR;
current_measurements_adc_val.sdc = adc_channels1.adcbank1.isense10 * CURR_SENSE_FACTOR_4_5A;
current_measurements_adc_val.inverter = adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_9A;
HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3);
HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2);
}
if (hadc == adc2){
current_measurement_adc_val.drs = adc_channels2.adcbank2.isense3 * CURR_SENSE_FACTOR_4_5A;
current_measurement_adc_val.misc = adc_channels2.adcbank2.isense8 * CURR_SENSE_FACTOR_4_5A;
current_measurement_adc_val.acu = adc_channels2.adcbank2.isense4 * CURR_SENSE_FACTOR_9A;
current_measurement_adc_val.epsc = adc_channels2.adcbank2.isense5 * CURR_SENSE_FACTOR_9A;
current_measurement_adc_val.epsc_precharge = adc_channels2.adcbank2.pc_read * PC_VSENSE_FACTOR;
current_measurement_adc_val.lidar = adc_channels2.adcbank2.isense7 * CURR_SENSE_FACTOR_4_5A;
current_measurements_adc_val.drs = adc_channels2.adcbank2.isense3 * CURR_SENSE_FACTOR_4_5A;
current_measurements_adc_val.misc = adc_channels2.adcbank2.isense8 * CURR_SENSE_FACTOR_4_5A;
current_measurements_adc_val.acu = adc_channels2.adcbank2.isense4 * CURR_SENSE_FACTOR_9A;
current_measurements_adc_val.epsc = adc_channels2.adcbank2.isense5 * CURR_SENSE_FACTOR_9A;
current_measurements_adc_val.epsc_precharge = adc_channels2.adcbank2.pc_read * LV_SENSE_FACTOR;
current_measurements_adc_val.lidar = adc_channels2.adcbank2.isense7 * CURR_SENSE_FACTOR_4_5A;
}
check_plausibility();
}

27
Software/Code/Core/Src/main.c
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@ -23,6 +23,7 @@
/* USER CODE BEGIN Includes */
#include "can_communication.h"
#include "channel_control.h"
//#include "plausibility_check.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -80,7 +81,6 @@ extern volatile uint8_t canmsg_received;
volatile enable_gpios update_ports;
uint32_t lastheartbeat;
int inhibit_SDC; // wenn =1 ist es unmoeglich den SDC zu schliessen
volatile int prev_epsc_state; // used for precharge
/* USER CODE END 0 */
/**
@ -168,16 +168,20 @@ int main(void)
if ((HAL_GetTick() - lasttick) > 100u){
lasttick = HAL_GetTick();
can_sendloop();
//can_error_report();
}
if (((HAL_GetTick() - lastheartbeat) > 125U) && (HAL_GetTick() > 1000U)) {
if (((HAL_GetTick() - lastheartbeat) > 200U) && (HAL_GetTick() > 1000U)) {
inhibit_SDC = 1;
}
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (GPIO_PinState)!update_ports.portb.sdc); // indicates open SDC
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (GPIO_PinState)inhibit_SDC); // indicates watchdog-status
// overcurrent check (wenn funktioniert, LED schalten)
ChannelControl_UpdateGPIOs(update_ports);
current_monitor_checklimits(); // currently not implemented
//check_plausibility();
}
/* USER CODE END 3 */
}
@ -279,10 +283,10 @@ static void MX_ADC1_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_2;
sConfig.Channel = ADC_CHANNEL_5;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
sConfig.SamplingTime = ADC_SAMPLETIME_61CYCLES_5;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
@ -292,7 +296,7 @@ static void MX_ADC1_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
sConfig.Channel = ADC_CHANNEL_6;
sConfig.Rank = ADC_REGULAR_RANK_2;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
@ -301,6 +305,7 @@ static void MX_ADC1_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_2;
sConfig.Rank = ADC_REGULAR_RANK_3;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
@ -309,6 +314,7 @@ static void MX_ADC1_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = ADC_REGULAR_RANK_4;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
@ -317,6 +323,7 @@ static void MX_ADC1_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
sConfig.Rank = ADC_REGULAR_RANK_5;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
@ -325,6 +332,7 @@ static void MX_ADC1_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_1;
sConfig.Rank = ADC_REGULAR_RANK_6;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
@ -333,6 +341,7 @@ static void MX_ADC1_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_7;
sConfig.Rank = ADC_REGULAR_RANK_7;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
@ -341,6 +350,7 @@ static void MX_ADC1_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_8;
sConfig.Rank = ADC_REGULAR_RANK_8;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
@ -396,7 +406,7 @@ static void MX_ADC2_Init(void)
sConfig.Channel = ADC_CHANNEL_1;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
sConfig.SamplingTime = ADC_SAMPLETIME_61CYCLES_5;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
@ -406,6 +416,7 @@ static void MX_ADC2_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_2;
sConfig.Rank = ADC_REGULAR_RANK_2;
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
{
@ -414,6 +425,7 @@ static void MX_ADC2_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
sConfig.Rank = ADC_REGULAR_RANK_3;
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
{
@ -422,6 +434,7 @@ static void MX_ADC2_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
sConfig.Rank = ADC_REGULAR_RANK_4;
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
{
@ -430,6 +443,7 @@ static void MX_ADC2_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_5;
sConfig.Rank = ADC_REGULAR_RANK_5;
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
{
@ -438,6 +452,7 @@ static void MX_ADC2_Init(void)
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_9;
sConfig.Rank = ADC_REGULAR_RANK_6;
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
{

113
Software/Code/Core/Src/plausibility_check.c Normal file
View File

@ -0,0 +1,113 @@
/*
* plausibility_check.c
*
* Created on: Mar 18, 2025
* Author: janek
*/
#include "plausibility_check.h"
extern enable_gpios update_ports;
extern current_measurements current_measurements_adc_val;
volatile uint8_t error_data[16];
void check_plausibility() {
if (!update_ports.portb.sdc) {error_data[0] = 1;}
else {error_data[0] = 0;}
if (update_ports.porta.acc_cooling == 1 && current_measurements_adc_val.acc_cooling == 0) {
error_data[3] = 1;
}
else {
error_data[3] = 0;
}
if (update_ports.porta.ts_cooling == 1 && current_measurements_adc_val.ts_cooling == 0) {
error_data[4] = 1;
}
else {
error_data[4] = 0;
}
if (update_ports.porta.drs == 1 && current_measurements_adc_val.drs == 0) {
error_data[5] = 1;
}
else {
error_data[5] = 0;
}
if (update_ports.porta.acu == 1 && current_measurements_adc_val.acu == 0) {
error_data[6] = 1;
}
else {
error_data[6] = 0;
}
if (update_ports.porta.epsc == 1 && current_measurements_adc_val.epsc == 0) {
error_data[7] = 1;
}
else {
error_data[7] = 0;
}
if (update_ports.porta.inverter == 1 && current_measurements_adc_val.inverter == 0) {
error_data[8] = 3;
}
else {
error_data[8] = 2;
}
if (update_ports.porta.lidar == 1 && current_measurements_adc_val.lidar == 0) {
error_data[9] = 3;
}
else {
error_data[9] = 2;
}
if (update_ports.porta.misc == 1 && current_measurements_adc_val.misc == 0) {
error_data[10] = 3;
}
else {
error_data[10] = 2;
}
if (update_ports.portb.alwayson == 1 && current_measurements_adc_val.alwayson == 0) {
error_data[11] = 3;
}
else {
error_data[11] = 2;
}
if (update_ports.portb.sdc == 1 && current_measurements_adc_val.sdc == 0) {
error_data[12] = 3;
}
else {
error_data[12] = 2;
}
if (update_ports.portb.ebs1 == 1 && current_measurements_adc_val.ebs1 == 0) {
error_data[13] = 3;
}
else {
error_data[13] = 2;
}
if (update_ports.portb.ebs2 == 1 && current_measurements_adc_val.ebs2 == 0) {
error_data[14] = 3;
}
else {
error_data[14] = 2;
}
if (update_ports.portb.ebs3 == 1 && current_measurements_adc_val.ebs3 == 0) {
error_data[15] = 3;
}
else {
error_data[15] = 2;
}
}

3
Software/Code/Core/Src/stm32f3xx_hal_msp.c
View File

@ -342,6 +342,7 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
/* USER CODE BEGIN CAN_MspInit 1 */
/* USER CODE END CAN_MspInit 1 */
}
}
@ -399,6 +400,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
/* USER CODE BEGIN TIM6_MspInit 1 */
/* USER CODE END TIM6_MspInit 1 */
}
}
@ -460,6 +462,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
/* USER CODE BEGIN UART4_MspInit 1 */
/* USER CODE END UART4_MspInit 1 */
}
}

7
Software/Code/Debug/Core/Src/can_communication.cyclo
View File

@ -1,3 +1,4 @@
../Core/Src/can_communication.c:20:6:can_init 1
../Core/Src/can_communication.c:25:6:can_sendloop 1
../Core/Src/can_communication.c:36:6:ftcan_msg_received_cb 4
../Core/Src/can_communication.c:23:6:can_init 1
../Core/Src/can_communication.c:28:6:can_sendloop 5
../Core/Src/can_communication.c:95:6:can_error_report 3
../Core/Src/can_communication.c:131:6:ftcan_msg_received_cb 4

8
Software/Code/Debug/Core/Src/can_communication.d
View File

@ -33,7 +33,9 @@ Core/Src/can_communication.o: ../Core/Src/can_communication.c \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h \
../Core/Inc/can_halal.h ../Core/Inc/channel_control.h
../Core/Inc/can_halal.h ../Core/Inc/current_monitoring.h \
../Core/Inc/channel_control.h ../Core/Inc/current_monitoring.h \
../Core/Inc/plausibility_check.h ../Core/Inc/can_communication.h
../Core/Inc/can_communication.h:
../Core/Inc/channel_control.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h:
@ -70,4 +72,8 @@ Core/Src/can_communication.o: ../Core/Src/can_communication.c \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h:
../Core/Inc/can_halal.h:
../Core/Inc/current_monitoring.h:
../Core/Inc/channel_control.h:
../Core/Inc/current_monitoring.h:
../Core/Inc/plausibility_check.h:
../Core/Inc/can_communication.h:

BIN
Software/Code/Debug/Core/Src/can_communication.o
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Binary file not shown.

7
Software/Code/Debug/Core/Src/can_communication.su
View File

@ -1,3 +1,4 @@
../Core/Src/can_communication.c:20:6:can_init 16 static
../Core/Src/can_communication.c:25:6:can_sendloop 16 static
../Core/Src/can_communication.c:36:6:ftcan_msg_received_cb 24 static
../Core/Src/can_communication.c:23:6:can_init 16 static
../Core/Src/can_communication.c:28:6:can_sendloop 24 static
../Core/Src/can_communication.c:95:6:can_error_report 16 static
../Core/Src/can_communication.c:131:6:ftcan_msg_received_cb 24 static

BIN
Software/Code/Debug/Core/Src/can_halal.o
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Binary file not shown.

4
Software/Code/Debug/Core/Src/channel_control.cyclo
View File

@ -1,2 +1,2 @@
../Core/Src/channel_control.c:16:6:ChannelControl_init 1
../Core/Src/channel_control.c:23:6:ChannelControl_UpdateGPIOs 4
../Core/Src/channel_control.c:18:6:ChannelControl_init 1
../Core/Src/channel_control.c:27:6:ChannelControl_UpdateGPIOs 8

3
Software/Code/Debug/Core/Src/channel_control.d
View File

@ -33,7 +33,7 @@ Core/Src/channel_control.o: ../Core/Src/channel_control.c \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h \
../Core/Inc/main.h
../Core/Inc/current_monitoring.h ../Core/Inc/main.h
../Core/Inc/channel_control.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h:
../Core/Inc/stm32f3xx_hal_conf.h:
@ -68,4 +68,5 @@ Core/Src/channel_control.o: ../Core/Src/channel_control.c \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h:
../Core/Inc/current_monitoring.h:
../Core/Inc/main.h:

BIN
Software/Code/Debug/Core/Src/channel_control.o
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Binary file not shown.

4
Software/Code/Debug/Core/Src/channel_control.su
View File

@ -1,2 +1,2 @@
../Core/Src/channel_control.c:16:6:ChannelControl_init 8 static
../Core/Src/channel_control.c:23:6:ChannelControl_UpdateGPIOs 16 static
../Core/Src/channel_control.c:18:6:ChannelControl_init 8 static
../Core/Src/channel_control.c:27:6:ChannelControl_UpdateGPIOs 16 static

3
Software/Code/Debug/Core/Src/current_monitoring.cyclo Normal file
View File

@ -0,0 +1,3 @@
../Core/Src/current_monitoring.c:46:6:current_monitor_init 1
../Core/Src/current_monitoring.c:56:9:current_monitor_checklimits 1
../Core/Src/current_monitoring.c:58:6:HAL_ADC_ConvCpltCallback 9

78
Software/Code/Debug/Core/Src/current_monitoring.d Normal file
View File

@ -0,0 +1,78 @@
Core/Src/current_monitoring.o: ../Core/Src/current_monitoring.c \
../Core/Inc/current_monitoring.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \
../Core/Inc/stm32f3xx_hal_conf.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \
../Drivers/CMSIS/Include/core_cm4.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv7.h \
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h \
../Core/Inc/main.h ../Core/Inc/plausibility_check.h \
../Core/Inc/current_monitoring.h ../Core/Inc/channel_control.h \
../Core/Inc/can_communication.h ../Core/Inc/can_halal.h
../Core/Inc/current_monitoring.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h:
../Core/Inc/stm32f3xx_hal_conf.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h:
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h:
../Drivers/CMSIS/Include/core_cm4.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv7.h:
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h:
../Core/Inc/main.h:
../Core/Inc/plausibility_check.h:
../Core/Inc/current_monitoring.h:
../Core/Inc/channel_control.h:
../Core/Inc/can_communication.h:
../Core/Inc/can_halal.h:

BIN
Software/Code/Debug/Core/Src/current_monitoring.o Normal file
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3
Software/Code/Debug/Core/Src/current_monitoring.su Normal file
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@ -0,0 +1,3 @@
../Core/Src/current_monitoring.c:46:6:current_monitor_init 24 static
../Core/Src/current_monitoring.c:56:9:current_monitor_checklimits 4 static
../Core/Src/current_monitoring.c:58:6:HAL_ADC_ConvCpltCallback 16 static

20
Software/Code/Debug/Core/Src/main.cyclo
View File

@ -1,10 +1,10 @@
../Core/Src/main.c:89:5:main 5
../Core/Src/main.c:186:6:SystemClock_Config 4
../Core/Src/main.c:234:13:MX_ADC1_Init 11
../Core/Src/main.c:357:13:MX_ADC2_Init 8
../Core/Src/main.c:454:13:MX_CAN_Init 2
../Core/Src/main.c:491:13:MX_TIM6_Init 3
../Core/Src/main.c:529:13:MX_UART4_Init 2
../Core/Src/main.c:562:13:MX_DMA_Init 1
../Core/Src/main.c:584:13:MX_GPIO_Init 1
../Core/Src/main.c:647:6:Error_Handler 1
../Core/Src/main.c:90:5:main 5
../Core/Src/main.c:193:6:SystemClock_Config 4
../Core/Src/main.c:241:13:MX_ADC1_Init 11
../Core/Src/main.c:370:13:MX_ADC2_Init 8
../Core/Src/main.c:472:13:MX_CAN_Init 2
../Core/Src/main.c:509:13:MX_TIM6_Init 3
../Core/Src/main.c:547:13:MX_UART4_Init 2
../Core/Src/main.c:580:13:MX_DMA_Init 1
../Core/Src/main.c:602:13:MX_GPIO_Init 1
../Core/Src/main.c:665:6:Error_Handler 1

4
Software/Code/Debug/Core/Src/main.d
View File

@ -33,7 +33,8 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h \
../Core/Inc/can_communication.h ../Core/Inc/channel_control.h \
../Core/Inc/can_halal.h ../Core/Inc/channel_control.h
../Core/Inc/can_halal.h ../Core/Inc/current_monitoring.h \
../Core/Inc/channel_control.h
../Core/Inc/main.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h:
../Core/Inc/stm32f3xx_hal_conf.h:
@ -71,4 +72,5 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
../Core/Inc/can_communication.h:
../Core/Inc/channel_control.h:
../Core/Inc/can_halal.h:
../Core/Inc/current_monitoring.h:
../Core/Inc/channel_control.h:

BIN
Software/Code/Debug/Core/Src/main.o
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20
Software/Code/Debug/Core/Src/main.su
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@ -1,10 +1,10 @@
../Core/Src/main.c:89:5:main 16 static
../Core/Src/main.c:186:6:SystemClock_Config 120 static
../Core/Src/main.c:234:13:MX_ADC1_Init 48 static
../Core/Src/main.c:357:13:MX_ADC2_Init 32 static
../Core/Src/main.c:454:13:MX_CAN_Init 8 static
../Core/Src/main.c:491:13:MX_TIM6_Init 24 static
../Core/Src/main.c:529:13:MX_UART4_Init 8 static
../Core/Src/main.c:562:13:MX_DMA_Init 16 static
../Core/Src/main.c:584:13:MX_GPIO_Init 48 static
../Core/Src/main.c:647:6:Error_Handler 4 static,ignoring_inline_asm
../Core/Src/main.c:90:5:main 16 static
../Core/Src/main.c:193:6:SystemClock_Config 120 static
../Core/Src/main.c:241:13:MX_ADC1_Init 48 static
../Core/Src/main.c:370:13:MX_ADC2_Init 32 static
../Core/Src/main.c:472:13:MX_CAN_Init 8 static
../Core/Src/main.c:509:13:MX_TIM6_Init 24 static
../Core/Src/main.c:547:13:MX_UART4_Init 8 static
../Core/Src/main.c:580:13:MX_DMA_Init 16 static
../Core/Src/main.c:602:13:MX_GPIO_Init 48 static
../Core/Src/main.c:665:6:Error_Handler 4 static,ignoring_inline_asm

1
Software/Code/Debug/Core/Src/plausibility_check.cyclo Normal file
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@ -0,0 +1 @@
../Core/Src/plausibility_check.c:13:6:check_plausibility 28

75
Software/Code/Debug/Core/Src/plausibility_check.d Normal file
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@ -0,0 +1,75 @@
Core/Src/plausibility_check.o: ../Core/Src/plausibility_check.c \
../Core/Inc/plausibility_check.h ../Core/Inc/current_monitoring.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \
../Core/Inc/stm32f3xx_hal_conf.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \
../Drivers/CMSIS/Include/core_cm4.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv7.h \
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h \
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h \
../Core/Inc/channel_control.h ../Core/Inc/can_communication.h \
../Core/Inc/can_halal.h
../Core/Inc/plausibility_check.h:
../Core/Inc/current_monitoring.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h:
../Core/Inc/stm32f3xx_hal_conf.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h:
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h:
../Drivers/CMSIS/Include/core_cm4.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv7.h:
../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h:
../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h:
../Core/Inc/channel_control.h:
../Core/Inc/can_communication.h:
../Core/Inc/can_halal.h:

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1
Software/Code/Debug/Core/Src/plausibility_check.su Normal file
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@ -0,0 +1 @@
../Core/Src/plausibility_check.c:13:6:check_plausibility 4 static

10
Software/Code/Debug/Core/Src/stm32f3xx_hal_msp.cyclo
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@ -2,8 +2,8 @@
../Core/Src/stm32f3xx_hal_msp.c:91:6:HAL_ADC_MspInit 7
../Core/Src/stm32f3xx_hal_msp.c:221:6:HAL_ADC_MspDeInit 5
../Core/Src/stm32f3xx_hal_msp.c:314:6:HAL_CAN_MspInit 2
../Core/Src/stm32f3xx_hal_msp.c:355:6:HAL_CAN_MspDeInit 2
../Core/Src/stm32f3xx_hal_msp.c:387:6:HAL_TIM_Base_MspInit 2
../Core/Src/stm32f3xx_hal_msp.c:412:6:HAL_TIM_Base_MspDeInit 2
../Core/Src/stm32f3xx_hal_msp.c:437:6:HAL_UART_MspInit 2
../Core/Src/stm32f3xx_hal_msp.c:473:6:HAL_UART_MspDeInit 2
../Core/Src/stm32f3xx_hal_msp.c:356:6:HAL_CAN_MspDeInit 2
../Core/Src/stm32f3xx_hal_msp.c:388:6:HAL_TIM_Base_MspInit 2
../Core/Src/stm32f3xx_hal_msp.c:414:6:HAL_TIM_Base_MspDeInit 2
../Core/Src/stm32f3xx_hal_msp.c:439:6:HAL_UART_MspInit 2
../Core/Src/stm32f3xx_hal_msp.c:476:6:HAL_UART_MspDeInit 2

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10
Software/Code/Debug/Core/Src/stm32f3xx_hal_msp.su
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@ -2,8 +2,8 @@
../Core/Src/stm32f3xx_hal_msp.c:91:6:HAL_ADC_MspInit 64 static
../Core/Src/stm32f3xx_hal_msp.c:221:6:HAL_ADC_MspDeInit 16 static
../Core/Src/stm32f3xx_hal_msp.c:314:6:HAL_CAN_MspInit 48 static
../Core/Src/stm32f3xx_hal_msp.c:355:6:HAL_CAN_MspDeInit 16 static
../Core/Src/stm32f3xx_hal_msp.c:387:6:HAL_TIM_Base_MspInit 24 static
../Core/Src/stm32f3xx_hal_msp.c:412:6:HAL_TIM_Base_MspDeInit 16 static
../Core/Src/stm32f3xx_hal_msp.c:437:6:HAL_UART_MspInit 48 static
../Core/Src/stm32f3xx_hal_msp.c:473:6:HAL_UART_MspDeInit 16 static
../Core/Src/stm32f3xx_hal_msp.c:356:6:HAL_CAN_MspDeInit 16 static
../Core/Src/stm32f3xx_hal_msp.c:388:6:HAL_TIM_Base_MspInit 24 static
../Core/Src/stm32f3xx_hal_msp.c:414:6:HAL_TIM_Base_MspDeInit 16 static
../Core/Src/stm32f3xx_hal_msp.c:439:6:HAL_UART_MspInit 48 static
../Core/Src/stm32f3xx_hal_msp.c:476:6:HAL_UART_MspDeInit 16 static

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8
Software/Code/Debug/Core/Src/subdir.mk
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@ -8,7 +8,9 @@ C_SRCS += \
../Core/Src/can_communication.c \
../Core/Src/can_halal.c \
../Core/Src/channel_control.c \
../Core/Src/current_monitoring.c \
../Core/Src/main.c \
../Core/Src/plausibility_check.c \
../Core/Src/stm32f3xx_hal_msp.c \
../Core/Src/stm32f3xx_it.c \
../Core/Src/syscalls.c \
@ -19,7 +21,9 @@ OBJS += \
./Core/Src/can_communication.o \
./Core/Src/can_halal.o \
./Core/Src/channel_control.o \
./Core/Src/current_monitoring.o \
./Core/Src/main.o \
./Core/Src/plausibility_check.o \
./Core/Src/stm32f3xx_hal_msp.o \
./Core/Src/stm32f3xx_it.o \
./Core/Src/syscalls.o \
@ -30,7 +34,9 @@ C_DEPS += \
./Core/Src/can_communication.d \
./Core/Src/can_halal.d \
./Core/Src/channel_control.d \
./Core/Src/current_monitoring.d \
./Core/Src/main.d \
./Core/Src/plausibility_check.d \
./Core/Src/stm32f3xx_hal_msp.d \
./Core/Src/stm32f3xx_it.d \
./Core/Src/syscalls.d \
@ -45,7 +51,7 @@ Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
clean: clean-Core-2f-Src
clean-Core-2f-Src:
-$(RM) ./Core/Src/can_communication.cyclo ./Core/Src/can_communication.d ./Core/Src/can_communication.o ./Core/Src/can_communication.su ./Core/Src/can_halal.cyclo ./Core/Src/can_halal.d ./Core/Src/can_halal.o ./Core/Src/can_halal.su ./Core/Src/channel_control.cyclo ./Core/Src/channel_control.d ./Core/Src/channel_control.o ./Core/Src/channel_control.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f3xx_hal_msp.cyclo ./Core/Src/stm32f3xx_hal_msp.d ./Core/Src/stm32f3xx_hal_msp.o ./Core/Src/stm32f3xx_hal_msp.su ./Core/Src/stm32f3xx_it.cyclo ./Core/Src/stm32f3xx_it.d ./Core/Src/stm32f3xx_it.o ./Core/Src/stm32f3xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f3xx.cyclo ./Core/Src/system_stm32f3xx.d ./Core/Src/system_stm32f3xx.o ./Core/Src/system_stm32f3xx.su
-$(RM) ./Core/Src/can_communication.cyclo ./Core/Src/can_communication.d ./Core/Src/can_communication.o ./Core/Src/can_communication.su ./Core/Src/can_halal.cyclo ./Core/Src/can_halal.d ./Core/Src/can_halal.o ./Core/Src/can_halal.su ./Core/Src/channel_control.cyclo ./Core/Src/channel_control.d ./Core/Src/channel_control.o ./Core/Src/channel_control.su ./Core/Src/current_monitoring.cyclo ./Core/Src/current_monitoring.d ./Core/Src/current_monitoring.o ./Core/Src/current_monitoring.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/plausibility_check.cyclo ./Core/Src/plausibility_check.d ./Core/Src/plausibility_check.o ./Core/Src/plausibility_check.su ./Core/Src/stm32f3xx_hal_msp.cyclo ./Core/Src/stm32f3xx_hal_msp.d ./Core/Src/stm32f3xx_hal_msp.o ./Core/Src/stm32f3xx_hal_msp.su ./Core/Src/stm32f3xx_it.cyclo ./Core/Src/stm32f3xx_it.d ./Core/Src/stm32f3xx_it.o ./Core/Src/stm32f3xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f3xx.cyclo ./Core/Src/system_stm32f3xx.d ./Core/Src/system_stm32f3xx.o ./Core/Src/system_stm32f3xx.su
.PHONY: clean-Core-2f-Src

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@ -21,22 +21,22 @@
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4585:19:HAL_ADCEx_MultiModeStart_DMA 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4725:19:HAL_ADCEx_MultiModeStop_DMA 14
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4850:10:HAL_ADCEx_MultiModeGetValue 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4901:10:HAL_ADCEx_InjectedGetValue 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5015:19:HAL_ADCEx_RegularStop 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5089:19:HAL_ADCEx_RegularStop_IT 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5169:19:HAL_ADCEx_RegularStop_DMA 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5281:19:HAL_ADCEx_RegularMultiModeStop_DMA 15
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5431:13:HAL_ADCEx_InjectedConvCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5454:13:HAL_ADCEx_InjectedQueueOverflowCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5470:13:HAL_ADCEx_LevelOutOfWindow2Callback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5485:13:HAL_ADCEx_LevelOutOfWindow3Callback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5548:19:HAL_ADC_ConfigChannel 41
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:6014:19:HAL_ADCEx_InjectedConfigChannel 49
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:6766:19:HAL_ADC_AnalogWDGConfig 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7051:19:HAL_ADCEx_MultiModeConfigChannel 19
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7181:13:ADC_DMAConvCplt 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7228:13:ADC_DMAHalfConvCplt 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7246:13:ADC_DMAError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7276:26:ADC_Enable 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7334:26:ADC_Disable 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7397:26:ADC_ConversionStop 18
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4904:10:HAL_ADCEx_InjectedGetValue 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5018:19:HAL_ADCEx_RegularStop 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5092:19:HAL_ADCEx_RegularStop_IT 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5172:19:HAL_ADCEx_RegularStop_DMA 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5284:19:HAL_ADCEx_RegularMultiModeStop_DMA 15
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5434:13:HAL_ADCEx_InjectedConvCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5457:13:HAL_ADCEx_InjectedQueueOverflowCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5473:13:HAL_ADCEx_LevelOutOfWindow2Callback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5488:13:HAL_ADCEx_LevelOutOfWindow3Callback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5551:19:HAL_ADC_ConfigChannel 41
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:6017:19:HAL_ADCEx_InjectedConfigChannel 49
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:6769:19:HAL_ADC_AnalogWDGConfig 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7054:19:HAL_ADCEx_MultiModeConfigChannel 19
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7184:13:ADC_DMAConvCplt 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7231:13:ADC_DMAHalfConvCplt 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7249:13:ADC_DMAError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7279:26:ADC_Enable 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7337:26:ADC_Disable 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7400:26:ADC_ConversionStop 18

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@ -21,22 +21,22 @@
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4585:19:HAL_ADCEx_MultiModeStart_DMA 112 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4725:19:HAL_ADCEx_MultiModeStop_DMA 104 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4850:10:HAL_ADCEx_MultiModeGetValue 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4901:10:HAL_ADCEx_InjectedGetValue 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5015:19:HAL_ADCEx_RegularStop 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5089:19:HAL_ADCEx_RegularStop_IT 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5169:19:HAL_ADCEx_RegularStop_DMA 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5281:19:HAL_ADCEx_RegularMultiModeStop_DMA 104 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5431:13:HAL_ADCEx_InjectedConvCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5454:13:HAL_ADCEx_InjectedQueueOverflowCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5470:13:HAL_ADCEx_LevelOutOfWindow2Callback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5485:13:HAL_ADCEx_LevelOutOfWindow3Callback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5548:19:HAL_ADC_ConfigChannel 112 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:6014:19:HAL_ADCEx_InjectedConfigChannel 120 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:6766:19:HAL_ADC_AnalogWDGConfig 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7051:19:HAL_ADCEx_MultiModeConfigChannel 104 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7181:13:ADC_DMAConvCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7228:13:ADC_DMAHalfConvCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7246:13:ADC_DMAError 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7276:26:ADC_Enable 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7334:26:ADC_Disable 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7397:26:ADC_ConversionStop 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:4904:10:HAL_ADCEx_InjectedGetValue 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5018:19:HAL_ADCEx_RegularStop 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5092:19:HAL_ADCEx_RegularStop_IT 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5172:19:HAL_ADCEx_RegularStop_DMA 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5284:19:HAL_ADCEx_RegularMultiModeStop_DMA 104 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5434:13:HAL_ADCEx_InjectedConvCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5457:13:HAL_ADCEx_InjectedQueueOverflowCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5473:13:HAL_ADCEx_LevelOutOfWindow2Callback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5488:13:HAL_ADCEx_LevelOutOfWindow3Callback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:5551:19:HAL_ADC_ConfigChannel 112 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:6017:19:HAL_ADCEx_InjectedConfigChannel 120 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:6769:19:HAL_ADC_AnalogWDGConfig 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7054:19:HAL_ADCEx_MultiModeConfigChannel 104 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7184:13:ADC_DMAConvCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7231:13:ADC_DMAHalfConvCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7249:13:ADC_DMAError 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7279:26:ADC_Enable 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7337:26:ADC_Disable 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c:7400:26:ADC_ConversionStop 32 static

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@ -1,36 +1,36 @@
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:274:19:HAL_CAN_Init 13
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:459:19:HAL_CAN_DeInit 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:506:13:HAL_CAN_MspInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:522:13:HAL_CAN_MspDeInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:839:19:HAL_CAN_ConfigFilter 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:989:19:HAL_CAN_Start 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1041:19:HAL_CAN_Stop 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1096:19:HAL_CAN_RequestSleep 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1127:19:HAL_CAN_WakeUp 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1176:10:HAL_CAN_IsSleepActive 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1207:19:HAL_CAN_AddTxMessage 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1307:19:HAL_CAN_AbortTxRequest 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1356:10:HAL_CAN_GetTxMailboxesFreeLevel 6
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@ -56,66 +56,66 @@
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2480:13:HAL_UART_ErrorCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2495:13:HAL_UART_AbortCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2510:13:HAL_UART_AbortTransmitCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2525:13:HAL_UART_AbortReceiveCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2542:13:HAL_UARTEx_RxEventCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2590:6:HAL_UART_ReceiverTimeout_Config 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2602:19:HAL_UART_EnableReceiverTimeout 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2633:19:HAL_UART_DisableReceiverTimeout 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2664:19:HAL_MultiProcessor_EnableMuteMode 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2684:19:HAL_MultiProcessor_DisableMuteMode 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2704:6:HAL_MultiProcessor_EnterMuteMode 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2714:19:HAL_HalfDuplex_EnableTransmitter 64 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2737:19:HAL_HalfDuplex_EnableReceiver 64 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2761:19:HAL_LIN_SendBreak 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2806:23:HAL_UART_GetState 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2822:10:HAL_UART_GetError 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2866:19:UART_SetConfig 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3010:6:UART_AdvFeatureConfig 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3084:19:UART_CheckIdleState 104 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3153:19:UART_WaitOnFlagUntilTimeout 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3221:19:UART_Start_Receive_IT 96 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3270:19:UART_Start_Receive_DMA 96 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3327:13:UART_EndTxTransfer 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3342:13:UART_EndRxTransfer 88 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3368:13:UART_DMATransmitCplt 72 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3402:13:UART_DMATxHalfCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3420:13:UART_DMAReceiveCplt 120 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3481:13:UART_DMARxHalfCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3519:13:UART_DMAError 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3559:13:UART_DMAAbortOnError 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3582:13:UART_DMATxAbortCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3632:13:UART_DMARxAbortCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3684:13:UART_DMATxOnlyAbortCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3712:13:UART_DMARxOnlyAbortCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3745:13:UART_TxISR_8BIT 64 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3774:13:UART_TxISR_16BIT 72 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3806:13:UART_EndTransmit_IT 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3831:13:UART_RxISR_8BIT 120 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3919:13:UART_RxISR_16BIT 120 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:364:19:HAL_HalfDuplex_Init 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:439:19:HAL_LIN_Init 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:538:19:HAL_MultiProcessor_Init 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:614:19:HAL_UART_DeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:661:13:HAL_UART_MspInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:676:13:HAL_UART_MspDeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1076:19:HAL_UART_Transmit 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1162:19:HAL_UART_Receive 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1246:19:HAL_UART_Transmit_IT 48 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1295:19:HAL_UART_Receive_IT 48 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1333:19:HAL_UART_Transmit_DMA 48 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1403:19:HAL_UART_Receive_DMA 48 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1436:19:HAL_UART_DMAPause 120 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1466:19:HAL_UART_DMAResume 112 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1497:19:HAL_UART_DMAStop 72 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1572:19:HAL_UART_Abort 136 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1669:19:HAL_UART_AbortTransmit 64 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1722:19:HAL_UART_AbortReceive 112 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1790:19:HAL_UART_Abort_IT 144 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:1937:19:HAL_UART_AbortTransmit_IT 64 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2022:19:HAL_UART_AbortReceive_IT 112 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2115:6:HAL_UART_IRQHandler 240 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2417:13:HAL_UART_TxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2432:13:HAL_UART_TxHalfCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2447:13:HAL_UART_RxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2462:13:HAL_UART_RxHalfCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2477:13:HAL_UART_ErrorCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2492:13:HAL_UART_AbortCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2507:13:HAL_UART_AbortTransmitCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2522:13:HAL_UART_AbortReceiveCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2539:13:HAL_UARTEx_RxEventCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2587:6:HAL_UART_ReceiverTimeout_Config 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2599:19:HAL_UART_EnableReceiverTimeout 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2630:19:HAL_UART_DisableReceiverTimeout 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2661:19:HAL_MultiProcessor_EnableMuteMode 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2681:19:HAL_MultiProcessor_DisableMuteMode 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2701:6:HAL_MultiProcessor_EnterMuteMode 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2711:19:HAL_HalfDuplex_EnableTransmitter 64 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2734:19:HAL_HalfDuplex_EnableReceiver 64 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2758:19:HAL_LIN_SendBreak 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2803:23:HAL_UART_GetState 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2819:10:HAL_UART_GetError 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:2863:19:UART_SetConfig 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3007:6:UART_AdvFeatureConfig 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3081:19:UART_CheckIdleState 104 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3150:19:UART_WaitOnFlagUntilTimeout 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3218:19:UART_Start_Receive_IT 96 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3267:19:UART_Start_Receive_DMA 96 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3324:13:UART_EndTxTransfer 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3339:13:UART_EndRxTransfer 88 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3365:13:UART_DMATransmitCplt 72 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3399:13:UART_DMATxHalfCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3417:13:UART_DMAReceiveCplt 120 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3478:13:UART_DMARxHalfCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3516:13:UART_DMAError 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3556:13:UART_DMAAbortOnError 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3579:13:UART_DMATxAbortCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3629:13:UART_DMARxAbortCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3681:13:UART_DMATxOnlyAbortCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3709:13:UART_DMARxOnlyAbortCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3742:13:UART_TxISR_8BIT 64 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3771:13:UART_TxISR_16BIT 72 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3803:13:UART_EndTransmit_IT 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3828:13:UART_RxISR_8BIT 120 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c:3916:13:UART_RxISR_16BIT 120 static,ignoring_inline_asm

20
Software/Code/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.cyclo
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@ -1,11 +1,11 @@
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:148:19:HAL_RS485Ex_Init 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:250:13:HAL_UARTEx_WakeupCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:332:19:HAL_MultiProcessorEx_AddressLength_Set 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:370:19:HAL_UARTEx_StopModeWakeUpSourceConfig 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:425:19:HAL_UARTEx_EnableStopMode 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:444:19:HAL_UARTEx_DisableStopMode 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:475:19:HAL_UARTEx_ReceiveToIdle 18
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:598:19:HAL_UARTEx_ReceiveToIdle_IT 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:659:19:HAL_UARTEx_ReceiveToIdle_DMA 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:727:29:HAL_UARTEx_GetRxEventType 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:751:13:UARTEx_Wakeup_AddressConfig 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:252:13:HAL_UARTEx_WakeupCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:334:19:HAL_MultiProcessorEx_AddressLength_Set 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:372:19:HAL_UARTEx_StopModeWakeUpSourceConfig 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:427:19:HAL_UARTEx_EnableStopMode 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:446:19:HAL_UARTEx_DisableStopMode 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:477:19:HAL_UARTEx_ReceiveToIdle 18
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:600:19:HAL_UARTEx_ReceiveToIdle_IT 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:657:19:HAL_UARTEx_ReceiveToIdle_DMA 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:725:29:HAL_UARTEx_GetRxEventType 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:749:13:UARTEx_Wakeup_AddressConfig 1

BIN
Software/Code/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.o
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20
Software/Code/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.su
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@ -1,11 +1,11 @@
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:148:19:HAL_RS485Ex_Init 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:250:13:HAL_UARTEx_WakeupCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:332:19:HAL_MultiProcessorEx_AddressLength_Set 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:370:19:HAL_UARTEx_StopModeWakeUpSourceConfig 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:425:19:HAL_UARTEx_EnableStopMode 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:444:19:HAL_UARTEx_DisableStopMode 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:475:19:HAL_UARTEx_ReceiveToIdle 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:598:19:HAL_UARTEx_ReceiveToIdle_IT 56 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:659:19:HAL_UARTEx_ReceiveToIdle_DMA 56 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:727:29:HAL_UARTEx_GetRxEventType 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:751:13:UARTEx_Wakeup_AddressConfig 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:252:13:HAL_UARTEx_WakeupCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:334:19:HAL_MultiProcessorEx_AddressLength_Set 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:372:19:HAL_UARTEx_StopModeWakeUpSourceConfig 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:427:19:HAL_UARTEx_EnableStopMode 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:446:19:HAL_UARTEx_DisableStopMode 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:477:19:HAL_UARTEx_ReceiveToIdle 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:600:19:HAL_UARTEx_ReceiveToIdle_IT 56 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:657:19:HAL_UARTEx_ReceiveToIdle_DMA 56 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:725:29:HAL_UARTEx_GetRxEventType 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c:749:13:UARTEx_Wakeup_AddressConfig 24 static

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Software/Code/Debug/PDU_FT25.map
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2
Software/Code/Debug/objects.list
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@ -1,7 +1,9 @@
"./Core/Src/can_communication.o"
"./Core/Src/can_halal.o"
"./Core/Src/channel_control.o"
"./Core/Src/current_monitoring.o"
"./Core/Src/main.o"
"./Core/Src/plausibility_check.o"
"./Core/Src/stm32f3xx_hal_msp.o"
"./Core/Src/stm32f3xx_it.o"
"./Core/Src/syscalls.o"

4
Software/Code/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h
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@ -102,11 +102,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.7
* @brief CMSIS Device version number V2.3.8
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

77
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@ -37,16 +37,12 @@ extern "C" {
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
#if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
#if defined(STM32U5)
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
#endif /* STM32U5 || STM32H7 || STM32MP1 */
#endif /* STM32H7 || STM32MP1 */
/**
* @}
*/
@ -279,7 +275,7 @@ extern "C" {
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
@ -552,6 +548,16 @@ extern "C" {
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
#if defined(STM32U0)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_USER_nBOOT1 OB_USER_NBOOT1
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#endif /* STM32U0 */
/**
* @}
@ -1243,10 +1249,10 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H5)
#if defined(STM32H5) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
#endif /* STM32H5 */
#endif /* STM32H5 || STM32H7RS */
#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@ -1258,10 +1264,10 @@ extern "C" {
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */
#if defined(STM32H5) || defined(STM32WBA)
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
#endif /* STM32H5 || STM32WBA */
#endif /* STM32H5 || STM32WBA || STM32H7RS */
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@ -1599,6 +1605,8 @@ extern "C" {
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
/**
* @}
*/
@ -1991,12 +1999,12 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32H5) || defined(STM32WBA)
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
#endif /* STM32H5 || STM32WBA */
#endif /* STM32H5 || STM32WBA || STM32H7RS */
/**
* @}
@ -2311,8 +2319,8 @@ extern "C" {
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F302xE) || defined(STM32F302xC)
#endif
#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@ -2345,8 +2353,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#endif
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@ -2403,8 +2411,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F373xC) ||defined(STM32F378xx)
#endif
#if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@ -2421,7 +2429,7 @@ extern "C" {
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
# endif
#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@ -2723,6 +2731,12 @@ extern "C" {
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
#if defined(STM32C0)
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
#endif /* STM32C0 */
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@ -3646,8 +3660,12 @@ extern "C" {
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32U0)
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
#endif
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
defined(STM32WL) || defined(STM32C0)
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@ -3749,8 +3767,10 @@ extern "C" {
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@ -3896,7 +3916,8 @@ extern "C" {
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
defined (STM32WBA) || defined (STM32H5) || \
defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3931,6 +3952,13 @@ extern "C" {
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
defined (STM32H7) || \
defined (STM32L0) || defined (STM32L1) || \
defined (STM32WB)
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
#endif
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
@ -4212,6 +4240,9 @@ extern "C" {
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/**
* @}
*/

4
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h
View File

@ -204,7 +204,11 @@ typedef struct
/**
* @brief CAN handle Structure definition
*/
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
typedef struct __CAN_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
{
CAN_TypeDef *Instance; /*!< Register base address */

2
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h
View File

@ -271,6 +271,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1U)
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);

2
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h
View File

@ -118,8 +118,6 @@ typedef enum
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;

62
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h
View File

@ -398,7 +398,7 @@ typedef struct
void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
#if defined(TIM_BDTR_BK2E)
void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
#endif /* */
#endif /* TIM_BDTR_BK2E */
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
} TIM_HandleTypeDef;
@ -408,29 +408,28 @@ typedef struct
*/
typedef enum
{
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
@ -1037,8 +1036,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
#endif /* TIM_CCMR1_OC1M_3 */
/**
* @}
@ -1330,7 +1329,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*)
* @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*)
* @arg TIM_FLAG_CC6: Capture/Compare 6 interrupt flag (*)
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
@ -1354,7 +1353,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*)
* @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*)
* @arg TIM_FLAG_CC6: Capture/Compare 6 interrupt flag (*)
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
@ -1931,6 +1930,14 @@ mode.
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
((__PRESCALER__) == TIM_ICPSC_DIV8))
#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E)
#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
((__CHANNEL__) != (TIM_CHANNEL_5)) && \
((__CHANNEL__) != (TIM_CHANNEL_6)))
#else
#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__))
#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
((__MODE__) == TIM_OPMODE_REPETITIVE))
@ -1959,8 +1966,9 @@ mode.
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
((__PERIOD__) > 0U))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
@ -2013,7 +2021,6 @@ mode.
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
@ -2087,8 +2094,8 @@ mode.
((__MODE__) == TIM_OCMODE_PWM2) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
#else
#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
((__MODE__) == TIM_OCMODE_PWM2))
@ -2450,7 +2457,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);

2
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h
View File

@ -139,7 +139,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/**

5
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h
View File

@ -8072,8 +8072,9 @@ typedef struct
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
/* Delay required between ADC disable and ADC calibration start. */
/* Note: On this STM32 series, before starting a calibration, */
/* ADC must be disabled. */
/* Note: On this STM32 series, before starting a calibration, */
/* ADC must be enabled on STM32F37x and disabled on */
/* other STM32F3 devices. */
/* A minimum number of ADC clock cycles are required */
/* between ADC disable state and calibration start. */
/* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. */

60
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h
View File

@ -577,7 +577,9 @@ typedef struct
#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
#if defined(TIM_SR_B2IF)
#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
#endif /* TIM_SR_B2IF */
#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
@ -654,10 +656,10 @@ typedef struct
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
@ -722,8 +724,12 @@ typedef struct
#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
#if defined(TIM_CCER_CC5E)
#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
#endif /* TIM_CCER_CC5E */
#if defined(TIM_CCER_CC6E)
#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
#endif /* TIM_CCER_CC6E */
#else
#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
@ -748,6 +754,15 @@ typedef struct
*/
#endif /* USE_FULL_LL_DRIVER */
/** Legacy definitions for compatibility purpose
@cond 0
*/
#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
/**
@endcond
*/
/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
* @{
*/
@ -768,8 +783,8 @@ typedef struct
#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
#endif
#if defined(TIM_CCMR1_OC1M_3)
#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
#define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
#define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
#endif
/**
* @}
@ -980,11 +995,11 @@ typedef struct
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
@ -1844,6 +1859,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
}
/**
* @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
* @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
}
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
@ -2094,15 +2120,15 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
* @note The following OC modes are not available on all F3 devices :
* - LL_TIM_OCMODE_RETRIG_OPM1
* - LL_TIM_OCMODE_RETRIG_OPM2
* - LL_TIM_OCMODE_COMBINED_PWM1
* - LL_TIM_OCMODE_COMBINED_PWM2
* - LL_TIM_OCMODE_ASSYMETRIC_PWM1
* - LL_TIM_OCMODE_ASSYMETRIC_PWM2
* - LL_TIM_OCMODE_ASYMMETRIC_PWM1
* - LL_TIM_OCMODE_ASYMMETRIC_PWM2
* @note CH5 and CH6 channels are not available for all F3 devices
* @retval None
*/
@ -2142,8 +2168,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
* - LL_TIM_OCMODE_RETRIG_OPM2
* - LL_TIM_OCMODE_COMBINED_PWM1
* - LL_TIM_OCMODE_COMBINED_PWM2
* - LL_TIM_OCMODE_ASSYMETRIC_PWM1
* - LL_TIM_OCMODE_ASSYMETRIC_PWM2
* - LL_TIM_OCMODE_ASYMMETRIC_PWM1
* - LL_TIM_OCMODE_ASYMMETRIC_PWM2
* @note CH5 and CH6 channels are not available for all F3 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_OCMODE_FROZEN
@ -2158,8 +2184,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
{

2
Software/Code/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h
View File

@ -225,7 +225,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)

2
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
View File

@ -56,7 +56,7 @@
*/
#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F3xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\

5
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
View File

@ -4853,7 +4853,10 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
/* control registers) */

37
Software/Code/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
View File

@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
(+++) Configure CAN pins as alternate function open-drain
(+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
* @brief Configuration functions.
*
* @brief Configuration functions.
*
@verbatim
==============================================================================
##### Configuration functions #####
@ -954,8 +955,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
* @brief Control functions
*
* @brief Control functions
*
@verbatim
==============================================================================
##### Control functions #####
@ -1127,7 +1128,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@ -1143,15 +1143,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
count++;
/* Check if timeout is reached */
if (count > timeout)
if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
} while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@ -1592,8 +1591,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
*
* @brief Interrupts management
*
@verbatim
==============================================================================
##### Interrupts management #####
@ -2058,8 +2057,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
* @brief CAN Callback functions
*
* @brief CAN Callback functions
*
@verbatim
==============================================================================
##### Callback functions #####
@ -2308,8 +2307,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
* @brief CAN Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####

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