FaSTTUBe/dashboard
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dashboard/Software/Debug/Dashboard.list
Finley b7f10b326f Add software
2025-03-26 14:36:13 +01:00

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Dashboard.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000030f4 08000188 08000188 00001188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000030 0800327c 0800327c 0000427c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080032ac 080032ac 0000500c 2**0
CONTENTS
4 .ARM 00000000 080032ac 080032ac 0000500c 2**0
CONTENTS
5 .preinit_array 00000000 080032ac 080032ac 0000500c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080032ac 080032ac 000042ac 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 080032b0 080032b0 000042b0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 080032b4 00005000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000bc 2000000c 080032c0 0000500c 2**2
ALLOC
10 ._user_heap_stack 00000600 200000c8 080032c0 000050c8 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000500c 2**0
CONTENTS, READONLY
12 .debug_info 00006338 00000000 00000000 0000503c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000013d9 00000000 00000000 0000b374 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000568 00000000 00000000 0000c750 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000003f5 00000000 00000000 0000ccb8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001a91b 00000000 00000000 0000d0ad 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00006ae1 00000000 00000000 000279c8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0009e1e0 00000000 00000000 0002e4a9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000cc689 2**0
CONTENTS, READONLY
20 .debug_frame 000014a0 00000000 00000000 000cc6cc 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000068 00000000 00000000 000cdb6c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000000c .word 0x2000000c
80001a4: 00000000 .word 0x00000000
80001a8: 08003264 .word 0x08003264
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000010 .word 0x20000010
80001c4: 08003264 .word 0x08003264
080001c8 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80001c8: b580 push {r7, lr}
80001ca: b092 sub sp, #72 @ 0x48
80001cc: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80001ce: f000 fc1f bl 8000a10 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80001d2: f000 f9ff bl 80005d4 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80001d6: f000 fa73 bl 80006c0 <MX_GPIO_Init>
MX_CAN_Init();
80001da: f000 fa3b bl 8000654 <MX_CAN_Init>
/* USER CODE BEGIN 2 */
txHeader.IDE = CAN_ID_STD;
80001de: 4bae ldr r3, [pc, #696] @ (8000498 <main+0x2d0>)
80001e0: 2200 movs r2, #0
80001e2: 609a str r2, [r3, #8]
txHeader.StdId = CAN_ID_TX;
80001e4: 4bac ldr r3, [pc, #688] @ (8000498 <main+0x2d0>)
80001e6: f44f 6284 mov.w r2, #1056 @ 0x420
80001ea: 601a str r2, [r3, #0]
txHeader.RTR = CAN_RTR_DATA;
80001ec: 4baa ldr r3, [pc, #680] @ (8000498 <main+0x2d0>)
80001ee: 2200 movs r2, #0
80001f0: 60da str r2, [r3, #12]
txHeader.DLC = 1;
80001f2: 4ba9 ldr r3, [pc, #676] @ (8000498 <main+0x2d0>)
80001f4: 2201 movs r2, #1
80001f6: 611a str r2, [r3, #16]
if (HAL_CAN_Start(&hcan) != HAL_OK)
80001f8: 48a8 ldr r0, [pc, #672] @ (800049c <main+0x2d4>)
80001fa: f000 fea3 bl 8000f44 <HAL_CAN_Start>
80001fe: 4603 mov r3, r0
8000200: 2b00 cmp r3, #0
8000202: d001 beq.n 8000208 <main+0x40>
Error_Handler();
8000204: f000 fb06 bl 8000814 <Error_Handler>
CAN_FilterTypeDef canfilterconfig;
canfilterconfig.FilterActivation = CAN_FILTER_ENABLE;
8000208: 2301 movs r3, #1
800020a: 627b str r3, [r7, #36] @ 0x24
canfilterconfig.FilterBank = 0;
800020c: 2300 movs r3, #0
800020e: 61bb str r3, [r7, #24]
canfilterconfig.FilterFIFOAssignment = CAN_FILTER_FIFO0;
8000210: 2300 movs r3, #0
8000212: 617b str r3, [r7, #20]
canfilterconfig.FilterIdHigh = CAN_ID_RX_AMS << (16 - 11);
8000214: f44f 73a0 mov.w r3, #320 @ 0x140
8000218: 607b str r3, [r7, #4]
canfilterconfig.FilterIdLow = CAN_ID_RX_R2D << (16 - 11);
800021a: f44f 4302 mov.w r3, #33280 @ 0x8200
800021e: 60bb str r3, [r7, #8]
canfilterconfig.FilterMaskIdHigh = 0x7FF << (16 - 11);
8000220: f64f 73e0 movw r3, #65504 @ 0xffe0
8000224: 60fb str r3, [r7, #12]
canfilterconfig.FilterMaskIdLow = 0x7FF << (16 - 11);
8000226: f64f 73e0 movw r3, #65504 @ 0xffe0
800022a: 613b str r3, [r7, #16]
canfilterconfig.FilterMode = CAN_FILTERMODE_IDMASK;
800022c: 2300 movs r3, #0
800022e: 61fb str r3, [r7, #28]
canfilterconfig.FilterScale = CAN_FILTERSCALE_32BIT;
8000230: 2301 movs r3, #1
8000232: 623b str r3, [r7, #32]
canfilterconfig.SlaveStartFilterBank = 14;
8000234: 230e movs r3, #14
8000236: 62bb str r3, [r7, #40] @ 0x28
if (HAL_CAN_ConfigFilter(&hcan, &canfilterconfig) != HAL_OK) {
8000238: 1d3b adds r3, r7, #4
800023a: 4619 mov r1, r3
800023c: 4897 ldr r0, [pc, #604] @ (800049c <main+0x2d4>)
800023e: f000 fdb7 bl 8000db0 <HAL_CAN_ConfigFilter>
8000242: 4603 mov r3, r0
8000244: 2b00 cmp r3, #0
8000246: d001 beq.n 800024c <main+0x84>
Error_Handler();
8000248: f000 fae4 bl 8000814 <Error_Handler>
}
if (HAL_CAN_ActivateNotification(&hcan, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK)
800024c: 2102 movs r1, #2
800024e: 4893 ldr r0, [pc, #588] @ (800049c <main+0x2d4>)
8000250: f001 f8ae bl 80013b0 <HAL_CAN_ActivateNotification>
8000254: 4603 mov r3, r0
8000256: 2b00 cmp r3, #0
8000258: d001 beq.n 800025e <main+0x96>
Error_Handler();
800025a: f000 fadb bl 8000814 <Error_Handler>
// blink flags
int blink_state = 0;
800025e: 2300 movs r3, #0
8000260: 647b str r3, [r7, #68] @ 0x44
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
dash_tx.tson = HAL_GPIO_ReadPin(TSON_BTN_GPIO_Port, TSON_BTN_Pin);
8000262: f44f 4100 mov.w r1, #32768 @ 0x8000
8000266: 488e ldr r0, [pc, #568] @ (80004a0 <main+0x2d8>)
8000268: f001 fd92 bl 8001d90 <HAL_GPIO_ReadPin>
800026c: 4603 mov r3, r0
800026e: 01db lsls r3, r3, #7
8000270: b25b sxtb r3, r3
8000272: 11db asrs r3, r3, #7
8000274: b259 sxtb r1, r3
8000276: 4a8b ldr r2, [pc, #556] @ (80004a4 <main+0x2dc>)
8000278: 7813 ldrb r3, [r2, #0]
800027a: f361 0341 bfi r3, r1, #1, #1
800027e: 7013 strb r3, [r2, #0]
dash_tx.r2d = HAL_GPIO_ReadPin(R2D_BTN_GPIO_Port, R2D_BTN_Pin);
8000280: 2120 movs r1, #32
8000282: 4887 ldr r0, [pc, #540] @ (80004a0 <main+0x2d8>)
8000284: f001 fd84 bl 8001d90 <HAL_GPIO_ReadPin>
8000288: 4603 mov r3, r0
800028a: 01db lsls r3, r3, #7
800028c: b25b sxtb r3, r3
800028e: 11db asrs r3, r3, #7
8000290: b259 sxtb r1, r3
8000292: 4a84 ldr r2, [pc, #528] @ (80004a4 <main+0x2dc>)
8000294: 7813 ldrb r3, [r2, #0]
8000296: f361 0300 bfi r3, r1, #0, #1
800029a: 7013 strb r3, [r2, #0]
dash_tx.sdc_in = HAL_GPIO_ReadPin(SDC_In_3V3_GPIO_Port, SDC_In_3V3_Pin);
800029c: 2110 movs r1, #16
800029e: 4880 ldr r0, [pc, #512] @ (80004a0 <main+0x2d8>)
80002a0: f001 fd76 bl 8001d90 <HAL_GPIO_ReadPin>
80002a4: 4603 mov r3, r0
80002a6: 01db lsls r3, r3, #7
80002a8: b25b sxtb r3, r3
80002aa: 11db asrs r3, r3, #7
80002ac: b259 sxtb r1, r3
80002ae: 4a7d ldr r2, [pc, #500] @ (80004a4 <main+0x2dc>)
80002b0: 7813 ldrb r3, [r2, #0]
80002b2: f361 03c3 bfi r3, r1, #3, #1
80002b6: 7013 strb r3, [r2, #0]
dash_tx.sdc_out = HAL_GPIO_ReadPin(SDC_Out_3V3_GPIO_Port, SDC_Out_3V3_Pin);
80002b8: 2108 movs r1, #8
80002ba: 4879 ldr r0, [pc, #484] @ (80004a0 <main+0x2d8>)
80002bc: f001 fd68 bl 8001d90 <HAL_GPIO_ReadPin>
80002c0: 4603 mov r3, r0
80002c2: 01db lsls r3, r3, #7
80002c4: b25b sxtb r3, r3
80002c6: 11db asrs r3, r3, #7
80002c8: b259 sxtb r1, r3
80002ca: 4a76 ldr r2, [pc, #472] @ (80004a4 <main+0x2dc>)
80002cc: 7813 ldrb r3, [r2, #0]
80002ce: f361 1304 bfi r3, r1, #4, #1
80002d2: 7013 strb r3, [r2, #0]
dash_tx.racemode = HAL_GPIO_ReadPin(RMode_Out_3V3_GPIO_Port, RMode_Out_3V3_Pin);
80002d4: f44f 7180 mov.w r1, #256 @ 0x100
80002d8: 4871 ldr r0, [pc, #452] @ (80004a0 <main+0x2d8>)
80002da: f001 fd59 bl 8001d90 <HAL_GPIO_ReadPin>
80002de: 4603 mov r3, r0
80002e0: 01db lsls r3, r3, #7
80002e2: b25b sxtb r3, r3
80002e4: 11db asrs r3, r3, #7
80002e6: b259 sxtb r1, r3
80002e8: 4a6e ldr r2, [pc, #440] @ (80004a4 <main+0x2dc>)
80002ea: 7813 ldrb r3, [r2, #0]
80002ec: f361 0382 bfi r3, r1, #2, #1
80002f0: 7013 strb r3, [r2, #0]
if ((HAL_GetTick() - last_send_can_tick ) > 200) {
80002f2: f000 fbe7 bl 8000ac4 <HAL_GetTick>
80002f6: 4602 mov r2, r0
80002f8: 4b6b ldr r3, [pc, #428] @ (80004a8 <main+0x2e0>)
80002fa: 681b ldr r3, [r3, #0]
80002fc: 1ad3 subs r3, r2, r3
80002fe: 2bc8 cmp r3, #200 @ 0xc8
8000300: d90f bls.n 8000322 <main+0x15a>
if (HAL_CAN_AddTxMessage(&hcan, &txHeader, (uint8_t*) &dash_tx, &txMailbox) != HAL_OK) {
8000302: 4b6a ldr r3, [pc, #424] @ (80004ac <main+0x2e4>)
8000304: 4a67 ldr r2, [pc, #412] @ (80004a4 <main+0x2dc>)
8000306: 4964 ldr r1, [pc, #400] @ (8000498 <main+0x2d0>)
8000308: 4864 ldr r0, [pc, #400] @ (800049c <main+0x2d4>)
800030a: f000 fe5f bl 8000fcc <HAL_CAN_AddTxMessage>
800030e: 4603 mov r3, r0
8000310: 2b00 cmp r3, #0
8000312: d001 beq.n 8000318 <main+0x150>
Error_Handler();
8000314: f000 fa7e bl 8000814 <Error_Handler>
}
last_send_can_tick = HAL_GetTick();
8000318: f000 fbd4 bl 8000ac4 <HAL_GetTick>
800031c: 4603 mov r3, r0
800031e: 4a62 ldr r2, [pc, #392] @ (80004a8 <main+0x2e0>)
8000320: 6013 str r3, [r2, #0]
}
// Inverted in hardware
if ((HAL_GetTick() - ams_last_tick) < 80) {
8000322: f000 fbcf bl 8000ac4 <HAL_GetTick>
8000326: 4602 mov r2, r0
8000328: 4b61 ldr r3, [pc, #388] @ (80004b0 <main+0x2e8>)
800032a: 681b ldr r3, [r3, #0]
800032c: 1ad3 subs r3, r2, r3
800032e: 2b4f cmp r3, #79 @ 0x4f
8000330: d823 bhi.n 800037a <main+0x1b2>
HAL_GPIO_WritePin(IMD_LED_GPIO_Port, IMD_LED_Pin, dash_rx.imd_ok);
8000332: 4b60 ldr r3, [pc, #384] @ (80004b4 <main+0x2ec>)
8000334: 685b ldr r3, [r3, #4]
8000336: b2db uxtb r3, r3
8000338: 461a mov r2, r3
800033a: 2108 movs r1, #8
800033c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000340: f001 fd3e bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(AMS_LED_GPIO_Port, AMS_LED_Pin, dash_rx.ams_state != TS_ERROR);
8000344: 4b5b ldr r3, [pc, #364] @ (80004b4 <main+0x2ec>)
8000346: 781b ldrb r3, [r3, #0]
8000348: 2b04 cmp r3, #4
800034a: bf14 ite ne
800034c: 2301 movne r3, #1
800034e: 2300 moveq r3, #0
8000350: b2db uxtb r3, r3
8000352: 461a mov r2, r3
8000354: 2110 movs r1, #16
8000356: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800035a: f001 fd31 bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSOFF_LED_GPIO_Port, TSOFF_LED_Pin, dash_rx.ams_state == TS_INACTIVE);
800035e: 4b55 ldr r3, [pc, #340] @ (80004b4 <main+0x2ec>)
8000360: 781b ldrb r3, [r3, #0]
8000362: 2b00 cmp r3, #0
8000364: bf0c ite eq
8000366: 2301 moveq r3, #1
8000368: 2300 movne r3, #0
800036a: b2db uxtb r3, r3
800036c: 461a mov r2, r3
800036e: 2120 movs r1, #32
8000370: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000374: f001 fd24 bl 8001dc0 <HAL_GPIO_WritePin>
8000378: e011 b.n 800039e <main+0x1d6>
} else {
// Safe state: Error LEDs on, TSOFF off
HAL_GPIO_WritePin(IMD_LED_GPIO_Port, IMD_LED_Pin, 0);
800037a: 2200 movs r2, #0
800037c: 2108 movs r1, #8
800037e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000382: f001 fd1d bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(AMS_LED_GPIO_Port, AMS_LED_Pin, 0);
8000386: 2200 movs r2, #0
8000388: 2110 movs r1, #16
800038a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800038e: f001 fd17 bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSOFF_LED_GPIO_Port, TSOFF_LED_Pin, 0);
8000392: 2200 movs r2, #0
8000394: 2120 movs r1, #32
8000396: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800039a: f001 fd11 bl 8001dc0 <HAL_GPIO_WritePin>
}
int r = 0, g = 0, b = 0;
800039e: 2300 movs r3, #0
80003a0: 643b str r3, [r7, #64] @ 0x40
80003a2: 2300 movs r3, #0
80003a4: 63fb str r3, [r7, #60] @ 0x3c
80003a6: 2300 movs r3, #0
80003a8: 63bb str r3, [r7, #56] @ 0x38
int br = 0, bg = 0, bb = 0;
80003aa: 2300 movs r3, #0
80003ac: 637b str r3, [r7, #52] @ 0x34
80003ae: 2300 movs r3, #0
80003b0: 633b str r3, [r7, #48] @ 0x30
80003b2: 2300 movs r3, #0
80003b4: 62fb str r3, [r7, #44] @ 0x2c
if (dash_rx.sdc_closed) {
80003b6: 4b3f ldr r3, [pc, #252] @ (80004b4 <main+0x2ec>)
80003b8: 689b ldr r3, [r3, #8]
80003ba: 2b00 cmp r3, #0
80003bc: d021 beq.n 8000402 <main+0x23a>
switch (dash_rx.ams_state) {
80003be: 4b3d ldr r3, [pc, #244] @ (80004b4 <main+0x2ec>)
80003c0: 781b ldrb r3, [r3, #0]
80003c2: 2b03 cmp r3, #3
80003c4: d81a bhi.n 80003fc <main+0x234>
80003c6: a201 add r2, pc, #4 @ (adr r2, 80003cc <main+0x204>)
80003c8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80003cc: 080003dd .word 0x080003dd
80003d0: 080003f1 .word 0x080003f1
80003d4: 080003e7 .word 0x080003e7
80003d8: 080003f7 .word 0x080003f7
case TS_INACTIVE:
r = g = 1;
80003dc: 2301 movs r3, #1
80003de: 63fb str r3, [r7, #60] @ 0x3c
80003e0: 6bfb ldr r3, [r7, #60] @ 0x3c
80003e2: 643b str r3, [r7, #64] @ 0x40
break;
80003e4: e00f b.n 8000406 <main+0x23e>
case TS_PRECHARGE:
// Gelb blink
br = bg = 1;
80003e6: 2301 movs r3, #1
80003e8: 633b str r3, [r7, #48] @ 0x30
80003ea: 6b3b ldr r3, [r7, #48] @ 0x30
80003ec: 637b str r3, [r7, #52] @ 0x34
break;
80003ee: e00a b.n 8000406 <main+0x23e>
case TS_ACTIVE:
g = 1;
80003f0: 2301 movs r3, #1
80003f2: 63fb str r3, [r7, #60] @ 0x3c
break;
80003f4: e007 b.n 8000406 <main+0x23e>
case TS_DISCHARGE:
// Blau blink
bb = 1;
80003f6: 2301 movs r3, #1
80003f8: 62fb str r3, [r7, #44] @ 0x2c
break;
80003fa: e004 b.n 8000406 <main+0x23e>
default:
r = 1;
80003fc: 2301 movs r3, #1
80003fe: 643b str r3, [r7, #64] @ 0x40
break;
8000400: e001 b.n 8000406 <main+0x23e>
}
} else {
b = 1;
8000402: 2301 movs r3, #1
8000404: 63bb str r3, [r7, #56] @ 0x38
}
HAL_GPIO_WritePin(TSON_R_GPIO_Port, TSON_R_Pin, r);
8000406: 6c3b ldr r3, [r7, #64] @ 0x40
8000408: b2db uxtb r3, r3
800040a: 461a mov r2, r3
800040c: 2101 movs r1, #1
800040e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000412: f001 fcd5 bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSON_G_GPIO_Port, TSON_G_Pin, g);
8000416: 6bfb ldr r3, [r7, #60] @ 0x3c
8000418: b2db uxtb r3, r3
800041a: 461a mov r2, r3
800041c: 2102 movs r1, #2
800041e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000422: f001 fccd bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSON_B_GPIO_Port, TSON_B_Pin, b);
8000426: 6bbb ldr r3, [r7, #56] @ 0x38
8000428: b2db uxtb r3, r3
800042a: 461a mov r2, r3
800042c: 2104 movs r1, #4
800042e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000432: f001 fcc5 bl 8001dc0 <HAL_GPIO_WritePin>
if (br || bg || bb) {
8000436: 6b7b ldr r3, [r7, #52] @ 0x34
8000438: 2b00 cmp r3, #0
800043a: d105 bne.n 8000448 <main+0x280>
800043c: 6b3b ldr r3, [r7, #48] @ 0x30
800043e: 2b00 cmp r3, #0
8000440: d102 bne.n 8000448 <main+0x280>
8000442: 6afb ldr r3, [r7, #44] @ 0x2c
8000444: 2b00 cmp r3, #0
8000446: d03f beq.n 80004c8 <main+0x300>
HAL_GPIO_WritePin(TSON_R_GPIO_Port, TSON_R_Pin, br && blink_state);
8000448: 6b7b ldr r3, [r7, #52] @ 0x34
800044a: 2b00 cmp r3, #0
800044c: d004 beq.n 8000458 <main+0x290>
800044e: 6c7b ldr r3, [r7, #68] @ 0x44
8000450: 2b00 cmp r3, #0
8000452: d001 beq.n 8000458 <main+0x290>
8000454: 2301 movs r3, #1
8000456: e000 b.n 800045a <main+0x292>
8000458: 2300 movs r3, #0
800045a: b2db uxtb r3, r3
800045c: 461a mov r2, r3
800045e: 2101 movs r1, #1
8000460: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000464: f001 fcac bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSON_G_GPIO_Port, TSON_G_Pin, bg && blink_state);
8000468: 6b3b ldr r3, [r7, #48] @ 0x30
800046a: 2b00 cmp r3, #0
800046c: d004 beq.n 8000478 <main+0x2b0>
800046e: 6c7b ldr r3, [r7, #68] @ 0x44
8000470: 2b00 cmp r3, #0
8000472: d001 beq.n 8000478 <main+0x2b0>
8000474: 2301 movs r3, #1
8000476: e000 b.n 800047a <main+0x2b2>
8000478: 2300 movs r3, #0
800047a: b2db uxtb r3, r3
800047c: 461a mov r2, r3
800047e: 2102 movs r1, #2
8000480: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000484: f001 fc9c bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSON_B_GPIO_Port, TSON_B_Pin, bb && blink_state);
8000488: 6afb ldr r3, [r7, #44] @ 0x2c
800048a: 2b00 cmp r3, #0
800048c: d014 beq.n 80004b8 <main+0x2f0>
800048e: 6c7b ldr r3, [r7, #68] @ 0x44
8000490: 2b00 cmp r3, #0
8000492: d011 beq.n 80004b8 <main+0x2f0>
8000494: 2301 movs r3, #1
8000496: e010 b.n 80004ba <main+0x2f2>
8000498: 20000090 .word 0x20000090
800049c: 20000028 .word 0x20000028
80004a0: 48000400 .word 0x48000400
80004a4: 2000008c .word 0x2000008c
80004a8: 200000c0 .word 0x200000c0
80004ac: 200000a8 .word 0x200000a8
80004b0: 200000bc .word 0x200000bc
80004b4: 200000ac .word 0x200000ac
80004b8: 2300 movs r3, #0
80004ba: b2db uxtb r3, r3
80004bc: 461a mov r2, r3
80004be: 2104 movs r1, #4
80004c0: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80004c4: f001 fc7c bl 8001dc0 <HAL_GPIO_WritePin>
}
r = g = b = 0;
80004c8: 2300 movs r3, #0
80004ca: 63bb str r3, [r7, #56] @ 0x38
80004cc: 6bbb ldr r3, [r7, #56] @ 0x38
80004ce: 63fb str r3, [r7, #60] @ 0x3c
80004d0: 6bfb ldr r3, [r7, #60] @ 0x3c
80004d2: 643b str r3, [r7, #64] @ 0x40
br = bg = bb = 0;
80004d4: 2300 movs r3, #0
80004d6: 62fb str r3, [r7, #44] @ 0x2c
80004d8: 6afb ldr r3, [r7, #44] @ 0x2c
80004da: 633b str r3, [r7, #48] @ 0x30
80004dc: 6b3b ldr r3, [r7, #48] @ 0x30
80004de: 637b str r3, [r7, #52] @ 0x34
if (dash_rx.ams_state == TS_ACTIVE) {
80004e0: 4b3a ldr r3, [pc, #232] @ (80005cc <main+0x404>)
80004e2: 781b ldrb r3, [r3, #0]
80004e4: 2b01 cmp r3, #1
80004e6: d116 bne.n 8000516 <main+0x34e>
switch (dash_rx.r2d_progress) {
80004e8: 4b38 ldr r3, [pc, #224] @ (80005cc <main+0x404>)
80004ea: 7b1b ldrb r3, [r3, #12]
80004ec: 2b02 cmp r3, #2
80004ee: dc02 bgt.n 80004f6 <main+0x32e>
80004f0: 2b00 cmp r3, #0
80004f2: da03 bge.n 80004fc <main+0x334>
80004f4: e00a b.n 800050c <main+0x344>
80004f6: 2b0f cmp r3, #15
80004f8: d005 beq.n 8000506 <main+0x33e>
80004fa: e007 b.n 800050c <main+0x344>
case R2D_NONE:
case R2D_TSMS:
case R2D_TSActive:
r = g = 1;
80004fc: 2301 movs r3, #1
80004fe: 63fb str r3, [r7, #60] @ 0x3c
8000500: 6bfb ldr r3, [r7, #60] @ 0x3c
8000502: 643b str r3, [r7, #64] @ 0x40
break;
8000504: e009 b.n 800051a <main+0x352>
case R2D_Success:
g = 1;
8000506: 2301 movs r3, #1
8000508: 63fb str r3, [r7, #60] @ 0x3c
break;
800050a: e006 b.n 800051a <main+0x352>
default:
// Gelb blink
bg = br = 1;
800050c: 2301 movs r3, #1
800050e: 637b str r3, [r7, #52] @ 0x34
8000510: 6b7b ldr r3, [r7, #52] @ 0x34
8000512: 633b str r3, [r7, #48] @ 0x30
break;
8000514: e001 b.n 800051a <main+0x352>
}
} else {
b = 1;
8000516: 2301 movs r3, #1
8000518: 63bb str r3, [r7, #56] @ 0x38
}
HAL_GPIO_WritePin(R2D_R_GPIO_Port, R2D_R_Pin, r);
800051a: 6c3b ldr r3, [r7, #64] @ 0x40
800051c: b2db uxtb r3, r3
800051e: 461a mov r2, r3
8000520: 2180 movs r1, #128 @ 0x80
8000522: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000526: f001 fc4b bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(R2D_G_GPIO_Port, R2D_G_Pin, g);
800052a: 6bfb ldr r3, [r7, #60] @ 0x3c
800052c: b2db uxtb r3, r3
800052e: 461a mov r2, r3
8000530: 2101 movs r1, #1
8000532: 4827 ldr r0, [pc, #156] @ (80005d0 <main+0x408>)
8000534: f001 fc44 bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(R2D_B_GPIO_Port, R2D_B_Pin, b);
8000538: 6bbb ldr r3, [r7, #56] @ 0x38
800053a: b2db uxtb r3, r3
800053c: 461a mov r2, r3
800053e: 2102 movs r1, #2
8000540: 4823 ldr r0, [pc, #140] @ (80005d0 <main+0x408>)
8000542: f001 fc3d bl 8001dc0 <HAL_GPIO_WritePin>
if (br || bg || bb) {
8000546: 6b7b ldr r3, [r7, #52] @ 0x34
8000548: 2b00 cmp r3, #0
800054a: d105 bne.n 8000558 <main+0x390>
800054c: 6b3b ldr r3, [r7, #48] @ 0x30
800054e: 2b00 cmp r3, #0
8000550: d102 bne.n 8000558 <main+0x390>
8000552: 6afb ldr r3, [r7, #44] @ 0x2c
8000554: 2b00 cmp r3, #0
8000556: d02d beq.n 80005b4 <main+0x3ec>
HAL_GPIO_WritePin(R2D_R_GPIO_Port, R2D_R_Pin, br && blink_state);
8000558: 6b7b ldr r3, [r7, #52] @ 0x34
800055a: 2b00 cmp r3, #0
800055c: d004 beq.n 8000568 <main+0x3a0>
800055e: 6c7b ldr r3, [r7, #68] @ 0x44
8000560: 2b00 cmp r3, #0
8000562: d001 beq.n 8000568 <main+0x3a0>
8000564: 2301 movs r3, #1
8000566: e000 b.n 800056a <main+0x3a2>
8000568: 2300 movs r3, #0
800056a: b2db uxtb r3, r3
800056c: 461a mov r2, r3
800056e: 2180 movs r1, #128 @ 0x80
8000570: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000574: f001 fc24 bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(R2D_G_GPIO_Port, R2D_G_Pin, bg && blink_state);
8000578: 6b3b ldr r3, [r7, #48] @ 0x30
800057a: 2b00 cmp r3, #0
800057c: d004 beq.n 8000588 <main+0x3c0>
800057e: 6c7b ldr r3, [r7, #68] @ 0x44
8000580: 2b00 cmp r3, #0
8000582: d001 beq.n 8000588 <main+0x3c0>
8000584: 2301 movs r3, #1
8000586: e000 b.n 800058a <main+0x3c2>
8000588: 2300 movs r3, #0
800058a: b2db uxtb r3, r3
800058c: 461a mov r2, r3
800058e: 2101 movs r1, #1
8000590: 480f ldr r0, [pc, #60] @ (80005d0 <main+0x408>)
8000592: f001 fc15 bl 8001dc0 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(R2D_B_GPIO_Port, R2D_B_Pin, bb && blink_state);
8000596: 6afb ldr r3, [r7, #44] @ 0x2c
8000598: 2b00 cmp r3, #0
800059a: d004 beq.n 80005a6 <main+0x3de>
800059c: 6c7b ldr r3, [r7, #68] @ 0x44
800059e: 2b00 cmp r3, #0
80005a0: d001 beq.n 80005a6 <main+0x3de>
80005a2: 2301 movs r3, #1
80005a4: e000 b.n 80005a8 <main+0x3e0>
80005a6: 2300 movs r3, #0
80005a8: b2db uxtb r3, r3
80005aa: 461a mov r2, r3
80005ac: 2102 movs r1, #2
80005ae: 4808 ldr r0, [pc, #32] @ (80005d0 <main+0x408>)
80005b0: f001 fc06 bl 8001dc0 <HAL_GPIO_WritePin>
}
blink_state = !blink_state;
80005b4: 6c7b ldr r3, [r7, #68] @ 0x44
80005b6: 2b00 cmp r3, #0
80005b8: bf0c ite eq
80005ba: 2301 moveq r3, #1
80005bc: 2300 movne r3, #0
80005be: b2db uxtb r3, r3
80005c0: 647b str r3, [r7, #68] @ 0x44
HAL_Delay(50);
80005c2: 2032 movs r0, #50 @ 0x32
80005c4: f000 fa8a bl 8000adc <HAL_Delay>
{
80005c8: e64b b.n 8000262 <main+0x9a>
80005ca: bf00 nop
80005cc: 200000ac .word 0x200000ac
80005d0: 48000400 .word 0x48000400
080005d4 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80005d4: b580 push {r7, lr}
80005d6: b090 sub sp, #64 @ 0x40
80005d8: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80005da: f107 0318 add.w r3, r7, #24
80005de: 2228 movs r2, #40 @ 0x28
80005e0: 2100 movs r1, #0
80005e2: 4618 mov r0, r3
80005e4: f002 fe12 bl 800320c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80005e8: 1d3b adds r3, r7, #4
80005ea: 2200 movs r2, #0
80005ec: 601a str r2, [r3, #0]
80005ee: 605a str r2, [r3, #4]
80005f0: 609a str r2, [r3, #8]
80005f2: 60da str r2, [r3, #12]
80005f4: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80005f6: 2302 movs r3, #2
80005f8: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80005fa: 2301 movs r3, #1
80005fc: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80005fe: 2310 movs r3, #16
8000600: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000602: 2302 movs r3, #2
8000604: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
8000606: 2300 movs r3, #0
8000608: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
800060a: f44f 2300 mov.w r3, #524288 @ 0x80000
800060e: 63fb str r3, [r7, #60] @ 0x3c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000610: f107 0318 add.w r3, r7, #24
8000614: 4618 mov r0, r3
8000616: f001 fbeb bl 8001df0 <HAL_RCC_OscConfig>
800061a: 4603 mov r3, r0
800061c: 2b00 cmp r3, #0
800061e: d001 beq.n 8000624 <SystemClock_Config+0x50>
{
Error_Handler();
8000620: f000 f8f8 bl 8000814 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000624: 230f movs r3, #15
8000626: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000628: 2302 movs r3, #2
800062a: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800062c: 2300 movs r3, #0
800062e: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000630: 2300 movs r3, #0
8000632: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000634: 2300 movs r3, #0
8000636: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000638: 1d3b adds r3, r7, #4
800063a: 2100 movs r1, #0
800063c: 4618 mov r0, r3
800063e: f002 fc15 bl 8002e6c <HAL_RCC_ClockConfig>
8000642: 4603 mov r3, r0
8000644: 2b00 cmp r3, #0
8000646: d001 beq.n 800064c <SystemClock_Config+0x78>
{
Error_Handler();
8000648: f000 f8e4 bl 8000814 <Error_Handler>
}
}
800064c: bf00 nop
800064e: 3740 adds r7, #64 @ 0x40
8000650: 46bd mov sp, r7
8000652: bd80 pop {r7, pc}
08000654 <MX_CAN_Init>:
* @brief CAN Initialization Function
* @param None
* @retval None
*/
static void MX_CAN_Init(void)
{
8000654: b580 push {r7, lr}
8000656: af00 add r7, sp, #0
/* USER CODE END CAN_Init 0 */
/* USER CODE BEGIN CAN_Init 1 */
/* USER CODE END CAN_Init 1 */
hcan.Instance = CAN;
8000658: 4b17 ldr r3, [pc, #92] @ (80006b8 <MX_CAN_Init+0x64>)
800065a: 4a18 ldr r2, [pc, #96] @ (80006bc <MX_CAN_Init+0x68>)
800065c: 601a str r2, [r3, #0]
hcan.Init.Prescaler = 2;
800065e: 4b16 ldr r3, [pc, #88] @ (80006b8 <MX_CAN_Init+0x64>)
8000660: 2202 movs r2, #2
8000662: 605a str r2, [r3, #4]
hcan.Init.Mode = CAN_MODE_NORMAL;
8000664: 4b14 ldr r3, [pc, #80] @ (80006b8 <MX_CAN_Init+0x64>)
8000666: 2200 movs r2, #0
8000668: 609a str r2, [r3, #8]
hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
800066a: 4b13 ldr r3, [pc, #76] @ (80006b8 <MX_CAN_Init+0x64>)
800066c: 2200 movs r2, #0
800066e: 60da str r2, [r3, #12]
hcan.Init.TimeSeg1 = CAN_BS1_13TQ;
8000670: 4b11 ldr r3, [pc, #68] @ (80006b8 <MX_CAN_Init+0x64>)
8000672: f44f 2240 mov.w r2, #786432 @ 0xc0000
8000676: 611a str r2, [r3, #16]
hcan.Init.TimeSeg2 = CAN_BS2_2TQ;
8000678: 4b0f ldr r3, [pc, #60] @ (80006b8 <MX_CAN_Init+0x64>)
800067a: f44f 1280 mov.w r2, #1048576 @ 0x100000
800067e: 615a str r2, [r3, #20]
hcan.Init.TimeTriggeredMode = DISABLE;
8000680: 4b0d ldr r3, [pc, #52] @ (80006b8 <MX_CAN_Init+0x64>)
8000682: 2200 movs r2, #0
8000684: 761a strb r2, [r3, #24]
hcan.Init.AutoBusOff = DISABLE;
8000686: 4b0c ldr r3, [pc, #48] @ (80006b8 <MX_CAN_Init+0x64>)
8000688: 2200 movs r2, #0
800068a: 765a strb r2, [r3, #25]
hcan.Init.AutoWakeUp = DISABLE;
800068c: 4b0a ldr r3, [pc, #40] @ (80006b8 <MX_CAN_Init+0x64>)
800068e: 2200 movs r2, #0
8000690: 769a strb r2, [r3, #26]
hcan.Init.AutoRetransmission = DISABLE;
8000692: 4b09 ldr r3, [pc, #36] @ (80006b8 <MX_CAN_Init+0x64>)
8000694: 2200 movs r2, #0
8000696: 76da strb r2, [r3, #27]
hcan.Init.ReceiveFifoLocked = DISABLE;
8000698: 4b07 ldr r3, [pc, #28] @ (80006b8 <MX_CAN_Init+0x64>)
800069a: 2200 movs r2, #0
800069c: 771a strb r2, [r3, #28]
hcan.Init.TransmitFifoPriority = DISABLE;
800069e: 4b06 ldr r3, [pc, #24] @ (80006b8 <MX_CAN_Init+0x64>)
80006a0: 2200 movs r2, #0
80006a2: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan) != HAL_OK)
80006a4: 4804 ldr r0, [pc, #16] @ (80006b8 <MX_CAN_Init+0x64>)
80006a6: f000 fa3d bl 8000b24 <HAL_CAN_Init>
80006aa: 4603 mov r3, r0
80006ac: 2b00 cmp r3, #0
80006ae: d001 beq.n 80006b4 <MX_CAN_Init+0x60>
{
Error_Handler();
80006b0: f000 f8b0 bl 8000814 <Error_Handler>
}
/* USER CODE BEGIN CAN_Init 2 */
/* USER CODE END CAN_Init 2 */
}
80006b4: bf00 nop
80006b6: bd80 pop {r7, pc}
80006b8: 20000028 .word 0x20000028
80006bc: 40006400 .word 0x40006400
080006c0 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80006c0: b580 push {r7, lr}
80006c2: b088 sub sp, #32
80006c4: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006c6: f107 030c add.w r3, r7, #12
80006ca: 2200 movs r2, #0
80006cc: 601a str r2, [r3, #0]
80006ce: 605a str r2, [r3, #4]
80006d0: 609a str r2, [r3, #8]
80006d2: 60da str r2, [r3, #12]
80006d4: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
80006d6: 4b28 ldr r3, [pc, #160] @ (8000778 <MX_GPIO_Init+0xb8>)
80006d8: 695b ldr r3, [r3, #20]
80006da: 4a27 ldr r2, [pc, #156] @ (8000778 <MX_GPIO_Init+0xb8>)
80006dc: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80006e0: 6153 str r3, [r2, #20]
80006e2: 4b25 ldr r3, [pc, #148] @ (8000778 <MX_GPIO_Init+0xb8>)
80006e4: 695b ldr r3, [r3, #20]
80006e6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80006ea: 60bb str r3, [r7, #8]
80006ec: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
80006ee: 4b22 ldr r3, [pc, #136] @ (8000778 <MX_GPIO_Init+0xb8>)
80006f0: 695b ldr r3, [r3, #20]
80006f2: 4a21 ldr r2, [pc, #132] @ (8000778 <MX_GPIO_Init+0xb8>)
80006f4: f443 2380 orr.w r3, r3, #262144 @ 0x40000
80006f8: 6153 str r3, [r2, #20]
80006fa: 4b1f ldr r3, [pc, #124] @ (8000778 <MX_GPIO_Init+0xb8>)
80006fc: 695b ldr r3, [r3, #20]
80006fe: f403 2380 and.w r3, r3, #262144 @ 0x40000
8000702: 607b str r3, [r7, #4]
8000704: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, TSON_R_Pin|TSON_G_Pin|TSON_B_Pin|IMD_LED_Pin
8000706: 2200 movs r2, #0
8000708: 21bf movs r1, #191 @ 0xbf
800070a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800070e: f001 fb57 bl 8001dc0 <HAL_GPIO_WritePin>
|AMS_LED_Pin|TSOFF_LED_Pin|R2D_R_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, R2D_G_Pin|R2D_B_Pin, GPIO_PIN_RESET);
8000712: 2200 movs r2, #0
8000714: 2103 movs r1, #3
8000716: 4819 ldr r0, [pc, #100] @ (800077c <MX_GPIO_Init+0xbc>)
8000718: f001 fb52 bl 8001dc0 <HAL_GPIO_WritePin>
/*Configure GPIO pins : TSON_R_Pin TSON_G_Pin TSON_B_Pin IMD_LED_Pin
AMS_LED_Pin TSOFF_LED_Pin R2D_R_Pin */
GPIO_InitStruct.Pin = TSON_R_Pin|TSON_G_Pin|TSON_B_Pin|IMD_LED_Pin
800071c: 23bf movs r3, #191 @ 0xbf
800071e: 60fb str r3, [r7, #12]
|AMS_LED_Pin|TSOFF_LED_Pin|R2D_R_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000720: 2301 movs r3, #1
8000722: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000724: 2300 movs r3, #0
8000726: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000728: 2300 movs r3, #0
800072a: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800072c: f107 030c add.w r3, r7, #12
8000730: 4619 mov r1, r3
8000732: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000736: f001 f9b1 bl 8001a9c <HAL_GPIO_Init>
/*Configure GPIO pins : R2D_G_Pin R2D_B_Pin */
GPIO_InitStruct.Pin = R2D_G_Pin|R2D_B_Pin;
800073a: 2303 movs r3, #3
800073c: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800073e: 2301 movs r3, #1
8000740: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000742: 2300 movs r3, #0
8000744: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000746: 2300 movs r3, #0
8000748: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800074a: f107 030c add.w r3, r7, #12
800074e: 4619 mov r1, r3
8000750: 480a ldr r0, [pc, #40] @ (800077c <MX_GPIO_Init+0xbc>)
8000752: f001 f9a3 bl 8001a9c <HAL_GPIO_Init>
/*Configure GPIO pins : TSON_BTN_Pin SDC_Out_3V3_Pin SDC_In_3V3_Pin R2D_BTN_Pin
RMode_Out_3V3_Pin */
GPIO_InitStruct.Pin = TSON_BTN_Pin|SDC_Out_3V3_Pin|SDC_In_3V3_Pin|R2D_BTN_Pin
8000756: f248 1338 movw r3, #33080 @ 0x8138
800075a: 60fb str r3, [r7, #12]
|RMode_Out_3V3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800075c: 2300 movs r3, #0
800075e: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000760: 2300 movs r3, #0
8000762: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000764: f107 030c add.w r3, r7, #12
8000768: 4619 mov r1, r3
800076a: 4804 ldr r0, [pc, #16] @ (800077c <MX_GPIO_Init+0xbc>)
800076c: f001 f996 bl 8001a9c <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000770: bf00 nop
8000772: 3720 adds r7, #32
8000774: 46bd mov sp, r7
8000776: bd80 pop {r7, pc}
8000778: 40021000 .word 0x40021000
800077c: 48000400 .word 0x48000400
08000780 <HAL_CAN_RxFifo0MsgPendingCallback>:
/* USER CODE BEGIN 4 */
// CAN RX interrupt handler
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) {
8000780: b580 push {r7, lr}
8000782: b08c sub sp, #48 @ 0x30
8000784: af00 add r7, sp, #0
8000786: 6078 str r0, [r7, #4]
CAN_RxHeaderTypeDef rxHeader;
uint8_t rxData[8];
// Read frame from HW into buffer
if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &rxHeader, rxData) != HAL_OK)
8000788: f107 0308 add.w r3, r7, #8
800078c: f107 0210 add.w r2, r7, #16
8000790: 2100 movs r1, #0
8000792: 6878 ldr r0, [r7, #4]
8000794: f000 fcea bl 800116c <HAL_CAN_GetRxMessage>
8000798: 4603 mov r3, r0
800079a: 2b00 cmp r3, #0
800079c: d001 beq.n 80007a2 <HAL_CAN_RxFifo0MsgPendingCallback+0x22>
Error_Handler();
800079e: f000 f839 bl 8000814 <Error_Handler>
// Discard if it's not for us (shouldn't happen thanks to filter, but just to be sure)
if (rxHeader.StdId == CAN_ID_RX_AMS) {
80007a2: 693b ldr r3, [r7, #16]
80007a4: 2b0a cmp r3, #10
80007a6: d11f bne.n 80007e8 <HAL_CAN_RxFifo0MsgPendingCallback+0x68>
uint8_t ams_info = rxData[0];
80007a8: 7a3b ldrb r3, [r7, #8]
80007aa: f887 302f strb.w r3, [r7, #47] @ 0x2f
uint8_t imd_info = rxData[6];
80007ae: 7bbb ldrb r3, [r7, #14]
80007b0: f887 302e strb.w r3, [r7, #46] @ 0x2e
dash_rx.ams_state = ams_info & 0b01111111;
80007b4: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
80007b8: f003 037f and.w r3, r3, #127 @ 0x7f
80007bc: b2da uxtb r2, r3
80007be: 4b13 ldr r3, [pc, #76] @ (800080c <HAL_CAN_RxFifo0MsgPendingCallback+0x8c>)
80007c0: 701a strb r2, [r3, #0]
dash_rx.sdc_closed = ams_info >> 7;
80007c2: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
80007c6: 09db lsrs r3, r3, #7
80007c8: b2db uxtb r3, r3
80007ca: 461a mov r2, r3
80007cc: 4b0f ldr r3, [pc, #60] @ (800080c <HAL_CAN_RxFifo0MsgPendingCallback+0x8c>)
80007ce: 609a str r2, [r3, #8]
dash_rx.imd_ok = imd_info >> 7;
80007d0: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
80007d4: 09db lsrs r3, r3, #7
80007d6: b2db uxtb r3, r3
80007d8: 461a mov r2, r3
80007da: 4b0c ldr r3, [pc, #48] @ (800080c <HAL_CAN_RxFifo0MsgPendingCallback+0x8c>)
80007dc: 605a str r2, [r3, #4]
ams_last_tick = HAL_GetTick();
80007de: f000 f971 bl 8000ac4 <HAL_GetTick>
80007e2: 4603 mov r3, r0
80007e4: 4a0a ldr r2, [pc, #40] @ (8000810 <HAL_CAN_RxFifo0MsgPendingCallback+0x90>)
80007e6: 6013 str r3, [r2, #0]
}
if (rxHeader.StdId == CAN_ID_RX_R2D) {
80007e8: 693b ldr r3, [r7, #16]
80007ea: f5b3 6f82 cmp.w r3, #1040 @ 0x410
80007ee: d109 bne.n 8000804 <HAL_CAN_RxFifo0MsgPendingCallback+0x84>
uint8_t r2d_info = rxData[1];
80007f0: 7a7b ldrb r3, [r7, #9]
80007f2: f887 302d strb.w r3, [r7, #45] @ 0x2d
dash_rx.r2d_progress = r2d_info & 0b00001111;
80007f6: f897 302d ldrb.w r3, [r7, #45] @ 0x2d
80007fa: f003 030f and.w r3, r3, #15
80007fe: b2da uxtb r2, r3
8000800: 4b02 ldr r3, [pc, #8] @ (800080c <HAL_CAN_RxFifo0MsgPendingCallback+0x8c>)
8000802: 731a strb r2, [r3, #12]
}
}
8000804: bf00 nop
8000806: 3730 adds r7, #48 @ 0x30
8000808: 46bd mov sp, r7
800080a: bd80 pop {r7, pc}
800080c: 200000ac .word 0x200000ac
8000810: 200000bc .word 0x200000bc
08000814 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000814: b480 push {r7}
8000816: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000818: b672 cpsid i
}
800081a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800081c: bf00 nop
800081e: e7fd b.n 800081c <Error_Handler+0x8>
08000820 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000820: b480 push {r7}
8000822: b083 sub sp, #12
8000824: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000826: 4b0f ldr r3, [pc, #60] @ (8000864 <HAL_MspInit+0x44>)
8000828: 699b ldr r3, [r3, #24]
800082a: 4a0e ldr r2, [pc, #56] @ (8000864 <HAL_MspInit+0x44>)
800082c: f043 0301 orr.w r3, r3, #1
8000830: 6193 str r3, [r2, #24]
8000832: 4b0c ldr r3, [pc, #48] @ (8000864 <HAL_MspInit+0x44>)
8000834: 699b ldr r3, [r3, #24]
8000836: f003 0301 and.w r3, r3, #1
800083a: 607b str r3, [r7, #4]
800083c: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800083e: 4b09 ldr r3, [pc, #36] @ (8000864 <HAL_MspInit+0x44>)
8000840: 69db ldr r3, [r3, #28]
8000842: 4a08 ldr r2, [pc, #32] @ (8000864 <HAL_MspInit+0x44>)
8000844: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000848: 61d3 str r3, [r2, #28]
800084a: 4b06 ldr r3, [pc, #24] @ (8000864 <HAL_MspInit+0x44>)
800084c: 69db ldr r3, [r3, #28]
800084e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000852: 603b str r3, [r7, #0]
8000854: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000856: bf00 nop
8000858: 370c adds r7, #12
800085a: 46bd mov sp, r7
800085c: f85d 7b04 ldr.w r7, [sp], #4
8000860: 4770 bx lr
8000862: bf00 nop
8000864: 40021000 .word 0x40021000
08000868 <HAL_CAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
8000868: b580 push {r7, lr}
800086a: b08a sub sp, #40 @ 0x28
800086c: af00 add r7, sp, #0
800086e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000870: f107 0314 add.w r3, r7, #20
8000874: 2200 movs r2, #0
8000876: 601a str r2, [r3, #0]
8000878: 605a str r2, [r3, #4]
800087a: 609a str r2, [r3, #8]
800087c: 60da str r2, [r3, #12]
800087e: 611a str r2, [r3, #16]
if(hcan->Instance==CAN)
8000880: 687b ldr r3, [r7, #4]
8000882: 681b ldr r3, [r3, #0]
8000884: 4a20 ldr r2, [pc, #128] @ (8000908 <HAL_CAN_MspInit+0xa0>)
8000886: 4293 cmp r3, r2
8000888: d139 bne.n 80008fe <HAL_CAN_MspInit+0x96>
{
/* USER CODE BEGIN CAN_MspInit 0 */
/* USER CODE END CAN_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
800088a: 4b20 ldr r3, [pc, #128] @ (800090c <HAL_CAN_MspInit+0xa4>)
800088c: 69db ldr r3, [r3, #28]
800088e: 4a1f ldr r2, [pc, #124] @ (800090c <HAL_CAN_MspInit+0xa4>)
8000890: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8000894: 61d3 str r3, [r2, #28]
8000896: 4b1d ldr r3, [pc, #116] @ (800090c <HAL_CAN_MspInit+0xa4>)
8000898: 69db ldr r3, [r3, #28]
800089a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800089e: 613b str r3, [r7, #16]
80008a0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80008a2: 4b1a ldr r3, [pc, #104] @ (800090c <HAL_CAN_MspInit+0xa4>)
80008a4: 695b ldr r3, [r3, #20]
80008a6: 4a19 ldr r2, [pc, #100] @ (800090c <HAL_CAN_MspInit+0xa4>)
80008a8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80008ac: 6153 str r3, [r2, #20]
80008ae: 4b17 ldr r3, [pc, #92] @ (800090c <HAL_CAN_MspInit+0xa4>)
80008b0: 695b ldr r3, [r3, #20]
80008b2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80008b6: 60fb str r3, [r7, #12]
80008b8: 68fb ldr r3, [r7, #12]
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
80008ba: f44f 53c0 mov.w r3, #6144 @ 0x1800
80008be: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80008c0: 2302 movs r3, #2
80008c2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008c4: 2300 movs r3, #0
80008c6: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80008c8: 2303 movs r3, #3
80008ca: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
80008cc: 2309 movs r3, #9
80008ce: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80008d0: f107 0314 add.w r3, r7, #20
80008d4: 4619 mov r1, r3
80008d6: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80008da: f001 f8df bl 8001a9c <HAL_GPIO_Init>
/* CAN interrupt Init */
HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0);
80008de: 2200 movs r2, #0
80008e0: 2100 movs r1, #0
80008e2: 2014 movs r0, #20
80008e4: f001 f8a3 bl 8001a2e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
80008e8: 2014 movs r0, #20
80008ea: f001 f8bc bl 8001a66 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
80008ee: 2200 movs r2, #0
80008f0: 2100 movs r1, #0
80008f2: 2015 movs r0, #21
80008f4: f001 f89b bl 8001a2e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
80008f8: 2015 movs r0, #21
80008fa: f001 f8b4 bl 8001a66 <HAL_NVIC_EnableIRQ>
/* USER CODE END CAN_MspInit 1 */
}
}
80008fe: bf00 nop
8000900: 3728 adds r7, #40 @ 0x28
8000902: 46bd mov sp, r7
8000904: bd80 pop {r7, pc}
8000906: bf00 nop
8000908: 40006400 .word 0x40006400
800090c: 40021000 .word 0x40021000
08000910 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000910: b480 push {r7}
8000912: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000914: bf00 nop
8000916: e7fd b.n 8000914 <NMI_Handler+0x4>
08000918 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000918: b480 push {r7}
800091a: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800091c: bf00 nop
800091e: e7fd b.n 800091c <HardFault_Handler+0x4>
08000920 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000920: b480 push {r7}
8000922: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000924: bf00 nop
8000926: e7fd b.n 8000924 <MemManage_Handler+0x4>
08000928 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000928: b480 push {r7}
800092a: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800092c: bf00 nop
800092e: e7fd b.n 800092c <BusFault_Handler+0x4>
08000930 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000930: b480 push {r7}
8000932: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000934: bf00 nop
8000936: e7fd b.n 8000934 <UsageFault_Handler+0x4>
08000938 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000938: b480 push {r7}
800093a: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800093c: bf00 nop
800093e: 46bd mov sp, r7
8000940: f85d 7b04 ldr.w r7, [sp], #4
8000944: 4770 bx lr
08000946 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000946: b480 push {r7}
8000948: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800094a: bf00 nop
800094c: 46bd mov sp, r7
800094e: f85d 7b04 ldr.w r7, [sp], #4
8000952: 4770 bx lr
08000954 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000954: b480 push {r7}
8000956: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000958: bf00 nop
800095a: 46bd mov sp, r7
800095c: f85d 7b04 ldr.w r7, [sp], #4
8000960: 4770 bx lr
08000962 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000962: b580 push {r7, lr}
8000964: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000966: f000 f899 bl 8000a9c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800096a: bf00 nop
800096c: bd80 pop {r7, pc}
...
08000970 <USB_LP_CAN_RX0_IRQHandler>:
/**
* @brief This function handles USB low priority or CAN_RX0 interrupts.
*/
void USB_LP_CAN_RX0_IRQHandler(void)
{
8000970: b580 push {r7, lr}
8000972: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN_RX0_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
8000974: 4802 ldr r0, [pc, #8] @ (8000980 <USB_LP_CAN_RX0_IRQHandler+0x10>)
8000976: f000 fd41 bl 80013fc <HAL_CAN_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN_RX0_IRQn 1 */
}
800097a: bf00 nop
800097c: bd80 pop {r7, pc}
800097e: bf00 nop
8000980: 20000028 .word 0x20000028
08000984 <CAN_RX1_IRQHandler>:
/**
* @brief This function handles CAN RX1 interrupt.
*/
void CAN_RX1_IRQHandler(void)
{
8000984: b580 push {r7, lr}
8000986: af00 add r7, sp, #0
/* USER CODE BEGIN CAN_RX1_IRQn 0 */
/* USER CODE END CAN_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
8000988: 4802 ldr r0, [pc, #8] @ (8000994 <CAN_RX1_IRQHandler+0x10>)
800098a: f000 fd37 bl 80013fc <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN_RX1_IRQn 1 */
/* USER CODE END CAN_RX1_IRQn 1 */
}
800098e: bf00 nop
8000990: bd80 pop {r7, pc}
8000992: bf00 nop
8000994: 20000028 .word 0x20000028
08000998 <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
8000998: b480 push {r7}
800099a: af00 add r7, sp, #0
/* FPU settings --------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
800099c: 4b06 ldr r3, [pc, #24] @ (80009b8 <SystemInit+0x20>)
800099e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80009a2: 4a05 ldr r2, [pc, #20] @ (80009b8 <SystemInit+0x20>)
80009a4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80009a8: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80009ac: bf00 nop
80009ae: 46bd mov sp, r7
80009b0: f85d 7b04 ldr.w r7, [sp], #4
80009b4: 4770 bx lr
80009b6: bf00 nop
80009b8: e000ed00 .word 0xe000ed00
080009bc <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
80009bc: f8df d034 ldr.w sp, [pc, #52] @ 80009f4 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
80009c0: f7ff ffea bl 8000998 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80009c4: 480c ldr r0, [pc, #48] @ (80009f8 <LoopForever+0x6>)
ldr r1, =_edata
80009c6: 490d ldr r1, [pc, #52] @ (80009fc <LoopForever+0xa>)
ldr r2, =_sidata
80009c8: 4a0d ldr r2, [pc, #52] @ (8000a00 <LoopForever+0xe>)
movs r3, #0
80009ca: 2300 movs r3, #0
b LoopCopyDataInit
80009cc: e002 b.n 80009d4 <LoopCopyDataInit>
080009ce <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80009ce: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80009d0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80009d2: 3304 adds r3, #4
080009d4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80009d4: 18c4 adds r4, r0, r3
cmp r4, r1
80009d6: 428c cmp r4, r1
bcc CopyDataInit
80009d8: d3f9 bcc.n 80009ce <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80009da: 4a0a ldr r2, [pc, #40] @ (8000a04 <LoopForever+0x12>)
ldr r4, =_ebss
80009dc: 4c0a ldr r4, [pc, #40] @ (8000a08 <LoopForever+0x16>)
movs r3, #0
80009de: 2300 movs r3, #0
b LoopFillZerobss
80009e0: e001 b.n 80009e6 <LoopFillZerobss>
080009e2 <FillZerobss>:
FillZerobss:
str r3, [r2]
80009e2: 6013 str r3, [r2, #0]
adds r2, r2, #4
80009e4: 3204 adds r2, #4
080009e6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80009e6: 42a2 cmp r2, r4
bcc FillZerobss
80009e8: d3fb bcc.n 80009e2 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80009ea: f002 fc17 bl 800321c <__libc_init_array>
/* Call the application's entry point.*/
bl main
80009ee: f7ff fbeb bl 80001c8 <main>
080009f2 <LoopForever>:
LoopForever:
b LoopForever
80009f2: e7fe b.n 80009f2 <LoopForever>
ldr sp, =_estack /* Atollic update: set stack pointer */
80009f4: 20008000 .word 0x20008000
ldr r0, =_sdata
80009f8: 20000000 .word 0x20000000
ldr r1, =_edata
80009fc: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000a00: 080032b4 .word 0x080032b4
ldr r2, =_sbss
8000a04: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000a08: 200000c8 .word 0x200000c8
08000a0c <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000a0c: e7fe b.n 8000a0c <ADC1_2_IRQHandler>
...
08000a10 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000a10: b580 push {r7, lr}
8000a12: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000a14: 4b08 ldr r3, [pc, #32] @ (8000a38 <HAL_Init+0x28>)
8000a16: 681b ldr r3, [r3, #0]
8000a18: 4a07 ldr r2, [pc, #28] @ (8000a38 <HAL_Init+0x28>)
8000a1a: f043 0310 orr.w r3, r3, #16
8000a1e: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000a20: 2003 movs r0, #3
8000a22: f000 fff9 bl 8001a18 <HAL_NVIC_SetPriorityGrouping>
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000a26: 200f movs r0, #15
8000a28: f000 f808 bl 8000a3c <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000a2c: f7ff fef8 bl 8000820 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000a30: 2300 movs r3, #0
}
8000a32: 4618 mov r0, r3
8000a34: bd80 pop {r7, pc}
8000a36: bf00 nop
8000a38: 40022000 .word 0x40022000
08000a3c <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000a3c: b580 push {r7, lr}
8000a3e: b082 sub sp, #8
8000a40: af00 add r7, sp, #0
8000a42: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000a44: 4b12 ldr r3, [pc, #72] @ (8000a90 <HAL_InitTick+0x54>)
8000a46: 681a ldr r2, [r3, #0]
8000a48: 4b12 ldr r3, [pc, #72] @ (8000a94 <HAL_InitTick+0x58>)
8000a4a: 781b ldrb r3, [r3, #0]
8000a4c: 4619 mov r1, r3
8000a4e: f44f 737a mov.w r3, #1000 @ 0x3e8
8000a52: fbb3 f3f1 udiv r3, r3, r1
8000a56: fbb2 f3f3 udiv r3, r2, r3
8000a5a: 4618 mov r0, r3
8000a5c: f001 f811 bl 8001a82 <HAL_SYSTICK_Config>
8000a60: 4603 mov r3, r0
8000a62: 2b00 cmp r3, #0
8000a64: d001 beq.n 8000a6a <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000a66: 2301 movs r3, #1
8000a68: e00e b.n 8000a88 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000a6a: 687b ldr r3, [r7, #4]
8000a6c: 2b0f cmp r3, #15
8000a6e: d80a bhi.n 8000a86 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000a70: 2200 movs r2, #0
8000a72: 6879 ldr r1, [r7, #4]
8000a74: f04f 30ff mov.w r0, #4294967295
8000a78: f000 ffd9 bl 8001a2e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000a7c: 4a06 ldr r2, [pc, #24] @ (8000a98 <HAL_InitTick+0x5c>)
8000a7e: 687b ldr r3, [r7, #4]
8000a80: 6013 str r3, [r2, #0]
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000a82: 2300 movs r3, #0
8000a84: e000 b.n 8000a88 <HAL_InitTick+0x4c>
return HAL_ERROR;
8000a86: 2301 movs r3, #1
}
8000a88: 4618 mov r0, r3
8000a8a: 3708 adds r7, #8
8000a8c: 46bd mov sp, r7
8000a8e: bd80 pop {r7, pc}
8000a90: 20000000 .word 0x20000000
8000a94: 20000008 .word 0x20000008
8000a98: 20000004 .word 0x20000004
08000a9c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000a9c: b480 push {r7}
8000a9e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000aa0: 4b06 ldr r3, [pc, #24] @ (8000abc <HAL_IncTick+0x20>)
8000aa2: 781b ldrb r3, [r3, #0]
8000aa4: 461a mov r2, r3
8000aa6: 4b06 ldr r3, [pc, #24] @ (8000ac0 <HAL_IncTick+0x24>)
8000aa8: 681b ldr r3, [r3, #0]
8000aaa: 4413 add r3, r2
8000aac: 4a04 ldr r2, [pc, #16] @ (8000ac0 <HAL_IncTick+0x24>)
8000aae: 6013 str r3, [r2, #0]
}
8000ab0: bf00 nop
8000ab2: 46bd mov sp, r7
8000ab4: f85d 7b04 ldr.w r7, [sp], #4
8000ab8: 4770 bx lr
8000aba: bf00 nop
8000abc: 20000008 .word 0x20000008
8000ac0: 200000c4 .word 0x200000c4
08000ac4 <HAL_GetTick>:
* @note The function is declared as __Weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000ac4: b480 push {r7}
8000ac6: af00 add r7, sp, #0
return uwTick;
8000ac8: 4b03 ldr r3, [pc, #12] @ (8000ad8 <HAL_GetTick+0x14>)
8000aca: 681b ldr r3, [r3, #0]
}
8000acc: 4618 mov r0, r3
8000ace: 46bd mov sp, r7
8000ad0: f85d 7b04 ldr.w r7, [sp], #4
8000ad4: 4770 bx lr
8000ad6: bf00 nop
8000ad8: 200000c4 .word 0x200000c4
08000adc <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000adc: b580 push {r7, lr}
8000ade: b084 sub sp, #16
8000ae0: af00 add r7, sp, #0
8000ae2: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000ae4: f7ff ffee bl 8000ac4 <HAL_GetTick>
8000ae8: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000aea: 687b ldr r3, [r7, #4]
8000aec: 60fb str r3, [r7, #12]
/* Add freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8000aee: 68fb ldr r3, [r7, #12]
8000af0: f1b3 3fff cmp.w r3, #4294967295
8000af4: d005 beq.n 8000b02 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8000af6: 4b0a ldr r3, [pc, #40] @ (8000b20 <HAL_Delay+0x44>)
8000af8: 781b ldrb r3, [r3, #0]
8000afa: 461a mov r2, r3
8000afc: 68fb ldr r3, [r7, #12]
8000afe: 4413 add r3, r2
8000b00: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8000b02: bf00 nop
8000b04: f7ff ffde bl 8000ac4 <HAL_GetTick>
8000b08: 4602 mov r2, r0
8000b0a: 68bb ldr r3, [r7, #8]
8000b0c: 1ad3 subs r3, r2, r3
8000b0e: 68fa ldr r2, [r7, #12]
8000b10: 429a cmp r2, r3
8000b12: d8f7 bhi.n 8000b04 <HAL_Delay+0x28>
{
}
}
8000b14: bf00 nop
8000b16: bf00 nop
8000b18: 3710 adds r7, #16
8000b1a: 46bd mov sp, r7
8000b1c: bd80 pop {r7, pc}
8000b1e: bf00 nop
8000b20: 20000008 .word 0x20000008
08000b24 <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
8000b24: b580 push {r7, lr}
8000b26: b084 sub sp, #16
8000b28: af00 add r7, sp, #0
8000b2a: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
8000b2c: 687b ldr r3, [r7, #4]
8000b2e: 2b00 cmp r3, #0
8000b30: d101 bne.n 8000b36 <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
8000b32: 2301 movs r3, #1
8000b34: e11c b.n 8000d70 <HAL_CAN_Init+0x24c>
assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
if (hcan->State == HAL_CAN_STATE_RESET)
8000b36: 687b ldr r3, [r7, #4]
8000b38: f893 3020 ldrb.w r3, [r3, #32]
8000b3c: b2db uxtb r3, r3
8000b3e: 2b00 cmp r3, #0
8000b40: d131 bne.n 8000ba6 <HAL_CAN_Init+0x82>
{
/* Reset callbacks to legacy functions */
hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */
8000b42: 687b ldr r3, [r7, #4]
8000b44: 4a8c ldr r2, [pc, #560] @ (8000d78 <HAL_CAN_Init+0x254>)
8000b46: 641a str r2, [r3, #64] @ 0x40
hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */
8000b48: 687b ldr r3, [r7, #4]
8000b4a: 4a8c ldr r2, [pc, #560] @ (8000d7c <HAL_CAN_Init+0x258>)
8000b4c: 645a str r2, [r3, #68] @ 0x44
hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */
8000b4e: 687b ldr r3, [r7, #4]
8000b50: 4a8b ldr r2, [pc, #556] @ (8000d80 <HAL_CAN_Init+0x25c>)
8000b52: 649a str r2, [r3, #72] @ 0x48
hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */
8000b54: 687b ldr r3, [r7, #4]
8000b56: 4a8b ldr r2, [pc, #556] @ (8000d84 <HAL_CAN_Init+0x260>)
8000b58: 64da str r2, [r3, #76] @ 0x4c
hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
8000b5a: 687b ldr r3, [r7, #4]
8000b5c: 4a8a ldr r2, [pc, #552] @ (8000d88 <HAL_CAN_Init+0x264>)
8000b5e: 629a str r2, [r3, #40] @ 0x28
hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
8000b60: 687b ldr r3, [r7, #4]
8000b62: 4a8a ldr r2, [pc, #552] @ (8000d8c <HAL_CAN_Init+0x268>)
8000b64: 62da str r2, [r3, #44] @ 0x2c
hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
8000b66: 687b ldr r3, [r7, #4]
8000b68: 4a89 ldr r2, [pc, #548] @ (8000d90 <HAL_CAN_Init+0x26c>)
8000b6a: 631a str r2, [r3, #48] @ 0x30
hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */
8000b6c: 687b ldr r3, [r7, #4]
8000b6e: 4a89 ldr r2, [pc, #548] @ (8000d94 <HAL_CAN_Init+0x270>)
8000b70: 635a str r2, [r3, #52] @ 0x34
hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */
8000b72: 687b ldr r3, [r7, #4]
8000b74: 4a88 ldr r2, [pc, #544] @ (8000d98 <HAL_CAN_Init+0x274>)
8000b76: 639a str r2, [r3, #56] @ 0x38
hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */
8000b78: 687b ldr r3, [r7, #4]
8000b7a: 4a88 ldr r2, [pc, #544] @ (8000d9c <HAL_CAN_Init+0x278>)
8000b7c: 63da str r2, [r3, #60] @ 0x3c
hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */
8000b7e: 687b ldr r3, [r7, #4]
8000b80: 4a87 ldr r2, [pc, #540] @ (8000da0 <HAL_CAN_Init+0x27c>)
8000b82: 651a str r2, [r3, #80] @ 0x50
hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */
8000b84: 687b ldr r3, [r7, #4]
8000b86: 4a87 ldr r2, [pc, #540] @ (8000da4 <HAL_CAN_Init+0x280>)
8000b88: 655a str r2, [r3, #84] @ 0x54
hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */
8000b8a: 687b ldr r3, [r7, #4]
8000b8c: 4a86 ldr r2, [pc, #536] @ (8000da8 <HAL_CAN_Init+0x284>)
8000b8e: 659a str r2, [r3, #88] @ 0x58
if (hcan->MspInitCallback == NULL)
8000b90: 687b ldr r3, [r7, #4]
8000b92: 6ddb ldr r3, [r3, #92] @ 0x5c
8000b94: 2b00 cmp r3, #0
8000b96: d102 bne.n 8000b9e <HAL_CAN_Init+0x7a>
{
hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
8000b98: 687b ldr r3, [r7, #4]
8000b9a: 4a84 ldr r2, [pc, #528] @ (8000dac <HAL_CAN_Init+0x288>)
8000b9c: 65da str r2, [r3, #92] @ 0x5c
}
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
8000b9e: 687b ldr r3, [r7, #4]
8000ba0: 6ddb ldr r3, [r3, #92] @ 0x5c
8000ba2: 6878 ldr r0, [r7, #4]
8000ba4: 4798 blx r3
HAL_CAN_MspInit(hcan);
}
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8000ba6: 687b ldr r3, [r7, #4]
8000ba8: 681b ldr r3, [r3, #0]
8000baa: 681a ldr r2, [r3, #0]
8000bac: 687b ldr r3, [r7, #4]
8000bae: 681b ldr r3, [r3, #0]
8000bb0: f042 0201 orr.w r2, r2, #1
8000bb4: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000bb6: f7ff ff85 bl 8000ac4 <HAL_GetTick>
8000bba: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000bbc: e012 b.n 8000be4 <HAL_CAN_Init+0xc0>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000bbe: f7ff ff81 bl 8000ac4 <HAL_GetTick>
8000bc2: 4602 mov r2, r0
8000bc4: 68fb ldr r3, [r7, #12]
8000bc6: 1ad3 subs r3, r2, r3
8000bc8: 2b0a cmp r3, #10
8000bca: d90b bls.n 8000be4 <HAL_CAN_Init+0xc0>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000bcc: 687b ldr r3, [r7, #4]
8000bce: 6a5b ldr r3, [r3, #36] @ 0x24
8000bd0: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8000bd4: 687b ldr r3, [r7, #4]
8000bd6: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000bd8: 687b ldr r3, [r7, #4]
8000bda: 2205 movs r2, #5
8000bdc: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000be0: 2301 movs r3, #1
8000be2: e0c5 b.n 8000d70 <HAL_CAN_Init+0x24c>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000be4: 687b ldr r3, [r7, #4]
8000be6: 681b ldr r3, [r3, #0]
8000be8: 685b ldr r3, [r3, #4]
8000bea: f003 0301 and.w r3, r3, #1
8000bee: 2b00 cmp r3, #0
8000bf0: d0e5 beq.n 8000bbe <HAL_CAN_Init+0x9a>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
8000bf2: 687b ldr r3, [r7, #4]
8000bf4: 681b ldr r3, [r3, #0]
8000bf6: 681a ldr r2, [r3, #0]
8000bf8: 687b ldr r3, [r7, #4]
8000bfa: 681b ldr r3, [r3, #0]
8000bfc: f022 0202 bic.w r2, r2, #2
8000c00: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000c02: f7ff ff5f bl 8000ac4 <HAL_GetTick>
8000c06: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000c08: e012 b.n 8000c30 <HAL_CAN_Init+0x10c>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000c0a: f7ff ff5b bl 8000ac4 <HAL_GetTick>
8000c0e: 4602 mov r2, r0
8000c10: 68fb ldr r3, [r7, #12]
8000c12: 1ad3 subs r3, r2, r3
8000c14: 2b0a cmp r3, #10
8000c16: d90b bls.n 8000c30 <HAL_CAN_Init+0x10c>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000c18: 687b ldr r3, [r7, #4]
8000c1a: 6a5b ldr r3, [r3, #36] @ 0x24
8000c1c: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8000c20: 687b ldr r3, [r7, #4]
8000c22: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000c24: 687b ldr r3, [r7, #4]
8000c26: 2205 movs r2, #5
8000c28: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000c2c: 2301 movs r3, #1
8000c2e: e09f b.n 8000d70 <HAL_CAN_Init+0x24c>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000c30: 687b ldr r3, [r7, #4]
8000c32: 681b ldr r3, [r3, #0]
8000c34: 685b ldr r3, [r3, #4]
8000c36: f003 0302 and.w r3, r3, #2
8000c3a: 2b00 cmp r3, #0
8000c3c: d1e5 bne.n 8000c0a <HAL_CAN_Init+0xe6>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
8000c3e: 687b ldr r3, [r7, #4]
8000c40: 7e1b ldrb r3, [r3, #24]
8000c42: 2b01 cmp r3, #1
8000c44: d108 bne.n 8000c58 <HAL_CAN_Init+0x134>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000c46: 687b ldr r3, [r7, #4]
8000c48: 681b ldr r3, [r3, #0]
8000c4a: 681a ldr r2, [r3, #0]
8000c4c: 687b ldr r3, [r7, #4]
8000c4e: 681b ldr r3, [r3, #0]
8000c50: f042 0280 orr.w r2, r2, #128 @ 0x80
8000c54: 601a str r2, [r3, #0]
8000c56: e007 b.n 8000c68 <HAL_CAN_Init+0x144>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000c58: 687b ldr r3, [r7, #4]
8000c5a: 681b ldr r3, [r3, #0]
8000c5c: 681a ldr r2, [r3, #0]
8000c5e: 687b ldr r3, [r7, #4]
8000c60: 681b ldr r3, [r3, #0]
8000c62: f022 0280 bic.w r2, r2, #128 @ 0x80
8000c66: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
8000c68: 687b ldr r3, [r7, #4]
8000c6a: 7e5b ldrb r3, [r3, #25]
8000c6c: 2b01 cmp r3, #1
8000c6e: d108 bne.n 8000c82 <HAL_CAN_Init+0x15e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000c70: 687b ldr r3, [r7, #4]
8000c72: 681b ldr r3, [r3, #0]
8000c74: 681a ldr r2, [r3, #0]
8000c76: 687b ldr r3, [r7, #4]
8000c78: 681b ldr r3, [r3, #0]
8000c7a: f042 0240 orr.w r2, r2, #64 @ 0x40
8000c7e: 601a str r2, [r3, #0]
8000c80: e007 b.n 8000c92 <HAL_CAN_Init+0x16e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000c82: 687b ldr r3, [r7, #4]
8000c84: 681b ldr r3, [r3, #0]
8000c86: 681a ldr r2, [r3, #0]
8000c88: 687b ldr r3, [r7, #4]
8000c8a: 681b ldr r3, [r3, #0]
8000c8c: f022 0240 bic.w r2, r2, #64 @ 0x40
8000c90: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
8000c92: 687b ldr r3, [r7, #4]
8000c94: 7e9b ldrb r3, [r3, #26]
8000c96: 2b01 cmp r3, #1
8000c98: d108 bne.n 8000cac <HAL_CAN_Init+0x188>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000c9a: 687b ldr r3, [r7, #4]
8000c9c: 681b ldr r3, [r3, #0]
8000c9e: 681a ldr r2, [r3, #0]
8000ca0: 687b ldr r3, [r7, #4]
8000ca2: 681b ldr r3, [r3, #0]
8000ca4: f042 0220 orr.w r2, r2, #32
8000ca8: 601a str r2, [r3, #0]
8000caa: e007 b.n 8000cbc <HAL_CAN_Init+0x198>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000cac: 687b ldr r3, [r7, #4]
8000cae: 681b ldr r3, [r3, #0]
8000cb0: 681a ldr r2, [r3, #0]
8000cb2: 687b ldr r3, [r7, #4]
8000cb4: 681b ldr r3, [r3, #0]
8000cb6: f022 0220 bic.w r2, r2, #32
8000cba: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
8000cbc: 687b ldr r3, [r7, #4]
8000cbe: 7edb ldrb r3, [r3, #27]
8000cc0: 2b01 cmp r3, #1
8000cc2: d108 bne.n 8000cd6 <HAL_CAN_Init+0x1b2>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000cc4: 687b ldr r3, [r7, #4]
8000cc6: 681b ldr r3, [r3, #0]
8000cc8: 681a ldr r2, [r3, #0]
8000cca: 687b ldr r3, [r7, #4]
8000ccc: 681b ldr r3, [r3, #0]
8000cce: f022 0210 bic.w r2, r2, #16
8000cd2: 601a str r2, [r3, #0]
8000cd4: e007 b.n 8000ce6 <HAL_CAN_Init+0x1c2>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000cd6: 687b ldr r3, [r7, #4]
8000cd8: 681b ldr r3, [r3, #0]
8000cda: 681a ldr r2, [r3, #0]
8000cdc: 687b ldr r3, [r7, #4]
8000cde: 681b ldr r3, [r3, #0]
8000ce0: f042 0210 orr.w r2, r2, #16
8000ce4: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
8000ce6: 687b ldr r3, [r7, #4]
8000ce8: 7f1b ldrb r3, [r3, #28]
8000cea: 2b01 cmp r3, #1
8000cec: d108 bne.n 8000d00 <HAL_CAN_Init+0x1dc>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000cee: 687b ldr r3, [r7, #4]
8000cf0: 681b ldr r3, [r3, #0]
8000cf2: 681a ldr r2, [r3, #0]
8000cf4: 687b ldr r3, [r7, #4]
8000cf6: 681b ldr r3, [r3, #0]
8000cf8: f042 0208 orr.w r2, r2, #8
8000cfc: 601a str r2, [r3, #0]
8000cfe: e007 b.n 8000d10 <HAL_CAN_Init+0x1ec>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000d00: 687b ldr r3, [r7, #4]
8000d02: 681b ldr r3, [r3, #0]
8000d04: 681a ldr r2, [r3, #0]
8000d06: 687b ldr r3, [r7, #4]
8000d08: 681b ldr r3, [r3, #0]
8000d0a: f022 0208 bic.w r2, r2, #8
8000d0e: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
8000d10: 687b ldr r3, [r7, #4]
8000d12: 7f5b ldrb r3, [r3, #29]
8000d14: 2b01 cmp r3, #1
8000d16: d108 bne.n 8000d2a <HAL_CAN_Init+0x206>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000d18: 687b ldr r3, [r7, #4]
8000d1a: 681b ldr r3, [r3, #0]
8000d1c: 681a ldr r2, [r3, #0]
8000d1e: 687b ldr r3, [r7, #4]
8000d20: 681b ldr r3, [r3, #0]
8000d22: f042 0204 orr.w r2, r2, #4
8000d26: 601a str r2, [r3, #0]
8000d28: e007 b.n 8000d3a <HAL_CAN_Init+0x216>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000d2a: 687b ldr r3, [r7, #4]
8000d2c: 681b ldr r3, [r3, #0]
8000d2e: 681a ldr r2, [r3, #0]
8000d30: 687b ldr r3, [r7, #4]
8000d32: 681b ldr r3, [r3, #0]
8000d34: f022 0204 bic.w r2, r2, #4
8000d38: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
8000d3a: 687b ldr r3, [r7, #4]
8000d3c: 689a ldr r2, [r3, #8]
8000d3e: 687b ldr r3, [r7, #4]
8000d40: 68db ldr r3, [r3, #12]
8000d42: 431a orrs r2, r3
8000d44: 687b ldr r3, [r7, #4]
8000d46: 691b ldr r3, [r3, #16]
8000d48: 431a orrs r2, r3
8000d4a: 687b ldr r3, [r7, #4]
8000d4c: 695b ldr r3, [r3, #20]
8000d4e: ea42 0103 orr.w r1, r2, r3
8000d52: 687b ldr r3, [r7, #4]
8000d54: 685b ldr r3, [r3, #4]
8000d56: 1e5a subs r2, r3, #1
8000d58: 687b ldr r3, [r7, #4]
8000d5a: 681b ldr r3, [r3, #0]
8000d5c: 430a orrs r2, r1
8000d5e: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8000d60: 687b ldr r3, [r7, #4]
8000d62: 2200 movs r2, #0
8000d64: 625a str r2, [r3, #36] @ 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
8000d66: 687b ldr r3, [r7, #4]
8000d68: 2201 movs r2, #1
8000d6a: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
8000d6e: 2300 movs r3, #0
}
8000d70: 4618 mov r0, r3
8000d72: 3710 adds r7, #16
8000d74: 46bd mov sp, r7
8000d76: bd80 pop {r7, pc}
8000d78: 08000781 .word 0x08000781
8000d7c: 080017ff .word 0x080017ff
8000d80: 08001813 .word 0x08001813
8000d84: 08001827 .word 0x08001827
8000d88: 08001787 .word 0x08001787
8000d8c: 0800179b .word 0x0800179b
8000d90: 080017af .word 0x080017af
8000d94: 080017c3 .word 0x080017c3
8000d98: 080017d7 .word 0x080017d7
8000d9c: 080017eb .word 0x080017eb
8000da0: 0800183b .word 0x0800183b
8000da4: 0800184f .word 0x0800184f
8000da8: 08001863 .word 0x08001863
8000dac: 08000869 .word 0x08000869
08000db0 <HAL_CAN_ConfigFilter>:
* @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
{
8000db0: b480 push {r7}
8000db2: b087 sub sp, #28
8000db4: af00 add r7, sp, #0
8000db6: 6078 str r0, [r7, #4]
8000db8: 6039 str r1, [r7, #0]
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
8000dba: 687b ldr r3, [r7, #4]
8000dbc: 681b ldr r3, [r3, #0]
8000dbe: 617b str r3, [r7, #20]
HAL_CAN_StateTypeDef state = hcan->State;
8000dc0: 687b ldr r3, [r7, #4]
8000dc2: f893 3020 ldrb.w r3, [r3, #32]
8000dc6: 74fb strb r3, [r7, #19]
if ((state == HAL_CAN_STATE_READY) ||
8000dc8: 7cfb ldrb r3, [r7, #19]
8000dca: 2b01 cmp r3, #1
8000dcc: d003 beq.n 8000dd6 <HAL_CAN_ConfigFilter+0x26>
8000dce: 7cfb ldrb r3, [r7, #19]
8000dd0: 2b02 cmp r3, #2
8000dd2: f040 80aa bne.w 8000f2a <HAL_CAN_ConfigFilter+0x17a>
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
8000dd6: 697b ldr r3, [r7, #20]
8000dd8: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200
8000ddc: f043 0201 orr.w r2, r3, #1
8000de0: 697b ldr r3, [r7, #20]
8000de2: f8c3 2200 str.w r2, [r3, #512] @ 0x200
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
8000de6: 683b ldr r3, [r7, #0]
8000de8: 695b ldr r3, [r3, #20]
8000dea: f003 031f and.w r3, r3, #31
8000dee: 2201 movs r2, #1
8000df0: fa02 f303 lsl.w r3, r2, r3
8000df4: 60fb str r3, [r7, #12]
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
8000df6: 697b ldr r3, [r7, #20]
8000df8: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c
8000dfc: 68fb ldr r3, [r7, #12]
8000dfe: 43db mvns r3, r3
8000e00: 401a ands r2, r3
8000e02: 697b ldr r3, [r7, #20]
8000e04: f8c3 221c str.w r2, [r3, #540] @ 0x21c
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
8000e08: 683b ldr r3, [r7, #0]
8000e0a: 69db ldr r3, [r3, #28]
8000e0c: 2b00 cmp r3, #0
8000e0e: d123 bne.n 8000e58 <HAL_CAN_ConfigFilter+0xa8>
{
/* 16-bit scale for the filter */
CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
8000e10: 697b ldr r3, [r7, #20]
8000e12: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c
8000e16: 68fb ldr r3, [r7, #12]
8000e18: 43db mvns r3, r3
8000e1a: 401a ands r2, r3
8000e1c: 697b ldr r3, [r7, #20]
8000e1e: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8000e22: 683b ldr r3, [r7, #0]
8000e24: 68db ldr r3, [r3, #12]
8000e26: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8000e28: 683b ldr r3, [r7, #0]
8000e2a: 685b ldr r3, [r3, #4]
8000e2c: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000e2e: 683a ldr r2, [r7, #0]
8000e30: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8000e32: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000e34: 697b ldr r3, [r7, #20]
8000e36: 3248 adds r2, #72 @ 0x48
8000e38: f843 1032 str.w r1, [r3, r2, lsl #3]
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000e3c: 683b ldr r3, [r7, #0]
8000e3e: 689b ldr r3, [r3, #8]
8000e40: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
8000e42: 683b ldr r3, [r7, #0]
8000e44: 681b ldr r3, [r3, #0]
8000e46: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000e48: 683b ldr r3, [r7, #0]
8000e4a: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000e4c: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000e4e: 6979 ldr r1, [r7, #20]
8000e50: 3348 adds r3, #72 @ 0x48
8000e52: 00db lsls r3, r3, #3
8000e54: 440b add r3, r1
8000e56: 605a str r2, [r3, #4]
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
8000e58: 683b ldr r3, [r7, #0]
8000e5a: 69db ldr r3, [r3, #28]
8000e5c: 2b01 cmp r3, #1
8000e5e: d122 bne.n 8000ea6 <HAL_CAN_ConfigFilter+0xf6>
{
/* 32-bit scale for the filter */
SET_BIT(can_ip->FS1R, filternbrbitpos);
8000e60: 697b ldr r3, [r7, #20]
8000e62: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c
8000e66: 68fb ldr r3, [r7, #12]
8000e68: 431a orrs r2, r3
8000e6a: 697b ldr r3, [r7, #20]
8000e6c: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* 32-bit identifier or First 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8000e70: 683b ldr r3, [r7, #0]
8000e72: 681b ldr r3, [r3, #0]
8000e74: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8000e76: 683b ldr r3, [r7, #0]
8000e78: 685b ldr r3, [r3, #4]
8000e7a: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000e7c: 683a ldr r2, [r7, #0]
8000e7e: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8000e80: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000e82: 697b ldr r3, [r7, #20]
8000e84: 3248 adds r2, #72 @ 0x48
8000e86: f843 1032 str.w r1, [r3, r2, lsl #3]
/* 32-bit mask or Second 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000e8a: 683b ldr r3, [r7, #0]
8000e8c: 689b ldr r3, [r3, #8]
8000e8e: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
8000e90: 683b ldr r3, [r7, #0]
8000e92: 68db ldr r3, [r3, #12]
8000e94: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000e96: 683b ldr r3, [r7, #0]
8000e98: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000e9a: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000e9c: 6979 ldr r1, [r7, #20]
8000e9e: 3348 adds r3, #72 @ 0x48
8000ea0: 00db lsls r3, r3, #3
8000ea2: 440b add r3, r1
8000ea4: 605a str r2, [r3, #4]
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
8000ea6: 683b ldr r3, [r7, #0]
8000ea8: 699b ldr r3, [r3, #24]
8000eaa: 2b00 cmp r3, #0
8000eac: d109 bne.n 8000ec2 <HAL_CAN_ConfigFilter+0x112>
{
/* Id/Mask mode for the filter*/
CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
8000eae: 697b ldr r3, [r7, #20]
8000eb0: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8000eb4: 68fb ldr r3, [r7, #12]
8000eb6: 43db mvns r3, r3
8000eb8: 401a ands r2, r3
8000eba: 697b ldr r3, [r7, #20]
8000ebc: f8c3 2204 str.w r2, [r3, #516] @ 0x204
8000ec0: e007 b.n 8000ed2 <HAL_CAN_ConfigFilter+0x122>
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/* Identifier list mode for the filter*/
SET_BIT(can_ip->FM1R, filternbrbitpos);
8000ec2: 697b ldr r3, [r7, #20]
8000ec4: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8000ec8: 68fb ldr r3, [r7, #12]
8000eca: 431a orrs r2, r3
8000ecc: 697b ldr r3, [r7, #20]
8000ece: f8c3 2204 str.w r2, [r3, #516] @ 0x204
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
8000ed2: 683b ldr r3, [r7, #0]
8000ed4: 691b ldr r3, [r3, #16]
8000ed6: 2b00 cmp r3, #0
8000ed8: d109 bne.n 8000eee <HAL_CAN_ConfigFilter+0x13e>
{
/* FIFO 0 assignation for the filter */
CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
8000eda: 697b ldr r3, [r7, #20]
8000edc: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214
8000ee0: 68fb ldr r3, [r7, #12]
8000ee2: 43db mvns r3, r3
8000ee4: 401a ands r2, r3
8000ee6: 697b ldr r3, [r7, #20]
8000ee8: f8c3 2214 str.w r2, [r3, #532] @ 0x214
8000eec: e007 b.n 8000efe <HAL_CAN_ConfigFilter+0x14e>
}
else
{
/* FIFO 1 assignation for the filter */
SET_BIT(can_ip->FFA1R, filternbrbitpos);
8000eee: 697b ldr r3, [r7, #20]
8000ef0: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214
8000ef4: 68fb ldr r3, [r7, #12]
8000ef6: 431a orrs r2, r3
8000ef8: 697b ldr r3, [r7, #20]
8000efa: f8c3 2214 str.w r2, [r3, #532] @ 0x214
}
/* Filter activation */
if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
8000efe: 683b ldr r3, [r7, #0]
8000f00: 6a1b ldr r3, [r3, #32]
8000f02: 2b01 cmp r3, #1
8000f04: d107 bne.n 8000f16 <HAL_CAN_ConfigFilter+0x166>
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
8000f06: 697b ldr r3, [r7, #20]
8000f08: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c
8000f0c: 68fb ldr r3, [r7, #12]
8000f0e: 431a orrs r2, r3
8000f10: 697b ldr r3, [r7, #20]
8000f12: f8c3 221c str.w r2, [r3, #540] @ 0x21c
}
/* Leave the initialisation mode for the filter */
CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
8000f16: 697b ldr r3, [r7, #20]
8000f18: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200
8000f1c: f023 0201 bic.w r2, r3, #1
8000f20: 697b ldr r3, [r7, #20]
8000f22: f8c3 2200 str.w r2, [r3, #512] @ 0x200
/* Return function status */
return HAL_OK;
8000f26: 2300 movs r3, #0
8000f28: e006 b.n 8000f38 <HAL_CAN_ConfigFilter+0x188>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8000f2a: 687b ldr r3, [r7, #4]
8000f2c: 6a5b ldr r3, [r3, #36] @ 0x24
8000f2e: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8000f32: 687b ldr r3, [r7, #4]
8000f34: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8000f36: 2301 movs r3, #1
}
}
8000f38: 4618 mov r0, r3
8000f3a: 371c adds r7, #28
8000f3c: 46bd mov sp, r7
8000f3e: f85d 7b04 ldr.w r7, [sp], #4
8000f42: 4770 bx lr
08000f44 <HAL_CAN_Start>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
8000f44: b580 push {r7, lr}
8000f46: b084 sub sp, #16
8000f48: af00 add r7, sp, #0
8000f4a: 6078 str r0, [r7, #4]
uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
8000f4c: 687b ldr r3, [r7, #4]
8000f4e: f893 3020 ldrb.w r3, [r3, #32]
8000f52: b2db uxtb r3, r3
8000f54: 2b01 cmp r3, #1
8000f56: d12e bne.n 8000fb6 <HAL_CAN_Start+0x72>
{
/* Change CAN peripheral state */
hcan->State = HAL_CAN_STATE_LISTENING;
8000f58: 687b ldr r3, [r7, #4]
8000f5a: 2202 movs r2, #2
8000f5c: f883 2020 strb.w r2, [r3, #32]
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8000f60: 687b ldr r3, [r7, #4]
8000f62: 681b ldr r3, [r3, #0]
8000f64: 681a ldr r2, [r3, #0]
8000f66: 687b ldr r3, [r7, #4]
8000f68: 681b ldr r3, [r3, #0]
8000f6a: f022 0201 bic.w r2, r2, #1
8000f6e: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000f70: f7ff fda8 bl 8000ac4 <HAL_GetTick>
8000f74: 60f8 str r0, [r7, #12]
/* Wait the acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
8000f76: e012 b.n 8000f9e <HAL_CAN_Start+0x5a>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000f78: f7ff fda4 bl 8000ac4 <HAL_GetTick>
8000f7c: 4602 mov r2, r0
8000f7e: 68fb ldr r3, [r7, #12]
8000f80: 1ad3 subs r3, r2, r3
8000f82: 2b0a cmp r3, #10
8000f84: d90b bls.n 8000f9e <HAL_CAN_Start+0x5a>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000f86: 687b ldr r3, [r7, #4]
8000f88: 6a5b ldr r3, [r3, #36] @ 0x24
8000f8a: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8000f8e: 687b ldr r3, [r7, #4]
8000f90: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000f92: 687b ldr r3, [r7, #4]
8000f94: 2205 movs r2, #5
8000f96: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000f9a: 2301 movs r3, #1
8000f9c: e012 b.n 8000fc4 <HAL_CAN_Start+0x80>
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
8000f9e: 687b ldr r3, [r7, #4]
8000fa0: 681b ldr r3, [r3, #0]
8000fa2: 685b ldr r3, [r3, #4]
8000fa4: f003 0301 and.w r3, r3, #1
8000fa8: 2b00 cmp r3, #0
8000faa: d1e5 bne.n 8000f78 <HAL_CAN_Start+0x34>
}
}
/* Reset the CAN ErrorCode */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8000fac: 687b ldr r3, [r7, #4]
8000fae: 2200 movs r2, #0
8000fb0: 625a str r2, [r3, #36] @ 0x24
/* Return function status */
return HAL_OK;
8000fb2: 2300 movs r3, #0
8000fb4: e006 b.n 8000fc4 <HAL_CAN_Start+0x80>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
8000fb6: 687b ldr r3, [r7, #4]
8000fb8: 6a5b ldr r3, [r3, #36] @ 0x24
8000fba: f443 2200 orr.w r2, r3, #524288 @ 0x80000
8000fbe: 687b ldr r3, [r7, #4]
8000fc0: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8000fc2: 2301 movs r3, #1
}
}
8000fc4: 4618 mov r0, r3
8000fc6: 3710 adds r7, #16
8000fc8: 46bd mov sp, r7
8000fca: bd80 pop {r7, pc}
08000fcc <HAL_CAN_AddTxMessage>:
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox)
{
8000fcc: b480 push {r7}
8000fce: b089 sub sp, #36 @ 0x24
8000fd0: af00 add r7, sp, #0
8000fd2: 60f8 str r0, [r7, #12]
8000fd4: 60b9 str r1, [r7, #8]
8000fd6: 607a str r2, [r7, #4]
8000fd8: 603b str r3, [r7, #0]
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
8000fda: 68fb ldr r3, [r7, #12]
8000fdc: f893 3020 ldrb.w r3, [r3, #32]
8000fe0: 77fb strb r3, [r7, #31]
uint32_t tsr = READ_REG(hcan->Instance->TSR);
8000fe2: 68fb ldr r3, [r7, #12]
8000fe4: 681b ldr r3, [r3, #0]
8000fe6: 689b ldr r3, [r3, #8]
8000fe8: 61bb str r3, [r7, #24]
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
8000fea: 7ffb ldrb r3, [r7, #31]
8000fec: 2b01 cmp r3, #1
8000fee: d003 beq.n 8000ff8 <HAL_CAN_AddTxMessage+0x2c>
8000ff0: 7ffb ldrb r3, [r7, #31]
8000ff2: 2b02 cmp r3, #2
8000ff4: f040 80ad bne.w 8001152 <HAL_CAN_AddTxMessage+0x186>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
8000ff8: 69bb ldr r3, [r7, #24]
8000ffa: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8000ffe: 2b00 cmp r3, #0
8001000: d10a bne.n 8001018 <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME1) != 0U) ||
8001002: 69bb ldr r3, [r7, #24]
8001004: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
if (((tsr & CAN_TSR_TME0) != 0U) ||
8001008: 2b00 cmp r3, #0
800100a: d105 bne.n 8001018 <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME2) != 0U))
800100c: 69bb ldr r3, [r7, #24]
800100e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
((tsr & CAN_TSR_TME1) != 0U) ||
8001012: 2b00 cmp r3, #0
8001014: f000 8095 beq.w 8001142 <HAL_CAN_AddTxMessage+0x176>
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
8001018: 69bb ldr r3, [r7, #24]
800101a: 0e1b lsrs r3, r3, #24
800101c: f003 0303 and.w r3, r3, #3
8001020: 617b str r3, [r7, #20]
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
8001022: 2201 movs r2, #1
8001024: 697b ldr r3, [r7, #20]
8001026: 409a lsls r2, r3
8001028: 683b ldr r3, [r7, #0]
800102a: 601a str r2, [r3, #0]
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
800102c: 68bb ldr r3, [r7, #8]
800102e: 689b ldr r3, [r3, #8]
8001030: 2b00 cmp r3, #0
8001032: d10d bne.n 8001050 <HAL_CAN_AddTxMessage+0x84>
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8001034: 68bb ldr r3, [r7, #8]
8001036: 681b ldr r3, [r3, #0]
8001038: 055a lsls r2, r3, #21
pHeader->RTR);
800103a: 68bb ldr r3, [r7, #8]
800103c: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
800103e: 68f9 ldr r1, [r7, #12]
8001040: 6809 ldr r1, [r1, #0]
8001042: 431a orrs r2, r3
8001044: 697b ldr r3, [r7, #20]
8001046: 3318 adds r3, #24
8001048: 011b lsls r3, r3, #4
800104a: 440b add r3, r1
800104c: 601a str r2, [r3, #0]
800104e: e00f b.n 8001070 <HAL_CAN_AddTxMessage+0xa4>
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001050: 68bb ldr r3, [r7, #8]
8001052: 685b ldr r3, [r3, #4]
8001054: 00da lsls r2, r3, #3
pHeader->IDE |
8001056: 68bb ldr r3, [r7, #8]
8001058: 689b ldr r3, [r3, #8]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
800105a: 431a orrs r2, r3
pHeader->RTR);
800105c: 68bb ldr r3, [r7, #8]
800105e: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001060: 68f9 ldr r1, [r7, #12]
8001062: 6809 ldr r1, [r1, #0]
pHeader->IDE |
8001064: 431a orrs r2, r3
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001066: 697b ldr r3, [r7, #20]
8001068: 3318 adds r3, #24
800106a: 011b lsls r3, r3, #4
800106c: 440b add r3, r1
800106e: 601a str r2, [r3, #0]
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
8001070: 68fb ldr r3, [r7, #12]
8001072: 6819 ldr r1, [r3, #0]
8001074: 68bb ldr r3, [r7, #8]
8001076: 691a ldr r2, [r3, #16]
8001078: 697b ldr r3, [r7, #20]
800107a: 3318 adds r3, #24
800107c: 011b lsls r3, r3, #4
800107e: 440b add r3, r1
8001080: 3304 adds r3, #4
8001082: 601a str r2, [r3, #0]
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
8001084: 68bb ldr r3, [r7, #8]
8001086: 7d1b ldrb r3, [r3, #20]
8001088: 2b01 cmp r3, #1
800108a: d111 bne.n 80010b0 <HAL_CAN_AddTxMessage+0xe4>
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
800108c: 68fb ldr r3, [r7, #12]
800108e: 681a ldr r2, [r3, #0]
8001090: 697b ldr r3, [r7, #20]
8001092: 3318 adds r3, #24
8001094: 011b lsls r3, r3, #4
8001096: 4413 add r3, r2
8001098: 3304 adds r3, #4
800109a: 681b ldr r3, [r3, #0]
800109c: 68fa ldr r2, [r7, #12]
800109e: 6811 ldr r1, [r2, #0]
80010a0: f443 7280 orr.w r2, r3, #256 @ 0x100
80010a4: 697b ldr r3, [r7, #20]
80010a6: 3318 adds r3, #24
80010a8: 011b lsls r3, r3, #4
80010aa: 440b add r3, r1
80010ac: 3304 adds r3, #4
80010ae: 601a str r2, [r3, #0]
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
80010b0: 687b ldr r3, [r7, #4]
80010b2: 3307 adds r3, #7
80010b4: 781b ldrb r3, [r3, #0]
80010b6: 061a lsls r2, r3, #24
80010b8: 687b ldr r3, [r7, #4]
80010ba: 3306 adds r3, #6
80010bc: 781b ldrb r3, [r3, #0]
80010be: 041b lsls r3, r3, #16
80010c0: 431a orrs r2, r3
80010c2: 687b ldr r3, [r7, #4]
80010c4: 3305 adds r3, #5
80010c6: 781b ldrb r3, [r3, #0]
80010c8: 021b lsls r3, r3, #8
80010ca: 4313 orrs r3, r2
80010cc: 687a ldr r2, [r7, #4]
80010ce: 3204 adds r2, #4
80010d0: 7812 ldrb r2, [r2, #0]
80010d2: 4610 mov r0, r2
80010d4: 68fa ldr r2, [r7, #12]
80010d6: 6811 ldr r1, [r2, #0]
80010d8: ea43 0200 orr.w r2, r3, r0
80010dc: 697b ldr r3, [r7, #20]
80010de: 011b lsls r3, r3, #4
80010e0: 440b add r3, r1
80010e2: f503 73c6 add.w r3, r3, #396 @ 0x18c
80010e6: 601a str r2, [r3, #0]
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
80010e8: 687b ldr r3, [r7, #4]
80010ea: 3303 adds r3, #3
80010ec: 781b ldrb r3, [r3, #0]
80010ee: 061a lsls r2, r3, #24
80010f0: 687b ldr r3, [r7, #4]
80010f2: 3302 adds r3, #2
80010f4: 781b ldrb r3, [r3, #0]
80010f6: 041b lsls r3, r3, #16
80010f8: 431a orrs r2, r3
80010fa: 687b ldr r3, [r7, #4]
80010fc: 3301 adds r3, #1
80010fe: 781b ldrb r3, [r3, #0]
8001100: 021b lsls r3, r3, #8
8001102: 4313 orrs r3, r2
8001104: 687a ldr r2, [r7, #4]
8001106: 7812 ldrb r2, [r2, #0]
8001108: 4610 mov r0, r2
800110a: 68fa ldr r2, [r7, #12]
800110c: 6811 ldr r1, [r2, #0]
800110e: ea43 0200 orr.w r2, r3, r0
8001112: 697b ldr r3, [r7, #20]
8001114: 011b lsls r3, r3, #4
8001116: 440b add r3, r1
8001118: f503 73c4 add.w r3, r3, #392 @ 0x188
800111c: 601a str r2, [r3, #0]
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
800111e: 68fb ldr r3, [r7, #12]
8001120: 681a ldr r2, [r3, #0]
8001122: 697b ldr r3, [r7, #20]
8001124: 3318 adds r3, #24
8001126: 011b lsls r3, r3, #4
8001128: 4413 add r3, r2
800112a: 681b ldr r3, [r3, #0]
800112c: 68fa ldr r2, [r7, #12]
800112e: 6811 ldr r1, [r2, #0]
8001130: f043 0201 orr.w r2, r3, #1
8001134: 697b ldr r3, [r7, #20]
8001136: 3318 adds r3, #24
8001138: 011b lsls r3, r3, #4
800113a: 440b add r3, r1
800113c: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
800113e: 2300 movs r3, #0
8001140: e00e b.n 8001160 <HAL_CAN_AddTxMessage+0x194>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8001142: 68fb ldr r3, [r7, #12]
8001144: 6a5b ldr r3, [r3, #36] @ 0x24
8001146: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
800114a: 68fb ldr r3, [r7, #12]
800114c: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
800114e: 2301 movs r3, #1
8001150: e006 b.n 8001160 <HAL_CAN_AddTxMessage+0x194>
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8001152: 68fb ldr r3, [r7, #12]
8001154: 6a5b ldr r3, [r3, #36] @ 0x24
8001156: f443 2280 orr.w r2, r3, #262144 @ 0x40000
800115a: 68fb ldr r3, [r7, #12]
800115c: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
800115e: 2301 movs r3, #1
}
}
8001160: 4618 mov r0, r3
8001162: 3724 adds r7, #36 @ 0x24
8001164: 46bd mov sp, r7
8001166: f85d 7b04 ldr.w r7, [sp], #4
800116a: 4770 bx lr
0800116c <HAL_CAN_GetRxMessage>:
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
800116c: b480 push {r7}
800116e: b087 sub sp, #28
8001170: af00 add r7, sp, #0
8001172: 60f8 str r0, [r7, #12]
8001174: 60b9 str r1, [r7, #8]
8001176: 607a str r2, [r7, #4]
8001178: 603b str r3, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
800117a: 68fb ldr r3, [r7, #12]
800117c: f893 3020 ldrb.w r3, [r3, #32]
8001180: 75fb strb r3, [r7, #23]
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
8001182: 7dfb ldrb r3, [r7, #23]
8001184: 2b01 cmp r3, #1
8001186: d003 beq.n 8001190 <HAL_CAN_GetRxMessage+0x24>
8001188: 7dfb ldrb r3, [r7, #23]
800118a: 2b02 cmp r3, #2
800118c: f040 8103 bne.w 8001396 <HAL_CAN_GetRxMessage+0x22a>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
8001190: 68bb ldr r3, [r7, #8]
8001192: 2b00 cmp r3, #0
8001194: d10e bne.n 80011b4 <HAL_CAN_GetRxMessage+0x48>
{
/* Check that the Rx FIFO 0 is not empty */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
8001196: 68fb ldr r3, [r7, #12]
8001198: 681b ldr r3, [r3, #0]
800119a: 68db ldr r3, [r3, #12]
800119c: f003 0303 and.w r3, r3, #3
80011a0: 2b00 cmp r3, #0
80011a2: d116 bne.n 80011d2 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80011a4: 68fb ldr r3, [r7, #12]
80011a6: 6a5b ldr r3, [r3, #36] @ 0x24
80011a8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80011ac: 68fb ldr r3, [r7, #12]
80011ae: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80011b0: 2301 movs r3, #1
80011b2: e0f7 b.n 80013a4 <HAL_CAN_GetRxMessage+0x238>
}
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
80011b4: 68fb ldr r3, [r7, #12]
80011b6: 681b ldr r3, [r3, #0]
80011b8: 691b ldr r3, [r3, #16]
80011ba: f003 0303 and.w r3, r3, #3
80011be: 2b00 cmp r3, #0
80011c0: d107 bne.n 80011d2 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80011c2: 68fb ldr r3, [r7, #12]
80011c4: 6a5b ldr r3, [r3, #36] @ 0x24
80011c6: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80011ca: 68fb ldr r3, [r7, #12]
80011cc: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80011ce: 2301 movs r3, #1
80011d0: e0e8 b.n 80013a4 <HAL_CAN_GetRxMessage+0x238>
}
}
/* Get the header */
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
80011d2: 68fb ldr r3, [r7, #12]
80011d4: 681a ldr r2, [r3, #0]
80011d6: 68bb ldr r3, [r7, #8]
80011d8: 331b adds r3, #27
80011da: 011b lsls r3, r3, #4
80011dc: 4413 add r3, r2
80011de: 681b ldr r3, [r3, #0]
80011e0: f003 0204 and.w r2, r3, #4
80011e4: 687b ldr r3, [r7, #4]
80011e6: 609a str r2, [r3, #8]
if (pHeader->IDE == CAN_ID_STD)
80011e8: 687b ldr r3, [r7, #4]
80011ea: 689b ldr r3, [r3, #8]
80011ec: 2b00 cmp r3, #0
80011ee: d10c bne.n 800120a <HAL_CAN_GetRxMessage+0x9e>
{
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
80011f0: 68fb ldr r3, [r7, #12]
80011f2: 681a ldr r2, [r3, #0]
80011f4: 68bb ldr r3, [r7, #8]
80011f6: 331b adds r3, #27
80011f8: 011b lsls r3, r3, #4
80011fa: 4413 add r3, r2
80011fc: 681b ldr r3, [r3, #0]
80011fe: 0d5b lsrs r3, r3, #21
8001200: f3c3 020a ubfx r2, r3, #0, #11
8001204: 687b ldr r3, [r7, #4]
8001206: 601a str r2, [r3, #0]
8001208: e00b b.n 8001222 <HAL_CAN_GetRxMessage+0xb6>
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
800120a: 68fb ldr r3, [r7, #12]
800120c: 681a ldr r2, [r3, #0]
800120e: 68bb ldr r3, [r7, #8]
8001210: 331b adds r3, #27
8001212: 011b lsls r3, r3, #4
8001214: 4413 add r3, r2
8001216: 681b ldr r3, [r3, #0]
8001218: 08db lsrs r3, r3, #3
800121a: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
800121e: 687b ldr r3, [r7, #4]
8001220: 605a str r2, [r3, #4]
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
8001222: 68fb ldr r3, [r7, #12]
8001224: 681a ldr r2, [r3, #0]
8001226: 68bb ldr r3, [r7, #8]
8001228: 331b adds r3, #27
800122a: 011b lsls r3, r3, #4
800122c: 4413 add r3, r2
800122e: 681b ldr r3, [r3, #0]
8001230: f003 0202 and.w r2, r3, #2
8001234: 687b ldr r3, [r7, #4]
8001236: 60da str r2, [r3, #12]
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
8001238: 68fb ldr r3, [r7, #12]
800123a: 681a ldr r2, [r3, #0]
800123c: 68bb ldr r3, [r7, #8]
800123e: 331b adds r3, #27
8001240: 011b lsls r3, r3, #4
8001242: 4413 add r3, r2
8001244: 3304 adds r3, #4
8001246: 681b ldr r3, [r3, #0]
8001248: f003 0308 and.w r3, r3, #8
800124c: 2b00 cmp r3, #0
800124e: d003 beq.n 8001258 <HAL_CAN_GetRxMessage+0xec>
{
/* Truncate DLC to 8 if received field is over range */
pHeader->DLC = 8U;
8001250: 687b ldr r3, [r7, #4]
8001252: 2208 movs r2, #8
8001254: 611a str r2, [r3, #16]
8001256: e00b b.n 8001270 <HAL_CAN_GetRxMessage+0x104>
}
else
{
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
8001258: 68fb ldr r3, [r7, #12]
800125a: 681a ldr r2, [r3, #0]
800125c: 68bb ldr r3, [r7, #8]
800125e: 331b adds r3, #27
8001260: 011b lsls r3, r3, #4
8001262: 4413 add r3, r2
8001264: 3304 adds r3, #4
8001266: 681b ldr r3, [r3, #0]
8001268: f003 020f and.w r2, r3, #15
800126c: 687b ldr r3, [r7, #4]
800126e: 611a str r2, [r3, #16]
}
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
8001270: 68fb ldr r3, [r7, #12]
8001272: 681a ldr r2, [r3, #0]
8001274: 68bb ldr r3, [r7, #8]
8001276: 331b adds r3, #27
8001278: 011b lsls r3, r3, #4
800127a: 4413 add r3, r2
800127c: 3304 adds r3, #4
800127e: 681b ldr r3, [r3, #0]
8001280: 0a1b lsrs r3, r3, #8
8001282: b2da uxtb r2, r3
8001284: 687b ldr r3, [r7, #4]
8001286: 619a str r2, [r3, #24]
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
8001288: 68fb ldr r3, [r7, #12]
800128a: 681a ldr r2, [r3, #0]
800128c: 68bb ldr r3, [r7, #8]
800128e: 331b adds r3, #27
8001290: 011b lsls r3, r3, #4
8001292: 4413 add r3, r2
8001294: 3304 adds r3, #4
8001296: 681b ldr r3, [r3, #0]
8001298: 0c1b lsrs r3, r3, #16
800129a: b29a uxth r2, r3
800129c: 687b ldr r3, [r7, #4]
800129e: 615a str r2, [r3, #20]
/* Get the data */
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
80012a0: 68fb ldr r3, [r7, #12]
80012a2: 681a ldr r2, [r3, #0]
80012a4: 68bb ldr r3, [r7, #8]
80012a6: 011b lsls r3, r3, #4
80012a8: 4413 add r3, r2
80012aa: f503 73dc add.w r3, r3, #440 @ 0x1b8
80012ae: 681b ldr r3, [r3, #0]
80012b0: b2da uxtb r2, r3
80012b2: 683b ldr r3, [r7, #0]
80012b4: 701a strb r2, [r3, #0]
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
80012b6: 68fb ldr r3, [r7, #12]
80012b8: 681a ldr r2, [r3, #0]
80012ba: 68bb ldr r3, [r7, #8]
80012bc: 011b lsls r3, r3, #4
80012be: 4413 add r3, r2
80012c0: f503 73dc add.w r3, r3, #440 @ 0x1b8
80012c4: 681b ldr r3, [r3, #0]
80012c6: 0a1a lsrs r2, r3, #8
80012c8: 683b ldr r3, [r7, #0]
80012ca: 3301 adds r3, #1
80012cc: b2d2 uxtb r2, r2
80012ce: 701a strb r2, [r3, #0]
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
80012d0: 68fb ldr r3, [r7, #12]
80012d2: 681a ldr r2, [r3, #0]
80012d4: 68bb ldr r3, [r7, #8]
80012d6: 011b lsls r3, r3, #4
80012d8: 4413 add r3, r2
80012da: f503 73dc add.w r3, r3, #440 @ 0x1b8
80012de: 681b ldr r3, [r3, #0]
80012e0: 0c1a lsrs r2, r3, #16
80012e2: 683b ldr r3, [r7, #0]
80012e4: 3302 adds r3, #2
80012e6: b2d2 uxtb r2, r2
80012e8: 701a strb r2, [r3, #0]
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
80012ea: 68fb ldr r3, [r7, #12]
80012ec: 681a ldr r2, [r3, #0]
80012ee: 68bb ldr r3, [r7, #8]
80012f0: 011b lsls r3, r3, #4
80012f2: 4413 add r3, r2
80012f4: f503 73dc add.w r3, r3, #440 @ 0x1b8
80012f8: 681b ldr r3, [r3, #0]
80012fa: 0e1a lsrs r2, r3, #24
80012fc: 683b ldr r3, [r7, #0]
80012fe: 3303 adds r3, #3
8001300: b2d2 uxtb r2, r2
8001302: 701a strb r2, [r3, #0]
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
8001304: 68fb ldr r3, [r7, #12]
8001306: 681a ldr r2, [r3, #0]
8001308: 68bb ldr r3, [r7, #8]
800130a: 011b lsls r3, r3, #4
800130c: 4413 add r3, r2
800130e: f503 73de add.w r3, r3, #444 @ 0x1bc
8001312: 681a ldr r2, [r3, #0]
8001314: 683b ldr r3, [r7, #0]
8001316: 3304 adds r3, #4
8001318: b2d2 uxtb r2, r2
800131a: 701a strb r2, [r3, #0]
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
800131c: 68fb ldr r3, [r7, #12]
800131e: 681a ldr r2, [r3, #0]
8001320: 68bb ldr r3, [r7, #8]
8001322: 011b lsls r3, r3, #4
8001324: 4413 add r3, r2
8001326: f503 73de add.w r3, r3, #444 @ 0x1bc
800132a: 681b ldr r3, [r3, #0]
800132c: 0a1a lsrs r2, r3, #8
800132e: 683b ldr r3, [r7, #0]
8001330: 3305 adds r3, #5
8001332: b2d2 uxtb r2, r2
8001334: 701a strb r2, [r3, #0]
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
8001336: 68fb ldr r3, [r7, #12]
8001338: 681a ldr r2, [r3, #0]
800133a: 68bb ldr r3, [r7, #8]
800133c: 011b lsls r3, r3, #4
800133e: 4413 add r3, r2
8001340: f503 73de add.w r3, r3, #444 @ 0x1bc
8001344: 681b ldr r3, [r3, #0]
8001346: 0c1a lsrs r2, r3, #16
8001348: 683b ldr r3, [r7, #0]
800134a: 3306 adds r3, #6
800134c: b2d2 uxtb r2, r2
800134e: 701a strb r2, [r3, #0]
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
8001350: 68fb ldr r3, [r7, #12]
8001352: 681a ldr r2, [r3, #0]
8001354: 68bb ldr r3, [r7, #8]
8001356: 011b lsls r3, r3, #4
8001358: 4413 add r3, r2
800135a: f503 73de add.w r3, r3, #444 @ 0x1bc
800135e: 681b ldr r3, [r3, #0]
8001360: 0e1a lsrs r2, r3, #24
8001362: 683b ldr r3, [r7, #0]
8001364: 3307 adds r3, #7
8001366: b2d2 uxtb r2, r2
8001368: 701a strb r2, [r3, #0]
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
800136a: 68bb ldr r3, [r7, #8]
800136c: 2b00 cmp r3, #0
800136e: d108 bne.n 8001382 <HAL_CAN_GetRxMessage+0x216>
{
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
8001370: 68fb ldr r3, [r7, #12]
8001372: 681b ldr r3, [r3, #0]
8001374: 68da ldr r2, [r3, #12]
8001376: 68fb ldr r3, [r7, #12]
8001378: 681b ldr r3, [r3, #0]
800137a: f042 0220 orr.w r2, r2, #32
800137e: 60da str r2, [r3, #12]
8001380: e007 b.n 8001392 <HAL_CAN_GetRxMessage+0x226>
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
8001382: 68fb ldr r3, [r7, #12]
8001384: 681b ldr r3, [r3, #0]
8001386: 691a ldr r2, [r3, #16]
8001388: 68fb ldr r3, [r7, #12]
800138a: 681b ldr r3, [r3, #0]
800138c: f042 0220 orr.w r2, r2, #32
8001390: 611a str r2, [r3, #16]
}
/* Return function status */
return HAL_OK;
8001392: 2300 movs r3, #0
8001394: e006 b.n 80013a4 <HAL_CAN_GetRxMessage+0x238>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8001396: 68fb ldr r3, [r7, #12]
8001398: 6a5b ldr r3, [r3, #36] @ 0x24
800139a: f443 2280 orr.w r2, r3, #262144 @ 0x40000
800139e: 68fb ldr r3, [r7, #12]
80013a0: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80013a2: 2301 movs r3, #1
}
}
80013a4: 4618 mov r0, r3
80013a6: 371c adds r7, #28
80013a8: 46bd mov sp, r7
80013aa: f85d 7b04 ldr.w r7, [sp], #4
80013ae: 4770 bx lr
080013b0 <HAL_CAN_ActivateNotification>:
* @param ActiveITs indicates which interrupts will be enabled.
* This parameter can be any combination of @arg CAN_Interrupts.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
80013b0: b480 push {r7}
80013b2: b085 sub sp, #20
80013b4: af00 add r7, sp, #0
80013b6: 6078 str r0, [r7, #4]
80013b8: 6039 str r1, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
80013ba: 687b ldr r3, [r7, #4]
80013bc: f893 3020 ldrb.w r3, [r3, #32]
80013c0: 73fb strb r3, [r7, #15]
/* Check function parameters */
assert_param(IS_CAN_IT(ActiveITs));
if ((state == HAL_CAN_STATE_READY) ||
80013c2: 7bfb ldrb r3, [r7, #15]
80013c4: 2b01 cmp r3, #1
80013c6: d002 beq.n 80013ce <HAL_CAN_ActivateNotification+0x1e>
80013c8: 7bfb ldrb r3, [r7, #15]
80013ca: 2b02 cmp r3, #2
80013cc: d109 bne.n 80013e2 <HAL_CAN_ActivateNotification+0x32>
(state == HAL_CAN_STATE_LISTENING))
{
/* Enable the selected interrupts */
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
80013ce: 687b ldr r3, [r7, #4]
80013d0: 681b ldr r3, [r3, #0]
80013d2: 6959 ldr r1, [r3, #20]
80013d4: 687b ldr r3, [r7, #4]
80013d6: 681b ldr r3, [r3, #0]
80013d8: 683a ldr r2, [r7, #0]
80013da: 430a orrs r2, r1
80013dc: 615a str r2, [r3, #20]
/* Return function status */
return HAL_OK;
80013de: 2300 movs r3, #0
80013e0: e006 b.n 80013f0 <HAL_CAN_ActivateNotification+0x40>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
80013e2: 687b ldr r3, [r7, #4]
80013e4: 6a5b ldr r3, [r3, #36] @ 0x24
80013e6: f443 2280 orr.w r2, r3, #262144 @ 0x40000
80013ea: 687b ldr r3, [r7, #4]
80013ec: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80013ee: 2301 movs r3, #1
}
}
80013f0: 4618 mov r0, r3
80013f2: 3714 adds r7, #20
80013f4: 46bd mov sp, r7
80013f6: f85d 7b04 ldr.w r7, [sp], #4
80013fa: 4770 bx lr
080013fc <HAL_CAN_IRQHandler>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
80013fc: b580 push {r7, lr}
80013fe: b08a sub sp, #40 @ 0x28
8001400: af00 add r7, sp, #0
8001402: 6078 str r0, [r7, #4]
uint32_t errorcode = HAL_CAN_ERROR_NONE;
8001404: 2300 movs r3, #0
8001406: 627b str r3, [r7, #36] @ 0x24
uint32_t interrupts = READ_REG(hcan->Instance->IER);
8001408: 687b ldr r3, [r7, #4]
800140a: 681b ldr r3, [r3, #0]
800140c: 695b ldr r3, [r3, #20]
800140e: 623b str r3, [r7, #32]
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
8001410: 687b ldr r3, [r7, #4]
8001412: 681b ldr r3, [r3, #0]
8001414: 685b ldr r3, [r3, #4]
8001416: 61fb str r3, [r7, #28]
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
8001418: 687b ldr r3, [r7, #4]
800141a: 681b ldr r3, [r3, #0]
800141c: 689b ldr r3, [r3, #8]
800141e: 61bb str r3, [r7, #24]
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
8001420: 687b ldr r3, [r7, #4]
8001422: 681b ldr r3, [r3, #0]
8001424: 68db ldr r3, [r3, #12]
8001426: 617b str r3, [r7, #20]
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
8001428: 687b ldr r3, [r7, #4]
800142a: 681b ldr r3, [r3, #0]
800142c: 691b ldr r3, [r3, #16]
800142e: 613b str r3, [r7, #16]
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
8001430: 687b ldr r3, [r7, #4]
8001432: 681b ldr r3, [r3, #0]
8001434: 699b ldr r3, [r3, #24]
8001436: 60fb str r3, [r7, #12]
/* Transmit Mailbox empty interrupt management *****************************/
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
8001438: 6a3b ldr r3, [r7, #32]
800143a: f003 0301 and.w r3, r3, #1
800143e: 2b00 cmp r3, #0
8001440: f000 8083 beq.w 800154a <HAL_CAN_IRQHandler+0x14e>
{
/* Transmit Mailbox 0 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
8001444: 69bb ldr r3, [r7, #24]
8001446: f003 0301 and.w r3, r3, #1
800144a: 2b00 cmp r3, #0
800144c: d025 beq.n 800149a <HAL_CAN_IRQHandler+0x9e>
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
800144e: 687b ldr r3, [r7, #4]
8001450: 681b ldr r3, [r3, #0]
8001452: 2201 movs r2, #1
8001454: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
8001456: 69bb ldr r3, [r7, #24]
8001458: f003 0302 and.w r3, r3, #2
800145c: 2b00 cmp r3, #0
800145e: d004 beq.n 800146a <HAL_CAN_IRQHandler+0x6e>
{
/* Transmission Mailbox 0 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0CompleteCallback(hcan);
8001460: 687b ldr r3, [r7, #4]
8001462: 6a9b ldr r3, [r3, #40] @ 0x28
8001464: 6878 ldr r0, [r7, #4]
8001466: 4798 blx r3
8001468: e017 b.n 800149a <HAL_CAN_IRQHandler+0x9e>
HAL_CAN_TxMailbox0CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST0) != 0U)
800146a: 69bb ldr r3, [r7, #24]
800146c: f003 0304 and.w r3, r3, #4
8001470: 2b00 cmp r3, #0
8001472: d004 beq.n 800147e <HAL_CAN_IRQHandler+0x82>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
8001474: 6a7b ldr r3, [r7, #36] @ 0x24
8001476: f443 6300 orr.w r3, r3, #2048 @ 0x800
800147a: 627b str r3, [r7, #36] @ 0x24
800147c: e00d b.n 800149a <HAL_CAN_IRQHandler+0x9e>
}
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
800147e: 69bb ldr r3, [r7, #24]
8001480: f003 0308 and.w r3, r3, #8
8001484: 2b00 cmp r3, #0
8001486: d004 beq.n 8001492 <HAL_CAN_IRQHandler+0x96>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
8001488: 6a7b ldr r3, [r7, #36] @ 0x24
800148a: f443 5380 orr.w r3, r3, #4096 @ 0x1000
800148e: 627b str r3, [r7, #36] @ 0x24
8001490: e003 b.n 800149a <HAL_CAN_IRQHandler+0x9e>
else
{
/* Transmission Mailbox 0 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0AbortCallback(hcan);
8001492: 687b ldr r3, [r7, #4]
8001494: 6b5b ldr r3, [r3, #52] @ 0x34
8001496: 6878 ldr r0, [r7, #4]
8001498: 4798 blx r3
}
}
}
/* Transmit Mailbox 1 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
800149a: 69bb ldr r3, [r7, #24]
800149c: f403 7380 and.w r3, r3, #256 @ 0x100
80014a0: 2b00 cmp r3, #0
80014a2: d026 beq.n 80014f2 <HAL_CAN_IRQHandler+0xf6>
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
80014a4: 687b ldr r3, [r7, #4]
80014a6: 681b ldr r3, [r3, #0]
80014a8: f44f 7280 mov.w r2, #256 @ 0x100
80014ac: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
80014ae: 69bb ldr r3, [r7, #24]
80014b0: f403 7300 and.w r3, r3, #512 @ 0x200
80014b4: 2b00 cmp r3, #0
80014b6: d004 beq.n 80014c2 <HAL_CAN_IRQHandler+0xc6>
{
/* Transmission Mailbox 1 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1CompleteCallback(hcan);
80014b8: 687b ldr r3, [r7, #4]
80014ba: 6adb ldr r3, [r3, #44] @ 0x2c
80014bc: 6878 ldr r0, [r7, #4]
80014be: 4798 blx r3
80014c0: e017 b.n 80014f2 <HAL_CAN_IRQHandler+0xf6>
HAL_CAN_TxMailbox1CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST1) != 0U)
80014c2: 69bb ldr r3, [r7, #24]
80014c4: f403 6380 and.w r3, r3, #1024 @ 0x400
80014c8: 2b00 cmp r3, #0
80014ca: d004 beq.n 80014d6 <HAL_CAN_IRQHandler+0xda>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
80014cc: 6a7b ldr r3, [r7, #36] @ 0x24
80014ce: f443 5300 orr.w r3, r3, #8192 @ 0x2000
80014d2: 627b str r3, [r7, #36] @ 0x24
80014d4: e00d b.n 80014f2 <HAL_CAN_IRQHandler+0xf6>
}
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
80014d6: 69bb ldr r3, [r7, #24]
80014d8: f403 6300 and.w r3, r3, #2048 @ 0x800
80014dc: 2b00 cmp r3, #0
80014de: d004 beq.n 80014ea <HAL_CAN_IRQHandler+0xee>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
80014e0: 6a7b ldr r3, [r7, #36] @ 0x24
80014e2: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80014e6: 627b str r3, [r7, #36] @ 0x24
80014e8: e003 b.n 80014f2 <HAL_CAN_IRQHandler+0xf6>
else
{
/* Transmission Mailbox 1 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1AbortCallback(hcan);
80014ea: 687b ldr r3, [r7, #4]
80014ec: 6b9b ldr r3, [r3, #56] @ 0x38
80014ee: 6878 ldr r0, [r7, #4]
80014f0: 4798 blx r3
}
}
}
/* Transmit Mailbox 2 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
80014f2: 69bb ldr r3, [r7, #24]
80014f4: f403 3380 and.w r3, r3, #65536 @ 0x10000
80014f8: 2b00 cmp r3, #0
80014fa: d026 beq.n 800154a <HAL_CAN_IRQHandler+0x14e>
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
80014fc: 687b ldr r3, [r7, #4]
80014fe: 681b ldr r3, [r3, #0]
8001500: f44f 3280 mov.w r2, #65536 @ 0x10000
8001504: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
8001506: 69bb ldr r3, [r7, #24]
8001508: f403 3300 and.w r3, r3, #131072 @ 0x20000
800150c: 2b00 cmp r3, #0
800150e: d004 beq.n 800151a <HAL_CAN_IRQHandler+0x11e>
{
/* Transmission Mailbox 2 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2CompleteCallback(hcan);
8001510: 687b ldr r3, [r7, #4]
8001512: 6b1b ldr r3, [r3, #48] @ 0x30
8001514: 6878 ldr r0, [r7, #4]
8001516: 4798 blx r3
8001518: e017 b.n 800154a <HAL_CAN_IRQHandler+0x14e>
HAL_CAN_TxMailbox2CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST2) != 0U)
800151a: 69bb ldr r3, [r7, #24]
800151c: f403 2380 and.w r3, r3, #262144 @ 0x40000
8001520: 2b00 cmp r3, #0
8001522: d004 beq.n 800152e <HAL_CAN_IRQHandler+0x132>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
8001524: 6a7b ldr r3, [r7, #36] @ 0x24
8001526: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800152a: 627b str r3, [r7, #36] @ 0x24
800152c: e00d b.n 800154a <HAL_CAN_IRQHandler+0x14e>
}
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
800152e: 69bb ldr r3, [r7, #24]
8001530: f403 2300 and.w r3, r3, #524288 @ 0x80000
8001534: 2b00 cmp r3, #0
8001536: d004 beq.n 8001542 <HAL_CAN_IRQHandler+0x146>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
8001538: 6a7b ldr r3, [r7, #36] @ 0x24
800153a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800153e: 627b str r3, [r7, #36] @ 0x24
8001540: e003 b.n 800154a <HAL_CAN_IRQHandler+0x14e>
else
{
/* Transmission Mailbox 2 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2AbortCallback(hcan);
8001542: 687b ldr r3, [r7, #4]
8001544: 6bdb ldr r3, [r3, #60] @ 0x3c
8001546: 6878 ldr r0, [r7, #4]
8001548: 4798 blx r3
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
800154a: 6a3b ldr r3, [r7, #32]
800154c: f003 0308 and.w r3, r3, #8
8001550: 2b00 cmp r3, #0
8001552: d00c beq.n 800156e <HAL_CAN_IRQHandler+0x172>
{
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
8001554: 697b ldr r3, [r7, #20]
8001556: f003 0310 and.w r3, r3, #16
800155a: 2b00 cmp r3, #0
800155c: d007 beq.n 800156e <HAL_CAN_IRQHandler+0x172>
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
800155e: 6a7b ldr r3, [r7, #36] @ 0x24
8001560: f443 7300 orr.w r3, r3, #512 @ 0x200
8001564: 627b str r3, [r7, #36] @ 0x24
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
8001566: 687b ldr r3, [r7, #4]
8001568: 681b ldr r3, [r3, #0]
800156a: 2210 movs r2, #16
800156c: 60da str r2, [r3, #12]
}
}
/* Receive FIFO 0 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
800156e: 6a3b ldr r3, [r7, #32]
8001570: f003 0304 and.w r3, r3, #4
8001574: 2b00 cmp r3, #0
8001576: d00c beq.n 8001592 <HAL_CAN_IRQHandler+0x196>
{
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
8001578: 697b ldr r3, [r7, #20]
800157a: f003 0308 and.w r3, r3, #8
800157e: 2b00 cmp r3, #0
8001580: d007 beq.n 8001592 <HAL_CAN_IRQHandler+0x196>
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
8001582: 687b ldr r3, [r7, #4]
8001584: 681b ldr r3, [r3, #0]
8001586: 2208 movs r2, #8
8001588: 60da str r2, [r3, #12]
/* Receive FIFO 0 full Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0FullCallback(hcan);
800158a: 687b ldr r3, [r7, #4]
800158c: 6c5b ldr r3, [r3, #68] @ 0x44
800158e: 6878 ldr r0, [r7, #4]
8001590: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
8001592: 6a3b ldr r3, [r7, #32]
8001594: f003 0302 and.w r3, r3, #2
8001598: 2b00 cmp r3, #0
800159a: d00a beq.n 80015b2 <HAL_CAN_IRQHandler+0x1b6>
{
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
800159c: 687b ldr r3, [r7, #4]
800159e: 681b ldr r3, [r3, #0]
80015a0: 68db ldr r3, [r3, #12]
80015a2: f003 0303 and.w r3, r3, #3
80015a6: 2b00 cmp r3, #0
80015a8: d003 beq.n 80015b2 <HAL_CAN_IRQHandler+0x1b6>
{
/* Receive FIFO 0 message pending Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
80015aa: 687b ldr r3, [r7, #4]
80015ac: 6c1b ldr r3, [r3, #64] @ 0x40
80015ae: 6878 ldr r0, [r7, #4]
80015b0: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
80015b2: 6a3b ldr r3, [r7, #32]
80015b4: f003 0340 and.w r3, r3, #64 @ 0x40
80015b8: 2b00 cmp r3, #0
80015ba: d00c beq.n 80015d6 <HAL_CAN_IRQHandler+0x1da>
{
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
80015bc: 693b ldr r3, [r7, #16]
80015be: f003 0310 and.w r3, r3, #16
80015c2: 2b00 cmp r3, #0
80015c4: d007 beq.n 80015d6 <HAL_CAN_IRQHandler+0x1da>
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
80015c6: 6a7b ldr r3, [r7, #36] @ 0x24
80015c8: f443 6380 orr.w r3, r3, #1024 @ 0x400
80015cc: 627b str r3, [r7, #36] @ 0x24
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
80015ce: 687b ldr r3, [r7, #4]
80015d0: 681b ldr r3, [r3, #0]
80015d2: 2210 movs r2, #16
80015d4: 611a str r2, [r3, #16]
}
}
/* Receive FIFO 1 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
80015d6: 6a3b ldr r3, [r7, #32]
80015d8: f003 0320 and.w r3, r3, #32
80015dc: 2b00 cmp r3, #0
80015de: d00c beq.n 80015fa <HAL_CAN_IRQHandler+0x1fe>
{
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
80015e0: 693b ldr r3, [r7, #16]
80015e2: f003 0308 and.w r3, r3, #8
80015e6: 2b00 cmp r3, #0
80015e8: d007 beq.n 80015fa <HAL_CAN_IRQHandler+0x1fe>
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
80015ea: 687b ldr r3, [r7, #4]
80015ec: 681b ldr r3, [r3, #0]
80015ee: 2208 movs r2, #8
80015f0: 611a str r2, [r3, #16]
/* Receive FIFO 1 full Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1FullCallback(hcan);
80015f2: 687b ldr r3, [r7, #4]
80015f4: 6cdb ldr r3, [r3, #76] @ 0x4c
80015f6: 6878 ldr r0, [r7, #4]
80015f8: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
80015fa: 6a3b ldr r3, [r7, #32]
80015fc: f003 0310 and.w r3, r3, #16
8001600: 2b00 cmp r3, #0
8001602: d00a beq.n 800161a <HAL_CAN_IRQHandler+0x21e>
{
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
8001604: 687b ldr r3, [r7, #4]
8001606: 681b ldr r3, [r3, #0]
8001608: 691b ldr r3, [r3, #16]
800160a: f003 0303 and.w r3, r3, #3
800160e: 2b00 cmp r3, #0
8001610: d003 beq.n 800161a <HAL_CAN_IRQHandler+0x21e>
{
/* Receive FIFO 1 message pending Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
8001612: 687b ldr r3, [r7, #4]
8001614: 6c9b ldr r3, [r3, #72] @ 0x48
8001616: 6878 ldr r0, [r7, #4]
8001618: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
800161a: 6a3b ldr r3, [r7, #32]
800161c: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001620: 2b00 cmp r3, #0
8001622: d00c beq.n 800163e <HAL_CAN_IRQHandler+0x242>
{
if ((msrflags & CAN_MSR_SLAKI) != 0U)
8001624: 69fb ldr r3, [r7, #28]
8001626: f003 0310 and.w r3, r3, #16
800162a: 2b00 cmp r3, #0
800162c: d007 beq.n 800163e <HAL_CAN_IRQHandler+0x242>
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
800162e: 687b ldr r3, [r7, #4]
8001630: 681b ldr r3, [r3, #0]
8001632: 2210 movs r2, #16
8001634: 605a str r2, [r3, #4]
/* Sleep Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->SleepCallback(hcan);
8001636: 687b ldr r3, [r7, #4]
8001638: 6d1b ldr r3, [r3, #80] @ 0x50
800163a: 6878 ldr r0, [r7, #4]
800163c: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
if ((interrupts & CAN_IT_WAKEUP) != 0U)
800163e: 6a3b ldr r3, [r7, #32]
8001640: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001644: 2b00 cmp r3, #0
8001646: d00c beq.n 8001662 <HAL_CAN_IRQHandler+0x266>
{
if ((msrflags & CAN_MSR_WKUI) != 0U)
8001648: 69fb ldr r3, [r7, #28]
800164a: f003 0308 and.w r3, r3, #8
800164e: 2b00 cmp r3, #0
8001650: d007 beq.n 8001662 <HAL_CAN_IRQHandler+0x266>
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
8001652: 687b ldr r3, [r7, #4]
8001654: 681b ldr r3, [r3, #0]
8001656: 2208 movs r2, #8
8001658: 605a str r2, [r3, #4]
/* WakeUp Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->WakeUpFromRxMsgCallback(hcan);
800165a: 687b ldr r3, [r7, #4]
800165c: 6d5b ldr r3, [r3, #84] @ 0x54
800165e: 6878 ldr r0, [r7, #4]
8001660: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
if ((interrupts & CAN_IT_ERROR) != 0U)
8001662: 6a3b ldr r3, [r7, #32]
8001664: f403 4300 and.w r3, r3, #32768 @ 0x8000
8001668: 2b00 cmp r3, #0
800166a: d07b beq.n 8001764 <HAL_CAN_IRQHandler+0x368>
{
if ((msrflags & CAN_MSR_ERRI) != 0U)
800166c: 69fb ldr r3, [r7, #28]
800166e: f003 0304 and.w r3, r3, #4
8001672: 2b00 cmp r3, #0
8001674: d072 beq.n 800175c <HAL_CAN_IRQHandler+0x360>
{
/* Check Error Warning Flag */
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
8001676: 6a3b ldr r3, [r7, #32]
8001678: f403 7380 and.w r3, r3, #256 @ 0x100
800167c: 2b00 cmp r3, #0
800167e: d008 beq.n 8001692 <HAL_CAN_IRQHandler+0x296>
((esrflags & CAN_ESR_EWGF) != 0U))
8001680: 68fb ldr r3, [r7, #12]
8001682: f003 0301 and.w r3, r3, #1
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
8001686: 2b00 cmp r3, #0
8001688: d003 beq.n 8001692 <HAL_CAN_IRQHandler+0x296>
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
800168a: 6a7b ldr r3, [r7, #36] @ 0x24
800168c: f043 0301 orr.w r3, r3, #1
8001690: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Warning Flag as read-only */
}
/* Check Error Passive Flag */
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8001692: 6a3b ldr r3, [r7, #32]
8001694: f403 7300 and.w r3, r3, #512 @ 0x200
8001698: 2b00 cmp r3, #0
800169a: d008 beq.n 80016ae <HAL_CAN_IRQHandler+0x2b2>
((esrflags & CAN_ESR_EPVF) != 0U))
800169c: 68fb ldr r3, [r7, #12]
800169e: f003 0302 and.w r3, r3, #2
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
80016a2: 2b00 cmp r3, #0
80016a4: d003 beq.n 80016ae <HAL_CAN_IRQHandler+0x2b2>
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
80016a6: 6a7b ldr r3, [r7, #36] @ 0x24
80016a8: f043 0302 orr.w r3, r3, #2
80016ac: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Passive Flag as read-only */
}
/* Check Bus-off Flag */
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
80016ae: 6a3b ldr r3, [r7, #32]
80016b0: f403 6380 and.w r3, r3, #1024 @ 0x400
80016b4: 2b00 cmp r3, #0
80016b6: d008 beq.n 80016ca <HAL_CAN_IRQHandler+0x2ce>
((esrflags & CAN_ESR_BOFF) != 0U))
80016b8: 68fb ldr r3, [r7, #12]
80016ba: f003 0304 and.w r3, r3, #4
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
80016be: 2b00 cmp r3, #0
80016c0: d003 beq.n 80016ca <HAL_CAN_IRQHandler+0x2ce>
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
80016c2: 6a7b ldr r3, [r7, #36] @ 0x24
80016c4: f043 0304 orr.w r3, r3, #4
80016c8: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Bus-Off as read-only */
}
/* Check Last Error Code Flag */
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
80016ca: 6a3b ldr r3, [r7, #32]
80016cc: f403 6300 and.w r3, r3, #2048 @ 0x800
80016d0: 2b00 cmp r3, #0
80016d2: d043 beq.n 800175c <HAL_CAN_IRQHandler+0x360>
((esrflags & CAN_ESR_LEC) != 0U))
80016d4: 68fb ldr r3, [r7, #12]
80016d6: f003 0370 and.w r3, r3, #112 @ 0x70
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
80016da: 2b00 cmp r3, #0
80016dc: d03e beq.n 800175c <HAL_CAN_IRQHandler+0x360>
{
switch (esrflags & CAN_ESR_LEC)
80016de: 68fb ldr r3, [r7, #12]
80016e0: f003 0370 and.w r3, r3, #112 @ 0x70
80016e4: 2b60 cmp r3, #96 @ 0x60
80016e6: d02b beq.n 8001740 <HAL_CAN_IRQHandler+0x344>
80016e8: 2b60 cmp r3, #96 @ 0x60
80016ea: d82e bhi.n 800174a <HAL_CAN_IRQHandler+0x34e>
80016ec: 2b50 cmp r3, #80 @ 0x50
80016ee: d022 beq.n 8001736 <HAL_CAN_IRQHandler+0x33a>
80016f0: 2b50 cmp r3, #80 @ 0x50
80016f2: d82a bhi.n 800174a <HAL_CAN_IRQHandler+0x34e>
80016f4: 2b40 cmp r3, #64 @ 0x40
80016f6: d019 beq.n 800172c <HAL_CAN_IRQHandler+0x330>
80016f8: 2b40 cmp r3, #64 @ 0x40
80016fa: d826 bhi.n 800174a <HAL_CAN_IRQHandler+0x34e>
80016fc: 2b30 cmp r3, #48 @ 0x30
80016fe: d010 beq.n 8001722 <HAL_CAN_IRQHandler+0x326>
8001700: 2b30 cmp r3, #48 @ 0x30
8001702: d822 bhi.n 800174a <HAL_CAN_IRQHandler+0x34e>
8001704: 2b10 cmp r3, #16
8001706: d002 beq.n 800170e <HAL_CAN_IRQHandler+0x312>
8001708: 2b20 cmp r3, #32
800170a: d005 beq.n 8001718 <HAL_CAN_IRQHandler+0x31c>
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
/* Set CAN error code to CRC error */
errorcode |= HAL_CAN_ERROR_CRC;
break;
default:
break;
800170c: e01d b.n 800174a <HAL_CAN_IRQHandler+0x34e>
errorcode |= HAL_CAN_ERROR_STF;
800170e: 6a7b ldr r3, [r7, #36] @ 0x24
8001710: f043 0308 orr.w r3, r3, #8
8001714: 627b str r3, [r7, #36] @ 0x24
break;
8001716: e019 b.n 800174c <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_FOR;
8001718: 6a7b ldr r3, [r7, #36] @ 0x24
800171a: f043 0310 orr.w r3, r3, #16
800171e: 627b str r3, [r7, #36] @ 0x24
break;
8001720: e014 b.n 800174c <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_ACK;
8001722: 6a7b ldr r3, [r7, #36] @ 0x24
8001724: f043 0320 orr.w r3, r3, #32
8001728: 627b str r3, [r7, #36] @ 0x24
break;
800172a: e00f b.n 800174c <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_BR;
800172c: 6a7b ldr r3, [r7, #36] @ 0x24
800172e: f043 0340 orr.w r3, r3, #64 @ 0x40
8001732: 627b str r3, [r7, #36] @ 0x24
break;
8001734: e00a b.n 800174c <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_BD;
8001736: 6a7b ldr r3, [r7, #36] @ 0x24
8001738: f043 0380 orr.w r3, r3, #128 @ 0x80
800173c: 627b str r3, [r7, #36] @ 0x24
break;
800173e: e005 b.n 800174c <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_CRC;
8001740: 6a7b ldr r3, [r7, #36] @ 0x24
8001742: f443 7380 orr.w r3, r3, #256 @ 0x100
8001746: 627b str r3, [r7, #36] @ 0x24
break;
8001748: e000 b.n 800174c <HAL_CAN_IRQHandler+0x350>
break;
800174a: bf00 nop
}
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
800174c: 687b ldr r3, [r7, #4]
800174e: 681b ldr r3, [r3, #0]
8001750: 699a ldr r2, [r3, #24]
8001752: 687b ldr r3, [r7, #4]
8001754: 681b ldr r3, [r3, #0]
8001756: f022 0270 bic.w r2, r2, #112 @ 0x70
800175a: 619a str r2, [r3, #24]
}
}
/* Clear ERRI Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
800175c: 687b ldr r3, [r7, #4]
800175e: 681b ldr r3, [r3, #0]
8001760: 2204 movs r2, #4
8001762: 605a str r2, [r3, #4]
}
/* Call the Error call Back in case of Errors */
if (errorcode != HAL_CAN_ERROR_NONE)
8001764: 6a7b ldr r3, [r7, #36] @ 0x24
8001766: 2b00 cmp r3, #0
8001768: d009 beq.n 800177e <HAL_CAN_IRQHandler+0x382>
{
/* Update error code in handle */
hcan->ErrorCode |= errorcode;
800176a: 687b ldr r3, [r7, #4]
800176c: 6a5a ldr r2, [r3, #36] @ 0x24
800176e: 6a7b ldr r3, [r7, #36] @ 0x24
8001770: 431a orrs r2, r3
8001772: 687b ldr r3, [r7, #4]
8001774: 625a str r2, [r3, #36] @ 0x24
/* Call Error callback function */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->ErrorCallback(hcan);
8001776: 687b ldr r3, [r7, #4]
8001778: 6d9b ldr r3, [r3, #88] @ 0x58
800177a: 6878 ldr r0, [r7, #4]
800177c: 4798 blx r3
#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
800177e: bf00 nop
8001780: 3728 adds r7, #40 @ 0x28
8001782: 46bd mov sp, r7
8001784: bd80 pop {r7, pc}
08001786 <HAL_CAN_TxMailbox0CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
8001786: b480 push {r7}
8001788: b083 sub sp, #12
800178a: af00 add r7, sp, #0
800178c: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
user file
*/
}
800178e: bf00 nop
8001790: 370c adds r7, #12
8001792: 46bd mov sp, r7
8001794: f85d 7b04 ldr.w r7, [sp], #4
8001798: 4770 bx lr
0800179a <HAL_CAN_TxMailbox1CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
800179a: b480 push {r7}
800179c: b083 sub sp, #12
800179e: af00 add r7, sp, #0
80017a0: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
user file
*/
}
80017a2: bf00 nop
80017a4: 370c adds r7, #12
80017a6: 46bd mov sp, r7
80017a8: f85d 7b04 ldr.w r7, [sp], #4
80017ac: 4770 bx lr
080017ae <HAL_CAN_TxMailbox2CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
80017ae: b480 push {r7}
80017b0: b083 sub sp, #12
80017b2: af00 add r7, sp, #0
80017b4: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
user file
*/
}
80017b6: bf00 nop
80017b8: 370c adds r7, #12
80017ba: 46bd mov sp, r7
80017bc: f85d 7b04 ldr.w r7, [sp], #4
80017c0: 4770 bx lr
080017c2 <HAL_CAN_TxMailbox0AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
80017c2: b480 push {r7}
80017c4: b083 sub sp, #12
80017c6: af00 add r7, sp, #0
80017c8: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
user file
*/
}
80017ca: bf00 nop
80017cc: 370c adds r7, #12
80017ce: 46bd mov sp, r7
80017d0: f85d 7b04 ldr.w r7, [sp], #4
80017d4: 4770 bx lr
080017d6 <HAL_CAN_TxMailbox1AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
80017d6: b480 push {r7}
80017d8: b083 sub sp, #12
80017da: af00 add r7, sp, #0
80017dc: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
user file
*/
}
80017de: bf00 nop
80017e0: 370c adds r7, #12
80017e2: 46bd mov sp, r7
80017e4: f85d 7b04 ldr.w r7, [sp], #4
80017e8: 4770 bx lr
080017ea <HAL_CAN_TxMailbox2AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
80017ea: b480 push {r7}
80017ec: b083 sub sp, #12
80017ee: af00 add r7, sp, #0
80017f0: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
user file
*/
}
80017f2: bf00 nop
80017f4: 370c adds r7, #12
80017f6: 46bd mov sp, r7
80017f8: f85d 7b04 ldr.w r7, [sp], #4
80017fc: 4770 bx lr
080017fe <HAL_CAN_RxFifo0FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
80017fe: b480 push {r7}
8001800: b083 sub sp, #12
8001802: af00 add r7, sp, #0
8001804: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
file
*/
}
8001806: bf00 nop
8001808: 370c adds r7, #12
800180a: 46bd mov sp, r7
800180c: f85d 7b04 ldr.w r7, [sp], #4
8001810: 4770 bx lr
08001812 <HAL_CAN_RxFifo1MsgPendingCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
8001812: b480 push {r7}
8001814: b083 sub sp, #12
8001816: af00 add r7, sp, #0
8001818: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
user file
*/
}
800181a: bf00 nop
800181c: 370c adds r7, #12
800181e: 46bd mov sp, r7
8001820: f85d 7b04 ldr.w r7, [sp], #4
8001824: 4770 bx lr
08001826 <HAL_CAN_RxFifo1FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
8001826: b480 push {r7}
8001828: b083 sub sp, #12
800182a: af00 add r7, sp, #0
800182c: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
file
*/
}
800182e: bf00 nop
8001830: 370c adds r7, #12
8001832: 46bd mov sp, r7
8001834: f85d 7b04 ldr.w r7, [sp], #4
8001838: 4770 bx lr
0800183a <HAL_CAN_SleepCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
800183a: b480 push {r7}
800183c: b083 sub sp, #12
800183e: af00 add r7, sp, #0
8001840: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_SleepCallback could be implemented in the user file
*/
}
8001842: bf00 nop
8001844: 370c adds r7, #12
8001846: 46bd mov sp, r7
8001848: f85d 7b04 ldr.w r7, [sp], #4
800184c: 4770 bx lr
0800184e <HAL_CAN_WakeUpFromRxMsgCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
800184e: b480 push {r7}
8001850: b083 sub sp, #12
8001852: af00 add r7, sp, #0
8001854: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
user file
*/
}
8001856: bf00 nop
8001858: 370c adds r7, #12
800185a: 46bd mov sp, r7
800185c: f85d 7b04 ldr.w r7, [sp], #4
8001860: 4770 bx lr
08001862 <HAL_CAN_ErrorCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
8001862: b480 push {r7}
8001864: b083 sub sp, #12
8001866: af00 add r7, sp, #0
8001868: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
800186a: bf00 nop
800186c: 370c adds r7, #12
800186e: 46bd mov sp, r7
8001870: f85d 7b04 ldr.w r7, [sp], #4
8001874: 4770 bx lr
...
08001878 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001878: b480 push {r7}
800187a: b085 sub sp, #20
800187c: af00 add r7, sp, #0
800187e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001880: 687b ldr r3, [r7, #4]
8001882: f003 0307 and.w r3, r3, #7
8001886: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001888: 4b0c ldr r3, [pc, #48] @ (80018bc <__NVIC_SetPriorityGrouping+0x44>)
800188a: 68db ldr r3, [r3, #12]
800188c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800188e: 68ba ldr r2, [r7, #8]
8001890: f64f 03ff movw r3, #63743 @ 0xf8ff
8001894: 4013 ands r3, r2
8001896: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001898: 68fb ldr r3, [r7, #12]
800189a: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
800189c: 68bb ldr r3, [r7, #8]
800189e: 4313 orrs r3, r2
reg_value = (reg_value |
80018a0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
80018a4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80018a8: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80018aa: 4a04 ldr r2, [pc, #16] @ (80018bc <__NVIC_SetPriorityGrouping+0x44>)
80018ac: 68bb ldr r3, [r7, #8]
80018ae: 60d3 str r3, [r2, #12]
}
80018b0: bf00 nop
80018b2: 3714 adds r7, #20
80018b4: 46bd mov sp, r7
80018b6: f85d 7b04 ldr.w r7, [sp], #4
80018ba: 4770 bx lr
80018bc: e000ed00 .word 0xe000ed00
080018c0 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80018c0: b480 push {r7}
80018c2: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80018c4: 4b04 ldr r3, [pc, #16] @ (80018d8 <__NVIC_GetPriorityGrouping+0x18>)
80018c6: 68db ldr r3, [r3, #12]
80018c8: 0a1b lsrs r3, r3, #8
80018ca: f003 0307 and.w r3, r3, #7
}
80018ce: 4618 mov r0, r3
80018d0: 46bd mov sp, r7
80018d2: f85d 7b04 ldr.w r7, [sp], #4
80018d6: 4770 bx lr
80018d8: e000ed00 .word 0xe000ed00
080018dc <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80018dc: b480 push {r7}
80018de: b083 sub sp, #12
80018e0: af00 add r7, sp, #0
80018e2: 4603 mov r3, r0
80018e4: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80018e6: f997 3007 ldrsb.w r3, [r7, #7]
80018ea: 2b00 cmp r3, #0
80018ec: db0b blt.n 8001906 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80018ee: 79fb ldrb r3, [r7, #7]
80018f0: f003 021f and.w r2, r3, #31
80018f4: 4907 ldr r1, [pc, #28] @ (8001914 <__NVIC_EnableIRQ+0x38>)
80018f6: f997 3007 ldrsb.w r3, [r7, #7]
80018fa: 095b lsrs r3, r3, #5
80018fc: 2001 movs r0, #1
80018fe: fa00 f202 lsl.w r2, r0, r2
8001902: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001906: bf00 nop
8001908: 370c adds r7, #12
800190a: 46bd mov sp, r7
800190c: f85d 7b04 ldr.w r7, [sp], #4
8001910: 4770 bx lr
8001912: bf00 nop
8001914: e000e100 .word 0xe000e100
08001918 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001918: b480 push {r7}
800191a: b083 sub sp, #12
800191c: af00 add r7, sp, #0
800191e: 4603 mov r3, r0
8001920: 6039 str r1, [r7, #0]
8001922: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001924: f997 3007 ldrsb.w r3, [r7, #7]
8001928: 2b00 cmp r3, #0
800192a: db0a blt.n 8001942 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800192c: 683b ldr r3, [r7, #0]
800192e: b2da uxtb r2, r3
8001930: 490c ldr r1, [pc, #48] @ (8001964 <__NVIC_SetPriority+0x4c>)
8001932: f997 3007 ldrsb.w r3, [r7, #7]
8001936: 0112 lsls r2, r2, #4
8001938: b2d2 uxtb r2, r2
800193a: 440b add r3, r1
800193c: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001940: e00a b.n 8001958 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001942: 683b ldr r3, [r7, #0]
8001944: b2da uxtb r2, r3
8001946: 4908 ldr r1, [pc, #32] @ (8001968 <__NVIC_SetPriority+0x50>)
8001948: 79fb ldrb r3, [r7, #7]
800194a: f003 030f and.w r3, r3, #15
800194e: 3b04 subs r3, #4
8001950: 0112 lsls r2, r2, #4
8001952: b2d2 uxtb r2, r2
8001954: 440b add r3, r1
8001956: 761a strb r2, [r3, #24]
}
8001958: bf00 nop
800195a: 370c adds r7, #12
800195c: 46bd mov sp, r7
800195e: f85d 7b04 ldr.w r7, [sp], #4
8001962: 4770 bx lr
8001964: e000e100 .word 0xe000e100
8001968: e000ed00 .word 0xe000ed00
0800196c <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
800196c: b480 push {r7}
800196e: b089 sub sp, #36 @ 0x24
8001970: af00 add r7, sp, #0
8001972: 60f8 str r0, [r7, #12]
8001974: 60b9 str r1, [r7, #8]
8001976: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001978: 68fb ldr r3, [r7, #12]
800197a: f003 0307 and.w r3, r3, #7
800197e: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001980: 69fb ldr r3, [r7, #28]
8001982: f1c3 0307 rsb r3, r3, #7
8001986: 2b04 cmp r3, #4
8001988: bf28 it cs
800198a: 2304 movcs r3, #4
800198c: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800198e: 69fb ldr r3, [r7, #28]
8001990: 3304 adds r3, #4
8001992: 2b06 cmp r3, #6
8001994: d902 bls.n 800199c <NVIC_EncodePriority+0x30>
8001996: 69fb ldr r3, [r7, #28]
8001998: 3b03 subs r3, #3
800199a: e000 b.n 800199e <NVIC_EncodePriority+0x32>
800199c: 2300 movs r3, #0
800199e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80019a0: f04f 32ff mov.w r2, #4294967295
80019a4: 69bb ldr r3, [r7, #24]
80019a6: fa02 f303 lsl.w r3, r2, r3
80019aa: 43da mvns r2, r3
80019ac: 68bb ldr r3, [r7, #8]
80019ae: 401a ands r2, r3
80019b0: 697b ldr r3, [r7, #20]
80019b2: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80019b4: f04f 31ff mov.w r1, #4294967295
80019b8: 697b ldr r3, [r7, #20]
80019ba: fa01 f303 lsl.w r3, r1, r3
80019be: 43d9 mvns r1, r3
80019c0: 687b ldr r3, [r7, #4]
80019c2: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80019c4: 4313 orrs r3, r2
);
}
80019c6: 4618 mov r0, r3
80019c8: 3724 adds r7, #36 @ 0x24
80019ca: 46bd mov sp, r7
80019cc: f85d 7b04 ldr.w r7, [sp], #4
80019d0: 4770 bx lr
...
080019d4 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80019d4: b580 push {r7, lr}
80019d6: b082 sub sp, #8
80019d8: af00 add r7, sp, #0
80019da: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80019dc: 687b ldr r3, [r7, #4]
80019de: 3b01 subs r3, #1
80019e0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80019e4: d301 bcc.n 80019ea <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80019e6: 2301 movs r3, #1
80019e8: e00f b.n 8001a0a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80019ea: 4a0a ldr r2, [pc, #40] @ (8001a14 <SysTick_Config+0x40>)
80019ec: 687b ldr r3, [r7, #4]
80019ee: 3b01 subs r3, #1
80019f0: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80019f2: 210f movs r1, #15
80019f4: f04f 30ff mov.w r0, #4294967295
80019f8: f7ff ff8e bl 8001918 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80019fc: 4b05 ldr r3, [pc, #20] @ (8001a14 <SysTick_Config+0x40>)
80019fe: 2200 movs r2, #0
8001a00: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001a02: 4b04 ldr r3, [pc, #16] @ (8001a14 <SysTick_Config+0x40>)
8001a04: 2207 movs r2, #7
8001a06: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001a08: 2300 movs r3, #0
}
8001a0a: 4618 mov r0, r3
8001a0c: 3708 adds r7, #8
8001a0e: 46bd mov sp, r7
8001a10: bd80 pop {r7, pc}
8001a12: bf00 nop
8001a14: e000e010 .word 0xe000e010
08001a18 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001a18: b580 push {r7, lr}
8001a1a: b082 sub sp, #8
8001a1c: af00 add r7, sp, #0
8001a1e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001a20: 6878 ldr r0, [r7, #4]
8001a22: f7ff ff29 bl 8001878 <__NVIC_SetPriorityGrouping>
}
8001a26: bf00 nop
8001a28: 3708 adds r7, #8
8001a2a: 46bd mov sp, r7
8001a2c: bd80 pop {r7, pc}
08001a2e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001a2e: b580 push {r7, lr}
8001a30: b086 sub sp, #24
8001a32: af00 add r7, sp, #0
8001a34: 4603 mov r3, r0
8001a36: 60b9 str r1, [r7, #8]
8001a38: 607a str r2, [r7, #4]
8001a3a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8001a3c: 2300 movs r3, #0
8001a3e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001a40: f7ff ff3e bl 80018c0 <__NVIC_GetPriorityGrouping>
8001a44: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001a46: 687a ldr r2, [r7, #4]
8001a48: 68b9 ldr r1, [r7, #8]
8001a4a: 6978 ldr r0, [r7, #20]
8001a4c: f7ff ff8e bl 800196c <NVIC_EncodePriority>
8001a50: 4602 mov r2, r0
8001a52: f997 300f ldrsb.w r3, [r7, #15]
8001a56: 4611 mov r1, r2
8001a58: 4618 mov r0, r3
8001a5a: f7ff ff5d bl 8001918 <__NVIC_SetPriority>
}
8001a5e: bf00 nop
8001a60: 3718 adds r7, #24
8001a62: 46bd mov sp, r7
8001a64: bd80 pop {r7, pc}
08001a66 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001a66: b580 push {r7, lr}
8001a68: b082 sub sp, #8
8001a6a: af00 add r7, sp, #0
8001a6c: 4603 mov r3, r0
8001a6e: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001a70: f997 3007 ldrsb.w r3, [r7, #7]
8001a74: 4618 mov r0, r3
8001a76: f7ff ff31 bl 80018dc <__NVIC_EnableIRQ>
}
8001a7a: bf00 nop
8001a7c: 3708 adds r7, #8
8001a7e: 46bd mov sp, r7
8001a80: bd80 pop {r7, pc}
08001a82 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8001a82: b580 push {r7, lr}
8001a84: b082 sub sp, #8
8001a86: af00 add r7, sp, #0
8001a88: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001a8a: 6878 ldr r0, [r7, #4]
8001a8c: f7ff ffa2 bl 80019d4 <SysTick_Config>
8001a90: 4603 mov r3, r0
}
8001a92: 4618 mov r0, r3
8001a94: 3708 adds r7, #8
8001a96: 46bd mov sp, r7
8001a98: bd80 pop {r7, pc}
...
08001a9c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001a9c: b480 push {r7}
8001a9e: b087 sub sp, #28
8001aa0: af00 add r7, sp, #0
8001aa2: 6078 str r0, [r7, #4]
8001aa4: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8001aa6: 2300 movs r3, #0
8001aa8: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001aaa: e154 b.n 8001d56 <HAL_GPIO_Init+0x2ba>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8001aac: 683b ldr r3, [r7, #0]
8001aae: 681a ldr r2, [r3, #0]
8001ab0: 2101 movs r1, #1
8001ab2: 697b ldr r3, [r7, #20]
8001ab4: fa01 f303 lsl.w r3, r1, r3
8001ab8: 4013 ands r3, r2
8001aba: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001abc: 68fb ldr r3, [r7, #12]
8001abe: 2b00 cmp r3, #0
8001ac0: f000 8146 beq.w 8001d50 <HAL_GPIO_Init+0x2b4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001ac4: 683b ldr r3, [r7, #0]
8001ac6: 685b ldr r3, [r3, #4]
8001ac8: f003 0303 and.w r3, r3, #3
8001acc: 2b01 cmp r3, #1
8001ace: d005 beq.n 8001adc <HAL_GPIO_Init+0x40>
8001ad0: 683b ldr r3, [r7, #0]
8001ad2: 685b ldr r3, [r3, #4]
8001ad4: f003 0303 and.w r3, r3, #3
8001ad8: 2b02 cmp r3, #2
8001ada: d130 bne.n 8001b3e <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001adc: 687b ldr r3, [r7, #4]
8001ade: 689b ldr r3, [r3, #8]
8001ae0: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
8001ae2: 697b ldr r3, [r7, #20]
8001ae4: 005b lsls r3, r3, #1
8001ae6: 2203 movs r2, #3
8001ae8: fa02 f303 lsl.w r3, r2, r3
8001aec: 43db mvns r3, r3
8001aee: 693a ldr r2, [r7, #16]
8001af0: 4013 ands r3, r2
8001af2: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001af4: 683b ldr r3, [r7, #0]
8001af6: 68da ldr r2, [r3, #12]
8001af8: 697b ldr r3, [r7, #20]
8001afa: 005b lsls r3, r3, #1
8001afc: fa02 f303 lsl.w r3, r2, r3
8001b00: 693a ldr r2, [r7, #16]
8001b02: 4313 orrs r3, r2
8001b04: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8001b06: 687b ldr r3, [r7, #4]
8001b08: 693a ldr r2, [r7, #16]
8001b0a: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001b0c: 687b ldr r3, [r7, #4]
8001b0e: 685b ldr r3, [r3, #4]
8001b10: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001b12: 2201 movs r2, #1
8001b14: 697b ldr r3, [r7, #20]
8001b16: fa02 f303 lsl.w r3, r2, r3
8001b1a: 43db mvns r3, r3
8001b1c: 693a ldr r2, [r7, #16]
8001b1e: 4013 ands r3, r2
8001b20: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001b22: 683b ldr r3, [r7, #0]
8001b24: 685b ldr r3, [r3, #4]
8001b26: 091b lsrs r3, r3, #4
8001b28: f003 0201 and.w r2, r3, #1
8001b2c: 697b ldr r3, [r7, #20]
8001b2e: fa02 f303 lsl.w r3, r2, r3
8001b32: 693a ldr r2, [r7, #16]
8001b34: 4313 orrs r3, r2
8001b36: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 693a ldr r2, [r7, #16]
8001b3c: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001b3e: 683b ldr r3, [r7, #0]
8001b40: 685b ldr r3, [r3, #4]
8001b42: f003 0303 and.w r3, r3, #3
8001b46: 2b03 cmp r3, #3
8001b48: d017 beq.n 8001b7a <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001b4a: 687b ldr r3, [r7, #4]
8001b4c: 68db ldr r3, [r3, #12]
8001b4e: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8001b50: 697b ldr r3, [r7, #20]
8001b52: 005b lsls r3, r3, #1
8001b54: 2203 movs r2, #3
8001b56: fa02 f303 lsl.w r3, r2, r3
8001b5a: 43db mvns r3, r3
8001b5c: 693a ldr r2, [r7, #16]
8001b5e: 4013 ands r3, r2
8001b60: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
8001b62: 683b ldr r3, [r7, #0]
8001b64: 689a ldr r2, [r3, #8]
8001b66: 697b ldr r3, [r7, #20]
8001b68: 005b lsls r3, r3, #1
8001b6a: fa02 f303 lsl.w r3, r2, r3
8001b6e: 693a ldr r2, [r7, #16]
8001b70: 4313 orrs r3, r2
8001b72: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8001b74: 687b ldr r3, [r7, #4]
8001b76: 693a ldr r2, [r7, #16]
8001b78: 60da str r2, [r3, #12]
}
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001b7a: 683b ldr r3, [r7, #0]
8001b7c: 685b ldr r3, [r3, #4]
8001b7e: f003 0303 and.w r3, r3, #3
8001b82: 2b02 cmp r3, #2
8001b84: d123 bne.n 8001bce <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8001b86: 697b ldr r3, [r7, #20]
8001b88: 08da lsrs r2, r3, #3
8001b8a: 687b ldr r3, [r7, #4]
8001b8c: 3208 adds r2, #8
8001b8e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001b92: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8001b94: 697b ldr r3, [r7, #20]
8001b96: f003 0307 and.w r3, r3, #7
8001b9a: 009b lsls r3, r3, #2
8001b9c: 220f movs r2, #15
8001b9e: fa02 f303 lsl.w r3, r2, r3
8001ba2: 43db mvns r3, r3
8001ba4: 693a ldr r2, [r7, #16]
8001ba6: 4013 ands r3, r2
8001ba8: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8001baa: 683b ldr r3, [r7, #0]
8001bac: 691a ldr r2, [r3, #16]
8001bae: 697b ldr r3, [r7, #20]
8001bb0: f003 0307 and.w r3, r3, #7
8001bb4: 009b lsls r3, r3, #2
8001bb6: fa02 f303 lsl.w r3, r2, r3
8001bba: 693a ldr r2, [r7, #16]
8001bbc: 4313 orrs r3, r2
8001bbe: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001bc0: 697b ldr r3, [r7, #20]
8001bc2: 08da lsrs r2, r3, #3
8001bc4: 687b ldr r3, [r7, #4]
8001bc6: 3208 adds r2, #8
8001bc8: 6939 ldr r1, [r7, #16]
8001bca: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001bce: 687b ldr r3, [r7, #4]
8001bd0: 681b ldr r3, [r3, #0]
8001bd2: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8001bd4: 697b ldr r3, [r7, #20]
8001bd6: 005b lsls r3, r3, #1
8001bd8: 2203 movs r2, #3
8001bda: fa02 f303 lsl.w r3, r2, r3
8001bde: 43db mvns r3, r3
8001be0: 693a ldr r2, [r7, #16]
8001be2: 4013 ands r3, r2
8001be4: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001be6: 683b ldr r3, [r7, #0]
8001be8: 685b ldr r3, [r3, #4]
8001bea: f003 0203 and.w r2, r3, #3
8001bee: 697b ldr r3, [r7, #20]
8001bf0: 005b lsls r3, r3, #1
8001bf2: fa02 f303 lsl.w r3, r2, r3
8001bf6: 693a ldr r2, [r7, #16]
8001bf8: 4313 orrs r3, r2
8001bfa: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001bfc: 687b ldr r3, [r7, #4]
8001bfe: 693a ldr r2, [r7, #16]
8001c00: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001c02: 683b ldr r3, [r7, #0]
8001c04: 685b ldr r3, [r3, #4]
8001c06: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001c0a: 2b00 cmp r3, #0
8001c0c: f000 80a0 beq.w 8001d50 <HAL_GPIO_Init+0x2b4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001c10: 4b58 ldr r3, [pc, #352] @ (8001d74 <HAL_GPIO_Init+0x2d8>)
8001c12: 699b ldr r3, [r3, #24]
8001c14: 4a57 ldr r2, [pc, #348] @ (8001d74 <HAL_GPIO_Init+0x2d8>)
8001c16: f043 0301 orr.w r3, r3, #1
8001c1a: 6193 str r3, [r2, #24]
8001c1c: 4b55 ldr r3, [pc, #340] @ (8001d74 <HAL_GPIO_Init+0x2d8>)
8001c1e: 699b ldr r3, [r3, #24]
8001c20: f003 0301 and.w r3, r3, #1
8001c24: 60bb str r3, [r7, #8]
8001c26: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8001c28: 4a53 ldr r2, [pc, #332] @ (8001d78 <HAL_GPIO_Init+0x2dc>)
8001c2a: 697b ldr r3, [r7, #20]
8001c2c: 089b lsrs r3, r3, #2
8001c2e: 3302 adds r3, #2
8001c30: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001c34: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8001c36: 697b ldr r3, [r7, #20]
8001c38: f003 0303 and.w r3, r3, #3
8001c3c: 009b lsls r3, r3, #2
8001c3e: 220f movs r2, #15
8001c40: fa02 f303 lsl.w r3, r2, r3
8001c44: 43db mvns r3, r3
8001c46: 693a ldr r2, [r7, #16]
8001c48: 4013 ands r3, r2
8001c4a: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8001c4c: 687b ldr r3, [r7, #4]
8001c4e: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8001c52: d019 beq.n 8001c88 <HAL_GPIO_Init+0x1ec>
8001c54: 687b ldr r3, [r7, #4]
8001c56: 4a49 ldr r2, [pc, #292] @ (8001d7c <HAL_GPIO_Init+0x2e0>)
8001c58: 4293 cmp r3, r2
8001c5a: d013 beq.n 8001c84 <HAL_GPIO_Init+0x1e8>
8001c5c: 687b ldr r3, [r7, #4]
8001c5e: 4a48 ldr r2, [pc, #288] @ (8001d80 <HAL_GPIO_Init+0x2e4>)
8001c60: 4293 cmp r3, r2
8001c62: d00d beq.n 8001c80 <HAL_GPIO_Init+0x1e4>
8001c64: 687b ldr r3, [r7, #4]
8001c66: 4a47 ldr r2, [pc, #284] @ (8001d84 <HAL_GPIO_Init+0x2e8>)
8001c68: 4293 cmp r3, r2
8001c6a: d007 beq.n 8001c7c <HAL_GPIO_Init+0x1e0>
8001c6c: 687b ldr r3, [r7, #4]
8001c6e: 4a46 ldr r2, [pc, #280] @ (8001d88 <HAL_GPIO_Init+0x2ec>)
8001c70: 4293 cmp r3, r2
8001c72: d101 bne.n 8001c78 <HAL_GPIO_Init+0x1dc>
8001c74: 2304 movs r3, #4
8001c76: e008 b.n 8001c8a <HAL_GPIO_Init+0x1ee>
8001c78: 2305 movs r3, #5
8001c7a: e006 b.n 8001c8a <HAL_GPIO_Init+0x1ee>
8001c7c: 2303 movs r3, #3
8001c7e: e004 b.n 8001c8a <HAL_GPIO_Init+0x1ee>
8001c80: 2302 movs r3, #2
8001c82: e002 b.n 8001c8a <HAL_GPIO_Init+0x1ee>
8001c84: 2301 movs r3, #1
8001c86: e000 b.n 8001c8a <HAL_GPIO_Init+0x1ee>
8001c88: 2300 movs r3, #0
8001c8a: 697a ldr r2, [r7, #20]
8001c8c: f002 0203 and.w r2, r2, #3
8001c90: 0092 lsls r2, r2, #2
8001c92: 4093 lsls r3, r2
8001c94: 693a ldr r2, [r7, #16]
8001c96: 4313 orrs r3, r2
8001c98: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8001c9a: 4937 ldr r1, [pc, #220] @ (8001d78 <HAL_GPIO_Init+0x2dc>)
8001c9c: 697b ldr r3, [r7, #20]
8001c9e: 089b lsrs r3, r3, #2
8001ca0: 3302 adds r3, #2
8001ca2: 693a ldr r2, [r7, #16]
8001ca4: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001ca8: 4b38 ldr r3, [pc, #224] @ (8001d8c <HAL_GPIO_Init+0x2f0>)
8001caa: 689b ldr r3, [r3, #8]
8001cac: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001cae: 68fb ldr r3, [r7, #12]
8001cb0: 43db mvns r3, r3
8001cb2: 693a ldr r2, [r7, #16]
8001cb4: 4013 ands r3, r2
8001cb6: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001cb8: 683b ldr r3, [r7, #0]
8001cba: 685b ldr r3, [r3, #4]
8001cbc: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001cc0: 2b00 cmp r3, #0
8001cc2: d003 beq.n 8001ccc <HAL_GPIO_Init+0x230>
{
temp |= iocurrent;
8001cc4: 693a ldr r2, [r7, #16]
8001cc6: 68fb ldr r3, [r7, #12]
8001cc8: 4313 orrs r3, r2
8001cca: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8001ccc: 4a2f ldr r2, [pc, #188] @ (8001d8c <HAL_GPIO_Init+0x2f0>)
8001cce: 693b ldr r3, [r7, #16]
8001cd0: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001cd2: 4b2e ldr r3, [pc, #184] @ (8001d8c <HAL_GPIO_Init+0x2f0>)
8001cd4: 68db ldr r3, [r3, #12]
8001cd6: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001cd8: 68fb ldr r3, [r7, #12]
8001cda: 43db mvns r3, r3
8001cdc: 693a ldr r2, [r7, #16]
8001cde: 4013 ands r3, r2
8001ce0: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8001ce2: 683b ldr r3, [r7, #0]
8001ce4: 685b ldr r3, [r3, #4]
8001ce6: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001cea: 2b00 cmp r3, #0
8001cec: d003 beq.n 8001cf6 <HAL_GPIO_Init+0x25a>
{
temp |= iocurrent;
8001cee: 693a ldr r2, [r7, #16]
8001cf0: 68fb ldr r3, [r7, #12]
8001cf2: 4313 orrs r3, r2
8001cf4: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8001cf6: 4a25 ldr r2, [pc, #148] @ (8001d8c <HAL_GPIO_Init+0x2f0>)
8001cf8: 693b ldr r3, [r7, #16]
8001cfa: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001cfc: 4b23 ldr r3, [pc, #140] @ (8001d8c <HAL_GPIO_Init+0x2f0>)
8001cfe: 685b ldr r3, [r3, #4]
8001d00: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001d02: 68fb ldr r3, [r7, #12]
8001d04: 43db mvns r3, r3
8001d06: 693a ldr r2, [r7, #16]
8001d08: 4013 ands r3, r2
8001d0a: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001d0c: 683b ldr r3, [r7, #0]
8001d0e: 685b ldr r3, [r3, #4]
8001d10: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001d14: 2b00 cmp r3, #0
8001d16: d003 beq.n 8001d20 <HAL_GPIO_Init+0x284>
{
temp |= iocurrent;
8001d18: 693a ldr r2, [r7, #16]
8001d1a: 68fb ldr r3, [r7, #12]
8001d1c: 4313 orrs r3, r2
8001d1e: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8001d20: 4a1a ldr r2, [pc, #104] @ (8001d8c <HAL_GPIO_Init+0x2f0>)
8001d22: 693b ldr r3, [r7, #16]
8001d24: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001d26: 4b19 ldr r3, [pc, #100] @ (8001d8c <HAL_GPIO_Init+0x2f0>)
8001d28: 681b ldr r3, [r3, #0]
8001d2a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001d2c: 68fb ldr r3, [r7, #12]
8001d2e: 43db mvns r3, r3
8001d30: 693a ldr r2, [r7, #16]
8001d32: 4013 ands r3, r2
8001d34: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001d36: 683b ldr r3, [r7, #0]
8001d38: 685b ldr r3, [r3, #4]
8001d3a: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001d3e: 2b00 cmp r3, #0
8001d40: d003 beq.n 8001d4a <HAL_GPIO_Init+0x2ae>
{
temp |= iocurrent;
8001d42: 693a ldr r2, [r7, #16]
8001d44: 68fb ldr r3, [r7, #12]
8001d46: 4313 orrs r3, r2
8001d48: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8001d4a: 4a10 ldr r2, [pc, #64] @ (8001d8c <HAL_GPIO_Init+0x2f0>)
8001d4c: 693b ldr r3, [r7, #16]
8001d4e: 6013 str r3, [r2, #0]
}
}
position++;
8001d50: 697b ldr r3, [r7, #20]
8001d52: 3301 adds r3, #1
8001d54: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001d56: 683b ldr r3, [r7, #0]
8001d58: 681a ldr r2, [r3, #0]
8001d5a: 697b ldr r3, [r7, #20]
8001d5c: fa22 f303 lsr.w r3, r2, r3
8001d60: 2b00 cmp r3, #0
8001d62: f47f aea3 bne.w 8001aac <HAL_GPIO_Init+0x10>
}
}
8001d66: bf00 nop
8001d68: bf00 nop
8001d6a: 371c adds r7, #28
8001d6c: 46bd mov sp, r7
8001d6e: f85d 7b04 ldr.w r7, [sp], #4
8001d72: 4770 bx lr
8001d74: 40021000 .word 0x40021000
8001d78: 40010000 .word 0x40010000
8001d7c: 48000400 .word 0x48000400
8001d80: 48000800 .word 0x48000800
8001d84: 48000c00 .word 0x48000c00
8001d88: 48001000 .word 0x48001000
8001d8c: 40010400 .word 0x40010400
08001d90 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001d90: b480 push {r7}
8001d92: b085 sub sp, #20
8001d94: af00 add r7, sp, #0
8001d96: 6078 str r0, [r7, #4]
8001d98: 460b mov r3, r1
8001d9a: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8001d9c: 687b ldr r3, [r7, #4]
8001d9e: 691a ldr r2, [r3, #16]
8001da0: 887b ldrh r3, [r7, #2]
8001da2: 4013 ands r3, r2
8001da4: 2b00 cmp r3, #0
8001da6: d002 beq.n 8001dae <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8001da8: 2301 movs r3, #1
8001daa: 73fb strb r3, [r7, #15]
8001dac: e001 b.n 8001db2 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8001dae: 2300 movs r3, #0
8001db0: 73fb strb r3, [r7, #15]
}
return bitstatus;
8001db2: 7bfb ldrb r3, [r7, #15]
}
8001db4: 4618 mov r0, r3
8001db6: 3714 adds r7, #20
8001db8: 46bd mov sp, r7
8001dba: f85d 7b04 ldr.w r7, [sp], #4
8001dbe: 4770 bx lr
08001dc0 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001dc0: b480 push {r7}
8001dc2: b083 sub sp, #12
8001dc4: af00 add r7, sp, #0
8001dc6: 6078 str r0, [r7, #4]
8001dc8: 460b mov r3, r1
8001dca: 807b strh r3, [r7, #2]
8001dcc: 4613 mov r3, r2
8001dce: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001dd0: 787b ldrb r3, [r7, #1]
8001dd2: 2b00 cmp r3, #0
8001dd4: d003 beq.n 8001dde <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001dd6: 887a ldrh r2, [r7, #2]
8001dd8: 687b ldr r3, [r7, #4]
8001dda: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8001ddc: e002 b.n 8001de4 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8001dde: 887a ldrh r2, [r7, #2]
8001de0: 687b ldr r3, [r7, #4]
8001de2: 629a str r2, [r3, #40] @ 0x28
}
8001de4: bf00 nop
8001de6: 370c adds r7, #12
8001de8: 46bd mov sp, r7
8001dea: f85d 7b04 ldr.w r7, [sp], #4
8001dee: 4770 bx lr
08001df0 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001df0: b580 push {r7, lr}
8001df2: f5ad 7d00 sub.w sp, sp, #512 @ 0x200
8001df6: af00 add r7, sp, #0
8001df8: f507 7300 add.w r3, r7, #512 @ 0x200
8001dfc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001e00: 6018 str r0, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
uint32_t pll_config2;
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8001e02: f507 7300 add.w r3, r7, #512 @ 0x200
8001e06: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001e0a: 681b ldr r3, [r3, #0]
8001e0c: 2b00 cmp r3, #0
8001e0e: d102 bne.n 8001e16 <HAL_RCC_OscConfig+0x26>
{
return HAL_ERROR;
8001e10: 2301 movs r3, #1
8001e12: f001 b823 b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001e16: f507 7300 add.w r3, r7, #512 @ 0x200
8001e1a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001e1e: 681b ldr r3, [r3, #0]
8001e20: 681b ldr r3, [r3, #0]
8001e22: f003 0301 and.w r3, r3, #1
8001e26: 2b00 cmp r3, #0
8001e28: f000 817d beq.w 8002126 <HAL_RCC_OscConfig+0x336>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001e2c: 4bbc ldr r3, [pc, #752] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001e2e: 685b ldr r3, [r3, #4]
8001e30: f003 030c and.w r3, r3, #12
8001e34: 2b04 cmp r3, #4
8001e36: d00c beq.n 8001e52 <HAL_RCC_OscConfig+0x62>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8001e38: 4bb9 ldr r3, [pc, #740] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001e3a: 685b ldr r3, [r3, #4]
8001e3c: f003 030c and.w r3, r3, #12
8001e40: 2b08 cmp r3, #8
8001e42: d15c bne.n 8001efe <HAL_RCC_OscConfig+0x10e>
8001e44: 4bb6 ldr r3, [pc, #728] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001e46: 685b ldr r3, [r3, #4]
8001e48: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001e4c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001e50: d155 bne.n 8001efe <HAL_RCC_OscConfig+0x10e>
8001e52: f44f 3300 mov.w r3, #131072 @ 0x20000
8001e56: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001e5a: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0
8001e5e: fa93 f3a3 rbit r3, r3
8001e62: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8001e66: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001e6a: fab3 f383 clz r3, r3
8001e6e: b2db uxtb r3, r3
8001e70: 095b lsrs r3, r3, #5
8001e72: b2db uxtb r3, r3
8001e74: f043 0301 orr.w r3, r3, #1
8001e78: b2db uxtb r3, r3
8001e7a: 2b01 cmp r3, #1
8001e7c: d102 bne.n 8001e84 <HAL_RCC_OscConfig+0x94>
8001e7e: 4ba8 ldr r3, [pc, #672] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001e80: 681b ldr r3, [r3, #0]
8001e82: e015 b.n 8001eb0 <HAL_RCC_OscConfig+0xc0>
8001e84: f44f 3300 mov.w r3, #131072 @ 0x20000
8001e88: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001e8c: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8
8001e90: fa93 f3a3 rbit r3, r3
8001e94: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4
8001e98: f44f 3300 mov.w r3, #131072 @ 0x20000
8001e9c: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0
8001ea0: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0
8001ea4: fa93 f3a3 rbit r3, r3
8001ea8: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc
8001eac: 4b9c ldr r3, [pc, #624] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001eae: 6a5b ldr r3, [r3, #36] @ 0x24
8001eb0: f44f 3200 mov.w r2, #131072 @ 0x20000
8001eb4: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8
8001eb8: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8
8001ebc: fa92 f2a2 rbit r2, r2
8001ec0: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4
return result;
8001ec4: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4
8001ec8: fab2 f282 clz r2, r2
8001ecc: b2d2 uxtb r2, r2
8001ece: f042 0220 orr.w r2, r2, #32
8001ed2: b2d2 uxtb r2, r2
8001ed4: f002 021f and.w r2, r2, #31
8001ed8: 2101 movs r1, #1
8001eda: fa01 f202 lsl.w r2, r1, r2
8001ede: 4013 ands r3, r2
8001ee0: 2b00 cmp r3, #0
8001ee2: f000 811f beq.w 8002124 <HAL_RCC_OscConfig+0x334>
8001ee6: f507 7300 add.w r3, r7, #512 @ 0x200
8001eea: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001eee: 681b ldr r3, [r3, #0]
8001ef0: 685b ldr r3, [r3, #4]
8001ef2: 2b00 cmp r3, #0
8001ef4: f040 8116 bne.w 8002124 <HAL_RCC_OscConfig+0x334>
{
return HAL_ERROR;
8001ef8: 2301 movs r3, #1
8001efa: f000 bfaf b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001efe: f507 7300 add.w r3, r7, #512 @ 0x200
8001f02: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001f06: 681b ldr r3, [r3, #0]
8001f08: 685b ldr r3, [r3, #4]
8001f0a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001f0e: d106 bne.n 8001f1e <HAL_RCC_OscConfig+0x12e>
8001f10: 4b83 ldr r3, [pc, #524] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f12: 681b ldr r3, [r3, #0]
8001f14: 4a82 ldr r2, [pc, #520] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f16: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001f1a: 6013 str r3, [r2, #0]
8001f1c: e036 b.n 8001f8c <HAL_RCC_OscConfig+0x19c>
8001f1e: f507 7300 add.w r3, r7, #512 @ 0x200
8001f22: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001f26: 681b ldr r3, [r3, #0]
8001f28: 685b ldr r3, [r3, #4]
8001f2a: 2b00 cmp r3, #0
8001f2c: d10c bne.n 8001f48 <HAL_RCC_OscConfig+0x158>
8001f2e: 4b7c ldr r3, [pc, #496] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f30: 681b ldr r3, [r3, #0]
8001f32: 4a7b ldr r2, [pc, #492] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f34: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001f38: 6013 str r3, [r2, #0]
8001f3a: 4b79 ldr r3, [pc, #484] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f3c: 681b ldr r3, [r3, #0]
8001f3e: 4a78 ldr r2, [pc, #480] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f40: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001f44: 6013 str r3, [r2, #0]
8001f46: e021 b.n 8001f8c <HAL_RCC_OscConfig+0x19c>
8001f48: f507 7300 add.w r3, r7, #512 @ 0x200
8001f4c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001f50: 681b ldr r3, [r3, #0]
8001f52: 685b ldr r3, [r3, #4]
8001f54: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8001f58: d10c bne.n 8001f74 <HAL_RCC_OscConfig+0x184>
8001f5a: 4b71 ldr r3, [pc, #452] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f5c: 681b ldr r3, [r3, #0]
8001f5e: 4a70 ldr r2, [pc, #448] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f60: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8001f64: 6013 str r3, [r2, #0]
8001f66: 4b6e ldr r3, [pc, #440] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f68: 681b ldr r3, [r3, #0]
8001f6a: 4a6d ldr r2, [pc, #436] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f6c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001f70: 6013 str r3, [r2, #0]
8001f72: e00b b.n 8001f8c <HAL_RCC_OscConfig+0x19c>
8001f74: 4b6a ldr r3, [pc, #424] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f76: 681b ldr r3, [r3, #0]
8001f78: 4a69 ldr r2, [pc, #420] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f7a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001f7e: 6013 str r3, [r2, #0]
8001f80: 4b67 ldr r3, [pc, #412] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f82: 681b ldr r3, [r3, #0]
8001f84: 4a66 ldr r2, [pc, #408] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f86: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001f8a: 6013 str r3, [r2, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
/* Configure the HSE predivision factor --------------------------------*/
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8001f8c: 4b64 ldr r3, [pc, #400] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001f8e: 6adb ldr r3, [r3, #44] @ 0x2c
8001f90: f023 020f bic.w r2, r3, #15
8001f94: f507 7300 add.w r3, r7, #512 @ 0x200
8001f98: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001f9c: 681b ldr r3, [r3, #0]
8001f9e: 689b ldr r3, [r3, #8]
8001fa0: 495f ldr r1, [pc, #380] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8001fa2: 4313 orrs r3, r2
8001fa4: 62cb str r3, [r1, #44] @ 0x2c
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001fa6: f507 7300 add.w r3, r7, #512 @ 0x200
8001faa: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001fae: 681b ldr r3, [r3, #0]
8001fb0: 685b ldr r3, [r3, #4]
8001fb2: 2b00 cmp r3, #0
8001fb4: d059 beq.n 800206a <HAL_RCC_OscConfig+0x27a>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001fb6: f7fe fd85 bl 8000ac4 <HAL_GetTick>
8001fba: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001fbe: e00a b.n 8001fd6 <HAL_RCC_OscConfig+0x1e6>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001fc0: f7fe fd80 bl 8000ac4 <HAL_GetTick>
8001fc4: 4602 mov r2, r0
8001fc6: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8001fca: 1ad3 subs r3, r2, r3
8001fcc: 2b64 cmp r3, #100 @ 0x64
8001fce: d902 bls.n 8001fd6 <HAL_RCC_OscConfig+0x1e6>
{
return HAL_TIMEOUT;
8001fd0: 2303 movs r3, #3
8001fd2: f000 bf43 b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
8001fd6: f44f 3300 mov.w r3, #131072 @ 0x20000
8001fda: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001fde: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0
8001fe2: fa93 f3a3 rbit r3, r3
8001fe6: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc
return result;
8001fea: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001fee: fab3 f383 clz r3, r3
8001ff2: b2db uxtb r3, r3
8001ff4: 095b lsrs r3, r3, #5
8001ff6: b2db uxtb r3, r3
8001ff8: f043 0301 orr.w r3, r3, #1
8001ffc: b2db uxtb r3, r3
8001ffe: 2b01 cmp r3, #1
8002000: d102 bne.n 8002008 <HAL_RCC_OscConfig+0x218>
8002002: 4b47 ldr r3, [pc, #284] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8002004: 681b ldr r3, [r3, #0]
8002006: e015 b.n 8002034 <HAL_RCC_OscConfig+0x244>
8002008: f44f 3300 mov.w r3, #131072 @ 0x20000
800200c: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002010: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8
8002014: fa93 f3a3 rbit r3, r3
8002018: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4
800201c: f44f 3300 mov.w r3, #131072 @ 0x20000
8002020: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0
8002024: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0
8002028: fa93 f3a3 rbit r3, r3
800202c: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc
8002030: 4b3b ldr r3, [pc, #236] @ (8002120 <HAL_RCC_OscConfig+0x330>)
8002032: 6a5b ldr r3, [r3, #36] @ 0x24
8002034: f44f 3200 mov.w r2, #131072 @ 0x20000
8002038: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8
800203c: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8
8002040: fa92 f2a2 rbit r2, r2
8002044: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4
return result;
8002048: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4
800204c: fab2 f282 clz r2, r2
8002050: b2d2 uxtb r2, r2
8002052: f042 0220 orr.w r2, r2, #32
8002056: b2d2 uxtb r2, r2
8002058: f002 021f and.w r2, r2, #31
800205c: 2101 movs r1, #1
800205e: fa01 f202 lsl.w r2, r1, r2
8002062: 4013 ands r3, r2
8002064: 2b00 cmp r3, #0
8002066: d0ab beq.n 8001fc0 <HAL_RCC_OscConfig+0x1d0>
8002068: e05d b.n 8002126 <HAL_RCC_OscConfig+0x336>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800206a: f7fe fd2b bl 8000ac4 <HAL_GetTick>
800206e: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002072: e00a b.n 800208a <HAL_RCC_OscConfig+0x29a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002074: f7fe fd26 bl 8000ac4 <HAL_GetTick>
8002078: 4602 mov r2, r0
800207a: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
800207e: 1ad3 subs r3, r2, r3
8002080: 2b64 cmp r3, #100 @ 0x64
8002082: d902 bls.n 800208a <HAL_RCC_OscConfig+0x29a>
{
return HAL_TIMEOUT;
8002084: 2303 movs r3, #3
8002086: f000 bee9 b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
800208a: f44f 3300 mov.w r3, #131072 @ 0x20000
800208e: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002092: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0
8002096: fa93 f3a3 rbit r3, r3
800209a: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac
return result;
800209e: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80020a2: fab3 f383 clz r3, r3
80020a6: b2db uxtb r3, r3
80020a8: 095b lsrs r3, r3, #5
80020aa: b2db uxtb r3, r3
80020ac: f043 0301 orr.w r3, r3, #1
80020b0: b2db uxtb r3, r3
80020b2: 2b01 cmp r3, #1
80020b4: d102 bne.n 80020bc <HAL_RCC_OscConfig+0x2cc>
80020b6: 4b1a ldr r3, [pc, #104] @ (8002120 <HAL_RCC_OscConfig+0x330>)
80020b8: 681b ldr r3, [r3, #0]
80020ba: e015 b.n 80020e8 <HAL_RCC_OscConfig+0x2f8>
80020bc: f44f 3300 mov.w r3, #131072 @ 0x20000
80020c0: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80020c4: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8
80020c8: fa93 f3a3 rbit r3, r3
80020cc: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4
80020d0: f44f 3300 mov.w r3, #131072 @ 0x20000
80020d4: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0
80020d8: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0
80020dc: fa93 f3a3 rbit r3, r3
80020e0: f8c7 319c str.w r3, [r7, #412] @ 0x19c
80020e4: 4b0e ldr r3, [pc, #56] @ (8002120 <HAL_RCC_OscConfig+0x330>)
80020e6: 6a5b ldr r3, [r3, #36] @ 0x24
80020e8: f44f 3200 mov.w r2, #131072 @ 0x20000
80020ec: f8c7 2198 str.w r2, [r7, #408] @ 0x198
80020f0: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198
80020f4: fa92 f2a2 rbit r2, r2
80020f8: f8c7 2194 str.w r2, [r7, #404] @ 0x194
return result;
80020fc: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194
8002100: fab2 f282 clz r2, r2
8002104: b2d2 uxtb r2, r2
8002106: f042 0220 orr.w r2, r2, #32
800210a: b2d2 uxtb r2, r2
800210c: f002 021f and.w r2, r2, #31
8002110: 2101 movs r1, #1
8002112: fa01 f202 lsl.w r2, r1, r2
8002116: 4013 ands r3, r2
8002118: 2b00 cmp r3, #0
800211a: d1ab bne.n 8002074 <HAL_RCC_OscConfig+0x284>
800211c: e003 b.n 8002126 <HAL_RCC_OscConfig+0x336>
800211e: bf00 nop
8002120: 40021000 .word 0x40021000
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002124: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002126: f507 7300 add.w r3, r7, #512 @ 0x200
800212a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800212e: 681b ldr r3, [r3, #0]
8002130: 681b ldr r3, [r3, #0]
8002132: f003 0302 and.w r3, r3, #2
8002136: 2b00 cmp r3, #0
8002138: f000 817d beq.w 8002436 <HAL_RCC_OscConfig+0x646>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
800213c: 4ba6 ldr r3, [pc, #664] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
800213e: 685b ldr r3, [r3, #4]
8002140: f003 030c and.w r3, r3, #12
8002144: 2b00 cmp r3, #0
8002146: d00b beq.n 8002160 <HAL_RCC_OscConfig+0x370>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8002148: 4ba3 ldr r3, [pc, #652] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
800214a: 685b ldr r3, [r3, #4]
800214c: f003 030c and.w r3, r3, #12
8002150: 2b08 cmp r3, #8
8002152: d172 bne.n 800223a <HAL_RCC_OscConfig+0x44a>
8002154: 4ba0 ldr r3, [pc, #640] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
8002156: 685b ldr r3, [r3, #4]
8002158: f403 3380 and.w r3, r3, #65536 @ 0x10000
800215c: 2b00 cmp r3, #0
800215e: d16c bne.n 800223a <HAL_RCC_OscConfig+0x44a>
8002160: 2302 movs r3, #2
8002162: f8c7 3190 str.w r3, [r7, #400] @ 0x190
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002166: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190
800216a: fa93 f3a3 rbit r3, r3
800216e: f8c7 318c str.w r3, [r7, #396] @ 0x18c
return result;
8002172: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002176: fab3 f383 clz r3, r3
800217a: b2db uxtb r3, r3
800217c: 095b lsrs r3, r3, #5
800217e: b2db uxtb r3, r3
8002180: f043 0301 orr.w r3, r3, #1
8002184: b2db uxtb r3, r3
8002186: 2b01 cmp r3, #1
8002188: d102 bne.n 8002190 <HAL_RCC_OscConfig+0x3a0>
800218a: 4b93 ldr r3, [pc, #588] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
800218c: 681b ldr r3, [r3, #0]
800218e: e013 b.n 80021b8 <HAL_RCC_OscConfig+0x3c8>
8002190: 2302 movs r3, #2
8002192: f8c7 3188 str.w r3, [r7, #392] @ 0x188
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002196: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188
800219a: fa93 f3a3 rbit r3, r3
800219e: f8c7 3184 str.w r3, [r7, #388] @ 0x184
80021a2: 2302 movs r3, #2
80021a4: f8c7 3180 str.w r3, [r7, #384] @ 0x180
80021a8: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180
80021ac: fa93 f3a3 rbit r3, r3
80021b0: f8c7 317c str.w r3, [r7, #380] @ 0x17c
80021b4: 4b88 ldr r3, [pc, #544] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
80021b6: 6a5b ldr r3, [r3, #36] @ 0x24
80021b8: 2202 movs r2, #2
80021ba: f8c7 2178 str.w r2, [r7, #376] @ 0x178
80021be: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178
80021c2: fa92 f2a2 rbit r2, r2
80021c6: f8c7 2174 str.w r2, [r7, #372] @ 0x174
return result;
80021ca: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174
80021ce: fab2 f282 clz r2, r2
80021d2: b2d2 uxtb r2, r2
80021d4: f042 0220 orr.w r2, r2, #32
80021d8: b2d2 uxtb r2, r2
80021da: f002 021f and.w r2, r2, #31
80021de: 2101 movs r1, #1
80021e0: fa01 f202 lsl.w r2, r1, r2
80021e4: 4013 ands r3, r2
80021e6: 2b00 cmp r3, #0
80021e8: d00a beq.n 8002200 <HAL_RCC_OscConfig+0x410>
80021ea: f507 7300 add.w r3, r7, #512 @ 0x200
80021ee: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80021f2: 681b ldr r3, [r3, #0]
80021f4: 691b ldr r3, [r3, #16]
80021f6: 2b01 cmp r3, #1
80021f8: d002 beq.n 8002200 <HAL_RCC_OscConfig+0x410>
{
return HAL_ERROR;
80021fa: 2301 movs r3, #1
80021fc: f000 be2e b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002200: 4b75 ldr r3, [pc, #468] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
8002202: 681b ldr r3, [r3, #0]
8002204: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8002208: f507 7300 add.w r3, r7, #512 @ 0x200
800220c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002210: 681b ldr r3, [r3, #0]
8002212: 695b ldr r3, [r3, #20]
8002214: 21f8 movs r1, #248 @ 0xf8
8002216: f8c7 1170 str.w r1, [r7, #368] @ 0x170
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800221a: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170
800221e: fa91 f1a1 rbit r1, r1
8002222: f8c7 116c str.w r1, [r7, #364] @ 0x16c
return result;
8002226: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c
800222a: fab1 f181 clz r1, r1
800222e: b2c9 uxtb r1, r1
8002230: 408b lsls r3, r1
8002232: 4969 ldr r1, [pc, #420] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
8002234: 4313 orrs r3, r2
8002236: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002238: e0fd b.n 8002436 <HAL_RCC_OscConfig+0x646>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800223a: f507 7300 add.w r3, r7, #512 @ 0x200
800223e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002242: 681b ldr r3, [r3, #0]
8002244: 691b ldr r3, [r3, #16]
8002246: 2b00 cmp r3, #0
8002248: f000 8088 beq.w 800235c <HAL_RCC_OscConfig+0x56c>
800224c: 2301 movs r3, #1
800224e: f8c7 3168 str.w r3, [r7, #360] @ 0x168
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002252: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168
8002256: fa93 f3a3 rbit r3, r3
800225a: f8c7 3164 str.w r3, [r7, #356] @ 0x164
return result;
800225e: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002262: fab3 f383 clz r3, r3
8002266: b2db uxtb r3, r3
8002268: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
800226c: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002270: 009b lsls r3, r3, #2
8002272: 461a mov r2, r3
8002274: 2301 movs r3, #1
8002276: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002278: f7fe fc24 bl 8000ac4 <HAL_GetTick>
800227c: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002280: e00a b.n 8002298 <HAL_RCC_OscConfig+0x4a8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002282: f7fe fc1f bl 8000ac4 <HAL_GetTick>
8002286: 4602 mov r2, r0
8002288: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
800228c: 1ad3 subs r3, r2, r3
800228e: 2b02 cmp r3, #2
8002290: d902 bls.n 8002298 <HAL_RCC_OscConfig+0x4a8>
{
return HAL_TIMEOUT;
8002292: 2303 movs r3, #3
8002294: f000 bde2 b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
8002298: 2302 movs r3, #2
800229a: f8c7 3160 str.w r3, [r7, #352] @ 0x160
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800229e: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160
80022a2: fa93 f3a3 rbit r3, r3
80022a6: f8c7 315c str.w r3, [r7, #348] @ 0x15c
return result;
80022aa: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80022ae: fab3 f383 clz r3, r3
80022b2: b2db uxtb r3, r3
80022b4: 095b lsrs r3, r3, #5
80022b6: b2db uxtb r3, r3
80022b8: f043 0301 orr.w r3, r3, #1
80022bc: b2db uxtb r3, r3
80022be: 2b01 cmp r3, #1
80022c0: d102 bne.n 80022c8 <HAL_RCC_OscConfig+0x4d8>
80022c2: 4b45 ldr r3, [pc, #276] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
80022c4: 681b ldr r3, [r3, #0]
80022c6: e013 b.n 80022f0 <HAL_RCC_OscConfig+0x500>
80022c8: 2302 movs r3, #2
80022ca: f8c7 3158 str.w r3, [r7, #344] @ 0x158
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80022ce: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158
80022d2: fa93 f3a3 rbit r3, r3
80022d6: f8c7 3154 str.w r3, [r7, #340] @ 0x154
80022da: 2302 movs r3, #2
80022dc: f8c7 3150 str.w r3, [r7, #336] @ 0x150
80022e0: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150
80022e4: fa93 f3a3 rbit r3, r3
80022e8: f8c7 314c str.w r3, [r7, #332] @ 0x14c
80022ec: 4b3a ldr r3, [pc, #232] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
80022ee: 6a5b ldr r3, [r3, #36] @ 0x24
80022f0: 2202 movs r2, #2
80022f2: f8c7 2148 str.w r2, [r7, #328] @ 0x148
80022f6: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148
80022fa: fa92 f2a2 rbit r2, r2
80022fe: f8c7 2144 str.w r2, [r7, #324] @ 0x144
return result;
8002302: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144
8002306: fab2 f282 clz r2, r2
800230a: b2d2 uxtb r2, r2
800230c: f042 0220 orr.w r2, r2, #32
8002310: b2d2 uxtb r2, r2
8002312: f002 021f and.w r2, r2, #31
8002316: 2101 movs r1, #1
8002318: fa01 f202 lsl.w r2, r1, r2
800231c: 4013 ands r3, r2
800231e: 2b00 cmp r3, #0
8002320: d0af beq.n 8002282 <HAL_RCC_OscConfig+0x492>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002322: 4b2d ldr r3, [pc, #180] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
8002324: 681b ldr r3, [r3, #0]
8002326: f023 02f8 bic.w r2, r3, #248 @ 0xf8
800232a: f507 7300 add.w r3, r7, #512 @ 0x200
800232e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002332: 681b ldr r3, [r3, #0]
8002334: 695b ldr r3, [r3, #20]
8002336: 21f8 movs r1, #248 @ 0xf8
8002338: f8c7 1140 str.w r1, [r7, #320] @ 0x140
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800233c: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140
8002340: fa91 f1a1 rbit r1, r1
8002344: f8c7 113c str.w r1, [r7, #316] @ 0x13c
return result;
8002348: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c
800234c: fab1 f181 clz r1, r1
8002350: b2c9 uxtb r1, r1
8002352: 408b lsls r3, r1
8002354: 4920 ldr r1, [pc, #128] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
8002356: 4313 orrs r3, r2
8002358: 600b str r3, [r1, #0]
800235a: e06c b.n 8002436 <HAL_RCC_OscConfig+0x646>
800235c: 2301 movs r3, #1
800235e: f8c7 3138 str.w r3, [r7, #312] @ 0x138
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002362: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138
8002366: fa93 f3a3 rbit r3, r3
800236a: f8c7 3134 str.w r3, [r7, #308] @ 0x134
return result;
800236e: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8002372: fab3 f383 clz r3, r3
8002376: b2db uxtb r3, r3
8002378: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
800237c: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002380: 009b lsls r3, r3, #2
8002382: 461a mov r2, r3
8002384: 2300 movs r3, #0
8002386: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002388: f7fe fb9c bl 8000ac4 <HAL_GetTick>
800238c: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002390: e00a b.n 80023a8 <HAL_RCC_OscConfig+0x5b8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002392: f7fe fb97 bl 8000ac4 <HAL_GetTick>
8002396: 4602 mov r2, r0
8002398: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
800239c: 1ad3 subs r3, r2, r3
800239e: 2b02 cmp r3, #2
80023a0: d902 bls.n 80023a8 <HAL_RCC_OscConfig+0x5b8>
{
return HAL_TIMEOUT;
80023a2: 2303 movs r3, #3
80023a4: f000 bd5a b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
80023a8: 2302 movs r3, #2
80023aa: f8c7 3130 str.w r3, [r7, #304] @ 0x130
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80023ae: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130
80023b2: fa93 f3a3 rbit r3, r3
80023b6: f8c7 312c str.w r3, [r7, #300] @ 0x12c
return result;
80023ba: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80023be: fab3 f383 clz r3, r3
80023c2: b2db uxtb r3, r3
80023c4: 095b lsrs r3, r3, #5
80023c6: b2db uxtb r3, r3
80023c8: f043 0301 orr.w r3, r3, #1
80023cc: b2db uxtb r3, r3
80023ce: 2b01 cmp r3, #1
80023d0: d104 bne.n 80023dc <HAL_RCC_OscConfig+0x5ec>
80023d2: 4b01 ldr r3, [pc, #4] @ (80023d8 <HAL_RCC_OscConfig+0x5e8>)
80023d4: 681b ldr r3, [r3, #0]
80023d6: e015 b.n 8002404 <HAL_RCC_OscConfig+0x614>
80023d8: 40021000 .word 0x40021000
80023dc: 2302 movs r3, #2
80023de: f8c7 3128 str.w r3, [r7, #296] @ 0x128
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80023e2: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128
80023e6: fa93 f3a3 rbit r3, r3
80023ea: f8c7 3124 str.w r3, [r7, #292] @ 0x124
80023ee: 2302 movs r3, #2
80023f0: f8c7 3120 str.w r3, [r7, #288] @ 0x120
80023f4: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120
80023f8: fa93 f3a3 rbit r3, r3
80023fc: f8c7 311c str.w r3, [r7, #284] @ 0x11c
8002400: 4bc8 ldr r3, [pc, #800] @ (8002724 <HAL_RCC_OscConfig+0x934>)
8002402: 6a5b ldr r3, [r3, #36] @ 0x24
8002404: 2202 movs r2, #2
8002406: f8c7 2118 str.w r2, [r7, #280] @ 0x118
800240a: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118
800240e: fa92 f2a2 rbit r2, r2
8002412: f8c7 2114 str.w r2, [r7, #276] @ 0x114
return result;
8002416: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114
800241a: fab2 f282 clz r2, r2
800241e: b2d2 uxtb r2, r2
8002420: f042 0220 orr.w r2, r2, #32
8002424: b2d2 uxtb r2, r2
8002426: f002 021f and.w r2, r2, #31
800242a: 2101 movs r1, #1
800242c: fa01 f202 lsl.w r2, r1, r2
8002430: 4013 ands r3, r2
8002432: 2b00 cmp r3, #0
8002434: d1ad bne.n 8002392 <HAL_RCC_OscConfig+0x5a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8002436: f507 7300 add.w r3, r7, #512 @ 0x200
800243a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800243e: 681b ldr r3, [r3, #0]
8002440: 681b ldr r3, [r3, #0]
8002442: f003 0308 and.w r3, r3, #8
8002446: 2b00 cmp r3, #0
8002448: f000 8110 beq.w 800266c <HAL_RCC_OscConfig+0x87c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
800244c: f507 7300 add.w r3, r7, #512 @ 0x200
8002450: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002454: 681b ldr r3, [r3, #0]
8002456: 699b ldr r3, [r3, #24]
8002458: 2b00 cmp r3, #0
800245a: d079 beq.n 8002550 <HAL_RCC_OscConfig+0x760>
800245c: 2301 movs r3, #1
800245e: f8c7 3110 str.w r3, [r7, #272] @ 0x110
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002462: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110
8002466: fa93 f3a3 rbit r3, r3
800246a: f8c7 310c str.w r3, [r7, #268] @ 0x10c
return result;
800246e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8002472: fab3 f383 clz r3, r3
8002476: b2db uxtb r3, r3
8002478: 461a mov r2, r3
800247a: 4bab ldr r3, [pc, #684] @ (8002728 <HAL_RCC_OscConfig+0x938>)
800247c: 4413 add r3, r2
800247e: 009b lsls r3, r3, #2
8002480: 461a mov r2, r3
8002482: 2301 movs r3, #1
8002484: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002486: f7fe fb1d bl 8000ac4 <HAL_GetTick>
800248a: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800248e: e00a b.n 80024a6 <HAL_RCC_OscConfig+0x6b6>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002490: f7fe fb18 bl 8000ac4 <HAL_GetTick>
8002494: 4602 mov r2, r0
8002496: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
800249a: 1ad3 subs r3, r2, r3
800249c: 2b02 cmp r3, #2
800249e: d902 bls.n 80024a6 <HAL_RCC_OscConfig+0x6b6>
{
return HAL_TIMEOUT;
80024a0: 2303 movs r3, #3
80024a2: f000 bcdb b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
80024a6: 2302 movs r3, #2
80024a8: f8c7 3108 str.w r3, [r7, #264] @ 0x108
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80024ac: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108
80024b0: fa93 f3a3 rbit r3, r3
80024b4: f8c7 3104 str.w r3, [r7, #260] @ 0x104
80024b8: f507 7300 add.w r3, r7, #512 @ 0x200
80024bc: f5a3 7380 sub.w r3, r3, #256 @ 0x100
80024c0: 2202 movs r2, #2
80024c2: 601a str r2, [r3, #0]
80024c4: f507 7300 add.w r3, r7, #512 @ 0x200
80024c8: f5a3 7380 sub.w r3, r3, #256 @ 0x100
80024cc: 681b ldr r3, [r3, #0]
80024ce: fa93 f2a3 rbit r2, r3
80024d2: f507 7300 add.w r3, r7, #512 @ 0x200
80024d6: f5a3 7382 sub.w r3, r3, #260 @ 0x104
80024da: 601a str r2, [r3, #0]
80024dc: f507 7300 add.w r3, r7, #512 @ 0x200
80024e0: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80024e4: 2202 movs r2, #2
80024e6: 601a str r2, [r3, #0]
80024e8: f507 7300 add.w r3, r7, #512 @ 0x200
80024ec: f5a3 7384 sub.w r3, r3, #264 @ 0x108
80024f0: 681b ldr r3, [r3, #0]
80024f2: fa93 f2a3 rbit r2, r3
80024f6: f507 7300 add.w r3, r7, #512 @ 0x200
80024fa: f5a3 7386 sub.w r3, r3, #268 @ 0x10c
80024fe: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002500: 4b88 ldr r3, [pc, #544] @ (8002724 <HAL_RCC_OscConfig+0x934>)
8002502: 6a5a ldr r2, [r3, #36] @ 0x24
8002504: f507 7300 add.w r3, r7, #512 @ 0x200
8002508: f5a3 7388 sub.w r3, r3, #272 @ 0x110
800250c: 2102 movs r1, #2
800250e: 6019 str r1, [r3, #0]
8002510: f507 7300 add.w r3, r7, #512 @ 0x200
8002514: f5a3 7388 sub.w r3, r3, #272 @ 0x110
8002518: 681b ldr r3, [r3, #0]
800251a: fa93 f1a3 rbit r1, r3
800251e: f507 7300 add.w r3, r7, #512 @ 0x200
8002522: f5a3 738a sub.w r3, r3, #276 @ 0x114
8002526: 6019 str r1, [r3, #0]
return result;
8002528: f507 7300 add.w r3, r7, #512 @ 0x200
800252c: f5a3 738a sub.w r3, r3, #276 @ 0x114
8002530: 681b ldr r3, [r3, #0]
8002532: fab3 f383 clz r3, r3
8002536: b2db uxtb r3, r3
8002538: f043 0360 orr.w r3, r3, #96 @ 0x60
800253c: b2db uxtb r3, r3
800253e: f003 031f and.w r3, r3, #31
8002542: 2101 movs r1, #1
8002544: fa01 f303 lsl.w r3, r1, r3
8002548: 4013 ands r3, r2
800254a: 2b00 cmp r3, #0
800254c: d0a0 beq.n 8002490 <HAL_RCC_OscConfig+0x6a0>
800254e: e08d b.n 800266c <HAL_RCC_OscConfig+0x87c>
8002550: f507 7300 add.w r3, r7, #512 @ 0x200
8002554: f5a3 738c sub.w r3, r3, #280 @ 0x118
8002558: 2201 movs r2, #1
800255a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800255c: f507 7300 add.w r3, r7, #512 @ 0x200
8002560: f5a3 738c sub.w r3, r3, #280 @ 0x118
8002564: 681b ldr r3, [r3, #0]
8002566: fa93 f2a3 rbit r2, r3
800256a: f507 7300 add.w r3, r7, #512 @ 0x200
800256e: f5a3 738e sub.w r3, r3, #284 @ 0x11c
8002572: 601a str r2, [r3, #0]
return result;
8002574: f507 7300 add.w r3, r7, #512 @ 0x200
8002578: f5a3 738e sub.w r3, r3, #284 @ 0x11c
800257c: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
800257e: fab3 f383 clz r3, r3
8002582: b2db uxtb r3, r3
8002584: 461a mov r2, r3
8002586: 4b68 ldr r3, [pc, #416] @ (8002728 <HAL_RCC_OscConfig+0x938>)
8002588: 4413 add r3, r2
800258a: 009b lsls r3, r3, #2
800258c: 461a mov r2, r3
800258e: 2300 movs r3, #0
8002590: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002592: f7fe fa97 bl 8000ac4 <HAL_GetTick>
8002596: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800259a: e00a b.n 80025b2 <HAL_RCC_OscConfig+0x7c2>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800259c: f7fe fa92 bl 8000ac4 <HAL_GetTick>
80025a0: 4602 mov r2, r0
80025a2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80025a6: 1ad3 subs r3, r2, r3
80025a8: 2b02 cmp r3, #2
80025aa: d902 bls.n 80025b2 <HAL_RCC_OscConfig+0x7c2>
{
return HAL_TIMEOUT;
80025ac: 2303 movs r3, #3
80025ae: f000 bc55 b.w 8002e5c <HAL_RCC_OscConfig+0x106c>
80025b2: f507 7300 add.w r3, r7, #512 @ 0x200
80025b6: f5a3 7390 sub.w r3, r3, #288 @ 0x120
80025ba: 2202 movs r2, #2
80025bc: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80025be: f507 7300 add.w r3, r7, #512 @ 0x200
80025c2: f5a3 7390 sub.w r3, r3, #288 @ 0x120
80025c6: 681b ldr r3, [r3, #0]
80025c8: fa93 f2a3 rbit r2, r3
80025cc: f507 7300 add.w r3, r7, #512 @ 0x200
80025d0: f5a3 7392 sub.w r3, r3, #292 @ 0x124
80025d4: 601a str r2, [r3, #0]
80025d6: f507 7300 add.w r3, r7, #512 @ 0x200
80025da: f5a3 7394 sub.w r3, r3, #296 @ 0x128
80025de: 2202 movs r2, #2
80025e0: 601a str r2, [r3, #0]
80025e2: f507 7300 add.w r3, r7, #512 @ 0x200
80025e6: f5a3 7394 sub.w r3, r3, #296 @ 0x128
80025ea: 681b ldr r3, [r3, #0]
80025ec: fa93 f2a3 rbit r2, r3
80025f0: f507 7300 add.w r3, r7, #512 @ 0x200
80025f4: f5a3 7396 sub.w r3, r3, #300 @ 0x12c
80025f8: 601a str r2, [r3, #0]
80025fa: f507 7300 add.w r3, r7, #512 @ 0x200
80025fe: f5a3 7398 sub.w r3, r3, #304 @ 0x130
8002602: 2202 movs r2, #2
8002604: 601a str r2, [r3, #0]
8002606: f507 7300 add.w r3, r7, #512 @ 0x200
800260a: f5a3 7398 sub.w r3, r3, #304 @ 0x130
800260e: 681b ldr r3, [r3, #0]
8002610: fa93 f2a3 rbit r2, r3
8002614: f507 7300 add.w r3, r7, #512 @ 0x200
8002618: f5a3 739a sub.w r3, r3, #308 @ 0x134
800261c: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800261e: 4b41 ldr r3, [pc, #260] @ (8002724 <HAL_RCC_OscConfig+0x934>)
8002620: 6a5a ldr r2, [r3, #36] @ 0x24
8002622: f507 7300 add.w r3, r7, #512 @ 0x200
8002626: f5a3 739c sub.w r3, r3, #312 @ 0x138
800262a: 2102 movs r1, #2
800262c: 6019 str r1, [r3, #0]
800262e: f507 7300 add.w r3, r7, #512 @ 0x200
8002632: f5a3 739c sub.w r3, r3, #312 @ 0x138
8002636: 681b ldr r3, [r3, #0]
8002638: fa93 f1a3 rbit r1, r3
800263c: f507 7300 add.w r3, r7, #512 @ 0x200
8002640: f5a3 739e sub.w r3, r3, #316 @ 0x13c
8002644: 6019 str r1, [r3, #0]
return result;
8002646: f507 7300 add.w r3, r7, #512 @ 0x200
800264a: f5a3 739e sub.w r3, r3, #316 @ 0x13c
800264e: 681b ldr r3, [r3, #0]
8002650: fab3 f383 clz r3, r3
8002654: b2db uxtb r3, r3
8002656: f043 0360 orr.w r3, r3, #96 @ 0x60
800265a: b2db uxtb r3, r3
800265c: f003 031f and.w r3, r3, #31
8002660: 2101 movs r1, #1
8002662: fa01 f303 lsl.w r3, r1, r3
8002666: 4013 ands r3, r2
8002668: 2b00 cmp r3, #0
800266a: d197 bne.n 800259c <HAL_RCC_OscConfig+0x7ac>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800266c: f507 7300 add.w r3, r7, #512 @ 0x200
8002670: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002674: 681b ldr r3, [r3, #0]
8002676: 681b ldr r3, [r3, #0]
8002678: f003 0304 and.w r3, r3, #4
800267c: 2b00 cmp r3, #0
800267e: f000 81a1 beq.w 80029c4 <HAL_RCC_OscConfig+0xbd4>
{
FlagStatus pwrclkchanged = RESET;
8002682: 2300 movs r3, #0
8002684: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8002688: 4b26 ldr r3, [pc, #152] @ (8002724 <HAL_RCC_OscConfig+0x934>)
800268a: 69db ldr r3, [r3, #28]
800268c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002690: 2b00 cmp r3, #0
8002692: d116 bne.n 80026c2 <HAL_RCC_OscConfig+0x8d2>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002694: 4b23 ldr r3, [pc, #140] @ (8002724 <HAL_RCC_OscConfig+0x934>)
8002696: 69db ldr r3, [r3, #28]
8002698: 4a22 ldr r2, [pc, #136] @ (8002724 <HAL_RCC_OscConfig+0x934>)
800269a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800269e: 61d3 str r3, [r2, #28]
80026a0: 4b20 ldr r3, [pc, #128] @ (8002724 <HAL_RCC_OscConfig+0x934>)
80026a2: 69db ldr r3, [r3, #28]
80026a4: f003 5280 and.w r2, r3, #268435456 @ 0x10000000
80026a8: f507 7300 add.w r3, r7, #512 @ 0x200
80026ac: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
80026b0: 601a str r2, [r3, #0]
80026b2: f507 7300 add.w r3, r7, #512 @ 0x200
80026b6: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
80026ba: 681b ldr r3, [r3, #0]
pwrclkchanged = SET;
80026bc: 2301 movs r3, #1
80026be: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80026c2: 4b1a ldr r3, [pc, #104] @ (800272c <HAL_RCC_OscConfig+0x93c>)
80026c4: 681b ldr r3, [r3, #0]
80026c6: f403 7380 and.w r3, r3, #256 @ 0x100
80026ca: 2b00 cmp r3, #0
80026cc: d11a bne.n 8002704 <HAL_RCC_OscConfig+0x914>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80026ce: 4b17 ldr r3, [pc, #92] @ (800272c <HAL_RCC_OscConfig+0x93c>)
80026d0: 681b ldr r3, [r3, #0]
80026d2: 4a16 ldr r2, [pc, #88] @ (800272c <HAL_RCC_OscConfig+0x93c>)
80026d4: f443 7380 orr.w r3, r3, #256 @ 0x100
80026d8: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80026da: f7fe f9f3 bl 8000ac4 <HAL_GetTick>
80026de: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80026e2: e009 b.n 80026f8 <HAL_RCC_OscConfig+0x908>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80026e4: f7fe f9ee bl 8000ac4 <HAL_GetTick>
80026e8: 4602 mov r2, r0
80026ea: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80026ee: 1ad3 subs r3, r2, r3
80026f0: 2b64 cmp r3, #100 @ 0x64
80026f2: d901 bls.n 80026f8 <HAL_RCC_OscConfig+0x908>
{
return HAL_TIMEOUT;
80026f4: 2303 movs r3, #3
80026f6: e3b1 b.n 8002e5c <HAL_RCC_OscConfig+0x106c>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80026f8: 4b0c ldr r3, [pc, #48] @ (800272c <HAL_RCC_OscConfig+0x93c>)
80026fa: 681b ldr r3, [r3, #0]
80026fc: f403 7380 and.w r3, r3, #256 @ 0x100
8002700: 2b00 cmp r3, #0
8002702: d0ef beq.n 80026e4 <HAL_RCC_OscConfig+0x8f4>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002704: f507 7300 add.w r3, r7, #512 @ 0x200
8002708: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800270c: 681b ldr r3, [r3, #0]
800270e: 68db ldr r3, [r3, #12]
8002710: 2b01 cmp r3, #1
8002712: d10d bne.n 8002730 <HAL_RCC_OscConfig+0x940>
8002714: 4b03 ldr r3, [pc, #12] @ (8002724 <HAL_RCC_OscConfig+0x934>)
8002716: 6a1b ldr r3, [r3, #32]
8002718: 4a02 ldr r2, [pc, #8] @ (8002724 <HAL_RCC_OscConfig+0x934>)
800271a: f043 0301 orr.w r3, r3, #1
800271e: 6213 str r3, [r2, #32]
8002720: e03c b.n 800279c <HAL_RCC_OscConfig+0x9ac>
8002722: bf00 nop
8002724: 40021000 .word 0x40021000
8002728: 10908120 .word 0x10908120
800272c: 40007000 .word 0x40007000
8002730: f507 7300 add.w r3, r7, #512 @ 0x200
8002734: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002738: 681b ldr r3, [r3, #0]
800273a: 68db ldr r3, [r3, #12]
800273c: 2b00 cmp r3, #0
800273e: d10c bne.n 800275a <HAL_RCC_OscConfig+0x96a>
8002740: 4bc1 ldr r3, [pc, #772] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002742: 6a1b ldr r3, [r3, #32]
8002744: 4ac0 ldr r2, [pc, #768] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002746: f023 0301 bic.w r3, r3, #1
800274a: 6213 str r3, [r2, #32]
800274c: 4bbe ldr r3, [pc, #760] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
800274e: 6a1b ldr r3, [r3, #32]
8002750: 4abd ldr r2, [pc, #756] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002752: f023 0304 bic.w r3, r3, #4
8002756: 6213 str r3, [r2, #32]
8002758: e020 b.n 800279c <HAL_RCC_OscConfig+0x9ac>
800275a: f507 7300 add.w r3, r7, #512 @ 0x200
800275e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002762: 681b ldr r3, [r3, #0]
8002764: 68db ldr r3, [r3, #12]
8002766: 2b05 cmp r3, #5
8002768: d10c bne.n 8002784 <HAL_RCC_OscConfig+0x994>
800276a: 4bb7 ldr r3, [pc, #732] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
800276c: 6a1b ldr r3, [r3, #32]
800276e: 4ab6 ldr r2, [pc, #728] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002770: f043 0304 orr.w r3, r3, #4
8002774: 6213 str r3, [r2, #32]
8002776: 4bb4 ldr r3, [pc, #720] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002778: 6a1b ldr r3, [r3, #32]
800277a: 4ab3 ldr r2, [pc, #716] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
800277c: f043 0301 orr.w r3, r3, #1
8002780: 6213 str r3, [r2, #32]
8002782: e00b b.n 800279c <HAL_RCC_OscConfig+0x9ac>
8002784: 4bb0 ldr r3, [pc, #704] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002786: 6a1b ldr r3, [r3, #32]
8002788: 4aaf ldr r2, [pc, #700] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
800278a: f023 0301 bic.w r3, r3, #1
800278e: 6213 str r3, [r2, #32]
8002790: 4bad ldr r3, [pc, #692] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002792: 6a1b ldr r3, [r3, #32]
8002794: 4aac ldr r2, [pc, #688] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002796: f023 0304 bic.w r3, r3, #4
800279a: 6213 str r3, [r2, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
800279c: f507 7300 add.w r3, r7, #512 @ 0x200
80027a0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80027a4: 681b ldr r3, [r3, #0]
80027a6: 68db ldr r3, [r3, #12]
80027a8: 2b00 cmp r3, #0
80027aa: f000 8081 beq.w 80028b0 <HAL_RCC_OscConfig+0xac0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80027ae: f7fe f989 bl 8000ac4 <HAL_GetTick>
80027b2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80027b6: e00b b.n 80027d0 <HAL_RCC_OscConfig+0x9e0>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80027b8: f7fe f984 bl 8000ac4 <HAL_GetTick>
80027bc: 4602 mov r2, r0
80027be: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80027c2: 1ad3 subs r3, r2, r3
80027c4: f241 3288 movw r2, #5000 @ 0x1388
80027c8: 4293 cmp r3, r2
80027ca: d901 bls.n 80027d0 <HAL_RCC_OscConfig+0x9e0>
{
return HAL_TIMEOUT;
80027cc: 2303 movs r3, #3
80027ce: e345 b.n 8002e5c <HAL_RCC_OscConfig+0x106c>
80027d0: f507 7300 add.w r3, r7, #512 @ 0x200
80027d4: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
80027d8: 2202 movs r2, #2
80027da: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80027dc: f507 7300 add.w r3, r7, #512 @ 0x200
80027e0: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
80027e4: 681b ldr r3, [r3, #0]
80027e6: fa93 f2a3 rbit r2, r3
80027ea: f507 7300 add.w r3, r7, #512 @ 0x200
80027ee: f5a3 73a2 sub.w r3, r3, #324 @ 0x144
80027f2: 601a str r2, [r3, #0]
80027f4: f507 7300 add.w r3, r7, #512 @ 0x200
80027f8: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
80027fc: 2202 movs r2, #2
80027fe: 601a str r2, [r3, #0]
8002800: f507 7300 add.w r3, r7, #512 @ 0x200
8002804: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
8002808: 681b ldr r3, [r3, #0]
800280a: fa93 f2a3 rbit r2, r3
800280e: f507 7300 add.w r3, r7, #512 @ 0x200
8002812: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
8002816: 601a str r2, [r3, #0]
return result;
8002818: f507 7300 add.w r3, r7, #512 @ 0x200
800281c: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
8002820: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002822: fab3 f383 clz r3, r3
8002826: b2db uxtb r3, r3
8002828: 095b lsrs r3, r3, #5
800282a: b2db uxtb r3, r3
800282c: f043 0302 orr.w r3, r3, #2
8002830: b2db uxtb r3, r3
8002832: 2b02 cmp r3, #2
8002834: d102 bne.n 800283c <HAL_RCC_OscConfig+0xa4c>
8002836: 4b84 ldr r3, [pc, #528] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002838: 6a1b ldr r3, [r3, #32]
800283a: e013 b.n 8002864 <HAL_RCC_OscConfig+0xa74>
800283c: f507 7300 add.w r3, r7, #512 @ 0x200
8002840: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
8002844: 2202 movs r2, #2
8002846: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002848: f507 7300 add.w r3, r7, #512 @ 0x200
800284c: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
8002850: 681b ldr r3, [r3, #0]
8002852: fa93 f2a3 rbit r2, r3
8002856: f507 7300 add.w r3, r7, #512 @ 0x200
800285a: f5a3 73aa sub.w r3, r3, #340 @ 0x154
800285e: 601a str r2, [r3, #0]
8002860: 4b79 ldr r3, [pc, #484] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002862: 6a5b ldr r3, [r3, #36] @ 0x24
8002864: f507 7200 add.w r2, r7, #512 @ 0x200
8002868: f5a2 72ac sub.w r2, r2, #344 @ 0x158
800286c: 2102 movs r1, #2
800286e: 6011 str r1, [r2, #0]
8002870: f507 7200 add.w r2, r7, #512 @ 0x200
8002874: f5a2 72ac sub.w r2, r2, #344 @ 0x158
8002878: 6812 ldr r2, [r2, #0]
800287a: fa92 f1a2 rbit r1, r2
800287e: f507 7200 add.w r2, r7, #512 @ 0x200
8002882: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
8002886: 6011 str r1, [r2, #0]
return result;
8002888: f507 7200 add.w r2, r7, #512 @ 0x200
800288c: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
8002890: 6812 ldr r2, [r2, #0]
8002892: fab2 f282 clz r2, r2
8002896: b2d2 uxtb r2, r2
8002898: f042 0240 orr.w r2, r2, #64 @ 0x40
800289c: b2d2 uxtb r2, r2
800289e: f002 021f and.w r2, r2, #31
80028a2: 2101 movs r1, #1
80028a4: fa01 f202 lsl.w r2, r1, r2
80028a8: 4013 ands r3, r2
80028aa: 2b00 cmp r3, #0
80028ac: d084 beq.n 80027b8 <HAL_RCC_OscConfig+0x9c8>
80028ae: e07f b.n 80029b0 <HAL_RCC_OscConfig+0xbc0>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80028b0: f7fe f908 bl 8000ac4 <HAL_GetTick>
80028b4: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80028b8: e00b b.n 80028d2 <HAL_RCC_OscConfig+0xae2>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80028ba: f7fe f903 bl 8000ac4 <HAL_GetTick>
80028be: 4602 mov r2, r0
80028c0: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80028c4: 1ad3 subs r3, r2, r3
80028c6: f241 3288 movw r2, #5000 @ 0x1388
80028ca: 4293 cmp r3, r2
80028cc: d901 bls.n 80028d2 <HAL_RCC_OscConfig+0xae2>
{
return HAL_TIMEOUT;
80028ce: 2303 movs r3, #3
80028d0: e2c4 b.n 8002e5c <HAL_RCC_OscConfig+0x106c>
80028d2: f507 7300 add.w r3, r7, #512 @ 0x200
80028d6: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
80028da: 2202 movs r2, #2
80028dc: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80028de: f507 7300 add.w r3, r7, #512 @ 0x200
80028e2: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
80028e6: 681b ldr r3, [r3, #0]
80028e8: fa93 f2a3 rbit r2, r3
80028ec: f507 7300 add.w r3, r7, #512 @ 0x200
80028f0: f5a3 73b2 sub.w r3, r3, #356 @ 0x164
80028f4: 601a str r2, [r3, #0]
80028f6: f507 7300 add.w r3, r7, #512 @ 0x200
80028fa: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
80028fe: 2202 movs r2, #2
8002900: 601a str r2, [r3, #0]
8002902: f507 7300 add.w r3, r7, #512 @ 0x200
8002906: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
800290a: 681b ldr r3, [r3, #0]
800290c: fa93 f2a3 rbit r2, r3
8002910: f507 7300 add.w r3, r7, #512 @ 0x200
8002914: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
8002918: 601a str r2, [r3, #0]
return result;
800291a: f507 7300 add.w r3, r7, #512 @ 0x200
800291e: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
8002922: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002924: fab3 f383 clz r3, r3
8002928: b2db uxtb r3, r3
800292a: 095b lsrs r3, r3, #5
800292c: b2db uxtb r3, r3
800292e: f043 0302 orr.w r3, r3, #2
8002932: b2db uxtb r3, r3
8002934: 2b02 cmp r3, #2
8002936: d102 bne.n 800293e <HAL_RCC_OscConfig+0xb4e>
8002938: 4b43 ldr r3, [pc, #268] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
800293a: 6a1b ldr r3, [r3, #32]
800293c: e013 b.n 8002966 <HAL_RCC_OscConfig+0xb76>
800293e: f507 7300 add.w r3, r7, #512 @ 0x200
8002942: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
8002946: 2202 movs r2, #2
8002948: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800294a: f507 7300 add.w r3, r7, #512 @ 0x200
800294e: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
8002952: 681b ldr r3, [r3, #0]
8002954: fa93 f2a3 rbit r2, r3
8002958: f507 7300 add.w r3, r7, #512 @ 0x200
800295c: f5a3 73ba sub.w r3, r3, #372 @ 0x174
8002960: 601a str r2, [r3, #0]
8002962: 4b39 ldr r3, [pc, #228] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
8002964: 6a5b ldr r3, [r3, #36] @ 0x24
8002966: f507 7200 add.w r2, r7, #512 @ 0x200
800296a: f5a2 72bc sub.w r2, r2, #376 @ 0x178
800296e: 2102 movs r1, #2
8002970: 6011 str r1, [r2, #0]
8002972: f507 7200 add.w r2, r7, #512 @ 0x200
8002976: f5a2 72bc sub.w r2, r2, #376 @ 0x178
800297a: 6812 ldr r2, [r2, #0]
800297c: fa92 f1a2 rbit r1, r2
8002980: f507 7200 add.w r2, r7, #512 @ 0x200
8002984: f5a2 72be sub.w r2, r2, #380 @ 0x17c
8002988: 6011 str r1, [r2, #0]
return result;
800298a: f507 7200 add.w r2, r7, #512 @ 0x200
800298e: f5a2 72be sub.w r2, r2, #380 @ 0x17c
8002992: 6812 ldr r2, [r2, #0]
8002994: fab2 f282 clz r2, r2
8002998: b2d2 uxtb r2, r2
800299a: f042 0240 orr.w r2, r2, #64 @ 0x40
800299e: b2d2 uxtb r2, r2
80029a0: f002 021f and.w r2, r2, #31
80029a4: 2101 movs r1, #1
80029a6: fa01 f202 lsl.w r2, r1, r2
80029aa: 4013 ands r3, r2
80029ac: 2b00 cmp r3, #0
80029ae: d184 bne.n 80028ba <HAL_RCC_OscConfig+0xaca>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80029b0: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff
80029b4: 2b01 cmp r3, #1
80029b6: d105 bne.n 80029c4 <HAL_RCC_OscConfig+0xbd4>
{
__HAL_RCC_PWR_CLK_DISABLE();
80029b8: 4b23 ldr r3, [pc, #140] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
80029ba: 69db ldr r3, [r3, #28]
80029bc: 4a22 ldr r2, [pc, #136] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
80029be: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80029c2: 61d3 str r3, [r2, #28]
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80029c4: f507 7300 add.w r3, r7, #512 @ 0x200
80029c8: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80029cc: 681b ldr r3, [r3, #0]
80029ce: 69db ldr r3, [r3, #28]
80029d0: 2b00 cmp r3, #0
80029d2: f000 8242 beq.w 8002e5a <HAL_RCC_OscConfig+0x106a>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80029d6: 4b1c ldr r3, [pc, #112] @ (8002a48 <HAL_RCC_OscConfig+0xc58>)
80029d8: 685b ldr r3, [r3, #4]
80029da: f003 030c and.w r3, r3, #12
80029de: 2b08 cmp r3, #8
80029e0: f000 8213 beq.w 8002e0a <HAL_RCC_OscConfig+0x101a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80029e4: f507 7300 add.w r3, r7, #512 @ 0x200
80029e8: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80029ec: 681b ldr r3, [r3, #0]
80029ee: 69db ldr r3, [r3, #28]
80029f0: 2b02 cmp r3, #2
80029f2: f040 8162 bne.w 8002cba <HAL_RCC_OscConfig+0xeca>
80029f6: f507 7300 add.w r3, r7, #512 @ 0x200
80029fa: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
80029fe: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8002a02: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a04: f507 7300 add.w r3, r7, #512 @ 0x200
8002a08: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
8002a0c: 681b ldr r3, [r3, #0]
8002a0e: fa93 f2a3 rbit r2, r3
8002a12: f507 7300 add.w r3, r7, #512 @ 0x200
8002a16: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
8002a1a: 601a str r2, [r3, #0]
return result;
8002a1c: f507 7300 add.w r3, r7, #512 @ 0x200
8002a20: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
8002a24: 681b ldr r3, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002a26: fab3 f383 clz r3, r3
8002a2a: b2db uxtb r3, r3
8002a2c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8002a30: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002a34: 009b lsls r3, r3, #2
8002a36: 461a mov r2, r3
8002a38: 2300 movs r3, #0
8002a3a: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002a3c: f7fe f842 bl 8000ac4 <HAL_GetTick>
8002a40: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002a44: e00c b.n 8002a60 <HAL_RCC_OscConfig+0xc70>
8002a46: bf00 nop
8002a48: 40021000 .word 0x40021000
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002a4c: f7fe f83a bl 8000ac4 <HAL_GetTick>
8002a50: 4602 mov r2, r0
8002a52: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8002a56: 1ad3 subs r3, r2, r3
8002a58: 2b02 cmp r3, #2
8002a5a: d901 bls.n 8002a60 <HAL_RCC_OscConfig+0xc70>
{
return HAL_TIMEOUT;
8002a5c: 2303 movs r3, #3
8002a5e: e1fd b.n 8002e5c <HAL_RCC_OscConfig+0x106c>
8002a60: f507 7300 add.w r3, r7, #512 @ 0x200
8002a64: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
8002a68: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002a6c: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a6e: f507 7300 add.w r3, r7, #512 @ 0x200
8002a72: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
8002a76: 681b ldr r3, [r3, #0]
8002a78: fa93 f2a3 rbit r2, r3
8002a7c: f507 7300 add.w r3, r7, #512 @ 0x200
8002a80: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
8002a84: 601a str r2, [r3, #0]
return result;
8002a86: f507 7300 add.w r3, r7, #512 @ 0x200
8002a8a: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
8002a8e: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002a90: fab3 f383 clz r3, r3
8002a94: b2db uxtb r3, r3
8002a96: 095b lsrs r3, r3, #5
8002a98: b2db uxtb r3, r3
8002a9a: f043 0301 orr.w r3, r3, #1
8002a9e: b2db uxtb r3, r3
8002aa0: 2b01 cmp r3, #1
8002aa2: d102 bne.n 8002aaa <HAL_RCC_OscConfig+0xcba>
8002aa4: 4bb0 ldr r3, [pc, #704] @ (8002d68 <HAL_RCC_OscConfig+0xf78>)
8002aa6: 681b ldr r3, [r3, #0]
8002aa8: e027 b.n 8002afa <HAL_RCC_OscConfig+0xd0a>
8002aaa: f507 7300 add.w r3, r7, #512 @ 0x200
8002aae: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
8002ab2: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002ab6: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ab8: f507 7300 add.w r3, r7, #512 @ 0x200
8002abc: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
8002ac0: 681b ldr r3, [r3, #0]
8002ac2: fa93 f2a3 rbit r2, r3
8002ac6: f507 7300 add.w r3, r7, #512 @ 0x200
8002aca: f5a3 73ca sub.w r3, r3, #404 @ 0x194
8002ace: 601a str r2, [r3, #0]
8002ad0: f507 7300 add.w r3, r7, #512 @ 0x200
8002ad4: f5a3 73cc sub.w r3, r3, #408 @ 0x198
8002ad8: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002adc: 601a str r2, [r3, #0]
8002ade: f507 7300 add.w r3, r7, #512 @ 0x200
8002ae2: f5a3 73cc sub.w r3, r3, #408 @ 0x198
8002ae6: 681b ldr r3, [r3, #0]
8002ae8: fa93 f2a3 rbit r2, r3
8002aec: f507 7300 add.w r3, r7, #512 @ 0x200
8002af0: f5a3 73ce sub.w r3, r3, #412 @ 0x19c
8002af4: 601a str r2, [r3, #0]
8002af6: 4b9c ldr r3, [pc, #624] @ (8002d68 <HAL_RCC_OscConfig+0xf78>)
8002af8: 6a5b ldr r3, [r3, #36] @ 0x24
8002afa: f507 7200 add.w r2, r7, #512 @ 0x200
8002afe: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
8002b02: f04f 7100 mov.w r1, #33554432 @ 0x2000000
8002b06: 6011 str r1, [r2, #0]
8002b08: f507 7200 add.w r2, r7, #512 @ 0x200
8002b0c: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
8002b10: 6812 ldr r2, [r2, #0]
8002b12: fa92 f1a2 rbit r1, r2
8002b16: f507 7200 add.w r2, r7, #512 @ 0x200
8002b1a: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
8002b1e: 6011 str r1, [r2, #0]
return result;
8002b20: f507 7200 add.w r2, r7, #512 @ 0x200
8002b24: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
8002b28: 6812 ldr r2, [r2, #0]
8002b2a: fab2 f282 clz r2, r2
8002b2e: b2d2 uxtb r2, r2
8002b30: f042 0220 orr.w r2, r2, #32
8002b34: b2d2 uxtb r2, r2
8002b36: f002 021f and.w r2, r2, #31
8002b3a: 2101 movs r1, #1
8002b3c: fa01 f202 lsl.w r2, r1, r2
8002b40: 4013 ands r3, r2
8002b42: 2b00 cmp r3, #0
8002b44: d182 bne.n 8002a4c <HAL_RCC_OscConfig+0xc5c>
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
#else
/* Configure the main PLL clock source and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8002b46: 4b88 ldr r3, [pc, #544] @ (8002d68 <HAL_RCC_OscConfig+0xf78>)
8002b48: 685b ldr r3, [r3, #4]
8002b4a: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8002b4e: f507 7300 add.w r3, r7, #512 @ 0x200
8002b52: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002b56: 681b ldr r3, [r3, #0]
8002b58: 6a59 ldr r1, [r3, #36] @ 0x24
8002b5a: f507 7300 add.w r3, r7, #512 @ 0x200
8002b5e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002b62: 681b ldr r3, [r3, #0]
8002b64: 6a1b ldr r3, [r3, #32]
8002b66: 430b orrs r3, r1
8002b68: 497f ldr r1, [pc, #508] @ (8002d68 <HAL_RCC_OscConfig+0xf78>)
8002b6a: 4313 orrs r3, r2
8002b6c: 604b str r3, [r1, #4]
8002b6e: f507 7300 add.w r3, r7, #512 @ 0x200
8002b72: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
8002b76: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8002b7a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002b7c: f507 7300 add.w r3, r7, #512 @ 0x200
8002b80: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
8002b84: 681b ldr r3, [r3, #0]
8002b86: fa93 f2a3 rbit r2, r3
8002b8a: f507 7300 add.w r3, r7, #512 @ 0x200
8002b8e: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
8002b92: 601a str r2, [r3, #0]
return result;
8002b94: f507 7300 add.w r3, r7, #512 @ 0x200
8002b98: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
8002b9c: 681b ldr r3, [r3, #0]
RCC_OscInitStruct->PLL.PLLMUL);
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002b9e: fab3 f383 clz r3, r3
8002ba2: b2db uxtb r3, r3
8002ba4: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8002ba8: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002bac: 009b lsls r3, r3, #2
8002bae: 461a mov r2, r3
8002bb0: 2301 movs r3, #1
8002bb2: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002bb4: f7fd ff86 bl 8000ac4 <HAL_GetTick>
8002bb8: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002bbc: e009 b.n 8002bd2 <HAL_RCC_OscConfig+0xde2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002bbe: f7fd ff81 bl 8000ac4 <HAL_GetTick>
8002bc2: 4602 mov r2, r0
8002bc4: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8002bc8: 1ad3 subs r3, r2, r3
8002bca: 2b02 cmp r3, #2
8002bcc: d901 bls.n 8002bd2 <HAL_RCC_OscConfig+0xde2>
{
return HAL_TIMEOUT;
8002bce: 2303 movs r3, #3
8002bd0: e144 b.n 8002e5c <HAL_RCC_OscConfig+0x106c>
8002bd2: f507 7300 add.w r3, r7, #512 @ 0x200
8002bd6: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
8002bda: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002bde: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002be0: f507 7300 add.w r3, r7, #512 @ 0x200
8002be4: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
8002be8: 681b ldr r3, [r3, #0]
8002bea: fa93 f2a3 rbit r2, r3
8002bee: f507 7300 add.w r3, r7, #512 @ 0x200
8002bf2: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
8002bf6: 601a str r2, [r3, #0]
return result;
8002bf8: f507 7300 add.w r3, r7, #512 @ 0x200
8002bfc: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
8002c00: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002c02: fab3 f383 clz r3, r3
8002c06: b2db uxtb r3, r3
8002c08: 095b lsrs r3, r3, #5
8002c0a: b2db uxtb r3, r3
8002c0c: f043 0301 orr.w r3, r3, #1
8002c10: b2db uxtb r3, r3
8002c12: 2b01 cmp r3, #1
8002c14: d102 bne.n 8002c1c <HAL_RCC_OscConfig+0xe2c>
8002c16: 4b54 ldr r3, [pc, #336] @ (8002d68 <HAL_RCC_OscConfig+0xf78>)
8002c18: 681b ldr r3, [r3, #0]
8002c1a: e027 b.n 8002c6c <HAL_RCC_OscConfig+0xe7c>
8002c1c: f507 7300 add.w r3, r7, #512 @ 0x200
8002c20: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
8002c24: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002c28: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c2a: f507 7300 add.w r3, r7, #512 @ 0x200
8002c2e: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
8002c32: 681b ldr r3, [r3, #0]
8002c34: fa93 f2a3 rbit r2, r3
8002c38: f507 7300 add.w r3, r7, #512 @ 0x200
8002c3c: f5a3 73de sub.w r3, r3, #444 @ 0x1bc
8002c40: 601a str r2, [r3, #0]
8002c42: f507 7300 add.w r3, r7, #512 @ 0x200
8002c46: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
8002c4a: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002c4e: 601a str r2, [r3, #0]
8002c50: f507 7300 add.w r3, r7, #512 @ 0x200
8002c54: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
8002c58: 681b ldr r3, [r3, #0]
8002c5a: fa93 f2a3 rbit r2, r3
8002c5e: f507 7300 add.w r3, r7, #512 @ 0x200
8002c62: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4
8002c66: 601a str r2, [r3, #0]
8002c68: 4b3f ldr r3, [pc, #252] @ (8002d68 <HAL_RCC_OscConfig+0xf78>)
8002c6a: 6a5b ldr r3, [r3, #36] @ 0x24
8002c6c: f507 7200 add.w r2, r7, #512 @ 0x200
8002c70: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
8002c74: f04f 7100 mov.w r1, #33554432 @ 0x2000000
8002c78: 6011 str r1, [r2, #0]
8002c7a: f507 7200 add.w r2, r7, #512 @ 0x200
8002c7e: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
8002c82: 6812 ldr r2, [r2, #0]
8002c84: fa92 f1a2 rbit r1, r2
8002c88: f507 7200 add.w r2, r7, #512 @ 0x200
8002c8c: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
8002c90: 6011 str r1, [r2, #0]
return result;
8002c92: f507 7200 add.w r2, r7, #512 @ 0x200
8002c96: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
8002c9a: 6812 ldr r2, [r2, #0]
8002c9c: fab2 f282 clz r2, r2
8002ca0: b2d2 uxtb r2, r2
8002ca2: f042 0220 orr.w r2, r2, #32
8002ca6: b2d2 uxtb r2, r2
8002ca8: f002 021f and.w r2, r2, #31
8002cac: 2101 movs r1, #1
8002cae: fa01 f202 lsl.w r2, r1, r2
8002cb2: 4013 ands r3, r2
8002cb4: 2b00 cmp r3, #0
8002cb6: d082 beq.n 8002bbe <HAL_RCC_OscConfig+0xdce>
8002cb8: e0cf b.n 8002e5a <HAL_RCC_OscConfig+0x106a>
8002cba: f507 7300 add.w r3, r7, #512 @ 0x200
8002cbe: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
8002cc2: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8002cc6: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002cc8: f507 7300 add.w r3, r7, #512 @ 0x200
8002ccc: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
8002cd0: 681b ldr r3, [r3, #0]
8002cd2: fa93 f2a3 rbit r2, r3
8002cd6: f507 7300 add.w r3, r7, #512 @ 0x200
8002cda: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
8002cde: 601a str r2, [r3, #0]
return result;
8002ce0: f507 7300 add.w r3, r7, #512 @ 0x200
8002ce4: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
8002ce8: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002cea: fab3 f383 clz r3, r3
8002cee: b2db uxtb r3, r3
8002cf0: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8002cf4: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002cf8: 009b lsls r3, r3, #2
8002cfa: 461a mov r2, r3
8002cfc: 2300 movs r3, #0
8002cfe: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002d00: f7fd fee0 bl 8000ac4 <HAL_GetTick>
8002d04: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002d08: e009 b.n 8002d1e <HAL_RCC_OscConfig+0xf2e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002d0a: f7fd fedb bl 8000ac4 <HAL_GetTick>
8002d0e: 4602 mov r2, r0
8002d10: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8002d14: 1ad3 subs r3, r2, r3
8002d16: 2b02 cmp r3, #2
8002d18: d901 bls.n 8002d1e <HAL_RCC_OscConfig+0xf2e>
{
return HAL_TIMEOUT;
8002d1a: 2303 movs r3, #3
8002d1c: e09e b.n 8002e5c <HAL_RCC_OscConfig+0x106c>
8002d1e: f507 7300 add.w r3, r7, #512 @ 0x200
8002d22: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
8002d26: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002d2a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d2c: f507 7300 add.w r3, r7, #512 @ 0x200
8002d30: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
8002d34: 681b ldr r3, [r3, #0]
8002d36: fa93 f2a3 rbit r2, r3
8002d3a: f507 7300 add.w r3, r7, #512 @ 0x200
8002d3e: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
8002d42: 601a str r2, [r3, #0]
return result;
8002d44: f507 7300 add.w r3, r7, #512 @ 0x200
8002d48: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
8002d4c: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002d4e: fab3 f383 clz r3, r3
8002d52: b2db uxtb r3, r3
8002d54: 095b lsrs r3, r3, #5
8002d56: b2db uxtb r3, r3
8002d58: f043 0301 orr.w r3, r3, #1
8002d5c: b2db uxtb r3, r3
8002d5e: 2b01 cmp r3, #1
8002d60: d104 bne.n 8002d6c <HAL_RCC_OscConfig+0xf7c>
8002d62: 4b01 ldr r3, [pc, #4] @ (8002d68 <HAL_RCC_OscConfig+0xf78>)
8002d64: 681b ldr r3, [r3, #0]
8002d66: e029 b.n 8002dbc <HAL_RCC_OscConfig+0xfcc>
8002d68: 40021000 .word 0x40021000
8002d6c: f507 7300 add.w r3, r7, #512 @ 0x200
8002d70: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
8002d74: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002d78: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d7a: f507 7300 add.w r3, r7, #512 @ 0x200
8002d7e: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
8002d82: 681b ldr r3, [r3, #0]
8002d84: fa93 f2a3 rbit r2, r3
8002d88: f507 7300 add.w r3, r7, #512 @ 0x200
8002d8c: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4
8002d90: 601a str r2, [r3, #0]
8002d92: f507 7300 add.w r3, r7, #512 @ 0x200
8002d96: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
8002d9a: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002d9e: 601a str r2, [r3, #0]
8002da0: f507 7300 add.w r3, r7, #512 @ 0x200
8002da4: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
8002da8: 681b ldr r3, [r3, #0]
8002daa: fa93 f2a3 rbit r2, r3
8002dae: f507 7300 add.w r3, r7, #512 @ 0x200
8002db2: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec
8002db6: 601a str r2, [r3, #0]
8002db8: 4b2b ldr r3, [pc, #172] @ (8002e68 <HAL_RCC_OscConfig+0x1078>)
8002dba: 6a5b ldr r3, [r3, #36] @ 0x24
8002dbc: f507 7200 add.w r2, r7, #512 @ 0x200
8002dc0: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
8002dc4: f04f 7100 mov.w r1, #33554432 @ 0x2000000
8002dc8: 6011 str r1, [r2, #0]
8002dca: f507 7200 add.w r2, r7, #512 @ 0x200
8002dce: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
8002dd2: 6812 ldr r2, [r2, #0]
8002dd4: fa92 f1a2 rbit r1, r2
8002dd8: f507 7200 add.w r2, r7, #512 @ 0x200
8002ddc: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
8002de0: 6011 str r1, [r2, #0]
return result;
8002de2: f507 7200 add.w r2, r7, #512 @ 0x200
8002de6: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
8002dea: 6812 ldr r2, [r2, #0]
8002dec: fab2 f282 clz r2, r2
8002df0: b2d2 uxtb r2, r2
8002df2: f042 0220 orr.w r2, r2, #32
8002df6: b2d2 uxtb r2, r2
8002df8: f002 021f and.w r2, r2, #31
8002dfc: 2101 movs r1, #1
8002dfe: fa01 f202 lsl.w r2, r1, r2
8002e02: 4013 ands r3, r2
8002e04: 2b00 cmp r3, #0
8002e06: d180 bne.n 8002d0a <HAL_RCC_OscConfig+0xf1a>
8002e08: e027 b.n 8002e5a <HAL_RCC_OscConfig+0x106a>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002e0a: f507 7300 add.w r3, r7, #512 @ 0x200
8002e0e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002e12: 681b ldr r3, [r3, #0]
8002e14: 69db ldr r3, [r3, #28]
8002e16: 2b01 cmp r3, #1
8002e18: d101 bne.n 8002e1e <HAL_RCC_OscConfig+0x102e>
{
return HAL_ERROR;
8002e1a: 2301 movs r3, #1
8002e1c: e01e b.n 8002e5c <HAL_RCC_OscConfig+0x106c>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8002e1e: 4b12 ldr r3, [pc, #72] @ (8002e68 <HAL_RCC_OscConfig+0x1078>)
8002e20: 685b ldr r3, [r3, #4]
8002e22: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4
pll_config2 = RCC->CFGR2;
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
#else
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002e26: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
8002e2a: f403 3280 and.w r2, r3, #65536 @ 0x10000
8002e2e: f507 7300 add.w r3, r7, #512 @ 0x200
8002e32: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002e36: 681b ldr r3, [r3, #0]
8002e38: 6a1b ldr r3, [r3, #32]
8002e3a: 429a cmp r2, r3
8002e3c: d10b bne.n 8002e56 <HAL_RCC_OscConfig+0x1066>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8002e3e: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
8002e42: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8002e46: f507 7300 add.w r3, r7, #512 @ 0x200
8002e4a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002e4e: 681b ldr r3, [r3, #0]
8002e50: 6a5b ldr r3, [r3, #36] @ 0x24
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002e52: 429a cmp r2, r3
8002e54: d001 beq.n 8002e5a <HAL_RCC_OscConfig+0x106a>
#endif
{
return HAL_ERROR;
8002e56: 2301 movs r3, #1
8002e58: e000 b.n 8002e5c <HAL_RCC_OscConfig+0x106c>
}
}
}
}
return HAL_OK;
8002e5a: 2300 movs r3, #0
}
8002e5c: 4618 mov r0, r3
8002e5e: f507 7700 add.w r7, r7, #512 @ 0x200
8002e62: 46bd mov sp, r7
8002e64: bd80 pop {r7, pc}
8002e66: bf00 nop
8002e68: 40021000 .word 0x40021000
08002e6c <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002e6c: b580 push {r7, lr}
8002e6e: b09e sub sp, #120 @ 0x78
8002e70: af00 add r7, sp, #0
8002e72: 6078 str r0, [r7, #4]
8002e74: 6039 str r1, [r7, #0]
uint32_t tickstart = 0U;
8002e76: 2300 movs r3, #0
8002e78: 677b str r3, [r7, #116] @ 0x74
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002e7a: 687b ldr r3, [r7, #4]
8002e7c: 2b00 cmp r3, #0
8002e7e: d101 bne.n 8002e84 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002e80: 2301 movs r3, #1
8002e82: e162 b.n 800314a <HAL_RCC_ClockConfig+0x2de>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8002e84: 4b90 ldr r3, [pc, #576] @ (80030c8 <HAL_RCC_ClockConfig+0x25c>)
8002e86: 681b ldr r3, [r3, #0]
8002e88: f003 0307 and.w r3, r3, #7
8002e8c: 683a ldr r2, [r7, #0]
8002e8e: 429a cmp r2, r3
8002e90: d910 bls.n 8002eb4 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002e92: 4b8d ldr r3, [pc, #564] @ (80030c8 <HAL_RCC_ClockConfig+0x25c>)
8002e94: 681b ldr r3, [r3, #0]
8002e96: f023 0207 bic.w r2, r3, #7
8002e9a: 498b ldr r1, [pc, #556] @ (80030c8 <HAL_RCC_ClockConfig+0x25c>)
8002e9c: 683b ldr r3, [r7, #0]
8002e9e: 4313 orrs r3, r2
8002ea0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002ea2: 4b89 ldr r3, [pc, #548] @ (80030c8 <HAL_RCC_ClockConfig+0x25c>)
8002ea4: 681b ldr r3, [r3, #0]
8002ea6: f003 0307 and.w r3, r3, #7
8002eaa: 683a ldr r2, [r7, #0]
8002eac: 429a cmp r2, r3
8002eae: d001 beq.n 8002eb4 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8002eb0: 2301 movs r3, #1
8002eb2: e14a b.n 800314a <HAL_RCC_ClockConfig+0x2de>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002eb4: 687b ldr r3, [r7, #4]
8002eb6: 681b ldr r3, [r3, #0]
8002eb8: f003 0302 and.w r3, r3, #2
8002ebc: 2b00 cmp r3, #0
8002ebe: d008 beq.n 8002ed2 <HAL_RCC_ClockConfig+0x66>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002ec0: 4b82 ldr r3, [pc, #520] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8002ec2: 685b ldr r3, [r3, #4]
8002ec4: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002ec8: 687b ldr r3, [r7, #4]
8002eca: 689b ldr r3, [r3, #8]
8002ecc: 497f ldr r1, [pc, #508] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8002ece: 4313 orrs r3, r2
8002ed0: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002ed2: 687b ldr r3, [r7, #4]
8002ed4: 681b ldr r3, [r3, #0]
8002ed6: f003 0301 and.w r3, r3, #1
8002eda: 2b00 cmp r3, #0
8002edc: f000 80dc beq.w 8003098 <HAL_RCC_ClockConfig+0x22c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002ee0: 687b ldr r3, [r7, #4]
8002ee2: 685b ldr r3, [r3, #4]
8002ee4: 2b01 cmp r3, #1
8002ee6: d13c bne.n 8002f62 <HAL_RCC_ClockConfig+0xf6>
8002ee8: f44f 3300 mov.w r3, #131072 @ 0x20000
8002eec: 673b str r3, [r7, #112] @ 0x70
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002eee: 6f3b ldr r3, [r7, #112] @ 0x70
8002ef0: fa93 f3a3 rbit r3, r3
8002ef4: 66fb str r3, [r7, #108] @ 0x6c
return result;
8002ef6: 6efb ldr r3, [r7, #108] @ 0x6c
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002ef8: fab3 f383 clz r3, r3
8002efc: b2db uxtb r3, r3
8002efe: 095b lsrs r3, r3, #5
8002f00: b2db uxtb r3, r3
8002f02: f043 0301 orr.w r3, r3, #1
8002f06: b2db uxtb r3, r3
8002f08: 2b01 cmp r3, #1
8002f0a: d102 bne.n 8002f12 <HAL_RCC_ClockConfig+0xa6>
8002f0c: 4b6f ldr r3, [pc, #444] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8002f0e: 681b ldr r3, [r3, #0]
8002f10: e00f b.n 8002f32 <HAL_RCC_ClockConfig+0xc6>
8002f12: f44f 3300 mov.w r3, #131072 @ 0x20000
8002f16: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f18: 6ebb ldr r3, [r7, #104] @ 0x68
8002f1a: fa93 f3a3 rbit r3, r3
8002f1e: 667b str r3, [r7, #100] @ 0x64
8002f20: f44f 3300 mov.w r3, #131072 @ 0x20000
8002f24: 663b str r3, [r7, #96] @ 0x60
8002f26: 6e3b ldr r3, [r7, #96] @ 0x60
8002f28: fa93 f3a3 rbit r3, r3
8002f2c: 65fb str r3, [r7, #92] @ 0x5c
8002f2e: 4b67 ldr r3, [pc, #412] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8002f30: 6a5b ldr r3, [r3, #36] @ 0x24
8002f32: f44f 3200 mov.w r2, #131072 @ 0x20000
8002f36: 65ba str r2, [r7, #88] @ 0x58
8002f38: 6dba ldr r2, [r7, #88] @ 0x58
8002f3a: fa92 f2a2 rbit r2, r2
8002f3e: 657a str r2, [r7, #84] @ 0x54
return result;
8002f40: 6d7a ldr r2, [r7, #84] @ 0x54
8002f42: fab2 f282 clz r2, r2
8002f46: b2d2 uxtb r2, r2
8002f48: f042 0220 orr.w r2, r2, #32
8002f4c: b2d2 uxtb r2, r2
8002f4e: f002 021f and.w r2, r2, #31
8002f52: 2101 movs r1, #1
8002f54: fa01 f202 lsl.w r2, r1, r2
8002f58: 4013 ands r3, r2
8002f5a: 2b00 cmp r3, #0
8002f5c: d17b bne.n 8003056 <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8002f5e: 2301 movs r3, #1
8002f60: e0f3 b.n 800314a <HAL_RCC_ClockConfig+0x2de>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8002f62: 687b ldr r3, [r7, #4]
8002f64: 685b ldr r3, [r3, #4]
8002f66: 2b02 cmp r3, #2
8002f68: d13c bne.n 8002fe4 <HAL_RCC_ClockConfig+0x178>
8002f6a: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8002f6e: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f70: 6d3b ldr r3, [r7, #80] @ 0x50
8002f72: fa93 f3a3 rbit r3, r3
8002f76: 64fb str r3, [r7, #76] @ 0x4c
return result;
8002f78: 6cfb ldr r3, [r7, #76] @ 0x4c
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002f7a: fab3 f383 clz r3, r3
8002f7e: b2db uxtb r3, r3
8002f80: 095b lsrs r3, r3, #5
8002f82: b2db uxtb r3, r3
8002f84: f043 0301 orr.w r3, r3, #1
8002f88: b2db uxtb r3, r3
8002f8a: 2b01 cmp r3, #1
8002f8c: d102 bne.n 8002f94 <HAL_RCC_ClockConfig+0x128>
8002f8e: 4b4f ldr r3, [pc, #316] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8002f90: 681b ldr r3, [r3, #0]
8002f92: e00f b.n 8002fb4 <HAL_RCC_ClockConfig+0x148>
8002f94: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8002f98: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f9a: 6cbb ldr r3, [r7, #72] @ 0x48
8002f9c: fa93 f3a3 rbit r3, r3
8002fa0: 647b str r3, [r7, #68] @ 0x44
8002fa2: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8002fa6: 643b str r3, [r7, #64] @ 0x40
8002fa8: 6c3b ldr r3, [r7, #64] @ 0x40
8002faa: fa93 f3a3 rbit r3, r3
8002fae: 63fb str r3, [r7, #60] @ 0x3c
8002fb0: 4b46 ldr r3, [pc, #280] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8002fb2: 6a5b ldr r3, [r3, #36] @ 0x24
8002fb4: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002fb8: 63ba str r2, [r7, #56] @ 0x38
8002fba: 6bba ldr r2, [r7, #56] @ 0x38
8002fbc: fa92 f2a2 rbit r2, r2
8002fc0: 637a str r2, [r7, #52] @ 0x34
return result;
8002fc2: 6b7a ldr r2, [r7, #52] @ 0x34
8002fc4: fab2 f282 clz r2, r2
8002fc8: b2d2 uxtb r2, r2
8002fca: f042 0220 orr.w r2, r2, #32
8002fce: b2d2 uxtb r2, r2
8002fd0: f002 021f and.w r2, r2, #31
8002fd4: 2101 movs r1, #1
8002fd6: fa01 f202 lsl.w r2, r1, r2
8002fda: 4013 ands r3, r2
8002fdc: 2b00 cmp r3, #0
8002fde: d13a bne.n 8003056 <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8002fe0: 2301 movs r3, #1
8002fe2: e0b2 b.n 800314a <HAL_RCC_ClockConfig+0x2de>
8002fe4: 2302 movs r3, #2
8002fe6: 633b str r3, [r7, #48] @ 0x30
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002fe8: 6b3b ldr r3, [r7, #48] @ 0x30
8002fea: fa93 f3a3 rbit r3, r3
8002fee: 62fb str r3, [r7, #44] @ 0x2c
return result;
8002ff0: 6afb ldr r3, [r7, #44] @ 0x2c
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002ff2: fab3 f383 clz r3, r3
8002ff6: b2db uxtb r3, r3
8002ff8: 095b lsrs r3, r3, #5
8002ffa: b2db uxtb r3, r3
8002ffc: f043 0301 orr.w r3, r3, #1
8003000: b2db uxtb r3, r3
8003002: 2b01 cmp r3, #1
8003004: d102 bne.n 800300c <HAL_RCC_ClockConfig+0x1a0>
8003006: 4b31 ldr r3, [pc, #196] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8003008: 681b ldr r3, [r3, #0]
800300a: e00d b.n 8003028 <HAL_RCC_ClockConfig+0x1bc>
800300c: 2302 movs r3, #2
800300e: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003010: 6abb ldr r3, [r7, #40] @ 0x28
8003012: fa93 f3a3 rbit r3, r3
8003016: 627b str r3, [r7, #36] @ 0x24
8003018: 2302 movs r3, #2
800301a: 623b str r3, [r7, #32]
800301c: 6a3b ldr r3, [r7, #32]
800301e: fa93 f3a3 rbit r3, r3
8003022: 61fb str r3, [r7, #28]
8003024: 4b29 ldr r3, [pc, #164] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8003026: 6a5b ldr r3, [r3, #36] @ 0x24
8003028: 2202 movs r2, #2
800302a: 61ba str r2, [r7, #24]
800302c: 69ba ldr r2, [r7, #24]
800302e: fa92 f2a2 rbit r2, r2
8003032: 617a str r2, [r7, #20]
return result;
8003034: 697a ldr r2, [r7, #20]
8003036: fab2 f282 clz r2, r2
800303a: b2d2 uxtb r2, r2
800303c: f042 0220 orr.w r2, r2, #32
8003040: b2d2 uxtb r2, r2
8003042: f002 021f and.w r2, r2, #31
8003046: 2101 movs r1, #1
8003048: fa01 f202 lsl.w r2, r1, r2
800304c: 4013 ands r3, r2
800304e: 2b00 cmp r3, #0
8003050: d101 bne.n 8003056 <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8003052: 2301 movs r3, #1
8003054: e079 b.n 800314a <HAL_RCC_ClockConfig+0x2de>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8003056: 4b1d ldr r3, [pc, #116] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8003058: 685b ldr r3, [r3, #4]
800305a: f023 0203 bic.w r2, r3, #3
800305e: 687b ldr r3, [r7, #4]
8003060: 685b ldr r3, [r3, #4]
8003062: 491a ldr r1, [pc, #104] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8003064: 4313 orrs r3, r2
8003066: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003068: f7fd fd2c bl 8000ac4 <HAL_GetTick>
800306c: 6778 str r0, [r7, #116] @ 0x74
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800306e: e00a b.n 8003086 <HAL_RCC_ClockConfig+0x21a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003070: f7fd fd28 bl 8000ac4 <HAL_GetTick>
8003074: 4602 mov r2, r0
8003076: 6f7b ldr r3, [r7, #116] @ 0x74
8003078: 1ad3 subs r3, r2, r3
800307a: f241 3288 movw r2, #5000 @ 0x1388
800307e: 4293 cmp r3, r2
8003080: d901 bls.n 8003086 <HAL_RCC_ClockConfig+0x21a>
{
return HAL_TIMEOUT;
8003082: 2303 movs r3, #3
8003084: e061 b.n 800314a <HAL_RCC_ClockConfig+0x2de>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003086: 4b11 ldr r3, [pc, #68] @ (80030cc <HAL_RCC_ClockConfig+0x260>)
8003088: 685b ldr r3, [r3, #4]
800308a: f003 020c and.w r2, r3, #12
800308e: 687b ldr r3, [r7, #4]
8003090: 685b ldr r3, [r3, #4]
8003092: 009b lsls r3, r3, #2
8003094: 429a cmp r2, r3
8003096: d1eb bne.n 8003070 <HAL_RCC_ClockConfig+0x204>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8003098: 4b0b ldr r3, [pc, #44] @ (80030c8 <HAL_RCC_ClockConfig+0x25c>)
800309a: 681b ldr r3, [r3, #0]
800309c: f003 0307 and.w r3, r3, #7
80030a0: 683a ldr r2, [r7, #0]
80030a2: 429a cmp r2, r3
80030a4: d214 bcs.n 80030d0 <HAL_RCC_ClockConfig+0x264>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80030a6: 4b08 ldr r3, [pc, #32] @ (80030c8 <HAL_RCC_ClockConfig+0x25c>)
80030a8: 681b ldr r3, [r3, #0]
80030aa: f023 0207 bic.w r2, r3, #7
80030ae: 4906 ldr r1, [pc, #24] @ (80030c8 <HAL_RCC_ClockConfig+0x25c>)
80030b0: 683b ldr r3, [r7, #0]
80030b2: 4313 orrs r3, r2
80030b4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80030b6: 4b04 ldr r3, [pc, #16] @ (80030c8 <HAL_RCC_ClockConfig+0x25c>)
80030b8: 681b ldr r3, [r3, #0]
80030ba: f003 0307 and.w r3, r3, #7
80030be: 683a ldr r2, [r7, #0]
80030c0: 429a cmp r2, r3
80030c2: d005 beq.n 80030d0 <HAL_RCC_ClockConfig+0x264>
{
return HAL_ERROR;
80030c4: 2301 movs r3, #1
80030c6: e040 b.n 800314a <HAL_RCC_ClockConfig+0x2de>
80030c8: 40022000 .word 0x40022000
80030cc: 40021000 .word 0x40021000
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80030d0: 687b ldr r3, [r7, #4]
80030d2: 681b ldr r3, [r3, #0]
80030d4: f003 0304 and.w r3, r3, #4
80030d8: 2b00 cmp r3, #0
80030da: d008 beq.n 80030ee <HAL_RCC_ClockConfig+0x282>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80030dc: 4b1d ldr r3, [pc, #116] @ (8003154 <HAL_RCC_ClockConfig+0x2e8>)
80030de: 685b ldr r3, [r3, #4]
80030e0: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80030e4: 687b ldr r3, [r7, #4]
80030e6: 68db ldr r3, [r3, #12]
80030e8: 491a ldr r1, [pc, #104] @ (8003154 <HAL_RCC_ClockConfig+0x2e8>)
80030ea: 4313 orrs r3, r2
80030ec: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80030ee: 687b ldr r3, [r7, #4]
80030f0: 681b ldr r3, [r3, #0]
80030f2: f003 0308 and.w r3, r3, #8
80030f6: 2b00 cmp r3, #0
80030f8: d009 beq.n 800310e <HAL_RCC_ClockConfig+0x2a2>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80030fa: 4b16 ldr r3, [pc, #88] @ (8003154 <HAL_RCC_ClockConfig+0x2e8>)
80030fc: 685b ldr r3, [r3, #4]
80030fe: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8003102: 687b ldr r3, [r7, #4]
8003104: 691b ldr r3, [r3, #16]
8003106: 00db lsls r3, r3, #3
8003108: 4912 ldr r1, [pc, #72] @ (8003154 <HAL_RCC_ClockConfig+0x2e8>)
800310a: 4313 orrs r3, r2
800310c: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
800310e: f000 f829 bl 8003164 <HAL_RCC_GetSysClockFreq>
8003112: 4601 mov r1, r0
8003114: 4b0f ldr r3, [pc, #60] @ (8003154 <HAL_RCC_ClockConfig+0x2e8>)
8003116: 685b ldr r3, [r3, #4]
8003118: f003 03f0 and.w r3, r3, #240 @ 0xf0
800311c: 22f0 movs r2, #240 @ 0xf0
800311e: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003120: 693a ldr r2, [r7, #16]
8003122: fa92 f2a2 rbit r2, r2
8003126: 60fa str r2, [r7, #12]
return result;
8003128: 68fa ldr r2, [r7, #12]
800312a: fab2 f282 clz r2, r2
800312e: b2d2 uxtb r2, r2
8003130: 40d3 lsrs r3, r2
8003132: 4a09 ldr r2, [pc, #36] @ (8003158 <HAL_RCC_ClockConfig+0x2ec>)
8003134: 5cd3 ldrb r3, [r2, r3]
8003136: fa21 f303 lsr.w r3, r1, r3
800313a: 4a08 ldr r2, [pc, #32] @ (800315c <HAL_RCC_ClockConfig+0x2f0>)
800313c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (uwTickPrio);
800313e: 4b08 ldr r3, [pc, #32] @ (8003160 <HAL_RCC_ClockConfig+0x2f4>)
8003140: 681b ldr r3, [r3, #0]
8003142: 4618 mov r0, r3
8003144: f7fd fc7a bl 8000a3c <HAL_InitTick>
return HAL_OK;
8003148: 2300 movs r3, #0
}
800314a: 4618 mov r0, r3
800314c: 3778 adds r7, #120 @ 0x78
800314e: 46bd mov sp, r7
8003150: bd80 pop {r7, pc}
8003152: bf00 nop
8003154: 40021000 .word 0x40021000
8003158: 0800327c .word 0x0800327c
800315c: 20000000 .word 0x20000000
8003160: 20000004 .word 0x20000004
08003164 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003164: b480 push {r7}
8003166: b087 sub sp, #28
8003168: af00 add r7, sp, #0
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
800316a: 2300 movs r3, #0
800316c: 60fb str r3, [r7, #12]
800316e: 2300 movs r3, #0
8003170: 60bb str r3, [r7, #8]
8003172: 2300 movs r3, #0
8003174: 617b str r3, [r7, #20]
8003176: 2300 movs r3, #0
8003178: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
800317a: 2300 movs r3, #0
800317c: 613b str r3, [r7, #16]
tmpreg = RCC->CFGR;
800317e: 4b1e ldr r3, [pc, #120] @ (80031f8 <HAL_RCC_GetSysClockFreq+0x94>)
8003180: 685b ldr r3, [r3, #4]
8003182: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8003184: 68fb ldr r3, [r7, #12]
8003186: f003 030c and.w r3, r3, #12
800318a: 2b04 cmp r3, #4
800318c: d002 beq.n 8003194 <HAL_RCC_GetSysClockFreq+0x30>
800318e: 2b08 cmp r3, #8
8003190: d003 beq.n 800319a <HAL_RCC_GetSysClockFreq+0x36>
8003192: e026 b.n 80031e2 <HAL_RCC_GetSysClockFreq+0x7e>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8003194: 4b19 ldr r3, [pc, #100] @ (80031fc <HAL_RCC_GetSysClockFreq+0x98>)
8003196: 613b str r3, [r7, #16]
break;
8003198: e026 b.n 80031e8 <HAL_RCC_GetSysClockFreq+0x84>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
800319a: 68fb ldr r3, [r7, #12]
800319c: 0c9b lsrs r3, r3, #18
800319e: f003 030f and.w r3, r3, #15
80031a2: 4a17 ldr r2, [pc, #92] @ (8003200 <HAL_RCC_GetSysClockFreq+0x9c>)
80031a4: 5cd3 ldrb r3, [r2, r3]
80031a6: 607b str r3, [r7, #4]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_Pos];
80031a8: 4b13 ldr r3, [pc, #76] @ (80031f8 <HAL_RCC_GetSysClockFreq+0x94>)
80031aa: 6adb ldr r3, [r3, #44] @ 0x2c
80031ac: f003 030f and.w r3, r3, #15
80031b0: 4a14 ldr r2, [pc, #80] @ (8003204 <HAL_RCC_GetSysClockFreq+0xa0>)
80031b2: 5cd3 ldrb r3, [r2, r3]
80031b4: 60bb str r3, [r7, #8]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
80031b6: 68fb ldr r3, [r7, #12]
80031b8: f403 3380 and.w r3, r3, #65536 @ 0x10000
80031bc: 2b00 cmp r3, #0
80031be: d008 beq.n 80031d2 <HAL_RCC_GetSysClockFreq+0x6e>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
80031c0: 4a0e ldr r2, [pc, #56] @ (80031fc <HAL_RCC_GetSysClockFreq+0x98>)
80031c2: 68bb ldr r3, [r7, #8]
80031c4: fbb2 f2f3 udiv r2, r2, r3
80031c8: 687b ldr r3, [r7, #4]
80031ca: fb02 f303 mul.w r3, r2, r3
80031ce: 617b str r3, [r7, #20]
80031d0: e004 b.n 80031dc <HAL_RCC_GetSysClockFreq+0x78>
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
80031d2: 687b ldr r3, [r7, #4]
80031d4: 4a0c ldr r2, [pc, #48] @ (8003208 <HAL_RCC_GetSysClockFreq+0xa4>)
80031d6: fb02 f303 mul.w r3, r2, r3
80031da: 617b str r3, [r7, #20]
{
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
}
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
sysclockfreq = pllclk;
80031dc: 697b ldr r3, [r7, #20]
80031de: 613b str r3, [r7, #16]
break;
80031e0: e002 b.n 80031e8 <HAL_RCC_GetSysClockFreq+0x84>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
80031e2: 4b06 ldr r3, [pc, #24] @ (80031fc <HAL_RCC_GetSysClockFreq+0x98>)
80031e4: 613b str r3, [r7, #16]
break;
80031e6: bf00 nop
}
}
return sysclockfreq;
80031e8: 693b ldr r3, [r7, #16]
}
80031ea: 4618 mov r0, r3
80031ec: 371c adds r7, #28
80031ee: 46bd mov sp, r7
80031f0: f85d 7b04 ldr.w r7, [sp], #4
80031f4: 4770 bx lr
80031f6: bf00 nop
80031f8: 40021000 .word 0x40021000
80031fc: 007a1200 .word 0x007a1200
8003200: 0800328c .word 0x0800328c
8003204: 0800329c .word 0x0800329c
8003208: 003d0900 .word 0x003d0900
0800320c <memset>:
800320c: 4402 add r2, r0
800320e: 4603 mov r3, r0
8003210: 4293 cmp r3, r2
8003212: d100 bne.n 8003216 <memset+0xa>
8003214: 4770 bx lr
8003216: f803 1b01 strb.w r1, [r3], #1
800321a: e7f9 b.n 8003210 <memset+0x4>
0800321c <__libc_init_array>:
800321c: b570 push {r4, r5, r6, lr}
800321e: 4d0d ldr r5, [pc, #52] @ (8003254 <__libc_init_array+0x38>)
8003220: 4c0d ldr r4, [pc, #52] @ (8003258 <__libc_init_array+0x3c>)
8003222: 1b64 subs r4, r4, r5
8003224: 10a4 asrs r4, r4, #2
8003226: 2600 movs r6, #0
8003228: 42a6 cmp r6, r4
800322a: d109 bne.n 8003240 <__libc_init_array+0x24>
800322c: 4d0b ldr r5, [pc, #44] @ (800325c <__libc_init_array+0x40>)
800322e: 4c0c ldr r4, [pc, #48] @ (8003260 <__libc_init_array+0x44>)
8003230: f000 f818 bl 8003264 <_init>
8003234: 1b64 subs r4, r4, r5
8003236: 10a4 asrs r4, r4, #2
8003238: 2600 movs r6, #0
800323a: 42a6 cmp r6, r4
800323c: d105 bne.n 800324a <__libc_init_array+0x2e>
800323e: bd70 pop {r4, r5, r6, pc}
8003240: f855 3b04 ldr.w r3, [r5], #4
8003244: 4798 blx r3
8003246: 3601 adds r6, #1
8003248: e7ee b.n 8003228 <__libc_init_array+0xc>
800324a: f855 3b04 ldr.w r3, [r5], #4
800324e: 4798 blx r3
8003250: 3601 adds r6, #1
8003252: e7f2 b.n 800323a <__libc_init_array+0x1e>
8003254: 080032ac .word 0x080032ac
8003258: 080032ac .word 0x080032ac
800325c: 080032ac .word 0x080032ac
8003260: 080032b0 .word 0x080032b0
08003264 <_init>:
8003264: b5f8 push {r3, r4, r5, r6, r7, lr}
8003266: bf00 nop
8003268: bcf8 pop {r3, r4, r5, r6, r7}
800326a: bc08 pop {r3}
800326c: 469e mov lr, r3
800326e: 4770 bx lr
08003270 <_fini>:
8003270: b5f8 push {r3, r4, r5, r6, r7, lr}
8003272: bf00 nop
8003274: bcf8 pop {r3, r4, r5, r6, r7}
8003276: bc08 pop {r3}
8003278: 469e mov lr, r3
800327a: 4770 bx lr
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