: /** * @brief The application entry point. * @retval int */ int main(void) { 80001c8: b580 push {r7, lr} 80001ca: b092 sub sp, #72 @ 0x48 80001cc: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80001ce: f000 fc1f bl 8000a10 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80001d2: f000 f9ff bl 80005d4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80001d6: f000 fa73 bl 80006c0 MX_CAN_Init(); 80001da: f000 fa3b bl 8000654 /* USER CODE BEGIN 2 */ txHeader.IDE = CAN_ID_STD; 80001de: 4bae ldr r3, [pc, #696] @ (8000498 ) 80001e0: 2200 movs r2, #0 80001e2: 609a str r2, [r3, #8] txHeader.StdId = CAN_ID_TX; 80001e4: 4bac ldr r3, [pc, #688] @ (8000498 ) 80001e6: f44f 6284 mov.w r2, #1056 @ 0x420 80001ea: 601a str r2, [r3, #0] txHeader.RTR = CAN_RTR_DATA; 80001ec: 4baa ldr r3, [pc, #680] @ (8000498 ) 80001ee: 2200 movs r2, #0 80001f0: 60da str r2, [r3, #12] txHeader.DLC = 1; 80001f2: 4ba9 ldr r3, [pc, #676] @ (8000498 ) 80001f4: 2201 movs r2, #1 80001f6: 611a str r2, [r3, #16] if (HAL_CAN_Start(&hcan) != HAL_OK) 80001f8: 48a8 ldr r0, [pc, #672] @ (800049c ) 80001fa: f000 fea3 bl 8000f44 80001fe: 4603 mov r3, r0 8000200: 2b00 cmp r3, #0 8000202: d001 beq.n 8000208 Error_Handler(); 8000204: f000 fb06 bl 8000814 CAN_FilterTypeDef canfilterconfig; canfilterconfig.FilterActivation = CAN_FILTER_ENABLE; 8000208: 2301 movs r3, #1 800020a: 627b str r3, [r7, #36] @ 0x24 canfilterconfig.FilterBank = 0; 800020c: 2300 movs r3, #0 800020e: 61bb str r3, [r7, #24] canfilterconfig.FilterFIFOAssignment = CAN_FILTER_FIFO0; 8000210: 2300 movs r3, #0 8000212: 617b str r3, [r7, #20] canfilterconfig.FilterIdHigh = CAN_ID_RX_AMS << (16 - 11); 8000214: f44f 73a0 mov.w r3, #320 @ 0x140 8000218: 607b str r3, [r7, #4] canfilterconfig.FilterIdLow = CAN_ID_RX_R2D << (16 - 11); 800021a: f44f 4302 mov.w r3, #33280 @ 0x8200 800021e: 60bb str r3, [r7, #8] canfilterconfig.FilterMaskIdHigh = 0x7FF << (16 - 11); 8000220: f64f 73e0 movw r3, #65504 @ 0xffe0 8000224: 60fb str r3, [r7, #12] canfilterconfig.FilterMaskIdLow = 0x7FF << (16 - 11); 8000226: f64f 73e0 movw r3, #65504 @ 0xffe0 800022a: 613b str r3, [r7, #16] canfilterconfig.FilterMode = CAN_FILTERMODE_IDMASK; 800022c: 2300 movs r3, #0 800022e: 61fb str r3, [r7, #28] canfilterconfig.FilterScale = CAN_FILTERSCALE_32BIT; 8000230: 2301 movs r3, #1 8000232: 623b str r3, [r7, #32] canfilterconfig.SlaveStartFilterBank = 14; 8000234: 230e movs r3, #14 8000236: 62bb str r3, [r7, #40] @ 0x28 if (HAL_CAN_ConfigFilter(&hcan, &canfilterconfig) != HAL_OK) { 8000238: 1d3b adds r3, r7, #4 800023a: 4619 mov r1, r3 800023c: 4897 ldr r0, [pc, #604] @ (800049c ) 800023e: f000 fdb7 bl 8000db0 8000242: 4603 mov r3, r0 8000244: 2b00 cmp r3, #0 8000246: d001 beq.n 800024c Error_Handler(); 8000248: f000 fae4 bl 8000814 } if (HAL_CAN_ActivateNotification(&hcan, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) 800024c: 2102 movs r1, #2 800024e: 4893 ldr r0, [pc, #588] @ (800049c ) 8000250: f001 f8ae bl 80013b0 8000254: 4603 mov r3, r0 8000256: 2b00 cmp r3, #0 8000258: d001 beq.n 800025e Error_Handler(); 800025a: f000 fadb bl 8000814 // blink flags int blink_state = 0; 800025e: 2300 movs r3, #0 8000260: 647b str r3, [r7, #68] @ 0x44 while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ dash_tx.tson = HAL_GPIO_ReadPin(TSON_BTN_GPIO_Port, TSON_BTN_Pin); 8000262: f44f 4100 mov.w r1, #32768 @ 0x8000 8000266: 488e ldr r0, [pc, #568] @ (80004a0 ) 8000268: f001 fd92 bl 8001d90 800026c: 4603 mov r3, r0 800026e: 01db lsls r3, r3, #7 8000270: b25b sxtb r3, r3 8000272: 11db asrs r3, r3, #7 8000274: b259 sxtb r1, r3 8000276: 4a8b ldr r2, [pc, #556] @ (80004a4 ) 8000278: 7813 ldrb r3, [r2, #0] 800027a: f361 0341 bfi r3, r1, #1, #1 800027e: 7013 strb r3, [r2, #0] dash_tx.r2d = HAL_GPIO_ReadPin(R2D_BTN_GPIO_Port, R2D_BTN_Pin); 8000280: 2120 movs r1, #32 8000282: 4887 ldr r0, [pc, #540] @ (80004a0 ) 8000284: f001 fd84 bl 8001d90 8000288: 4603 mov r3, r0 800028a: 01db lsls r3, r3, #7 800028c: b25b sxtb r3, r3 800028e: 11db asrs r3, r3, #7 8000290: b259 sxtb r1, r3 8000292: 4a84 ldr r2, [pc, #528] @ (80004a4 ) 8000294: 7813 ldrb r3, [r2, #0] 8000296: f361 0300 bfi r3, r1, #0, #1 800029a: 7013 strb r3, [r2, #0] dash_tx.sdc_in = HAL_GPIO_ReadPin(SDC_In_3V3_GPIO_Port, SDC_In_3V3_Pin); 800029c: 2110 movs r1, #16 800029e: 4880 ldr r0, [pc, #512] @ (80004a0 ) 80002a0: f001 fd76 bl 8001d90 80002a4: 4603 mov r3, r0 80002a6: 01db lsls r3, r3, #7 80002a8: b25b sxtb r3, r3 80002aa: 11db asrs r3, r3, #7 80002ac: b259 sxtb r1, r3 80002ae: 4a7d ldr r2, [pc, #500] @ (80004a4 ) 80002b0: 7813 ldrb r3, [r2, #0] 80002b2: f361 03c3 bfi r3, r1, #3, #1 80002b6: 7013 strb r3, [r2, #0] dash_tx.sdc_out = HAL_GPIO_ReadPin(SDC_Out_3V3_GPIO_Port, SDC_Out_3V3_Pin); 80002b8: 2108 movs r1, #8 80002ba: 4879 ldr r0, [pc, #484] @ (80004a0 ) 80002bc: f001 fd68 bl 8001d90 80002c0: 4603 mov r3, r0 80002c2: 01db lsls r3, r3, #7 80002c4: b25b sxtb r3, r3 80002c6: 11db asrs r3, r3, #7 80002c8: b259 sxtb r1, r3 80002ca: 4a76 ldr r2, [pc, #472] @ (80004a4 ) 80002cc: 7813 ldrb r3, [r2, #0] 80002ce: f361 1304 bfi r3, r1, #4, #1 80002d2: 7013 strb r3, [r2, #0] dash_tx.racemode = HAL_GPIO_ReadPin(RMode_Out_3V3_GPIO_Port, RMode_Out_3V3_Pin); 80002d4: f44f 7180 mov.w r1, #256 @ 0x100 80002d8: 4871 ldr r0, [pc, #452] @ (80004a0 ) 80002da: f001 fd59 bl 8001d90 80002de: 4603 mov r3, r0 80002e0: 01db lsls r3, r3, #7 80002e2: b25b sxtb r3, r3 80002e4: 11db asrs r3, r3, #7 80002e6: b259 sxtb r1, r3 80002e8: 4a6e ldr r2, [pc, #440] @ (80004a4 ) 80002ea: 7813 ldrb r3, [r2, #0] 80002ec: f361 0382 bfi r3, r1, #2, #1 80002f0: 7013 strb r3, [r2, #0] if ((HAL_GetTick() - last_send_can_tick ) > 200) { 80002f2: f000 fbe7 bl 8000ac4 80002f6: 4602 mov r2, r0 80002f8: 4b6b ldr r3, [pc, #428] @ (80004a8 ) 80002fa: 681b ldr r3, [r3, #0] 80002fc: 1ad3 subs r3, r2, r3 80002fe: 2bc8 cmp r3, #200 @ 0xc8 8000300: d90f bls.n 8000322 if (HAL_CAN_AddTxMessage(&hcan, &txHeader, (uint8_t*) &dash_tx, &txMailbox) != HAL_OK) { 8000302: 4b6a ldr r3, [pc, #424] @ (80004ac ) 8000304: 4a67 ldr r2, [pc, #412] @ (80004a4 ) 8000306: 4964 ldr r1, [pc, #400] @ (8000498 ) 8000308: 4864 ldr r0, [pc, #400] @ (800049c ) 800030a: f000 fe5f bl 8000fcc 800030e: 4603 mov r3, r0 8000310: 2b00 cmp r3, #0 8000312: d001 beq.n 8000318 Error_Handler(); 8000314: f000 fa7e bl 8000814 } last_send_can_tick = HAL_GetTick(); 8000318: f000 fbd4 bl 8000ac4 800031c: 4603 mov r3, r0 800031e: 4a62 ldr r2, [pc, #392] @ (80004a8 ) 8000320: 6013 str r3, [r2, #0] } // Inverted in hardware if ((HAL_GetTick() - ams_last_tick) < 80) { 8000322: f000 fbcf bl 8000ac4 8000326: 4602 mov r2, r0 8000328: 4b61 ldr r3, [pc, #388] @ (80004b0 ) 800032a: 681b ldr r3, [r3, #0] 800032c: 1ad3 subs r3, r2, r3 800032e: 2b4f cmp r3, #79 @ 0x4f 8000330: d823 bhi.n 800037a HAL_GPIO_WritePin(IMD_LED_GPIO_Port, IMD_LED_Pin, dash_rx.imd_ok); 8000332: 4b60 ldr r3, [pc, #384] @ (80004b4 ) 8000334: 685b ldr r3, [r3, #4] 8000336: b2db uxtb r3, r3 8000338: 461a mov r2, r3 800033a: 2108 movs r1, #8 800033c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000340: f001 fd3e bl 8001dc0 HAL_GPIO_WritePin(AMS_LED_GPIO_Port, AMS_LED_Pin, dash_rx.ams_state != TS_ERROR); 8000344: 4b5b ldr r3, [pc, #364] @ (80004b4 ) 8000346: 781b ldrb r3, [r3, #0] 8000348: 2b04 cmp r3, #4 800034a: bf14 ite ne 800034c: 2301 movne r3, #1 800034e: 2300 moveq r3, #0 8000350: b2db uxtb r3, r3 8000352: 461a mov r2, r3 8000354: 2110 movs r1, #16 8000356: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 800035a: f001 fd31 bl 8001dc0 HAL_GPIO_WritePin(TSOFF_LED_GPIO_Port, TSOFF_LED_Pin, dash_rx.ams_state == TS_INACTIVE); 800035e: 4b55 ldr r3, [pc, #340] @ (80004b4 ) 8000360: 781b ldrb r3, [r3, #0] 8000362: 2b00 cmp r3, #0 8000364: bf0c ite eq 8000366: 2301 moveq r3, #1 8000368: 2300 movne r3, #0 800036a: b2db uxtb r3, r3 800036c: 461a mov r2, r3 800036e: 2120 movs r1, #32 8000370: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000374: f001 fd24 bl 8001dc0 8000378: e011 b.n 800039e } else { // Safe state: Error LEDs on, TSOFF off HAL_GPIO_WritePin(IMD_LED_GPIO_Port, IMD_LED_Pin, 0); 800037a: 2200 movs r2, #0 800037c: 2108 movs r1, #8 800037e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000382: f001 fd1d bl 8001dc0 HAL_GPIO_WritePin(AMS_LED_GPIO_Port, AMS_LED_Pin, 0); 8000386: 2200 movs r2, #0 8000388: 2110 movs r1, #16 800038a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 800038e: f001 fd17 bl 8001dc0 HAL_GPIO_WritePin(TSOFF_LED_GPIO_Port, TSOFF_LED_Pin, 0); 8000392: 2200 movs r2, #0 8000394: 2120 movs r1, #32 8000396: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 800039a: f001 fd11 bl 8001dc0 } int r = 0, g = 0, b = 0; 800039e: 2300 movs r3, #0 80003a0: 643b str r3, [r7, #64] @ 0x40 80003a2: 2300 movs r3, #0 80003a4: 63fb str r3, [r7, #60] @ 0x3c 80003a6: 2300 movs r3, #0 80003a8: 63bb str r3, [r7, #56] @ 0x38 int br = 0, bg = 0, bb = 0; 80003aa: 2300 movs r3, #0 80003ac: 637b str r3, [r7, #52] @ 0x34 80003ae: 2300 movs r3, #0 80003b0: 633b str r3, [r7, #48] @ 0x30 80003b2: 2300 movs r3, #0 80003b4: 62fb str r3, [r7, #44] @ 0x2c if (dash_rx.sdc_closed) { 80003b6: 4b3f ldr r3, [pc, #252] @ (80004b4 ) 80003b8: 689b ldr r3, [r3, #8] 80003ba: 2b00 cmp r3, #0 80003bc: d021 beq.n 8000402 switch (dash_rx.ams_state) { 80003be: 4b3d ldr r3, [pc, #244] @ (80004b4 ) 80003c0: 781b ldrb r3, [r3, #0] 80003c2: 2b03 cmp r3, #3 80003c4: d81a bhi.n 80003fc 80003c6: a201 add r2, pc, #4 @ (adr r2, 80003cc ) 80003c8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80003cc: 080003dd .word 0x080003dd 80003d0: 080003f1 .word 0x080003f1 80003d4: 080003e7 .word 0x080003e7 80003d8: 080003f7 .word 0x080003f7 case TS_INACTIVE: r = g = 1; 80003dc: 2301 movs r3, #1 80003de: 63fb str r3, [r7, #60] @ 0x3c 80003e0: 6bfb ldr r3, [r7, #60] @ 0x3c 80003e2: 643b str r3, [r7, #64] @ 0x40 break; 80003e4: e00f b.n 8000406 case TS_PRECHARGE: // Gelb blink br = bg = 1; 80003e6: 2301 movs r3, #1 80003e8: 633b str r3, [r7, #48] @ 0x30 80003ea: 6b3b ldr r3, [r7, #48] @ 0x30 80003ec: 637b str r3, [r7, #52] @ 0x34 break; 80003ee: e00a b.n 8000406 case TS_ACTIVE: g = 1; 80003f0: 2301 movs r3, #1 80003f2: 63fb str r3, [r7, #60] @ 0x3c break; 80003f4: e007 b.n 8000406 case TS_DISCHARGE: // Blau blink bb = 1; 80003f6: 2301 movs r3, #1 80003f8: 62fb str r3, [r7, #44] @ 0x2c break; 80003fa: e004 b.n 8000406 default: r = 1; 80003fc: 2301 movs r3, #1 80003fe: 643b str r3, [r7, #64] @ 0x40 break; 8000400: e001 b.n 8000406 } } else { b = 1; 8000402: 2301 movs r3, #1 8000404: 63bb str r3, [r7, #56] @ 0x38 } HAL_GPIO_WritePin(TSON_R_GPIO_Port, TSON_R_Pin, r); 8000406: 6c3b ldr r3, [r7, #64] @ 0x40 8000408: b2db uxtb r3, r3 800040a: 461a mov r2, r3 800040c: 2101 movs r1, #1 800040e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000412: f001 fcd5 bl 8001dc0 HAL_GPIO_WritePin(TSON_G_GPIO_Port, TSON_G_Pin, g); 8000416: 6bfb ldr r3, [r7, #60] @ 0x3c 8000418: b2db uxtb r3, r3 800041a: 461a mov r2, r3 800041c: 2102 movs r1, #2 800041e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000422: f001 fccd bl 8001dc0 HAL_GPIO_WritePin(TSON_B_GPIO_Port, TSON_B_Pin, b); 8000426: 6bbb ldr r3, [r7, #56] @ 0x38 8000428: b2db uxtb r3, r3 800042a: 461a mov r2, r3 800042c: 2104 movs r1, #4 800042e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000432: f001 fcc5 bl 8001dc0 if (br || bg || bb) { 8000436: 6b7b ldr r3, [r7, #52] @ 0x34 8000438: 2b00 cmp r3, #0 800043a: d105 bne.n 8000448 800043c: 6b3b ldr r3, [r7, #48] @ 0x30 800043e: 2b00 cmp r3, #0 8000440: d102 bne.n 8000448 8000442: 6afb ldr r3, [r7, #44] @ 0x2c 8000444: 2b00 cmp r3, #0 8000446: d03f beq.n 80004c8 HAL_GPIO_WritePin(TSON_R_GPIO_Port, TSON_R_Pin, br && blink_state); 8000448: 6b7b ldr r3, [r7, #52] @ 0x34 800044a: 2b00 cmp r3, #0 800044c: d004 beq.n 8000458 800044e: 6c7b ldr r3, [r7, #68] @ 0x44 8000450: 2b00 cmp r3, #0 8000452: d001 beq.n 8000458 8000454: 2301 movs r3, #1 8000456: e000 b.n 800045a 8000458: 2300 movs r3, #0 800045a: b2db uxtb r3, r3 800045c: 461a mov r2, r3 800045e: 2101 movs r1, #1 8000460: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000464: f001 fcac bl 8001dc0 HAL_GPIO_WritePin(TSON_G_GPIO_Port, TSON_G_Pin, bg && blink_state); 8000468: 6b3b ldr r3, [r7, #48] @ 0x30 800046a: 2b00 cmp r3, #0 800046c: d004 beq.n 8000478 800046e: 6c7b ldr r3, [r7, #68] @ 0x44 8000470: 2b00 cmp r3, #0 8000472: d001 beq.n 8000478 8000474: 2301 movs r3, #1 8000476: e000 b.n 800047a 8000478: 2300 movs r3, #0 800047a: b2db uxtb r3, r3 800047c: 461a mov r2, r3 800047e: 2102 movs r1, #2 8000480: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000484: f001 fc9c bl 8001dc0 HAL_GPIO_WritePin(TSON_B_GPIO_Port, TSON_B_Pin, bb && blink_state); 8000488: 6afb ldr r3, [r7, #44] @ 0x2c 800048a: 2b00 cmp r3, #0 800048c: d014 beq.n 80004b8 800048e: 6c7b ldr r3, [r7, #68] @ 0x44 8000490: 2b00 cmp r3, #0 8000492: d011 beq.n 80004b8 8000494: 2301 movs r3, #1 8000496: e010 b.n 80004ba 8000498: 20000090 .word 0x20000090 800049c: 20000028 .word 0x20000028 80004a0: 48000400 .word 0x48000400 80004a4: 2000008c .word 0x2000008c 80004a8: 200000c0 .word 0x200000c0 80004ac: 200000a8 .word 0x200000a8 80004b0: 200000bc .word 0x200000bc 80004b4: 200000ac .word 0x200000ac 80004b8: 2300 movs r3, #0 80004ba: b2db uxtb r3, r3 80004bc: 461a mov r2, r3 80004be: 2104 movs r1, #4 80004c0: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80004c4: f001 fc7c bl 8001dc0 } r = g = b = 0; 80004c8: 2300 movs r3, #0 80004ca: 63bb str r3, [r7, #56] @ 0x38 80004cc: 6bbb ldr r3, [r7, #56] @ 0x38 80004ce: 63fb str r3, [r7, #60] @ 0x3c 80004d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80004d2: 643b str r3, [r7, #64] @ 0x40 br = bg = bb = 0; 80004d4: 2300 movs r3, #0 80004d6: 62fb str r3, [r7, #44] @ 0x2c 80004d8: 6afb ldr r3, [r7, #44] @ 0x2c 80004da: 633b str r3, [r7, #48] @ 0x30 80004dc: 6b3b ldr r3, [r7, #48] @ 0x30 80004de: 637b str r3, [r7, #52] @ 0x34 if (dash_rx.ams_state == TS_ACTIVE) { 80004e0: 4b3a ldr r3, [pc, #232] @ (80005cc ) 80004e2: 781b ldrb r3, [r3, #0] 80004e4: 2b01 cmp r3, #1 80004e6: d116 bne.n 8000516 switch (dash_rx.r2d_progress) { 80004e8: 4b38 ldr r3, [pc, #224] @ (80005cc ) 80004ea: 7b1b ldrb r3, [r3, #12] 80004ec: 2b02 cmp r3, #2 80004ee: dc02 bgt.n 80004f6 80004f0: 2b00 cmp r3, #0 80004f2: da03 bge.n 80004fc 80004f4: e00a b.n 800050c 80004f6: 2b0f cmp r3, #15 80004f8: d005 beq.n 8000506 80004fa: e007 b.n 800050c case R2D_NONE: case R2D_TSMS: case R2D_TSActive: r = g = 1; 80004fc: 2301 movs r3, #1 80004fe: 63fb str r3, [r7, #60] @ 0x3c 8000500: 6bfb ldr r3, [r7, #60] @ 0x3c 8000502: 643b str r3, [r7, #64] @ 0x40 break; 8000504: e009 b.n 800051a case R2D_Success: g = 1; 8000506: 2301 movs r3, #1 8000508: 63fb str r3, [r7, #60] @ 0x3c break; 800050a: e006 b.n 800051a default: // Gelb blink bg = br = 1; 800050c: 2301 movs r3, #1 800050e: 637b str r3, [r7, #52] @ 0x34 8000510: 6b7b ldr r3, [r7, #52] @ 0x34 8000512: 633b str r3, [r7, #48] @ 0x30 break; 8000514: e001 b.n 800051a } } else { b = 1; 8000516: 2301 movs r3, #1 8000518: 63bb str r3, [r7, #56] @ 0x38 } HAL_GPIO_WritePin(R2D_R_GPIO_Port, R2D_R_Pin, r); 800051a: 6c3b ldr r3, [r7, #64] @ 0x40 800051c: b2db uxtb r3, r3 800051e: 461a mov r2, r3 8000520: 2180 movs r1, #128 @ 0x80 8000522: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000526: f001 fc4b bl 8001dc0 HAL_GPIO_WritePin(R2D_G_GPIO_Port, R2D_G_Pin, g); 800052a: 6bfb ldr r3, [r7, #60] @ 0x3c 800052c: b2db uxtb r3, r3 800052e: 461a mov r2, r3 8000530: 2101 movs r1, #1 8000532: 4827 ldr r0, [pc, #156] @ (80005d0 ) 8000534: f001 fc44 bl 8001dc0 HAL_GPIO_WritePin(R2D_B_GPIO_Port, R2D_B_Pin, b); 8000538: 6bbb ldr r3, [r7, #56] @ 0x38 800053a: b2db uxtb r3, r3 800053c: 461a mov r2, r3 800053e: 2102 movs r1, #2 8000540: 4823 ldr r0, [pc, #140] @ (80005d0 ) 8000542: f001 fc3d bl 8001dc0 if (br || bg || bb) { 8000546: 6b7b ldr r3, [r7, #52] @ 0x34 8000548: 2b00 cmp r3, #0 800054a: d105 bne.n 8000558 800054c: 6b3b ldr r3, [r7, #48] @ 0x30 800054e: 2b00 cmp r3, #0 8000550: d102 bne.n 8000558 8000552: 6afb ldr r3, [r7, #44] @ 0x2c 8000554: 2b00 cmp r3, #0 8000556: d02d beq.n 80005b4 HAL_GPIO_WritePin(R2D_R_GPIO_Port, R2D_R_Pin, br && blink_state); 8000558: 6b7b ldr r3, [r7, #52] @ 0x34 800055a: 2b00 cmp r3, #0 800055c: d004 beq.n 8000568 800055e: 6c7b ldr r3, [r7, #68] @ 0x44 8000560: 2b00 cmp r3, #0 8000562: d001 beq.n 8000568 8000564: 2301 movs r3, #1 8000566: e000 b.n 800056a 8000568: 2300 movs r3, #0 800056a: b2db uxtb r3, r3 800056c: 461a mov r2, r3 800056e: 2180 movs r1, #128 @ 0x80 8000570: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000574: f001 fc24 bl 8001dc0 HAL_GPIO_WritePin(R2D_G_GPIO_Port, R2D_G_Pin, bg && blink_state); 8000578: 6b3b ldr r3, [r7, #48] @ 0x30 800057a: 2b00 cmp r3, #0 800057c: d004 beq.n 8000588 800057e: 6c7b ldr r3, [r7, #68] @ 0x44 8000580: 2b00 cmp r3, #0 8000582: d001 beq.n 8000588 8000584: 2301 movs r3, #1 8000586: e000 b.n 800058a 8000588: 2300 movs r3, #0 800058a: b2db uxtb r3, r3 800058c: 461a mov r2, r3 800058e: 2101 movs r1, #1 8000590: 480f ldr r0, [pc, #60] @ (80005d0 ) 8000592: f001 fc15 bl 8001dc0 HAL_GPIO_WritePin(R2D_B_GPIO_Port, R2D_B_Pin, bb && blink_state); 8000596: 6afb ldr r3, [r7, #44] @ 0x2c 8000598: 2b00 cmp r3, #0 800059a: d004 beq.n 80005a6 800059c: 6c7b ldr r3, [r7, #68] @ 0x44 800059e: 2b00 cmp r3, #0 80005a0: d001 beq.n 80005a6 80005a2: 2301 movs r3, #1 80005a4: e000 b.n 80005a8 80005a6: 2300 movs r3, #0 80005a8: b2db uxtb r3, r3 80005aa: 461a mov r2, r3 80005ac: 2102 movs r1, #2 80005ae: 4808 ldr r0, [pc, #32] @ (80005d0 ) 80005b0: f001 fc06 bl 8001dc0 } blink_state = !blink_state; 80005b4: 6c7b ldr r3, [r7, #68] @ 0x44 80005b6: 2b00 cmp r3, #0 80005b8: bf0c ite eq 80005ba: 2301 moveq r3, #1 80005bc: 2300 movne r3, #0 80005be: b2db uxtb r3, r3 80005c0: 647b str r3, [r7, #68] @ 0x44 HAL_Delay(50); 80005c2: 2032 movs r0, #50 @ 0x32 80005c4: f000 fa8a bl 8000adc { 80005c8: e64b b.n 8000262 80005ca: bf00 nop 80005cc: 200000ac .word 0x200000ac 80005d0: 48000400 .word 0x48000400 080005d4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80005d4: b580 push {r7, lr} 80005d6: b090 sub sp, #64 @ 0x40 80005d8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80005da: f107 0318 add.w r3, r7, #24 80005de: 2228 movs r2, #40 @ 0x28 80005e0: 2100 movs r1, #0 80005e2: 4618 mov r0, r3 80005e4: f002 fe12 bl 800320c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80005e8: 1d3b adds r3, r7, #4 80005ea: 2200 movs r2, #0 80005ec: 601a str r2, [r3, #0] 80005ee: 605a str r2, [r3, #4] 80005f0: 609a str r2, [r3, #8] 80005f2: 60da str r2, [r3, #12] 80005f4: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 80005f6: 2302 movs r3, #2 80005f8: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 80005fa: 2301 movs r3, #1 80005fc: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 80005fe: 2310 movs r3, #16 8000600: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000602: 2302 movs r3, #2 8000604: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 8000606: 2300 movs r3, #0 8000608: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; 800060a: f44f 2300 mov.w r3, #524288 @ 0x80000 800060e: 63fb str r3, [r7, #60] @ 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000610: f107 0318 add.w r3, r7, #24 8000614: 4618 mov r0, r3 8000616: f001 fbeb bl 8001df0 800061a: 4603 mov r3, r0 800061c: 2b00 cmp r3, #0 800061e: d001 beq.n 8000624 { Error_Handler(); 8000620: f000 f8f8 bl 8000814 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000624: 230f movs r3, #15 8000626: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000628: 2302 movs r3, #2 800062a: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800062c: 2300 movs r3, #0 800062e: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8000630: 2300 movs r3, #0 8000632: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000634: 2300 movs r3, #0 8000636: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8000638: 1d3b adds r3, r7, #4 800063a: 2100 movs r1, #0 800063c: 4618 mov r0, r3 800063e: f002 fc15 bl 8002e6c 8000642: 4603 mov r3, r0 8000644: 2b00 cmp r3, #0 8000646: d001 beq.n 800064c { Error_Handler(); 8000648: f000 f8e4 bl 8000814 } } 800064c: bf00 nop 800064e: 3740 adds r7, #64 @ 0x40 8000650: 46bd mov sp, r7 8000652: bd80 pop {r7, pc} 08000654 : * @brief CAN Initialization Function * @param None * @retval None */ static void MX_CAN_Init(void) { 8000654: b580 push {r7, lr} 8000656: af00 add r7, sp, #0 /* USER CODE END CAN_Init 0 */ /* USER CODE BEGIN CAN_Init 1 */ /* USER CODE END CAN_Init 1 */ hcan.Instance = CAN; 8000658: 4b17 ldr r3, [pc, #92] @ (80006b8 ) 800065a: 4a18 ldr r2, [pc, #96] @ (80006bc ) 800065c: 601a str r2, [r3, #0] hcan.Init.Prescaler = 2; 800065e: 4b16 ldr r3, [pc, #88] @ (80006b8 ) 8000660: 2202 movs r2, #2 8000662: 605a str r2, [r3, #4] hcan.Init.Mode = CAN_MODE_NORMAL; 8000664: 4b14 ldr r3, [pc, #80] @ (80006b8 ) 8000666: 2200 movs r2, #0 8000668: 609a str r2, [r3, #8] hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 800066a: 4b13 ldr r3, [pc, #76] @ (80006b8 ) 800066c: 2200 movs r2, #0 800066e: 60da str r2, [r3, #12] hcan.Init.TimeSeg1 = CAN_BS1_13TQ; 8000670: 4b11 ldr r3, [pc, #68] @ (80006b8 ) 8000672: f44f 2240 mov.w r2, #786432 @ 0xc0000 8000676: 611a str r2, [r3, #16] hcan.Init.TimeSeg2 = CAN_BS2_2TQ; 8000678: 4b0f ldr r3, [pc, #60] @ (80006b8 ) 800067a: f44f 1280 mov.w r2, #1048576 @ 0x100000 800067e: 615a str r2, [r3, #20] hcan.Init.TimeTriggeredMode = DISABLE; 8000680: 4b0d ldr r3, [pc, #52] @ (80006b8 ) 8000682: 2200 movs r2, #0 8000684: 761a strb r2, [r3, #24] hcan.Init.AutoBusOff = DISABLE; 8000686: 4b0c ldr r3, [pc, #48] @ (80006b8 ) 8000688: 2200 movs r2, #0 800068a: 765a strb r2, [r3, #25] hcan.Init.AutoWakeUp = DISABLE; 800068c: 4b0a ldr r3, [pc, #40] @ (80006b8 ) 800068e: 2200 movs r2, #0 8000690: 769a strb r2, [r3, #26] hcan.Init.AutoRetransmission = DISABLE; 8000692: 4b09 ldr r3, [pc, #36] @ (80006b8 ) 8000694: 2200 movs r2, #0 8000696: 76da strb r2, [r3, #27] hcan.Init.ReceiveFifoLocked = DISABLE; 8000698: 4b07 ldr r3, [pc, #28] @ (80006b8 ) 800069a: 2200 movs r2, #0 800069c: 771a strb r2, [r3, #28] hcan.Init.TransmitFifoPriority = DISABLE; 800069e: 4b06 ldr r3, [pc, #24] @ (80006b8 ) 80006a0: 2200 movs r2, #0 80006a2: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan) != HAL_OK) 80006a4: 4804 ldr r0, [pc, #16] @ (80006b8 ) 80006a6: f000 fa3d bl 8000b24 80006aa: 4603 mov r3, r0 80006ac: 2b00 cmp r3, #0 80006ae: d001 beq.n 80006b4 { Error_Handler(); 80006b0: f000 f8b0 bl 8000814 } /* USER CODE BEGIN CAN_Init 2 */ /* USER CODE END CAN_Init 2 */ } 80006b4: bf00 nop 80006b6: bd80 pop {r7, pc} 80006b8: 20000028 .word 0x20000028 80006bc: 40006400 .word 0x40006400 080006c0 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80006c0: b580 push {r7, lr} 80006c2: b088 sub sp, #32 80006c4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80006c6: f107 030c add.w r3, r7, #12 80006ca: 2200 movs r2, #0 80006cc: 601a str r2, [r3, #0] 80006ce: 605a str r2, [r3, #4] 80006d0: 609a str r2, [r3, #8] 80006d2: 60da str r2, [r3, #12] 80006d4: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80006d6: 4b28 ldr r3, [pc, #160] @ (8000778 ) 80006d8: 695b ldr r3, [r3, #20] 80006da: 4a27 ldr r2, [pc, #156] @ (8000778 ) 80006dc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80006e0: 6153 str r3, [r2, #20] 80006e2: 4b25 ldr r3, [pc, #148] @ (8000778 ) 80006e4: 695b ldr r3, [r3, #20] 80006e6: f403 3300 and.w r3, r3, #131072 @ 0x20000 80006ea: 60bb str r3, [r7, #8] 80006ec: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 80006ee: 4b22 ldr r3, [pc, #136] @ (8000778 ) 80006f0: 695b ldr r3, [r3, #20] 80006f2: 4a21 ldr r2, [pc, #132] @ (8000778 ) 80006f4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80006f8: 6153 str r3, [r2, #20] 80006fa: 4b1f ldr r3, [pc, #124] @ (8000778 ) 80006fc: 695b ldr r3, [r3, #20] 80006fe: f403 2380 and.w r3, r3, #262144 @ 0x40000 8000702: 607b str r3, [r7, #4] 8000704: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, TSON_R_Pin|TSON_G_Pin|TSON_B_Pin|IMD_LED_Pin 8000706: 2200 movs r2, #0 8000708: 21bf movs r1, #191 @ 0xbf 800070a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 800070e: f001 fb57 bl 8001dc0 |AMS_LED_Pin|TSOFF_LED_Pin|R2D_R_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, R2D_G_Pin|R2D_B_Pin, GPIO_PIN_RESET); 8000712: 2200 movs r2, #0 8000714: 2103 movs r1, #3 8000716: 4819 ldr r0, [pc, #100] @ (800077c ) 8000718: f001 fb52 bl 8001dc0 /*Configure GPIO pins : TSON_R_Pin TSON_G_Pin TSON_B_Pin IMD_LED_Pin AMS_LED_Pin TSOFF_LED_Pin R2D_R_Pin */ GPIO_InitStruct.Pin = TSON_R_Pin|TSON_G_Pin|TSON_B_Pin|IMD_LED_Pin 800071c: 23bf movs r3, #191 @ 0xbf 800071e: 60fb str r3, [r7, #12] |AMS_LED_Pin|TSOFF_LED_Pin|R2D_R_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000720: 2301 movs r3, #1 8000722: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000724: 2300 movs r3, #0 8000726: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000728: 2300 movs r3, #0 800072a: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800072c: f107 030c add.w r3, r7, #12 8000730: 4619 mov r1, r3 8000732: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000736: f001 f9b1 bl 8001a9c /*Configure GPIO pins : R2D_G_Pin R2D_B_Pin */ GPIO_InitStruct.Pin = R2D_G_Pin|R2D_B_Pin; 800073a: 2303 movs r3, #3 800073c: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800073e: 2301 movs r3, #1 8000740: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000742: 2300 movs r3, #0 8000744: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000746: 2300 movs r3, #0 8000748: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800074a: f107 030c add.w r3, r7, #12 800074e: 4619 mov r1, r3 8000750: 480a ldr r0, [pc, #40] @ (800077c ) 8000752: f001 f9a3 bl 8001a9c /*Configure GPIO pins : TSON_BTN_Pin SDC_Out_3V3_Pin SDC_In_3V3_Pin R2D_BTN_Pin RMode_Out_3V3_Pin */ GPIO_InitStruct.Pin = TSON_BTN_Pin|SDC_Out_3V3_Pin|SDC_In_3V3_Pin|R2D_BTN_Pin 8000756: f248 1338 movw r3, #33080 @ 0x8138 800075a: 60fb str r3, [r7, #12] |RMode_Out_3V3_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800075c: 2300 movs r3, #0 800075e: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000760: 2300 movs r3, #0 8000762: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000764: f107 030c add.w r3, r7, #12 8000768: 4619 mov r1, r3 800076a: 4804 ldr r0, [pc, #16] @ (800077c ) 800076c: f001 f996 bl 8001a9c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000770: bf00 nop 8000772: 3720 adds r7, #32 8000774: 46bd mov sp, r7 8000776: bd80 pop {r7, pc} 8000778: 40021000 .word 0x40021000 800077c: 48000400 .word 0x48000400 08000780 : /* USER CODE BEGIN 4 */ // CAN RX interrupt handler void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 8000780: b580 push {r7, lr} 8000782: b08c sub sp, #48 @ 0x30 8000784: af00 add r7, sp, #0 8000786: 6078 str r0, [r7, #4] CAN_RxHeaderTypeDef rxHeader; uint8_t rxData[8]; // Read frame from HW into buffer if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &rxHeader, rxData) != HAL_OK) 8000788: f107 0308 add.w r3, r7, #8 800078c: f107 0210 add.w r2, r7, #16 8000790: 2100 movs r1, #0 8000792: 6878 ldr r0, [r7, #4] 8000794: f000 fcea bl 800116c 8000798: 4603 mov r3, r0 800079a: 2b00 cmp r3, #0 800079c: d001 beq.n 80007a2 Error_Handler(); 800079e: f000 f839 bl 8000814 // Discard if it's not for us (shouldn't happen thanks to filter, but just to be sure) if (rxHeader.StdId == CAN_ID_RX_AMS) { 80007a2: 693b ldr r3, [r7, #16] 80007a4: 2b0a cmp r3, #10 80007a6: d11f bne.n 80007e8 uint8_t ams_info = rxData[0]; 80007a8: 7a3b ldrb r3, [r7, #8] 80007aa: f887 302f strb.w r3, [r7, #47] @ 0x2f uint8_t imd_info = rxData[6]; 80007ae: 7bbb ldrb r3, [r7, #14] 80007b0: f887 302e strb.w r3, [r7, #46] @ 0x2e dash_rx.ams_state = ams_info & 0b01111111; 80007b4: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80007b8: f003 037f and.w r3, r3, #127 @ 0x7f 80007bc: b2da uxtb r2, r3 80007be: 4b13 ldr r3, [pc, #76] @ (800080c ) 80007c0: 701a strb r2, [r3, #0] dash_rx.sdc_closed = ams_info >> 7; 80007c2: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80007c6: 09db lsrs r3, r3, #7 80007c8: b2db uxtb r3, r3 80007ca: 461a mov r2, r3 80007cc: 4b0f ldr r3, [pc, #60] @ (800080c ) 80007ce: 609a str r2, [r3, #8] dash_rx.imd_ok = imd_info >> 7; 80007d0: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 80007d4: 09db lsrs r3, r3, #7 80007d6: b2db uxtb r3, r3 80007d8: 461a mov r2, r3 80007da: 4b0c ldr r3, [pc, #48] @ (800080c ) 80007dc: 605a str r2, [r3, #4] ams_last_tick = HAL_GetTick(); 80007de: f000 f971 bl 8000ac4 80007e2: 4603 mov r3, r0 80007e4: 4a0a ldr r2, [pc, #40] @ (8000810 ) 80007e6: 6013 str r3, [r2, #0] } if (rxHeader.StdId == CAN_ID_RX_R2D) { 80007e8: 693b ldr r3, [r7, #16] 80007ea: f5b3 6f82 cmp.w r3, #1040 @ 0x410 80007ee: d109 bne.n 8000804 uint8_t r2d_info = rxData[1]; 80007f0: 7a7b ldrb r3, [r7, #9] 80007f2: f887 302d strb.w r3, [r7, #45] @ 0x2d dash_rx.r2d_progress = r2d_info & 0b00001111; 80007f6: f897 302d ldrb.w r3, [r7, #45] @ 0x2d 80007fa: f003 030f and.w r3, r3, #15 80007fe: b2da uxtb r2, r3 8000800: 4b02 ldr r3, [pc, #8] @ (800080c ) 8000802: 731a strb r2, [r3, #12] } } 8000804: bf00 nop 8000806: 3730 adds r7, #48 @ 0x30 8000808: 46bd mov sp, r7 800080a: bd80 pop {r7, pc} 800080c: 200000ac .word 0x200000ac 8000810: 200000bc .word 0x200000bc 08000814 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000814: b480 push {r7} 8000816: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000818: b672 cpsid i } 800081a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800081c: bf00 nop 800081e: e7fd b.n 800081c 08000820 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000820: b480 push {r7} 8000822: b083 sub sp, #12 8000824: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000826: 4b0f ldr r3, [pc, #60] @ (8000864 ) 8000828: 699b ldr r3, [r3, #24] 800082a: 4a0e ldr r2, [pc, #56] @ (8000864 ) 800082c: f043 0301 orr.w r3, r3, #1 8000830: 6193 str r3, [r2, #24] 8000832: 4b0c ldr r3, [pc, #48] @ (8000864 ) 8000834: 699b ldr r3, [r3, #24] 8000836: f003 0301 and.w r3, r3, #1 800083a: 607b str r3, [r7, #4] 800083c: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 800083e: 4b09 ldr r3, [pc, #36] @ (8000864 ) 8000840: 69db ldr r3, [r3, #28] 8000842: 4a08 ldr r2, [pc, #32] @ (8000864 ) 8000844: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000848: 61d3 str r3, [r2, #28] 800084a: 4b06 ldr r3, [pc, #24] @ (8000864 ) 800084c: 69db ldr r3, [r3, #28] 800084e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000852: 603b str r3, [r7, #0] 8000854: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000856: bf00 nop 8000858: 370c adds r7, #12 800085a: 46bd mov sp, r7 800085c: f85d 7b04 ldr.w r7, [sp], #4 8000860: 4770 bx lr 8000862: bf00 nop 8000864: 40021000 .word 0x40021000 08000868 : * This function configures the hardware resources used in this example * @param hcan: CAN handle pointer * @retval None */ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) { 8000868: b580 push {r7, lr} 800086a: b08a sub sp, #40 @ 0x28 800086c: af00 add r7, sp, #0 800086e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000870: f107 0314 add.w r3, r7, #20 8000874: 2200 movs r2, #0 8000876: 601a str r2, [r3, #0] 8000878: 605a str r2, [r3, #4] 800087a: 609a str r2, [r3, #8] 800087c: 60da str r2, [r3, #12] 800087e: 611a str r2, [r3, #16] if(hcan->Instance==CAN) 8000880: 687b ldr r3, [r7, #4] 8000882: 681b ldr r3, [r3, #0] 8000884: 4a20 ldr r2, [pc, #128] @ (8000908 ) 8000886: 4293 cmp r3, r2 8000888: d139 bne.n 80008fe { /* USER CODE BEGIN CAN_MspInit 0 */ /* USER CODE END CAN_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CAN1_CLK_ENABLE(); 800088a: 4b20 ldr r3, [pc, #128] @ (800090c ) 800088c: 69db ldr r3, [r3, #28] 800088e: 4a1f ldr r2, [pc, #124] @ (800090c ) 8000890: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8000894: 61d3 str r3, [r2, #28] 8000896: 4b1d ldr r3, [pc, #116] @ (800090c ) 8000898: 69db ldr r3, [r3, #28] 800089a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800089e: 613b str r3, [r7, #16] 80008a0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80008a2: 4b1a ldr r3, [pc, #104] @ (800090c ) 80008a4: 695b ldr r3, [r3, #20] 80008a6: 4a19 ldr r2, [pc, #100] @ (800090c ) 80008a8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80008ac: 6153 str r3, [r2, #20] 80008ae: 4b17 ldr r3, [pc, #92] @ (800090c ) 80008b0: 695b ldr r3, [r3, #20] 80008b2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80008b6: 60fb str r3, [r7, #12] 80008b8: 68fb ldr r3, [r7, #12] /**CAN GPIO Configuration PA11 ------> CAN_RX PA12 ------> CAN_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 80008ba: f44f 53c0 mov.w r3, #6144 @ 0x1800 80008be: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80008c0: 2302 movs r3, #2 80008c2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80008c4: 2300 movs r3, #0 80008c6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80008c8: 2303 movs r3, #3 80008ca: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF9_CAN; 80008cc: 2309 movs r3, #9 80008ce: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80008d0: f107 0314 add.w r3, r7, #20 80008d4: 4619 mov r1, r3 80008d6: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80008da: f001 f8df bl 8001a9c /* CAN interrupt Init */ HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); 80008de: 2200 movs r2, #0 80008e0: 2100 movs r1, #0 80008e2: 2014 movs r0, #20 80008e4: f001 f8a3 bl 8001a2e HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); 80008e8: 2014 movs r0, #20 80008ea: f001 f8bc bl 8001a66 HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0); 80008ee: 2200 movs r2, #0 80008f0: 2100 movs r1, #0 80008f2: 2015 movs r0, #21 80008f4: f001 f89b bl 8001a2e HAL_NVIC_EnableIRQ(CAN_RX1_IRQn); 80008f8: 2015 movs r0, #21 80008fa: f001 f8b4 bl 8001a66 /* USER CODE END CAN_MspInit 1 */ } } 80008fe: bf00 nop 8000900: 3728 adds r7, #40 @ 0x28 8000902: 46bd mov sp, r7 8000904: bd80 pop {r7, pc} 8000906: bf00 nop 8000908: 40006400 .word 0x40006400 800090c: 40021000 .word 0x40021000 08000910 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000910: b480 push {r7} 8000912: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000914: bf00 nop 8000916: e7fd b.n 8000914 08000918 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000918: b480 push {r7} 800091a: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800091c: bf00 nop 800091e: e7fd b.n 800091c 08000920 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000920: b480 push {r7} 8000922: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000924: bf00 nop 8000926: e7fd b.n 8000924 08000928 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000928: b480 push {r7} 800092a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800092c: bf00 nop 800092e: e7fd b.n 800092c 08000930 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000930: b480 push {r7} 8000932: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000934: bf00 nop 8000936: e7fd b.n 8000934 08000938 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000938: b480 push {r7} 800093a: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800093c: bf00 nop 800093e: 46bd mov sp, r7 8000940: f85d 7b04 ldr.w r7, [sp], #4 8000944: 4770 bx lr 08000946 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000946: b480 push {r7} 8000948: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800094a: bf00 nop 800094c: 46bd mov sp, r7 800094e: f85d 7b04 ldr.w r7, [sp], #4 8000952: 4770 bx lr 08000954 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000954: b480 push {r7} 8000956: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000958: bf00 nop 800095a: 46bd mov sp, r7 800095c: f85d 7b04 ldr.w r7, [sp], #4 8000960: 4770 bx lr 08000962 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000962: b580 push {r7, lr} 8000964: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000966: f000 f899 bl 8000a9c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800096a: bf00 nop 800096c: bd80 pop {r7, pc} ... 08000970 : /** * @brief This function handles USB low priority or CAN_RX0 interrupts. */ void USB_LP_CAN_RX0_IRQHandler(void) { 8000970: b580 push {r7, lr} 8000972: af00 add r7, sp, #0 /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); 8000974: 4802 ldr r0, [pc, #8] @ (8000980 ) 8000976: f000 fd41 bl 80013fc /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ } 800097a: bf00 nop 800097c: bd80 pop {r7, pc} 800097e: bf00 nop 8000980: 20000028 .word 0x20000028 08000984 : /** * @brief This function handles CAN RX1 interrupt. */ void CAN_RX1_IRQHandler(void) { 8000984: b580 push {r7, lr} 8000986: af00 add r7, sp, #0 /* USER CODE BEGIN CAN_RX1_IRQn 0 */ /* USER CODE END CAN_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); 8000988: 4802 ldr r0, [pc, #8] @ (8000994 ) 800098a: f000 fd37 bl 80013fc /* USER CODE BEGIN CAN_RX1_IRQn 1 */ /* USER CODE END CAN_RX1_IRQn 1 */ } 800098e: bf00 nop 8000990: bd80 pop {r7, pc} 8000992: bf00 nop 8000994: 20000028 .word 0x20000028 08000998 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 8000998: b480 push {r7} 800099a: af00 add r7, sp, #0 /* FPU settings --------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 800099c: 4b06 ldr r3, [pc, #24] @ (80009b8 ) 800099e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80009a2: 4a05 ldr r2, [pc, #20] @ (80009b8 ) 80009a4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80009a8: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 80009ac: bf00 nop 80009ae: 46bd mov sp, r7 80009b0: f85d 7b04 ldr.w r7, [sp], #4 80009b4: 4770 bx lr 80009b6: bf00 nop 80009b8: e000ed00 .word 0xe000ed00 080009bc : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ 80009bc: f8df d034 ldr.w sp, [pc, #52] @ 80009f4 /* Call the clock system initialization function.*/ bl SystemInit 80009c0: f7ff ffea bl 8000998 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80009c4: 480c ldr r0, [pc, #48] @ (80009f8 ) ldr r1, =_edata 80009c6: 490d ldr r1, [pc, #52] @ (80009fc ) ldr r2, =_sidata 80009c8: 4a0d ldr r2, [pc, #52] @ (8000a00 ) movs r3, #0 80009ca: 2300 movs r3, #0 b LoopCopyDataInit 80009cc: e002 b.n 80009d4 080009ce : CopyDataInit: ldr r4, [r2, r3] 80009ce: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80009d0: 50c4 str r4, [r0, r3] adds r3, r3, #4 80009d2: 3304 adds r3, #4 080009d4 : LoopCopyDataInit: adds r4, r0, r3 80009d4: 18c4 adds r4, r0, r3 cmp r4, r1 80009d6: 428c cmp r4, r1 bcc CopyDataInit 80009d8: d3f9 bcc.n 80009ce /* Zero fill the bss segment. */ ldr r2, =_sbss 80009da: 4a0a ldr r2, [pc, #40] @ (8000a04 ) ldr r4, =_ebss 80009dc: 4c0a ldr r4, [pc, #40] @ (8000a08 ) movs r3, #0 80009de: 2300 movs r3, #0 b LoopFillZerobss 80009e0: e001 b.n 80009e6 080009e2 : FillZerobss: str r3, [r2] 80009e2: 6013 str r3, [r2, #0] adds r2, r2, #4 80009e4: 3204 adds r2, #4 080009e6 : LoopFillZerobss: cmp r2, r4 80009e6: 42a2 cmp r2, r4 bcc FillZerobss 80009e8: d3fb bcc.n 80009e2 /* Call static constructors */ bl __libc_init_array 80009ea: f002 fc17 bl 800321c <__libc_init_array> /* Call the application's entry point.*/ bl main 80009ee: f7ff fbeb bl 80001c8

080009f2 : LoopForever: b LoopForever 80009f2: e7fe b.n 80009f2 ldr sp, =_estack /* Atollic update: set stack pointer */ 80009f4: 20008000 .word 0x20008000 ldr r0, =_sdata 80009f8: 20000000 .word 0x20000000 ldr r1, =_edata 80009fc: 2000000c .word 0x2000000c ldr r2, =_sidata 8000a00: 080032b4 .word 0x080032b4 ldr r2, =_sbss 8000a04: 2000000c .word 0x2000000c ldr r4, =_ebss 8000a08: 200000c8 .word 0x200000c8 08000a0c : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000a0c: e7fe b.n 8000a0c ... 08000a10 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000a10: b580 push {r7, lr} 8000a12: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000a14: 4b08 ldr r3, [pc, #32] @ (8000a38 ) 8000a16: 681b ldr r3, [r3, #0] 8000a18: 4a07 ldr r2, [pc, #28] @ (8000a38 ) 8000a1a: f043 0310 orr.w r3, r3, #16 8000a1e: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000a20: 2003 movs r0, #3 8000a22: f000 fff9 bl 8001a18 /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000a26: 200f movs r0, #15 8000a28: f000 f808 bl 8000a3c /* Init the low level hardware */ HAL_MspInit(); 8000a2c: f7ff fef8 bl 8000820 /* Return function status */ return HAL_OK; 8000a30: 2300 movs r3, #0 } 8000a32: 4618 mov r0, r3 8000a34: bd80 pop {r7, pc} 8000a36: bf00 nop 8000a38: 40022000 .word 0x40022000 08000a3c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000a3c: b580 push {r7, lr} 8000a3e: b082 sub sp, #8 8000a40: af00 add r7, sp, #0 8000a42: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000a44: 4b12 ldr r3, [pc, #72] @ (8000a90 ) 8000a46: 681a ldr r2, [r3, #0] 8000a48: 4b12 ldr r3, [pc, #72] @ (8000a94 ) 8000a4a: 781b ldrb r3, [r3, #0] 8000a4c: 4619 mov r1, r3 8000a4e: f44f 737a mov.w r3, #1000 @ 0x3e8 8000a52: fbb3 f3f1 udiv r3, r3, r1 8000a56: fbb2 f3f3 udiv r3, r2, r3 8000a5a: 4618 mov r0, r3 8000a5c: f001 f811 bl 8001a82 8000a60: 4603 mov r3, r0 8000a62: 2b00 cmp r3, #0 8000a64: d001 beq.n 8000a6a { return HAL_ERROR; 8000a66: 2301 movs r3, #1 8000a68: e00e b.n 8000a88 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000a6a: 687b ldr r3, [r7, #4] 8000a6c: 2b0f cmp r3, #15 8000a6e: d80a bhi.n 8000a86 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000a70: 2200 movs r2, #0 8000a72: 6879 ldr r1, [r7, #4] 8000a74: f04f 30ff mov.w r0, #4294967295 8000a78: f000 ffd9 bl 8001a2e uwTickPrio = TickPriority; 8000a7c: 4a06 ldr r2, [pc, #24] @ (8000a98 ) 8000a7e: 687b ldr r3, [r7, #4] 8000a80: 6013 str r3, [r2, #0] else { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000a82: 2300 movs r3, #0 8000a84: e000 b.n 8000a88 return HAL_ERROR; 8000a86: 2301 movs r3, #1 } 8000a88: 4618 mov r0, r3 8000a8a: 3708 adds r7, #8 8000a8c: 46bd mov sp, r7 8000a8e: bd80 pop {r7, pc} 8000a90: 20000000 .word 0x20000000 8000a94: 20000008 .word 0x20000008 8000a98: 20000004 .word 0x20000004 08000a9c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000a9c: b480 push {r7} 8000a9e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000aa0: 4b06 ldr r3, [pc, #24] @ (8000abc ) 8000aa2: 781b ldrb r3, [r3, #0] 8000aa4: 461a mov r2, r3 8000aa6: 4b06 ldr r3, [pc, #24] @ (8000ac0 ) 8000aa8: 681b ldr r3, [r3, #0] 8000aaa: 4413 add r3, r2 8000aac: 4a04 ldr r2, [pc, #16] @ (8000ac0 ) 8000aae: 6013 str r3, [r2, #0] } 8000ab0: bf00 nop 8000ab2: 46bd mov sp, r7 8000ab4: f85d 7b04 ldr.w r7, [sp], #4 8000ab8: 4770 bx lr 8000aba: bf00 nop 8000abc: 20000008 .word 0x20000008 8000ac0: 200000c4 .word 0x200000c4 08000ac4 : * @note The function is declared as __Weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000ac4: b480 push {r7} 8000ac6: af00 add r7, sp, #0 return uwTick; 8000ac8: 4b03 ldr r3, [pc, #12] @ (8000ad8 ) 8000aca: 681b ldr r3, [r3, #0] } 8000acc: 4618 mov r0, r3 8000ace: 46bd mov sp, r7 8000ad0: f85d 7b04 ldr.w r7, [sp], #4 8000ad4: 4770 bx lr 8000ad6: bf00 nop 8000ad8: 200000c4 .word 0x200000c4 08000adc : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000adc: b580 push {r7, lr} 8000ade: b084 sub sp, #16 8000ae0: af00 add r7, sp, #0 8000ae2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000ae4: f7ff ffee bl 8000ac4 8000ae8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8000aea: 687b ldr r3, [r7, #4] 8000aec: 60fb str r3, [r7, #12] /* Add freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8000aee: 68fb ldr r3, [r7, #12] 8000af0: f1b3 3fff cmp.w r3, #4294967295 8000af4: d005 beq.n 8000b02 { wait += (uint32_t)(uwTickFreq); 8000af6: 4b0a ldr r3, [pc, #40] @ (8000b20 ) 8000af8: 781b ldrb r3, [r3, #0] 8000afa: 461a mov r2, r3 8000afc: 68fb ldr r3, [r7, #12] 8000afe: 4413 add r3, r2 8000b00: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8000b02: bf00 nop 8000b04: f7ff ffde bl 8000ac4 8000b08: 4602 mov r2, r0 8000b0a: 68bb ldr r3, [r7, #8] 8000b0c: 1ad3 subs r3, r2, r3 8000b0e: 68fa ldr r2, [r7, #12] 8000b10: 429a cmp r2, r3 8000b12: d8f7 bhi.n 8000b04 { } } 8000b14: bf00 nop 8000b16: bf00 nop 8000b18: 3710 adds r7, #16 8000b1a: 46bd mov sp, r7 8000b1c: bd80 pop {r7, pc} 8000b1e: bf00 nop 8000b20: 20000008 .word 0x20000008 08000b24 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 8000b24: b580 push {r7, lr} 8000b26: b084 sub sp, #16 8000b28: af00 add r7, sp, #0 8000b2a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 8000b2c: 687b ldr r3, [r7, #4] 8000b2e: 2b00 cmp r3, #0 8000b30: d101 bne.n 8000b36 { return HAL_ERROR; 8000b32: 2301 movs r3, #1 8000b34: e11c b.n 8000d70 assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 if (hcan->State == HAL_CAN_STATE_RESET) 8000b36: 687b ldr r3, [r7, #4] 8000b38: f893 3020 ldrb.w r3, [r3, #32] 8000b3c: b2db uxtb r3, r3 8000b3e: 2b00 cmp r3, #0 8000b40: d131 bne.n 8000ba6 { /* Reset callbacks to legacy functions */ hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ 8000b42: 687b ldr r3, [r7, #4] 8000b44: 4a8c ldr r2, [pc, #560] @ (8000d78 ) 8000b46: 641a str r2, [r3, #64] @ 0x40 hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ 8000b48: 687b ldr r3, [r7, #4] 8000b4a: 4a8c ldr r2, [pc, #560] @ (8000d7c ) 8000b4c: 645a str r2, [r3, #68] @ 0x44 hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ 8000b4e: 687b ldr r3, [r7, #4] 8000b50: 4a8b ldr r2, [pc, #556] @ (8000d80 ) 8000b52: 649a str r2, [r3, #72] @ 0x48 hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ 8000b54: 687b ldr r3, [r7, #4] 8000b56: 4a8b ldr r2, [pc, #556] @ (8000d84 ) 8000b58: 64da str r2, [r3, #76] @ 0x4c hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ 8000b5a: 687b ldr r3, [r7, #4] 8000b5c: 4a8a ldr r2, [pc, #552] @ (8000d88 ) 8000b5e: 629a str r2, [r3, #40] @ 0x28 hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ 8000b60: 687b ldr r3, [r7, #4] 8000b62: 4a8a ldr r2, [pc, #552] @ (8000d8c ) 8000b64: 62da str r2, [r3, #44] @ 0x2c hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ 8000b66: 687b ldr r3, [r7, #4] 8000b68: 4a89 ldr r2, [pc, #548] @ (8000d90 ) 8000b6a: 631a str r2, [r3, #48] @ 0x30 hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ 8000b6c: 687b ldr r3, [r7, #4] 8000b6e: 4a89 ldr r2, [pc, #548] @ (8000d94 ) 8000b70: 635a str r2, [r3, #52] @ 0x34 hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ 8000b72: 687b ldr r3, [r7, #4] 8000b74: 4a88 ldr r2, [pc, #544] @ (8000d98 ) 8000b76: 639a str r2, [r3, #56] @ 0x38 hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ 8000b78: 687b ldr r3, [r7, #4] 8000b7a: 4a88 ldr r2, [pc, #544] @ (8000d9c ) 8000b7c: 63da str r2, [r3, #60] @ 0x3c hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ 8000b7e: 687b ldr r3, [r7, #4] 8000b80: 4a87 ldr r2, [pc, #540] @ (8000da0 ) 8000b82: 651a str r2, [r3, #80] @ 0x50 hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ 8000b84: 687b ldr r3, [r7, #4] 8000b86: 4a87 ldr r2, [pc, #540] @ (8000da4 ) 8000b88: 655a str r2, [r3, #84] @ 0x54 hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ 8000b8a: 687b ldr r3, [r7, #4] 8000b8c: 4a86 ldr r2, [pc, #536] @ (8000da8 ) 8000b8e: 659a str r2, [r3, #88] @ 0x58 if (hcan->MspInitCallback == NULL) 8000b90: 687b ldr r3, [r7, #4] 8000b92: 6ddb ldr r3, [r3, #92] @ 0x5c 8000b94: 2b00 cmp r3, #0 8000b96: d102 bne.n 8000b9e { hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ 8000b98: 687b ldr r3, [r7, #4] 8000b9a: 4a84 ldr r2, [pc, #528] @ (8000dac ) 8000b9c: 65da str r2, [r3, #92] @ 0x5c } /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); 8000b9e: 687b ldr r3, [r7, #4] 8000ba0: 6ddb ldr r3, [r3, #92] @ 0x5c 8000ba2: 6878 ldr r0, [r7, #4] 8000ba4: 4798 blx r3 HAL_CAN_MspInit(hcan); } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8000ba6: 687b ldr r3, [r7, #4] 8000ba8: 681b ldr r3, [r3, #0] 8000baa: 681a ldr r2, [r3, #0] 8000bac: 687b ldr r3, [r7, #4] 8000bae: 681b ldr r3, [r3, #0] 8000bb0: f042 0201 orr.w r2, r2, #1 8000bb4: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8000bb6: f7ff ff85 bl 8000ac4 8000bba: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8000bbc: e012 b.n 8000be4 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8000bbe: f7ff ff81 bl 8000ac4 8000bc2: 4602 mov r2, r0 8000bc4: 68fb ldr r3, [r7, #12] 8000bc6: 1ad3 subs r3, r2, r3 8000bc8: 2b0a cmp r3, #10 8000bca: d90b bls.n 8000be4 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8000bcc: 687b ldr r3, [r7, #4] 8000bce: 6a5b ldr r3, [r3, #36] @ 0x24 8000bd0: f443 3200 orr.w r2, r3, #131072 @ 0x20000 8000bd4: 687b ldr r3, [r7, #4] 8000bd6: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8000bd8: 687b ldr r3, [r7, #4] 8000bda: 2205 movs r2, #5 8000bdc: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8000be0: 2301 movs r3, #1 8000be2: e0c5 b.n 8000d70 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8000be4: 687b ldr r3, [r7, #4] 8000be6: 681b ldr r3, [r3, #0] 8000be8: 685b ldr r3, [r3, #4] 8000bea: f003 0301 and.w r3, r3, #1 8000bee: 2b00 cmp r3, #0 8000bf0: d0e5 beq.n 8000bbe } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 8000bf2: 687b ldr r3, [r7, #4] 8000bf4: 681b ldr r3, [r3, #0] 8000bf6: 681a ldr r2, [r3, #0] 8000bf8: 687b ldr r3, [r7, #4] 8000bfa: 681b ldr r3, [r3, #0] 8000bfc: f022 0202 bic.w r2, r2, #2 8000c00: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8000c02: f7ff ff5f bl 8000ac4 8000c06: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 8000c08: e012 b.n 8000c30 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8000c0a: f7ff ff5b bl 8000ac4 8000c0e: 4602 mov r2, r0 8000c10: 68fb ldr r3, [r7, #12] 8000c12: 1ad3 subs r3, r2, r3 8000c14: 2b0a cmp r3, #10 8000c16: d90b bls.n 8000c30 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8000c18: 687b ldr r3, [r7, #4] 8000c1a: 6a5b ldr r3, [r3, #36] @ 0x24 8000c1c: f443 3200 orr.w r2, r3, #131072 @ 0x20000 8000c20: 687b ldr r3, [r7, #4] 8000c22: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8000c24: 687b ldr r3, [r7, #4] 8000c26: 2205 movs r2, #5 8000c28: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8000c2c: 2301 movs r3, #1 8000c2e: e09f b.n 8000d70 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 8000c30: 687b ldr r3, [r7, #4] 8000c32: 681b ldr r3, [r3, #0] 8000c34: 685b ldr r3, [r3, #4] 8000c36: f003 0302 and.w r3, r3, #2 8000c3a: 2b00 cmp r3, #0 8000c3c: d1e5 bne.n 8000c0a } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 8000c3e: 687b ldr r3, [r7, #4] 8000c40: 7e1b ldrb r3, [r3, #24] 8000c42: 2b01 cmp r3, #1 8000c44: d108 bne.n 8000c58 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 8000c46: 687b ldr r3, [r7, #4] 8000c48: 681b ldr r3, [r3, #0] 8000c4a: 681a ldr r2, [r3, #0] 8000c4c: 687b ldr r3, [r7, #4] 8000c4e: 681b ldr r3, [r3, #0] 8000c50: f042 0280 orr.w r2, r2, #128 @ 0x80 8000c54: 601a str r2, [r3, #0] 8000c56: e007 b.n 8000c68 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 8000c58: 687b ldr r3, [r7, #4] 8000c5a: 681b ldr r3, [r3, #0] 8000c5c: 681a ldr r2, [r3, #0] 8000c5e: 687b ldr r3, [r7, #4] 8000c60: 681b ldr r3, [r3, #0] 8000c62: f022 0280 bic.w r2, r2, #128 @ 0x80 8000c66: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 8000c68: 687b ldr r3, [r7, #4] 8000c6a: 7e5b ldrb r3, [r3, #25] 8000c6c: 2b01 cmp r3, #1 8000c6e: d108 bne.n 8000c82 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8000c70: 687b ldr r3, [r7, #4] 8000c72: 681b ldr r3, [r3, #0] 8000c74: 681a ldr r2, [r3, #0] 8000c76: 687b ldr r3, [r7, #4] 8000c78: 681b ldr r3, [r3, #0] 8000c7a: f042 0240 orr.w r2, r2, #64 @ 0x40 8000c7e: 601a str r2, [r3, #0] 8000c80: e007 b.n 8000c92 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 8000c82: 687b ldr r3, [r7, #4] 8000c84: 681b ldr r3, [r3, #0] 8000c86: 681a ldr r2, [r3, #0] 8000c88: 687b ldr r3, [r7, #4] 8000c8a: 681b ldr r3, [r3, #0] 8000c8c: f022 0240 bic.w r2, r2, #64 @ 0x40 8000c90: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 8000c92: 687b ldr r3, [r7, #4] 8000c94: 7e9b ldrb r3, [r3, #26] 8000c96: 2b01 cmp r3, #1 8000c98: d108 bne.n 8000cac { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 8000c9a: 687b ldr r3, [r7, #4] 8000c9c: 681b ldr r3, [r3, #0] 8000c9e: 681a ldr r2, [r3, #0] 8000ca0: 687b ldr r3, [r7, #4] 8000ca2: 681b ldr r3, [r3, #0] 8000ca4: f042 0220 orr.w r2, r2, #32 8000ca8: 601a str r2, [r3, #0] 8000caa: e007 b.n 8000cbc } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 8000cac: 687b ldr r3, [r7, #4] 8000cae: 681b ldr r3, [r3, #0] 8000cb0: 681a ldr r2, [r3, #0] 8000cb2: 687b ldr r3, [r7, #4] 8000cb4: 681b ldr r3, [r3, #0] 8000cb6: f022 0220 bic.w r2, r2, #32 8000cba: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 8000cbc: 687b ldr r3, [r7, #4] 8000cbe: 7edb ldrb r3, [r3, #27] 8000cc0: 2b01 cmp r3, #1 8000cc2: d108 bne.n 8000cd6 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8000cc4: 687b ldr r3, [r7, #4] 8000cc6: 681b ldr r3, [r3, #0] 8000cc8: 681a ldr r2, [r3, #0] 8000cca: 687b ldr r3, [r7, #4] 8000ccc: 681b ldr r3, [r3, #0] 8000cce: f022 0210 bic.w r2, r2, #16 8000cd2: 601a str r2, [r3, #0] 8000cd4: e007 b.n 8000ce6 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8000cd6: 687b ldr r3, [r7, #4] 8000cd8: 681b ldr r3, [r3, #0] 8000cda: 681a ldr r2, [r3, #0] 8000cdc: 687b ldr r3, [r7, #4] 8000cde: 681b ldr r3, [r3, #0] 8000ce0: f042 0210 orr.w r2, r2, #16 8000ce4: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 8000ce6: 687b ldr r3, [r7, #4] 8000ce8: 7f1b ldrb r3, [r3, #28] 8000cea: 2b01 cmp r3, #1 8000cec: d108 bne.n 8000d00 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8000cee: 687b ldr r3, [r7, #4] 8000cf0: 681b ldr r3, [r3, #0] 8000cf2: 681a ldr r2, [r3, #0] 8000cf4: 687b ldr r3, [r7, #4] 8000cf6: 681b ldr r3, [r3, #0] 8000cf8: f042 0208 orr.w r2, r2, #8 8000cfc: 601a str r2, [r3, #0] 8000cfe: e007 b.n 8000d10 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8000d00: 687b ldr r3, [r7, #4] 8000d02: 681b ldr r3, [r3, #0] 8000d04: 681a ldr r2, [r3, #0] 8000d06: 687b ldr r3, [r7, #4] 8000d08: 681b ldr r3, [r3, #0] 8000d0a: f022 0208 bic.w r2, r2, #8 8000d0e: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 8000d10: 687b ldr r3, [r7, #4] 8000d12: 7f5b ldrb r3, [r3, #29] 8000d14: 2b01 cmp r3, #1 8000d16: d108 bne.n 8000d2a { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 8000d18: 687b ldr r3, [r7, #4] 8000d1a: 681b ldr r3, [r3, #0] 8000d1c: 681a ldr r2, [r3, #0] 8000d1e: 687b ldr r3, [r7, #4] 8000d20: 681b ldr r3, [r3, #0] 8000d22: f042 0204 orr.w r2, r2, #4 8000d26: 601a str r2, [r3, #0] 8000d28: e007 b.n 8000d3a } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 8000d2a: 687b ldr r3, [r7, #4] 8000d2c: 681b ldr r3, [r3, #0] 8000d2e: 681a ldr r2, [r3, #0] 8000d30: 687b ldr r3, [r7, #4] 8000d32: 681b ldr r3, [r3, #0] 8000d34: f022 0204 bic.w r2, r2, #4 8000d38: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 8000d3a: 687b ldr r3, [r7, #4] 8000d3c: 689a ldr r2, [r3, #8] 8000d3e: 687b ldr r3, [r7, #4] 8000d40: 68db ldr r3, [r3, #12] 8000d42: 431a orrs r2, r3 8000d44: 687b ldr r3, [r7, #4] 8000d46: 691b ldr r3, [r3, #16] 8000d48: 431a orrs r2, r3 8000d4a: 687b ldr r3, [r7, #4] 8000d4c: 695b ldr r3, [r3, #20] 8000d4e: ea42 0103 orr.w r1, r2, r3 8000d52: 687b ldr r3, [r7, #4] 8000d54: 685b ldr r3, [r3, #4] 8000d56: 1e5a subs r2, r3, #1 8000d58: 687b ldr r3, [r7, #4] 8000d5a: 681b ldr r3, [r3, #0] 8000d5c: 430a orrs r2, r1 8000d5e: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8000d60: 687b ldr r3, [r7, #4] 8000d62: 2200 movs r2, #0 8000d64: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 8000d66: 687b ldr r3, [r7, #4] 8000d68: 2201 movs r2, #1 8000d6a: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 8000d6e: 2300 movs r3, #0 } 8000d70: 4618 mov r0, r3 8000d72: 3710 adds r7, #16 8000d74: 46bd mov sp, r7 8000d76: bd80 pop {r7, pc} 8000d78: 08000781 .word 0x08000781 8000d7c: 080017ff .word 0x080017ff 8000d80: 08001813 .word 0x08001813 8000d84: 08001827 .word 0x08001827 8000d88: 08001787 .word 0x08001787 8000d8c: 0800179b .word 0x0800179b 8000d90: 080017af .word 0x080017af 8000d94: 080017c3 .word 0x080017c3 8000d98: 080017d7 .word 0x080017d7 8000d9c: 080017eb .word 0x080017eb 8000da0: 0800183b .word 0x0800183b 8000da4: 0800184f .word 0x0800184f 8000da8: 08001863 .word 0x08001863 8000dac: 08000869 .word 0x08000869 08000db0 : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 8000db0: b480 push {r7} 8000db2: b087 sub sp, #28 8000db4: af00 add r7, sp, #0 8000db6: 6078 str r0, [r7, #4] 8000db8: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 8000dba: 687b ldr r3, [r7, #4] 8000dbc: 681b ldr r3, [r3, #0] 8000dbe: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 8000dc0: 687b ldr r3, [r7, #4] 8000dc2: f893 3020 ldrb.w r3, [r3, #32] 8000dc6: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 8000dc8: 7cfb ldrb r3, [r7, #19] 8000dca: 2b01 cmp r3, #1 8000dcc: d003 beq.n 8000dd6 8000dce: 7cfb ldrb r3, [r7, #19] 8000dd0: 2b02 cmp r3, #2 8000dd2: f040 80aa bne.w 8000f2a /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 8000dd6: 697b ldr r3, [r7, #20] 8000dd8: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 8000ddc: f043 0201 orr.w r2, r3, #1 8000de0: 697b ldr r3, [r7, #20] 8000de2: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 8000de6: 683b ldr r3, [r7, #0] 8000de8: 695b ldr r3, [r3, #20] 8000dea: f003 031f and.w r3, r3, #31 8000dee: 2201 movs r2, #1 8000df0: fa02 f303 lsl.w r3, r2, r3 8000df4: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 8000df6: 697b ldr r3, [r7, #20] 8000df8: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 8000dfc: 68fb ldr r3, [r7, #12] 8000dfe: 43db mvns r3, r3 8000e00: 401a ands r2, r3 8000e02: 697b ldr r3, [r7, #20] 8000e04: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 8000e08: 683b ldr r3, [r7, #0] 8000e0a: 69db ldr r3, [r3, #28] 8000e0c: 2b00 cmp r3, #0 8000e0e: d123 bne.n 8000e58 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 8000e10: 697b ldr r3, [r7, #20] 8000e12: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 8000e16: 68fb ldr r3, [r7, #12] 8000e18: 43db mvns r3, r3 8000e1a: 401a ands r2, r3 8000e1c: 697b ldr r3, [r7, #20] 8000e1e: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 8000e22: 683b ldr r3, [r7, #0] 8000e24: 68db ldr r3, [r3, #12] 8000e26: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 8000e28: 683b ldr r3, [r7, #0] 8000e2a: 685b ldr r3, [r3, #4] 8000e2c: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8000e2e: 683a ldr r2, [r7, #0] 8000e30: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 8000e32: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8000e34: 697b ldr r3, [r7, #20] 8000e36: 3248 adds r2, #72 @ 0x48 8000e38: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8000e3c: 683b ldr r3, [r7, #0] 8000e3e: 689b ldr r3, [r3, #8] 8000e40: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 8000e42: 683b ldr r3, [r7, #0] 8000e44: 681b ldr r3, [r3, #0] 8000e46: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8000e48: 683b ldr r3, [r7, #0] 8000e4a: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8000e4c: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8000e4e: 6979 ldr r1, [r7, #20] 8000e50: 3348 adds r3, #72 @ 0x48 8000e52: 00db lsls r3, r3, #3 8000e54: 440b add r3, r1 8000e56: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 8000e58: 683b ldr r3, [r7, #0] 8000e5a: 69db ldr r3, [r3, #28] 8000e5c: 2b01 cmp r3, #1 8000e5e: d122 bne.n 8000ea6 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 8000e60: 697b ldr r3, [r7, #20] 8000e62: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 8000e66: 68fb ldr r3, [r7, #12] 8000e68: 431a orrs r2, r3 8000e6a: 697b ldr r3, [r7, #20] 8000e6c: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 8000e70: 683b ldr r3, [r7, #0] 8000e72: 681b ldr r3, [r3, #0] 8000e74: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 8000e76: 683b ldr r3, [r7, #0] 8000e78: 685b ldr r3, [r3, #4] 8000e7a: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8000e7c: 683a ldr r2, [r7, #0] 8000e7e: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 8000e80: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8000e82: 697b ldr r3, [r7, #20] 8000e84: 3248 adds r2, #72 @ 0x48 8000e86: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8000e8a: 683b ldr r3, [r7, #0] 8000e8c: 689b ldr r3, [r3, #8] 8000e8e: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 8000e90: 683b ldr r3, [r7, #0] 8000e92: 68db ldr r3, [r3, #12] 8000e94: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8000e96: 683b ldr r3, [r7, #0] 8000e98: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8000e9a: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8000e9c: 6979 ldr r1, [r7, #20] 8000e9e: 3348 adds r3, #72 @ 0x48 8000ea0: 00db lsls r3, r3, #3 8000ea2: 440b add r3, r1 8000ea4: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 8000ea6: 683b ldr r3, [r7, #0] 8000ea8: 699b ldr r3, [r3, #24] 8000eaa: 2b00 cmp r3, #0 8000eac: d109 bne.n 8000ec2 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 8000eae: 697b ldr r3, [r7, #20] 8000eb0: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8000eb4: 68fb ldr r3, [r7, #12] 8000eb6: 43db mvns r3, r3 8000eb8: 401a ands r2, r3 8000eba: 697b ldr r3, [r7, #20] 8000ebc: f8c3 2204 str.w r2, [r3, #516] @ 0x204 8000ec0: e007 b.n 8000ed2 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 8000ec2: 697b ldr r3, [r7, #20] 8000ec4: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8000ec8: 68fb ldr r3, [r7, #12] 8000eca: 431a orrs r2, r3 8000ecc: 697b ldr r3, [r7, #20] 8000ece: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 8000ed2: 683b ldr r3, [r7, #0] 8000ed4: 691b ldr r3, [r3, #16] 8000ed6: 2b00 cmp r3, #0 8000ed8: d109 bne.n 8000eee { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 8000eda: 697b ldr r3, [r7, #20] 8000edc: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 8000ee0: 68fb ldr r3, [r7, #12] 8000ee2: 43db mvns r3, r3 8000ee4: 401a ands r2, r3 8000ee6: 697b ldr r3, [r7, #20] 8000ee8: f8c3 2214 str.w r2, [r3, #532] @ 0x214 8000eec: e007 b.n 8000efe } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 8000eee: 697b ldr r3, [r7, #20] 8000ef0: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 8000ef4: 68fb ldr r3, [r7, #12] 8000ef6: 431a orrs r2, r3 8000ef8: 697b ldr r3, [r7, #20] 8000efa: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 8000efe: 683b ldr r3, [r7, #0] 8000f00: 6a1b ldr r3, [r3, #32] 8000f02: 2b01 cmp r3, #1 8000f04: d107 bne.n 8000f16 { SET_BIT(can_ip->FA1R, filternbrbitpos); 8000f06: 697b ldr r3, [r7, #20] 8000f08: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 8000f0c: 68fb ldr r3, [r7, #12] 8000f0e: 431a orrs r2, r3 8000f10: 697b ldr r3, [r7, #20] 8000f12: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 8000f16: 697b ldr r3, [r7, #20] 8000f18: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 8000f1c: f023 0201 bic.w r2, r3, #1 8000f20: 697b ldr r3, [r7, #20] 8000f22: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 8000f26: 2300 movs r3, #0 8000f28: e006 b.n 8000f38 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8000f2a: 687b ldr r3, [r7, #4] 8000f2c: 6a5b ldr r3, [r3, #36] @ 0x24 8000f2e: f443 2280 orr.w r2, r3, #262144 @ 0x40000 8000f32: 687b ldr r3, [r7, #4] 8000f34: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8000f36: 2301 movs r3, #1 } } 8000f38: 4618 mov r0, r3 8000f3a: 371c adds r7, #28 8000f3c: 46bd mov sp, r7 8000f3e: f85d 7b04 ldr.w r7, [sp], #4 8000f42: 4770 bx lr 08000f44 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 8000f44: b580 push {r7, lr} 8000f46: b084 sub sp, #16 8000f48: af00 add r7, sp, #0 8000f4a: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 8000f4c: 687b ldr r3, [r7, #4] 8000f4e: f893 3020 ldrb.w r3, [r3, #32] 8000f52: b2db uxtb r3, r3 8000f54: 2b01 cmp r3, #1 8000f56: d12e bne.n 8000fb6 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 8000f58: 687b ldr r3, [r7, #4] 8000f5a: 2202 movs r2, #2 8000f5c: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8000f60: 687b ldr r3, [r7, #4] 8000f62: 681b ldr r3, [r3, #0] 8000f64: 681a ldr r2, [r3, #0] 8000f66: 687b ldr r3, [r7, #4] 8000f68: 681b ldr r3, [r3, #0] 8000f6a: f022 0201 bic.w r2, r2, #1 8000f6e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8000f70: f7ff fda8 bl 8000ac4 8000f74: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 8000f76: e012 b.n 8000f9e { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8000f78: f7ff fda4 bl 8000ac4 8000f7c: 4602 mov r2, r0 8000f7e: 68fb ldr r3, [r7, #12] 8000f80: 1ad3 subs r3, r2, r3 8000f82: 2b0a cmp r3, #10 8000f84: d90b bls.n 8000f9e { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8000f86: 687b ldr r3, [r7, #4] 8000f88: 6a5b ldr r3, [r3, #36] @ 0x24 8000f8a: f443 3200 orr.w r2, r3, #131072 @ 0x20000 8000f8e: 687b ldr r3, [r7, #4] 8000f90: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8000f92: 687b ldr r3, [r7, #4] 8000f94: 2205 movs r2, #5 8000f96: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8000f9a: 2301 movs r3, #1 8000f9c: e012 b.n 8000fc4 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 8000f9e: 687b ldr r3, [r7, #4] 8000fa0: 681b ldr r3, [r3, #0] 8000fa2: 685b ldr r3, [r3, #4] 8000fa4: f003 0301 and.w r3, r3, #1 8000fa8: 2b00 cmp r3, #0 8000faa: d1e5 bne.n 8000f78 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8000fac: 687b ldr r3, [r7, #4] 8000fae: 2200 movs r2, #0 8000fb0: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 8000fb2: 2300 movs r3, #0 8000fb4: e006 b.n 8000fc4 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 8000fb6: 687b ldr r3, [r7, #4] 8000fb8: 6a5b ldr r3, [r3, #36] @ 0x24 8000fba: f443 2200 orr.w r2, r3, #524288 @ 0x80000 8000fbe: 687b ldr r3, [r7, #4] 8000fc0: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 8000fc2: 2301 movs r3, #1 } } 8000fc4: 4618 mov r0, r3 8000fc6: 3710 adds r7, #16 8000fc8: 46bd mov sp, r7 8000fca: bd80 pop {r7, pc} 08000fcc : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 8000fcc: b480 push {r7} 8000fce: b089 sub sp, #36 @ 0x24 8000fd0: af00 add r7, sp, #0 8000fd2: 60f8 str r0, [r7, #12] 8000fd4: 60b9 str r1, [r7, #8] 8000fd6: 607a str r2, [r7, #4] 8000fd8: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 8000fda: 68fb ldr r3, [r7, #12] 8000fdc: f893 3020 ldrb.w r3, [r3, #32] 8000fe0: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 8000fe2: 68fb ldr r3, [r7, #12] 8000fe4: 681b ldr r3, [r3, #0] 8000fe6: 689b ldr r3, [r3, #8] 8000fe8: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 8000fea: 7ffb ldrb r3, [r7, #31] 8000fec: 2b01 cmp r3, #1 8000fee: d003 beq.n 8000ff8 8000ff0: 7ffb ldrb r3, [r7, #31] 8000ff2: 2b02 cmp r3, #2 8000ff4: f040 80ad bne.w 8001152 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 8000ff8: 69bb ldr r3, [r7, #24] 8000ffa: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8000ffe: 2b00 cmp r3, #0 8001000: d10a bne.n 8001018 ((tsr & CAN_TSR_TME1) != 0U) || 8001002: 69bb ldr r3, [r7, #24] 8001004: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 8001008: 2b00 cmp r3, #0 800100a: d105 bne.n 8001018 ((tsr & CAN_TSR_TME2) != 0U)) 800100c: 69bb ldr r3, [r7, #24] 800100e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 8001012: 2b00 cmp r3, #0 8001014: f000 8095 beq.w 8001142 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 8001018: 69bb ldr r3, [r7, #24] 800101a: 0e1b lsrs r3, r3, #24 800101c: f003 0303 and.w r3, r3, #3 8001020: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 8001022: 2201 movs r2, #1 8001024: 697b ldr r3, [r7, #20] 8001026: 409a lsls r2, r3 8001028: 683b ldr r3, [r7, #0] 800102a: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800102c: 68bb ldr r3, [r7, #8] 800102e: 689b ldr r3, [r3, #8] 8001030: 2b00 cmp r3, #0 8001032: d10d bne.n 8001050 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8001034: 68bb ldr r3, [r7, #8] 8001036: 681b ldr r3, [r3, #0] 8001038: 055a lsls r2, r3, #21 pHeader->RTR); 800103a: 68bb ldr r3, [r7, #8] 800103c: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800103e: 68f9 ldr r1, [r7, #12] 8001040: 6809 ldr r1, [r1, #0] 8001042: 431a orrs r2, r3 8001044: 697b ldr r3, [r7, #20] 8001046: 3318 adds r3, #24 8001048: 011b lsls r3, r3, #4 800104a: 440b add r3, r1 800104c: 601a str r2, [r3, #0] 800104e: e00f b.n 8001070 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8001050: 68bb ldr r3, [r7, #8] 8001052: 685b ldr r3, [r3, #4] 8001054: 00da lsls r2, r3, #3 pHeader->IDE | 8001056: 68bb ldr r3, [r7, #8] 8001058: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800105a: 431a orrs r2, r3 pHeader->RTR); 800105c: 68bb ldr r3, [r7, #8] 800105e: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8001060: 68f9 ldr r1, [r7, #12] 8001062: 6809 ldr r1, [r1, #0] pHeader->IDE | 8001064: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8001066: 697b ldr r3, [r7, #20] 8001068: 3318 adds r3, #24 800106a: 011b lsls r3, r3, #4 800106c: 440b add r3, r1 800106e: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 8001070: 68fb ldr r3, [r7, #12] 8001072: 6819 ldr r1, [r3, #0] 8001074: 68bb ldr r3, [r7, #8] 8001076: 691a ldr r2, [r3, #16] 8001078: 697b ldr r3, [r7, #20] 800107a: 3318 adds r3, #24 800107c: 011b lsls r3, r3, #4 800107e: 440b add r3, r1 8001080: 3304 adds r3, #4 8001082: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 8001084: 68bb ldr r3, [r7, #8] 8001086: 7d1b ldrb r3, [r3, #20] 8001088: 2b01 cmp r3, #1 800108a: d111 bne.n 80010b0 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800108c: 68fb ldr r3, [r7, #12] 800108e: 681a ldr r2, [r3, #0] 8001090: 697b ldr r3, [r7, #20] 8001092: 3318 adds r3, #24 8001094: 011b lsls r3, r3, #4 8001096: 4413 add r3, r2 8001098: 3304 adds r3, #4 800109a: 681b ldr r3, [r3, #0] 800109c: 68fa ldr r2, [r7, #12] 800109e: 6811 ldr r1, [r2, #0] 80010a0: f443 7280 orr.w r2, r3, #256 @ 0x100 80010a4: 697b ldr r3, [r7, #20] 80010a6: 3318 adds r3, #24 80010a8: 011b lsls r3, r3, #4 80010aa: 440b add r3, r1 80010ac: 3304 adds r3, #4 80010ae: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 80010b0: 687b ldr r3, [r7, #4] 80010b2: 3307 adds r3, #7 80010b4: 781b ldrb r3, [r3, #0] 80010b6: 061a lsls r2, r3, #24 80010b8: 687b ldr r3, [r7, #4] 80010ba: 3306 adds r3, #6 80010bc: 781b ldrb r3, [r3, #0] 80010be: 041b lsls r3, r3, #16 80010c0: 431a orrs r2, r3 80010c2: 687b ldr r3, [r7, #4] 80010c4: 3305 adds r3, #5 80010c6: 781b ldrb r3, [r3, #0] 80010c8: 021b lsls r3, r3, #8 80010ca: 4313 orrs r3, r2 80010cc: 687a ldr r2, [r7, #4] 80010ce: 3204 adds r2, #4 80010d0: 7812 ldrb r2, [r2, #0] 80010d2: 4610 mov r0, r2 80010d4: 68fa ldr r2, [r7, #12] 80010d6: 6811 ldr r1, [r2, #0] 80010d8: ea43 0200 orr.w r2, r3, r0 80010dc: 697b ldr r3, [r7, #20] 80010de: 011b lsls r3, r3, #4 80010e0: 440b add r3, r1 80010e2: f503 73c6 add.w r3, r3, #396 @ 0x18c 80010e6: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 80010e8: 687b ldr r3, [r7, #4] 80010ea: 3303 adds r3, #3 80010ec: 781b ldrb r3, [r3, #0] 80010ee: 061a lsls r2, r3, #24 80010f0: 687b ldr r3, [r7, #4] 80010f2: 3302 adds r3, #2 80010f4: 781b ldrb r3, [r3, #0] 80010f6: 041b lsls r3, r3, #16 80010f8: 431a orrs r2, r3 80010fa: 687b ldr r3, [r7, #4] 80010fc: 3301 adds r3, #1 80010fe: 781b ldrb r3, [r3, #0] 8001100: 021b lsls r3, r3, #8 8001102: 4313 orrs r3, r2 8001104: 687a ldr r2, [r7, #4] 8001106: 7812 ldrb r2, [r2, #0] 8001108: 4610 mov r0, r2 800110a: 68fa ldr r2, [r7, #12] 800110c: 6811 ldr r1, [r2, #0] 800110e: ea43 0200 orr.w r2, r3, r0 8001112: 697b ldr r3, [r7, #20] 8001114: 011b lsls r3, r3, #4 8001116: 440b add r3, r1 8001118: f503 73c4 add.w r3, r3, #392 @ 0x188 800111c: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800111e: 68fb ldr r3, [r7, #12] 8001120: 681a ldr r2, [r3, #0] 8001122: 697b ldr r3, [r7, #20] 8001124: 3318 adds r3, #24 8001126: 011b lsls r3, r3, #4 8001128: 4413 add r3, r2 800112a: 681b ldr r3, [r3, #0] 800112c: 68fa ldr r2, [r7, #12] 800112e: 6811 ldr r1, [r2, #0] 8001130: f043 0201 orr.w r2, r3, #1 8001134: 697b ldr r3, [r7, #20] 8001136: 3318 adds r3, #24 8001138: 011b lsls r3, r3, #4 800113a: 440b add r3, r1 800113c: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800113e: 2300 movs r3, #0 8001140: e00e b.n 8001160 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8001142: 68fb ldr r3, [r7, #12] 8001144: 6a5b ldr r3, [r3, #36] @ 0x24 8001146: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800114a: 68fb ldr r3, [r7, #12] 800114c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800114e: 2301 movs r3, #1 8001150: e006 b.n 8001160 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8001152: 68fb ldr r3, [r7, #12] 8001154: 6a5b ldr r3, [r3, #36] @ 0x24 8001156: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800115a: 68fb ldr r3, [r7, #12] 800115c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800115e: 2301 movs r3, #1 } } 8001160: 4618 mov r0, r3 8001162: 3724 adds r7, #36 @ 0x24 8001164: 46bd mov sp, r7 8001166: f85d 7b04 ldr.w r7, [sp], #4 800116a: 4770 bx lr 0800116c : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800116c: b480 push {r7} 800116e: b087 sub sp, #28 8001170: af00 add r7, sp, #0 8001172: 60f8 str r0, [r7, #12] 8001174: 60b9 str r1, [r7, #8] 8001176: 607a str r2, [r7, #4] 8001178: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800117a: 68fb ldr r3, [r7, #12] 800117c: f893 3020 ldrb.w r3, [r3, #32] 8001180: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 8001182: 7dfb ldrb r3, [r7, #23] 8001184: 2b01 cmp r3, #1 8001186: d003 beq.n 8001190 8001188: 7dfb ldrb r3, [r7, #23] 800118a: 2b02 cmp r3, #2 800118c: f040 8103 bne.w 8001396 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 8001190: 68bb ldr r3, [r7, #8] 8001192: 2b00 cmp r3, #0 8001194: d10e bne.n 80011b4 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 8001196: 68fb ldr r3, [r7, #12] 8001198: 681b ldr r3, [r3, #0] 800119a: 68db ldr r3, [r3, #12] 800119c: f003 0303 and.w r3, r3, #3 80011a0: 2b00 cmp r3, #0 80011a2: d116 bne.n 80011d2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 80011a4: 68fb ldr r3, [r7, #12] 80011a6: 6a5b ldr r3, [r3, #36] @ 0x24 80011a8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 80011ac: 68fb ldr r3, [r7, #12] 80011ae: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 80011b0: 2301 movs r3, #1 80011b2: e0f7 b.n 80013a4 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 80011b4: 68fb ldr r3, [r7, #12] 80011b6: 681b ldr r3, [r3, #0] 80011b8: 691b ldr r3, [r3, #16] 80011ba: f003 0303 and.w r3, r3, #3 80011be: 2b00 cmp r3, #0 80011c0: d107 bne.n 80011d2 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 80011c2: 68fb ldr r3, [r7, #12] 80011c4: 6a5b ldr r3, [r3, #36] @ 0x24 80011c6: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 80011ca: 68fb ldr r3, [r7, #12] 80011cc: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 80011ce: 2301 movs r3, #1 80011d0: e0e8 b.n 80013a4 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 80011d2: 68fb ldr r3, [r7, #12] 80011d4: 681a ldr r2, [r3, #0] 80011d6: 68bb ldr r3, [r7, #8] 80011d8: 331b adds r3, #27 80011da: 011b lsls r3, r3, #4 80011dc: 4413 add r3, r2 80011de: 681b ldr r3, [r3, #0] 80011e0: f003 0204 and.w r2, r3, #4 80011e4: 687b ldr r3, [r7, #4] 80011e6: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 80011e8: 687b ldr r3, [r7, #4] 80011ea: 689b ldr r3, [r3, #8] 80011ec: 2b00 cmp r3, #0 80011ee: d10c bne.n 800120a { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 80011f0: 68fb ldr r3, [r7, #12] 80011f2: 681a ldr r2, [r3, #0] 80011f4: 68bb ldr r3, [r7, #8] 80011f6: 331b adds r3, #27 80011f8: 011b lsls r3, r3, #4 80011fa: 4413 add r3, r2 80011fc: 681b ldr r3, [r3, #0] 80011fe: 0d5b lsrs r3, r3, #21 8001200: f3c3 020a ubfx r2, r3, #0, #11 8001204: 687b ldr r3, [r7, #4] 8001206: 601a str r2, [r3, #0] 8001208: e00b b.n 8001222 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800120a: 68fb ldr r3, [r7, #12] 800120c: 681a ldr r2, [r3, #0] 800120e: 68bb ldr r3, [r7, #8] 8001210: 331b adds r3, #27 8001212: 011b lsls r3, r3, #4 8001214: 4413 add r3, r2 8001216: 681b ldr r3, [r3, #0] 8001218: 08db lsrs r3, r3, #3 800121a: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800121e: 687b ldr r3, [r7, #4] 8001220: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 8001222: 68fb ldr r3, [r7, #12] 8001224: 681a ldr r2, [r3, #0] 8001226: 68bb ldr r3, [r7, #8] 8001228: 331b adds r3, #27 800122a: 011b lsls r3, r3, #4 800122c: 4413 add r3, r2 800122e: 681b ldr r3, [r3, #0] 8001230: f003 0202 and.w r2, r3, #2 8001234: 687b ldr r3, [r7, #4] 8001236: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 8001238: 68fb ldr r3, [r7, #12] 800123a: 681a ldr r2, [r3, #0] 800123c: 68bb ldr r3, [r7, #8] 800123e: 331b adds r3, #27 8001240: 011b lsls r3, r3, #4 8001242: 4413 add r3, r2 8001244: 3304 adds r3, #4 8001246: 681b ldr r3, [r3, #0] 8001248: f003 0308 and.w r3, r3, #8 800124c: 2b00 cmp r3, #0 800124e: d003 beq.n 8001258 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 8001250: 687b ldr r3, [r7, #4] 8001252: 2208 movs r2, #8 8001254: 611a str r2, [r3, #16] 8001256: e00b b.n 8001270 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 8001258: 68fb ldr r3, [r7, #12] 800125a: 681a ldr r2, [r3, #0] 800125c: 68bb ldr r3, [r7, #8] 800125e: 331b adds r3, #27 8001260: 011b lsls r3, r3, #4 8001262: 4413 add r3, r2 8001264: 3304 adds r3, #4 8001266: 681b ldr r3, [r3, #0] 8001268: f003 020f and.w r2, r3, #15 800126c: 687b ldr r3, [r7, #4] 800126e: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 8001270: 68fb ldr r3, [r7, #12] 8001272: 681a ldr r2, [r3, #0] 8001274: 68bb ldr r3, [r7, #8] 8001276: 331b adds r3, #27 8001278: 011b lsls r3, r3, #4 800127a: 4413 add r3, r2 800127c: 3304 adds r3, #4 800127e: 681b ldr r3, [r3, #0] 8001280: 0a1b lsrs r3, r3, #8 8001282: b2da uxtb r2, r3 8001284: 687b ldr r3, [r7, #4] 8001286: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 8001288: 68fb ldr r3, [r7, #12] 800128a: 681a ldr r2, [r3, #0] 800128c: 68bb ldr r3, [r7, #8] 800128e: 331b adds r3, #27 8001290: 011b lsls r3, r3, #4 8001292: 4413 add r3, r2 8001294: 3304 adds r3, #4 8001296: 681b ldr r3, [r3, #0] 8001298: 0c1b lsrs r3, r3, #16 800129a: b29a uxth r2, r3 800129c: 687b ldr r3, [r7, #4] 800129e: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 80012a0: 68fb ldr r3, [r7, #12] 80012a2: 681a ldr r2, [r3, #0] 80012a4: 68bb ldr r3, [r7, #8] 80012a6: 011b lsls r3, r3, #4 80012a8: 4413 add r3, r2 80012aa: f503 73dc add.w r3, r3, #440 @ 0x1b8 80012ae: 681b ldr r3, [r3, #0] 80012b0: b2da uxtb r2, r3 80012b2: 683b ldr r3, [r7, #0] 80012b4: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 80012b6: 68fb ldr r3, [r7, #12] 80012b8: 681a ldr r2, [r3, #0] 80012ba: 68bb ldr r3, [r7, #8] 80012bc: 011b lsls r3, r3, #4 80012be: 4413 add r3, r2 80012c0: f503 73dc add.w r3, r3, #440 @ 0x1b8 80012c4: 681b ldr r3, [r3, #0] 80012c6: 0a1a lsrs r2, r3, #8 80012c8: 683b ldr r3, [r7, #0] 80012ca: 3301 adds r3, #1 80012cc: b2d2 uxtb r2, r2 80012ce: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 80012d0: 68fb ldr r3, [r7, #12] 80012d2: 681a ldr r2, [r3, #0] 80012d4: 68bb ldr r3, [r7, #8] 80012d6: 011b lsls r3, r3, #4 80012d8: 4413 add r3, r2 80012da: f503 73dc add.w r3, r3, #440 @ 0x1b8 80012de: 681b ldr r3, [r3, #0] 80012e0: 0c1a lsrs r2, r3, #16 80012e2: 683b ldr r3, [r7, #0] 80012e4: 3302 adds r3, #2 80012e6: b2d2 uxtb r2, r2 80012e8: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 80012ea: 68fb ldr r3, [r7, #12] 80012ec: 681a ldr r2, [r3, #0] 80012ee: 68bb ldr r3, [r7, #8] 80012f0: 011b lsls r3, r3, #4 80012f2: 4413 add r3, r2 80012f4: f503 73dc add.w r3, r3, #440 @ 0x1b8 80012f8: 681b ldr r3, [r3, #0] 80012fa: 0e1a lsrs r2, r3, #24 80012fc: 683b ldr r3, [r7, #0] 80012fe: 3303 adds r3, #3 8001300: b2d2 uxtb r2, r2 8001302: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 8001304: 68fb ldr r3, [r7, #12] 8001306: 681a ldr r2, [r3, #0] 8001308: 68bb ldr r3, [r7, #8] 800130a: 011b lsls r3, r3, #4 800130c: 4413 add r3, r2 800130e: f503 73de add.w r3, r3, #444 @ 0x1bc 8001312: 681a ldr r2, [r3, #0] 8001314: 683b ldr r3, [r7, #0] 8001316: 3304 adds r3, #4 8001318: b2d2 uxtb r2, r2 800131a: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800131c: 68fb ldr r3, [r7, #12] 800131e: 681a ldr r2, [r3, #0] 8001320: 68bb ldr r3, [r7, #8] 8001322: 011b lsls r3, r3, #4 8001324: 4413 add r3, r2 8001326: f503 73de add.w r3, r3, #444 @ 0x1bc 800132a: 681b ldr r3, [r3, #0] 800132c: 0a1a lsrs r2, r3, #8 800132e: 683b ldr r3, [r7, #0] 8001330: 3305 adds r3, #5 8001332: b2d2 uxtb r2, r2 8001334: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 8001336: 68fb ldr r3, [r7, #12] 8001338: 681a ldr r2, [r3, #0] 800133a: 68bb ldr r3, [r7, #8] 800133c: 011b lsls r3, r3, #4 800133e: 4413 add r3, r2 8001340: f503 73de add.w r3, r3, #444 @ 0x1bc 8001344: 681b ldr r3, [r3, #0] 8001346: 0c1a lsrs r2, r3, #16 8001348: 683b ldr r3, [r7, #0] 800134a: 3306 adds r3, #6 800134c: b2d2 uxtb r2, r2 800134e: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 8001350: 68fb ldr r3, [r7, #12] 8001352: 681a ldr r2, [r3, #0] 8001354: 68bb ldr r3, [r7, #8] 8001356: 011b lsls r3, r3, #4 8001358: 4413 add r3, r2 800135a: f503 73de add.w r3, r3, #444 @ 0x1bc 800135e: 681b ldr r3, [r3, #0] 8001360: 0e1a lsrs r2, r3, #24 8001362: 683b ldr r3, [r7, #0] 8001364: 3307 adds r3, #7 8001366: b2d2 uxtb r2, r2 8001368: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800136a: 68bb ldr r3, [r7, #8] 800136c: 2b00 cmp r3, #0 800136e: d108 bne.n 8001382 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 8001370: 68fb ldr r3, [r7, #12] 8001372: 681b ldr r3, [r3, #0] 8001374: 68da ldr r2, [r3, #12] 8001376: 68fb ldr r3, [r7, #12] 8001378: 681b ldr r3, [r3, #0] 800137a: f042 0220 orr.w r2, r2, #32 800137e: 60da str r2, [r3, #12] 8001380: e007 b.n 8001392 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 8001382: 68fb ldr r3, [r7, #12] 8001384: 681b ldr r3, [r3, #0] 8001386: 691a ldr r2, [r3, #16] 8001388: 68fb ldr r3, [r7, #12] 800138a: 681b ldr r3, [r3, #0] 800138c: f042 0220 orr.w r2, r2, #32 8001390: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 8001392: 2300 movs r3, #0 8001394: e006 b.n 80013a4 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8001396: 68fb ldr r3, [r7, #12] 8001398: 6a5b ldr r3, [r3, #36] @ 0x24 800139a: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800139e: 68fb ldr r3, [r7, #12] 80013a0: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 80013a2: 2301 movs r3, #1 } } 80013a4: 4618 mov r0, r3 80013a6: 371c adds r7, #28 80013a8: 46bd mov sp, r7 80013aa: f85d 7b04 ldr.w r7, [sp], #4 80013ae: 4770 bx lr 080013b0 : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 80013b0: b480 push {r7} 80013b2: b085 sub sp, #20 80013b4: af00 add r7, sp, #0 80013b6: 6078 str r0, [r7, #4] 80013b8: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 80013ba: 687b ldr r3, [r7, #4] 80013bc: f893 3020 ldrb.w r3, [r3, #32] 80013c0: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 80013c2: 7bfb ldrb r3, [r7, #15] 80013c4: 2b01 cmp r3, #1 80013c6: d002 beq.n 80013ce 80013c8: 7bfb ldrb r3, [r7, #15] 80013ca: 2b02 cmp r3, #2 80013cc: d109 bne.n 80013e2 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 80013ce: 687b ldr r3, [r7, #4] 80013d0: 681b ldr r3, [r3, #0] 80013d2: 6959 ldr r1, [r3, #20] 80013d4: 687b ldr r3, [r7, #4] 80013d6: 681b ldr r3, [r3, #0] 80013d8: 683a ldr r2, [r7, #0] 80013da: 430a orrs r2, r1 80013dc: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 80013de: 2300 movs r3, #0 80013e0: e006 b.n 80013f0 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 80013e2: 687b ldr r3, [r7, #4] 80013e4: 6a5b ldr r3, [r3, #36] @ 0x24 80013e6: f443 2280 orr.w r2, r3, #262144 @ 0x40000 80013ea: 687b ldr r3, [r7, #4] 80013ec: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 80013ee: 2301 movs r3, #1 } } 80013f0: 4618 mov r0, r3 80013f2: 3714 adds r7, #20 80013f4: 46bd mov sp, r7 80013f6: f85d 7b04 ldr.w r7, [sp], #4 80013fa: 4770 bx lr 080013fc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 80013fc: b580 push {r7, lr} 80013fe: b08a sub sp, #40 @ 0x28 8001400: af00 add r7, sp, #0 8001402: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 8001404: 2300 movs r3, #0 8001406: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 8001408: 687b ldr r3, [r7, #4] 800140a: 681b ldr r3, [r3, #0] 800140c: 695b ldr r3, [r3, #20] 800140e: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 8001410: 687b ldr r3, [r7, #4] 8001412: 681b ldr r3, [r3, #0] 8001414: 685b ldr r3, [r3, #4] 8001416: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 8001418: 687b ldr r3, [r7, #4] 800141a: 681b ldr r3, [r3, #0] 800141c: 689b ldr r3, [r3, #8] 800141e: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 8001420: 687b ldr r3, [r7, #4] 8001422: 681b ldr r3, [r3, #0] 8001424: 68db ldr r3, [r3, #12] 8001426: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 8001428: 687b ldr r3, [r7, #4] 800142a: 681b ldr r3, [r3, #0] 800142c: 691b ldr r3, [r3, #16] 800142e: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 8001430: 687b ldr r3, [r7, #4] 8001432: 681b ldr r3, [r3, #0] 8001434: 699b ldr r3, [r3, #24] 8001436: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 8001438: 6a3b ldr r3, [r7, #32] 800143a: f003 0301 and.w r3, r3, #1 800143e: 2b00 cmp r3, #0 8001440: f000 8083 beq.w 800154a { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 8001444: 69bb ldr r3, [r7, #24] 8001446: f003 0301 and.w r3, r3, #1 800144a: 2b00 cmp r3, #0 800144c: d025 beq.n 800149a { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800144e: 687b ldr r3, [r7, #4] 8001450: 681b ldr r3, [r3, #0] 8001452: 2201 movs r2, #1 8001454: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 8001456: 69bb ldr r3, [r7, #24] 8001458: f003 0302 and.w r3, r3, #2 800145c: 2b00 cmp r3, #0 800145e: d004 beq.n 800146a { /* Transmission Mailbox 0 complete callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); 8001460: 687b ldr r3, [r7, #4] 8001462: 6a9b ldr r3, [r3, #40] @ 0x28 8001464: 6878 ldr r0, [r7, #4] 8001466: 4798 blx r3 8001468: e017 b.n 800149a HAL_CAN_TxMailbox0CompleteCallback(hcan); #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800146a: 69bb ldr r3, [r7, #24] 800146c: f003 0304 and.w r3, r3, #4 8001470: 2b00 cmp r3, #0 8001472: d004 beq.n 800147e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 8001474: 6a7b ldr r3, [r7, #36] @ 0x24 8001476: f443 6300 orr.w r3, r3, #2048 @ 0x800 800147a: 627b str r3, [r7, #36] @ 0x24 800147c: e00d b.n 800149a } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800147e: 69bb ldr r3, [r7, #24] 8001480: f003 0308 and.w r3, r3, #8 8001484: 2b00 cmp r3, #0 8001486: d004 beq.n 8001492 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 8001488: 6a7b ldr r3, [r7, #36] @ 0x24 800148a: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800148e: 627b str r3, [r7, #36] @ 0x24 8001490: e003 b.n 800149a else { /* Transmission Mailbox 0 abort callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); 8001492: 687b ldr r3, [r7, #4] 8001494: 6b5b ldr r3, [r3, #52] @ 0x34 8001496: 6878 ldr r0, [r7, #4] 8001498: 4798 blx r3 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800149a: 69bb ldr r3, [r7, #24] 800149c: f403 7380 and.w r3, r3, #256 @ 0x100 80014a0: 2b00 cmp r3, #0 80014a2: d026 beq.n 80014f2 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 80014a4: 687b ldr r3, [r7, #4] 80014a6: 681b ldr r3, [r3, #0] 80014a8: f44f 7280 mov.w r2, #256 @ 0x100 80014ac: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 80014ae: 69bb ldr r3, [r7, #24] 80014b0: f403 7300 and.w r3, r3, #512 @ 0x200 80014b4: 2b00 cmp r3, #0 80014b6: d004 beq.n 80014c2 { /* Transmission Mailbox 1 complete callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); 80014b8: 687b ldr r3, [r7, #4] 80014ba: 6adb ldr r3, [r3, #44] @ 0x2c 80014bc: 6878 ldr r0, [r7, #4] 80014be: 4798 blx r3 80014c0: e017 b.n 80014f2 HAL_CAN_TxMailbox1CompleteCallback(hcan); #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 80014c2: 69bb ldr r3, [r7, #24] 80014c4: f403 6380 and.w r3, r3, #1024 @ 0x400 80014c8: 2b00 cmp r3, #0 80014ca: d004 beq.n 80014d6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 80014cc: 6a7b ldr r3, [r7, #36] @ 0x24 80014ce: f443 5300 orr.w r3, r3, #8192 @ 0x2000 80014d2: 627b str r3, [r7, #36] @ 0x24 80014d4: e00d b.n 80014f2 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 80014d6: 69bb ldr r3, [r7, #24] 80014d8: f403 6300 and.w r3, r3, #2048 @ 0x800 80014dc: 2b00 cmp r3, #0 80014de: d004 beq.n 80014ea { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 80014e0: 6a7b ldr r3, [r7, #36] @ 0x24 80014e2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80014e6: 627b str r3, [r7, #36] @ 0x24 80014e8: e003 b.n 80014f2 else { /* Transmission Mailbox 1 abort callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); 80014ea: 687b ldr r3, [r7, #4] 80014ec: 6b9b ldr r3, [r3, #56] @ 0x38 80014ee: 6878 ldr r0, [r7, #4] 80014f0: 4798 blx r3 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 80014f2: 69bb ldr r3, [r7, #24] 80014f4: f403 3380 and.w r3, r3, #65536 @ 0x10000 80014f8: 2b00 cmp r3, #0 80014fa: d026 beq.n 800154a { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 80014fc: 687b ldr r3, [r7, #4] 80014fe: 681b ldr r3, [r3, #0] 8001500: f44f 3280 mov.w r2, #65536 @ 0x10000 8001504: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 8001506: 69bb ldr r3, [r7, #24] 8001508: f403 3300 and.w r3, r3, #131072 @ 0x20000 800150c: 2b00 cmp r3, #0 800150e: d004 beq.n 800151a { /* Transmission Mailbox 2 complete callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); 8001510: 687b ldr r3, [r7, #4] 8001512: 6b1b ldr r3, [r3, #48] @ 0x30 8001514: 6878 ldr r0, [r7, #4] 8001516: 4798 blx r3 8001518: e017 b.n 800154a HAL_CAN_TxMailbox2CompleteCallback(hcan); #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800151a: 69bb ldr r3, [r7, #24] 800151c: f403 2380 and.w r3, r3, #262144 @ 0x40000 8001520: 2b00 cmp r3, #0 8001522: d004 beq.n 800152e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 8001524: 6a7b ldr r3, [r7, #36] @ 0x24 8001526: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800152a: 627b str r3, [r7, #36] @ 0x24 800152c: e00d b.n 800154a } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800152e: 69bb ldr r3, [r7, #24] 8001530: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001534: 2b00 cmp r3, #0 8001536: d004 beq.n 8001542 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 8001538: 6a7b ldr r3, [r7, #36] @ 0x24 800153a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800153e: 627b str r3, [r7, #36] @ 0x24 8001540: e003 b.n 800154a else { /* Transmission Mailbox 2 abort callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); 8001542: 687b ldr r3, [r7, #4] 8001544: 6bdb ldr r3, [r3, #60] @ 0x3c 8001546: 6878 ldr r0, [r7, #4] 8001548: 4798 blx r3 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800154a: 6a3b ldr r3, [r7, #32] 800154c: f003 0308 and.w r3, r3, #8 8001550: 2b00 cmp r3, #0 8001552: d00c beq.n 800156e { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 8001554: 697b ldr r3, [r7, #20] 8001556: f003 0310 and.w r3, r3, #16 800155a: 2b00 cmp r3, #0 800155c: d007 beq.n 800156e { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800155e: 6a7b ldr r3, [r7, #36] @ 0x24 8001560: f443 7300 orr.w r3, r3, #512 @ 0x200 8001564: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 8001566: 687b ldr r3, [r7, #4] 8001568: 681b ldr r3, [r3, #0] 800156a: 2210 movs r2, #16 800156c: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800156e: 6a3b ldr r3, [r7, #32] 8001570: f003 0304 and.w r3, r3, #4 8001574: 2b00 cmp r3, #0 8001576: d00c beq.n 8001592 { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 8001578: 697b ldr r3, [r7, #20] 800157a: f003 0308 and.w r3, r3, #8 800157e: 2b00 cmp r3, #0 8001580: d007 beq.n 8001592 { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 8001582: 687b ldr r3, [r7, #4] 8001584: 681b ldr r3, [r3, #0] 8001586: 2208 movs r2, #8 8001588: 60da str r2, [r3, #12] /* Receive FIFO 0 full Callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); 800158a: 687b ldr r3, [r7, #4] 800158c: 6c5b ldr r3, [r3, #68] @ 0x44 800158e: 6878 ldr r0, [r7, #4] 8001590: 4798 blx r3 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 8001592: 6a3b ldr r3, [r7, #32] 8001594: f003 0302 and.w r3, r3, #2 8001598: 2b00 cmp r3, #0 800159a: d00a beq.n 80015b2 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800159c: 687b ldr r3, [r7, #4] 800159e: 681b ldr r3, [r3, #0] 80015a0: 68db ldr r3, [r3, #12] 80015a2: f003 0303 and.w r3, r3, #3 80015a6: 2b00 cmp r3, #0 80015a8: d003 beq.n 80015b2 { /* Receive FIFO 0 message pending Callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); 80015aa: 687b ldr r3, [r7, #4] 80015ac: 6c1b ldr r3, [r3, #64] @ 0x40 80015ae: 6878 ldr r0, [r7, #4] 80015b0: 4798 blx r3 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 80015b2: 6a3b ldr r3, [r7, #32] 80015b4: f003 0340 and.w r3, r3, #64 @ 0x40 80015b8: 2b00 cmp r3, #0 80015ba: d00c beq.n 80015d6 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 80015bc: 693b ldr r3, [r7, #16] 80015be: f003 0310 and.w r3, r3, #16 80015c2: 2b00 cmp r3, #0 80015c4: d007 beq.n 80015d6 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 80015c6: 6a7b ldr r3, [r7, #36] @ 0x24 80015c8: f443 6380 orr.w r3, r3, #1024 @ 0x400 80015cc: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 80015ce: 687b ldr r3, [r7, #4] 80015d0: 681b ldr r3, [r3, #0] 80015d2: 2210 movs r2, #16 80015d4: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 80015d6: 6a3b ldr r3, [r7, #32] 80015d8: f003 0320 and.w r3, r3, #32 80015dc: 2b00 cmp r3, #0 80015de: d00c beq.n 80015fa { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 80015e0: 693b ldr r3, [r7, #16] 80015e2: f003 0308 and.w r3, r3, #8 80015e6: 2b00 cmp r3, #0 80015e8: d007 beq.n 80015fa { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 80015ea: 687b ldr r3, [r7, #4] 80015ec: 681b ldr r3, [r3, #0] 80015ee: 2208 movs r2, #8 80015f0: 611a str r2, [r3, #16] /* Receive FIFO 1 full Callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); 80015f2: 687b ldr r3, [r7, #4] 80015f4: 6cdb ldr r3, [r3, #76] @ 0x4c 80015f6: 6878 ldr r0, [r7, #4] 80015f8: 4798 blx r3 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 80015fa: 6a3b ldr r3, [r7, #32] 80015fc: f003 0310 and.w r3, r3, #16 8001600: 2b00 cmp r3, #0 8001602: d00a beq.n 800161a { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 8001604: 687b ldr r3, [r7, #4] 8001606: 681b ldr r3, [r3, #0] 8001608: 691b ldr r3, [r3, #16] 800160a: f003 0303 and.w r3, r3, #3 800160e: 2b00 cmp r3, #0 8001610: d003 beq.n 800161a { /* Receive FIFO 1 message pending Callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); 8001612: 687b ldr r3, [r7, #4] 8001614: 6c9b ldr r3, [r3, #72] @ 0x48 8001616: 6878 ldr r0, [r7, #4] 8001618: 4798 blx r3 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800161a: 6a3b ldr r3, [r7, #32] 800161c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001620: 2b00 cmp r3, #0 8001622: d00c beq.n 800163e