FaSTTUBe/dashboard
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Dashboard.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00003220 08000188 08000188 00001188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000030 080033a8 080033a8 000043a8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080033d8 080033d8 0000500c 2**0
CONTENTS
4 .ARM 00000000 080033d8 080033d8 0000500c 2**0
CONTENTS
5 .preinit_array 00000000 080033d8 080033d8 0000500c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080033d8 080033d8 000043d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 080033dc 080033dc 000043dc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 080033e0 00005000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000e8 2000000c 080033ec 0000500c 2**2
ALLOC
10 ._user_heap_stack 00000604 200000f4 080033ec 000050f4 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000500c 2**0
CONTENTS, READONLY
12 .debug_info 000074b1 00000000 00000000 0000503c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001916 00000000 00000000 0000c4ed 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000005f0 00000000 00000000 0000de08 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000452 00000000 00000000 0000e3f8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001b63a 00000000 00000000 0000e84a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00007c2e 00000000 00000000 00029e84 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000a14e1 00000000 00000000 00031ab2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000d2f93 2**0
CONTENTS, READONLY
20 .debug_frame 00001670 00000000 00000000 000d2fd8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000075 00000000 00000000 000d4648 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000000c .word 0x2000000c
80001a4: 00000000 .word 0x00000000
80001a8: 08003390 .word 0x08003390
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000010 .word 0x20000010
80001c4: 08003390 .word 0x08003390
080001c8 <can_init>:
extern int ts_on;
extern int ams_last_tick;
extern int r2d_progress;
dash_tx_t dash_tx;
void can_init(CAN_HandleTypeDef* hcan){
80001c8: b580 push {r7, lr}
80001ca: b082 sub sp, #8
80001cc: af00 add r7, sp, #0
80001ce: 6078 str r0, [r7, #4]
ftcan_init(hcan);
80001d0: 6878 ldr r0, [r7, #4]
80001d2: f000 f84b bl 800026c <ftcan_init>
ftcan_add_filter(0x00, 0x00); // no filter
80001d6: 2100 movs r1, #0
80001d8: 2000 movs r0, #0
80001da: f000 f88b bl 80002f4 <ftcan_add_filter>
}
80001de: bf00 nop
80001e0: 3708 adds r7, #8
80001e2: 46bd mov sp, r7
80001e4: bd80 pop {r7, pc}
...
080001e8 <can_send>:
void can_send(){
80001e8: b580 push {r7, lr}
80001ea: b082 sub sp, #8
80001ec: af00 add r7, sp, #0
uint8_t data[1];
data[0] = dash_tx.dash_send;
80001ee: 4b07 ldr r3, [pc, #28] @ (800020c <can_send+0x24>)
80001f0: 781b ldrb r3, [r3, #0]
80001f2: 713b strb r3, [r7, #4]
ftcan_transmit(CAN_ID_TX, data, 1);
80001f4: 1d3b adds r3, r7, #4
80001f6: 2201 movs r2, #1
80001f8: 4619 mov r1, r3
80001fa: f44f 6084 mov.w r0, #1056 @ 0x420
80001fe: f000 f855 bl 80002ac <ftcan_transmit>
}
8000202: bf00 nop
8000204: 3708 adds r7, #8
8000206: 46bd mov sp, r7
8000208: bd80 pop {r7, pc}
800020a: bf00 nop
800020c: 2000002c .word 0x2000002c
08000210 <ftcan_msg_received_cb>:
void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){
8000210: b580 push {r7, lr}
8000212: b084 sub sp, #16
8000214: af00 add r7, sp, #0
8000216: 4603 mov r3, r0
8000218: 60b9 str r1, [r7, #8]
800021a: 607a str r2, [r7, #4]
800021c: 81fb strh r3, [r7, #14]
if(id == CAN_ID_RX_AMS){
800021e: 89fb ldrh r3, [r7, #14]
8000220: 2b0a cmp r3, #10
8000222: d10e bne.n 8000242 <ftcan_msg_received_cb+0x32>
ams_last_tick = HAL_GetTick();
8000224: f000 fcec bl 8000c00 <HAL_GetTick>
8000228: 4603 mov r3, r0
800022a: 461a mov r2, r3
800022c: 4b0c ldr r3, [pc, #48] @ (8000260 <ftcan_msg_received_cb+0x50>)
800022e: 601a str r2, [r3, #0]
acc_status.ams_status.ams_rx = data[0];
8000230: 687b ldr r3, [r7, #4]
8000232: 781a ldrb r2, [r3, #0]
8000234: 4b0b ldr r3, [pc, #44] @ (8000264 <ftcan_msg_received_cb+0x54>)
8000236: 701a strb r2, [r3, #0]
acc_status.led_status.ams_led = data[7];
8000238: 687b ldr r3, [r7, #4]
800023a: 3307 adds r3, #7
800023c: 781a ldrb r2, [r3, #0]
800023e: 4b09 ldr r3, [pc, #36] @ (8000264 <ftcan_msg_received_cb+0x54>)
8000240: 705a strb r2, [r3, #1]
}
if(id == CAN_ID_RX_R2D){
8000242: 89fb ldrh r3, [r7, #14]
8000244: f5b3 6f82 cmp.w r3, #1040 @ 0x410
8000248: d106 bne.n 8000258 <ftcan_msg_received_cb+0x48>
r2d_progress = data[1] & 0x0F;
800024a: 687b ldr r3, [r7, #4]
800024c: 3301 adds r3, #1
800024e: 781b ldrb r3, [r3, #0]
8000250: f003 030f and.w r3, r3, #15
8000254: 4a04 ldr r2, [pc, #16] @ (8000268 <ftcan_msg_received_cb+0x58>)
8000256: 6013 str r3, [r2, #0]
}
}
8000258: bf00 nop
800025a: 3710 adds r7, #16
800025c: 46bd mov sp, r7
800025e: bd80 pop {r7, pc}
8000260: 200000e8 .word 0x200000e8
8000264: 20000028 .word 0x20000028
8000268: 200000dd .word 0x200000dd
0800026c <ftcan_init>:
#include <string.h>
#if defined(FTCAN_IS_BXCAN)
static CAN_HandleTypeDef *hcan;
HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) {
800026c: b580 push {r7, lr}
800026e: b084 sub sp, #16
8000270: af00 add r7, sp, #0
8000272: 6078 str r0, [r7, #4]
hcan = handle;
8000274: 4a0c ldr r2, [pc, #48] @ (80002a8 <ftcan_init+0x3c>)
8000276: 687b ldr r3, [r7, #4]
8000278: 6013 str r3, [r2, #0]
HAL_StatusTypeDef status =
HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING);
800027a: 4b0b ldr r3, [pc, #44] @ (80002a8 <ftcan_init+0x3c>)
800027c: 681b ldr r3, [r3, #0]
800027e: 2102 movs r1, #2
8000280: 4618 mov r0, r3
8000282: f001 f90f bl 80014a4 <HAL_CAN_ActivateNotification>
8000286: 4603 mov r3, r0
8000288: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
800028a: 7bfb ldrb r3, [r7, #15]
800028c: 2b00 cmp r3, #0
800028e: d001 beq.n 8000294 <ftcan_init+0x28>
return status;
8000290: 7bfb ldrb r3, [r7, #15]
8000292: e005 b.n 80002a0 <ftcan_init+0x34>
}
return HAL_CAN_Start(hcan);
8000294: 4b04 ldr r3, [pc, #16] @ (80002a8 <ftcan_init+0x3c>)
8000296: 681b ldr r3, [r3, #0]
8000298: 4618 mov r0, r3
800029a: f000 fecd bl 8001038 <HAL_CAN_Start>
800029e: 4603 mov r3, r0
}
80002a0: 4618 mov r0, r3
80002a2: 3710 adds r7, #16
80002a4: 46bd mov sp, r7
80002a6: bd80 pop {r7, pc}
80002a8: 20000030 .word 0x20000030
080002ac <ftcan_transmit>:
HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data,
size_t datalen) {
80002ac: b580 push {r7, lr}
80002ae: b086 sub sp, #24
80002b0: af00 add r7, sp, #0
80002b2: 4603 mov r3, r0
80002b4: 60b9 str r1, [r7, #8]
80002b6: 607a str r2, [r7, #4]
80002b8: 81fb strh r3, [r7, #14]
static CAN_TxHeaderTypeDef header;
header.StdId = id;
80002ba: 89fb ldrh r3, [r7, #14]
80002bc: 4a0b ldr r2, [pc, #44] @ (80002ec <ftcan_transmit+0x40>)
80002be: 6013 str r3, [r2, #0]
header.IDE = CAN_ID_STD;
80002c0: 4b0a ldr r3, [pc, #40] @ (80002ec <ftcan_transmit+0x40>)
80002c2: 2200 movs r2, #0
80002c4: 609a str r2, [r3, #8]
header.RTR = CAN_RTR_DATA;
80002c6: 4b09 ldr r3, [pc, #36] @ (80002ec <ftcan_transmit+0x40>)
80002c8: 2200 movs r2, #0
80002ca: 60da str r2, [r3, #12]
header.DLC = datalen;
80002cc: 4a07 ldr r2, [pc, #28] @ (80002ec <ftcan_transmit+0x40>)
80002ce: 687b ldr r3, [r7, #4]
80002d0: 6113 str r3, [r2, #16]
uint32_t mailbox;
return HAL_CAN_AddTxMessage(hcan, &header, data, &mailbox);
80002d2: 4b07 ldr r3, [pc, #28] @ (80002f0 <ftcan_transmit+0x44>)
80002d4: 6818 ldr r0, [r3, #0]
80002d6: f107 0314 add.w r3, r7, #20
80002da: 68ba ldr r2, [r7, #8]
80002dc: 4903 ldr r1, [pc, #12] @ (80002ec <ftcan_transmit+0x40>)
80002de: f000 feef bl 80010c0 <HAL_CAN_AddTxMessage>
80002e2: 4603 mov r3, r0
}
80002e4: 4618 mov r0, r3
80002e6: 3718 adds r7, #24
80002e8: 46bd mov sp, r7
80002ea: bd80 pop {r7, pc}
80002ec: 20000034 .word 0x20000034
80002f0: 20000030 .word 0x20000030
080002f4 <ftcan_add_filter>:
HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) {
80002f4: b580 push {r7, lr}
80002f6: b084 sub sp, #16
80002f8: af00 add r7, sp, #0
80002fa: 4603 mov r3, r0
80002fc: 460a mov r2, r1
80002fe: 80fb strh r3, [r7, #6]
8000300: 4613 mov r3, r2
8000302: 80bb strh r3, [r7, #4]
static uint32_t next_filter_no = 0;
static CAN_FilterTypeDef filter;
if (next_filter_no % 2 == 0) {
8000304: 4b26 ldr r3, [pc, #152] @ (80003a0 <ftcan_add_filter+0xac>)
8000306: 681b ldr r3, [r3, #0]
8000308: f003 0301 and.w r3, r3, #1
800030c: 2b00 cmp r3, #0
800030e: d110 bne.n 8000332 <ftcan_add_filter+0x3e>
filter.FilterIdHigh = id << 5;
8000310: 88fb ldrh r3, [r7, #6]
8000312: 015b lsls r3, r3, #5
8000314: 4a23 ldr r2, [pc, #140] @ (80003a4 <ftcan_add_filter+0xb0>)
8000316: 6013 str r3, [r2, #0]
filter.FilterMaskIdHigh = mask << 5;
8000318: 88bb ldrh r3, [r7, #4]
800031a: 015b lsls r3, r3, #5
800031c: 4a21 ldr r2, [pc, #132] @ (80003a4 <ftcan_add_filter+0xb0>)
800031e: 6093 str r3, [r2, #8]
filter.FilterIdLow = id << 5;
8000320: 88fb ldrh r3, [r7, #6]
8000322: 015b lsls r3, r3, #5
8000324: 4a1f ldr r2, [pc, #124] @ (80003a4 <ftcan_add_filter+0xb0>)
8000326: 6053 str r3, [r2, #4]
filter.FilterMaskIdLow = mask << 5;
8000328: 88bb ldrh r3, [r7, #4]
800032a: 015b lsls r3, r3, #5
800032c: 4a1d ldr r2, [pc, #116] @ (80003a4 <ftcan_add_filter+0xb0>)
800032e: 60d3 str r3, [r2, #12]
8000330: e007 b.n 8000342 <ftcan_add_filter+0x4e>
} else {
// Leave high filter untouched from the last configuration
filter.FilterIdLow = id << 5;
8000332: 88fb ldrh r3, [r7, #6]
8000334: 015b lsls r3, r3, #5
8000336: 4a1b ldr r2, [pc, #108] @ (80003a4 <ftcan_add_filter+0xb0>)
8000338: 6053 str r3, [r2, #4]
filter.FilterMaskIdLow = mask << 5;
800033a: 88bb ldrh r3, [r7, #4]
800033c: 015b lsls r3, r3, #5
800033e: 4a19 ldr r2, [pc, #100] @ (80003a4 <ftcan_add_filter+0xb0>)
8000340: 60d3 str r3, [r2, #12]
}
filter.FilterFIFOAssignment = CAN_FILTER_FIFO0;
8000342: 4b18 ldr r3, [pc, #96] @ (80003a4 <ftcan_add_filter+0xb0>)
8000344: 2200 movs r2, #0
8000346: 611a str r2, [r3, #16]
filter.FilterBank = next_filter_no / 2;
8000348: 4b15 ldr r3, [pc, #84] @ (80003a0 <ftcan_add_filter+0xac>)
800034a: 681b ldr r3, [r3, #0]
800034c: 085b lsrs r3, r3, #1
800034e: 4a15 ldr r2, [pc, #84] @ (80003a4 <ftcan_add_filter+0xb0>)
8000350: 6153 str r3, [r2, #20]
if (filter.FilterBank > FTCAN_NUM_FILTERS + 1) {
8000352: 4b14 ldr r3, [pc, #80] @ (80003a4 <ftcan_add_filter+0xb0>)
8000354: 695b ldr r3, [r3, #20]
8000356: 2b0e cmp r3, #14
8000358: d901 bls.n 800035e <ftcan_add_filter+0x6a>
return HAL_ERROR;
800035a: 2301 movs r3, #1
800035c: e01c b.n 8000398 <ftcan_add_filter+0xa4>
}
filter.FilterMode = CAN_FILTERMODE_IDMASK;
800035e: 4b11 ldr r3, [pc, #68] @ (80003a4 <ftcan_add_filter+0xb0>)
8000360: 2200 movs r2, #0
8000362: 619a str r2, [r3, #24]
filter.FilterScale = CAN_FILTERSCALE_16BIT;
8000364: 4b0f ldr r3, [pc, #60] @ (80003a4 <ftcan_add_filter+0xb0>)
8000366: 2200 movs r2, #0
8000368: 61da str r2, [r3, #28]
filter.FilterActivation = CAN_FILTER_ENABLE;
800036a: 4b0e ldr r3, [pc, #56] @ (80003a4 <ftcan_add_filter+0xb0>)
800036c: 2201 movs r2, #1
800036e: 621a str r2, [r3, #32]
// Disable slave filters
// TODO: Some STM32 have multiple CAN peripherals, and one uses the slave
// filter bank
filter.SlaveStartFilterBank = FTCAN_NUM_FILTERS;
8000370: 4b0c ldr r3, [pc, #48] @ (80003a4 <ftcan_add_filter+0xb0>)
8000372: 220d movs r2, #13
8000374: 625a str r2, [r3, #36] @ 0x24
HAL_StatusTypeDef status = HAL_CAN_ConfigFilter(hcan, &filter);
8000376: 4b0c ldr r3, [pc, #48] @ (80003a8 <ftcan_add_filter+0xb4>)
8000378: 681b ldr r3, [r3, #0]
800037a: 490a ldr r1, [pc, #40] @ (80003a4 <ftcan_add_filter+0xb0>)
800037c: 4618 mov r0, r3
800037e: f000 fd91 bl 8000ea4 <HAL_CAN_ConfigFilter>
8000382: 4603 mov r3, r0
8000384: 73fb strb r3, [r7, #15]
if (status == HAL_OK) {
8000386: 7bfb ldrb r3, [r7, #15]
8000388: 2b00 cmp r3, #0
800038a: d104 bne.n 8000396 <ftcan_add_filter+0xa2>
next_filter_no++;
800038c: 4b04 ldr r3, [pc, #16] @ (80003a0 <ftcan_add_filter+0xac>)
800038e: 681b ldr r3, [r3, #0]
8000390: 3301 adds r3, #1
8000392: 4a03 ldr r2, [pc, #12] @ (80003a0 <ftcan_add_filter+0xac>)
8000394: 6013 str r3, [r2, #0]
}
return status;
8000396: 7bfb ldrb r3, [r7, #15]
}
8000398: 4618 mov r0, r3
800039a: 3710 adds r7, #16
800039c: 46bd mov sp, r7
800039e: bd80 pop {r7, pc}
80003a0: 2000004c .word 0x2000004c
80003a4: 20000050 .word 0x20000050
80003a8: 20000030 .word 0x20000030
080003ac <HAL_CAN_RxFifo0MsgPendingCallback>:
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) {
80003ac: b580 push {r7, lr}
80003ae: b08c sub sp, #48 @ 0x30
80003b0: af00 add r7, sp, #0
80003b2: 6078 str r0, [r7, #4]
if (handle != hcan) {
80003b4: 4b12 ldr r3, [pc, #72] @ (8000400 <HAL_CAN_RxFifo0MsgPendingCallback+0x54>)
80003b6: 681b ldr r3, [r3, #0]
80003b8: 687a ldr r2, [r7, #4]
80003ba: 429a cmp r2, r3
80003bc: d117 bne.n 80003ee <HAL_CAN_RxFifo0MsgPendingCallback+0x42>
return;
}
CAN_RxHeaderTypeDef header;
uint8_t data[8];
if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) {
80003be: 4b10 ldr r3, [pc, #64] @ (8000400 <HAL_CAN_RxFifo0MsgPendingCallback+0x54>)
80003c0: 6818 ldr r0, [r3, #0]
80003c2: f107 030c add.w r3, r7, #12
80003c6: f107 0214 add.w r2, r7, #20
80003ca: 2100 movs r1, #0
80003cc: f000 ff48 bl 8001260 <HAL_CAN_GetRxMessage>
80003d0: 4603 mov r3, r0
80003d2: 2b00 cmp r3, #0
80003d4: d10d bne.n 80003f2 <HAL_CAN_RxFifo0MsgPendingCallback+0x46>
return;
}
if (header.IDE != CAN_ID_STD) {
80003d6: 69fb ldr r3, [r7, #28]
80003d8: 2b00 cmp r3, #0
80003da: d10c bne.n 80003f6 <HAL_CAN_RxFifo0MsgPendingCallback+0x4a>
return;
}
ftcan_msg_received_cb(header.StdId, header.DLC, data);
80003dc: 697b ldr r3, [r7, #20]
80003de: b29b uxth r3, r3
80003e0: 6a79 ldr r1, [r7, #36] @ 0x24
80003e2: f107 020c add.w r2, r7, #12
80003e6: 4618 mov r0, r3
80003e8: f7ff ff12 bl 8000210 <ftcan_msg_received_cb>
80003ec: e004 b.n 80003f8 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
return;
80003ee: bf00 nop
80003f0: e002 b.n 80003f8 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
return;
80003f2: bf00 nop
80003f4: e000 b.n 80003f8 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
return;
80003f6: bf00 nop
}
80003f8: 3730 adds r7, #48 @ 0x30
80003fa: 46bd mov sp, r7
80003fc: bd80 pop {r7, pc}
80003fe: bf00 nop
8000400: 20000030 .word 0x20000030
08000404 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000404: b580 push {r7, lr}
8000406: b086 sub sp, #24
8000408: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800040a: f000 fb9f bl 8000b4c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800040e: f000 f9c1 bl 8000794 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000412: f000 fa31 bl 8000878 <MX_GPIO_Init>
MX_CAN_Init();
8000416: f000 f9f9 bl 800080c <MX_CAN_Init>
/* USER CODE BEGIN 2 */
can_init(&hcan);
800041a: 48a5 ldr r0, [pc, #660] @ (80006b0 <main+0x2ac>)
800041c: f7ff fed4 bl 80001c8 <can_init>
sdc_closed = 0;
8000420: 4ba4 ldr r3, [pc, #656] @ (80006b4 <main+0x2b0>)
8000422: 2200 movs r2, #0
8000424: 701a strb r2, [r3, #0]
blink_tick_tson = HAL_GetTick();
8000426: f000 fbeb bl 8000c00 <HAL_GetTick>
800042a: 4603 mov r3, r0
800042c: 4aa2 ldr r2, [pc, #648] @ (80006b8 <main+0x2b4>)
800042e: 6013 str r3, [r2, #0]
blink_tick_r2d = HAL_GetTick();
8000430: f000 fbe6 bl 8000c00 <HAL_GetTick>
8000434: 4603 mov r3, r0
8000436: 4aa1 ldr r2, [pc, #644] @ (80006bc <main+0x2b8>)
8000438: 6013 str r3, [r2, #0]
can_send_tick = HAL_GetTick();
800043a: f000 fbe1 bl 8000c00 <HAL_GetTick>
800043e: 4603 mov r3, r0
8000440: 4a9f ldr r2, [pc, #636] @ (80006c0 <main+0x2bc>)
8000442: 6013 str r3, [r2, #0]
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
dash_tx.tson = HAL_GPIO_ReadPin(TSON_BTN_GPIO_Port, TSON_BTN_Pin);
8000444: f44f 4100 mov.w r1, #32768 @ 0x8000
8000448: 489e ldr r0, [pc, #632] @ (80006c4 <main+0x2c0>)
800044a: f001 fd1b bl 8001e84 <HAL_GPIO_ReadPin>
800044e: 4603 mov r3, r0
8000450: f003 0301 and.w r3, r3, #1
8000454: b2d9 uxtb r1, r3
8000456: 4a9c ldr r2, [pc, #624] @ (80006c8 <main+0x2c4>)
8000458: 7813 ldrb r3, [r2, #0]
800045a: f361 0341 bfi r3, r1, #1, #1
800045e: 7013 strb r3, [r2, #0]
dash_tx.r2d = HAL_GPIO_ReadPin(R2D_BTN_GPIO_Port, R2D_BTN_Pin);
8000460: 2120 movs r1, #32
8000462: 4898 ldr r0, [pc, #608] @ (80006c4 <main+0x2c0>)
8000464: f001 fd0e bl 8001e84 <HAL_GPIO_ReadPin>
8000468: 4603 mov r3, r0
800046a: f003 0301 and.w r3, r3, #1
800046e: b2d9 uxtb r1, r3
8000470: 4a95 ldr r2, [pc, #596] @ (80006c8 <main+0x2c4>)
8000472: 7813 ldrb r3, [r2, #0]
8000474: f361 0300 bfi r3, r1, #0, #1
8000478: 7013 strb r3, [r2, #0]
dash_tx.sdc_in = HAL_GPIO_ReadPin(SDC_In_3V3_GPIO_Port, SDC_In_3V3_Pin);
800047a: 2110 movs r1, #16
800047c: 4891 ldr r0, [pc, #580] @ (80006c4 <main+0x2c0>)
800047e: f001 fd01 bl 8001e84 <HAL_GPIO_ReadPin>
8000482: 4603 mov r3, r0
8000484: f003 0301 and.w r3, r3, #1
8000488: b2d9 uxtb r1, r3
800048a: 4a8f ldr r2, [pc, #572] @ (80006c8 <main+0x2c4>)
800048c: 7813 ldrb r3, [r2, #0]
800048e: f361 03c3 bfi r3, r1, #3, #1
8000492: 7013 strb r3, [r2, #0]
dash_tx.sdc_out = HAL_GPIO_ReadPin(SDC_Out_3V3_GPIO_Port, SDC_Out_3V3_Pin);
8000494: 2108 movs r1, #8
8000496: 488b ldr r0, [pc, #556] @ (80006c4 <main+0x2c0>)
8000498: f001 fcf4 bl 8001e84 <HAL_GPIO_ReadPin>
800049c: 4603 mov r3, r0
800049e: f003 0301 and.w r3, r3, #1
80004a2: b2d9 uxtb r1, r3
80004a4: 4a88 ldr r2, [pc, #544] @ (80006c8 <main+0x2c4>)
80004a6: 7813 ldrb r3, [r2, #0]
80004a8: f361 1304 bfi r3, r1, #4, #1
80004ac: 7013 strb r3, [r2, #0]
dash_tx.racemode = HAL_GPIO_ReadPin(RMode_Out_3V3_GPIO_Port, RMode_Out_3V3_Pin);
80004ae: f44f 7180 mov.w r1, #256 @ 0x100
80004b2: 4884 ldr r0, [pc, #528] @ (80006c4 <main+0x2c0>)
80004b4: f001 fce6 bl 8001e84 <HAL_GPIO_ReadPin>
80004b8: 4603 mov r3, r0
80004ba: f003 0301 and.w r3, r3, #1
80004be: b2d9 uxtb r1, r3
80004c0: 4a81 ldr r2, [pc, #516] @ (80006c8 <main+0x2c4>)
80004c2: 7813 ldrb r3, [r2, #0]
80004c4: f361 0382 bfi r3, r1, #2, #1
80004c8: 7013 strb r3, [r2, #0]
// Inverted in hardware
if ((HAL_GetTick() - ams_last_tick) < 350) { //master sendet aller 100ms, fürs testen erstmal auf 150ms gesetzt -> kann später wieder runter
80004ca: f000 fb99 bl 8000c00 <HAL_GetTick>
80004ce: 4602 mov r2, r0
80004d0: 4b7e ldr r3, [pc, #504] @ (80006cc <main+0x2c8>)
80004d2: 681b ldr r3, [r3, #0]
80004d4: 1ad3 subs r3, r2, r3
80004d6: f5b3 7faf cmp.w r3, #350 @ 0x15e
80004da: d221 bcs.n 8000520 <main+0x11c>
HAL_GPIO_WritePin(IMD_LED_GPIO_Port, IMD_LED_Pin, acc_status.led_status.imd_error);
80004dc: 4b7c ldr r3, [pc, #496] @ (80006d0 <main+0x2cc>)
80004de: 785b ldrb r3, [r3, #1]
80004e0: f3c3 0340 ubfx r3, r3, #1, #1
80004e4: b2db uxtb r3, r3
80004e6: 461a mov r2, r3
80004e8: 2108 movs r1, #8
80004ea: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80004ee: f001 fce1 bl 8001eb4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(AMS_LED_GPIO_Port, AMS_LED_Pin, acc_status.led_status.ams_error);
80004f2: 4b77 ldr r3, [pc, #476] @ (80006d0 <main+0x2cc>)
80004f4: 785b ldrb r3, [r3, #1]
80004f6: f3c3 0380 ubfx r3, r3, #2, #1
80004fa: b2db uxtb r3, r3
80004fc: 461a mov r2, r3
80004fe: 2110 movs r1, #16
8000500: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000504: f001 fcd6 bl 8001eb4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSOFF_LED_GPIO_Port, TSOFF_LED_Pin,acc_status.led_status.ts_green);
8000508: 4b71 ldr r3, [pc, #452] @ (80006d0 <main+0x2cc>)
800050a: 785b ldrb r3, [r3, #1]
800050c: f3c3 0300 ubfx r3, r3, #0, #1
8000510: b2db uxtb r3, r3
8000512: 461a mov r2, r3
8000514: 2120 movs r1, #32
8000516: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800051a: f001 fccb bl 8001eb4 <HAL_GPIO_WritePin>
800051e: e011 b.n 8000544 <main+0x140>
} else {
// Safe state: Error LEDs on, TSOFF off
HAL_GPIO_WritePin(IMD_LED_GPIO_Port, IMD_LED_Pin, 0);
8000520: 2200 movs r2, #0
8000522: 2108 movs r1, #8
8000524: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000528: f001 fcc4 bl 8001eb4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(AMS_LED_GPIO_Port, AMS_LED_Pin, 0);
800052c: 2200 movs r2, #0
800052e: 2110 movs r1, #16
8000530: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000534: f001 fcbe bl 8001eb4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSOFF_LED_GPIO_Port, TSOFF_LED_Pin, 0);
8000538: 2200 movs r2, #0
800053a: 2120 movs r1, #32
800053c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000540: f001 fcb8 bl 8001eb4 <HAL_GPIO_WritePin>
}
int r = 0, g = 0, b = 0;
8000544: 2300 movs r3, #0
8000546: 617b str r3, [r7, #20]
8000548: 2300 movs r3, #0
800054a: 613b str r3, [r7, #16]
800054c: 2300 movs r3, #0
800054e: 60fb str r3, [r7, #12]
int br = 0, bg = 0, bb = 0;
8000550: 2300 movs r3, #0
8000552: 60bb str r3, [r7, #8]
8000554: 2300 movs r3, #0
8000556: 607b str r3, [r7, #4]
8000558: 2300 movs r3, #0
800055a: 603b str r3, [r7, #0]
if(acc_status.ams_status.sdc_closed == 1){
800055c: 4b5c ldr r3, [pc, #368] @ (80006d0 <main+0x2cc>)
800055e: 781b ldrb r3, [r3, #0]
8000560: f023 037f bic.w r3, r3, #127 @ 0x7f
8000564: b2db uxtb r3, r3
8000566: 2b00 cmp r3, #0
8000568: d014 beq.n 8000594 <main+0x190>
if(acc_status.ams_status.ts_state == TS_INACTIVE){
800056a: 4b59 ldr r3, [pc, #356] @ (80006d0 <main+0x2cc>)
800056c: 781b ldrb r3, [r3, #0]
800056e: f003 0301 and.w r3, r3, #1
8000572: b2db uxtb r3, r3
8000574: 2b00 cmp r3, #0
8000576: d103 bne.n 8000580 <main+0x17c>
r = g = 1;
8000578: 2301 movs r3, #1
800057a: 613b str r3, [r7, #16]
800057c: 693b ldr r3, [r7, #16]
800057e: 617b str r3, [r7, #20]
}
if(acc_status.ams_status.ts_state == TS_PRECHARGE){
br = bg = 1;
}
if(acc_status.ams_status.ts_state == TS_ACTIVE){
8000580: 4b53 ldr r3, [pc, #332] @ (80006d0 <main+0x2cc>)
8000582: 781b ldrb r3, [r3, #0]
8000584: f003 0301 and.w r3, r3, #1
8000588: b2db uxtb r3, r3
800058a: 2b00 cmp r3, #0
800058c: d006 beq.n 800059c <main+0x198>
g = 1;
800058e: 2301 movs r3, #1
8000590: 613b str r3, [r7, #16]
8000592: e003 b.n 800059c <main+0x198>
if(acc_status.ams_status.ts_state == TS_ERROR){
br = 1;
}
}
else{
b = r = 1;
8000594: 2301 movs r3, #1
8000596: 617b str r3, [r7, #20]
8000598: 697b ldr r3, [r7, #20]
800059a: 60fb str r3, [r7, #12]
}
HAL_GPIO_WritePin(TSON_R_GPIO_Port, TSON_R_Pin, r);
800059c: 697b ldr r3, [r7, #20]
800059e: b2db uxtb r3, r3
80005a0: 461a mov r2, r3
80005a2: 2101 movs r1, #1
80005a4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80005a8: f001 fc84 bl 8001eb4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSON_G_GPIO_Port, TSON_G_Pin, g);
80005ac: 693b ldr r3, [r7, #16]
80005ae: b2db uxtb r3, r3
80005b0: 461a mov r2, r3
80005b2: 2102 movs r1, #2
80005b4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80005b8: f001 fc7c bl 8001eb4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(TSON_B_GPIO_Port, TSON_B_Pin, b);
80005bc: 68fb ldr r3, [r7, #12]
80005be: b2db uxtb r3, r3
80005c0: 461a mov r2, r3
80005c2: 2104 movs r1, #4
80005c4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80005c8: f001 fc74 bl 8001eb4 <HAL_GPIO_WritePin>
if ((br || bg || bb) && ((HAL_GetTick() - blink_tick_tson) > 1000u)) {
80005cc: 68bb ldr r3, [r7, #8]
80005ce: 2b00 cmp r3, #0
80005d0: d105 bne.n 80005de <main+0x1da>
80005d2: 687b ldr r3, [r7, #4]
80005d4: 2b00 cmp r3, #0
80005d6: d102 bne.n 80005de <main+0x1da>
80005d8: 683b ldr r3, [r7, #0]
80005da: 2b00 cmp r3, #0
80005dc: d025 beq.n 800062a <main+0x226>
80005de: f000 fb0f bl 8000c00 <HAL_GetTick>
80005e2: 4602 mov r2, r0
80005e4: 4b34 ldr r3, [pc, #208] @ (80006b8 <main+0x2b4>)
80005e6: 681b ldr r3, [r3, #0]
80005e8: 1ad3 subs r3, r2, r3
80005ea: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
80005ee: d91c bls.n 800062a <main+0x226>
if (br) { HAL_GPIO_TogglePin(TSON_R_GPIO_Port, TSON_R_Pin); }
80005f0: 68bb ldr r3, [r7, #8]
80005f2: 2b00 cmp r3, #0
80005f4: d004 beq.n 8000600 <main+0x1fc>
80005f6: 2101 movs r1, #1
80005f8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80005fc: f001 fc72 bl 8001ee4 <HAL_GPIO_TogglePin>
if (bg) { HAL_GPIO_TogglePin(TSON_G_GPIO_Port, TSON_G_Pin); }
8000600: 687b ldr r3, [r7, #4]
8000602: 2b00 cmp r3, #0
8000604: d004 beq.n 8000610 <main+0x20c>
8000606: 2102 movs r1, #2
8000608: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800060c: f001 fc6a bl 8001ee4 <HAL_GPIO_TogglePin>
if (bb) { HAL_GPIO_TogglePin(TSON_B_GPIO_Port, TSON_B_Pin); }
8000610: 683b ldr r3, [r7, #0]
8000612: 2b00 cmp r3, #0
8000614: d004 beq.n 8000620 <main+0x21c>
8000616: 2104 movs r1, #4
8000618: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800061c: f001 fc62 bl 8001ee4 <HAL_GPIO_TogglePin>
blink_tick_tson = HAL_GetTick();
8000620: f000 faee bl 8000c00 <HAL_GetTick>
8000624: 4603 mov r3, r0
8000626: 4a24 ldr r2, [pc, #144] @ (80006b8 <main+0x2b4>)
8000628: 6013 str r3, [r2, #0]
}
r = g = b = 0;
800062a: 2300 movs r3, #0
800062c: 60fb str r3, [r7, #12]
800062e: 68fb ldr r3, [r7, #12]
8000630: 613b str r3, [r7, #16]
8000632: 693b ldr r3, [r7, #16]
8000634: 617b str r3, [r7, #20]
br = bg = bb = 0;
8000636: 2300 movs r3, #0
8000638: 603b str r3, [r7, #0]
800063a: 683b ldr r3, [r7, #0]
800063c: 607b str r3, [r7, #4]
800063e: 687b ldr r3, [r7, #4]
8000640: 60bb str r3, [r7, #8]
if (acc_status.ams_status.ts_state == TS_ACTIVE) {
8000642: 4b23 ldr r3, [pc, #140] @ (80006d0 <main+0x2cc>)
8000644: 781b ldrb r3, [r3, #0]
8000646: f003 0301 and.w r3, r3, #1
800064a: b2db uxtb r3, r3
800064c: 2b00 cmp r3, #0
800064e: d043 beq.n 80006d8 <main+0x2d4>
if((r2d_progress == R2D_TS_ACTIVE) || (r2d_progress == R2D_TSMS) || (r2d_progress == R2D_NONE)){
8000650: 4b20 ldr r3, [pc, #128] @ (80006d4 <main+0x2d0>)
8000652: 781b ldrb r3, [r3, #0]
8000654: 2b02 cmp r3, #2
8000656: d007 beq.n 8000668 <main+0x264>
8000658: 4b1e ldr r3, [pc, #120] @ (80006d4 <main+0x2d0>)
800065a: 781b ldrb r3, [r3, #0]
800065c: 2b01 cmp r3, #1
800065e: d003 beq.n 8000668 <main+0x264>
8000660: 4b1c ldr r3, [pc, #112] @ (80006d4 <main+0x2d0>)
8000662: 781b ldrb r3, [r3, #0]
8000664: 2b00 cmp r3, #0
8000666: d103 bne.n 8000670 <main+0x26c>
r = g = 1;
8000668: 2301 movs r3, #1
800066a: 613b str r3, [r7, #16]
800066c: 693b ldr r3, [r7, #16]
800066e: 617b str r3, [r7, #20]
}
if((r2d_progress == R2D_RESETTING_NODES) || (r2d_progress == R2D_RESETTING_COMMS) || (r2d_progress == R2D_WAITING_INIT) || (r2d_progress == R2D_INIT_STAGE1) || (r2d_progress == R2D_INIT_STAGE2)){
8000670: 4b18 ldr r3, [pc, #96] @ (80006d4 <main+0x2d0>)
8000672: 781b ldrb r3, [r3, #0]
8000674: 2b03 cmp r3, #3
8000676: d00f beq.n 8000698 <main+0x294>
8000678: 4b16 ldr r3, [pc, #88] @ (80006d4 <main+0x2d0>)
800067a: 781b ldrb r3, [r3, #0]
800067c: 2b04 cmp r3, #4
800067e: d00b beq.n 8000698 <main+0x294>
8000680: 4b14 ldr r3, [pc, #80] @ (80006d4 <main+0x2d0>)
8000682: 781b ldrb r3, [r3, #0]
8000684: 2b05 cmp r3, #5
8000686: d007 beq.n 8000698 <main+0x294>
8000688: 4b12 ldr r3, [pc, #72] @ (80006d4 <main+0x2d0>)
800068a: 781b ldrb r3, [r3, #0]
800068c: 2b06 cmp r3, #6
800068e: d003 beq.n 8000698 <main+0x294>
8000690: 4b10 ldr r3, [pc, #64] @ (80006d4 <main+0x2d0>)
8000692: 781b ldrb r3, [r3, #0]
8000694: 2b07 cmp r3, #7
8000696: d103 bne.n 80006a0 <main+0x29c>
br = bg = 1;
8000698: 2301 movs r3, #1
800069a: 607b str r3, [r7, #4]
800069c: 687b ldr r3, [r7, #4]
800069e: 60bb str r3, [r7, #8]
}
if(r2d_progress == R2D_INIT_SUCCESS){
80006a0: 4b0c ldr r3, [pc, #48] @ (80006d4 <main+0x2d0>)
80006a2: 781b ldrb r3, [r3, #0]
80006a4: 2b0f cmp r3, #15
80006a6: d11b bne.n 80006e0 <main+0x2dc>
g = 1;
80006a8: 2301 movs r3, #1
80006aa: 613b str r3, [r7, #16]
80006ac: e018 b.n 80006e0 <main+0x2dc>
80006ae: bf00 nop
80006b0: 20000078 .word 0x20000078
80006b4: 200000dc .word 0x200000dc
80006b8: 200000e0 .word 0x200000e0
80006bc: 200000e4 .word 0x200000e4
80006c0: 200000ec .word 0x200000ec
80006c4: 48000400 .word 0x48000400
80006c8: 2000002c .word 0x2000002c
80006cc: 200000e8 .word 0x200000e8
80006d0: 20000028 .word 0x20000028
80006d4: 200000dd .word 0x200000dd
}
} else {
b = r = 1;
80006d8: 2301 movs r3, #1
80006da: 617b str r3, [r7, #20]
80006dc: 697b ldr r3, [r7, #20]
80006de: 60fb str r3, [r7, #12]
}
HAL_GPIO_WritePin(R2D_R_GPIO_Port, R2D_R_Pin, r);
80006e0: 697b ldr r3, [r7, #20]
80006e2: b2db uxtb r3, r3
80006e4: 461a mov r2, r3
80006e6: 2180 movs r1, #128 @ 0x80
80006e8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80006ec: f001 fbe2 bl 8001eb4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(R2D_G_GPIO_Port, R2D_G_Pin, g);
80006f0: 693b ldr r3, [r7, #16]
80006f2: b2db uxtb r3, r3
80006f4: 461a mov r2, r3
80006f6: 2101 movs r1, #1
80006f8: 4823 ldr r0, [pc, #140] @ (8000788 <main+0x384>)
80006fa: f001 fbdb bl 8001eb4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(R2D_B_GPIO_Port, R2D_B_Pin, b);
80006fe: 68fb ldr r3, [r7, #12]
8000700: b2db uxtb r3, r3
8000702: 461a mov r2, r3
8000704: 2102 movs r1, #2
8000706: 4820 ldr r0, [pc, #128] @ (8000788 <main+0x384>)
8000708: f001 fbd4 bl 8001eb4 <HAL_GPIO_WritePin>
if ((br || bg || bb) && ((HAL_GetTick() - blink_tick_r2d) > 1000u)) {
800070c: 68bb ldr r3, [r7, #8]
800070e: 2b00 cmp r3, #0
8000710: d105 bne.n 800071e <main+0x31a>
8000712: 687b ldr r3, [r7, #4]
8000714: 2b00 cmp r3, #0
8000716: d102 bne.n 800071e <main+0x31a>
8000718: 683b ldr r3, [r7, #0]
800071a: 2b00 cmp r3, #0
800071c: d023 beq.n 8000766 <main+0x362>
800071e: f000 fa6f bl 8000c00 <HAL_GetTick>
8000722: 4602 mov r2, r0
8000724: 4b19 ldr r3, [pc, #100] @ (800078c <main+0x388>)
8000726: 681b ldr r3, [r3, #0]
8000728: 1ad3 subs r3, r2, r3
800072a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
800072e: d91a bls.n 8000766 <main+0x362>
if (br) { HAL_GPIO_TogglePin(R2D_R_GPIO_Port, R2D_R_Pin); }
8000730: 68bb ldr r3, [r7, #8]
8000732: 2b00 cmp r3, #0
8000734: d004 beq.n 8000740 <main+0x33c>
8000736: 2180 movs r1, #128 @ 0x80
8000738: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800073c: f001 fbd2 bl 8001ee4 <HAL_GPIO_TogglePin>
if (bg) { HAL_GPIO_TogglePin(R2D_G_GPIO_Port, R2D_G_Pin); }
8000740: 687b ldr r3, [r7, #4]
8000742: 2b00 cmp r3, #0
8000744: d003 beq.n 800074e <main+0x34a>
8000746: 2101 movs r1, #1
8000748: 480f ldr r0, [pc, #60] @ (8000788 <main+0x384>)
800074a: f001 fbcb bl 8001ee4 <HAL_GPIO_TogglePin>
if (bb) { HAL_GPIO_TogglePin(R2D_B_GPIO_Port, R2D_B_Pin); }
800074e: 683b ldr r3, [r7, #0]
8000750: 2b00 cmp r3, #0
8000752: d003 beq.n 800075c <main+0x358>
8000754: 2102 movs r1, #2
8000756: 480c ldr r0, [pc, #48] @ (8000788 <main+0x384>)
8000758: f001 fbc4 bl 8001ee4 <HAL_GPIO_TogglePin>
blink_tick_r2d = HAL_GetTick();
800075c: f000 fa50 bl 8000c00 <HAL_GetTick>
8000760: 4603 mov r3, r0
8000762: 4a0a ldr r2, [pc, #40] @ (800078c <main+0x388>)
8000764: 6013 str r3, [r2, #0]
}
if ((HAL_GetTick() - can_send_tick) > 50u){
8000766: f000 fa4b bl 8000c00 <HAL_GetTick>
800076a: 4602 mov r2, r0
800076c: 4b08 ldr r3, [pc, #32] @ (8000790 <main+0x38c>)
800076e: 681b ldr r3, [r3, #0]
8000770: 1ad3 subs r3, r2, r3
8000772: 2b32 cmp r3, #50 @ 0x32
8000774: f67f ae66 bls.w 8000444 <main+0x40>
can_send();
8000778: f7ff fd36 bl 80001e8 <can_send>
can_send_tick = HAL_GetTick();
800077c: f000 fa40 bl 8000c00 <HAL_GetTick>
8000780: 4603 mov r3, r0
8000782: 4a03 ldr r2, [pc, #12] @ (8000790 <main+0x38c>)
8000784: 6013 str r3, [r2, #0]
{
8000786: e65d b.n 8000444 <main+0x40>
8000788: 48000400 .word 0x48000400
800078c: 200000e4 .word 0x200000e4
8000790: 200000ec .word 0x200000ec
08000794 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000794: b580 push {r7, lr}
8000796: b090 sub sp, #64 @ 0x40
8000798: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800079a: f107 0318 add.w r3, r7, #24
800079e: 2228 movs r2, #40 @ 0x28
80007a0: 2100 movs r1, #0
80007a2: 4618 mov r0, r3
80007a4: f002 fdc8 bl 8003338 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80007a8: 1d3b adds r3, r7, #4
80007aa: 2200 movs r2, #0
80007ac: 601a str r2, [r3, #0]
80007ae: 605a str r2, [r3, #4]
80007b0: 609a str r2, [r3, #8]
80007b2: 60da str r2, [r3, #12]
80007b4: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80007b6: 2301 movs r3, #1
80007b8: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80007ba: f44f 3380 mov.w r3, #65536 @ 0x10000
80007be: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80007c0: 2301 movs r3, #1
80007c2: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
80007c4: 2300 movs r3, #0
80007c6: 637b str r3, [r7, #52] @ 0x34
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80007c8: f107 0318 add.w r3, r7, #24
80007cc: 4618 mov r0, r3
80007ce: f001 fba3 bl 8001f18 <HAL_RCC_OscConfig>
80007d2: 4603 mov r3, r0
80007d4: 2b00 cmp r3, #0
80007d6: d001 beq.n 80007dc <SystemClock_Config+0x48>
{
Error_Handler();
80007d8: f000 f8ba bl 8000950 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80007dc: 230f movs r3, #15
80007de: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
80007e0: 2301 movs r3, #1
80007e2: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80007e4: 2300 movs r3, #0
80007e6: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80007e8: 2300 movs r3, #0
80007ea: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80007ec: 2300 movs r3, #0
80007ee: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80007f0: 1d3b adds r3, r7, #4
80007f2: 2100 movs r1, #0
80007f4: 4618 mov r0, r3
80007f6: f002 fbcd bl 8002f94 <HAL_RCC_ClockConfig>
80007fa: 4603 mov r3, r0
80007fc: 2b00 cmp r3, #0
80007fe: d001 beq.n 8000804 <SystemClock_Config+0x70>
{
Error_Handler();
8000800: f000 f8a6 bl 8000950 <Error_Handler>
}
}
8000804: bf00 nop
8000806: 3740 adds r7, #64 @ 0x40
8000808: 46bd mov sp, r7
800080a: bd80 pop {r7, pc}
0800080c <MX_CAN_Init>:
* @brief CAN Initialization Function
* @param None
* @retval None
*/
static void MX_CAN_Init(void)
{
800080c: b580 push {r7, lr}
800080e: af00 add r7, sp, #0
/* USER CODE END CAN_Init 0 */
/* USER CODE BEGIN CAN_Init 1 */
/* USER CODE END CAN_Init 1 */
hcan.Instance = CAN;
8000810: 4b17 ldr r3, [pc, #92] @ (8000870 <MX_CAN_Init+0x64>)
8000812: 4a18 ldr r2, [pc, #96] @ (8000874 <MX_CAN_Init+0x68>)
8000814: 601a str r2, [r3, #0]
hcan.Init.Prescaler = 2;
8000816: 4b16 ldr r3, [pc, #88] @ (8000870 <MX_CAN_Init+0x64>)
8000818: 2202 movs r2, #2
800081a: 605a str r2, [r3, #4]
hcan.Init.Mode = CAN_MODE_NORMAL;
800081c: 4b14 ldr r3, [pc, #80] @ (8000870 <MX_CAN_Init+0x64>)
800081e: 2200 movs r2, #0
8000820: 609a str r2, [r3, #8]
hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
8000822: 4b13 ldr r3, [pc, #76] @ (8000870 <MX_CAN_Init+0x64>)
8000824: 2200 movs r2, #0
8000826: 60da str r2, [r3, #12]
hcan.Init.TimeSeg1 = CAN_BS1_13TQ;
8000828: 4b11 ldr r3, [pc, #68] @ (8000870 <MX_CAN_Init+0x64>)
800082a: f44f 2240 mov.w r2, #786432 @ 0xc0000
800082e: 611a str r2, [r3, #16]
hcan.Init.TimeSeg2 = CAN_BS2_2TQ;
8000830: 4b0f ldr r3, [pc, #60] @ (8000870 <MX_CAN_Init+0x64>)
8000832: f44f 1280 mov.w r2, #1048576 @ 0x100000
8000836: 615a str r2, [r3, #20]
hcan.Init.TimeTriggeredMode = DISABLE;
8000838: 4b0d ldr r3, [pc, #52] @ (8000870 <MX_CAN_Init+0x64>)
800083a: 2200 movs r2, #0
800083c: 761a strb r2, [r3, #24]
hcan.Init.AutoBusOff = DISABLE;
800083e: 4b0c ldr r3, [pc, #48] @ (8000870 <MX_CAN_Init+0x64>)
8000840: 2200 movs r2, #0
8000842: 765a strb r2, [r3, #25]
hcan.Init.AutoWakeUp = DISABLE;
8000844: 4b0a ldr r3, [pc, #40] @ (8000870 <MX_CAN_Init+0x64>)
8000846: 2200 movs r2, #0
8000848: 769a strb r2, [r3, #26]
hcan.Init.AutoRetransmission = DISABLE;
800084a: 4b09 ldr r3, [pc, #36] @ (8000870 <MX_CAN_Init+0x64>)
800084c: 2200 movs r2, #0
800084e: 76da strb r2, [r3, #27]
hcan.Init.ReceiveFifoLocked = DISABLE;
8000850: 4b07 ldr r3, [pc, #28] @ (8000870 <MX_CAN_Init+0x64>)
8000852: 2200 movs r2, #0
8000854: 771a strb r2, [r3, #28]
hcan.Init.TransmitFifoPriority = DISABLE;
8000856: 4b06 ldr r3, [pc, #24] @ (8000870 <MX_CAN_Init+0x64>)
8000858: 2200 movs r2, #0
800085a: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan) != HAL_OK)
800085c: 4804 ldr r0, [pc, #16] @ (8000870 <MX_CAN_Init+0x64>)
800085e: f000 f9db bl 8000c18 <HAL_CAN_Init>
8000862: 4603 mov r3, r0
8000864: 2b00 cmp r3, #0
8000866: d001 beq.n 800086c <MX_CAN_Init+0x60>
{
Error_Handler();
8000868: f000 f872 bl 8000950 <Error_Handler>
}
/* USER CODE BEGIN CAN_Init 2 */
/* USER CODE END CAN_Init 2 */
}
800086c: bf00 nop
800086e: bd80 pop {r7, pc}
8000870: 20000078 .word 0x20000078
8000874: 40006400 .word 0x40006400
08000878 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000878: b580 push {r7, lr}
800087a: b088 sub sp, #32
800087c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800087e: f107 030c add.w r3, r7, #12
8000882: 2200 movs r2, #0
8000884: 601a str r2, [r3, #0]
8000886: 605a str r2, [r3, #4]
8000888: 609a str r2, [r3, #8]
800088a: 60da str r2, [r3, #12]
800088c: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
800088e: 4b2e ldr r3, [pc, #184] @ (8000948 <MX_GPIO_Init+0xd0>)
8000890: 695b ldr r3, [r3, #20]
8000892: 4a2d ldr r2, [pc, #180] @ (8000948 <MX_GPIO_Init+0xd0>)
8000894: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8000898: 6153 str r3, [r2, #20]
800089a: 4b2b ldr r3, [pc, #172] @ (8000948 <MX_GPIO_Init+0xd0>)
800089c: 695b ldr r3, [r3, #20]
800089e: f403 0380 and.w r3, r3, #4194304 @ 0x400000
80008a2: 60bb str r3, [r7, #8]
80008a4: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80008a6: 4b28 ldr r3, [pc, #160] @ (8000948 <MX_GPIO_Init+0xd0>)
80008a8: 695b ldr r3, [r3, #20]
80008aa: 4a27 ldr r2, [pc, #156] @ (8000948 <MX_GPIO_Init+0xd0>)
80008ac: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80008b0: 6153 str r3, [r2, #20]
80008b2: 4b25 ldr r3, [pc, #148] @ (8000948 <MX_GPIO_Init+0xd0>)
80008b4: 695b ldr r3, [r3, #20]
80008b6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80008ba: 607b str r3, [r7, #4]
80008bc: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
80008be: 4b22 ldr r3, [pc, #136] @ (8000948 <MX_GPIO_Init+0xd0>)
80008c0: 695b ldr r3, [r3, #20]
80008c2: 4a21 ldr r2, [pc, #132] @ (8000948 <MX_GPIO_Init+0xd0>)
80008c4: f443 2380 orr.w r3, r3, #262144 @ 0x40000
80008c8: 6153 str r3, [r2, #20]
80008ca: 4b1f ldr r3, [pc, #124] @ (8000948 <MX_GPIO_Init+0xd0>)
80008cc: 695b ldr r3, [r3, #20]
80008ce: f403 2380 and.w r3, r3, #262144 @ 0x40000
80008d2: 603b str r3, [r7, #0]
80008d4: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, TSON_R_Pin|TSON_G_Pin|TSON_B_Pin|IMD_LED_Pin
80008d6: 2200 movs r2, #0
80008d8: 21bf movs r1, #191 @ 0xbf
80008da: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80008de: f001 fae9 bl 8001eb4 <HAL_GPIO_WritePin>
|AMS_LED_Pin|TSOFF_LED_Pin|R2D_R_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, R2D_G_Pin|R2D_B_Pin, GPIO_PIN_RESET);
80008e2: 2200 movs r2, #0
80008e4: 2103 movs r1, #3
80008e6: 4819 ldr r0, [pc, #100] @ (800094c <MX_GPIO_Init+0xd4>)
80008e8: f001 fae4 bl 8001eb4 <HAL_GPIO_WritePin>
/*Configure GPIO pins : TSON_R_Pin TSON_G_Pin TSON_B_Pin IMD_LED_Pin
AMS_LED_Pin TSOFF_LED_Pin R2D_R_Pin */
GPIO_InitStruct.Pin = TSON_R_Pin|TSON_G_Pin|TSON_B_Pin|IMD_LED_Pin
80008ec: 23bf movs r3, #191 @ 0xbf
80008ee: 60fb str r3, [r7, #12]
|AMS_LED_Pin|TSOFF_LED_Pin|R2D_R_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80008f0: 2301 movs r3, #1
80008f2: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008f4: 2300 movs r3, #0
80008f6: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80008f8: 2300 movs r3, #0
80008fa: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80008fc: f107 030c add.w r3, r7, #12
8000900: 4619 mov r1, r3
8000902: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000906: f001 f943 bl 8001b90 <HAL_GPIO_Init>
/*Configure GPIO pins : R2D_G_Pin R2D_B_Pin */
GPIO_InitStruct.Pin = R2D_G_Pin|R2D_B_Pin;
800090a: 2303 movs r3, #3
800090c: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800090e: 2301 movs r3, #1
8000910: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000912: 2300 movs r3, #0
8000914: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000916: 2300 movs r3, #0
8000918: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800091a: f107 030c add.w r3, r7, #12
800091e: 4619 mov r1, r3
8000920: 480a ldr r0, [pc, #40] @ (800094c <MX_GPIO_Init+0xd4>)
8000922: f001 f935 bl 8001b90 <HAL_GPIO_Init>
/*Configure GPIO pins : TSON_BTN_Pin SDC_Out_3V3_Pin SDC_In_3V3_Pin R2D_BTN_Pin
RMode_Out_3V3_Pin */
GPIO_InitStruct.Pin = TSON_BTN_Pin|SDC_Out_3V3_Pin|SDC_In_3V3_Pin|R2D_BTN_Pin
8000926: f248 1338 movw r3, #33080 @ 0x8138
800092a: 60fb str r3, [r7, #12]
|RMode_Out_3V3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800092c: 2300 movs r3, #0
800092e: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000930: 2300 movs r3, #0
8000932: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000934: f107 030c add.w r3, r7, #12
8000938: 4619 mov r1, r3
800093a: 4804 ldr r0, [pc, #16] @ (800094c <MX_GPIO_Init+0xd4>)
800093c: f001 f928 bl 8001b90 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000940: bf00 nop
8000942: 3720 adds r7, #32
8000944: 46bd mov sp, r7
8000946: bd80 pop {r7, pc}
8000948: 40021000 .word 0x40021000
800094c: 48000400 .word 0x48000400
08000950 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000950: b480 push {r7}
8000952: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000954: b672 cpsid i
}
8000956: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000958: bf00 nop
800095a: e7fd b.n 8000958 <Error_Handler+0x8>
0800095c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800095c: b480 push {r7}
800095e: b083 sub sp, #12
8000960: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000962: 4b0f ldr r3, [pc, #60] @ (80009a0 <HAL_MspInit+0x44>)
8000964: 699b ldr r3, [r3, #24]
8000966: 4a0e ldr r2, [pc, #56] @ (80009a0 <HAL_MspInit+0x44>)
8000968: f043 0301 orr.w r3, r3, #1
800096c: 6193 str r3, [r2, #24]
800096e: 4b0c ldr r3, [pc, #48] @ (80009a0 <HAL_MspInit+0x44>)
8000970: 699b ldr r3, [r3, #24]
8000972: f003 0301 and.w r3, r3, #1
8000976: 607b str r3, [r7, #4]
8000978: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800097a: 4b09 ldr r3, [pc, #36] @ (80009a0 <HAL_MspInit+0x44>)
800097c: 69db ldr r3, [r3, #28]
800097e: 4a08 ldr r2, [pc, #32] @ (80009a0 <HAL_MspInit+0x44>)
8000980: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000984: 61d3 str r3, [r2, #28]
8000986: 4b06 ldr r3, [pc, #24] @ (80009a0 <HAL_MspInit+0x44>)
8000988: 69db ldr r3, [r3, #28]
800098a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800098e: 603b str r3, [r7, #0]
8000990: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000992: bf00 nop
8000994: 370c adds r7, #12
8000996: 46bd mov sp, r7
8000998: f85d 7b04 ldr.w r7, [sp], #4
800099c: 4770 bx lr
800099e: bf00 nop
80009a0: 40021000 .word 0x40021000
080009a4 <HAL_CAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
80009a4: b580 push {r7, lr}
80009a6: b08a sub sp, #40 @ 0x28
80009a8: af00 add r7, sp, #0
80009aa: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80009ac: f107 0314 add.w r3, r7, #20
80009b0: 2200 movs r2, #0
80009b2: 601a str r2, [r3, #0]
80009b4: 605a str r2, [r3, #4]
80009b6: 609a str r2, [r3, #8]
80009b8: 60da str r2, [r3, #12]
80009ba: 611a str r2, [r3, #16]
if(hcan->Instance==CAN)
80009bc: 687b ldr r3, [r7, #4]
80009be: 681b ldr r3, [r3, #0]
80009c0: 4a20 ldr r2, [pc, #128] @ (8000a44 <HAL_CAN_MspInit+0xa0>)
80009c2: 4293 cmp r3, r2
80009c4: d139 bne.n 8000a3a <HAL_CAN_MspInit+0x96>
{
/* USER CODE BEGIN CAN_MspInit 0 */
/* USER CODE END CAN_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
80009c6: 4b20 ldr r3, [pc, #128] @ (8000a48 <HAL_CAN_MspInit+0xa4>)
80009c8: 69db ldr r3, [r3, #28]
80009ca: 4a1f ldr r2, [pc, #124] @ (8000a48 <HAL_CAN_MspInit+0xa4>)
80009cc: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
80009d0: 61d3 str r3, [r2, #28]
80009d2: 4b1d ldr r3, [pc, #116] @ (8000a48 <HAL_CAN_MspInit+0xa4>)
80009d4: 69db ldr r3, [r3, #28]
80009d6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80009da: 613b str r3, [r7, #16]
80009dc: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80009de: 4b1a ldr r3, [pc, #104] @ (8000a48 <HAL_CAN_MspInit+0xa4>)
80009e0: 695b ldr r3, [r3, #20]
80009e2: 4a19 ldr r2, [pc, #100] @ (8000a48 <HAL_CAN_MspInit+0xa4>)
80009e4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80009e8: 6153 str r3, [r2, #20]
80009ea: 4b17 ldr r3, [pc, #92] @ (8000a48 <HAL_CAN_MspInit+0xa4>)
80009ec: 695b ldr r3, [r3, #20]
80009ee: f403 3300 and.w r3, r3, #131072 @ 0x20000
80009f2: 60fb str r3, [r7, #12]
80009f4: 68fb ldr r3, [r7, #12]
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
80009f6: f44f 53c0 mov.w r3, #6144 @ 0x1800
80009fa: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80009fc: 2302 movs r3, #2
80009fe: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a00: 2300 movs r3, #0
8000a02: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000a04: 2303 movs r3, #3
8000a06: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
8000a08: 2309 movs r3, #9
8000a0a: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a0c: f107 0314 add.w r3, r7, #20
8000a10: 4619 mov r1, r3
8000a12: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000a16: f001 f8bb bl 8001b90 <HAL_GPIO_Init>
/* CAN interrupt Init */
HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0);
8000a1a: 2200 movs r2, #0
8000a1c: 2100 movs r1, #0
8000a1e: 2014 movs r0, #20
8000a20: f001 f87f bl 8001b22 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
8000a24: 2014 movs r0, #20
8000a26: f001 f898 bl 8001b5a <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
8000a2a: 2200 movs r2, #0
8000a2c: 2100 movs r1, #0
8000a2e: 2015 movs r0, #21
8000a30: f001 f877 bl 8001b22 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
8000a34: 2015 movs r0, #21
8000a36: f001 f890 bl 8001b5a <HAL_NVIC_EnableIRQ>
/* USER CODE END CAN_MspInit 1 */
}
}
8000a3a: bf00 nop
8000a3c: 3728 adds r7, #40 @ 0x28
8000a3e: 46bd mov sp, r7
8000a40: bd80 pop {r7, pc}
8000a42: bf00 nop
8000a44: 40006400 .word 0x40006400
8000a48: 40021000 .word 0x40021000
08000a4c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000a4c: b480 push {r7}
8000a4e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000a50: bf00 nop
8000a52: e7fd b.n 8000a50 <NMI_Handler+0x4>
08000a54 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000a54: b480 push {r7}
8000a56: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000a58: bf00 nop
8000a5a: e7fd b.n 8000a58 <HardFault_Handler+0x4>
08000a5c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000a5c: b480 push {r7}
8000a5e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000a60: bf00 nop
8000a62: e7fd b.n 8000a60 <MemManage_Handler+0x4>
08000a64 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000a64: b480 push {r7}
8000a66: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000a68: bf00 nop
8000a6a: e7fd b.n 8000a68 <BusFault_Handler+0x4>
08000a6c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000a6c: b480 push {r7}
8000a6e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000a70: bf00 nop
8000a72: e7fd b.n 8000a70 <UsageFault_Handler+0x4>
08000a74 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000a74: b480 push {r7}
8000a76: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000a78: bf00 nop
8000a7a: 46bd mov sp, r7
8000a7c: f85d 7b04 ldr.w r7, [sp], #4
8000a80: 4770 bx lr
08000a82 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000a82: b480 push {r7}
8000a84: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000a86: bf00 nop
8000a88: 46bd mov sp, r7
8000a8a: f85d 7b04 ldr.w r7, [sp], #4
8000a8e: 4770 bx lr
08000a90 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000a90: b480 push {r7}
8000a92: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000a94: bf00 nop
8000a96: 46bd mov sp, r7
8000a98: f85d 7b04 ldr.w r7, [sp], #4
8000a9c: 4770 bx lr
08000a9e <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000a9e: b580 push {r7, lr}
8000aa0: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000aa2: f000 f899 bl 8000bd8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000aa6: bf00 nop
8000aa8: bd80 pop {r7, pc}
...
08000aac <USB_LP_CAN_RX0_IRQHandler>:
/**
* @brief This function handles USB low priority or CAN_RX0 interrupts.
*/
void USB_LP_CAN_RX0_IRQHandler(void)
{
8000aac: b580 push {r7, lr}
8000aae: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN_RX0_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
8000ab0: 4802 ldr r0, [pc, #8] @ (8000abc <USB_LP_CAN_RX0_IRQHandler+0x10>)
8000ab2: f000 fd1d bl 80014f0 <HAL_CAN_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN_RX0_IRQn 1 */
}
8000ab6: bf00 nop
8000ab8: bd80 pop {r7, pc}
8000aba: bf00 nop
8000abc: 20000078 .word 0x20000078
08000ac0 <CAN_RX1_IRQHandler>:
/**
* @brief This function handles CAN RX1 interrupt.
*/
void CAN_RX1_IRQHandler(void)
{
8000ac0: b580 push {r7, lr}
8000ac2: af00 add r7, sp, #0
/* USER CODE BEGIN CAN_RX1_IRQn 0 */
/* USER CODE END CAN_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
8000ac4: 4802 ldr r0, [pc, #8] @ (8000ad0 <CAN_RX1_IRQHandler+0x10>)
8000ac6: f000 fd13 bl 80014f0 <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN_RX1_IRQn 1 */
/* USER CODE END CAN_RX1_IRQn 1 */
}
8000aca: bf00 nop
8000acc: bd80 pop {r7, pc}
8000ace: bf00 nop
8000ad0: 20000078 .word 0x20000078
08000ad4 <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
8000ad4: b480 push {r7}
8000ad6: af00 add r7, sp, #0
/* FPU settings --------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000ad8: 4b06 ldr r3, [pc, #24] @ (8000af4 <SystemInit+0x20>)
8000ada: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8000ade: 4a05 ldr r2, [pc, #20] @ (8000af4 <SystemInit+0x20>)
8000ae0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8000ae4: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000ae8: bf00 nop
8000aea: 46bd mov sp, r7
8000aec: f85d 7b04 ldr.w r7, [sp], #4
8000af0: 4770 bx lr
8000af2: bf00 nop
8000af4: e000ed00 .word 0xe000ed00
08000af8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
8000af8: f8df d034 ldr.w sp, [pc, #52] @ 8000b30 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
8000afc: f7ff ffea bl 8000ad4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000b00: 480c ldr r0, [pc, #48] @ (8000b34 <LoopForever+0x6>)
ldr r1, =_edata
8000b02: 490d ldr r1, [pc, #52] @ (8000b38 <LoopForever+0xa>)
ldr r2, =_sidata
8000b04: 4a0d ldr r2, [pc, #52] @ (8000b3c <LoopForever+0xe>)
movs r3, #0
8000b06: 2300 movs r3, #0
b LoopCopyDataInit
8000b08: e002 b.n 8000b10 <LoopCopyDataInit>
08000b0a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000b0a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000b0c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000b0e: 3304 adds r3, #4
08000b10 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000b10: 18c4 adds r4, r0, r3
cmp r4, r1
8000b12: 428c cmp r4, r1
bcc CopyDataInit
8000b14: d3f9 bcc.n 8000b0a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000b16: 4a0a ldr r2, [pc, #40] @ (8000b40 <LoopForever+0x12>)
ldr r4, =_ebss
8000b18: 4c0a ldr r4, [pc, #40] @ (8000b44 <LoopForever+0x16>)
movs r3, #0
8000b1a: 2300 movs r3, #0
b LoopFillZerobss
8000b1c: e001 b.n 8000b22 <LoopFillZerobss>
08000b1e <FillZerobss>:
FillZerobss:
str r3, [r2]
8000b1e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000b20: 3204 adds r2, #4
08000b22 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000b22: 42a2 cmp r2, r4
bcc FillZerobss
8000b24: d3fb bcc.n 8000b1e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000b26: f002 fc0f bl 8003348 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000b2a: f7ff fc6b bl 8000404 <main>
08000b2e <LoopForever>:
LoopForever:
b LoopForever
8000b2e: e7fe b.n 8000b2e <LoopForever>
ldr sp, =_estack /* Atollic update: set stack pointer */
8000b30: 20008000 .word 0x20008000
ldr r0, =_sdata
8000b34: 20000000 .word 0x20000000
ldr r1, =_edata
8000b38: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000b3c: 080033e0 .word 0x080033e0
ldr r2, =_sbss
8000b40: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000b44: 200000f4 .word 0x200000f4
08000b48 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000b48: e7fe b.n 8000b48 <ADC1_2_IRQHandler>
...
08000b4c <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000b4c: b580 push {r7, lr}
8000b4e: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000b50: 4b08 ldr r3, [pc, #32] @ (8000b74 <HAL_Init+0x28>)
8000b52: 681b ldr r3, [r3, #0]
8000b54: 4a07 ldr r2, [pc, #28] @ (8000b74 <HAL_Init+0x28>)
8000b56: f043 0310 orr.w r3, r3, #16
8000b5a: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000b5c: 2003 movs r0, #3
8000b5e: f000 ffd5 bl 8001b0c <HAL_NVIC_SetPriorityGrouping>
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000b62: 200f movs r0, #15
8000b64: f000 f808 bl 8000b78 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000b68: f7ff fef8 bl 800095c <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000b6c: 2300 movs r3, #0
}
8000b6e: 4618 mov r0, r3
8000b70: bd80 pop {r7, pc}
8000b72: bf00 nop
8000b74: 40022000 .word 0x40022000
08000b78 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000b78: b580 push {r7, lr}
8000b7a: b082 sub sp, #8
8000b7c: af00 add r7, sp, #0
8000b7e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000b80: 4b12 ldr r3, [pc, #72] @ (8000bcc <HAL_InitTick+0x54>)
8000b82: 681a ldr r2, [r3, #0]
8000b84: 4b12 ldr r3, [pc, #72] @ (8000bd0 <HAL_InitTick+0x58>)
8000b86: 781b ldrb r3, [r3, #0]
8000b88: 4619 mov r1, r3
8000b8a: f44f 737a mov.w r3, #1000 @ 0x3e8
8000b8e: fbb3 f3f1 udiv r3, r3, r1
8000b92: fbb2 f3f3 udiv r3, r2, r3
8000b96: 4618 mov r0, r3
8000b98: f000 ffed bl 8001b76 <HAL_SYSTICK_Config>
8000b9c: 4603 mov r3, r0
8000b9e: 2b00 cmp r3, #0
8000ba0: d001 beq.n 8000ba6 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000ba2: 2301 movs r3, #1
8000ba4: e00e b.n 8000bc4 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000ba6: 687b ldr r3, [r7, #4]
8000ba8: 2b0f cmp r3, #15
8000baa: d80a bhi.n 8000bc2 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000bac: 2200 movs r2, #0
8000bae: 6879 ldr r1, [r7, #4]
8000bb0: f04f 30ff mov.w r0, #4294967295
8000bb4: f000 ffb5 bl 8001b22 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000bb8: 4a06 ldr r2, [pc, #24] @ (8000bd4 <HAL_InitTick+0x5c>)
8000bba: 687b ldr r3, [r7, #4]
8000bbc: 6013 str r3, [r2, #0]
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000bbe: 2300 movs r3, #0
8000bc0: e000 b.n 8000bc4 <HAL_InitTick+0x4c>
return HAL_ERROR;
8000bc2: 2301 movs r3, #1
}
8000bc4: 4618 mov r0, r3
8000bc6: 3708 adds r7, #8
8000bc8: 46bd mov sp, r7
8000bca: bd80 pop {r7, pc}
8000bcc: 20000000 .word 0x20000000
8000bd0: 20000008 .word 0x20000008
8000bd4: 20000004 .word 0x20000004
08000bd8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000bd8: b480 push {r7}
8000bda: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000bdc: 4b06 ldr r3, [pc, #24] @ (8000bf8 <HAL_IncTick+0x20>)
8000bde: 781b ldrb r3, [r3, #0]
8000be0: 461a mov r2, r3
8000be2: 4b06 ldr r3, [pc, #24] @ (8000bfc <HAL_IncTick+0x24>)
8000be4: 681b ldr r3, [r3, #0]
8000be6: 4413 add r3, r2
8000be8: 4a04 ldr r2, [pc, #16] @ (8000bfc <HAL_IncTick+0x24>)
8000bea: 6013 str r3, [r2, #0]
}
8000bec: bf00 nop
8000bee: 46bd mov sp, r7
8000bf0: f85d 7b04 ldr.w r7, [sp], #4
8000bf4: 4770 bx lr
8000bf6: bf00 nop
8000bf8: 20000008 .word 0x20000008
8000bfc: 200000f0 .word 0x200000f0
08000c00 <HAL_GetTick>:
* @note The function is declared as __Weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000c00: b480 push {r7}
8000c02: af00 add r7, sp, #0
return uwTick;
8000c04: 4b03 ldr r3, [pc, #12] @ (8000c14 <HAL_GetTick+0x14>)
8000c06: 681b ldr r3, [r3, #0]
}
8000c08: 4618 mov r0, r3
8000c0a: 46bd mov sp, r7
8000c0c: f85d 7b04 ldr.w r7, [sp], #4
8000c10: 4770 bx lr
8000c12: bf00 nop
8000c14: 200000f0 .word 0x200000f0
08000c18 <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
8000c18: b580 push {r7, lr}
8000c1a: b084 sub sp, #16
8000c1c: af00 add r7, sp, #0
8000c1e: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
8000c20: 687b ldr r3, [r7, #4]
8000c22: 2b00 cmp r3, #0
8000c24: d101 bne.n 8000c2a <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
8000c26: 2301 movs r3, #1
8000c28: e11c b.n 8000e64 <HAL_CAN_Init+0x24c>
assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
if (hcan->State == HAL_CAN_STATE_RESET)
8000c2a: 687b ldr r3, [r7, #4]
8000c2c: f893 3020 ldrb.w r3, [r3, #32]
8000c30: b2db uxtb r3, r3
8000c32: 2b00 cmp r3, #0
8000c34: d131 bne.n 8000c9a <HAL_CAN_Init+0x82>
{
/* Reset callbacks to legacy functions */
hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */
8000c36: 687b ldr r3, [r7, #4]
8000c38: 4a8c ldr r2, [pc, #560] @ (8000e6c <HAL_CAN_Init+0x254>)
8000c3a: 641a str r2, [r3, #64] @ 0x40
hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */
8000c3c: 687b ldr r3, [r7, #4]
8000c3e: 4a8c ldr r2, [pc, #560] @ (8000e70 <HAL_CAN_Init+0x258>)
8000c40: 645a str r2, [r3, #68] @ 0x44
hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */
8000c42: 687b ldr r3, [r7, #4]
8000c44: 4a8b ldr r2, [pc, #556] @ (8000e74 <HAL_CAN_Init+0x25c>)
8000c46: 649a str r2, [r3, #72] @ 0x48
hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */
8000c48: 687b ldr r3, [r7, #4]
8000c4a: 4a8b ldr r2, [pc, #556] @ (8000e78 <HAL_CAN_Init+0x260>)
8000c4c: 64da str r2, [r3, #76] @ 0x4c
hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
8000c4e: 687b ldr r3, [r7, #4]
8000c50: 4a8a ldr r2, [pc, #552] @ (8000e7c <HAL_CAN_Init+0x264>)
8000c52: 629a str r2, [r3, #40] @ 0x28
hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
8000c54: 687b ldr r3, [r7, #4]
8000c56: 4a8a ldr r2, [pc, #552] @ (8000e80 <HAL_CAN_Init+0x268>)
8000c58: 62da str r2, [r3, #44] @ 0x2c
hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
8000c5a: 687b ldr r3, [r7, #4]
8000c5c: 4a89 ldr r2, [pc, #548] @ (8000e84 <HAL_CAN_Init+0x26c>)
8000c5e: 631a str r2, [r3, #48] @ 0x30
hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */
8000c60: 687b ldr r3, [r7, #4]
8000c62: 4a89 ldr r2, [pc, #548] @ (8000e88 <HAL_CAN_Init+0x270>)
8000c64: 635a str r2, [r3, #52] @ 0x34
hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */
8000c66: 687b ldr r3, [r7, #4]
8000c68: 4a88 ldr r2, [pc, #544] @ (8000e8c <HAL_CAN_Init+0x274>)
8000c6a: 639a str r2, [r3, #56] @ 0x38
hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */
8000c6c: 687b ldr r3, [r7, #4]
8000c6e: 4a88 ldr r2, [pc, #544] @ (8000e90 <HAL_CAN_Init+0x278>)
8000c70: 63da str r2, [r3, #60] @ 0x3c
hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */
8000c72: 687b ldr r3, [r7, #4]
8000c74: 4a87 ldr r2, [pc, #540] @ (8000e94 <HAL_CAN_Init+0x27c>)
8000c76: 651a str r2, [r3, #80] @ 0x50
hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */
8000c78: 687b ldr r3, [r7, #4]
8000c7a: 4a87 ldr r2, [pc, #540] @ (8000e98 <HAL_CAN_Init+0x280>)
8000c7c: 655a str r2, [r3, #84] @ 0x54
hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */
8000c7e: 687b ldr r3, [r7, #4]
8000c80: 4a86 ldr r2, [pc, #536] @ (8000e9c <HAL_CAN_Init+0x284>)
8000c82: 659a str r2, [r3, #88] @ 0x58
if (hcan->MspInitCallback == NULL)
8000c84: 687b ldr r3, [r7, #4]
8000c86: 6ddb ldr r3, [r3, #92] @ 0x5c
8000c88: 2b00 cmp r3, #0
8000c8a: d102 bne.n 8000c92 <HAL_CAN_Init+0x7a>
{
hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
8000c8c: 687b ldr r3, [r7, #4]
8000c8e: 4a84 ldr r2, [pc, #528] @ (8000ea0 <HAL_CAN_Init+0x288>)
8000c90: 65da str r2, [r3, #92] @ 0x5c
}
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
8000c92: 687b ldr r3, [r7, #4]
8000c94: 6ddb ldr r3, [r3, #92] @ 0x5c
8000c96: 6878 ldr r0, [r7, #4]
8000c98: 4798 blx r3
HAL_CAN_MspInit(hcan);
}
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8000c9a: 687b ldr r3, [r7, #4]
8000c9c: 681b ldr r3, [r3, #0]
8000c9e: 681a ldr r2, [r3, #0]
8000ca0: 687b ldr r3, [r7, #4]
8000ca2: 681b ldr r3, [r3, #0]
8000ca4: f042 0201 orr.w r2, r2, #1
8000ca8: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000caa: f7ff ffa9 bl 8000c00 <HAL_GetTick>
8000cae: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000cb0: e012 b.n 8000cd8 <HAL_CAN_Init+0xc0>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000cb2: f7ff ffa5 bl 8000c00 <HAL_GetTick>
8000cb6: 4602 mov r2, r0
8000cb8: 68fb ldr r3, [r7, #12]
8000cba: 1ad3 subs r3, r2, r3
8000cbc: 2b0a cmp r3, #10
8000cbe: d90b bls.n 8000cd8 <HAL_CAN_Init+0xc0>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000cc0: 687b ldr r3, [r7, #4]
8000cc2: 6a5b ldr r3, [r3, #36] @ 0x24
8000cc4: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8000cc8: 687b ldr r3, [r7, #4]
8000cca: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000ccc: 687b ldr r3, [r7, #4]
8000cce: 2205 movs r2, #5
8000cd0: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000cd4: 2301 movs r3, #1
8000cd6: e0c5 b.n 8000e64 <HAL_CAN_Init+0x24c>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000cd8: 687b ldr r3, [r7, #4]
8000cda: 681b ldr r3, [r3, #0]
8000cdc: 685b ldr r3, [r3, #4]
8000cde: f003 0301 and.w r3, r3, #1
8000ce2: 2b00 cmp r3, #0
8000ce4: d0e5 beq.n 8000cb2 <HAL_CAN_Init+0x9a>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
8000ce6: 687b ldr r3, [r7, #4]
8000ce8: 681b ldr r3, [r3, #0]
8000cea: 681a ldr r2, [r3, #0]
8000cec: 687b ldr r3, [r7, #4]
8000cee: 681b ldr r3, [r3, #0]
8000cf0: f022 0202 bic.w r2, r2, #2
8000cf4: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000cf6: f7ff ff83 bl 8000c00 <HAL_GetTick>
8000cfa: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000cfc: e012 b.n 8000d24 <HAL_CAN_Init+0x10c>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000cfe: f7ff ff7f bl 8000c00 <HAL_GetTick>
8000d02: 4602 mov r2, r0
8000d04: 68fb ldr r3, [r7, #12]
8000d06: 1ad3 subs r3, r2, r3
8000d08: 2b0a cmp r3, #10
8000d0a: d90b bls.n 8000d24 <HAL_CAN_Init+0x10c>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000d0c: 687b ldr r3, [r7, #4]
8000d0e: 6a5b ldr r3, [r3, #36] @ 0x24
8000d10: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8000d14: 687b ldr r3, [r7, #4]
8000d16: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000d18: 687b ldr r3, [r7, #4]
8000d1a: 2205 movs r2, #5
8000d1c: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000d20: 2301 movs r3, #1
8000d22: e09f b.n 8000e64 <HAL_CAN_Init+0x24c>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000d24: 687b ldr r3, [r7, #4]
8000d26: 681b ldr r3, [r3, #0]
8000d28: 685b ldr r3, [r3, #4]
8000d2a: f003 0302 and.w r3, r3, #2
8000d2e: 2b00 cmp r3, #0
8000d30: d1e5 bne.n 8000cfe <HAL_CAN_Init+0xe6>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
8000d32: 687b ldr r3, [r7, #4]
8000d34: 7e1b ldrb r3, [r3, #24]
8000d36: 2b01 cmp r3, #1
8000d38: d108 bne.n 8000d4c <HAL_CAN_Init+0x134>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000d3a: 687b ldr r3, [r7, #4]
8000d3c: 681b ldr r3, [r3, #0]
8000d3e: 681a ldr r2, [r3, #0]
8000d40: 687b ldr r3, [r7, #4]
8000d42: 681b ldr r3, [r3, #0]
8000d44: f042 0280 orr.w r2, r2, #128 @ 0x80
8000d48: 601a str r2, [r3, #0]
8000d4a: e007 b.n 8000d5c <HAL_CAN_Init+0x144>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000d4c: 687b ldr r3, [r7, #4]
8000d4e: 681b ldr r3, [r3, #0]
8000d50: 681a ldr r2, [r3, #0]
8000d52: 687b ldr r3, [r7, #4]
8000d54: 681b ldr r3, [r3, #0]
8000d56: f022 0280 bic.w r2, r2, #128 @ 0x80
8000d5a: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
8000d5c: 687b ldr r3, [r7, #4]
8000d5e: 7e5b ldrb r3, [r3, #25]
8000d60: 2b01 cmp r3, #1
8000d62: d108 bne.n 8000d76 <HAL_CAN_Init+0x15e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000d64: 687b ldr r3, [r7, #4]
8000d66: 681b ldr r3, [r3, #0]
8000d68: 681a ldr r2, [r3, #0]
8000d6a: 687b ldr r3, [r7, #4]
8000d6c: 681b ldr r3, [r3, #0]
8000d6e: f042 0240 orr.w r2, r2, #64 @ 0x40
8000d72: 601a str r2, [r3, #0]
8000d74: e007 b.n 8000d86 <HAL_CAN_Init+0x16e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000d76: 687b ldr r3, [r7, #4]
8000d78: 681b ldr r3, [r3, #0]
8000d7a: 681a ldr r2, [r3, #0]
8000d7c: 687b ldr r3, [r7, #4]
8000d7e: 681b ldr r3, [r3, #0]
8000d80: f022 0240 bic.w r2, r2, #64 @ 0x40
8000d84: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
8000d86: 687b ldr r3, [r7, #4]
8000d88: 7e9b ldrb r3, [r3, #26]
8000d8a: 2b01 cmp r3, #1
8000d8c: d108 bne.n 8000da0 <HAL_CAN_Init+0x188>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000d8e: 687b ldr r3, [r7, #4]
8000d90: 681b ldr r3, [r3, #0]
8000d92: 681a ldr r2, [r3, #0]
8000d94: 687b ldr r3, [r7, #4]
8000d96: 681b ldr r3, [r3, #0]
8000d98: f042 0220 orr.w r2, r2, #32
8000d9c: 601a str r2, [r3, #0]
8000d9e: e007 b.n 8000db0 <HAL_CAN_Init+0x198>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000da0: 687b ldr r3, [r7, #4]
8000da2: 681b ldr r3, [r3, #0]
8000da4: 681a ldr r2, [r3, #0]
8000da6: 687b ldr r3, [r7, #4]
8000da8: 681b ldr r3, [r3, #0]
8000daa: f022 0220 bic.w r2, r2, #32
8000dae: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
8000db0: 687b ldr r3, [r7, #4]
8000db2: 7edb ldrb r3, [r3, #27]
8000db4: 2b01 cmp r3, #1
8000db6: d108 bne.n 8000dca <HAL_CAN_Init+0x1b2>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000db8: 687b ldr r3, [r7, #4]
8000dba: 681b ldr r3, [r3, #0]
8000dbc: 681a ldr r2, [r3, #0]
8000dbe: 687b ldr r3, [r7, #4]
8000dc0: 681b ldr r3, [r3, #0]
8000dc2: f022 0210 bic.w r2, r2, #16
8000dc6: 601a str r2, [r3, #0]
8000dc8: e007 b.n 8000dda <HAL_CAN_Init+0x1c2>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000dca: 687b ldr r3, [r7, #4]
8000dcc: 681b ldr r3, [r3, #0]
8000dce: 681a ldr r2, [r3, #0]
8000dd0: 687b ldr r3, [r7, #4]
8000dd2: 681b ldr r3, [r3, #0]
8000dd4: f042 0210 orr.w r2, r2, #16
8000dd8: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
8000dda: 687b ldr r3, [r7, #4]
8000ddc: 7f1b ldrb r3, [r3, #28]
8000dde: 2b01 cmp r3, #1
8000de0: d108 bne.n 8000df4 <HAL_CAN_Init+0x1dc>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000de2: 687b ldr r3, [r7, #4]
8000de4: 681b ldr r3, [r3, #0]
8000de6: 681a ldr r2, [r3, #0]
8000de8: 687b ldr r3, [r7, #4]
8000dea: 681b ldr r3, [r3, #0]
8000dec: f042 0208 orr.w r2, r2, #8
8000df0: 601a str r2, [r3, #0]
8000df2: e007 b.n 8000e04 <HAL_CAN_Init+0x1ec>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000df4: 687b ldr r3, [r7, #4]
8000df6: 681b ldr r3, [r3, #0]
8000df8: 681a ldr r2, [r3, #0]
8000dfa: 687b ldr r3, [r7, #4]
8000dfc: 681b ldr r3, [r3, #0]
8000dfe: f022 0208 bic.w r2, r2, #8
8000e02: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
8000e04: 687b ldr r3, [r7, #4]
8000e06: 7f5b ldrb r3, [r3, #29]
8000e08: 2b01 cmp r3, #1
8000e0a: d108 bne.n 8000e1e <HAL_CAN_Init+0x206>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000e0c: 687b ldr r3, [r7, #4]
8000e0e: 681b ldr r3, [r3, #0]
8000e10: 681a ldr r2, [r3, #0]
8000e12: 687b ldr r3, [r7, #4]
8000e14: 681b ldr r3, [r3, #0]
8000e16: f042 0204 orr.w r2, r2, #4
8000e1a: 601a str r2, [r3, #0]
8000e1c: e007 b.n 8000e2e <HAL_CAN_Init+0x216>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000e1e: 687b ldr r3, [r7, #4]
8000e20: 681b ldr r3, [r3, #0]
8000e22: 681a ldr r2, [r3, #0]
8000e24: 687b ldr r3, [r7, #4]
8000e26: 681b ldr r3, [r3, #0]
8000e28: f022 0204 bic.w r2, r2, #4
8000e2c: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
8000e2e: 687b ldr r3, [r7, #4]
8000e30: 689a ldr r2, [r3, #8]
8000e32: 687b ldr r3, [r7, #4]
8000e34: 68db ldr r3, [r3, #12]
8000e36: 431a orrs r2, r3
8000e38: 687b ldr r3, [r7, #4]
8000e3a: 691b ldr r3, [r3, #16]
8000e3c: 431a orrs r2, r3
8000e3e: 687b ldr r3, [r7, #4]
8000e40: 695b ldr r3, [r3, #20]
8000e42: ea42 0103 orr.w r1, r2, r3
8000e46: 687b ldr r3, [r7, #4]
8000e48: 685b ldr r3, [r3, #4]
8000e4a: 1e5a subs r2, r3, #1
8000e4c: 687b ldr r3, [r7, #4]
8000e4e: 681b ldr r3, [r3, #0]
8000e50: 430a orrs r2, r1
8000e52: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8000e54: 687b ldr r3, [r7, #4]
8000e56: 2200 movs r2, #0
8000e58: 625a str r2, [r3, #36] @ 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
8000e5a: 687b ldr r3, [r7, #4]
8000e5c: 2201 movs r2, #1
8000e5e: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
8000e62: 2300 movs r3, #0
}
8000e64: 4618 mov r0, r3
8000e66: 3710 adds r7, #16
8000e68: 46bd mov sp, r7
8000e6a: bd80 pop {r7, pc}
8000e6c: 080003ad .word 0x080003ad
8000e70: 080018f3 .word 0x080018f3
8000e74: 08001907 .word 0x08001907
8000e78: 0800191b .word 0x0800191b
8000e7c: 0800187b .word 0x0800187b
8000e80: 0800188f .word 0x0800188f
8000e84: 080018a3 .word 0x080018a3
8000e88: 080018b7 .word 0x080018b7
8000e8c: 080018cb .word 0x080018cb
8000e90: 080018df .word 0x080018df
8000e94: 0800192f .word 0x0800192f
8000e98: 08001943 .word 0x08001943
8000e9c: 08001957 .word 0x08001957
8000ea0: 080009a5 .word 0x080009a5
08000ea4 <HAL_CAN_ConfigFilter>:
* @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
{
8000ea4: b480 push {r7}
8000ea6: b087 sub sp, #28
8000ea8: af00 add r7, sp, #0
8000eaa: 6078 str r0, [r7, #4]
8000eac: 6039 str r1, [r7, #0]
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
8000eae: 687b ldr r3, [r7, #4]
8000eb0: 681b ldr r3, [r3, #0]
8000eb2: 617b str r3, [r7, #20]
HAL_CAN_StateTypeDef state = hcan->State;
8000eb4: 687b ldr r3, [r7, #4]
8000eb6: f893 3020 ldrb.w r3, [r3, #32]
8000eba: 74fb strb r3, [r7, #19]
if ((state == HAL_CAN_STATE_READY) ||
8000ebc: 7cfb ldrb r3, [r7, #19]
8000ebe: 2b01 cmp r3, #1
8000ec0: d003 beq.n 8000eca <HAL_CAN_ConfigFilter+0x26>
8000ec2: 7cfb ldrb r3, [r7, #19]
8000ec4: 2b02 cmp r3, #2
8000ec6: f040 80aa bne.w 800101e <HAL_CAN_ConfigFilter+0x17a>
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
8000eca: 697b ldr r3, [r7, #20]
8000ecc: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200
8000ed0: f043 0201 orr.w r2, r3, #1
8000ed4: 697b ldr r3, [r7, #20]
8000ed6: f8c3 2200 str.w r2, [r3, #512] @ 0x200
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
8000eda: 683b ldr r3, [r7, #0]
8000edc: 695b ldr r3, [r3, #20]
8000ede: f003 031f and.w r3, r3, #31
8000ee2: 2201 movs r2, #1
8000ee4: fa02 f303 lsl.w r3, r2, r3
8000ee8: 60fb str r3, [r7, #12]
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
8000eea: 697b ldr r3, [r7, #20]
8000eec: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c
8000ef0: 68fb ldr r3, [r7, #12]
8000ef2: 43db mvns r3, r3
8000ef4: 401a ands r2, r3
8000ef6: 697b ldr r3, [r7, #20]
8000ef8: f8c3 221c str.w r2, [r3, #540] @ 0x21c
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
8000efc: 683b ldr r3, [r7, #0]
8000efe: 69db ldr r3, [r3, #28]
8000f00: 2b00 cmp r3, #0
8000f02: d123 bne.n 8000f4c <HAL_CAN_ConfigFilter+0xa8>
{
/* 16-bit scale for the filter */
CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
8000f04: 697b ldr r3, [r7, #20]
8000f06: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c
8000f0a: 68fb ldr r3, [r7, #12]
8000f0c: 43db mvns r3, r3
8000f0e: 401a ands r2, r3
8000f10: 697b ldr r3, [r7, #20]
8000f12: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8000f16: 683b ldr r3, [r7, #0]
8000f18: 68db ldr r3, [r3, #12]
8000f1a: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8000f1c: 683b ldr r3, [r7, #0]
8000f1e: 685b ldr r3, [r3, #4]
8000f20: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000f22: 683a ldr r2, [r7, #0]
8000f24: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8000f26: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000f28: 697b ldr r3, [r7, #20]
8000f2a: 3248 adds r2, #72 @ 0x48
8000f2c: f843 1032 str.w r1, [r3, r2, lsl #3]
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000f30: 683b ldr r3, [r7, #0]
8000f32: 689b ldr r3, [r3, #8]
8000f34: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
8000f36: 683b ldr r3, [r7, #0]
8000f38: 681b ldr r3, [r3, #0]
8000f3a: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000f3c: 683b ldr r3, [r7, #0]
8000f3e: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000f40: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000f42: 6979 ldr r1, [r7, #20]
8000f44: 3348 adds r3, #72 @ 0x48
8000f46: 00db lsls r3, r3, #3
8000f48: 440b add r3, r1
8000f4a: 605a str r2, [r3, #4]
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
8000f4c: 683b ldr r3, [r7, #0]
8000f4e: 69db ldr r3, [r3, #28]
8000f50: 2b01 cmp r3, #1
8000f52: d122 bne.n 8000f9a <HAL_CAN_ConfigFilter+0xf6>
{
/* 32-bit scale for the filter */
SET_BIT(can_ip->FS1R, filternbrbitpos);
8000f54: 697b ldr r3, [r7, #20]
8000f56: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c
8000f5a: 68fb ldr r3, [r7, #12]
8000f5c: 431a orrs r2, r3
8000f5e: 697b ldr r3, [r7, #20]
8000f60: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* 32-bit identifier or First 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8000f64: 683b ldr r3, [r7, #0]
8000f66: 681b ldr r3, [r3, #0]
8000f68: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8000f6a: 683b ldr r3, [r7, #0]
8000f6c: 685b ldr r3, [r3, #4]
8000f6e: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000f70: 683a ldr r2, [r7, #0]
8000f72: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8000f74: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000f76: 697b ldr r3, [r7, #20]
8000f78: 3248 adds r2, #72 @ 0x48
8000f7a: f843 1032 str.w r1, [r3, r2, lsl #3]
/* 32-bit mask or Second 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000f7e: 683b ldr r3, [r7, #0]
8000f80: 689b ldr r3, [r3, #8]
8000f82: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
8000f84: 683b ldr r3, [r7, #0]
8000f86: 68db ldr r3, [r3, #12]
8000f88: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000f8a: 683b ldr r3, [r7, #0]
8000f8c: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000f8e: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000f90: 6979 ldr r1, [r7, #20]
8000f92: 3348 adds r3, #72 @ 0x48
8000f94: 00db lsls r3, r3, #3
8000f96: 440b add r3, r1
8000f98: 605a str r2, [r3, #4]
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
8000f9a: 683b ldr r3, [r7, #0]
8000f9c: 699b ldr r3, [r3, #24]
8000f9e: 2b00 cmp r3, #0
8000fa0: d109 bne.n 8000fb6 <HAL_CAN_ConfigFilter+0x112>
{
/* Id/Mask mode for the filter*/
CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
8000fa2: 697b ldr r3, [r7, #20]
8000fa4: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8000fa8: 68fb ldr r3, [r7, #12]
8000faa: 43db mvns r3, r3
8000fac: 401a ands r2, r3
8000fae: 697b ldr r3, [r7, #20]
8000fb0: f8c3 2204 str.w r2, [r3, #516] @ 0x204
8000fb4: e007 b.n 8000fc6 <HAL_CAN_ConfigFilter+0x122>
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/* Identifier list mode for the filter*/
SET_BIT(can_ip->FM1R, filternbrbitpos);
8000fb6: 697b ldr r3, [r7, #20]
8000fb8: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
8000fbc: 68fb ldr r3, [r7, #12]
8000fbe: 431a orrs r2, r3
8000fc0: 697b ldr r3, [r7, #20]
8000fc2: f8c3 2204 str.w r2, [r3, #516] @ 0x204
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
8000fc6: 683b ldr r3, [r7, #0]
8000fc8: 691b ldr r3, [r3, #16]
8000fca: 2b00 cmp r3, #0
8000fcc: d109 bne.n 8000fe2 <HAL_CAN_ConfigFilter+0x13e>
{
/* FIFO 0 assignation for the filter */
CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
8000fce: 697b ldr r3, [r7, #20]
8000fd0: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214
8000fd4: 68fb ldr r3, [r7, #12]
8000fd6: 43db mvns r3, r3
8000fd8: 401a ands r2, r3
8000fda: 697b ldr r3, [r7, #20]
8000fdc: f8c3 2214 str.w r2, [r3, #532] @ 0x214
8000fe0: e007 b.n 8000ff2 <HAL_CAN_ConfigFilter+0x14e>
}
else
{
/* FIFO 1 assignation for the filter */
SET_BIT(can_ip->FFA1R, filternbrbitpos);
8000fe2: 697b ldr r3, [r7, #20]
8000fe4: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214
8000fe8: 68fb ldr r3, [r7, #12]
8000fea: 431a orrs r2, r3
8000fec: 697b ldr r3, [r7, #20]
8000fee: f8c3 2214 str.w r2, [r3, #532] @ 0x214
}
/* Filter activation */
if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
8000ff2: 683b ldr r3, [r7, #0]
8000ff4: 6a1b ldr r3, [r3, #32]
8000ff6: 2b01 cmp r3, #1
8000ff8: d107 bne.n 800100a <HAL_CAN_ConfigFilter+0x166>
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
8000ffa: 697b ldr r3, [r7, #20]
8000ffc: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c
8001000: 68fb ldr r3, [r7, #12]
8001002: 431a orrs r2, r3
8001004: 697b ldr r3, [r7, #20]
8001006: f8c3 221c str.w r2, [r3, #540] @ 0x21c
}
/* Leave the initialisation mode for the filter */
CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
800100a: 697b ldr r3, [r7, #20]
800100c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200
8001010: f023 0201 bic.w r2, r3, #1
8001014: 697b ldr r3, [r7, #20]
8001016: f8c3 2200 str.w r2, [r3, #512] @ 0x200
/* Return function status */
return HAL_OK;
800101a: 2300 movs r3, #0
800101c: e006 b.n 800102c <HAL_CAN_ConfigFilter+0x188>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
800101e: 687b ldr r3, [r7, #4]
8001020: 6a5b ldr r3, [r3, #36] @ 0x24
8001022: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8001026: 687b ldr r3, [r7, #4]
8001028: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
800102a: 2301 movs r3, #1
}
}
800102c: 4618 mov r0, r3
800102e: 371c adds r7, #28
8001030: 46bd mov sp, r7
8001032: f85d 7b04 ldr.w r7, [sp], #4
8001036: 4770 bx lr
08001038 <HAL_CAN_Start>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
8001038: b580 push {r7, lr}
800103a: b084 sub sp, #16
800103c: af00 add r7, sp, #0
800103e: 6078 str r0, [r7, #4]
uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
8001040: 687b ldr r3, [r7, #4]
8001042: f893 3020 ldrb.w r3, [r3, #32]
8001046: b2db uxtb r3, r3
8001048: 2b01 cmp r3, #1
800104a: d12e bne.n 80010aa <HAL_CAN_Start+0x72>
{
/* Change CAN peripheral state */
hcan->State = HAL_CAN_STATE_LISTENING;
800104c: 687b ldr r3, [r7, #4]
800104e: 2202 movs r2, #2
8001050: f883 2020 strb.w r2, [r3, #32]
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8001054: 687b ldr r3, [r7, #4]
8001056: 681b ldr r3, [r3, #0]
8001058: 681a ldr r2, [r3, #0]
800105a: 687b ldr r3, [r7, #4]
800105c: 681b ldr r3, [r3, #0]
800105e: f022 0201 bic.w r2, r2, #1
8001062: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001064: f7ff fdcc bl 8000c00 <HAL_GetTick>
8001068: 60f8 str r0, [r7, #12]
/* Wait the acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
800106a: e012 b.n 8001092 <HAL_CAN_Start+0x5a>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
800106c: f7ff fdc8 bl 8000c00 <HAL_GetTick>
8001070: 4602 mov r2, r0
8001072: 68fb ldr r3, [r7, #12]
8001074: 1ad3 subs r3, r2, r3
8001076: 2b0a cmp r3, #10
8001078: d90b bls.n 8001092 <HAL_CAN_Start+0x5a>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
800107a: 687b ldr r3, [r7, #4]
800107c: 6a5b ldr r3, [r3, #36] @ 0x24
800107e: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8001082: 687b ldr r3, [r7, #4]
8001084: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8001086: 687b ldr r3, [r7, #4]
8001088: 2205 movs r2, #5
800108a: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
800108e: 2301 movs r3, #1
8001090: e012 b.n 80010b8 <HAL_CAN_Start+0x80>
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
8001092: 687b ldr r3, [r7, #4]
8001094: 681b ldr r3, [r3, #0]
8001096: 685b ldr r3, [r3, #4]
8001098: f003 0301 and.w r3, r3, #1
800109c: 2b00 cmp r3, #0
800109e: d1e5 bne.n 800106c <HAL_CAN_Start+0x34>
}
}
/* Reset the CAN ErrorCode */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
80010a0: 687b ldr r3, [r7, #4]
80010a2: 2200 movs r2, #0
80010a4: 625a str r2, [r3, #36] @ 0x24
/* Return function status */
return HAL_OK;
80010a6: 2300 movs r3, #0
80010a8: e006 b.n 80010b8 <HAL_CAN_Start+0x80>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
80010aa: 687b ldr r3, [r7, #4]
80010ac: 6a5b ldr r3, [r3, #36] @ 0x24
80010ae: f443 2200 orr.w r2, r3, #524288 @ 0x80000
80010b2: 687b ldr r3, [r7, #4]
80010b4: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80010b6: 2301 movs r3, #1
}
}
80010b8: 4618 mov r0, r3
80010ba: 3710 adds r7, #16
80010bc: 46bd mov sp, r7
80010be: bd80 pop {r7, pc}
080010c0 <HAL_CAN_AddTxMessage>:
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox)
{
80010c0: b480 push {r7}
80010c2: b089 sub sp, #36 @ 0x24
80010c4: af00 add r7, sp, #0
80010c6: 60f8 str r0, [r7, #12]
80010c8: 60b9 str r1, [r7, #8]
80010ca: 607a str r2, [r7, #4]
80010cc: 603b str r3, [r7, #0]
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
80010ce: 68fb ldr r3, [r7, #12]
80010d0: f893 3020 ldrb.w r3, [r3, #32]
80010d4: 77fb strb r3, [r7, #31]
uint32_t tsr = READ_REG(hcan->Instance->TSR);
80010d6: 68fb ldr r3, [r7, #12]
80010d8: 681b ldr r3, [r3, #0]
80010da: 689b ldr r3, [r3, #8]
80010dc: 61bb str r3, [r7, #24]
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
80010de: 7ffb ldrb r3, [r7, #31]
80010e0: 2b01 cmp r3, #1
80010e2: d003 beq.n 80010ec <HAL_CAN_AddTxMessage+0x2c>
80010e4: 7ffb ldrb r3, [r7, #31]
80010e6: 2b02 cmp r3, #2
80010e8: f040 80ad bne.w 8001246 <HAL_CAN_AddTxMessage+0x186>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
80010ec: 69bb ldr r3, [r7, #24]
80010ee: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
80010f2: 2b00 cmp r3, #0
80010f4: d10a bne.n 800110c <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME1) != 0U) ||
80010f6: 69bb ldr r3, [r7, #24]
80010f8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
if (((tsr & CAN_TSR_TME0) != 0U) ||
80010fc: 2b00 cmp r3, #0
80010fe: d105 bne.n 800110c <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME2) != 0U))
8001100: 69bb ldr r3, [r7, #24]
8001102: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
((tsr & CAN_TSR_TME1) != 0U) ||
8001106: 2b00 cmp r3, #0
8001108: f000 8095 beq.w 8001236 <HAL_CAN_AddTxMessage+0x176>
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
800110c: 69bb ldr r3, [r7, #24]
800110e: 0e1b lsrs r3, r3, #24
8001110: f003 0303 and.w r3, r3, #3
8001114: 617b str r3, [r7, #20]
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
8001116: 2201 movs r2, #1
8001118: 697b ldr r3, [r7, #20]
800111a: 409a lsls r2, r3
800111c: 683b ldr r3, [r7, #0]
800111e: 601a str r2, [r3, #0]
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
8001120: 68bb ldr r3, [r7, #8]
8001122: 689b ldr r3, [r3, #8]
8001124: 2b00 cmp r3, #0
8001126: d10d bne.n 8001144 <HAL_CAN_AddTxMessage+0x84>
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8001128: 68bb ldr r3, [r7, #8]
800112a: 681b ldr r3, [r3, #0]
800112c: 055a lsls r2, r3, #21
pHeader->RTR);
800112e: 68bb ldr r3, [r7, #8]
8001130: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8001132: 68f9 ldr r1, [r7, #12]
8001134: 6809 ldr r1, [r1, #0]
8001136: 431a orrs r2, r3
8001138: 697b ldr r3, [r7, #20]
800113a: 3318 adds r3, #24
800113c: 011b lsls r3, r3, #4
800113e: 440b add r3, r1
8001140: 601a str r2, [r3, #0]
8001142: e00f b.n 8001164 <HAL_CAN_AddTxMessage+0xa4>
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001144: 68bb ldr r3, [r7, #8]
8001146: 685b ldr r3, [r3, #4]
8001148: 00da lsls r2, r3, #3
pHeader->IDE |
800114a: 68bb ldr r3, [r7, #8]
800114c: 689b ldr r3, [r3, #8]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
800114e: 431a orrs r2, r3
pHeader->RTR);
8001150: 68bb ldr r3, [r7, #8]
8001152: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8001154: 68f9 ldr r1, [r7, #12]
8001156: 6809 ldr r1, [r1, #0]
pHeader->IDE |
8001158: 431a orrs r2, r3
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
800115a: 697b ldr r3, [r7, #20]
800115c: 3318 adds r3, #24
800115e: 011b lsls r3, r3, #4
8001160: 440b add r3, r1
8001162: 601a str r2, [r3, #0]
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
8001164: 68fb ldr r3, [r7, #12]
8001166: 6819 ldr r1, [r3, #0]
8001168: 68bb ldr r3, [r7, #8]
800116a: 691a ldr r2, [r3, #16]
800116c: 697b ldr r3, [r7, #20]
800116e: 3318 adds r3, #24
8001170: 011b lsls r3, r3, #4
8001172: 440b add r3, r1
8001174: 3304 adds r3, #4
8001176: 601a str r2, [r3, #0]
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
8001178: 68bb ldr r3, [r7, #8]
800117a: 7d1b ldrb r3, [r3, #20]
800117c: 2b01 cmp r3, #1
800117e: d111 bne.n 80011a4 <HAL_CAN_AddTxMessage+0xe4>
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
8001180: 68fb ldr r3, [r7, #12]
8001182: 681a ldr r2, [r3, #0]
8001184: 697b ldr r3, [r7, #20]
8001186: 3318 adds r3, #24
8001188: 011b lsls r3, r3, #4
800118a: 4413 add r3, r2
800118c: 3304 adds r3, #4
800118e: 681b ldr r3, [r3, #0]
8001190: 68fa ldr r2, [r7, #12]
8001192: 6811 ldr r1, [r2, #0]
8001194: f443 7280 orr.w r2, r3, #256 @ 0x100
8001198: 697b ldr r3, [r7, #20]
800119a: 3318 adds r3, #24
800119c: 011b lsls r3, r3, #4
800119e: 440b add r3, r1
80011a0: 3304 adds r3, #4
80011a2: 601a str r2, [r3, #0]
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
80011a4: 687b ldr r3, [r7, #4]
80011a6: 3307 adds r3, #7
80011a8: 781b ldrb r3, [r3, #0]
80011aa: 061a lsls r2, r3, #24
80011ac: 687b ldr r3, [r7, #4]
80011ae: 3306 adds r3, #6
80011b0: 781b ldrb r3, [r3, #0]
80011b2: 041b lsls r3, r3, #16
80011b4: 431a orrs r2, r3
80011b6: 687b ldr r3, [r7, #4]
80011b8: 3305 adds r3, #5
80011ba: 781b ldrb r3, [r3, #0]
80011bc: 021b lsls r3, r3, #8
80011be: 4313 orrs r3, r2
80011c0: 687a ldr r2, [r7, #4]
80011c2: 3204 adds r2, #4
80011c4: 7812 ldrb r2, [r2, #0]
80011c6: 4610 mov r0, r2
80011c8: 68fa ldr r2, [r7, #12]
80011ca: 6811 ldr r1, [r2, #0]
80011cc: ea43 0200 orr.w r2, r3, r0
80011d0: 697b ldr r3, [r7, #20]
80011d2: 011b lsls r3, r3, #4
80011d4: 440b add r3, r1
80011d6: f503 73c6 add.w r3, r3, #396 @ 0x18c
80011da: 601a str r2, [r3, #0]
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
80011dc: 687b ldr r3, [r7, #4]
80011de: 3303 adds r3, #3
80011e0: 781b ldrb r3, [r3, #0]
80011e2: 061a lsls r2, r3, #24
80011e4: 687b ldr r3, [r7, #4]
80011e6: 3302 adds r3, #2
80011e8: 781b ldrb r3, [r3, #0]
80011ea: 041b lsls r3, r3, #16
80011ec: 431a orrs r2, r3
80011ee: 687b ldr r3, [r7, #4]
80011f0: 3301 adds r3, #1
80011f2: 781b ldrb r3, [r3, #0]
80011f4: 021b lsls r3, r3, #8
80011f6: 4313 orrs r3, r2
80011f8: 687a ldr r2, [r7, #4]
80011fa: 7812 ldrb r2, [r2, #0]
80011fc: 4610 mov r0, r2
80011fe: 68fa ldr r2, [r7, #12]
8001200: 6811 ldr r1, [r2, #0]
8001202: ea43 0200 orr.w r2, r3, r0
8001206: 697b ldr r3, [r7, #20]
8001208: 011b lsls r3, r3, #4
800120a: 440b add r3, r1
800120c: f503 73c4 add.w r3, r3, #392 @ 0x188
8001210: 601a str r2, [r3, #0]
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
8001212: 68fb ldr r3, [r7, #12]
8001214: 681a ldr r2, [r3, #0]
8001216: 697b ldr r3, [r7, #20]
8001218: 3318 adds r3, #24
800121a: 011b lsls r3, r3, #4
800121c: 4413 add r3, r2
800121e: 681b ldr r3, [r3, #0]
8001220: 68fa ldr r2, [r7, #12]
8001222: 6811 ldr r1, [r2, #0]
8001224: f043 0201 orr.w r2, r3, #1
8001228: 697b ldr r3, [r7, #20]
800122a: 3318 adds r3, #24
800122c: 011b lsls r3, r3, #4
800122e: 440b add r3, r1
8001230: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
8001232: 2300 movs r3, #0
8001234: e00e b.n 8001254 <HAL_CAN_AddTxMessage+0x194>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8001236: 68fb ldr r3, [r7, #12]
8001238: 6a5b ldr r3, [r3, #36] @ 0x24
800123a: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
800123e: 68fb ldr r3, [r7, #12]
8001240: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8001242: 2301 movs r3, #1
8001244: e006 b.n 8001254 <HAL_CAN_AddTxMessage+0x194>
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8001246: 68fb ldr r3, [r7, #12]
8001248: 6a5b ldr r3, [r3, #36] @ 0x24
800124a: f443 2280 orr.w r2, r3, #262144 @ 0x40000
800124e: 68fb ldr r3, [r7, #12]
8001250: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8001252: 2301 movs r3, #1
}
}
8001254: 4618 mov r0, r3
8001256: 3724 adds r7, #36 @ 0x24
8001258: 46bd mov sp, r7
800125a: f85d 7b04 ldr.w r7, [sp], #4
800125e: 4770 bx lr
08001260 <HAL_CAN_GetRxMessage>:
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
8001260: b480 push {r7}
8001262: b087 sub sp, #28
8001264: af00 add r7, sp, #0
8001266: 60f8 str r0, [r7, #12]
8001268: 60b9 str r1, [r7, #8]
800126a: 607a str r2, [r7, #4]
800126c: 603b str r3, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
800126e: 68fb ldr r3, [r7, #12]
8001270: f893 3020 ldrb.w r3, [r3, #32]
8001274: 75fb strb r3, [r7, #23]
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
8001276: 7dfb ldrb r3, [r7, #23]
8001278: 2b01 cmp r3, #1
800127a: d003 beq.n 8001284 <HAL_CAN_GetRxMessage+0x24>
800127c: 7dfb ldrb r3, [r7, #23]
800127e: 2b02 cmp r3, #2
8001280: f040 8103 bne.w 800148a <HAL_CAN_GetRxMessage+0x22a>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
8001284: 68bb ldr r3, [r7, #8]
8001286: 2b00 cmp r3, #0
8001288: d10e bne.n 80012a8 <HAL_CAN_GetRxMessage+0x48>
{
/* Check that the Rx FIFO 0 is not empty */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
800128a: 68fb ldr r3, [r7, #12]
800128c: 681b ldr r3, [r3, #0]
800128e: 68db ldr r3, [r3, #12]
8001290: f003 0303 and.w r3, r3, #3
8001294: 2b00 cmp r3, #0
8001296: d116 bne.n 80012c6 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8001298: 68fb ldr r3, [r7, #12]
800129a: 6a5b ldr r3, [r3, #36] @ 0x24
800129c: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80012a0: 68fb ldr r3, [r7, #12]
80012a2: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80012a4: 2301 movs r3, #1
80012a6: e0f7 b.n 8001498 <HAL_CAN_GetRxMessage+0x238>
}
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
80012a8: 68fb ldr r3, [r7, #12]
80012aa: 681b ldr r3, [r3, #0]
80012ac: 691b ldr r3, [r3, #16]
80012ae: f003 0303 and.w r3, r3, #3
80012b2: 2b00 cmp r3, #0
80012b4: d107 bne.n 80012c6 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80012b6: 68fb ldr r3, [r7, #12]
80012b8: 6a5b ldr r3, [r3, #36] @ 0x24
80012ba: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80012be: 68fb ldr r3, [r7, #12]
80012c0: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80012c2: 2301 movs r3, #1
80012c4: e0e8 b.n 8001498 <HAL_CAN_GetRxMessage+0x238>
}
}
/* Get the header */
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
80012c6: 68fb ldr r3, [r7, #12]
80012c8: 681a ldr r2, [r3, #0]
80012ca: 68bb ldr r3, [r7, #8]
80012cc: 331b adds r3, #27
80012ce: 011b lsls r3, r3, #4
80012d0: 4413 add r3, r2
80012d2: 681b ldr r3, [r3, #0]
80012d4: f003 0204 and.w r2, r3, #4
80012d8: 687b ldr r3, [r7, #4]
80012da: 609a str r2, [r3, #8]
if (pHeader->IDE == CAN_ID_STD)
80012dc: 687b ldr r3, [r7, #4]
80012de: 689b ldr r3, [r3, #8]
80012e0: 2b00 cmp r3, #0
80012e2: d10c bne.n 80012fe <HAL_CAN_GetRxMessage+0x9e>
{
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
80012e4: 68fb ldr r3, [r7, #12]
80012e6: 681a ldr r2, [r3, #0]
80012e8: 68bb ldr r3, [r7, #8]
80012ea: 331b adds r3, #27
80012ec: 011b lsls r3, r3, #4
80012ee: 4413 add r3, r2
80012f0: 681b ldr r3, [r3, #0]
80012f2: 0d5b lsrs r3, r3, #21
80012f4: f3c3 020a ubfx r2, r3, #0, #11
80012f8: 687b ldr r3, [r7, #4]
80012fa: 601a str r2, [r3, #0]
80012fc: e00b b.n 8001316 <HAL_CAN_GetRxMessage+0xb6>
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
80012fe: 68fb ldr r3, [r7, #12]
8001300: 681a ldr r2, [r3, #0]
8001302: 68bb ldr r3, [r7, #8]
8001304: 331b adds r3, #27
8001306: 011b lsls r3, r3, #4
8001308: 4413 add r3, r2
800130a: 681b ldr r3, [r3, #0]
800130c: 08db lsrs r3, r3, #3
800130e: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
8001312: 687b ldr r3, [r7, #4]
8001314: 605a str r2, [r3, #4]
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
8001316: 68fb ldr r3, [r7, #12]
8001318: 681a ldr r2, [r3, #0]
800131a: 68bb ldr r3, [r7, #8]
800131c: 331b adds r3, #27
800131e: 011b lsls r3, r3, #4
8001320: 4413 add r3, r2
8001322: 681b ldr r3, [r3, #0]
8001324: f003 0202 and.w r2, r3, #2
8001328: 687b ldr r3, [r7, #4]
800132a: 60da str r2, [r3, #12]
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
800132c: 68fb ldr r3, [r7, #12]
800132e: 681a ldr r2, [r3, #0]
8001330: 68bb ldr r3, [r7, #8]
8001332: 331b adds r3, #27
8001334: 011b lsls r3, r3, #4
8001336: 4413 add r3, r2
8001338: 3304 adds r3, #4
800133a: 681b ldr r3, [r3, #0]
800133c: f003 0308 and.w r3, r3, #8
8001340: 2b00 cmp r3, #0
8001342: d003 beq.n 800134c <HAL_CAN_GetRxMessage+0xec>
{
/* Truncate DLC to 8 if received field is over range */
pHeader->DLC = 8U;
8001344: 687b ldr r3, [r7, #4]
8001346: 2208 movs r2, #8
8001348: 611a str r2, [r3, #16]
800134a: e00b b.n 8001364 <HAL_CAN_GetRxMessage+0x104>
}
else
{
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
800134c: 68fb ldr r3, [r7, #12]
800134e: 681a ldr r2, [r3, #0]
8001350: 68bb ldr r3, [r7, #8]
8001352: 331b adds r3, #27
8001354: 011b lsls r3, r3, #4
8001356: 4413 add r3, r2
8001358: 3304 adds r3, #4
800135a: 681b ldr r3, [r3, #0]
800135c: f003 020f and.w r2, r3, #15
8001360: 687b ldr r3, [r7, #4]
8001362: 611a str r2, [r3, #16]
}
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
8001364: 68fb ldr r3, [r7, #12]
8001366: 681a ldr r2, [r3, #0]
8001368: 68bb ldr r3, [r7, #8]
800136a: 331b adds r3, #27
800136c: 011b lsls r3, r3, #4
800136e: 4413 add r3, r2
8001370: 3304 adds r3, #4
8001372: 681b ldr r3, [r3, #0]
8001374: 0a1b lsrs r3, r3, #8
8001376: b2da uxtb r2, r3
8001378: 687b ldr r3, [r7, #4]
800137a: 619a str r2, [r3, #24]
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
800137c: 68fb ldr r3, [r7, #12]
800137e: 681a ldr r2, [r3, #0]
8001380: 68bb ldr r3, [r7, #8]
8001382: 331b adds r3, #27
8001384: 011b lsls r3, r3, #4
8001386: 4413 add r3, r2
8001388: 3304 adds r3, #4
800138a: 681b ldr r3, [r3, #0]
800138c: 0c1b lsrs r3, r3, #16
800138e: b29a uxth r2, r3
8001390: 687b ldr r3, [r7, #4]
8001392: 615a str r2, [r3, #20]
/* Get the data */
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
8001394: 68fb ldr r3, [r7, #12]
8001396: 681a ldr r2, [r3, #0]
8001398: 68bb ldr r3, [r7, #8]
800139a: 011b lsls r3, r3, #4
800139c: 4413 add r3, r2
800139e: f503 73dc add.w r3, r3, #440 @ 0x1b8
80013a2: 681b ldr r3, [r3, #0]
80013a4: b2da uxtb r2, r3
80013a6: 683b ldr r3, [r7, #0]
80013a8: 701a strb r2, [r3, #0]
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
80013aa: 68fb ldr r3, [r7, #12]
80013ac: 681a ldr r2, [r3, #0]
80013ae: 68bb ldr r3, [r7, #8]
80013b0: 011b lsls r3, r3, #4
80013b2: 4413 add r3, r2
80013b4: f503 73dc add.w r3, r3, #440 @ 0x1b8
80013b8: 681b ldr r3, [r3, #0]
80013ba: 0a1a lsrs r2, r3, #8
80013bc: 683b ldr r3, [r7, #0]
80013be: 3301 adds r3, #1
80013c0: b2d2 uxtb r2, r2
80013c2: 701a strb r2, [r3, #0]
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
80013c4: 68fb ldr r3, [r7, #12]
80013c6: 681a ldr r2, [r3, #0]
80013c8: 68bb ldr r3, [r7, #8]
80013ca: 011b lsls r3, r3, #4
80013cc: 4413 add r3, r2
80013ce: f503 73dc add.w r3, r3, #440 @ 0x1b8
80013d2: 681b ldr r3, [r3, #0]
80013d4: 0c1a lsrs r2, r3, #16
80013d6: 683b ldr r3, [r7, #0]
80013d8: 3302 adds r3, #2
80013da: b2d2 uxtb r2, r2
80013dc: 701a strb r2, [r3, #0]
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
80013de: 68fb ldr r3, [r7, #12]
80013e0: 681a ldr r2, [r3, #0]
80013e2: 68bb ldr r3, [r7, #8]
80013e4: 011b lsls r3, r3, #4
80013e6: 4413 add r3, r2
80013e8: f503 73dc add.w r3, r3, #440 @ 0x1b8
80013ec: 681b ldr r3, [r3, #0]
80013ee: 0e1a lsrs r2, r3, #24
80013f0: 683b ldr r3, [r7, #0]
80013f2: 3303 adds r3, #3
80013f4: b2d2 uxtb r2, r2
80013f6: 701a strb r2, [r3, #0]
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
80013f8: 68fb ldr r3, [r7, #12]
80013fa: 681a ldr r2, [r3, #0]
80013fc: 68bb ldr r3, [r7, #8]
80013fe: 011b lsls r3, r3, #4
8001400: 4413 add r3, r2
8001402: f503 73de add.w r3, r3, #444 @ 0x1bc
8001406: 681a ldr r2, [r3, #0]
8001408: 683b ldr r3, [r7, #0]
800140a: 3304 adds r3, #4
800140c: b2d2 uxtb r2, r2
800140e: 701a strb r2, [r3, #0]
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
8001410: 68fb ldr r3, [r7, #12]
8001412: 681a ldr r2, [r3, #0]
8001414: 68bb ldr r3, [r7, #8]
8001416: 011b lsls r3, r3, #4
8001418: 4413 add r3, r2
800141a: f503 73de add.w r3, r3, #444 @ 0x1bc
800141e: 681b ldr r3, [r3, #0]
8001420: 0a1a lsrs r2, r3, #8
8001422: 683b ldr r3, [r7, #0]
8001424: 3305 adds r3, #5
8001426: b2d2 uxtb r2, r2
8001428: 701a strb r2, [r3, #0]
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
800142a: 68fb ldr r3, [r7, #12]
800142c: 681a ldr r2, [r3, #0]
800142e: 68bb ldr r3, [r7, #8]
8001430: 011b lsls r3, r3, #4
8001432: 4413 add r3, r2
8001434: f503 73de add.w r3, r3, #444 @ 0x1bc
8001438: 681b ldr r3, [r3, #0]
800143a: 0c1a lsrs r2, r3, #16
800143c: 683b ldr r3, [r7, #0]
800143e: 3306 adds r3, #6
8001440: b2d2 uxtb r2, r2
8001442: 701a strb r2, [r3, #0]
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
8001444: 68fb ldr r3, [r7, #12]
8001446: 681a ldr r2, [r3, #0]
8001448: 68bb ldr r3, [r7, #8]
800144a: 011b lsls r3, r3, #4
800144c: 4413 add r3, r2
800144e: f503 73de add.w r3, r3, #444 @ 0x1bc
8001452: 681b ldr r3, [r3, #0]
8001454: 0e1a lsrs r2, r3, #24
8001456: 683b ldr r3, [r7, #0]
8001458: 3307 adds r3, #7
800145a: b2d2 uxtb r2, r2
800145c: 701a strb r2, [r3, #0]
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
800145e: 68bb ldr r3, [r7, #8]
8001460: 2b00 cmp r3, #0
8001462: d108 bne.n 8001476 <HAL_CAN_GetRxMessage+0x216>
{
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
8001464: 68fb ldr r3, [r7, #12]
8001466: 681b ldr r3, [r3, #0]
8001468: 68da ldr r2, [r3, #12]
800146a: 68fb ldr r3, [r7, #12]
800146c: 681b ldr r3, [r3, #0]
800146e: f042 0220 orr.w r2, r2, #32
8001472: 60da str r2, [r3, #12]
8001474: e007 b.n 8001486 <HAL_CAN_GetRxMessage+0x226>
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
8001476: 68fb ldr r3, [r7, #12]
8001478: 681b ldr r3, [r3, #0]
800147a: 691a ldr r2, [r3, #16]
800147c: 68fb ldr r3, [r7, #12]
800147e: 681b ldr r3, [r3, #0]
8001480: f042 0220 orr.w r2, r2, #32
8001484: 611a str r2, [r3, #16]
}
/* Return function status */
return HAL_OK;
8001486: 2300 movs r3, #0
8001488: e006 b.n 8001498 <HAL_CAN_GetRxMessage+0x238>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
800148a: 68fb ldr r3, [r7, #12]
800148c: 6a5b ldr r3, [r3, #36] @ 0x24
800148e: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8001492: 68fb ldr r3, [r7, #12]
8001494: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8001496: 2301 movs r3, #1
}
}
8001498: 4618 mov r0, r3
800149a: 371c adds r7, #28
800149c: 46bd mov sp, r7
800149e: f85d 7b04 ldr.w r7, [sp], #4
80014a2: 4770 bx lr
080014a4 <HAL_CAN_ActivateNotification>:
* @param ActiveITs indicates which interrupts will be enabled.
* This parameter can be any combination of @arg CAN_Interrupts.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
80014a4: b480 push {r7}
80014a6: b085 sub sp, #20
80014a8: af00 add r7, sp, #0
80014aa: 6078 str r0, [r7, #4]
80014ac: 6039 str r1, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
80014ae: 687b ldr r3, [r7, #4]
80014b0: f893 3020 ldrb.w r3, [r3, #32]
80014b4: 73fb strb r3, [r7, #15]
/* Check function parameters */
assert_param(IS_CAN_IT(ActiveITs));
if ((state == HAL_CAN_STATE_READY) ||
80014b6: 7bfb ldrb r3, [r7, #15]
80014b8: 2b01 cmp r3, #1
80014ba: d002 beq.n 80014c2 <HAL_CAN_ActivateNotification+0x1e>
80014bc: 7bfb ldrb r3, [r7, #15]
80014be: 2b02 cmp r3, #2
80014c0: d109 bne.n 80014d6 <HAL_CAN_ActivateNotification+0x32>
(state == HAL_CAN_STATE_LISTENING))
{
/* Enable the selected interrupts */
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
80014c2: 687b ldr r3, [r7, #4]
80014c4: 681b ldr r3, [r3, #0]
80014c6: 6959 ldr r1, [r3, #20]
80014c8: 687b ldr r3, [r7, #4]
80014ca: 681b ldr r3, [r3, #0]
80014cc: 683a ldr r2, [r7, #0]
80014ce: 430a orrs r2, r1
80014d0: 615a str r2, [r3, #20]
/* Return function status */
return HAL_OK;
80014d2: 2300 movs r3, #0
80014d4: e006 b.n 80014e4 <HAL_CAN_ActivateNotification+0x40>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
80014d6: 687b ldr r3, [r7, #4]
80014d8: 6a5b ldr r3, [r3, #36] @ 0x24
80014da: f443 2280 orr.w r2, r3, #262144 @ 0x40000
80014de: 687b ldr r3, [r7, #4]
80014e0: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80014e2: 2301 movs r3, #1
}
}
80014e4: 4618 mov r0, r3
80014e6: 3714 adds r7, #20
80014e8: 46bd mov sp, r7
80014ea: f85d 7b04 ldr.w r7, [sp], #4
80014ee: 4770 bx lr
080014f0 <HAL_CAN_IRQHandler>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
80014f0: b580 push {r7, lr}
80014f2: b08a sub sp, #40 @ 0x28
80014f4: af00 add r7, sp, #0
80014f6: 6078 str r0, [r7, #4]
uint32_t errorcode = HAL_CAN_ERROR_NONE;
80014f8: 2300 movs r3, #0
80014fa: 627b str r3, [r7, #36] @ 0x24
uint32_t interrupts = READ_REG(hcan->Instance->IER);
80014fc: 687b ldr r3, [r7, #4]
80014fe: 681b ldr r3, [r3, #0]
8001500: 695b ldr r3, [r3, #20]
8001502: 623b str r3, [r7, #32]
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
8001504: 687b ldr r3, [r7, #4]
8001506: 681b ldr r3, [r3, #0]
8001508: 685b ldr r3, [r3, #4]
800150a: 61fb str r3, [r7, #28]
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
800150c: 687b ldr r3, [r7, #4]
800150e: 681b ldr r3, [r3, #0]
8001510: 689b ldr r3, [r3, #8]
8001512: 61bb str r3, [r7, #24]
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
8001514: 687b ldr r3, [r7, #4]
8001516: 681b ldr r3, [r3, #0]
8001518: 68db ldr r3, [r3, #12]
800151a: 617b str r3, [r7, #20]
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
800151c: 687b ldr r3, [r7, #4]
800151e: 681b ldr r3, [r3, #0]
8001520: 691b ldr r3, [r3, #16]
8001522: 613b str r3, [r7, #16]
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
8001524: 687b ldr r3, [r7, #4]
8001526: 681b ldr r3, [r3, #0]
8001528: 699b ldr r3, [r3, #24]
800152a: 60fb str r3, [r7, #12]
/* Transmit Mailbox empty interrupt management *****************************/
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
800152c: 6a3b ldr r3, [r7, #32]
800152e: f003 0301 and.w r3, r3, #1
8001532: 2b00 cmp r3, #0
8001534: f000 8083 beq.w 800163e <HAL_CAN_IRQHandler+0x14e>
{
/* Transmit Mailbox 0 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
8001538: 69bb ldr r3, [r7, #24]
800153a: f003 0301 and.w r3, r3, #1
800153e: 2b00 cmp r3, #0
8001540: d025 beq.n 800158e <HAL_CAN_IRQHandler+0x9e>
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
8001542: 687b ldr r3, [r7, #4]
8001544: 681b ldr r3, [r3, #0]
8001546: 2201 movs r2, #1
8001548: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
800154a: 69bb ldr r3, [r7, #24]
800154c: f003 0302 and.w r3, r3, #2
8001550: 2b00 cmp r3, #0
8001552: d004 beq.n 800155e <HAL_CAN_IRQHandler+0x6e>
{
/* Transmission Mailbox 0 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0CompleteCallback(hcan);
8001554: 687b ldr r3, [r7, #4]
8001556: 6a9b ldr r3, [r3, #40] @ 0x28
8001558: 6878 ldr r0, [r7, #4]
800155a: 4798 blx r3
800155c: e017 b.n 800158e <HAL_CAN_IRQHandler+0x9e>
HAL_CAN_TxMailbox0CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST0) != 0U)
800155e: 69bb ldr r3, [r7, #24]
8001560: f003 0304 and.w r3, r3, #4
8001564: 2b00 cmp r3, #0
8001566: d004 beq.n 8001572 <HAL_CAN_IRQHandler+0x82>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
8001568: 6a7b ldr r3, [r7, #36] @ 0x24
800156a: f443 6300 orr.w r3, r3, #2048 @ 0x800
800156e: 627b str r3, [r7, #36] @ 0x24
8001570: e00d b.n 800158e <HAL_CAN_IRQHandler+0x9e>
}
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
8001572: 69bb ldr r3, [r7, #24]
8001574: f003 0308 and.w r3, r3, #8
8001578: 2b00 cmp r3, #0
800157a: d004 beq.n 8001586 <HAL_CAN_IRQHandler+0x96>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
800157c: 6a7b ldr r3, [r7, #36] @ 0x24
800157e: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8001582: 627b str r3, [r7, #36] @ 0x24
8001584: e003 b.n 800158e <HAL_CAN_IRQHandler+0x9e>
else
{
/* Transmission Mailbox 0 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0AbortCallback(hcan);
8001586: 687b ldr r3, [r7, #4]
8001588: 6b5b ldr r3, [r3, #52] @ 0x34
800158a: 6878 ldr r0, [r7, #4]
800158c: 4798 blx r3
}
}
}
/* Transmit Mailbox 1 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
800158e: 69bb ldr r3, [r7, #24]
8001590: f403 7380 and.w r3, r3, #256 @ 0x100
8001594: 2b00 cmp r3, #0
8001596: d026 beq.n 80015e6 <HAL_CAN_IRQHandler+0xf6>
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
8001598: 687b ldr r3, [r7, #4]
800159a: 681b ldr r3, [r3, #0]
800159c: f44f 7280 mov.w r2, #256 @ 0x100
80015a0: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
80015a2: 69bb ldr r3, [r7, #24]
80015a4: f403 7300 and.w r3, r3, #512 @ 0x200
80015a8: 2b00 cmp r3, #0
80015aa: d004 beq.n 80015b6 <HAL_CAN_IRQHandler+0xc6>
{
/* Transmission Mailbox 1 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1CompleteCallback(hcan);
80015ac: 687b ldr r3, [r7, #4]
80015ae: 6adb ldr r3, [r3, #44] @ 0x2c
80015b0: 6878 ldr r0, [r7, #4]
80015b2: 4798 blx r3
80015b4: e017 b.n 80015e6 <HAL_CAN_IRQHandler+0xf6>
HAL_CAN_TxMailbox1CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST1) != 0U)
80015b6: 69bb ldr r3, [r7, #24]
80015b8: f403 6380 and.w r3, r3, #1024 @ 0x400
80015bc: 2b00 cmp r3, #0
80015be: d004 beq.n 80015ca <HAL_CAN_IRQHandler+0xda>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
80015c0: 6a7b ldr r3, [r7, #36] @ 0x24
80015c2: f443 5300 orr.w r3, r3, #8192 @ 0x2000
80015c6: 627b str r3, [r7, #36] @ 0x24
80015c8: e00d b.n 80015e6 <HAL_CAN_IRQHandler+0xf6>
}
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
80015ca: 69bb ldr r3, [r7, #24]
80015cc: f403 6300 and.w r3, r3, #2048 @ 0x800
80015d0: 2b00 cmp r3, #0
80015d2: d004 beq.n 80015de <HAL_CAN_IRQHandler+0xee>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
80015d4: 6a7b ldr r3, [r7, #36] @ 0x24
80015d6: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80015da: 627b str r3, [r7, #36] @ 0x24
80015dc: e003 b.n 80015e6 <HAL_CAN_IRQHandler+0xf6>
else
{
/* Transmission Mailbox 1 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1AbortCallback(hcan);
80015de: 687b ldr r3, [r7, #4]
80015e0: 6b9b ldr r3, [r3, #56] @ 0x38
80015e2: 6878 ldr r0, [r7, #4]
80015e4: 4798 blx r3
}
}
}
/* Transmit Mailbox 2 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
80015e6: 69bb ldr r3, [r7, #24]
80015e8: f403 3380 and.w r3, r3, #65536 @ 0x10000
80015ec: 2b00 cmp r3, #0
80015ee: d026 beq.n 800163e <HAL_CAN_IRQHandler+0x14e>
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
80015f0: 687b ldr r3, [r7, #4]
80015f2: 681b ldr r3, [r3, #0]
80015f4: f44f 3280 mov.w r2, #65536 @ 0x10000
80015f8: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
80015fa: 69bb ldr r3, [r7, #24]
80015fc: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001600: 2b00 cmp r3, #0
8001602: d004 beq.n 800160e <HAL_CAN_IRQHandler+0x11e>
{
/* Transmission Mailbox 2 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2CompleteCallback(hcan);
8001604: 687b ldr r3, [r7, #4]
8001606: 6b1b ldr r3, [r3, #48] @ 0x30
8001608: 6878 ldr r0, [r7, #4]
800160a: 4798 blx r3
800160c: e017 b.n 800163e <HAL_CAN_IRQHandler+0x14e>
HAL_CAN_TxMailbox2CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST2) != 0U)
800160e: 69bb ldr r3, [r7, #24]
8001610: f403 2380 and.w r3, r3, #262144 @ 0x40000
8001614: 2b00 cmp r3, #0
8001616: d004 beq.n 8001622 <HAL_CAN_IRQHandler+0x132>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
8001618: 6a7b ldr r3, [r7, #36] @ 0x24
800161a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800161e: 627b str r3, [r7, #36] @ 0x24
8001620: e00d b.n 800163e <HAL_CAN_IRQHandler+0x14e>
}
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
8001622: 69bb ldr r3, [r7, #24]
8001624: f403 2300 and.w r3, r3, #524288 @ 0x80000
8001628: 2b00 cmp r3, #0
800162a: d004 beq.n 8001636 <HAL_CAN_IRQHandler+0x146>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
800162c: 6a7b ldr r3, [r7, #36] @ 0x24
800162e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001632: 627b str r3, [r7, #36] @ 0x24
8001634: e003 b.n 800163e <HAL_CAN_IRQHandler+0x14e>
else
{
/* Transmission Mailbox 2 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2AbortCallback(hcan);
8001636: 687b ldr r3, [r7, #4]
8001638: 6bdb ldr r3, [r3, #60] @ 0x3c
800163a: 6878 ldr r0, [r7, #4]
800163c: 4798 blx r3
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
800163e: 6a3b ldr r3, [r7, #32]
8001640: f003 0308 and.w r3, r3, #8
8001644: 2b00 cmp r3, #0
8001646: d00c beq.n 8001662 <HAL_CAN_IRQHandler+0x172>
{
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
8001648: 697b ldr r3, [r7, #20]
800164a: f003 0310 and.w r3, r3, #16
800164e: 2b00 cmp r3, #0
8001650: d007 beq.n 8001662 <HAL_CAN_IRQHandler+0x172>
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
8001652: 6a7b ldr r3, [r7, #36] @ 0x24
8001654: f443 7300 orr.w r3, r3, #512 @ 0x200
8001658: 627b str r3, [r7, #36] @ 0x24
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
800165a: 687b ldr r3, [r7, #4]
800165c: 681b ldr r3, [r3, #0]
800165e: 2210 movs r2, #16
8001660: 60da str r2, [r3, #12]
}
}
/* Receive FIFO 0 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
8001662: 6a3b ldr r3, [r7, #32]
8001664: f003 0304 and.w r3, r3, #4
8001668: 2b00 cmp r3, #0
800166a: d00c beq.n 8001686 <HAL_CAN_IRQHandler+0x196>
{
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
800166c: 697b ldr r3, [r7, #20]
800166e: f003 0308 and.w r3, r3, #8
8001672: 2b00 cmp r3, #0
8001674: d007 beq.n 8001686 <HAL_CAN_IRQHandler+0x196>
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
8001676: 687b ldr r3, [r7, #4]
8001678: 681b ldr r3, [r3, #0]
800167a: 2208 movs r2, #8
800167c: 60da str r2, [r3, #12]
/* Receive FIFO 0 full Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0FullCallback(hcan);
800167e: 687b ldr r3, [r7, #4]
8001680: 6c5b ldr r3, [r3, #68] @ 0x44
8001682: 6878 ldr r0, [r7, #4]
8001684: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
8001686: 6a3b ldr r3, [r7, #32]
8001688: f003 0302 and.w r3, r3, #2
800168c: 2b00 cmp r3, #0
800168e: d00a beq.n 80016a6 <HAL_CAN_IRQHandler+0x1b6>
{
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
8001690: 687b ldr r3, [r7, #4]
8001692: 681b ldr r3, [r3, #0]
8001694: 68db ldr r3, [r3, #12]
8001696: f003 0303 and.w r3, r3, #3
800169a: 2b00 cmp r3, #0
800169c: d003 beq.n 80016a6 <HAL_CAN_IRQHandler+0x1b6>
{
/* Receive FIFO 0 message pending Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
800169e: 687b ldr r3, [r7, #4]
80016a0: 6c1b ldr r3, [r3, #64] @ 0x40
80016a2: 6878 ldr r0, [r7, #4]
80016a4: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
80016a6: 6a3b ldr r3, [r7, #32]
80016a8: f003 0340 and.w r3, r3, #64 @ 0x40
80016ac: 2b00 cmp r3, #0
80016ae: d00c beq.n 80016ca <HAL_CAN_IRQHandler+0x1da>
{
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
80016b0: 693b ldr r3, [r7, #16]
80016b2: f003 0310 and.w r3, r3, #16
80016b6: 2b00 cmp r3, #0
80016b8: d007 beq.n 80016ca <HAL_CAN_IRQHandler+0x1da>
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
80016ba: 6a7b ldr r3, [r7, #36] @ 0x24
80016bc: f443 6380 orr.w r3, r3, #1024 @ 0x400
80016c0: 627b str r3, [r7, #36] @ 0x24
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
80016c2: 687b ldr r3, [r7, #4]
80016c4: 681b ldr r3, [r3, #0]
80016c6: 2210 movs r2, #16
80016c8: 611a str r2, [r3, #16]
}
}
/* Receive FIFO 1 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
80016ca: 6a3b ldr r3, [r7, #32]
80016cc: f003 0320 and.w r3, r3, #32
80016d0: 2b00 cmp r3, #0
80016d2: d00c beq.n 80016ee <HAL_CAN_IRQHandler+0x1fe>
{
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
80016d4: 693b ldr r3, [r7, #16]
80016d6: f003 0308 and.w r3, r3, #8
80016da: 2b00 cmp r3, #0
80016dc: d007 beq.n 80016ee <HAL_CAN_IRQHandler+0x1fe>
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
80016de: 687b ldr r3, [r7, #4]
80016e0: 681b ldr r3, [r3, #0]
80016e2: 2208 movs r2, #8
80016e4: 611a str r2, [r3, #16]
/* Receive FIFO 1 full Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1FullCallback(hcan);
80016e6: 687b ldr r3, [r7, #4]
80016e8: 6cdb ldr r3, [r3, #76] @ 0x4c
80016ea: 6878 ldr r0, [r7, #4]
80016ec: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
80016ee: 6a3b ldr r3, [r7, #32]
80016f0: f003 0310 and.w r3, r3, #16
80016f4: 2b00 cmp r3, #0
80016f6: d00a beq.n 800170e <HAL_CAN_IRQHandler+0x21e>
{
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
80016f8: 687b ldr r3, [r7, #4]
80016fa: 681b ldr r3, [r3, #0]
80016fc: 691b ldr r3, [r3, #16]
80016fe: f003 0303 and.w r3, r3, #3
8001702: 2b00 cmp r3, #0
8001704: d003 beq.n 800170e <HAL_CAN_IRQHandler+0x21e>
{
/* Receive FIFO 1 message pending Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
8001706: 687b ldr r3, [r7, #4]
8001708: 6c9b ldr r3, [r3, #72] @ 0x48
800170a: 6878 ldr r0, [r7, #4]
800170c: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
800170e: 6a3b ldr r3, [r7, #32]
8001710: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001714: 2b00 cmp r3, #0
8001716: d00c beq.n 8001732 <HAL_CAN_IRQHandler+0x242>
{
if ((msrflags & CAN_MSR_SLAKI) != 0U)
8001718: 69fb ldr r3, [r7, #28]
800171a: f003 0310 and.w r3, r3, #16
800171e: 2b00 cmp r3, #0
8001720: d007 beq.n 8001732 <HAL_CAN_IRQHandler+0x242>
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
8001722: 687b ldr r3, [r7, #4]
8001724: 681b ldr r3, [r3, #0]
8001726: 2210 movs r2, #16
8001728: 605a str r2, [r3, #4]
/* Sleep Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->SleepCallback(hcan);
800172a: 687b ldr r3, [r7, #4]
800172c: 6d1b ldr r3, [r3, #80] @ 0x50
800172e: 6878 ldr r0, [r7, #4]
8001730: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
if ((interrupts & CAN_IT_WAKEUP) != 0U)
8001732: 6a3b ldr r3, [r7, #32]
8001734: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001738: 2b00 cmp r3, #0
800173a: d00c beq.n 8001756 <HAL_CAN_IRQHandler+0x266>
{
if ((msrflags & CAN_MSR_WKUI) != 0U)
800173c: 69fb ldr r3, [r7, #28]
800173e: f003 0308 and.w r3, r3, #8
8001742: 2b00 cmp r3, #0
8001744: d007 beq.n 8001756 <HAL_CAN_IRQHandler+0x266>
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
8001746: 687b ldr r3, [r7, #4]
8001748: 681b ldr r3, [r3, #0]
800174a: 2208 movs r2, #8
800174c: 605a str r2, [r3, #4]
/* WakeUp Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->WakeUpFromRxMsgCallback(hcan);
800174e: 687b ldr r3, [r7, #4]
8001750: 6d5b ldr r3, [r3, #84] @ 0x54
8001752: 6878 ldr r0, [r7, #4]
8001754: 4798 blx r3
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
if ((interrupts & CAN_IT_ERROR) != 0U)
8001756: 6a3b ldr r3, [r7, #32]
8001758: f403 4300 and.w r3, r3, #32768 @ 0x8000
800175c: 2b00 cmp r3, #0
800175e: d07b beq.n 8001858 <HAL_CAN_IRQHandler+0x368>
{
if ((msrflags & CAN_MSR_ERRI) != 0U)
8001760: 69fb ldr r3, [r7, #28]
8001762: f003 0304 and.w r3, r3, #4
8001766: 2b00 cmp r3, #0
8001768: d072 beq.n 8001850 <HAL_CAN_IRQHandler+0x360>
{
/* Check Error Warning Flag */
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
800176a: 6a3b ldr r3, [r7, #32]
800176c: f403 7380 and.w r3, r3, #256 @ 0x100
8001770: 2b00 cmp r3, #0
8001772: d008 beq.n 8001786 <HAL_CAN_IRQHandler+0x296>
((esrflags & CAN_ESR_EWGF) != 0U))
8001774: 68fb ldr r3, [r7, #12]
8001776: f003 0301 and.w r3, r3, #1
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
800177a: 2b00 cmp r3, #0
800177c: d003 beq.n 8001786 <HAL_CAN_IRQHandler+0x296>
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
800177e: 6a7b ldr r3, [r7, #36] @ 0x24
8001780: f043 0301 orr.w r3, r3, #1
8001784: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Warning Flag as read-only */
}
/* Check Error Passive Flag */
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8001786: 6a3b ldr r3, [r7, #32]
8001788: f403 7300 and.w r3, r3, #512 @ 0x200
800178c: 2b00 cmp r3, #0
800178e: d008 beq.n 80017a2 <HAL_CAN_IRQHandler+0x2b2>
((esrflags & CAN_ESR_EPVF) != 0U))
8001790: 68fb ldr r3, [r7, #12]
8001792: f003 0302 and.w r3, r3, #2
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8001796: 2b00 cmp r3, #0
8001798: d003 beq.n 80017a2 <HAL_CAN_IRQHandler+0x2b2>
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
800179a: 6a7b ldr r3, [r7, #36] @ 0x24
800179c: f043 0302 orr.w r3, r3, #2
80017a0: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Passive Flag as read-only */
}
/* Check Bus-off Flag */
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
80017a2: 6a3b ldr r3, [r7, #32]
80017a4: f403 6380 and.w r3, r3, #1024 @ 0x400
80017a8: 2b00 cmp r3, #0
80017aa: d008 beq.n 80017be <HAL_CAN_IRQHandler+0x2ce>
((esrflags & CAN_ESR_BOFF) != 0U))
80017ac: 68fb ldr r3, [r7, #12]
80017ae: f003 0304 and.w r3, r3, #4
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
80017b2: 2b00 cmp r3, #0
80017b4: d003 beq.n 80017be <HAL_CAN_IRQHandler+0x2ce>
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
80017b6: 6a7b ldr r3, [r7, #36] @ 0x24
80017b8: f043 0304 orr.w r3, r3, #4
80017bc: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Bus-Off as read-only */
}
/* Check Last Error Code Flag */
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
80017be: 6a3b ldr r3, [r7, #32]
80017c0: f403 6300 and.w r3, r3, #2048 @ 0x800
80017c4: 2b00 cmp r3, #0
80017c6: d043 beq.n 8001850 <HAL_CAN_IRQHandler+0x360>
((esrflags & CAN_ESR_LEC) != 0U))
80017c8: 68fb ldr r3, [r7, #12]
80017ca: f003 0370 and.w r3, r3, #112 @ 0x70
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
80017ce: 2b00 cmp r3, #0
80017d0: d03e beq.n 8001850 <HAL_CAN_IRQHandler+0x360>
{
switch (esrflags & CAN_ESR_LEC)
80017d2: 68fb ldr r3, [r7, #12]
80017d4: f003 0370 and.w r3, r3, #112 @ 0x70
80017d8: 2b60 cmp r3, #96 @ 0x60
80017da: d02b beq.n 8001834 <HAL_CAN_IRQHandler+0x344>
80017dc: 2b60 cmp r3, #96 @ 0x60
80017de: d82e bhi.n 800183e <HAL_CAN_IRQHandler+0x34e>
80017e0: 2b50 cmp r3, #80 @ 0x50
80017e2: d022 beq.n 800182a <HAL_CAN_IRQHandler+0x33a>
80017e4: 2b50 cmp r3, #80 @ 0x50
80017e6: d82a bhi.n 800183e <HAL_CAN_IRQHandler+0x34e>
80017e8: 2b40 cmp r3, #64 @ 0x40
80017ea: d019 beq.n 8001820 <HAL_CAN_IRQHandler+0x330>
80017ec: 2b40 cmp r3, #64 @ 0x40
80017ee: d826 bhi.n 800183e <HAL_CAN_IRQHandler+0x34e>
80017f0: 2b30 cmp r3, #48 @ 0x30
80017f2: d010 beq.n 8001816 <HAL_CAN_IRQHandler+0x326>
80017f4: 2b30 cmp r3, #48 @ 0x30
80017f6: d822 bhi.n 800183e <HAL_CAN_IRQHandler+0x34e>
80017f8: 2b10 cmp r3, #16
80017fa: d002 beq.n 8001802 <HAL_CAN_IRQHandler+0x312>
80017fc: 2b20 cmp r3, #32
80017fe: d005 beq.n 800180c <HAL_CAN_IRQHandler+0x31c>
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
/* Set CAN error code to CRC error */
errorcode |= HAL_CAN_ERROR_CRC;
break;
default:
break;
8001800: e01d b.n 800183e <HAL_CAN_IRQHandler+0x34e>
errorcode |= HAL_CAN_ERROR_STF;
8001802: 6a7b ldr r3, [r7, #36] @ 0x24
8001804: f043 0308 orr.w r3, r3, #8
8001808: 627b str r3, [r7, #36] @ 0x24
break;
800180a: e019 b.n 8001840 <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_FOR;
800180c: 6a7b ldr r3, [r7, #36] @ 0x24
800180e: f043 0310 orr.w r3, r3, #16
8001812: 627b str r3, [r7, #36] @ 0x24
break;
8001814: e014 b.n 8001840 <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_ACK;
8001816: 6a7b ldr r3, [r7, #36] @ 0x24
8001818: f043 0320 orr.w r3, r3, #32
800181c: 627b str r3, [r7, #36] @ 0x24
break;
800181e: e00f b.n 8001840 <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_BR;
8001820: 6a7b ldr r3, [r7, #36] @ 0x24
8001822: f043 0340 orr.w r3, r3, #64 @ 0x40
8001826: 627b str r3, [r7, #36] @ 0x24
break;
8001828: e00a b.n 8001840 <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_BD;
800182a: 6a7b ldr r3, [r7, #36] @ 0x24
800182c: f043 0380 orr.w r3, r3, #128 @ 0x80
8001830: 627b str r3, [r7, #36] @ 0x24
break;
8001832: e005 b.n 8001840 <HAL_CAN_IRQHandler+0x350>
errorcode |= HAL_CAN_ERROR_CRC;
8001834: 6a7b ldr r3, [r7, #36] @ 0x24
8001836: f443 7380 orr.w r3, r3, #256 @ 0x100
800183a: 627b str r3, [r7, #36] @ 0x24
break;
800183c: e000 b.n 8001840 <HAL_CAN_IRQHandler+0x350>
break;
800183e: bf00 nop
}
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
8001840: 687b ldr r3, [r7, #4]
8001842: 681b ldr r3, [r3, #0]
8001844: 699a ldr r2, [r3, #24]
8001846: 687b ldr r3, [r7, #4]
8001848: 681b ldr r3, [r3, #0]
800184a: f022 0270 bic.w r2, r2, #112 @ 0x70
800184e: 619a str r2, [r3, #24]
}
}
/* Clear ERRI Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
8001850: 687b ldr r3, [r7, #4]
8001852: 681b ldr r3, [r3, #0]
8001854: 2204 movs r2, #4
8001856: 605a str r2, [r3, #4]
}
/* Call the Error call Back in case of Errors */
if (errorcode != HAL_CAN_ERROR_NONE)
8001858: 6a7b ldr r3, [r7, #36] @ 0x24
800185a: 2b00 cmp r3, #0
800185c: d009 beq.n 8001872 <HAL_CAN_IRQHandler+0x382>
{
/* Update error code in handle */
hcan->ErrorCode |= errorcode;
800185e: 687b ldr r3, [r7, #4]
8001860: 6a5a ldr r2, [r3, #36] @ 0x24
8001862: 6a7b ldr r3, [r7, #36] @ 0x24
8001864: 431a orrs r2, r3
8001866: 687b ldr r3, [r7, #4]
8001868: 625a str r2, [r3, #36] @ 0x24
/* Call Error callback function */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->ErrorCallback(hcan);
800186a: 687b ldr r3, [r7, #4]
800186c: 6d9b ldr r3, [r3, #88] @ 0x58
800186e: 6878 ldr r0, [r7, #4]
8001870: 4798 blx r3
#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
8001872: bf00 nop
8001874: 3728 adds r7, #40 @ 0x28
8001876: 46bd mov sp, r7
8001878: bd80 pop {r7, pc}
0800187a <HAL_CAN_TxMailbox0CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
800187a: b480 push {r7}
800187c: b083 sub sp, #12
800187e: af00 add r7, sp, #0
8001880: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
user file
*/
}
8001882: bf00 nop
8001884: 370c adds r7, #12
8001886: 46bd mov sp, r7
8001888: f85d 7b04 ldr.w r7, [sp], #4
800188c: 4770 bx lr
0800188e <HAL_CAN_TxMailbox1CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
800188e: b480 push {r7}
8001890: b083 sub sp, #12
8001892: af00 add r7, sp, #0
8001894: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
user file
*/
}
8001896: bf00 nop
8001898: 370c adds r7, #12
800189a: 46bd mov sp, r7
800189c: f85d 7b04 ldr.w r7, [sp], #4
80018a0: 4770 bx lr
080018a2 <HAL_CAN_TxMailbox2CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
80018a2: b480 push {r7}
80018a4: b083 sub sp, #12
80018a6: af00 add r7, sp, #0
80018a8: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
user file
*/
}
80018aa: bf00 nop
80018ac: 370c adds r7, #12
80018ae: 46bd mov sp, r7
80018b0: f85d 7b04 ldr.w r7, [sp], #4
80018b4: 4770 bx lr
080018b6 <HAL_CAN_TxMailbox0AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
80018b6: b480 push {r7}
80018b8: b083 sub sp, #12
80018ba: af00 add r7, sp, #0
80018bc: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
user file
*/
}
80018be: bf00 nop
80018c0: 370c adds r7, #12
80018c2: 46bd mov sp, r7
80018c4: f85d 7b04 ldr.w r7, [sp], #4
80018c8: 4770 bx lr
080018ca <HAL_CAN_TxMailbox1AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
80018ca: b480 push {r7}
80018cc: b083 sub sp, #12
80018ce: af00 add r7, sp, #0
80018d0: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
user file
*/
}
80018d2: bf00 nop
80018d4: 370c adds r7, #12
80018d6: 46bd mov sp, r7
80018d8: f85d 7b04 ldr.w r7, [sp], #4
80018dc: 4770 bx lr
080018de <HAL_CAN_TxMailbox2AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
80018de: b480 push {r7}
80018e0: b083 sub sp, #12
80018e2: af00 add r7, sp, #0
80018e4: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
user file
*/
}
80018e6: bf00 nop
80018e8: 370c adds r7, #12
80018ea: 46bd mov sp, r7
80018ec: f85d 7b04 ldr.w r7, [sp], #4
80018f0: 4770 bx lr
080018f2 <HAL_CAN_RxFifo0FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
80018f2: b480 push {r7}
80018f4: b083 sub sp, #12
80018f6: af00 add r7, sp, #0
80018f8: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
file
*/
}
80018fa: bf00 nop
80018fc: 370c adds r7, #12
80018fe: 46bd mov sp, r7
8001900: f85d 7b04 ldr.w r7, [sp], #4
8001904: 4770 bx lr
08001906 <HAL_CAN_RxFifo1MsgPendingCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
8001906: b480 push {r7}
8001908: b083 sub sp, #12
800190a: af00 add r7, sp, #0
800190c: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
user file
*/
}
800190e: bf00 nop
8001910: 370c adds r7, #12
8001912: 46bd mov sp, r7
8001914: f85d 7b04 ldr.w r7, [sp], #4
8001918: 4770 bx lr
0800191a <HAL_CAN_RxFifo1FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
800191a: b480 push {r7}
800191c: b083 sub sp, #12
800191e: af00 add r7, sp, #0
8001920: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
file
*/
}
8001922: bf00 nop
8001924: 370c adds r7, #12
8001926: 46bd mov sp, r7
8001928: f85d 7b04 ldr.w r7, [sp], #4
800192c: 4770 bx lr
0800192e <HAL_CAN_SleepCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
800192e: b480 push {r7}
8001930: b083 sub sp, #12
8001932: af00 add r7, sp, #0
8001934: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_SleepCallback could be implemented in the user file
*/
}
8001936: bf00 nop
8001938: 370c adds r7, #12
800193a: 46bd mov sp, r7
800193c: f85d 7b04 ldr.w r7, [sp], #4
8001940: 4770 bx lr
08001942 <HAL_CAN_WakeUpFromRxMsgCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
8001942: b480 push {r7}
8001944: b083 sub sp, #12
8001946: af00 add r7, sp, #0
8001948: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
user file
*/
}
800194a: bf00 nop
800194c: 370c adds r7, #12
800194e: 46bd mov sp, r7
8001950: f85d 7b04 ldr.w r7, [sp], #4
8001954: 4770 bx lr
08001956 <HAL_CAN_ErrorCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
8001956: b480 push {r7}
8001958: b083 sub sp, #12
800195a: af00 add r7, sp, #0
800195c: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
800195e: bf00 nop
8001960: 370c adds r7, #12
8001962: 46bd mov sp, r7
8001964: f85d 7b04 ldr.w r7, [sp], #4
8001968: 4770 bx lr
...
0800196c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800196c: b480 push {r7}
800196e: b085 sub sp, #20
8001970: af00 add r7, sp, #0
8001972: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001974: 687b ldr r3, [r7, #4]
8001976: f003 0307 and.w r3, r3, #7
800197a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
800197c: 4b0c ldr r3, [pc, #48] @ (80019b0 <__NVIC_SetPriorityGrouping+0x44>)
800197e: 68db ldr r3, [r3, #12]
8001980: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8001982: 68ba ldr r2, [r7, #8]
8001984: f64f 03ff movw r3, #63743 @ 0xf8ff
8001988: 4013 ands r3, r2
800198a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800198c: 68fb ldr r3, [r7, #12]
800198e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001990: 68bb ldr r3, [r7, #8]
8001992: 4313 orrs r3, r2
reg_value = (reg_value |
8001994: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8001998: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800199c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800199e: 4a04 ldr r2, [pc, #16] @ (80019b0 <__NVIC_SetPriorityGrouping+0x44>)
80019a0: 68bb ldr r3, [r7, #8]
80019a2: 60d3 str r3, [r2, #12]
}
80019a4: bf00 nop
80019a6: 3714 adds r7, #20
80019a8: 46bd mov sp, r7
80019aa: f85d 7b04 ldr.w r7, [sp], #4
80019ae: 4770 bx lr
80019b0: e000ed00 .word 0xe000ed00
080019b4 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80019b4: b480 push {r7}
80019b6: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80019b8: 4b04 ldr r3, [pc, #16] @ (80019cc <__NVIC_GetPriorityGrouping+0x18>)
80019ba: 68db ldr r3, [r3, #12]
80019bc: 0a1b lsrs r3, r3, #8
80019be: f003 0307 and.w r3, r3, #7
}
80019c2: 4618 mov r0, r3
80019c4: 46bd mov sp, r7
80019c6: f85d 7b04 ldr.w r7, [sp], #4
80019ca: 4770 bx lr
80019cc: e000ed00 .word 0xe000ed00
080019d0 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80019d0: b480 push {r7}
80019d2: b083 sub sp, #12
80019d4: af00 add r7, sp, #0
80019d6: 4603 mov r3, r0
80019d8: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80019da: f997 3007 ldrsb.w r3, [r7, #7]
80019de: 2b00 cmp r3, #0
80019e0: db0b blt.n 80019fa <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80019e2: 79fb ldrb r3, [r7, #7]
80019e4: f003 021f and.w r2, r3, #31
80019e8: 4907 ldr r1, [pc, #28] @ (8001a08 <__NVIC_EnableIRQ+0x38>)
80019ea: f997 3007 ldrsb.w r3, [r7, #7]
80019ee: 095b lsrs r3, r3, #5
80019f0: 2001 movs r0, #1
80019f2: fa00 f202 lsl.w r2, r0, r2
80019f6: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
80019fa: bf00 nop
80019fc: 370c adds r7, #12
80019fe: 46bd mov sp, r7
8001a00: f85d 7b04 ldr.w r7, [sp], #4
8001a04: 4770 bx lr
8001a06: bf00 nop
8001a08: e000e100 .word 0xe000e100
08001a0c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001a0c: b480 push {r7}
8001a0e: b083 sub sp, #12
8001a10: af00 add r7, sp, #0
8001a12: 4603 mov r3, r0
8001a14: 6039 str r1, [r7, #0]
8001a16: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001a18: f997 3007 ldrsb.w r3, [r7, #7]
8001a1c: 2b00 cmp r3, #0
8001a1e: db0a blt.n 8001a36 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001a20: 683b ldr r3, [r7, #0]
8001a22: b2da uxtb r2, r3
8001a24: 490c ldr r1, [pc, #48] @ (8001a58 <__NVIC_SetPriority+0x4c>)
8001a26: f997 3007 ldrsb.w r3, [r7, #7]
8001a2a: 0112 lsls r2, r2, #4
8001a2c: b2d2 uxtb r2, r2
8001a2e: 440b add r3, r1
8001a30: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001a34: e00a b.n 8001a4c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001a36: 683b ldr r3, [r7, #0]
8001a38: b2da uxtb r2, r3
8001a3a: 4908 ldr r1, [pc, #32] @ (8001a5c <__NVIC_SetPriority+0x50>)
8001a3c: 79fb ldrb r3, [r7, #7]
8001a3e: f003 030f and.w r3, r3, #15
8001a42: 3b04 subs r3, #4
8001a44: 0112 lsls r2, r2, #4
8001a46: b2d2 uxtb r2, r2
8001a48: 440b add r3, r1
8001a4a: 761a strb r2, [r3, #24]
}
8001a4c: bf00 nop
8001a4e: 370c adds r7, #12
8001a50: 46bd mov sp, r7
8001a52: f85d 7b04 ldr.w r7, [sp], #4
8001a56: 4770 bx lr
8001a58: e000e100 .word 0xe000e100
8001a5c: e000ed00 .word 0xe000ed00
08001a60 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001a60: b480 push {r7}
8001a62: b089 sub sp, #36 @ 0x24
8001a64: af00 add r7, sp, #0
8001a66: 60f8 str r0, [r7, #12]
8001a68: 60b9 str r1, [r7, #8]
8001a6a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001a6c: 68fb ldr r3, [r7, #12]
8001a6e: f003 0307 and.w r3, r3, #7
8001a72: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001a74: 69fb ldr r3, [r7, #28]
8001a76: f1c3 0307 rsb r3, r3, #7
8001a7a: 2b04 cmp r3, #4
8001a7c: bf28 it cs
8001a7e: 2304 movcs r3, #4
8001a80: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001a82: 69fb ldr r3, [r7, #28]
8001a84: 3304 adds r3, #4
8001a86: 2b06 cmp r3, #6
8001a88: d902 bls.n 8001a90 <NVIC_EncodePriority+0x30>
8001a8a: 69fb ldr r3, [r7, #28]
8001a8c: 3b03 subs r3, #3
8001a8e: e000 b.n 8001a92 <NVIC_EncodePriority+0x32>
8001a90: 2300 movs r3, #0
8001a92: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001a94: f04f 32ff mov.w r2, #4294967295
8001a98: 69bb ldr r3, [r7, #24]
8001a9a: fa02 f303 lsl.w r3, r2, r3
8001a9e: 43da mvns r2, r3
8001aa0: 68bb ldr r3, [r7, #8]
8001aa2: 401a ands r2, r3
8001aa4: 697b ldr r3, [r7, #20]
8001aa6: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001aa8: f04f 31ff mov.w r1, #4294967295
8001aac: 697b ldr r3, [r7, #20]
8001aae: fa01 f303 lsl.w r3, r1, r3
8001ab2: 43d9 mvns r1, r3
8001ab4: 687b ldr r3, [r7, #4]
8001ab6: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001ab8: 4313 orrs r3, r2
);
}
8001aba: 4618 mov r0, r3
8001abc: 3724 adds r7, #36 @ 0x24
8001abe: 46bd mov sp, r7
8001ac0: f85d 7b04 ldr.w r7, [sp], #4
8001ac4: 4770 bx lr
...
08001ac8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001ac8: b580 push {r7, lr}
8001aca: b082 sub sp, #8
8001acc: af00 add r7, sp, #0
8001ace: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001ad0: 687b ldr r3, [r7, #4]
8001ad2: 3b01 subs r3, #1
8001ad4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8001ad8: d301 bcc.n 8001ade <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8001ada: 2301 movs r3, #1
8001adc: e00f b.n 8001afe <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001ade: 4a0a ldr r2, [pc, #40] @ (8001b08 <SysTick_Config+0x40>)
8001ae0: 687b ldr r3, [r7, #4]
8001ae2: 3b01 subs r3, #1
8001ae4: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001ae6: 210f movs r1, #15
8001ae8: f04f 30ff mov.w r0, #4294967295
8001aec: f7ff ff8e bl 8001a0c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001af0: 4b05 ldr r3, [pc, #20] @ (8001b08 <SysTick_Config+0x40>)
8001af2: 2200 movs r2, #0
8001af4: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001af6: 4b04 ldr r3, [pc, #16] @ (8001b08 <SysTick_Config+0x40>)
8001af8: 2207 movs r2, #7
8001afa: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001afc: 2300 movs r3, #0
}
8001afe: 4618 mov r0, r3
8001b00: 3708 adds r7, #8
8001b02: 46bd mov sp, r7
8001b04: bd80 pop {r7, pc}
8001b06: bf00 nop
8001b08: e000e010 .word 0xe000e010
08001b0c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001b0c: b580 push {r7, lr}
8001b0e: b082 sub sp, #8
8001b10: af00 add r7, sp, #0
8001b12: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001b14: 6878 ldr r0, [r7, #4]
8001b16: f7ff ff29 bl 800196c <__NVIC_SetPriorityGrouping>
}
8001b1a: bf00 nop
8001b1c: 3708 adds r7, #8
8001b1e: 46bd mov sp, r7
8001b20: bd80 pop {r7, pc}
08001b22 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001b22: b580 push {r7, lr}
8001b24: b086 sub sp, #24
8001b26: af00 add r7, sp, #0
8001b28: 4603 mov r3, r0
8001b2a: 60b9 str r1, [r7, #8]
8001b2c: 607a str r2, [r7, #4]
8001b2e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8001b30: 2300 movs r3, #0
8001b32: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001b34: f7ff ff3e bl 80019b4 <__NVIC_GetPriorityGrouping>
8001b38: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001b3a: 687a ldr r2, [r7, #4]
8001b3c: 68b9 ldr r1, [r7, #8]
8001b3e: 6978 ldr r0, [r7, #20]
8001b40: f7ff ff8e bl 8001a60 <NVIC_EncodePriority>
8001b44: 4602 mov r2, r0
8001b46: f997 300f ldrsb.w r3, [r7, #15]
8001b4a: 4611 mov r1, r2
8001b4c: 4618 mov r0, r3
8001b4e: f7ff ff5d bl 8001a0c <__NVIC_SetPriority>
}
8001b52: bf00 nop
8001b54: 3718 adds r7, #24
8001b56: 46bd mov sp, r7
8001b58: bd80 pop {r7, pc}
08001b5a <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001b5a: b580 push {r7, lr}
8001b5c: b082 sub sp, #8
8001b5e: af00 add r7, sp, #0
8001b60: 4603 mov r3, r0
8001b62: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001b64: f997 3007 ldrsb.w r3, [r7, #7]
8001b68: 4618 mov r0, r3
8001b6a: f7ff ff31 bl 80019d0 <__NVIC_EnableIRQ>
}
8001b6e: bf00 nop
8001b70: 3708 adds r7, #8
8001b72: 46bd mov sp, r7
8001b74: bd80 pop {r7, pc}
08001b76 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8001b76: b580 push {r7, lr}
8001b78: b082 sub sp, #8
8001b7a: af00 add r7, sp, #0
8001b7c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001b7e: 6878 ldr r0, [r7, #4]
8001b80: f7ff ffa2 bl 8001ac8 <SysTick_Config>
8001b84: 4603 mov r3, r0
}
8001b86: 4618 mov r0, r3
8001b88: 3708 adds r7, #8
8001b8a: 46bd mov sp, r7
8001b8c: bd80 pop {r7, pc}
...
08001b90 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001b90: b480 push {r7}
8001b92: b087 sub sp, #28
8001b94: af00 add r7, sp, #0
8001b96: 6078 str r0, [r7, #4]
8001b98: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8001b9a: 2300 movs r3, #0
8001b9c: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001b9e: e154 b.n 8001e4a <HAL_GPIO_Init+0x2ba>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8001ba0: 683b ldr r3, [r7, #0]
8001ba2: 681a ldr r2, [r3, #0]
8001ba4: 2101 movs r1, #1
8001ba6: 697b ldr r3, [r7, #20]
8001ba8: fa01 f303 lsl.w r3, r1, r3
8001bac: 4013 ands r3, r2
8001bae: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001bb0: 68fb ldr r3, [r7, #12]
8001bb2: 2b00 cmp r3, #0
8001bb4: f000 8146 beq.w 8001e44 <HAL_GPIO_Init+0x2b4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001bb8: 683b ldr r3, [r7, #0]
8001bba: 685b ldr r3, [r3, #4]
8001bbc: f003 0303 and.w r3, r3, #3
8001bc0: 2b01 cmp r3, #1
8001bc2: d005 beq.n 8001bd0 <HAL_GPIO_Init+0x40>
8001bc4: 683b ldr r3, [r7, #0]
8001bc6: 685b ldr r3, [r3, #4]
8001bc8: f003 0303 and.w r3, r3, #3
8001bcc: 2b02 cmp r3, #2
8001bce: d130 bne.n 8001c32 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001bd0: 687b ldr r3, [r7, #4]
8001bd2: 689b ldr r3, [r3, #8]
8001bd4: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
8001bd6: 697b ldr r3, [r7, #20]
8001bd8: 005b lsls r3, r3, #1
8001bda: 2203 movs r2, #3
8001bdc: fa02 f303 lsl.w r3, r2, r3
8001be0: 43db mvns r3, r3
8001be2: 693a ldr r2, [r7, #16]
8001be4: 4013 ands r3, r2
8001be6: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001be8: 683b ldr r3, [r7, #0]
8001bea: 68da ldr r2, [r3, #12]
8001bec: 697b ldr r3, [r7, #20]
8001bee: 005b lsls r3, r3, #1
8001bf0: fa02 f303 lsl.w r3, r2, r3
8001bf4: 693a ldr r2, [r7, #16]
8001bf6: 4313 orrs r3, r2
8001bf8: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8001bfa: 687b ldr r3, [r7, #4]
8001bfc: 693a ldr r2, [r7, #16]
8001bfe: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001c00: 687b ldr r3, [r7, #4]
8001c02: 685b ldr r3, [r3, #4]
8001c04: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001c06: 2201 movs r2, #1
8001c08: 697b ldr r3, [r7, #20]
8001c0a: fa02 f303 lsl.w r3, r2, r3
8001c0e: 43db mvns r3, r3
8001c10: 693a ldr r2, [r7, #16]
8001c12: 4013 ands r3, r2
8001c14: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001c16: 683b ldr r3, [r7, #0]
8001c18: 685b ldr r3, [r3, #4]
8001c1a: 091b lsrs r3, r3, #4
8001c1c: f003 0201 and.w r2, r3, #1
8001c20: 697b ldr r3, [r7, #20]
8001c22: fa02 f303 lsl.w r3, r2, r3
8001c26: 693a ldr r2, [r7, #16]
8001c28: 4313 orrs r3, r2
8001c2a: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001c2c: 687b ldr r3, [r7, #4]
8001c2e: 693a ldr r2, [r7, #16]
8001c30: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001c32: 683b ldr r3, [r7, #0]
8001c34: 685b ldr r3, [r3, #4]
8001c36: f003 0303 and.w r3, r3, #3
8001c3a: 2b03 cmp r3, #3
8001c3c: d017 beq.n 8001c6e <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001c3e: 687b ldr r3, [r7, #4]
8001c40: 68db ldr r3, [r3, #12]
8001c42: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8001c44: 697b ldr r3, [r7, #20]
8001c46: 005b lsls r3, r3, #1
8001c48: 2203 movs r2, #3
8001c4a: fa02 f303 lsl.w r3, r2, r3
8001c4e: 43db mvns r3, r3
8001c50: 693a ldr r2, [r7, #16]
8001c52: 4013 ands r3, r2
8001c54: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
8001c56: 683b ldr r3, [r7, #0]
8001c58: 689a ldr r2, [r3, #8]
8001c5a: 697b ldr r3, [r7, #20]
8001c5c: 005b lsls r3, r3, #1
8001c5e: fa02 f303 lsl.w r3, r2, r3
8001c62: 693a ldr r2, [r7, #16]
8001c64: 4313 orrs r3, r2
8001c66: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8001c68: 687b ldr r3, [r7, #4]
8001c6a: 693a ldr r2, [r7, #16]
8001c6c: 60da str r2, [r3, #12]
}
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001c6e: 683b ldr r3, [r7, #0]
8001c70: 685b ldr r3, [r3, #4]
8001c72: f003 0303 and.w r3, r3, #3
8001c76: 2b02 cmp r3, #2
8001c78: d123 bne.n 8001cc2 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8001c7a: 697b ldr r3, [r7, #20]
8001c7c: 08da lsrs r2, r3, #3
8001c7e: 687b ldr r3, [r7, #4]
8001c80: 3208 adds r2, #8
8001c82: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001c86: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8001c88: 697b ldr r3, [r7, #20]
8001c8a: f003 0307 and.w r3, r3, #7
8001c8e: 009b lsls r3, r3, #2
8001c90: 220f movs r2, #15
8001c92: fa02 f303 lsl.w r3, r2, r3
8001c96: 43db mvns r3, r3
8001c98: 693a ldr r2, [r7, #16]
8001c9a: 4013 ands r3, r2
8001c9c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8001c9e: 683b ldr r3, [r7, #0]
8001ca0: 691a ldr r2, [r3, #16]
8001ca2: 697b ldr r3, [r7, #20]
8001ca4: f003 0307 and.w r3, r3, #7
8001ca8: 009b lsls r3, r3, #2
8001caa: fa02 f303 lsl.w r3, r2, r3
8001cae: 693a ldr r2, [r7, #16]
8001cb0: 4313 orrs r3, r2
8001cb2: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001cb4: 697b ldr r3, [r7, #20]
8001cb6: 08da lsrs r2, r3, #3
8001cb8: 687b ldr r3, [r7, #4]
8001cba: 3208 adds r2, #8
8001cbc: 6939 ldr r1, [r7, #16]
8001cbe: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001cc2: 687b ldr r3, [r7, #4]
8001cc4: 681b ldr r3, [r3, #0]
8001cc6: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8001cc8: 697b ldr r3, [r7, #20]
8001cca: 005b lsls r3, r3, #1
8001ccc: 2203 movs r2, #3
8001cce: fa02 f303 lsl.w r3, r2, r3
8001cd2: 43db mvns r3, r3
8001cd4: 693a ldr r2, [r7, #16]
8001cd6: 4013 ands r3, r2
8001cd8: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001cda: 683b ldr r3, [r7, #0]
8001cdc: 685b ldr r3, [r3, #4]
8001cde: f003 0203 and.w r2, r3, #3
8001ce2: 697b ldr r3, [r7, #20]
8001ce4: 005b lsls r3, r3, #1
8001ce6: fa02 f303 lsl.w r3, r2, r3
8001cea: 693a ldr r2, [r7, #16]
8001cec: 4313 orrs r3, r2
8001cee: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001cf0: 687b ldr r3, [r7, #4]
8001cf2: 693a ldr r2, [r7, #16]
8001cf4: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001cf6: 683b ldr r3, [r7, #0]
8001cf8: 685b ldr r3, [r3, #4]
8001cfa: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001cfe: 2b00 cmp r3, #0
8001d00: f000 80a0 beq.w 8001e44 <HAL_GPIO_Init+0x2b4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001d04: 4b58 ldr r3, [pc, #352] @ (8001e68 <HAL_GPIO_Init+0x2d8>)
8001d06: 699b ldr r3, [r3, #24]
8001d08: 4a57 ldr r2, [pc, #348] @ (8001e68 <HAL_GPIO_Init+0x2d8>)
8001d0a: f043 0301 orr.w r3, r3, #1
8001d0e: 6193 str r3, [r2, #24]
8001d10: 4b55 ldr r3, [pc, #340] @ (8001e68 <HAL_GPIO_Init+0x2d8>)
8001d12: 699b ldr r3, [r3, #24]
8001d14: f003 0301 and.w r3, r3, #1
8001d18: 60bb str r3, [r7, #8]
8001d1a: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8001d1c: 4a53 ldr r2, [pc, #332] @ (8001e6c <HAL_GPIO_Init+0x2dc>)
8001d1e: 697b ldr r3, [r7, #20]
8001d20: 089b lsrs r3, r3, #2
8001d22: 3302 adds r3, #2
8001d24: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001d28: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8001d2a: 697b ldr r3, [r7, #20]
8001d2c: f003 0303 and.w r3, r3, #3
8001d30: 009b lsls r3, r3, #2
8001d32: 220f movs r2, #15
8001d34: fa02 f303 lsl.w r3, r2, r3
8001d38: 43db mvns r3, r3
8001d3a: 693a ldr r2, [r7, #16]
8001d3c: 4013 ands r3, r2
8001d3e: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8001d40: 687b ldr r3, [r7, #4]
8001d42: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8001d46: d019 beq.n 8001d7c <HAL_GPIO_Init+0x1ec>
8001d48: 687b ldr r3, [r7, #4]
8001d4a: 4a49 ldr r2, [pc, #292] @ (8001e70 <HAL_GPIO_Init+0x2e0>)
8001d4c: 4293 cmp r3, r2
8001d4e: d013 beq.n 8001d78 <HAL_GPIO_Init+0x1e8>
8001d50: 687b ldr r3, [r7, #4]
8001d52: 4a48 ldr r2, [pc, #288] @ (8001e74 <HAL_GPIO_Init+0x2e4>)
8001d54: 4293 cmp r3, r2
8001d56: d00d beq.n 8001d74 <HAL_GPIO_Init+0x1e4>
8001d58: 687b ldr r3, [r7, #4]
8001d5a: 4a47 ldr r2, [pc, #284] @ (8001e78 <HAL_GPIO_Init+0x2e8>)
8001d5c: 4293 cmp r3, r2
8001d5e: d007 beq.n 8001d70 <HAL_GPIO_Init+0x1e0>
8001d60: 687b ldr r3, [r7, #4]
8001d62: 4a46 ldr r2, [pc, #280] @ (8001e7c <HAL_GPIO_Init+0x2ec>)
8001d64: 4293 cmp r3, r2
8001d66: d101 bne.n 8001d6c <HAL_GPIO_Init+0x1dc>
8001d68: 2304 movs r3, #4
8001d6a: e008 b.n 8001d7e <HAL_GPIO_Init+0x1ee>
8001d6c: 2305 movs r3, #5
8001d6e: e006 b.n 8001d7e <HAL_GPIO_Init+0x1ee>
8001d70: 2303 movs r3, #3
8001d72: e004 b.n 8001d7e <HAL_GPIO_Init+0x1ee>
8001d74: 2302 movs r3, #2
8001d76: e002 b.n 8001d7e <HAL_GPIO_Init+0x1ee>
8001d78: 2301 movs r3, #1
8001d7a: e000 b.n 8001d7e <HAL_GPIO_Init+0x1ee>
8001d7c: 2300 movs r3, #0
8001d7e: 697a ldr r2, [r7, #20]
8001d80: f002 0203 and.w r2, r2, #3
8001d84: 0092 lsls r2, r2, #2
8001d86: 4093 lsls r3, r2
8001d88: 693a ldr r2, [r7, #16]
8001d8a: 4313 orrs r3, r2
8001d8c: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8001d8e: 4937 ldr r1, [pc, #220] @ (8001e6c <HAL_GPIO_Init+0x2dc>)
8001d90: 697b ldr r3, [r7, #20]
8001d92: 089b lsrs r3, r3, #2
8001d94: 3302 adds r3, #2
8001d96: 693a ldr r2, [r7, #16]
8001d98: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001d9c: 4b38 ldr r3, [pc, #224] @ (8001e80 <HAL_GPIO_Init+0x2f0>)
8001d9e: 689b ldr r3, [r3, #8]
8001da0: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001da2: 68fb ldr r3, [r7, #12]
8001da4: 43db mvns r3, r3
8001da6: 693a ldr r2, [r7, #16]
8001da8: 4013 ands r3, r2
8001daa: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001dac: 683b ldr r3, [r7, #0]
8001dae: 685b ldr r3, [r3, #4]
8001db0: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001db4: 2b00 cmp r3, #0
8001db6: d003 beq.n 8001dc0 <HAL_GPIO_Init+0x230>
{
temp |= iocurrent;
8001db8: 693a ldr r2, [r7, #16]
8001dba: 68fb ldr r3, [r7, #12]
8001dbc: 4313 orrs r3, r2
8001dbe: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8001dc0: 4a2f ldr r2, [pc, #188] @ (8001e80 <HAL_GPIO_Init+0x2f0>)
8001dc2: 693b ldr r3, [r7, #16]
8001dc4: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001dc6: 4b2e ldr r3, [pc, #184] @ (8001e80 <HAL_GPIO_Init+0x2f0>)
8001dc8: 68db ldr r3, [r3, #12]
8001dca: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001dcc: 68fb ldr r3, [r7, #12]
8001dce: 43db mvns r3, r3
8001dd0: 693a ldr r2, [r7, #16]
8001dd2: 4013 ands r3, r2
8001dd4: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8001dd6: 683b ldr r3, [r7, #0]
8001dd8: 685b ldr r3, [r3, #4]
8001dda: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001dde: 2b00 cmp r3, #0
8001de0: d003 beq.n 8001dea <HAL_GPIO_Init+0x25a>
{
temp |= iocurrent;
8001de2: 693a ldr r2, [r7, #16]
8001de4: 68fb ldr r3, [r7, #12]
8001de6: 4313 orrs r3, r2
8001de8: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8001dea: 4a25 ldr r2, [pc, #148] @ (8001e80 <HAL_GPIO_Init+0x2f0>)
8001dec: 693b ldr r3, [r7, #16]
8001dee: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001df0: 4b23 ldr r3, [pc, #140] @ (8001e80 <HAL_GPIO_Init+0x2f0>)
8001df2: 685b ldr r3, [r3, #4]
8001df4: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001df6: 68fb ldr r3, [r7, #12]
8001df8: 43db mvns r3, r3
8001dfa: 693a ldr r2, [r7, #16]
8001dfc: 4013 ands r3, r2
8001dfe: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001e00: 683b ldr r3, [r7, #0]
8001e02: 685b ldr r3, [r3, #4]
8001e04: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001e08: 2b00 cmp r3, #0
8001e0a: d003 beq.n 8001e14 <HAL_GPIO_Init+0x284>
{
temp |= iocurrent;
8001e0c: 693a ldr r2, [r7, #16]
8001e0e: 68fb ldr r3, [r7, #12]
8001e10: 4313 orrs r3, r2
8001e12: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8001e14: 4a1a ldr r2, [pc, #104] @ (8001e80 <HAL_GPIO_Init+0x2f0>)
8001e16: 693b ldr r3, [r7, #16]
8001e18: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001e1a: 4b19 ldr r3, [pc, #100] @ (8001e80 <HAL_GPIO_Init+0x2f0>)
8001e1c: 681b ldr r3, [r3, #0]
8001e1e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001e20: 68fb ldr r3, [r7, #12]
8001e22: 43db mvns r3, r3
8001e24: 693a ldr r2, [r7, #16]
8001e26: 4013 ands r3, r2
8001e28: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001e2a: 683b ldr r3, [r7, #0]
8001e2c: 685b ldr r3, [r3, #4]
8001e2e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001e32: 2b00 cmp r3, #0
8001e34: d003 beq.n 8001e3e <HAL_GPIO_Init+0x2ae>
{
temp |= iocurrent;
8001e36: 693a ldr r2, [r7, #16]
8001e38: 68fb ldr r3, [r7, #12]
8001e3a: 4313 orrs r3, r2
8001e3c: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8001e3e: 4a10 ldr r2, [pc, #64] @ (8001e80 <HAL_GPIO_Init+0x2f0>)
8001e40: 693b ldr r3, [r7, #16]
8001e42: 6013 str r3, [r2, #0]
}
}
position++;
8001e44: 697b ldr r3, [r7, #20]
8001e46: 3301 adds r3, #1
8001e48: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001e4a: 683b ldr r3, [r7, #0]
8001e4c: 681a ldr r2, [r3, #0]
8001e4e: 697b ldr r3, [r7, #20]
8001e50: fa22 f303 lsr.w r3, r2, r3
8001e54: 2b00 cmp r3, #0
8001e56: f47f aea3 bne.w 8001ba0 <HAL_GPIO_Init+0x10>
}
}
8001e5a: bf00 nop
8001e5c: bf00 nop
8001e5e: 371c adds r7, #28
8001e60: 46bd mov sp, r7
8001e62: f85d 7b04 ldr.w r7, [sp], #4
8001e66: 4770 bx lr
8001e68: 40021000 .word 0x40021000
8001e6c: 40010000 .word 0x40010000
8001e70: 48000400 .word 0x48000400
8001e74: 48000800 .word 0x48000800
8001e78: 48000c00 .word 0x48000c00
8001e7c: 48001000 .word 0x48001000
8001e80: 40010400 .word 0x40010400
08001e84 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001e84: b480 push {r7}
8001e86: b085 sub sp, #20
8001e88: af00 add r7, sp, #0
8001e8a: 6078 str r0, [r7, #4]
8001e8c: 460b mov r3, r1
8001e8e: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8001e90: 687b ldr r3, [r7, #4]
8001e92: 691a ldr r2, [r3, #16]
8001e94: 887b ldrh r3, [r7, #2]
8001e96: 4013 ands r3, r2
8001e98: 2b00 cmp r3, #0
8001e9a: d002 beq.n 8001ea2 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8001e9c: 2301 movs r3, #1
8001e9e: 73fb strb r3, [r7, #15]
8001ea0: e001 b.n 8001ea6 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8001ea2: 2300 movs r3, #0
8001ea4: 73fb strb r3, [r7, #15]
}
return bitstatus;
8001ea6: 7bfb ldrb r3, [r7, #15]
}
8001ea8: 4618 mov r0, r3
8001eaa: 3714 adds r7, #20
8001eac: 46bd mov sp, r7
8001eae: f85d 7b04 ldr.w r7, [sp], #4
8001eb2: 4770 bx lr
08001eb4 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001eb4: b480 push {r7}
8001eb6: b083 sub sp, #12
8001eb8: af00 add r7, sp, #0
8001eba: 6078 str r0, [r7, #4]
8001ebc: 460b mov r3, r1
8001ebe: 807b strh r3, [r7, #2]
8001ec0: 4613 mov r3, r2
8001ec2: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001ec4: 787b ldrb r3, [r7, #1]
8001ec6: 2b00 cmp r3, #0
8001ec8: d003 beq.n 8001ed2 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001eca: 887a ldrh r2, [r7, #2]
8001ecc: 687b ldr r3, [r7, #4]
8001ece: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8001ed0: e002 b.n 8001ed8 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8001ed2: 887a ldrh r2, [r7, #2]
8001ed4: 687b ldr r3, [r7, #4]
8001ed6: 629a str r2, [r3, #40] @ 0x28
}
8001ed8: bf00 nop
8001eda: 370c adds r7, #12
8001edc: 46bd mov sp, r7
8001ede: f85d 7b04 ldr.w r7, [sp], #4
8001ee2: 4770 bx lr
08001ee4 <HAL_GPIO_TogglePin>:
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
* @param GPIO_Pin specifies the pin to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001ee4: b480 push {r7}
8001ee6: b085 sub sp, #20
8001ee8: af00 add r7, sp, #0
8001eea: 6078 str r0, [r7, #4]
8001eec: 460b mov r3, r1
8001eee: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8001ef0: 687b ldr r3, [r7, #4]
8001ef2: 695b ldr r3, [r3, #20]
8001ef4: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8001ef6: 887a ldrh r2, [r7, #2]
8001ef8: 68fb ldr r3, [r7, #12]
8001efa: 4013 ands r3, r2
8001efc: 041a lsls r2, r3, #16
8001efe: 68fb ldr r3, [r7, #12]
8001f00: 43d9 mvns r1, r3
8001f02: 887b ldrh r3, [r7, #2]
8001f04: 400b ands r3, r1
8001f06: 431a orrs r2, r3
8001f08: 687b ldr r3, [r7, #4]
8001f0a: 619a str r2, [r3, #24]
}
8001f0c: bf00 nop
8001f0e: 3714 adds r7, #20
8001f10: 46bd mov sp, r7
8001f12: f85d 7b04 ldr.w r7, [sp], #4
8001f16: 4770 bx lr
08001f18 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001f18: b580 push {r7, lr}
8001f1a: f5ad 7d00 sub.w sp, sp, #512 @ 0x200
8001f1e: af00 add r7, sp, #0
8001f20: f507 7300 add.w r3, r7, #512 @ 0x200
8001f24: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001f28: 6018 str r0, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
uint32_t pll_config2;
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8001f2a: f507 7300 add.w r3, r7, #512 @ 0x200
8001f2e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001f32: 681b ldr r3, [r3, #0]
8001f34: 2b00 cmp r3, #0
8001f36: d102 bne.n 8001f3e <HAL_RCC_OscConfig+0x26>
{
return HAL_ERROR;
8001f38: 2301 movs r3, #1
8001f3a: f001 b823 b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001f3e: f507 7300 add.w r3, r7, #512 @ 0x200
8001f42: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001f46: 681b ldr r3, [r3, #0]
8001f48: 681b ldr r3, [r3, #0]
8001f4a: f003 0301 and.w r3, r3, #1
8001f4e: 2b00 cmp r3, #0
8001f50: f000 817d beq.w 800224e <HAL_RCC_OscConfig+0x336>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001f54: 4bbc ldr r3, [pc, #752] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8001f56: 685b ldr r3, [r3, #4]
8001f58: f003 030c and.w r3, r3, #12
8001f5c: 2b04 cmp r3, #4
8001f5e: d00c beq.n 8001f7a <HAL_RCC_OscConfig+0x62>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8001f60: 4bb9 ldr r3, [pc, #740] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8001f62: 685b ldr r3, [r3, #4]
8001f64: f003 030c and.w r3, r3, #12
8001f68: 2b08 cmp r3, #8
8001f6a: d15c bne.n 8002026 <HAL_RCC_OscConfig+0x10e>
8001f6c: 4bb6 ldr r3, [pc, #728] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8001f6e: 685b ldr r3, [r3, #4]
8001f70: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001f74: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001f78: d155 bne.n 8002026 <HAL_RCC_OscConfig+0x10e>
8001f7a: f44f 3300 mov.w r3, #131072 @ 0x20000
8001f7e: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001f82: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0
8001f86: fa93 f3a3 rbit r3, r3
8001f8a: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8001f8e: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001f92: fab3 f383 clz r3, r3
8001f96: b2db uxtb r3, r3
8001f98: 095b lsrs r3, r3, #5
8001f9a: b2db uxtb r3, r3
8001f9c: f043 0301 orr.w r3, r3, #1
8001fa0: b2db uxtb r3, r3
8001fa2: 2b01 cmp r3, #1
8001fa4: d102 bne.n 8001fac <HAL_RCC_OscConfig+0x94>
8001fa6: 4ba8 ldr r3, [pc, #672] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8001fa8: 681b ldr r3, [r3, #0]
8001faa: e015 b.n 8001fd8 <HAL_RCC_OscConfig+0xc0>
8001fac: f44f 3300 mov.w r3, #131072 @ 0x20000
8001fb0: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001fb4: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8
8001fb8: fa93 f3a3 rbit r3, r3
8001fbc: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4
8001fc0: f44f 3300 mov.w r3, #131072 @ 0x20000
8001fc4: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0
8001fc8: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0
8001fcc: fa93 f3a3 rbit r3, r3
8001fd0: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc
8001fd4: 4b9c ldr r3, [pc, #624] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8001fd6: 6a5b ldr r3, [r3, #36] @ 0x24
8001fd8: f44f 3200 mov.w r2, #131072 @ 0x20000
8001fdc: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8
8001fe0: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8
8001fe4: fa92 f2a2 rbit r2, r2
8001fe8: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4
return result;
8001fec: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4
8001ff0: fab2 f282 clz r2, r2
8001ff4: b2d2 uxtb r2, r2
8001ff6: f042 0220 orr.w r2, r2, #32
8001ffa: b2d2 uxtb r2, r2
8001ffc: f002 021f and.w r2, r2, #31
8002000: 2101 movs r1, #1
8002002: fa01 f202 lsl.w r2, r1, r2
8002006: 4013 ands r3, r2
8002008: 2b00 cmp r3, #0
800200a: f000 811f beq.w 800224c <HAL_RCC_OscConfig+0x334>
800200e: f507 7300 add.w r3, r7, #512 @ 0x200
8002012: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002016: 681b ldr r3, [r3, #0]
8002018: 685b ldr r3, [r3, #4]
800201a: 2b00 cmp r3, #0
800201c: f040 8116 bne.w 800224c <HAL_RCC_OscConfig+0x334>
{
return HAL_ERROR;
8002020: 2301 movs r3, #1
8002022: f000 bfaf b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002026: f507 7300 add.w r3, r7, #512 @ 0x200
800202a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800202e: 681b ldr r3, [r3, #0]
8002030: 685b ldr r3, [r3, #4]
8002032: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002036: d106 bne.n 8002046 <HAL_RCC_OscConfig+0x12e>
8002038: 4b83 ldr r3, [pc, #524] @ (8002248 <HAL_RCC_OscConfig+0x330>)
800203a: 681b ldr r3, [r3, #0]
800203c: 4a82 ldr r2, [pc, #520] @ (8002248 <HAL_RCC_OscConfig+0x330>)
800203e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002042: 6013 str r3, [r2, #0]
8002044: e036 b.n 80020b4 <HAL_RCC_OscConfig+0x19c>
8002046: f507 7300 add.w r3, r7, #512 @ 0x200
800204a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800204e: 681b ldr r3, [r3, #0]
8002050: 685b ldr r3, [r3, #4]
8002052: 2b00 cmp r3, #0
8002054: d10c bne.n 8002070 <HAL_RCC_OscConfig+0x158>
8002056: 4b7c ldr r3, [pc, #496] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8002058: 681b ldr r3, [r3, #0]
800205a: 4a7b ldr r2, [pc, #492] @ (8002248 <HAL_RCC_OscConfig+0x330>)
800205c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002060: 6013 str r3, [r2, #0]
8002062: 4b79 ldr r3, [pc, #484] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8002064: 681b ldr r3, [r3, #0]
8002066: 4a78 ldr r2, [pc, #480] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8002068: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800206c: 6013 str r3, [r2, #0]
800206e: e021 b.n 80020b4 <HAL_RCC_OscConfig+0x19c>
8002070: f507 7300 add.w r3, r7, #512 @ 0x200
8002074: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002078: 681b ldr r3, [r3, #0]
800207a: 685b ldr r3, [r3, #4]
800207c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8002080: d10c bne.n 800209c <HAL_RCC_OscConfig+0x184>
8002082: 4b71 ldr r3, [pc, #452] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8002084: 681b ldr r3, [r3, #0]
8002086: 4a70 ldr r2, [pc, #448] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8002088: f443 2380 orr.w r3, r3, #262144 @ 0x40000
800208c: 6013 str r3, [r2, #0]
800208e: 4b6e ldr r3, [pc, #440] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8002090: 681b ldr r3, [r3, #0]
8002092: 4a6d ldr r2, [pc, #436] @ (8002248 <HAL_RCC_OscConfig+0x330>)
8002094: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002098: 6013 str r3, [r2, #0]
800209a: e00b b.n 80020b4 <HAL_RCC_OscConfig+0x19c>
800209c: 4b6a ldr r3, [pc, #424] @ (8002248 <HAL_RCC_OscConfig+0x330>)
800209e: 681b ldr r3, [r3, #0]
80020a0: 4a69 ldr r2, [pc, #420] @ (8002248 <HAL_RCC_OscConfig+0x330>)
80020a2: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80020a6: 6013 str r3, [r2, #0]
80020a8: 4b67 ldr r3, [pc, #412] @ (8002248 <HAL_RCC_OscConfig+0x330>)
80020aa: 681b ldr r3, [r3, #0]
80020ac: 4a66 ldr r2, [pc, #408] @ (8002248 <HAL_RCC_OscConfig+0x330>)
80020ae: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80020b2: 6013 str r3, [r2, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
/* Configure the HSE predivision factor --------------------------------*/
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
80020b4: 4b64 ldr r3, [pc, #400] @ (8002248 <HAL_RCC_OscConfig+0x330>)
80020b6: 6adb ldr r3, [r3, #44] @ 0x2c
80020b8: f023 020f bic.w r2, r3, #15
80020bc: f507 7300 add.w r3, r7, #512 @ 0x200
80020c0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80020c4: 681b ldr r3, [r3, #0]
80020c6: 689b ldr r3, [r3, #8]
80020c8: 495f ldr r1, [pc, #380] @ (8002248 <HAL_RCC_OscConfig+0x330>)
80020ca: 4313 orrs r3, r2
80020cc: 62cb str r3, [r1, #44] @ 0x2c
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80020ce: f507 7300 add.w r3, r7, #512 @ 0x200
80020d2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80020d6: 681b ldr r3, [r3, #0]
80020d8: 685b ldr r3, [r3, #4]
80020da: 2b00 cmp r3, #0
80020dc: d059 beq.n 8002192 <HAL_RCC_OscConfig+0x27a>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80020de: f7fe fd8f bl 8000c00 <HAL_GetTick>
80020e2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80020e6: e00a b.n 80020fe <HAL_RCC_OscConfig+0x1e6>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80020e8: f7fe fd8a bl 8000c00 <HAL_GetTick>
80020ec: 4602 mov r2, r0
80020ee: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80020f2: 1ad3 subs r3, r2, r3
80020f4: 2b64 cmp r3, #100 @ 0x64
80020f6: d902 bls.n 80020fe <HAL_RCC_OscConfig+0x1e6>
{
return HAL_TIMEOUT;
80020f8: 2303 movs r3, #3
80020fa: f000 bf43 b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
80020fe: f44f 3300 mov.w r3, #131072 @ 0x20000
8002102: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002106: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0
800210a: fa93 f3a3 rbit r3, r3
800210e: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc
return result;
8002112: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002116: fab3 f383 clz r3, r3
800211a: b2db uxtb r3, r3
800211c: 095b lsrs r3, r3, #5
800211e: b2db uxtb r3, r3
8002120: f043 0301 orr.w r3, r3, #1
8002124: b2db uxtb r3, r3
8002126: 2b01 cmp r3, #1
8002128: d102 bne.n 8002130 <HAL_RCC_OscConfig+0x218>
800212a: 4b47 ldr r3, [pc, #284] @ (8002248 <HAL_RCC_OscConfig+0x330>)
800212c: 681b ldr r3, [r3, #0]
800212e: e015 b.n 800215c <HAL_RCC_OscConfig+0x244>
8002130: f44f 3300 mov.w r3, #131072 @ 0x20000
8002134: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002138: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8
800213c: fa93 f3a3 rbit r3, r3
8002140: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4
8002144: f44f 3300 mov.w r3, #131072 @ 0x20000
8002148: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0
800214c: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0
8002150: fa93 f3a3 rbit r3, r3
8002154: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc
8002158: 4b3b ldr r3, [pc, #236] @ (8002248 <HAL_RCC_OscConfig+0x330>)
800215a: 6a5b ldr r3, [r3, #36] @ 0x24
800215c: f44f 3200 mov.w r2, #131072 @ 0x20000
8002160: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8
8002164: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8
8002168: fa92 f2a2 rbit r2, r2
800216c: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4
return result;
8002170: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4
8002174: fab2 f282 clz r2, r2
8002178: b2d2 uxtb r2, r2
800217a: f042 0220 orr.w r2, r2, #32
800217e: b2d2 uxtb r2, r2
8002180: f002 021f and.w r2, r2, #31
8002184: 2101 movs r1, #1
8002186: fa01 f202 lsl.w r2, r1, r2
800218a: 4013 ands r3, r2
800218c: 2b00 cmp r3, #0
800218e: d0ab beq.n 80020e8 <HAL_RCC_OscConfig+0x1d0>
8002190: e05d b.n 800224e <HAL_RCC_OscConfig+0x336>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002192: f7fe fd35 bl 8000c00 <HAL_GetTick>
8002196: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800219a: e00a b.n 80021b2 <HAL_RCC_OscConfig+0x29a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800219c: f7fe fd30 bl 8000c00 <HAL_GetTick>
80021a0: 4602 mov r2, r0
80021a2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80021a6: 1ad3 subs r3, r2, r3
80021a8: 2b64 cmp r3, #100 @ 0x64
80021aa: d902 bls.n 80021b2 <HAL_RCC_OscConfig+0x29a>
{
return HAL_TIMEOUT;
80021ac: 2303 movs r3, #3
80021ae: f000 bee9 b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
80021b2: f44f 3300 mov.w r3, #131072 @ 0x20000
80021b6: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80021ba: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0
80021be: fa93 f3a3 rbit r3, r3
80021c2: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac
return result;
80021c6: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80021ca: fab3 f383 clz r3, r3
80021ce: b2db uxtb r3, r3
80021d0: 095b lsrs r3, r3, #5
80021d2: b2db uxtb r3, r3
80021d4: f043 0301 orr.w r3, r3, #1
80021d8: b2db uxtb r3, r3
80021da: 2b01 cmp r3, #1
80021dc: d102 bne.n 80021e4 <HAL_RCC_OscConfig+0x2cc>
80021de: 4b1a ldr r3, [pc, #104] @ (8002248 <HAL_RCC_OscConfig+0x330>)
80021e0: 681b ldr r3, [r3, #0]
80021e2: e015 b.n 8002210 <HAL_RCC_OscConfig+0x2f8>
80021e4: f44f 3300 mov.w r3, #131072 @ 0x20000
80021e8: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80021ec: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8
80021f0: fa93 f3a3 rbit r3, r3
80021f4: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4
80021f8: f44f 3300 mov.w r3, #131072 @ 0x20000
80021fc: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0
8002200: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0
8002204: fa93 f3a3 rbit r3, r3
8002208: f8c7 319c str.w r3, [r7, #412] @ 0x19c
800220c: 4b0e ldr r3, [pc, #56] @ (8002248 <HAL_RCC_OscConfig+0x330>)
800220e: 6a5b ldr r3, [r3, #36] @ 0x24
8002210: f44f 3200 mov.w r2, #131072 @ 0x20000
8002214: f8c7 2198 str.w r2, [r7, #408] @ 0x198
8002218: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198
800221c: fa92 f2a2 rbit r2, r2
8002220: f8c7 2194 str.w r2, [r7, #404] @ 0x194
return result;
8002224: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194
8002228: fab2 f282 clz r2, r2
800222c: b2d2 uxtb r2, r2
800222e: f042 0220 orr.w r2, r2, #32
8002232: b2d2 uxtb r2, r2
8002234: f002 021f and.w r2, r2, #31
8002238: 2101 movs r1, #1
800223a: fa01 f202 lsl.w r2, r1, r2
800223e: 4013 ands r3, r2
8002240: 2b00 cmp r3, #0
8002242: d1ab bne.n 800219c <HAL_RCC_OscConfig+0x284>
8002244: e003 b.n 800224e <HAL_RCC_OscConfig+0x336>
8002246: bf00 nop
8002248: 40021000 .word 0x40021000
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800224c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800224e: f507 7300 add.w r3, r7, #512 @ 0x200
8002252: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002256: 681b ldr r3, [r3, #0]
8002258: 681b ldr r3, [r3, #0]
800225a: f003 0302 and.w r3, r3, #2
800225e: 2b00 cmp r3, #0
8002260: f000 817d beq.w 800255e <HAL_RCC_OscConfig+0x646>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8002264: 4ba6 ldr r3, [pc, #664] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
8002266: 685b ldr r3, [r3, #4]
8002268: f003 030c and.w r3, r3, #12
800226c: 2b00 cmp r3, #0
800226e: d00b beq.n 8002288 <HAL_RCC_OscConfig+0x370>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8002270: 4ba3 ldr r3, [pc, #652] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
8002272: 685b ldr r3, [r3, #4]
8002274: f003 030c and.w r3, r3, #12
8002278: 2b08 cmp r3, #8
800227a: d172 bne.n 8002362 <HAL_RCC_OscConfig+0x44a>
800227c: 4ba0 ldr r3, [pc, #640] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
800227e: 685b ldr r3, [r3, #4]
8002280: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002284: 2b00 cmp r3, #0
8002286: d16c bne.n 8002362 <HAL_RCC_OscConfig+0x44a>
8002288: 2302 movs r3, #2
800228a: f8c7 3190 str.w r3, [r7, #400] @ 0x190
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800228e: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190
8002292: fa93 f3a3 rbit r3, r3
8002296: f8c7 318c str.w r3, [r7, #396] @ 0x18c
return result;
800229a: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800229e: fab3 f383 clz r3, r3
80022a2: b2db uxtb r3, r3
80022a4: 095b lsrs r3, r3, #5
80022a6: b2db uxtb r3, r3
80022a8: f043 0301 orr.w r3, r3, #1
80022ac: b2db uxtb r3, r3
80022ae: 2b01 cmp r3, #1
80022b0: d102 bne.n 80022b8 <HAL_RCC_OscConfig+0x3a0>
80022b2: 4b93 ldr r3, [pc, #588] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
80022b4: 681b ldr r3, [r3, #0]
80022b6: e013 b.n 80022e0 <HAL_RCC_OscConfig+0x3c8>
80022b8: 2302 movs r3, #2
80022ba: f8c7 3188 str.w r3, [r7, #392] @ 0x188
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80022be: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188
80022c2: fa93 f3a3 rbit r3, r3
80022c6: f8c7 3184 str.w r3, [r7, #388] @ 0x184
80022ca: 2302 movs r3, #2
80022cc: f8c7 3180 str.w r3, [r7, #384] @ 0x180
80022d0: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180
80022d4: fa93 f3a3 rbit r3, r3
80022d8: f8c7 317c str.w r3, [r7, #380] @ 0x17c
80022dc: 4b88 ldr r3, [pc, #544] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
80022de: 6a5b ldr r3, [r3, #36] @ 0x24
80022e0: 2202 movs r2, #2
80022e2: f8c7 2178 str.w r2, [r7, #376] @ 0x178
80022e6: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178
80022ea: fa92 f2a2 rbit r2, r2
80022ee: f8c7 2174 str.w r2, [r7, #372] @ 0x174
return result;
80022f2: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174
80022f6: fab2 f282 clz r2, r2
80022fa: b2d2 uxtb r2, r2
80022fc: f042 0220 orr.w r2, r2, #32
8002300: b2d2 uxtb r2, r2
8002302: f002 021f and.w r2, r2, #31
8002306: 2101 movs r1, #1
8002308: fa01 f202 lsl.w r2, r1, r2
800230c: 4013 ands r3, r2
800230e: 2b00 cmp r3, #0
8002310: d00a beq.n 8002328 <HAL_RCC_OscConfig+0x410>
8002312: f507 7300 add.w r3, r7, #512 @ 0x200
8002316: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800231a: 681b ldr r3, [r3, #0]
800231c: 691b ldr r3, [r3, #16]
800231e: 2b01 cmp r3, #1
8002320: d002 beq.n 8002328 <HAL_RCC_OscConfig+0x410>
{
return HAL_ERROR;
8002322: 2301 movs r3, #1
8002324: f000 be2e b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002328: 4b75 ldr r3, [pc, #468] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
800232a: 681b ldr r3, [r3, #0]
800232c: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8002330: f507 7300 add.w r3, r7, #512 @ 0x200
8002334: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002338: 681b ldr r3, [r3, #0]
800233a: 695b ldr r3, [r3, #20]
800233c: 21f8 movs r1, #248 @ 0xf8
800233e: f8c7 1170 str.w r1, [r7, #368] @ 0x170
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002342: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170
8002346: fa91 f1a1 rbit r1, r1
800234a: f8c7 116c str.w r1, [r7, #364] @ 0x16c
return result;
800234e: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c
8002352: fab1 f181 clz r1, r1
8002356: b2c9 uxtb r1, r1
8002358: 408b lsls r3, r1
800235a: 4969 ldr r1, [pc, #420] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
800235c: 4313 orrs r3, r2
800235e: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002360: e0fd b.n 800255e <HAL_RCC_OscConfig+0x646>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8002362: f507 7300 add.w r3, r7, #512 @ 0x200
8002366: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800236a: 681b ldr r3, [r3, #0]
800236c: 691b ldr r3, [r3, #16]
800236e: 2b00 cmp r3, #0
8002370: f000 8088 beq.w 8002484 <HAL_RCC_OscConfig+0x56c>
8002374: 2301 movs r3, #1
8002376: f8c7 3168 str.w r3, [r7, #360] @ 0x168
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800237a: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168
800237e: fa93 f3a3 rbit r3, r3
8002382: f8c7 3164 str.w r3, [r7, #356] @ 0x164
return result;
8002386: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800238a: fab3 f383 clz r3, r3
800238e: b2db uxtb r3, r3
8002390: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8002394: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002398: 009b lsls r3, r3, #2
800239a: 461a mov r2, r3
800239c: 2301 movs r3, #1
800239e: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80023a0: f7fe fc2e bl 8000c00 <HAL_GetTick>
80023a4: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80023a8: e00a b.n 80023c0 <HAL_RCC_OscConfig+0x4a8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80023aa: f7fe fc29 bl 8000c00 <HAL_GetTick>
80023ae: 4602 mov r2, r0
80023b0: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80023b4: 1ad3 subs r3, r2, r3
80023b6: 2b02 cmp r3, #2
80023b8: d902 bls.n 80023c0 <HAL_RCC_OscConfig+0x4a8>
{
return HAL_TIMEOUT;
80023ba: 2303 movs r3, #3
80023bc: f000 bde2 b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
80023c0: 2302 movs r3, #2
80023c2: f8c7 3160 str.w r3, [r7, #352] @ 0x160
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80023c6: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160
80023ca: fa93 f3a3 rbit r3, r3
80023ce: f8c7 315c str.w r3, [r7, #348] @ 0x15c
return result;
80023d2: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80023d6: fab3 f383 clz r3, r3
80023da: b2db uxtb r3, r3
80023dc: 095b lsrs r3, r3, #5
80023de: b2db uxtb r3, r3
80023e0: f043 0301 orr.w r3, r3, #1
80023e4: b2db uxtb r3, r3
80023e6: 2b01 cmp r3, #1
80023e8: d102 bne.n 80023f0 <HAL_RCC_OscConfig+0x4d8>
80023ea: 4b45 ldr r3, [pc, #276] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
80023ec: 681b ldr r3, [r3, #0]
80023ee: e013 b.n 8002418 <HAL_RCC_OscConfig+0x500>
80023f0: 2302 movs r3, #2
80023f2: f8c7 3158 str.w r3, [r7, #344] @ 0x158
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80023f6: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158
80023fa: fa93 f3a3 rbit r3, r3
80023fe: f8c7 3154 str.w r3, [r7, #340] @ 0x154
8002402: 2302 movs r3, #2
8002404: f8c7 3150 str.w r3, [r7, #336] @ 0x150
8002408: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150
800240c: fa93 f3a3 rbit r3, r3
8002410: f8c7 314c str.w r3, [r7, #332] @ 0x14c
8002414: 4b3a ldr r3, [pc, #232] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
8002416: 6a5b ldr r3, [r3, #36] @ 0x24
8002418: 2202 movs r2, #2
800241a: f8c7 2148 str.w r2, [r7, #328] @ 0x148
800241e: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148
8002422: fa92 f2a2 rbit r2, r2
8002426: f8c7 2144 str.w r2, [r7, #324] @ 0x144
return result;
800242a: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144
800242e: fab2 f282 clz r2, r2
8002432: b2d2 uxtb r2, r2
8002434: f042 0220 orr.w r2, r2, #32
8002438: b2d2 uxtb r2, r2
800243a: f002 021f and.w r2, r2, #31
800243e: 2101 movs r1, #1
8002440: fa01 f202 lsl.w r2, r1, r2
8002444: 4013 ands r3, r2
8002446: 2b00 cmp r3, #0
8002448: d0af beq.n 80023aa <HAL_RCC_OscConfig+0x492>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800244a: 4b2d ldr r3, [pc, #180] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
800244c: 681b ldr r3, [r3, #0]
800244e: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8002452: f507 7300 add.w r3, r7, #512 @ 0x200
8002456: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800245a: 681b ldr r3, [r3, #0]
800245c: 695b ldr r3, [r3, #20]
800245e: 21f8 movs r1, #248 @ 0xf8
8002460: f8c7 1140 str.w r1, [r7, #320] @ 0x140
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002464: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140
8002468: fa91 f1a1 rbit r1, r1
800246c: f8c7 113c str.w r1, [r7, #316] @ 0x13c
return result;
8002470: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c
8002474: fab1 f181 clz r1, r1
8002478: b2c9 uxtb r1, r1
800247a: 408b lsls r3, r1
800247c: 4920 ldr r1, [pc, #128] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
800247e: 4313 orrs r3, r2
8002480: 600b str r3, [r1, #0]
8002482: e06c b.n 800255e <HAL_RCC_OscConfig+0x646>
8002484: 2301 movs r3, #1
8002486: f8c7 3138 str.w r3, [r7, #312] @ 0x138
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800248a: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138
800248e: fa93 f3a3 rbit r3, r3
8002492: f8c7 3134 str.w r3, [r7, #308] @ 0x134
return result;
8002496: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800249a: fab3 f383 clz r3, r3
800249e: b2db uxtb r3, r3
80024a0: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
80024a4: f503 1384 add.w r3, r3, #1081344 @ 0x108000
80024a8: 009b lsls r3, r3, #2
80024aa: 461a mov r2, r3
80024ac: 2300 movs r3, #0
80024ae: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80024b0: f7fe fba6 bl 8000c00 <HAL_GetTick>
80024b4: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80024b8: e00a b.n 80024d0 <HAL_RCC_OscConfig+0x5b8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80024ba: f7fe fba1 bl 8000c00 <HAL_GetTick>
80024be: 4602 mov r2, r0
80024c0: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80024c4: 1ad3 subs r3, r2, r3
80024c6: 2b02 cmp r3, #2
80024c8: d902 bls.n 80024d0 <HAL_RCC_OscConfig+0x5b8>
{
return HAL_TIMEOUT;
80024ca: 2303 movs r3, #3
80024cc: f000 bd5a b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
80024d0: 2302 movs r3, #2
80024d2: f8c7 3130 str.w r3, [r7, #304] @ 0x130
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80024d6: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130
80024da: fa93 f3a3 rbit r3, r3
80024de: f8c7 312c str.w r3, [r7, #300] @ 0x12c
return result;
80024e2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80024e6: fab3 f383 clz r3, r3
80024ea: b2db uxtb r3, r3
80024ec: 095b lsrs r3, r3, #5
80024ee: b2db uxtb r3, r3
80024f0: f043 0301 orr.w r3, r3, #1
80024f4: b2db uxtb r3, r3
80024f6: 2b01 cmp r3, #1
80024f8: d104 bne.n 8002504 <HAL_RCC_OscConfig+0x5ec>
80024fa: 4b01 ldr r3, [pc, #4] @ (8002500 <HAL_RCC_OscConfig+0x5e8>)
80024fc: 681b ldr r3, [r3, #0]
80024fe: e015 b.n 800252c <HAL_RCC_OscConfig+0x614>
8002500: 40021000 .word 0x40021000
8002504: 2302 movs r3, #2
8002506: f8c7 3128 str.w r3, [r7, #296] @ 0x128
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800250a: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128
800250e: fa93 f3a3 rbit r3, r3
8002512: f8c7 3124 str.w r3, [r7, #292] @ 0x124
8002516: 2302 movs r3, #2
8002518: f8c7 3120 str.w r3, [r7, #288] @ 0x120
800251c: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120
8002520: fa93 f3a3 rbit r3, r3
8002524: f8c7 311c str.w r3, [r7, #284] @ 0x11c
8002528: 4bc8 ldr r3, [pc, #800] @ (800284c <HAL_RCC_OscConfig+0x934>)
800252a: 6a5b ldr r3, [r3, #36] @ 0x24
800252c: 2202 movs r2, #2
800252e: f8c7 2118 str.w r2, [r7, #280] @ 0x118
8002532: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118
8002536: fa92 f2a2 rbit r2, r2
800253a: f8c7 2114 str.w r2, [r7, #276] @ 0x114
return result;
800253e: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114
8002542: fab2 f282 clz r2, r2
8002546: b2d2 uxtb r2, r2
8002548: f042 0220 orr.w r2, r2, #32
800254c: b2d2 uxtb r2, r2
800254e: f002 021f and.w r2, r2, #31
8002552: 2101 movs r1, #1
8002554: fa01 f202 lsl.w r2, r1, r2
8002558: 4013 ands r3, r2
800255a: 2b00 cmp r3, #0
800255c: d1ad bne.n 80024ba <HAL_RCC_OscConfig+0x5a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800255e: f507 7300 add.w r3, r7, #512 @ 0x200
8002562: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002566: 681b ldr r3, [r3, #0]
8002568: 681b ldr r3, [r3, #0]
800256a: f003 0308 and.w r3, r3, #8
800256e: 2b00 cmp r3, #0
8002570: f000 8110 beq.w 8002794 <HAL_RCC_OscConfig+0x87c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8002574: f507 7300 add.w r3, r7, #512 @ 0x200
8002578: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800257c: 681b ldr r3, [r3, #0]
800257e: 699b ldr r3, [r3, #24]
8002580: 2b00 cmp r3, #0
8002582: d079 beq.n 8002678 <HAL_RCC_OscConfig+0x760>
8002584: 2301 movs r3, #1
8002586: f8c7 3110 str.w r3, [r7, #272] @ 0x110
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800258a: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110
800258e: fa93 f3a3 rbit r3, r3
8002592: f8c7 310c str.w r3, [r7, #268] @ 0x10c
return result;
8002596: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
800259a: fab3 f383 clz r3, r3
800259e: b2db uxtb r3, r3
80025a0: 461a mov r2, r3
80025a2: 4bab ldr r3, [pc, #684] @ (8002850 <HAL_RCC_OscConfig+0x938>)
80025a4: 4413 add r3, r2
80025a6: 009b lsls r3, r3, #2
80025a8: 461a mov r2, r3
80025aa: 2301 movs r3, #1
80025ac: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80025ae: f7fe fb27 bl 8000c00 <HAL_GetTick>
80025b2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80025b6: e00a b.n 80025ce <HAL_RCC_OscConfig+0x6b6>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80025b8: f7fe fb22 bl 8000c00 <HAL_GetTick>
80025bc: 4602 mov r2, r0
80025be: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80025c2: 1ad3 subs r3, r2, r3
80025c4: 2b02 cmp r3, #2
80025c6: d902 bls.n 80025ce <HAL_RCC_OscConfig+0x6b6>
{
return HAL_TIMEOUT;
80025c8: 2303 movs r3, #3
80025ca: f000 bcdb b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
80025ce: 2302 movs r3, #2
80025d0: f8c7 3108 str.w r3, [r7, #264] @ 0x108
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80025d4: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108
80025d8: fa93 f3a3 rbit r3, r3
80025dc: f8c7 3104 str.w r3, [r7, #260] @ 0x104
80025e0: f507 7300 add.w r3, r7, #512 @ 0x200
80025e4: f5a3 7380 sub.w r3, r3, #256 @ 0x100
80025e8: 2202 movs r2, #2
80025ea: 601a str r2, [r3, #0]
80025ec: f507 7300 add.w r3, r7, #512 @ 0x200
80025f0: f5a3 7380 sub.w r3, r3, #256 @ 0x100
80025f4: 681b ldr r3, [r3, #0]
80025f6: fa93 f2a3 rbit r2, r3
80025fa: f507 7300 add.w r3, r7, #512 @ 0x200
80025fe: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8002602: 601a str r2, [r3, #0]
8002604: f507 7300 add.w r3, r7, #512 @ 0x200
8002608: f5a3 7384 sub.w r3, r3, #264 @ 0x108
800260c: 2202 movs r2, #2
800260e: 601a str r2, [r3, #0]
8002610: f507 7300 add.w r3, r7, #512 @ 0x200
8002614: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8002618: 681b ldr r3, [r3, #0]
800261a: fa93 f2a3 rbit r2, r3
800261e: f507 7300 add.w r3, r7, #512 @ 0x200
8002622: f5a3 7386 sub.w r3, r3, #268 @ 0x10c
8002626: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002628: 4b88 ldr r3, [pc, #544] @ (800284c <HAL_RCC_OscConfig+0x934>)
800262a: 6a5a ldr r2, [r3, #36] @ 0x24
800262c: f507 7300 add.w r3, r7, #512 @ 0x200
8002630: f5a3 7388 sub.w r3, r3, #272 @ 0x110
8002634: 2102 movs r1, #2
8002636: 6019 str r1, [r3, #0]
8002638: f507 7300 add.w r3, r7, #512 @ 0x200
800263c: f5a3 7388 sub.w r3, r3, #272 @ 0x110
8002640: 681b ldr r3, [r3, #0]
8002642: fa93 f1a3 rbit r1, r3
8002646: f507 7300 add.w r3, r7, #512 @ 0x200
800264a: f5a3 738a sub.w r3, r3, #276 @ 0x114
800264e: 6019 str r1, [r3, #0]
return result;
8002650: f507 7300 add.w r3, r7, #512 @ 0x200
8002654: f5a3 738a sub.w r3, r3, #276 @ 0x114
8002658: 681b ldr r3, [r3, #0]
800265a: fab3 f383 clz r3, r3
800265e: b2db uxtb r3, r3
8002660: f043 0360 orr.w r3, r3, #96 @ 0x60
8002664: b2db uxtb r3, r3
8002666: f003 031f and.w r3, r3, #31
800266a: 2101 movs r1, #1
800266c: fa01 f303 lsl.w r3, r1, r3
8002670: 4013 ands r3, r2
8002672: 2b00 cmp r3, #0
8002674: d0a0 beq.n 80025b8 <HAL_RCC_OscConfig+0x6a0>
8002676: e08d b.n 8002794 <HAL_RCC_OscConfig+0x87c>
8002678: f507 7300 add.w r3, r7, #512 @ 0x200
800267c: f5a3 738c sub.w r3, r3, #280 @ 0x118
8002680: 2201 movs r2, #1
8002682: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002684: f507 7300 add.w r3, r7, #512 @ 0x200
8002688: f5a3 738c sub.w r3, r3, #280 @ 0x118
800268c: 681b ldr r3, [r3, #0]
800268e: fa93 f2a3 rbit r2, r3
8002692: f507 7300 add.w r3, r7, #512 @ 0x200
8002696: f5a3 738e sub.w r3, r3, #284 @ 0x11c
800269a: 601a str r2, [r3, #0]
return result;
800269c: f507 7300 add.w r3, r7, #512 @ 0x200
80026a0: f5a3 738e sub.w r3, r3, #284 @ 0x11c
80026a4: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80026a6: fab3 f383 clz r3, r3
80026aa: b2db uxtb r3, r3
80026ac: 461a mov r2, r3
80026ae: 4b68 ldr r3, [pc, #416] @ (8002850 <HAL_RCC_OscConfig+0x938>)
80026b0: 4413 add r3, r2
80026b2: 009b lsls r3, r3, #2
80026b4: 461a mov r2, r3
80026b6: 2300 movs r3, #0
80026b8: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80026ba: f7fe faa1 bl 8000c00 <HAL_GetTick>
80026be: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80026c2: e00a b.n 80026da <HAL_RCC_OscConfig+0x7c2>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80026c4: f7fe fa9c bl 8000c00 <HAL_GetTick>
80026c8: 4602 mov r2, r0
80026ca: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80026ce: 1ad3 subs r3, r2, r3
80026d0: 2b02 cmp r3, #2
80026d2: d902 bls.n 80026da <HAL_RCC_OscConfig+0x7c2>
{
return HAL_TIMEOUT;
80026d4: 2303 movs r3, #3
80026d6: f000 bc55 b.w 8002f84 <HAL_RCC_OscConfig+0x106c>
80026da: f507 7300 add.w r3, r7, #512 @ 0x200
80026de: f5a3 7390 sub.w r3, r3, #288 @ 0x120
80026e2: 2202 movs r2, #2
80026e4: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80026e6: f507 7300 add.w r3, r7, #512 @ 0x200
80026ea: f5a3 7390 sub.w r3, r3, #288 @ 0x120
80026ee: 681b ldr r3, [r3, #0]
80026f0: fa93 f2a3 rbit r2, r3
80026f4: f507 7300 add.w r3, r7, #512 @ 0x200
80026f8: f5a3 7392 sub.w r3, r3, #292 @ 0x124
80026fc: 601a str r2, [r3, #0]
80026fe: f507 7300 add.w r3, r7, #512 @ 0x200
8002702: f5a3 7394 sub.w r3, r3, #296 @ 0x128
8002706: 2202 movs r2, #2
8002708: 601a str r2, [r3, #0]
800270a: f507 7300 add.w r3, r7, #512 @ 0x200
800270e: f5a3 7394 sub.w r3, r3, #296 @ 0x128
8002712: 681b ldr r3, [r3, #0]
8002714: fa93 f2a3 rbit r2, r3
8002718: f507 7300 add.w r3, r7, #512 @ 0x200
800271c: f5a3 7396 sub.w r3, r3, #300 @ 0x12c
8002720: 601a str r2, [r3, #0]
8002722: f507 7300 add.w r3, r7, #512 @ 0x200
8002726: f5a3 7398 sub.w r3, r3, #304 @ 0x130
800272a: 2202 movs r2, #2
800272c: 601a str r2, [r3, #0]
800272e: f507 7300 add.w r3, r7, #512 @ 0x200
8002732: f5a3 7398 sub.w r3, r3, #304 @ 0x130
8002736: 681b ldr r3, [r3, #0]
8002738: fa93 f2a3 rbit r2, r3
800273c: f507 7300 add.w r3, r7, #512 @ 0x200
8002740: f5a3 739a sub.w r3, r3, #308 @ 0x134
8002744: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002746: 4b41 ldr r3, [pc, #260] @ (800284c <HAL_RCC_OscConfig+0x934>)
8002748: 6a5a ldr r2, [r3, #36] @ 0x24
800274a: f507 7300 add.w r3, r7, #512 @ 0x200
800274e: f5a3 739c sub.w r3, r3, #312 @ 0x138
8002752: 2102 movs r1, #2
8002754: 6019 str r1, [r3, #0]
8002756: f507 7300 add.w r3, r7, #512 @ 0x200
800275a: f5a3 739c sub.w r3, r3, #312 @ 0x138
800275e: 681b ldr r3, [r3, #0]
8002760: fa93 f1a3 rbit r1, r3
8002764: f507 7300 add.w r3, r7, #512 @ 0x200
8002768: f5a3 739e sub.w r3, r3, #316 @ 0x13c
800276c: 6019 str r1, [r3, #0]
return result;
800276e: f507 7300 add.w r3, r7, #512 @ 0x200
8002772: f5a3 739e sub.w r3, r3, #316 @ 0x13c
8002776: 681b ldr r3, [r3, #0]
8002778: fab3 f383 clz r3, r3
800277c: b2db uxtb r3, r3
800277e: f043 0360 orr.w r3, r3, #96 @ 0x60
8002782: b2db uxtb r3, r3
8002784: f003 031f and.w r3, r3, #31
8002788: 2101 movs r1, #1
800278a: fa01 f303 lsl.w r3, r1, r3
800278e: 4013 ands r3, r2
8002790: 2b00 cmp r3, #0
8002792: d197 bne.n 80026c4 <HAL_RCC_OscConfig+0x7ac>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002794: f507 7300 add.w r3, r7, #512 @ 0x200
8002798: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800279c: 681b ldr r3, [r3, #0]
800279e: 681b ldr r3, [r3, #0]
80027a0: f003 0304 and.w r3, r3, #4
80027a4: 2b00 cmp r3, #0
80027a6: f000 81a1 beq.w 8002aec <HAL_RCC_OscConfig+0xbd4>
{
FlagStatus pwrclkchanged = RESET;
80027aa: 2300 movs r3, #0
80027ac: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80027b0: 4b26 ldr r3, [pc, #152] @ (800284c <HAL_RCC_OscConfig+0x934>)
80027b2: 69db ldr r3, [r3, #28]
80027b4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80027b8: 2b00 cmp r3, #0
80027ba: d116 bne.n 80027ea <HAL_RCC_OscConfig+0x8d2>
{
__HAL_RCC_PWR_CLK_ENABLE();
80027bc: 4b23 ldr r3, [pc, #140] @ (800284c <HAL_RCC_OscConfig+0x934>)
80027be: 69db ldr r3, [r3, #28]
80027c0: 4a22 ldr r2, [pc, #136] @ (800284c <HAL_RCC_OscConfig+0x934>)
80027c2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80027c6: 61d3 str r3, [r2, #28]
80027c8: 4b20 ldr r3, [pc, #128] @ (800284c <HAL_RCC_OscConfig+0x934>)
80027ca: 69db ldr r3, [r3, #28]
80027cc: f003 5280 and.w r2, r3, #268435456 @ 0x10000000
80027d0: f507 7300 add.w r3, r7, #512 @ 0x200
80027d4: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
80027d8: 601a str r2, [r3, #0]
80027da: f507 7300 add.w r3, r7, #512 @ 0x200
80027de: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
80027e2: 681b ldr r3, [r3, #0]
pwrclkchanged = SET;
80027e4: 2301 movs r3, #1
80027e6: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80027ea: 4b1a ldr r3, [pc, #104] @ (8002854 <HAL_RCC_OscConfig+0x93c>)
80027ec: 681b ldr r3, [r3, #0]
80027ee: f403 7380 and.w r3, r3, #256 @ 0x100
80027f2: 2b00 cmp r3, #0
80027f4: d11a bne.n 800282c <HAL_RCC_OscConfig+0x914>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80027f6: 4b17 ldr r3, [pc, #92] @ (8002854 <HAL_RCC_OscConfig+0x93c>)
80027f8: 681b ldr r3, [r3, #0]
80027fa: 4a16 ldr r2, [pc, #88] @ (8002854 <HAL_RCC_OscConfig+0x93c>)
80027fc: f443 7380 orr.w r3, r3, #256 @ 0x100
8002800: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002802: f7fe f9fd bl 8000c00 <HAL_GetTick>
8002806: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800280a: e009 b.n 8002820 <HAL_RCC_OscConfig+0x908>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800280c: f7fe f9f8 bl 8000c00 <HAL_GetTick>
8002810: 4602 mov r2, r0
8002812: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8002816: 1ad3 subs r3, r2, r3
8002818: 2b64 cmp r3, #100 @ 0x64
800281a: d901 bls.n 8002820 <HAL_RCC_OscConfig+0x908>
{
return HAL_TIMEOUT;
800281c: 2303 movs r3, #3
800281e: e3b1 b.n 8002f84 <HAL_RCC_OscConfig+0x106c>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002820: 4b0c ldr r3, [pc, #48] @ (8002854 <HAL_RCC_OscConfig+0x93c>)
8002822: 681b ldr r3, [r3, #0]
8002824: f403 7380 and.w r3, r3, #256 @ 0x100
8002828: 2b00 cmp r3, #0
800282a: d0ef beq.n 800280c <HAL_RCC_OscConfig+0x8f4>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
800282c: f507 7300 add.w r3, r7, #512 @ 0x200
8002830: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002834: 681b ldr r3, [r3, #0]
8002836: 68db ldr r3, [r3, #12]
8002838: 2b01 cmp r3, #1
800283a: d10d bne.n 8002858 <HAL_RCC_OscConfig+0x940>
800283c: 4b03 ldr r3, [pc, #12] @ (800284c <HAL_RCC_OscConfig+0x934>)
800283e: 6a1b ldr r3, [r3, #32]
8002840: 4a02 ldr r2, [pc, #8] @ (800284c <HAL_RCC_OscConfig+0x934>)
8002842: f043 0301 orr.w r3, r3, #1
8002846: 6213 str r3, [r2, #32]
8002848: e03c b.n 80028c4 <HAL_RCC_OscConfig+0x9ac>
800284a: bf00 nop
800284c: 40021000 .word 0x40021000
8002850: 10908120 .word 0x10908120
8002854: 40007000 .word 0x40007000
8002858: f507 7300 add.w r3, r7, #512 @ 0x200
800285c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002860: 681b ldr r3, [r3, #0]
8002862: 68db ldr r3, [r3, #12]
8002864: 2b00 cmp r3, #0
8002866: d10c bne.n 8002882 <HAL_RCC_OscConfig+0x96a>
8002868: 4bc1 ldr r3, [pc, #772] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
800286a: 6a1b ldr r3, [r3, #32]
800286c: 4ac0 ldr r2, [pc, #768] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
800286e: f023 0301 bic.w r3, r3, #1
8002872: 6213 str r3, [r2, #32]
8002874: 4bbe ldr r3, [pc, #760] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002876: 6a1b ldr r3, [r3, #32]
8002878: 4abd ldr r2, [pc, #756] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
800287a: f023 0304 bic.w r3, r3, #4
800287e: 6213 str r3, [r2, #32]
8002880: e020 b.n 80028c4 <HAL_RCC_OscConfig+0x9ac>
8002882: f507 7300 add.w r3, r7, #512 @ 0x200
8002886: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800288a: 681b ldr r3, [r3, #0]
800288c: 68db ldr r3, [r3, #12]
800288e: 2b05 cmp r3, #5
8002890: d10c bne.n 80028ac <HAL_RCC_OscConfig+0x994>
8002892: 4bb7 ldr r3, [pc, #732] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002894: 6a1b ldr r3, [r3, #32]
8002896: 4ab6 ldr r2, [pc, #728] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002898: f043 0304 orr.w r3, r3, #4
800289c: 6213 str r3, [r2, #32]
800289e: 4bb4 ldr r3, [pc, #720] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
80028a0: 6a1b ldr r3, [r3, #32]
80028a2: 4ab3 ldr r2, [pc, #716] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
80028a4: f043 0301 orr.w r3, r3, #1
80028a8: 6213 str r3, [r2, #32]
80028aa: e00b b.n 80028c4 <HAL_RCC_OscConfig+0x9ac>
80028ac: 4bb0 ldr r3, [pc, #704] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
80028ae: 6a1b ldr r3, [r3, #32]
80028b0: 4aaf ldr r2, [pc, #700] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
80028b2: f023 0301 bic.w r3, r3, #1
80028b6: 6213 str r3, [r2, #32]
80028b8: 4bad ldr r3, [pc, #692] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
80028ba: 6a1b ldr r3, [r3, #32]
80028bc: 4aac ldr r2, [pc, #688] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
80028be: f023 0304 bic.w r3, r3, #4
80028c2: 6213 str r3, [r2, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80028c4: f507 7300 add.w r3, r7, #512 @ 0x200
80028c8: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80028cc: 681b ldr r3, [r3, #0]
80028ce: 68db ldr r3, [r3, #12]
80028d0: 2b00 cmp r3, #0
80028d2: f000 8081 beq.w 80029d8 <HAL_RCC_OscConfig+0xac0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80028d6: f7fe f993 bl 8000c00 <HAL_GetTick>
80028da: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80028de: e00b b.n 80028f8 <HAL_RCC_OscConfig+0x9e0>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80028e0: f7fe f98e bl 8000c00 <HAL_GetTick>
80028e4: 4602 mov r2, r0
80028e6: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80028ea: 1ad3 subs r3, r2, r3
80028ec: f241 3288 movw r2, #5000 @ 0x1388
80028f0: 4293 cmp r3, r2
80028f2: d901 bls.n 80028f8 <HAL_RCC_OscConfig+0x9e0>
{
return HAL_TIMEOUT;
80028f4: 2303 movs r3, #3
80028f6: e345 b.n 8002f84 <HAL_RCC_OscConfig+0x106c>
80028f8: f507 7300 add.w r3, r7, #512 @ 0x200
80028fc: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
8002900: 2202 movs r2, #2
8002902: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002904: f507 7300 add.w r3, r7, #512 @ 0x200
8002908: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
800290c: 681b ldr r3, [r3, #0]
800290e: fa93 f2a3 rbit r2, r3
8002912: f507 7300 add.w r3, r7, #512 @ 0x200
8002916: f5a3 73a2 sub.w r3, r3, #324 @ 0x144
800291a: 601a str r2, [r3, #0]
800291c: f507 7300 add.w r3, r7, #512 @ 0x200
8002920: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
8002924: 2202 movs r2, #2
8002926: 601a str r2, [r3, #0]
8002928: f507 7300 add.w r3, r7, #512 @ 0x200
800292c: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
8002930: 681b ldr r3, [r3, #0]
8002932: fa93 f2a3 rbit r2, r3
8002936: f507 7300 add.w r3, r7, #512 @ 0x200
800293a: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
800293e: 601a str r2, [r3, #0]
return result;
8002940: f507 7300 add.w r3, r7, #512 @ 0x200
8002944: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
8002948: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800294a: fab3 f383 clz r3, r3
800294e: b2db uxtb r3, r3
8002950: 095b lsrs r3, r3, #5
8002952: b2db uxtb r3, r3
8002954: f043 0302 orr.w r3, r3, #2
8002958: b2db uxtb r3, r3
800295a: 2b02 cmp r3, #2
800295c: d102 bne.n 8002964 <HAL_RCC_OscConfig+0xa4c>
800295e: 4b84 ldr r3, [pc, #528] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002960: 6a1b ldr r3, [r3, #32]
8002962: e013 b.n 800298c <HAL_RCC_OscConfig+0xa74>
8002964: f507 7300 add.w r3, r7, #512 @ 0x200
8002968: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
800296c: 2202 movs r2, #2
800296e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002970: f507 7300 add.w r3, r7, #512 @ 0x200
8002974: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
8002978: 681b ldr r3, [r3, #0]
800297a: fa93 f2a3 rbit r2, r3
800297e: f507 7300 add.w r3, r7, #512 @ 0x200
8002982: f5a3 73aa sub.w r3, r3, #340 @ 0x154
8002986: 601a str r2, [r3, #0]
8002988: 4b79 ldr r3, [pc, #484] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
800298a: 6a5b ldr r3, [r3, #36] @ 0x24
800298c: f507 7200 add.w r2, r7, #512 @ 0x200
8002990: f5a2 72ac sub.w r2, r2, #344 @ 0x158
8002994: 2102 movs r1, #2
8002996: 6011 str r1, [r2, #0]
8002998: f507 7200 add.w r2, r7, #512 @ 0x200
800299c: f5a2 72ac sub.w r2, r2, #344 @ 0x158
80029a0: 6812 ldr r2, [r2, #0]
80029a2: fa92 f1a2 rbit r1, r2
80029a6: f507 7200 add.w r2, r7, #512 @ 0x200
80029aa: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
80029ae: 6011 str r1, [r2, #0]
return result;
80029b0: f507 7200 add.w r2, r7, #512 @ 0x200
80029b4: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
80029b8: 6812 ldr r2, [r2, #0]
80029ba: fab2 f282 clz r2, r2
80029be: b2d2 uxtb r2, r2
80029c0: f042 0240 orr.w r2, r2, #64 @ 0x40
80029c4: b2d2 uxtb r2, r2
80029c6: f002 021f and.w r2, r2, #31
80029ca: 2101 movs r1, #1
80029cc: fa01 f202 lsl.w r2, r1, r2
80029d0: 4013 ands r3, r2
80029d2: 2b00 cmp r3, #0
80029d4: d084 beq.n 80028e0 <HAL_RCC_OscConfig+0x9c8>
80029d6: e07f b.n 8002ad8 <HAL_RCC_OscConfig+0xbc0>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80029d8: f7fe f912 bl 8000c00 <HAL_GetTick>
80029dc: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80029e0: e00b b.n 80029fa <HAL_RCC_OscConfig+0xae2>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80029e2: f7fe f90d bl 8000c00 <HAL_GetTick>
80029e6: 4602 mov r2, r0
80029e8: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80029ec: 1ad3 subs r3, r2, r3
80029ee: f241 3288 movw r2, #5000 @ 0x1388
80029f2: 4293 cmp r3, r2
80029f4: d901 bls.n 80029fa <HAL_RCC_OscConfig+0xae2>
{
return HAL_TIMEOUT;
80029f6: 2303 movs r3, #3
80029f8: e2c4 b.n 8002f84 <HAL_RCC_OscConfig+0x106c>
80029fa: f507 7300 add.w r3, r7, #512 @ 0x200
80029fe: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
8002a02: 2202 movs r2, #2
8002a04: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a06: f507 7300 add.w r3, r7, #512 @ 0x200
8002a0a: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
8002a0e: 681b ldr r3, [r3, #0]
8002a10: fa93 f2a3 rbit r2, r3
8002a14: f507 7300 add.w r3, r7, #512 @ 0x200
8002a18: f5a3 73b2 sub.w r3, r3, #356 @ 0x164
8002a1c: 601a str r2, [r3, #0]
8002a1e: f507 7300 add.w r3, r7, #512 @ 0x200
8002a22: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
8002a26: 2202 movs r2, #2
8002a28: 601a str r2, [r3, #0]
8002a2a: f507 7300 add.w r3, r7, #512 @ 0x200
8002a2e: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
8002a32: 681b ldr r3, [r3, #0]
8002a34: fa93 f2a3 rbit r2, r3
8002a38: f507 7300 add.w r3, r7, #512 @ 0x200
8002a3c: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
8002a40: 601a str r2, [r3, #0]
return result;
8002a42: f507 7300 add.w r3, r7, #512 @ 0x200
8002a46: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
8002a4a: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002a4c: fab3 f383 clz r3, r3
8002a50: b2db uxtb r3, r3
8002a52: 095b lsrs r3, r3, #5
8002a54: b2db uxtb r3, r3
8002a56: f043 0302 orr.w r3, r3, #2
8002a5a: b2db uxtb r3, r3
8002a5c: 2b02 cmp r3, #2
8002a5e: d102 bne.n 8002a66 <HAL_RCC_OscConfig+0xb4e>
8002a60: 4b43 ldr r3, [pc, #268] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002a62: 6a1b ldr r3, [r3, #32]
8002a64: e013 b.n 8002a8e <HAL_RCC_OscConfig+0xb76>
8002a66: f507 7300 add.w r3, r7, #512 @ 0x200
8002a6a: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
8002a6e: 2202 movs r2, #2
8002a70: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a72: f507 7300 add.w r3, r7, #512 @ 0x200
8002a76: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
8002a7a: 681b ldr r3, [r3, #0]
8002a7c: fa93 f2a3 rbit r2, r3
8002a80: f507 7300 add.w r3, r7, #512 @ 0x200
8002a84: f5a3 73ba sub.w r3, r3, #372 @ 0x174
8002a88: 601a str r2, [r3, #0]
8002a8a: 4b39 ldr r3, [pc, #228] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002a8c: 6a5b ldr r3, [r3, #36] @ 0x24
8002a8e: f507 7200 add.w r2, r7, #512 @ 0x200
8002a92: f5a2 72bc sub.w r2, r2, #376 @ 0x178
8002a96: 2102 movs r1, #2
8002a98: 6011 str r1, [r2, #0]
8002a9a: f507 7200 add.w r2, r7, #512 @ 0x200
8002a9e: f5a2 72bc sub.w r2, r2, #376 @ 0x178
8002aa2: 6812 ldr r2, [r2, #0]
8002aa4: fa92 f1a2 rbit r1, r2
8002aa8: f507 7200 add.w r2, r7, #512 @ 0x200
8002aac: f5a2 72be sub.w r2, r2, #380 @ 0x17c
8002ab0: 6011 str r1, [r2, #0]
return result;
8002ab2: f507 7200 add.w r2, r7, #512 @ 0x200
8002ab6: f5a2 72be sub.w r2, r2, #380 @ 0x17c
8002aba: 6812 ldr r2, [r2, #0]
8002abc: fab2 f282 clz r2, r2
8002ac0: b2d2 uxtb r2, r2
8002ac2: f042 0240 orr.w r2, r2, #64 @ 0x40
8002ac6: b2d2 uxtb r2, r2
8002ac8: f002 021f and.w r2, r2, #31
8002acc: 2101 movs r1, #1
8002ace: fa01 f202 lsl.w r2, r1, r2
8002ad2: 4013 ands r3, r2
8002ad4: 2b00 cmp r3, #0
8002ad6: d184 bne.n 80029e2 <HAL_RCC_OscConfig+0xaca>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8002ad8: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff
8002adc: 2b01 cmp r3, #1
8002ade: d105 bne.n 8002aec <HAL_RCC_OscConfig+0xbd4>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002ae0: 4b23 ldr r3, [pc, #140] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002ae2: 69db ldr r3, [r3, #28]
8002ae4: 4a22 ldr r2, [pc, #136] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002ae6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002aea: 61d3 str r3, [r2, #28]
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8002aec: f507 7300 add.w r3, r7, #512 @ 0x200
8002af0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002af4: 681b ldr r3, [r3, #0]
8002af6: 69db ldr r3, [r3, #28]
8002af8: 2b00 cmp r3, #0
8002afa: f000 8242 beq.w 8002f82 <HAL_RCC_OscConfig+0x106a>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8002afe: 4b1c ldr r3, [pc, #112] @ (8002b70 <HAL_RCC_OscConfig+0xc58>)
8002b00: 685b ldr r3, [r3, #4]
8002b02: f003 030c and.w r3, r3, #12
8002b06: 2b08 cmp r3, #8
8002b08: f000 8213 beq.w 8002f32 <HAL_RCC_OscConfig+0x101a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8002b0c: f507 7300 add.w r3, r7, #512 @ 0x200
8002b10: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002b14: 681b ldr r3, [r3, #0]
8002b16: 69db ldr r3, [r3, #28]
8002b18: 2b02 cmp r3, #2
8002b1a: f040 8162 bne.w 8002de2 <HAL_RCC_OscConfig+0xeca>
8002b1e: f507 7300 add.w r3, r7, #512 @ 0x200
8002b22: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
8002b26: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8002b2a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002b2c: f507 7300 add.w r3, r7, #512 @ 0x200
8002b30: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
8002b34: 681b ldr r3, [r3, #0]
8002b36: fa93 f2a3 rbit r2, r3
8002b3a: f507 7300 add.w r3, r7, #512 @ 0x200
8002b3e: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
8002b42: 601a str r2, [r3, #0]
return result;
8002b44: f507 7300 add.w r3, r7, #512 @ 0x200
8002b48: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
8002b4c: 681b ldr r3, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002b4e: fab3 f383 clz r3, r3
8002b52: b2db uxtb r3, r3
8002b54: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8002b58: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002b5c: 009b lsls r3, r3, #2
8002b5e: 461a mov r2, r3
8002b60: 2300 movs r3, #0
8002b62: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002b64: f7fe f84c bl 8000c00 <HAL_GetTick>
8002b68: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002b6c: e00c b.n 8002b88 <HAL_RCC_OscConfig+0xc70>
8002b6e: bf00 nop
8002b70: 40021000 .word 0x40021000
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002b74: f7fe f844 bl 8000c00 <HAL_GetTick>
8002b78: 4602 mov r2, r0
8002b7a: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8002b7e: 1ad3 subs r3, r2, r3
8002b80: 2b02 cmp r3, #2
8002b82: d901 bls.n 8002b88 <HAL_RCC_OscConfig+0xc70>
{
return HAL_TIMEOUT;
8002b84: 2303 movs r3, #3
8002b86: e1fd b.n 8002f84 <HAL_RCC_OscConfig+0x106c>
8002b88: f507 7300 add.w r3, r7, #512 @ 0x200
8002b8c: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
8002b90: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002b94: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002b96: f507 7300 add.w r3, r7, #512 @ 0x200
8002b9a: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
8002b9e: 681b ldr r3, [r3, #0]
8002ba0: fa93 f2a3 rbit r2, r3
8002ba4: f507 7300 add.w r3, r7, #512 @ 0x200
8002ba8: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
8002bac: 601a str r2, [r3, #0]
return result;
8002bae: f507 7300 add.w r3, r7, #512 @ 0x200
8002bb2: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
8002bb6: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002bb8: fab3 f383 clz r3, r3
8002bbc: b2db uxtb r3, r3
8002bbe: 095b lsrs r3, r3, #5
8002bc0: b2db uxtb r3, r3
8002bc2: f043 0301 orr.w r3, r3, #1
8002bc6: b2db uxtb r3, r3
8002bc8: 2b01 cmp r3, #1
8002bca: d102 bne.n 8002bd2 <HAL_RCC_OscConfig+0xcba>
8002bcc: 4bb0 ldr r3, [pc, #704] @ (8002e90 <HAL_RCC_OscConfig+0xf78>)
8002bce: 681b ldr r3, [r3, #0]
8002bd0: e027 b.n 8002c22 <HAL_RCC_OscConfig+0xd0a>
8002bd2: f507 7300 add.w r3, r7, #512 @ 0x200
8002bd6: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
8002bda: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002bde: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002be0: f507 7300 add.w r3, r7, #512 @ 0x200
8002be4: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
8002be8: 681b ldr r3, [r3, #0]
8002bea: fa93 f2a3 rbit r2, r3
8002bee: f507 7300 add.w r3, r7, #512 @ 0x200
8002bf2: f5a3 73ca sub.w r3, r3, #404 @ 0x194
8002bf6: 601a str r2, [r3, #0]
8002bf8: f507 7300 add.w r3, r7, #512 @ 0x200
8002bfc: f5a3 73cc sub.w r3, r3, #408 @ 0x198
8002c00: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002c04: 601a str r2, [r3, #0]
8002c06: f507 7300 add.w r3, r7, #512 @ 0x200
8002c0a: f5a3 73cc sub.w r3, r3, #408 @ 0x198
8002c0e: 681b ldr r3, [r3, #0]
8002c10: fa93 f2a3 rbit r2, r3
8002c14: f507 7300 add.w r3, r7, #512 @ 0x200
8002c18: f5a3 73ce sub.w r3, r3, #412 @ 0x19c
8002c1c: 601a str r2, [r3, #0]
8002c1e: 4b9c ldr r3, [pc, #624] @ (8002e90 <HAL_RCC_OscConfig+0xf78>)
8002c20: 6a5b ldr r3, [r3, #36] @ 0x24
8002c22: f507 7200 add.w r2, r7, #512 @ 0x200
8002c26: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
8002c2a: f04f 7100 mov.w r1, #33554432 @ 0x2000000
8002c2e: 6011 str r1, [r2, #0]
8002c30: f507 7200 add.w r2, r7, #512 @ 0x200
8002c34: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
8002c38: 6812 ldr r2, [r2, #0]
8002c3a: fa92 f1a2 rbit r1, r2
8002c3e: f507 7200 add.w r2, r7, #512 @ 0x200
8002c42: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
8002c46: 6011 str r1, [r2, #0]
return result;
8002c48: f507 7200 add.w r2, r7, #512 @ 0x200
8002c4c: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
8002c50: 6812 ldr r2, [r2, #0]
8002c52: fab2 f282 clz r2, r2
8002c56: b2d2 uxtb r2, r2
8002c58: f042 0220 orr.w r2, r2, #32
8002c5c: b2d2 uxtb r2, r2
8002c5e: f002 021f and.w r2, r2, #31
8002c62: 2101 movs r1, #1
8002c64: fa01 f202 lsl.w r2, r1, r2
8002c68: 4013 ands r3, r2
8002c6a: 2b00 cmp r3, #0
8002c6c: d182 bne.n 8002b74 <HAL_RCC_OscConfig+0xc5c>
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
#else
/* Configure the main PLL clock source and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8002c6e: 4b88 ldr r3, [pc, #544] @ (8002e90 <HAL_RCC_OscConfig+0xf78>)
8002c70: 685b ldr r3, [r3, #4]
8002c72: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8002c76: f507 7300 add.w r3, r7, #512 @ 0x200
8002c7a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002c7e: 681b ldr r3, [r3, #0]
8002c80: 6a59 ldr r1, [r3, #36] @ 0x24
8002c82: f507 7300 add.w r3, r7, #512 @ 0x200
8002c86: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002c8a: 681b ldr r3, [r3, #0]
8002c8c: 6a1b ldr r3, [r3, #32]
8002c8e: 430b orrs r3, r1
8002c90: 497f ldr r1, [pc, #508] @ (8002e90 <HAL_RCC_OscConfig+0xf78>)
8002c92: 4313 orrs r3, r2
8002c94: 604b str r3, [r1, #4]
8002c96: f507 7300 add.w r3, r7, #512 @ 0x200
8002c9a: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
8002c9e: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8002ca2: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ca4: f507 7300 add.w r3, r7, #512 @ 0x200
8002ca8: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
8002cac: 681b ldr r3, [r3, #0]
8002cae: fa93 f2a3 rbit r2, r3
8002cb2: f507 7300 add.w r3, r7, #512 @ 0x200
8002cb6: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
8002cba: 601a str r2, [r3, #0]
return result;
8002cbc: f507 7300 add.w r3, r7, #512 @ 0x200
8002cc0: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
8002cc4: 681b ldr r3, [r3, #0]
RCC_OscInitStruct->PLL.PLLMUL);
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002cc6: fab3 f383 clz r3, r3
8002cca: b2db uxtb r3, r3
8002ccc: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8002cd0: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002cd4: 009b lsls r3, r3, #2
8002cd6: 461a mov r2, r3
8002cd8: 2301 movs r3, #1
8002cda: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002cdc: f7fd ff90 bl 8000c00 <HAL_GetTick>
8002ce0: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002ce4: e009 b.n 8002cfa <HAL_RCC_OscConfig+0xde2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002ce6: f7fd ff8b bl 8000c00 <HAL_GetTick>
8002cea: 4602 mov r2, r0
8002cec: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8002cf0: 1ad3 subs r3, r2, r3
8002cf2: 2b02 cmp r3, #2
8002cf4: d901 bls.n 8002cfa <HAL_RCC_OscConfig+0xde2>
{
return HAL_TIMEOUT;
8002cf6: 2303 movs r3, #3
8002cf8: e144 b.n 8002f84 <HAL_RCC_OscConfig+0x106c>
8002cfa: f507 7300 add.w r3, r7, #512 @ 0x200
8002cfe: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
8002d02: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002d06: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d08: f507 7300 add.w r3, r7, #512 @ 0x200
8002d0c: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
8002d10: 681b ldr r3, [r3, #0]
8002d12: fa93 f2a3 rbit r2, r3
8002d16: f507 7300 add.w r3, r7, #512 @ 0x200
8002d1a: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
8002d1e: 601a str r2, [r3, #0]
return result;
8002d20: f507 7300 add.w r3, r7, #512 @ 0x200
8002d24: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
8002d28: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002d2a: fab3 f383 clz r3, r3
8002d2e: b2db uxtb r3, r3
8002d30: 095b lsrs r3, r3, #5
8002d32: b2db uxtb r3, r3
8002d34: f043 0301 orr.w r3, r3, #1
8002d38: b2db uxtb r3, r3
8002d3a: 2b01 cmp r3, #1
8002d3c: d102 bne.n 8002d44 <HAL_RCC_OscConfig+0xe2c>
8002d3e: 4b54 ldr r3, [pc, #336] @ (8002e90 <HAL_RCC_OscConfig+0xf78>)
8002d40: 681b ldr r3, [r3, #0]
8002d42: e027 b.n 8002d94 <HAL_RCC_OscConfig+0xe7c>
8002d44: f507 7300 add.w r3, r7, #512 @ 0x200
8002d48: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
8002d4c: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002d50: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d52: f507 7300 add.w r3, r7, #512 @ 0x200
8002d56: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
8002d5a: 681b ldr r3, [r3, #0]
8002d5c: fa93 f2a3 rbit r2, r3
8002d60: f507 7300 add.w r3, r7, #512 @ 0x200
8002d64: f5a3 73de sub.w r3, r3, #444 @ 0x1bc
8002d68: 601a str r2, [r3, #0]
8002d6a: f507 7300 add.w r3, r7, #512 @ 0x200
8002d6e: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
8002d72: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002d76: 601a str r2, [r3, #0]
8002d78: f507 7300 add.w r3, r7, #512 @ 0x200
8002d7c: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
8002d80: 681b ldr r3, [r3, #0]
8002d82: fa93 f2a3 rbit r2, r3
8002d86: f507 7300 add.w r3, r7, #512 @ 0x200
8002d8a: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4
8002d8e: 601a str r2, [r3, #0]
8002d90: 4b3f ldr r3, [pc, #252] @ (8002e90 <HAL_RCC_OscConfig+0xf78>)
8002d92: 6a5b ldr r3, [r3, #36] @ 0x24
8002d94: f507 7200 add.w r2, r7, #512 @ 0x200
8002d98: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
8002d9c: f04f 7100 mov.w r1, #33554432 @ 0x2000000
8002da0: 6011 str r1, [r2, #0]
8002da2: f507 7200 add.w r2, r7, #512 @ 0x200
8002da6: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
8002daa: 6812 ldr r2, [r2, #0]
8002dac: fa92 f1a2 rbit r1, r2
8002db0: f507 7200 add.w r2, r7, #512 @ 0x200
8002db4: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
8002db8: 6011 str r1, [r2, #0]
return result;
8002dba: f507 7200 add.w r2, r7, #512 @ 0x200
8002dbe: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
8002dc2: 6812 ldr r2, [r2, #0]
8002dc4: fab2 f282 clz r2, r2
8002dc8: b2d2 uxtb r2, r2
8002dca: f042 0220 orr.w r2, r2, #32
8002dce: b2d2 uxtb r2, r2
8002dd0: f002 021f and.w r2, r2, #31
8002dd4: 2101 movs r1, #1
8002dd6: fa01 f202 lsl.w r2, r1, r2
8002dda: 4013 ands r3, r2
8002ddc: 2b00 cmp r3, #0
8002dde: d082 beq.n 8002ce6 <HAL_RCC_OscConfig+0xdce>
8002de0: e0cf b.n 8002f82 <HAL_RCC_OscConfig+0x106a>
8002de2: f507 7300 add.w r3, r7, #512 @ 0x200
8002de6: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
8002dea: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8002dee: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002df0: f507 7300 add.w r3, r7, #512 @ 0x200
8002df4: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
8002df8: 681b ldr r3, [r3, #0]
8002dfa: fa93 f2a3 rbit r2, r3
8002dfe: f507 7300 add.w r3, r7, #512 @ 0x200
8002e02: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
8002e06: 601a str r2, [r3, #0]
return result;
8002e08: f507 7300 add.w r3, r7, #512 @ 0x200
8002e0c: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
8002e10: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002e12: fab3 f383 clz r3, r3
8002e16: b2db uxtb r3, r3
8002e18: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8002e1c: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002e20: 009b lsls r3, r3, #2
8002e22: 461a mov r2, r3
8002e24: 2300 movs r3, #0
8002e26: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002e28: f7fd feea bl 8000c00 <HAL_GetTick>
8002e2c: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002e30: e009 b.n 8002e46 <HAL_RCC_OscConfig+0xf2e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002e32: f7fd fee5 bl 8000c00 <HAL_GetTick>
8002e36: 4602 mov r2, r0
8002e38: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8002e3c: 1ad3 subs r3, r2, r3
8002e3e: 2b02 cmp r3, #2
8002e40: d901 bls.n 8002e46 <HAL_RCC_OscConfig+0xf2e>
{
return HAL_TIMEOUT;
8002e42: 2303 movs r3, #3
8002e44: e09e b.n 8002f84 <HAL_RCC_OscConfig+0x106c>
8002e46: f507 7300 add.w r3, r7, #512 @ 0x200
8002e4a: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
8002e4e: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002e52: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e54: f507 7300 add.w r3, r7, #512 @ 0x200
8002e58: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
8002e5c: 681b ldr r3, [r3, #0]
8002e5e: fa93 f2a3 rbit r2, r3
8002e62: f507 7300 add.w r3, r7, #512 @ 0x200
8002e66: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
8002e6a: 601a str r2, [r3, #0]
return result;
8002e6c: f507 7300 add.w r3, r7, #512 @ 0x200
8002e70: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
8002e74: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002e76: fab3 f383 clz r3, r3
8002e7a: b2db uxtb r3, r3
8002e7c: 095b lsrs r3, r3, #5
8002e7e: b2db uxtb r3, r3
8002e80: f043 0301 orr.w r3, r3, #1
8002e84: b2db uxtb r3, r3
8002e86: 2b01 cmp r3, #1
8002e88: d104 bne.n 8002e94 <HAL_RCC_OscConfig+0xf7c>
8002e8a: 4b01 ldr r3, [pc, #4] @ (8002e90 <HAL_RCC_OscConfig+0xf78>)
8002e8c: 681b ldr r3, [r3, #0]
8002e8e: e029 b.n 8002ee4 <HAL_RCC_OscConfig+0xfcc>
8002e90: 40021000 .word 0x40021000
8002e94: f507 7300 add.w r3, r7, #512 @ 0x200
8002e98: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
8002e9c: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002ea0: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ea2: f507 7300 add.w r3, r7, #512 @ 0x200
8002ea6: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
8002eaa: 681b ldr r3, [r3, #0]
8002eac: fa93 f2a3 rbit r2, r3
8002eb0: f507 7300 add.w r3, r7, #512 @ 0x200
8002eb4: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4
8002eb8: 601a str r2, [r3, #0]
8002eba: f507 7300 add.w r3, r7, #512 @ 0x200
8002ebe: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
8002ec2: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002ec6: 601a str r2, [r3, #0]
8002ec8: f507 7300 add.w r3, r7, #512 @ 0x200
8002ecc: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
8002ed0: 681b ldr r3, [r3, #0]
8002ed2: fa93 f2a3 rbit r2, r3
8002ed6: f507 7300 add.w r3, r7, #512 @ 0x200
8002eda: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec
8002ede: 601a str r2, [r3, #0]
8002ee0: 4b2b ldr r3, [pc, #172] @ (8002f90 <HAL_RCC_OscConfig+0x1078>)
8002ee2: 6a5b ldr r3, [r3, #36] @ 0x24
8002ee4: f507 7200 add.w r2, r7, #512 @ 0x200
8002ee8: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
8002eec: f04f 7100 mov.w r1, #33554432 @ 0x2000000
8002ef0: 6011 str r1, [r2, #0]
8002ef2: f507 7200 add.w r2, r7, #512 @ 0x200
8002ef6: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
8002efa: 6812 ldr r2, [r2, #0]
8002efc: fa92 f1a2 rbit r1, r2
8002f00: f507 7200 add.w r2, r7, #512 @ 0x200
8002f04: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
8002f08: 6011 str r1, [r2, #0]
return result;
8002f0a: f507 7200 add.w r2, r7, #512 @ 0x200
8002f0e: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
8002f12: 6812 ldr r2, [r2, #0]
8002f14: fab2 f282 clz r2, r2
8002f18: b2d2 uxtb r2, r2
8002f1a: f042 0220 orr.w r2, r2, #32
8002f1e: b2d2 uxtb r2, r2
8002f20: f002 021f and.w r2, r2, #31
8002f24: 2101 movs r1, #1
8002f26: fa01 f202 lsl.w r2, r1, r2
8002f2a: 4013 ands r3, r2
8002f2c: 2b00 cmp r3, #0
8002f2e: d180 bne.n 8002e32 <HAL_RCC_OscConfig+0xf1a>
8002f30: e027 b.n 8002f82 <HAL_RCC_OscConfig+0x106a>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002f32: f507 7300 add.w r3, r7, #512 @ 0x200
8002f36: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002f3a: 681b ldr r3, [r3, #0]
8002f3c: 69db ldr r3, [r3, #28]
8002f3e: 2b01 cmp r3, #1
8002f40: d101 bne.n 8002f46 <HAL_RCC_OscConfig+0x102e>
{
return HAL_ERROR;
8002f42: 2301 movs r3, #1
8002f44: e01e b.n 8002f84 <HAL_RCC_OscConfig+0x106c>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8002f46: 4b12 ldr r3, [pc, #72] @ (8002f90 <HAL_RCC_OscConfig+0x1078>)
8002f48: 685b ldr r3, [r3, #4]
8002f4a: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4
pll_config2 = RCC->CFGR2;
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
#else
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002f4e: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
8002f52: f403 3280 and.w r2, r3, #65536 @ 0x10000
8002f56: f507 7300 add.w r3, r7, #512 @ 0x200
8002f5a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002f5e: 681b ldr r3, [r3, #0]
8002f60: 6a1b ldr r3, [r3, #32]
8002f62: 429a cmp r2, r3
8002f64: d10b bne.n 8002f7e <HAL_RCC_OscConfig+0x1066>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8002f66: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
8002f6a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8002f6e: f507 7300 add.w r3, r7, #512 @ 0x200
8002f72: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002f76: 681b ldr r3, [r3, #0]
8002f78: 6a5b ldr r3, [r3, #36] @ 0x24
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002f7a: 429a cmp r2, r3
8002f7c: d001 beq.n 8002f82 <HAL_RCC_OscConfig+0x106a>
#endif
{
return HAL_ERROR;
8002f7e: 2301 movs r3, #1
8002f80: e000 b.n 8002f84 <HAL_RCC_OscConfig+0x106c>
}
}
}
}
return HAL_OK;
8002f82: 2300 movs r3, #0
}
8002f84: 4618 mov r0, r3
8002f86: f507 7700 add.w r7, r7, #512 @ 0x200
8002f8a: 46bd mov sp, r7
8002f8c: bd80 pop {r7, pc}
8002f8e: bf00 nop
8002f90: 40021000 .word 0x40021000
08002f94 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002f94: b580 push {r7, lr}
8002f96: b09e sub sp, #120 @ 0x78
8002f98: af00 add r7, sp, #0
8002f9a: 6078 str r0, [r7, #4]
8002f9c: 6039 str r1, [r7, #0]
uint32_t tickstart = 0U;
8002f9e: 2300 movs r3, #0
8002fa0: 677b str r3, [r7, #116] @ 0x74
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002fa2: 687b ldr r3, [r7, #4]
8002fa4: 2b00 cmp r3, #0
8002fa6: d101 bne.n 8002fac <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002fa8: 2301 movs r3, #1
8002faa: e162 b.n 8003272 <HAL_RCC_ClockConfig+0x2de>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8002fac: 4b90 ldr r3, [pc, #576] @ (80031f0 <HAL_RCC_ClockConfig+0x25c>)
8002fae: 681b ldr r3, [r3, #0]
8002fb0: f003 0307 and.w r3, r3, #7
8002fb4: 683a ldr r2, [r7, #0]
8002fb6: 429a cmp r2, r3
8002fb8: d910 bls.n 8002fdc <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002fba: 4b8d ldr r3, [pc, #564] @ (80031f0 <HAL_RCC_ClockConfig+0x25c>)
8002fbc: 681b ldr r3, [r3, #0]
8002fbe: f023 0207 bic.w r2, r3, #7
8002fc2: 498b ldr r1, [pc, #556] @ (80031f0 <HAL_RCC_ClockConfig+0x25c>)
8002fc4: 683b ldr r3, [r7, #0]
8002fc6: 4313 orrs r3, r2
8002fc8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002fca: 4b89 ldr r3, [pc, #548] @ (80031f0 <HAL_RCC_ClockConfig+0x25c>)
8002fcc: 681b ldr r3, [r3, #0]
8002fce: f003 0307 and.w r3, r3, #7
8002fd2: 683a ldr r2, [r7, #0]
8002fd4: 429a cmp r2, r3
8002fd6: d001 beq.n 8002fdc <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8002fd8: 2301 movs r3, #1
8002fda: e14a b.n 8003272 <HAL_RCC_ClockConfig+0x2de>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002fdc: 687b ldr r3, [r7, #4]
8002fde: 681b ldr r3, [r3, #0]
8002fe0: f003 0302 and.w r3, r3, #2
8002fe4: 2b00 cmp r3, #0
8002fe6: d008 beq.n 8002ffa <HAL_RCC_ClockConfig+0x66>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002fe8: 4b82 ldr r3, [pc, #520] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
8002fea: 685b ldr r3, [r3, #4]
8002fec: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002ff0: 687b ldr r3, [r7, #4]
8002ff2: 689b ldr r3, [r3, #8]
8002ff4: 497f ldr r1, [pc, #508] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
8002ff6: 4313 orrs r3, r2
8002ff8: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002ffa: 687b ldr r3, [r7, #4]
8002ffc: 681b ldr r3, [r3, #0]
8002ffe: f003 0301 and.w r3, r3, #1
8003002: 2b00 cmp r3, #0
8003004: f000 80dc beq.w 80031c0 <HAL_RCC_ClockConfig+0x22c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8003008: 687b ldr r3, [r7, #4]
800300a: 685b ldr r3, [r3, #4]
800300c: 2b01 cmp r3, #1
800300e: d13c bne.n 800308a <HAL_RCC_ClockConfig+0xf6>
8003010: f44f 3300 mov.w r3, #131072 @ 0x20000
8003014: 673b str r3, [r7, #112] @ 0x70
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003016: 6f3b ldr r3, [r7, #112] @ 0x70
8003018: fa93 f3a3 rbit r3, r3
800301c: 66fb str r3, [r7, #108] @ 0x6c
return result;
800301e: 6efb ldr r3, [r7, #108] @ 0x6c
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8003020: fab3 f383 clz r3, r3
8003024: b2db uxtb r3, r3
8003026: 095b lsrs r3, r3, #5
8003028: b2db uxtb r3, r3
800302a: f043 0301 orr.w r3, r3, #1
800302e: b2db uxtb r3, r3
8003030: 2b01 cmp r3, #1
8003032: d102 bne.n 800303a <HAL_RCC_ClockConfig+0xa6>
8003034: 4b6f ldr r3, [pc, #444] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
8003036: 681b ldr r3, [r3, #0]
8003038: e00f b.n 800305a <HAL_RCC_ClockConfig+0xc6>
800303a: f44f 3300 mov.w r3, #131072 @ 0x20000
800303e: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003040: 6ebb ldr r3, [r7, #104] @ 0x68
8003042: fa93 f3a3 rbit r3, r3
8003046: 667b str r3, [r7, #100] @ 0x64
8003048: f44f 3300 mov.w r3, #131072 @ 0x20000
800304c: 663b str r3, [r7, #96] @ 0x60
800304e: 6e3b ldr r3, [r7, #96] @ 0x60
8003050: fa93 f3a3 rbit r3, r3
8003054: 65fb str r3, [r7, #92] @ 0x5c
8003056: 4b67 ldr r3, [pc, #412] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
8003058: 6a5b ldr r3, [r3, #36] @ 0x24
800305a: f44f 3200 mov.w r2, #131072 @ 0x20000
800305e: 65ba str r2, [r7, #88] @ 0x58
8003060: 6dba ldr r2, [r7, #88] @ 0x58
8003062: fa92 f2a2 rbit r2, r2
8003066: 657a str r2, [r7, #84] @ 0x54
return result;
8003068: 6d7a ldr r2, [r7, #84] @ 0x54
800306a: fab2 f282 clz r2, r2
800306e: b2d2 uxtb r2, r2
8003070: f042 0220 orr.w r2, r2, #32
8003074: b2d2 uxtb r2, r2
8003076: f002 021f and.w r2, r2, #31
800307a: 2101 movs r1, #1
800307c: fa01 f202 lsl.w r2, r1, r2
8003080: 4013 ands r3, r2
8003082: 2b00 cmp r3, #0
8003084: d17b bne.n 800317e <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8003086: 2301 movs r3, #1
8003088: e0f3 b.n 8003272 <HAL_RCC_ClockConfig+0x2de>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800308a: 687b ldr r3, [r7, #4]
800308c: 685b ldr r3, [r3, #4]
800308e: 2b02 cmp r3, #2
8003090: d13c bne.n 800310c <HAL_RCC_ClockConfig+0x178>
8003092: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8003096: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003098: 6d3b ldr r3, [r7, #80] @ 0x50
800309a: fa93 f3a3 rbit r3, r3
800309e: 64fb str r3, [r7, #76] @ 0x4c
return result;
80030a0: 6cfb ldr r3, [r7, #76] @ 0x4c
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80030a2: fab3 f383 clz r3, r3
80030a6: b2db uxtb r3, r3
80030a8: 095b lsrs r3, r3, #5
80030aa: b2db uxtb r3, r3
80030ac: f043 0301 orr.w r3, r3, #1
80030b0: b2db uxtb r3, r3
80030b2: 2b01 cmp r3, #1
80030b4: d102 bne.n 80030bc <HAL_RCC_ClockConfig+0x128>
80030b6: 4b4f ldr r3, [pc, #316] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
80030b8: 681b ldr r3, [r3, #0]
80030ba: e00f b.n 80030dc <HAL_RCC_ClockConfig+0x148>
80030bc: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80030c0: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80030c2: 6cbb ldr r3, [r7, #72] @ 0x48
80030c4: fa93 f3a3 rbit r3, r3
80030c8: 647b str r3, [r7, #68] @ 0x44
80030ca: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80030ce: 643b str r3, [r7, #64] @ 0x40
80030d0: 6c3b ldr r3, [r7, #64] @ 0x40
80030d2: fa93 f3a3 rbit r3, r3
80030d6: 63fb str r3, [r7, #60] @ 0x3c
80030d8: 4b46 ldr r3, [pc, #280] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
80030da: 6a5b ldr r3, [r3, #36] @ 0x24
80030dc: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80030e0: 63ba str r2, [r7, #56] @ 0x38
80030e2: 6bba ldr r2, [r7, #56] @ 0x38
80030e4: fa92 f2a2 rbit r2, r2
80030e8: 637a str r2, [r7, #52] @ 0x34
return result;
80030ea: 6b7a ldr r2, [r7, #52] @ 0x34
80030ec: fab2 f282 clz r2, r2
80030f0: b2d2 uxtb r2, r2
80030f2: f042 0220 orr.w r2, r2, #32
80030f6: b2d2 uxtb r2, r2
80030f8: f002 021f and.w r2, r2, #31
80030fc: 2101 movs r1, #1
80030fe: fa01 f202 lsl.w r2, r1, r2
8003102: 4013 ands r3, r2
8003104: 2b00 cmp r3, #0
8003106: d13a bne.n 800317e <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8003108: 2301 movs r3, #1
800310a: e0b2 b.n 8003272 <HAL_RCC_ClockConfig+0x2de>
800310c: 2302 movs r3, #2
800310e: 633b str r3, [r7, #48] @ 0x30
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003110: 6b3b ldr r3, [r7, #48] @ 0x30
8003112: fa93 f3a3 rbit r3, r3
8003116: 62fb str r3, [r7, #44] @ 0x2c
return result;
8003118: 6afb ldr r3, [r7, #44] @ 0x2c
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800311a: fab3 f383 clz r3, r3
800311e: b2db uxtb r3, r3
8003120: 095b lsrs r3, r3, #5
8003122: b2db uxtb r3, r3
8003124: f043 0301 orr.w r3, r3, #1
8003128: b2db uxtb r3, r3
800312a: 2b01 cmp r3, #1
800312c: d102 bne.n 8003134 <HAL_RCC_ClockConfig+0x1a0>
800312e: 4b31 ldr r3, [pc, #196] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
8003130: 681b ldr r3, [r3, #0]
8003132: e00d b.n 8003150 <HAL_RCC_ClockConfig+0x1bc>
8003134: 2302 movs r3, #2
8003136: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003138: 6abb ldr r3, [r7, #40] @ 0x28
800313a: fa93 f3a3 rbit r3, r3
800313e: 627b str r3, [r7, #36] @ 0x24
8003140: 2302 movs r3, #2
8003142: 623b str r3, [r7, #32]
8003144: 6a3b ldr r3, [r7, #32]
8003146: fa93 f3a3 rbit r3, r3
800314a: 61fb str r3, [r7, #28]
800314c: 4b29 ldr r3, [pc, #164] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
800314e: 6a5b ldr r3, [r3, #36] @ 0x24
8003150: 2202 movs r2, #2
8003152: 61ba str r2, [r7, #24]
8003154: 69ba ldr r2, [r7, #24]
8003156: fa92 f2a2 rbit r2, r2
800315a: 617a str r2, [r7, #20]
return result;
800315c: 697a ldr r2, [r7, #20]
800315e: fab2 f282 clz r2, r2
8003162: b2d2 uxtb r2, r2
8003164: f042 0220 orr.w r2, r2, #32
8003168: b2d2 uxtb r2, r2
800316a: f002 021f and.w r2, r2, #31
800316e: 2101 movs r1, #1
8003170: fa01 f202 lsl.w r2, r1, r2
8003174: 4013 ands r3, r2
8003176: 2b00 cmp r3, #0
8003178: d101 bne.n 800317e <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
800317a: 2301 movs r3, #1
800317c: e079 b.n 8003272 <HAL_RCC_ClockConfig+0x2de>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800317e: 4b1d ldr r3, [pc, #116] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
8003180: 685b ldr r3, [r3, #4]
8003182: f023 0203 bic.w r2, r3, #3
8003186: 687b ldr r3, [r7, #4]
8003188: 685b ldr r3, [r3, #4]
800318a: 491a ldr r1, [pc, #104] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
800318c: 4313 orrs r3, r2
800318e: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003190: f7fd fd36 bl 8000c00 <HAL_GetTick>
8003194: 6778 str r0, [r7, #116] @ 0x74
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003196: e00a b.n 80031ae <HAL_RCC_ClockConfig+0x21a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003198: f7fd fd32 bl 8000c00 <HAL_GetTick>
800319c: 4602 mov r2, r0
800319e: 6f7b ldr r3, [r7, #116] @ 0x74
80031a0: 1ad3 subs r3, r2, r3
80031a2: f241 3288 movw r2, #5000 @ 0x1388
80031a6: 4293 cmp r3, r2
80031a8: d901 bls.n 80031ae <HAL_RCC_ClockConfig+0x21a>
{
return HAL_TIMEOUT;
80031aa: 2303 movs r3, #3
80031ac: e061 b.n 8003272 <HAL_RCC_ClockConfig+0x2de>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80031ae: 4b11 ldr r3, [pc, #68] @ (80031f4 <HAL_RCC_ClockConfig+0x260>)
80031b0: 685b ldr r3, [r3, #4]
80031b2: f003 020c and.w r2, r3, #12
80031b6: 687b ldr r3, [r7, #4]
80031b8: 685b ldr r3, [r3, #4]
80031ba: 009b lsls r3, r3, #2
80031bc: 429a cmp r2, r3
80031be: d1eb bne.n 8003198 <HAL_RCC_ClockConfig+0x204>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80031c0: 4b0b ldr r3, [pc, #44] @ (80031f0 <HAL_RCC_ClockConfig+0x25c>)
80031c2: 681b ldr r3, [r3, #0]
80031c4: f003 0307 and.w r3, r3, #7
80031c8: 683a ldr r2, [r7, #0]
80031ca: 429a cmp r2, r3
80031cc: d214 bcs.n 80031f8 <HAL_RCC_ClockConfig+0x264>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80031ce: 4b08 ldr r3, [pc, #32] @ (80031f0 <HAL_RCC_ClockConfig+0x25c>)
80031d0: 681b ldr r3, [r3, #0]
80031d2: f023 0207 bic.w r2, r3, #7
80031d6: 4906 ldr r1, [pc, #24] @ (80031f0 <HAL_RCC_ClockConfig+0x25c>)
80031d8: 683b ldr r3, [r7, #0]
80031da: 4313 orrs r3, r2
80031dc: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80031de: 4b04 ldr r3, [pc, #16] @ (80031f0 <HAL_RCC_ClockConfig+0x25c>)
80031e0: 681b ldr r3, [r3, #0]
80031e2: f003 0307 and.w r3, r3, #7
80031e6: 683a ldr r2, [r7, #0]
80031e8: 429a cmp r2, r3
80031ea: d005 beq.n 80031f8 <HAL_RCC_ClockConfig+0x264>
{
return HAL_ERROR;
80031ec: 2301 movs r3, #1
80031ee: e040 b.n 8003272 <HAL_RCC_ClockConfig+0x2de>
80031f0: 40022000 .word 0x40022000
80031f4: 40021000 .word 0x40021000
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80031f8: 687b ldr r3, [r7, #4]
80031fa: 681b ldr r3, [r3, #0]
80031fc: f003 0304 and.w r3, r3, #4
8003200: 2b00 cmp r3, #0
8003202: d008 beq.n 8003216 <HAL_RCC_ClockConfig+0x282>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8003204: 4b1d ldr r3, [pc, #116] @ (800327c <HAL_RCC_ClockConfig+0x2e8>)
8003206: 685b ldr r3, [r3, #4]
8003208: f423 62e0 bic.w r2, r3, #1792 @ 0x700
800320c: 687b ldr r3, [r7, #4]
800320e: 68db ldr r3, [r3, #12]
8003210: 491a ldr r1, [pc, #104] @ (800327c <HAL_RCC_ClockConfig+0x2e8>)
8003212: 4313 orrs r3, r2
8003214: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8003216: 687b ldr r3, [r7, #4]
8003218: 681b ldr r3, [r3, #0]
800321a: f003 0308 and.w r3, r3, #8
800321e: 2b00 cmp r3, #0
8003220: d009 beq.n 8003236 <HAL_RCC_ClockConfig+0x2a2>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8003222: 4b16 ldr r3, [pc, #88] @ (800327c <HAL_RCC_ClockConfig+0x2e8>)
8003224: 685b ldr r3, [r3, #4]
8003226: f423 5260 bic.w r2, r3, #14336 @ 0x3800
800322a: 687b ldr r3, [r7, #4]
800322c: 691b ldr r3, [r3, #16]
800322e: 00db lsls r3, r3, #3
8003230: 4912 ldr r1, [pc, #72] @ (800327c <HAL_RCC_ClockConfig+0x2e8>)
8003232: 4313 orrs r3, r2
8003234: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8003236: f000 f829 bl 800328c <HAL_RCC_GetSysClockFreq>
800323a: 4601 mov r1, r0
800323c: 4b0f ldr r3, [pc, #60] @ (800327c <HAL_RCC_ClockConfig+0x2e8>)
800323e: 685b ldr r3, [r3, #4]
8003240: f003 03f0 and.w r3, r3, #240 @ 0xf0
8003244: 22f0 movs r2, #240 @ 0xf0
8003246: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003248: 693a ldr r2, [r7, #16]
800324a: fa92 f2a2 rbit r2, r2
800324e: 60fa str r2, [r7, #12]
return result;
8003250: 68fa ldr r2, [r7, #12]
8003252: fab2 f282 clz r2, r2
8003256: b2d2 uxtb r2, r2
8003258: 40d3 lsrs r3, r2
800325a: 4a09 ldr r2, [pc, #36] @ (8003280 <HAL_RCC_ClockConfig+0x2ec>)
800325c: 5cd3 ldrb r3, [r2, r3]
800325e: fa21 f303 lsr.w r3, r1, r3
8003262: 4a08 ldr r2, [pc, #32] @ (8003284 <HAL_RCC_ClockConfig+0x2f0>)
8003264: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (uwTickPrio);
8003266: 4b08 ldr r3, [pc, #32] @ (8003288 <HAL_RCC_ClockConfig+0x2f4>)
8003268: 681b ldr r3, [r3, #0]
800326a: 4618 mov r0, r3
800326c: f7fd fc84 bl 8000b78 <HAL_InitTick>
return HAL_OK;
8003270: 2300 movs r3, #0
}
8003272: 4618 mov r0, r3
8003274: 3778 adds r7, #120 @ 0x78
8003276: 46bd mov sp, r7
8003278: bd80 pop {r7, pc}
800327a: bf00 nop
800327c: 40021000 .word 0x40021000
8003280: 080033a8 .word 0x080033a8
8003284: 20000000 .word 0x20000000
8003288: 20000004 .word 0x20000004
0800328c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800328c: b480 push {r7}
800328e: b087 sub sp, #28
8003290: af00 add r7, sp, #0
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8003292: 2300 movs r3, #0
8003294: 60fb str r3, [r7, #12]
8003296: 2300 movs r3, #0
8003298: 60bb str r3, [r7, #8]
800329a: 2300 movs r3, #0
800329c: 617b str r3, [r7, #20]
800329e: 2300 movs r3, #0
80032a0: 607b str r3, [r7, #4]
uint32_t sysclockfreq = 0U;
80032a2: 2300 movs r3, #0
80032a4: 613b str r3, [r7, #16]
tmpreg = RCC->CFGR;
80032a6: 4b1e ldr r3, [pc, #120] @ (8003320 <HAL_RCC_GetSysClockFreq+0x94>)
80032a8: 685b ldr r3, [r3, #4]
80032aa: 60fb str r3, [r7, #12]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80032ac: 68fb ldr r3, [r7, #12]
80032ae: f003 030c and.w r3, r3, #12
80032b2: 2b04 cmp r3, #4
80032b4: d002 beq.n 80032bc <HAL_RCC_GetSysClockFreq+0x30>
80032b6: 2b08 cmp r3, #8
80032b8: d003 beq.n 80032c2 <HAL_RCC_GetSysClockFreq+0x36>
80032ba: e026 b.n 800330a <HAL_RCC_GetSysClockFreq+0x7e>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80032bc: 4b19 ldr r3, [pc, #100] @ (8003324 <HAL_RCC_GetSysClockFreq+0x98>)
80032be: 613b str r3, [r7, #16]
break;
80032c0: e026 b.n 8003310 <HAL_RCC_GetSysClockFreq+0x84>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
80032c2: 68fb ldr r3, [r7, #12]
80032c4: 0c9b lsrs r3, r3, #18
80032c6: f003 030f and.w r3, r3, #15
80032ca: 4a17 ldr r2, [pc, #92] @ (8003328 <HAL_RCC_GetSysClockFreq+0x9c>)
80032cc: 5cd3 ldrb r3, [r2, r3]
80032ce: 607b str r3, [r7, #4]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_Pos];
80032d0: 4b13 ldr r3, [pc, #76] @ (8003320 <HAL_RCC_GetSysClockFreq+0x94>)
80032d2: 6adb ldr r3, [r3, #44] @ 0x2c
80032d4: f003 030f and.w r3, r3, #15
80032d8: 4a14 ldr r2, [pc, #80] @ (800332c <HAL_RCC_GetSysClockFreq+0xa0>)
80032da: 5cd3 ldrb r3, [r2, r3]
80032dc: 60bb str r3, [r7, #8]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
80032de: 68fb ldr r3, [r7, #12]
80032e0: f403 3380 and.w r3, r3, #65536 @ 0x10000
80032e4: 2b00 cmp r3, #0
80032e6: d008 beq.n 80032fa <HAL_RCC_GetSysClockFreq+0x6e>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
80032e8: 4a0e ldr r2, [pc, #56] @ (8003324 <HAL_RCC_GetSysClockFreq+0x98>)
80032ea: 68bb ldr r3, [r7, #8]
80032ec: fbb2 f2f3 udiv r2, r2, r3
80032f0: 687b ldr r3, [r7, #4]
80032f2: fb02 f303 mul.w r3, r2, r3
80032f6: 617b str r3, [r7, #20]
80032f8: e004 b.n 8003304 <HAL_RCC_GetSysClockFreq+0x78>
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
80032fa: 687b ldr r3, [r7, #4]
80032fc: 4a0c ldr r2, [pc, #48] @ (8003330 <HAL_RCC_GetSysClockFreq+0xa4>)
80032fe: fb02 f303 mul.w r3, r2, r3
8003302: 617b str r3, [r7, #20]
{
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
}
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
sysclockfreq = pllclk;
8003304: 697b ldr r3, [r7, #20]
8003306: 613b str r3, [r7, #16]
break;
8003308: e002 b.n 8003310 <HAL_RCC_GetSysClockFreq+0x84>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
800330a: 4b0a ldr r3, [pc, #40] @ (8003334 <HAL_RCC_GetSysClockFreq+0xa8>)
800330c: 613b str r3, [r7, #16]
break;
800330e: bf00 nop
}
}
return sysclockfreq;
8003310: 693b ldr r3, [r7, #16]
}
8003312: 4618 mov r0, r3
8003314: 371c adds r7, #28
8003316: 46bd mov sp, r7
8003318: f85d 7b04 ldr.w r7, [sp], #4
800331c: 4770 bx lr
800331e: bf00 nop
8003320: 40021000 .word 0x40021000
8003324: 00f42400 .word 0x00f42400
8003328: 080033b8 .word 0x080033b8
800332c: 080033c8 .word 0x080033c8
8003330: 003d0900 .word 0x003d0900
8003334: 007a1200 .word 0x007a1200
08003338 <memset>:
8003338: 4402 add r2, r0
800333a: 4603 mov r3, r0
800333c: 4293 cmp r3, r2
800333e: d100 bne.n 8003342 <memset+0xa>
8003340: 4770 bx lr
8003342: f803 1b01 strb.w r1, [r3], #1
8003346: e7f9 b.n 800333c <memset+0x4>
08003348 <__libc_init_array>:
8003348: b570 push {r4, r5, r6, lr}
800334a: 4d0d ldr r5, [pc, #52] @ (8003380 <__libc_init_array+0x38>)
800334c: 4c0d ldr r4, [pc, #52] @ (8003384 <__libc_init_array+0x3c>)
800334e: 1b64 subs r4, r4, r5
8003350: 10a4 asrs r4, r4, #2
8003352: 2600 movs r6, #0
8003354: 42a6 cmp r6, r4
8003356: d109 bne.n 800336c <__libc_init_array+0x24>
8003358: 4d0b ldr r5, [pc, #44] @ (8003388 <__libc_init_array+0x40>)
800335a: 4c0c ldr r4, [pc, #48] @ (800338c <__libc_init_array+0x44>)
800335c: f000 f818 bl 8003390 <_init>
8003360: 1b64 subs r4, r4, r5
8003362: 10a4 asrs r4, r4, #2
8003364: 2600 movs r6, #0
8003366: 42a6 cmp r6, r4
8003368: d105 bne.n 8003376 <__libc_init_array+0x2e>
800336a: bd70 pop {r4, r5, r6, pc}
800336c: f855 3b04 ldr.w r3, [r5], #4
8003370: 4798 blx r3
8003372: 3601 adds r6, #1
8003374: e7ee b.n 8003354 <__libc_init_array+0xc>
8003376: f855 3b04 ldr.w r3, [r5], #4
800337a: 4798 blx r3
800337c: 3601 adds r6, #1
800337e: e7f2 b.n 8003366 <__libc_init_array+0x1e>
8003380: 080033d8 .word 0x080033d8
8003384: 080033d8 .word 0x080033d8
8003388: 080033d8 .word 0x080033d8
800338c: 080033dc .word 0x080033dc
08003390 <_init>:
8003390: b5f8 push {r3, r4, r5, r6, r7, lr}
8003392: bf00 nop
8003394: bcf8 pop {r3, r4, r5, r6, r7}
8003396: bc08 pop {r3}
8003398: 469e mov lr, r3
800339a: 4770 bx lr
0800339c <_fini>:
800339c: b5f8 push {r3, r4, r5, r6, r7, lr}
800339e: bf00 nop
80033a0: bcf8 pop {r3, r4, r5, r6, r7}
80033a2: bc08 pop {r3}
80033a4: 469e mov lr, r3
80033a6: 4770 bx lr
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