27 Commits

Author SHA1 Message Date
ac78903414 zwischenspeicher 2025-05-29 01:28:02 +02:00
87d4f2b010 remove schematic error 2025-05-29 01:24:56 +02:00
65e6d8b36a remove error 2025-05-29 01:22:48 +02:00
46319c1f8e finish routing, start cleanup 2025-05-28 22:11:37 +02:00
d5fa999bff routing most other stuff 2025-05-28 18:02:08 +02:00
6e2335c7d3 route LVDS and display 2025-05-27 20:53:35 +02:00
c4ca43e0fe routing routing 2025-05-27 03:30:40 +02:00
3991340fbf RMII routing 2025-05-27 02:32:30 +02:00
31fe506927 ram routing 2025-05-26 23:41:58 +02:00
de7dec9d2e layout test 1 2025-05-24 17:55:57 +02:00
41ac030639 layout layout layout layout layout 2025-05-24 00:54:29 +02:00
95278ec8b6 layout change 2025-05-22 03:08:53 +02:00
224cdfe086 layout layout ~~ 2025-05-21 21:49:15 +02:00
85dd3c4fe8 add 12V compatibility 2025-05-21 17:32:34 +02:00
9dd8e6b138 add changes from PCB review 2025-02-21 20:46:14 +01:00
10fe1712b0 Bauteil Positionierung 2025-02-19 19:52:36 +01:00
f3088f4504 finishing schematic, starting to try layout position 2025-02-16 21:23:55 +01:00
6c67a2a88b add more function and board clean-up 2025-02-12 02:29:59 +01:00
a069658e62 added footprints & 3d models 2025-02-05 18:49:26 +01:00
6394f0667c change structure again (added peripheral sheet) 2025-02-05 04:24:50 +01:00
229155a679 display circuit 2025-02-04 23:33:58 +01:00
cd48af6ae8 structure change 2025-02-04 04:13:07 +01:00
991c6a0b0c finalise Ethernet circuit 2025-02-04 02:20:19 +01:00
b970b6e2e0 add SDC and SCS 2025-02-02 03:05:34 +01:00
79e716c988 add ethernet circuit 2025-02-01 23:29:17 +01:00
b28d41c90c add ioc file 2024-12-10 17:54:42 +01:00
426d20fb02 check branch 2024-12-06 18:24:53 +01:00