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add ioc file

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This commit is contained in:
Johnny Hsu 2024-12-10 17:54:42 +01:00
parent 426d20fb02
commit b28d41c90c
1479 changed files with 1124189 additions and 5574 deletions
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198
Hardware/FT25-Charger.kicad_pro
View File

@ -2,12 +2,204 @@
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {},
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.1,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {},
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"via_dimensions": []
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"ipc2581": {
"dist": "",

229
Software/.cproject
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@ -1,229 +0,0 @@
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25
Software/.mxproject
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File diff suppressed because one or more lines are too long

33
Software/.project
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@ -1,33 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>FT23_Charger</name>
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43
Software/Core/Inc/b_cccv_algo.h
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@ -1,43 +0,0 @@
/*
* b_cccv_algo.h
*
* Created on: 16.06.2023
* Author: max
*/
#include <stdint.h>
#include "stm32h7xx_hal.h"
#ifndef INC_B_CCCV_ALGO_H_
#define INC_B_CCCV_ALGO_H_
#define I_GAIN 4
#define P_GAIN 10
#define CHARGE_CURRENT_LIMIT 10.0
#define SIMULINKTEST
#undef SIMULINKTEST
typedef enum{
NO_CHARGING,
CHARGING_IN_PROGRESS,
CHARGING_COMPLETED
} CCCV_CONTROL_STATE;
#ifdef SIMULINKTEST
CCCV_CONTROL_STATE cccvloop(float maxcellvoltage, float voltagesetpoint, float maxcurrent, float*ccurrent);
#else
CCCV_CONTROL_STATE cccvloop(float maxcellvoltage, float voltagesetpoint, float maxcurrent);
void setchargecurrent(float chargecurrent);
void setchargevoltage(uint8_t numberofcells,float maximumcellvoltage);
float getMaximumCellVoltage();
void chargingloop(float maximumcellvoltage);
void startcharging(float endvoltage);
void initChargerAlgo(uint8_t numberofcells, float maximumcellvoltage);
void setchargevoltage(uint8_t numberofcells,float maximumcellvoltage);
void stopcharging();
#endif
float matlabvalidationwrapper(float maxcellvoltage, float voltagesetpoint, float maxcurrent);
#endif /* INC_B_CCCV_ALGO_H_ */

62
Software/Core/Inc/can-halal.h
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@ -1,62 +0,0 @@
#ifndef CAN_HALAL_H
#define CAN_HALAL_H
// Define family macros if none are defined and we recognize a chip macro
#if !defined(STM32F3) && !defined(STM32H7)
#if defined(STM32F302x6) || defined(STM32F302x8) || defined(STM32F302xB) || \
defined(STM32F302xC)
#define STM32F3
#endif
#if defined(STM32H7A3xx)
#define STM32H7
#endif
#endif
#if defined(STM32F3)
#include "stm32f3xx_hal.h"
#define FTCAN_IS_BXCAN
#define FTCAN_NUM_FILTERS 13
#elif defined(STM32H7)
#include "stm32h7xx_hal.h"
#define FTCAN_IS_FDCAN
#define FTCAN_NUM_FILTERS 13
#else
#error "Couldn't detect STM family"
#endif
#if defined(FTCAN_IS_BXCAN)
HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle);
#elif defined(FTCAN_IS_FDCAN)
HAL_StatusTypeDef ftcan_init(FDCAN_HandleTypeDef *handle);
#else
#error "Unknown CAN peripheral"
#endif
HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data,
size_t datalen);
HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask);
/**
* Define this function to be notified of incoming CAN messages
*/
void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t *data);
/**
* Read num_bytes bytes from a message (unmarshalled network byte order). The
* msg pointer is advanced by the corresponding number of bytes.
*
* Both methods return a 64-bit integer, but you can safely cast it to a smaller
* integer type.
*/
uint64_t ftcan_unmarshal_unsigned(const uint8_t **data, size_t num_bytes);
int64_t ftcan_unmarshal_signed(const uint8_t **data, size_t num_bytes);
/**
* Write num_bytes to a message (marshalled in network byte order). The pointer
* is advanced by the corresponding number of bytes and returned.
*/
uint8_t *ftcan_marshal_unsigned(uint8_t *data, uint64_t val, size_t num_bytes);
uint8_t *ftcan_marshal_signed(uint8_t *data, int64_t val, size_t num_bytes);
#endif // CAN_HALAL_H

22
Software/Core/Inc/can.h
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@ -1,22 +0,0 @@
/*
* can.h
*
* Created on: 21.06.2023
* Author: max
*/
#ifndef INC_CAN_H_
#define INC_CAN_H_
#include "stm32h7xx_hal.h"
#define CAN_ID_AMS_STATUS 0x00A
#define CAN_ID_AMS_IN 0x00B
#define CAN_ID_SLAVE_STATUS_BASE 0x080
#define CAN_ID_CHARGER_ACTIVE 0x200
void initCan(FDCAN_HandleTypeDef *hcan);
#endif /* INC_CAN_H_ */

17
Software/Core/Inc/charge_ctrl_test_shell.h
View File

@ -1,17 +0,0 @@
/*
* charge_ctrl_test_shell.h
*
* Created on: May 21, 2023
* Author: max
*/
#ifndef INC_CHARGE_CTRL_TEST_SHELL_H_
#define INC_CHARGE_CTRL_TEST_SHELL_H_
#include "stm32h7xx_hal.h"
void charge_shell_init(UART_HandleTypeDef *huart);
void charge_shell_loop();
#endif /* INC_CHARGE_CTRL_TEST_SHELL_H_ */

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Software/Core/Inc/charger_control.h
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/*
* charger_control.h
*
* Created on: May 21, 2023
* Author: MaxMax
*/
#ifndef INC_CHARGER_CONTROL_H_
#define INC_CHARGER_CONTROL_H_
#include "stm32h7xx_hal.h"
#define CURRENT_DAC_ADR 0x58
#define VOLTAGE_DAC_ADR 0x5E
#define CHARGER_ADC_ADR 0x90
typedef struct{
uint8_t acfail;
uint8_t dcfail;
uint8_t cc_status;
uint8_t ot_status;
uint8_t lim_status;
uint16_t voltage;
uint16_t current;
}ChargerStatusHandleTypeDef;
void charger_control_init(I2C_HandleTypeDef* hi2c);
ChargerStatusHandleTypeDef charger_control_get_state();
void charger_control_set_current(uint32_t current);
void charger_control_set_voltage(uint32_t voltage);
void charger_control_enable_charger_relay();
void charger_control_disable_charger_relay();
void charger_control_enable_remote();
void charger_control_disable_remote();
void charger_control_setup_DACs();
#endif /* INC_CHARGER_CONTROL_H_ */

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Software/Core/Inc/slave_handler.h
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/*
* slave_handler.h
*
* Created on: Jun 21, 2023
* Author: max
*/
#ifndef INC_SLAVE_HANDLER_H_
#define INC_SLAVE_HANDLER_H_
#include "stm32h7xx_hal.h"
#define N_SLAVES 6
typedef enum {
SLAVE_ERR_NONE,
SLAVE_ERR_TIMEOUT,
SLAVE_ERR_OT,
SLAVE_ERR_UT,
SLAVE_ERR_OV,
SLAVE_ERR_UV,
SLAVE_ERR_UNKNOWN,
} SlaveErrorKind;
typedef struct {
SlaveErrorKind kind;
uint32_t data; // Cell/temperature ID etc
} SlaveError;
typedef struct {
uint8_t id;
SlaveError error;
uint8_t soc;
uint16_t min_voltage;
uint16_t max_voltage;
int16_t max_temp;
uint32_t last_message;
} SlaveHandle;
extern SlaveHandle slaves[N_SLAVES];
float slaves_get_maximum_voltage();
void slaves_handle_status(const uint8_t *data);
void slave_handler_init();
#endif /* INC_SLAVE_HANDLER_H_ */

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Software/Core/Src/b_cccv_algo.c
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/*
* b_cccv_algo.c
*
* Created on: 16.06.2023
* Author: max
*/
#include "b_cccv_algo.h"
#include "charger_control.h"
#include "main.h"
static uint32_t dt;
static uint32_t lasttick;
static float errorintegration = 0;
static float finalvoltage = 4.15;
static float chargevoltage = 430;
static float chargecurrentlimit = CHARGE_CURRENT_LIMIT;
static float resistancelut[1024];
static float voltageresistancelut[1024];
#define CURRENT_R 2.2
#define VOLTAGE_R 18
CCCV_CONTROL_STATE chargerstate = NO_CHARGING;
#ifdef SIMULINKTEST
CCCV_CONTROL_STATE cccvloop(float maxcellvoltage, float voltagesetpoint, float maxcurrent, float*ccurrent)
#else
CCCV_CONTROL_STATE cccvloop(float maxcellvoltage, float voltagesetpoint, float maxcurrent)
#endif
{
#ifdef SIMULINKTEST
dt = 1000;
#else
dt = HAL_GetTick() - lasttick;
lasttick = HAL_GetTick();
#endif
float chargecurrent = 0;
//Calculate Voltage Error and I and P Factors
float voltageerror = voltagesetpoint-maxcellvoltage;
float errorproportional = P_GAIN * voltageerror;
errorintegration += I_GAIN*voltageerror * ((float)dt)/1000;
//Limit I and P Factors to maximum charge current
if(errorintegration > maxcurrent)
errorintegration = maxcurrent;
if(errorproportional > maxcurrent)
errorproportional = maxcurrent;
if(errorproportional <= -maxcurrent)
errorproportional = -maxcurrent;
if(errorintegration <= -maxcurrent)
errorintegration = -maxcurrent;
float errorintegrationout = errorintegration;
chargecurrent = (errorproportional + errorintegrationout);
if(chargecurrent > maxcurrent)
chargecurrent = maxcurrent;
if(chargecurrent <= 0)
chargecurrent = 0;
if(chargecurrent < 0.01) //If Charge Current ist below minimum threshold, stop charging
return CHARGING_COMPLETED;
#ifdef SIMULINKTEST
*ccurrent = chargecurrent;
#else
setchargevoltage(103,finalvoltage+0.05);
setchargecurrent(chargecurrent);
#endif
return CHARGING_IN_PROGRESS;
}
#ifndef SIMULINKTEST
void initChargerAlgo(uint8_t numberofcells, float maximumcellvoltage)
{
chargerstate = NO_CHARGING;
chargevoltage = numberofcells * maximumcellvoltage;
for(uint32_t i = 0; i < 1024; i++)
{
resistancelut[i] = 10*CURRENT_R/(CURRENT_R+(20*((float)i)/1024));
}
for(uint32_t i = 0; i < 1024; i++)
{
voltageresistancelut[i] = (600*VOLTAGE_R)/(VOLTAGE_R+(20*((float)i)/1024));
}
}
void setchargecurrent(float chargecurrent)
{
float targetresistance;
if(chargecurrent != 0)
{
for(uint32_t setpoint = 0; setpoint < 1024; setpoint++)
{
if(resistancelut[setpoint] <= chargecurrent)
{
targetresistance = (20000*((float)setpoint)/1024);
break;
}
}
}
else
{
targetresistance = 20000;
}
float wiperpos = targetresistance/20000 * (1023);
charger_control_set_current((uint32_t) wiperpos);
}
void setchargevoltage(uint8_t numberofcells,float maximumcellvoltage)
{
float chargevoltage = numberofcells * maximumcellvoltage;
float targetresistance;
if(chargevoltage != 0)
{
for(uint32_t setpoint = 0; setpoint < 1024; setpoint++)
{
if(voltageresistancelut[setpoint] <= chargevoltage)
{
targetresistance = (20000*((float)setpoint)/1024);
break;
}
}
}
else
{
targetresistance = 20000;
}
float wiperpos = targetresistance/20000 * (1023);
charger_control_set_voltage((uint32_t) wiperpos);
//@TODO Call Function to set Resistance for Voltage
}
void chargingloop(float maximumcellvoltage)
{
switch(chargerstate)
{
case NO_CHARGING: //Do Nothing IDLE Loop
chargerstate = NO_CHARGING;
charger_control_disable_remote();
errorintegration = 0;
break;
case CHARGING_IN_PROGRESS: //Run charging algo periodically
charger_control_enable_remote();
chargerstate = cccvloop(maximumcellvoltage, finalvoltage, chargecurrentlimit);
break;
case CHARGING_COMPLETED: //Signal Completion of Charging here
chargerstate = NO_CHARGING;
charger_control_disable_remote();
errorintegration = 0;
break;
}
}
void startcharging(float endvoltage)
{
chargerstate = CHARGING_IN_PROGRESS;
finalvoltage = endvoltage;
}
void stopcharging()
{
chargerstate = NO_CHARGING;
charger_control_disable_remote();
}
#endif
#ifdef SIMULINKTEST
float matlabvalidationwrapper(float maxcellvoltage, float voltagesetpoint, float maxcurrent)
{
float chargecurrent = 0;
(void*) cccvloop(maxcellvoltage,voltagesetpoint,maxcurrent, &chargecurrent);
return chargecurrent;
}
#endif

273
Software/Core/Src/can-halal.c
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#include "can-halal.h"
#include <string.h>
#if defined(FTCAN_IS_BXCAN)
static CAN_HandleTypeDef *hcan;
HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) {
hcan = handle;
HAL_StatusTypeDef status =
HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING);
if (status != HAL_OK) {
return status;
}
return HAL_CAN_Start(hcan);
}
HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data,
size_t datalen) {
static CAN_TxHeaderTypeDef header;
header.StdId = id;
header.IDE = CAN_ID_STD;
header.RTR = CAN_RTR_DATA;
header.DLC = datalen;
uint32_t mailbox;
return HAL_CAN_AddTxMessage(hcan, &header, data, &mailbox);
}
HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) {
static uint32_t next_filter_no = 0;
static CAN_FilterTypeDef filter;
if (next_filter_no % 2 == 0) {
filter.FilterIdHigh = id << 5;
filter.FilterMaskIdHigh = mask << 5;
filter.FilterIdLow = id << 5;
filter.FilterMaskIdLow = mask << 5;
} else {
// Leave high filter untouched from the last configuration
filter.FilterIdLow = id << 5;
filter.FilterMaskIdLow = mask << 5;
}
filter.FilterFIFOAssignment = CAN_FILTER_FIFO0;
filter.FilterBank = next_filter_no / 2;
if (filter.FilterBank > FTCAN_NUM_FILTERS + 1) {
return HAL_ERROR;
}
filter.FilterMode = CAN_FILTERMODE_IDMASK;
filter.FilterScale = CAN_FILTERSCALE_16BIT;
filter.FilterActivation = CAN_FILTER_ENABLE;
// Disable slave filters
// TODO: Some STM32 have multiple CAN peripherals, and one uses the slave
// filter bank
filter.SlaveStartFilterBank = FTCAN_NUM_FILTERS;
HAL_StatusTypeDef status = HAL_CAN_ConfigFilter(hcan, &filter);
if (status == HAL_OK) {
next_filter_no++;
}
return status;
}
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) {
if (handle != hcan) {
return;
}
CAN_RxHeaderTypeDef header;
uint8_t data[8];
if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) {
return;
}
if (header.IDE != CAN_ID_STD) {
return;
}
ftcan_msg_received_cb(header.StdId, header.DLC, data);
}
#elif defined(FTCAN_IS_FDCAN)
static FDCAN_HandleTypeDef *hcan;
HAL_StatusTypeDef ftcan_init(FDCAN_HandleTypeDef *handle) {
hcan = handle;
HAL_StatusTypeDef status =
HAL_FDCAN_ActivateNotification(hcan, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0);
if (status != HAL_OK) {
return status;
}
// Reject non-matching messages
status =
HAL_FDCAN_ConfigGlobalFilter(hcan, FDCAN_REJECT, FDCAN_REJECT,
FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
if (status != HAL_OK) {
return status;
}
return HAL_FDCAN_Start(hcan);
}
HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data,
size_t datalen) {
static FDCAN_TxHeaderTypeDef header;
header.Identifier = id;
header.IdType = FDCAN_STANDARD_ID;
header.TxFrameType = FDCAN_DATA_FRAME;
switch (datalen) {
case 0:
header.DataLength = FDCAN_DLC_BYTES_0;
break;
case 1:
header.DataLength = FDCAN_DLC_BYTES_1;
break;
case 2:
header.DataLength = FDCAN_DLC_BYTES_2;
break;
case 3:
header.DataLength = FDCAN_DLC_BYTES_3;
break;
case 4:
header.DataLength = FDCAN_DLC_BYTES_4;
break;
case 5:
header.DataLength = FDCAN_DLC_BYTES_5;
break;
case 6:
header.DataLength = FDCAN_DLC_BYTES_6;
break;
case 7:
header.DataLength = FDCAN_DLC_BYTES_7;
break;
case 8:
default:
header.DataLength = FDCAN_DLC_BYTES_8;
break;
}
header.ErrorStateIndicator = FDCAN_ESI_PASSIVE;
header.BitRateSwitch = FDCAN_BRS_OFF;
header.FDFormat = FDCAN_CLASSIC_CAN;
header.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
// HAL_FDCAN_AddMessageToTxFifoQ doesn't modify the data, but it's not marked
// as const for some reason.
uint8_t *data_nonconst = (uint8_t *)data;
return HAL_FDCAN_AddMessageToTxFifoQ(hcan, &header, data_nonconst);
}
HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) {
static uint32_t next_filter_no = 0;
static FDCAN_FilterTypeDef filter;
filter.IdType = FDCAN_STANDARD_ID;
filter.FilterIndex = next_filter_no;
if (filter.FilterIndex > FTCAN_NUM_FILTERS + 1) {
return HAL_ERROR;
}
filter.FilterType = FDCAN_FILTER_MASK;
filter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
filter.FilterID1 = id;
filter.FilterID2 = mask;
HAL_StatusTypeDef status = HAL_FDCAN_ConfigFilter(hcan, &filter);
if (status == HAL_OK) {
next_filter_no++;
}
return status;
}
void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *handle,
uint32_t RxFifo0ITs) {
if (handle != hcan || (RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) == RESET) {
return;
}
static FDCAN_RxHeaderTypeDef header;
static uint8_t data[8];
if (HAL_FDCAN_GetRxMessage(hcan, FDCAN_RX_FIFO0, &header, data) != HAL_OK) {
return;
}
if (header.FDFormat != FDCAN_CLASSIC_CAN ||
header.RxFrameType != FDCAN_DATA_FRAME ||
header.IdType != FDCAN_STANDARD_ID) {
return;
}
size_t datalen;
switch (header.DataLength) {
case FDCAN_DLC_BYTES_0:
datalen = 0;
break;
case FDCAN_DLC_BYTES_1:
datalen = 1;
break;
case FDCAN_DLC_BYTES_2:
datalen = 2;
break;
case FDCAN_DLC_BYTES_3:
datalen = 3;
break;
case FDCAN_DLC_BYTES_4:
datalen = 4;
break;
case FDCAN_DLC_BYTES_5:
datalen = 5;
break;
case FDCAN_DLC_BYTES_6:
datalen = 6;
break;
case FDCAN_DLC_BYTES_7:
datalen = 7;
break;
case FDCAN_DLC_BYTES_8:
datalen = 8;
break;
default:
return;
}
ftcan_msg_received_cb(header.Identifier, datalen, data);
}
#endif
__weak void ftcan_msg_received_cb(uint16_t id, size_t datalen,
const uint8_t *data) {}
uint64_t ftcan_unmarshal_unsigned(const uint8_t **data_ptr, size_t num_bytes) {
if (num_bytes > 8) {
num_bytes = 8;
}
const uint8_t *data = *data_ptr;
uint64_t result = 0;
for (size_t i = 0; i < num_bytes; i++) {
result <<= 8;
result |= data[i];
}
*data_ptr += num_bytes;
return result;
}
int64_t ftcan_unmarshal_signed(const uint8_t **data_ptr, size_t num_bytes) {
if (num_bytes > 8) {
num_bytes = 8;
}
uint64_t result_unsigned = ftcan_unmarshal_unsigned(data_ptr, num_bytes);
// Sign extend by shifting left, then copying to a signed int and shifting
// back to the right
size_t diff_to_64 = 64 - num_bytes * 8;
result_unsigned <<= diff_to_64;
int64_t result;
memcpy(&result, &result_unsigned, 8);
return result >> diff_to_64;
}
uint8_t *ftcan_marshal_unsigned(uint8_t *data, uint64_t val, size_t num_bytes) {
if (num_bytes > 8) {
num_bytes = 8;
}
for (int i = num_bytes - 1; i >= 0; i--) {
data[i] = val & 0xFF;
val >>= 8;
}
return data + num_bytes;
}
uint8_t *ftcan_marshal_signed(uint8_t *data, int64_t val, size_t num_bytes) {
return ftcan_marshal_unsigned(data, val, num_bytes);
}

57
Software/Core/Src/can.c
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/*
* can.c
*
* Created on: 21.06.2023
* Author: max
*/
#include "can.h"
#include "can-halal.h"
#include "slave_handler.h"
#include "b_cccv_algo.h"
#include "charger_control.h"
void initCan(FDCAN_HandleTypeDef *hcan)
{
ftcan_init(hcan);
ftcan_add_filter(0, 0);
}
void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t *data)
{
if ((id & 0xFF0) == CAN_ID_SLAVE_STATUS_BASE) {
// slaves_handle_status(data);
return;
}
/*if (id == CAN_ID_CHARGER_ACTIVE)
{
if(data[0] == 1)
{
uint8_t* ptr = &data[1];
startcharging(((float) ftcan_unmarshal_unsigned(&ptr, 2))/10000);
}
else
{
stopcharging();
}
return;
}*/
switch (id) {
case CAN_ID_AMS_STATUS: {
int sdc_closed = data[0] >> 7;
if (sdc_closed == 0) {
charger_control_disable_remote();
}
break;
}
case CAN_ID_AMS_IN: {
int active = data[0] & 0x01;
if (active) {
charger_control_enable_remote();
}
}
}
}

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Software/Core/Src/charge_ctrl_test_shell.c
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/*
* charge_ctrl_test_shell.c
*
* Created on: May 21, 2023
* Author: max
*/
#include "charge_ctrl_test_shell.h"
#include "charger_control.h"
UART_HandleTypeDef *suart;
void charge_shell_init(UART_HandleTypeDef *huart)
{
suart = huart;
}
void charge_shell_loop()
{
uint8_t command[3];
HAL_StatusTypeDef status = HAL_UART_Receive(suart, command, 3, 100);
if(status == HAL_OK)
{
switch(command[0])
{
case 'r':
if(command[1] == 'c') //enable remote control
{
charger_control_enable_remote();
}
else if(command[1] == 'o') //disable remote control
{
charger_control_disable_remote();
}
break;
case 'e':
if(command[1] == 'c')
{
charger_control_enable_charger_relay();
}
else if(command[1] == 'o')
{
charger_control_disable_charger_relay();
}
break;
case 'v':
;uint16_t voltage = (command[1]<<8) | command[2];
charger_control_set_voltage(voltage);
break;
case 'c':
;uint16_t current = (command[1]<<8 | command[2]);
charger_control_set_current(current);
break;
case 's':
;ChargerStatusHandleTypeDef charg = charger_control_get_state();
uint8_t txbuffer[9] = {charg.acfail, charg.dcfail, charg.cc_status,
charg.lim_status, charg.ot_status, (uint8_t)(charg.current>>8),
(uint8_t)charg.current&0xFF,(uint8_t)(charg.voltage>>8),
(uint8_t)charg.voltage&0xFF
};
HAL_UART_Transmit(suart, txbuffer, 9, 1000);
}
}
}

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Software/Core/Src/charger_control.c
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/*
* charger_control.c
*
* Created on: May 21, 2023
* Author: MaxMax
*/
#include "charger_control.h"
#include "main.h"
I2C_HandleTypeDef* charger_i2c;
/*** @brief Start ADC Conversion on Charger Current Channel and returns the result
* @note The ADC has a PGA leading to an input range of +-6.144 in twos complement. With single ended measurements, the range is 15 bit and
* Voltage = 6.144/(2^(15)-1)
* @note The charger maps a voltage range of 0-5V to the output current of 0-10A
* @retval ADC Conversion register value
*/
uint16_t readADCCurrent()
{
uint8_t writeconfigreg[3] = {0x01, 0xC1, 0xE3};
uint8_t readconfigreg[1] = {0x01};
uint8_t readconversionreg[1] = {0x00};
uint8_t configreg[2];
uint8_t conversionreg[2];
HAL_I2C_Master_Transmit(charger_i2c, CHARGER_ADC_ADR, writeconfigreg, 3, 1000); //Set Config Register and Start conversion
HAL_I2C_Master_Transmit(charger_i2c, CHARGER_ADC_ADR, readconfigreg, 1, 1000); //Read Back Config Reg to check for conversion completion
HAL_I2C_Master_Receive(charger_i2c, CHARGER_ADC_ADR, configreg, 2, 1000);
HAL_Delay(1);//@TODO Remove if ADC Works
HAL_I2C_Master_Transmit(charger_i2c, CHARGER_ADC_ADR, readconversionreg, 1, 1000); //Read Result from conversion register
HAL_I2C_Master_Receive(charger_i2c, CHARGER_ADC_ADR, conversionreg, 2, 1000);
return (uint16_t)(conversionreg[0]<<8 | conversionreg[1]);
}
/*** @brief Start ADC Conversion on Charger Voltage Channel and returns the result
* @note The ADC has a PGA leading to an input range of +-6.144 in twos complement. With single ended measurements, the range is 15 bit and
* Voltage = 6.144/(2^(15)-1)
* @note The charger maps a voltage range of 0-5V to the output voltage range of 0-600V
* @retval ADC Conversion register value
*/
uint16_t readADCVoltage()
{
uint8_t writeconfigreg[3] = {0x01, 0xC1, 0xE3};
uint8_t readconfigreg[1] = {0x01};
uint8_t readconversionreg[1] = {0x00};
uint8_t configreg[2];
uint8_t conversionreg[2];
HAL_I2C_Master_Transmit(charger_i2c, CHARGER_ADC_ADR, writeconfigreg, 3, 1000); //Set Config Register and Start conversion
HAL_I2C_Master_Transmit(charger_i2c, CHARGER_ADC_ADR, readconfigreg, 1, 1000); //Read Back Config Reg to check for conversion completion
HAL_I2C_Master_Receive(charger_i2c, CHARGER_ADC_ADR, configreg, 2, 1000);
HAL_Delay(1);//@TODO Remove if ADC Works
HAL_I2C_Master_Transmit(charger_i2c, CHARGER_ADC_ADR, readconversionreg, 1, 1000); //Read Result from conversion register
HAL_I2C_Master_Receive(charger_i2c, CHARGER_ADC_ADR, conversionreg, 2, 1000);
return (uint16_t)(conversionreg[0]<<8 | conversionreg[1]);
}
/*** @brief Initilization Routine of the charger
* @note initially all outputs are set to 0, remote control and charger relay are deactivated
* @param hi2c Handler to I2C struct for ADC and DAC communication
*/
void charger_control_init(I2C_HandleTypeDef* hi2c)
{
charger_i2c = hi2c;
charger_control_disable_remote();
charger_control_disable_charger_relay();
charger_control_setup_DACs();
charger_control_set_current(0);
charger_control_set_voltage(0);
}
/*** @brief Get State of voltage, current and error flags of the charger
* @retval Struct Containing charger information
*/
ChargerStatusHandleTypeDef charger_control_get_state()
{
ChargerStatusHandleTypeDef chargerstate;
chargerstate.voltage = readADCVoltage();
chargerstate.current = readADCCurrent();
chargerstate.acfail = HAL_GPIO_ReadPin(Charger_AC_Fail_GPIO_Port, Charger_AC_Fail_Pin);
chargerstate.dcfail = HAL_GPIO_ReadPin(Charger_DC_FAIL_GPIO_Port, Charger_DC_FAIL_Pin);
chargerstate.cc_status = HAL_GPIO_ReadPin(Charger_CC_Status_GPIO_Port, Charger_CC_Status_Pin);
chargerstate.lim_status = HAL_GPIO_ReadPin(Charger_LIM_GPIO_Port, Charger_LIM_Pin);
chargerstate.ot_status = HAL_GPIO_ReadPin(Charger_OT_GPIO_Port, Charger_OT_Pin);
return chargerstate;
}
void charger_control_setup_DACs()
{
uint8_t enabledacs[2] = {0x1C, 0x02};
HAL_I2C_Master_Transmit(charger_i2c, CURRENT_DAC_ADR, enabledacs, 2, 1000);
HAL_I2C_Master_Transmit(charger_i2c, VOLTAGE_DAC_ADR, enabledacs, 2, 1000);
}
/*** @brief set current channel using the DAC
* @param current value in 10 bit => 0-5V are equal to 0-10A so 1 bit is approx 49mA
*
*/
void charger_control_set_current(uint32_t current)
{
uint8_t currentlow = current & 0xFF;
uint8_t currenthigh = ((current>>8) & 0x03) | 0x04;
uint8_t current_dac_data[2] = {currenthigh,currentlow};
HAL_I2C_Master_Transmit(charger_i2c, CURRENT_DAC_ADR, current_dac_data, 2, 1000);
}
/** @brief set voltage channel using the DAC
* @param voltage value in 10 bit => 0-5V are equal to 0-600V so 1 bit is approx. 2.93V
*
*/
void charger_control_set_voltage(uint32_t voltage)
{
uint8_t voltagelow = voltage & 0xFF;
uint8_t voltagehigh = ((voltage>>8) & 0x03) | 0x04;
uint8_t voltage_dac_data[2] = {voltagehigh,voltagelow};
HAL_I2C_Master_Transmit(charger_i2c, VOLTAGE_DAC_ADR, voltage_dac_data, 2, 1000);
}
/** @brief Closes the main charger Relay
* @note The relay is also dependend on the Shutdown Circuit
*/
void charger_control_enable_charger_relay()
{
HAL_GPIO_WritePin(Charger_Relay_GPIO_Port, Charger_Relay_Pin, GPIO_PIN_SET);
}
/** @brief opens the main charger Relay
* @note The relay is also dependend on the Shutdown Circuit
*/
void charger_control_disable_charger_relay()
{
HAL_GPIO_WritePin(Charger_Relay_GPIO_Port, Charger_Relay_Pin, GPIO_PIN_RESET);
}
/** @brief enables remote control of the charger
* @note The relay is also dependend on the Shutdown Circuit
*/
void charger_control_enable_remote()
{
HAL_GPIO_WritePin(Charger_Remote_Shutdown_GPIO_Port, Charger_Remote_Shutdown_Pin, GPIO_PIN_SET);
}
/** @brief disable remote control of the charger
* @note The relay is also dependend on the Shutdown Circuit
*/
void charger_control_disable_remote()
{
HAL_GPIO_WritePin(Charger_Remote_Shutdown_GPIO_Port, Charger_Remote_Shutdown_Pin, GPIO_PIN_RESET);
}

811
Software/Core/Src/main.c
View File

@ -1,811 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2022 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "charger_control.h"
#include "slave_handler.h"
#include "can.h"
#include "b_cccv_algo.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
FDCAN_HandleTypeDef hfdcan1;
I2C_HandleTypeDef hi2c4;
LTDC_HandleTypeDef hltdc;
SD_HandleTypeDef hsd2;
UART_HandleTypeDef huart5;
UART_HandleTypeDef huart10;
PCD_HandleTypeDef hpcd_USB_OTG_HS;
SDRAM_HandleTypeDef hsdram1;
uint16_t setpoint = 0;
float currentsetpoint = 0.0;
float voltagesetpoint = 3.8;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
void PeriphCommonClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_FDCAN1_Init(void);
static void MX_FMC_Init(void);
static void MX_I2C4_Init(void);
static void MX_SDMMC2_SD_Init(void);
static void MX_USART10_UART_Init(void);
static void MX_USB_OTG_HS_PCD_Init(void);
static void MX_UART5_Init(void);
static void MX_LTDC_Init(void);
/* USER CODE BEGIN PFP */
uint32_t MemoryCheck(UART_HandleTypeDef *uart_console, SDRAM_HandleTypeDef *sram);
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
#define RAM_TEST_BLOCKSIZE 4096
__attribute__((section(".ahb_sec"))) uint32_t testarray[RAM_TEST_BLOCKSIZE];
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* Configure the peripherals common clocks */
PeriphCommonClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_FDCAN1_Init();
//MX_FMC_Init();
MX_I2C4_Init();
//MX_SDMMC2_SD_Init();
MX_USART10_UART_Init();
MX_USB_OTG_HS_PCD_Init();
MX_UART5_Init();
//MX_LTDC_Init();
/* USER CODE BEGIN 2 */
//uint32_t sdramcheck = MemoryCheck(&huart5, &hsdram1);
//MX_LTDC_Init();
slave_handler_init();
initCan(&hfdcan1);
charger_control_init(&hi2c4);
initChargerAlgo(102, 4.15);
setchargecurrent(0.0);
setchargevoltage(102, 0);
charger_control_disable_remote();
//HAL_LTDC_Reload(&hltdc, LTDC_RELOAD_IMMEDIATE);
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
uint32_t lasttick = HAL_GetTick();
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
if((HAL_GetTick() - lasttick) > 1000)
{
// float maxvoltage = slaves_get_maximum_voltage();
// lasttick = HAL_GetTick();
// chargingloop(slaves_get_maximum_voltage());
HAL_GPIO_TogglePin(STATUS_LED_2_GPIO_Port, STATUS_LED_2_Pin);
}
// HAL_Delay(500);
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/*AXI clock gating */
RCC->CKGAENR = 0xFFFFFFFF;
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Macro to configure the PLL clock source
*/
__HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLN = 20;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief Peripherals Common Clock Configuration
* @retval None
*/
void PeriphCommonClock_Config(void)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC|RCC_PERIPHCLK_SDMMC;
PeriphClkInitStruct.PLL2.PLL2M = 1;
PeriphClkInitStruct.PLL2.PLL2N = 20;
PeriphClkInitStruct.PLL2.PLL2P = 2;
PeriphClkInitStruct.PLL2.PLL2Q = 4;
PeriphClkInitStruct.PLL2.PLL2R = 2;
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief FDCAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_FDCAN1_Init(void)
{
/* USER CODE BEGIN FDCAN1_Init 0 */
/* USER CODE END FDCAN1_Init 0 */
/* USER CODE BEGIN FDCAN1_Init 1 */
/* USER CODE END FDCAN1_Init 1 */
hfdcan1.Instance = FDCAN1;
hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
hfdcan1.Init.AutoRetransmission = DISABLE;
hfdcan1.Init.TransmitPause = DISABLE;
hfdcan1.Init.ProtocolException = DISABLE;
hfdcan1.Init.NominalPrescaler = 2;
hfdcan1.Init.NominalSyncJumpWidth = 1;
hfdcan1.Init.NominalTimeSeg1 = 63;
hfdcan1.Init.NominalTimeSeg2 = 16;
hfdcan1.Init.DataPrescaler = 1;
hfdcan1.Init.DataSyncJumpWidth = 1;
hfdcan1.Init.DataTimeSeg1 = 1;
hfdcan1.Init.DataTimeSeg2 = 1;
hfdcan1.Init.MessageRAMOffset = 0;
hfdcan1.Init.StdFiltersNbr = 32;
hfdcan1.Init.ExtFiltersNbr = 0;
hfdcan1.Init.RxFifo0ElmtsNbr = 16;
hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxFifo1ElmtsNbr = 0;
hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxBuffersNbr = 0;
hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.TxEventsNbr = 0;
hfdcan1.Init.TxBuffersNbr = 0;
hfdcan1.Init.TxFifoQueueElmtsNbr = 1;
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FDCAN1_Init 2 */
/* USER CODE END FDCAN1_Init 2 */
}
/**
* @brief I2C4 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C4_Init(void)
{
/* USER CODE BEGIN I2C4_Init 0 */
/* USER CODE END I2C4_Init 0 */
/* USER CODE BEGIN I2C4_Init 1 */
/* USER CODE END I2C4_Init 1 */
hi2c4.Instance = I2C4;
hi2c4.Init.Timing = 0x10909CEC;
hi2c4.Init.OwnAddress1 = 0;
hi2c4.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c4.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c4.Init.OwnAddress2 = 0;
hi2c4.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
hi2c4.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c4.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c4) != HAL_OK)
{
Error_Handler();
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c4, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
{
Error_Handler();
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c4, 0) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN I2C4_Init 2 */
/* USER CODE END I2C4_Init 2 */
}
/**
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
hltdc.Init.HorizontalSync = 19;
hltdc.Init.VerticalSync = 2;
hltdc.Init.AccumulatedHBP = 159;
hltdc.Init.AccumulatedVBP = 22;
hltdc.Init.AccumulatedActiveW = 1183;
hltdc.Init.AccumulatedActiveH = 622;
hltdc.Init.TotalWidth = 1343;
hltdc.Init.TotalHeigh = 634;
hltdc.Init.Backcolor.Blue = 0;
hltdc.Init.Backcolor.Green = 0;
hltdc.Init.Backcolor.Red = 0;
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
{
Error_Handler();
}
pLayerCfg.WindowX0 = 0;
pLayerCfg.WindowX1 = 0;
pLayerCfg.WindowY0 = 0;
pLayerCfg.WindowY1 = 0;
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB888;
pLayerCfg.Alpha = 0;
pLayerCfg.Alpha0 = 0;
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
pLayerCfg.FBStartAdress = 201326592;
pLayerCfg.ImageWidth = 1024;
pLayerCfg.ImageHeight = 600;
pLayerCfg.Backcolor.Blue = 100;
pLayerCfg.Backcolor.Green = 0;
pLayerCfg.Backcolor.Red = 0;
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN LTDC_Init 2 */
__HAL_LTDC_ENABLE(&hltdc);
__HAL_LTDC_LAYER_ENABLE(&hltdc,1);
/* USER CODE END LTDC_Init 2 */
}
/**
* @brief SDMMC2 Initialization Function
* @param None
* @retval None
*/
static void MX_SDMMC2_SD_Init(void)
{
/* USER CODE BEGIN SDMMC2_Init 0 */
/* USER CODE END SDMMC2_Init 0 */
/* USER CODE BEGIN SDMMC2_Init 1 */
/* USER CODE END SDMMC2_Init 1 */
hsd2.Instance = SDMMC2;
hsd2.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
hsd2.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
hsd2.Init.BusWide = SDMMC_BUS_WIDE_1B;
hsd2.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
hsd2.Init.ClockDiv = 0;
if (HAL_SD_Init(&hsd2) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SDMMC2_Init 2 */
/* USER CODE END SDMMC2_Init 2 */
}
/**
* @brief UART5 Initialization Function
* @param None
* @retval None
*/
static void MX_UART5_Init(void)
{
/* USER CODE BEGIN UART5_Init 0 */
/* USER CODE END UART5_Init 0 */
/* USER CODE BEGIN UART5_Init 1 */
/* USER CODE END UART5_Init 1 */
huart5.Instance = UART5;
huart5.Init.BaudRate = 115200;
huart5.Init.WordLength = UART_WORDLENGTH_8B;
huart5.Init.StopBits = UART_STOPBITS_1;
huart5.Init.Parity = UART_PARITY_NONE;
huart5.Init.Mode = UART_MODE_TX_RX;
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart5.Init.OverSampling = UART_OVERSAMPLING_16;
huart5.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart5.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart5.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart5) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart5, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart5, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart5) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN UART5_Init 2 */
/* USER CODE END UART5_Init 2 */
}
/**
* @brief USART10 Initialization Function
* @param None
* @retval None
*/
static void MX_USART10_UART_Init(void)
{
/* USER CODE BEGIN USART10_Init 0 */
/* USER CODE END USART10_Init 0 */
/* USER CODE BEGIN USART10_Init 1 */
/* USER CODE END USART10_Init 1 */
huart10.Instance = USART10;
huart10.Init.BaudRate = 115200;
huart10.Init.WordLength = UART_WORDLENGTH_8B;
huart10.Init.StopBits = UART_STOPBITS_1;
huart10.Init.Parity = UART_PARITY_NONE;
huart10.Init.Mode = UART_MODE_TX_RX;
huart10.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart10.Init.OverSampling = UART_OVERSAMPLING_16;
huart10.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart10.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart10.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart10) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart10, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart10, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart10) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART10_Init 2 */
/* USER CODE END USART10_Init 2 */
}
/**
* @brief USB_OTG_HS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_HS_PCD_Init(void)
{
/* USER CODE BEGIN USB_OTG_HS_Init 0 */
/* USER CODE END USB_OTG_HS_Init 0 */
/* USER CODE BEGIN USB_OTG_HS_Init 1 */
/* USER CODE END USB_OTG_HS_Init 1 */
hpcd_USB_OTG_HS.Instance = USB_OTG_HS;
hpcd_USB_OTG_HS.Init.dev_endpoints = 9;
hpcd_USB_OTG_HS.Init.speed = PCD_SPEED_FULL;
hpcd_USB_OTG_HS.Init.dma_enable = DISABLE;
hpcd_USB_OTG_HS.Init.phy_itface = USB_OTG_EMBEDDED_PHY;
hpcd_USB_OTG_HS.Init.Sof_enable = DISABLE;
hpcd_USB_OTG_HS.Init.low_power_enable = DISABLE;
hpcd_USB_OTG_HS.Init.lpm_enable = DISABLE;
hpcd_USB_OTG_HS.Init.vbus_sensing_enable = ENABLE;
hpcd_USB_OTG_HS.Init.use_dedicated_ep1 = DISABLE;
hpcd_USB_OTG_HS.Init.use_external_vbus = DISABLE;
if (HAL_PCD_Init(&hpcd_USB_OTG_HS) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USB_OTG_HS_Init 2 */
/* USER CODE END USB_OTG_HS_Init 2 */
}
/* FMC initialization function */
static void MX_FMC_Init(void)
{
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
/* USER CODE BEGIN FMC_Init 1 */
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 2;
SdramTiming.ExitSelfRefreshDelay = 5;
SdramTiming.SelfRefreshTime = 3;
SdramTiming.RowCycleDelay = 4;
SdramTiming.WriteRecoveryTime = 3;
SdramTiming.RPDelay = 3;
SdramTiming.RCDDelay = 2;
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
{
Error_Handler( );
}
/* USER CODE BEGIN FMC_Init 2 */
FMC_SDRAM_CommandTypeDef command;
HAL_StatusTypeDef status;
command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
command.AutoRefreshNumber = 1;
command.ModeRegisterDefinition = 0;
status = HAL_SDRAM_SendCommand(&hsdram1, &command, 1000);
HAL_Delay(1);
command.CommandMode = FMC_SDRAM_CMD_PALL;
command.AutoRefreshNumber = 8;
command.ModeRegisterDefinition = 0;
status = HAL_SDRAM_SendCommand(&hsdram1, &command, 1000);
command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
command.AutoRefreshNumber = 1;
command.ModeRegisterDefinition = 0x130;
status = HAL_SDRAM_SendCommand(&hsdram1, &command, 1000);
command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
command.AutoRefreshNumber = 8;
command.ModeRegisterDefinition = 0;
status = HAL_SDRAM_SendCommand(&hsdram1, &command, 1000);
status = HAL_SDRAM_ProgramRefreshRate(&hsdram1, 0x0595);
/* USER CODE END FMC_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOF, STATUS_LED_1_Pin|STATUS_LED_2_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, Display_Reset_Pin|Display_Standby_Pin|Display_Left_Right_Pin|Display_Up_Down_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(Charger_Relay_GPIO_Port, Charger_Relay_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(Charger_Remote_Shutdown_GPIO_Port, Charger_Remote_Shutdown_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : STATUS_LED_1_Pin STATUS_LED_2_Pin */
GPIO_InitStruct.Pin = STATUS_LED_1_Pin|STATUS_LED_2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
/*Configure GPIO pins : Display_Reset_Pin Display_Standby_Pin Display_Left_Right_Pin Display_Up_Down_Pin */
GPIO_InitStruct.Pin = Display_Reset_Pin|Display_Standby_Pin|Display_Left_Right_Pin|Display_Up_Down_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/*Configure GPIO pins : Charger_CC_Status_Pin Charger_OT_Pin Charger_LIM_Pin Charger_DC_FAIL_Pin */
GPIO_InitStruct.Pin = Charger_CC_Status_Pin|Charger_OT_Pin|Charger_LIM_Pin|Charger_DC_FAIL_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
/*Configure GPIO pin : Charger_Relay_Pin */
GPIO_InitStruct.Pin = Charger_Relay_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(Charger_Relay_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : Charger_AC_Fail_Pin */
GPIO_InitStruct.Pin = Charger_AC_Fail_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(Charger_AC_Fail_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : Charger_Remote_Shutdown_Pin */
GPIO_InitStruct.Pin = Charger_Remote_Shutdown_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(Charger_Remote_Shutdown_GPIO_Port, &GPIO_InitStruct);
}
/* USER CODE BEGIN 4 */
/** @brief run a Memory Check over the complete SDRAM Area
*
*/
uint32_t MemoryCheck(UART_HandleTypeDef *uart_console, SDRAM_HandleTypeDef *sram)
{
uint32_t totalerrors = 0;
uint32_t numberofsectors = 400;
uint32_t testadr = 0xC0000000;
//*testpointer = 1;
for(uint32_t startaddress = 0; startaddress < numberofsectors*RAM_TEST_BLOCKSIZE; startaddress += RAM_TEST_BLOCKSIZE)
{
for(uint32_t i = 0; i < RAM_TEST_BLOCKSIZE; i++)
{
testarray[i] = 0xFFFF00FF;
}
//*testadr = (uint32_t*) ;
HAL_StatusTypeDef status = HAL_SDRAM_Write_32b(sram, (uint32_t*)(testadr+startaddress), testarray, RAM_TEST_BLOCKSIZE);
//testadr = (uint32_t*) (startaddress + 0xC0000000);
for(uint32_t i = 0; i < RAM_TEST_BLOCKSIZE; i++)
{
testarray[i] = 0;
}
status = HAL_SDRAM_Read_32b(sram,(uint32_t*)(testadr+startaddress), testarray, RAM_TEST_BLOCKSIZE);
uint32_t errorcounter = 0;
for(uint32_t i = 0; i <RAM_TEST_BLOCKSIZE;i++)
{
if(testarray[i] != (i+3000))
{
errorcounter++;
}
}
totalerrors += errorcounter;
}
return totalerrors;
}
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

70
Software/Core/Src/slave_handler.c
View File

@ -1,70 +0,0 @@
/*
* slave_handler.c
*
* Created on: Jun 21, 2023
* Author: max
*/
#include "slave_handler.h"
#include "can.h"
#include "can-halal.h"
static uint8_t slave_id_to_index[128] = {0xFF};
void slave_handler_init()
{
memset(slave_id_to_index,0xFF,128);
}
SlaveHandle slaves[N_SLAVES];
static size_t get_slave_index(uint8_t);
void slaves_handle_status(const uint8_t *data) {
uint8_t slave_id = data[0] & 0x7F;
uint8_t idx = get_slave_index(slave_id);
int error = data[0] & 0x80;
if (error) {
if (slaves[idx].error.kind == SLAVE_ERR_NONE) {
slaves[idx].error.kind = SLAVE_ERR_UNKNOWN;
}
} else {
slaves[idx].error.kind = SLAVE_ERR_NONE;
}
slaves[idx].soc = data[1];
const uint8_t *ptr = &data[2];
slaves[idx].min_voltage = ftcan_unmarshal_unsigned(&ptr, 2);
slaves[idx].max_voltage = ftcan_unmarshal_unsigned(&ptr, 2);
slaves[idx].max_temp = ftcan_unmarshal_unsigned(&ptr, 2);
slaves[idx].last_message = HAL_GetTick();
}
float slaves_get_maximum_voltage()
{
float maxvoltage = 0;
for(uint8_t i = 0; i < N_SLAVES; i++)
{
if(maxvoltage < slaves[i].max_voltage)
maxvoltage = slaves[i].max_voltage;
}
return ((float)maxvoltage)/10000;
}
static size_t get_slave_index(uint8_t slave_id) {
// Slave IDs are 7-bit, so we can use a 128-element array to map them to
// indices. 0xFF is used to mark unseen slave IDs, since the highest index we
// could need is N_SLAVES - 1 (i.e. 5).
static size_t next_slave_index = 0;
if (slave_id_to_index[slave_id] == 0xFF) {
if (next_slave_index >= N_SLAVES) {
// We've seen more than N_SLAVES slave IDs, this shouldn't happen.
Error_Handler();
}
slave_id_to_index[slave_id] = next_slave_index;
slaves[next_slave_index].id = slave_id;
next_slave_index++;
}
return slave_id_to_index[slave_id];
}

976
Software/Core/Src/stm32h7xx_hal_msp.c
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@ -1,976 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2022 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/**
* @brief FDCAN MSP Initialization
* This function configures the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspInit 0 */
/* USER CODE END FDCAN1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_FDCAN_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**FDCAN1 GPIO Configuration
PB8 ------> FDCAN1_RX
PB9 ------> FDCAN1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* FDCAN1 interrupt Init */
HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
HAL_NVIC_SetPriority(FDCAN_CAL_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(FDCAN_CAL_IRQn);
/* USER CODE BEGIN FDCAN1_MspInit 1 */
/* USER CODE END FDCAN1_MspInit 1 */
}
}
/**
* @brief FDCAN MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
{
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspDeInit 0 */
/* USER CODE END FDCAN1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_FDCAN_CLK_DISABLE();
/**FDCAN1 GPIO Configuration
PB8 ------> FDCAN1_RX
PB9 ------> FDCAN1_TX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
/* FDCAN1 interrupt DeInit */
HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
HAL_NVIC_DisableIRQ(FDCAN1_IT1_IRQn);
HAL_NVIC_DisableIRQ(FDCAN_CAL_IRQn);
/* USER CODE BEGIN FDCAN1_MspDeInit 1 */
/* USER CODE END FDCAN1_MspDeInit 1 */
}
}
/**
* @brief I2C MSP Initialization
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hi2c->Instance==I2C4)
{
/* USER CODE BEGIN I2C4_MspInit 0 */
/* USER CODE END I2C4_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C4;
PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
__HAL_RCC_GPIOB_CLK_ENABLE();
/**I2C4 GPIO Configuration
PB6 ------> I2C4_SCL
PB7 ------> I2C4_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF6_I2C4;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_I2C4_CLK_ENABLE();
/* USER CODE BEGIN I2C4_MspInit 1 */
/* USER CODE END I2C4_MspInit 1 */
}
}
/**
* @brief I2C MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
{
if(hi2c->Instance==I2C4)
{
/* USER CODE BEGIN I2C4_MspDeInit 0 */
/* USER CODE END I2C4_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C4_CLK_DISABLE();
/**I2C4 GPIO Configuration
PB6 ------> I2C4_SCL
PB7 ------> I2C4_SDA
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
/* USER CODE BEGIN I2C4_MspDeInit 1 */
/* USER CODE END I2C4_MspDeInit 1 */
}
}
/**
* @brief LTDC MSP Initialization
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hltdc->Instance==LTDC)
{
/* USER CODE BEGIN LTDC_MspInit 0 */
/* USER CODE END LTDC_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
PeriphClkInitStruct.PLL3.PLL3M = 1;
PeriphClkInitStruct.PLL3.PLL3N = 12;
PeriphClkInitStruct.PLL3.PLL3P = 2;
PeriphClkInitStruct.PLL3.PLL3Q = 3;
PeriphClkInitStruct.PLL3.PLL3R = 3;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**LTDC GPIO Configuration
PF10 ------> LTDC_DE
PC0 ------> LTDC_R5
PA1 ------> LTDC_R2
PA3 ------> LTDC_B5
PA4 ------> LTDC_VSYNC
PA5 ------> LTDC_R4
PA6 ------> LTDC_G2
PC4 ------> LTDC_R7
PB0 ------> LTDC_R3
PB1 ------> LTDC_R6
PB10 ------> LTDC_G4
PB11 ------> LTDC_G5
PB15 ------> LTDC_G7
PG7 ------> LTDC_CLK
PC6 ------> LTDC_HSYNC
PC7 ------> LTDC_G6
PC9 ------> LTDC_G3
PA8 ------> LTDC_B3
PA10 ------> LTDC_B4
PA15 ------> LTDC_B6
PD2 ------> LTDC_B7
PD6 ------> LTDC_B2
*/
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5
|GPIO_PIN_6|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF10_LTDC;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF13_LTDC;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF12_LTDC;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* LTDC interrupt Init */
HAL_NVIC_SetPriority(LTDC_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(LTDC_IRQn);
HAL_NVIC_SetPriority(LTDC_ER_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(LTDC_ER_IRQn);
/* USER CODE BEGIN LTDC_MspInit 1 */
/* USER CODE END LTDC_MspInit 1 */
}
}
/**
* @brief LTDC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
{
if(hltdc->Instance==LTDC)
{
/* USER CODE BEGIN LTDC_MspDeInit 0 */
/* USER CODE END LTDC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_LTDC_CLK_DISABLE();
/**LTDC GPIO Configuration
PF10 ------> LTDC_DE
PC0 ------> LTDC_R5
PA1 ------> LTDC_R2
PA3 ------> LTDC_B5
PA4 ------> LTDC_VSYNC
PA5 ------> LTDC_R4
PA6 ------> LTDC_G2
PC4 ------> LTDC_R7
PB0 ------> LTDC_R3
PB1 ------> LTDC_R6
PB10 ------> LTDC_G4
PB11 ------> LTDC_G5
PB15 ------> LTDC_G7
PG7 ------> LTDC_CLK
PC6 ------> LTDC_HSYNC
PC7 ------> LTDC_G6
PC9 ------> LTDC_G3
PA8 ------> LTDC_B3
PA10 ------> LTDC_B4
PA15 ------> LTDC_B6
PD2 ------> LTDC_B7
PD6 ------> LTDC_B2
*/
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_7
|GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5
|GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_10|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2|GPIO_PIN_6);
/* LTDC interrupt DeInit */
HAL_NVIC_DisableIRQ(LTDC_IRQn);
HAL_NVIC_DisableIRQ(LTDC_ER_IRQn);
/* USER CODE BEGIN LTDC_MspDeInit 1 */
/* USER CODE END LTDC_MspDeInit 1 */
}
}
/**
* @brief SD MSP Initialization
* This function configures the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hsd->Instance==SDMMC2)
{
/* USER CODE BEGIN SDMMC2_MspInit 0 */
/* USER CODE END SDMMC2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SDMMC2_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**SDMMC2 GPIO Configuration
PC1 ------> SDMMC2_CK
PB14 ------> SDMMC2_D0
PD7 ------> SDMMC2_CMD
*/
GPIO_InitStruct.Pin = GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_SDMMC2;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_SDMMC2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_SDMMC2;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* USER CODE BEGIN SDMMC2_MspInit 1 */
/* USER CODE END SDMMC2_MspInit 1 */
}
}
/**
* @brief SD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
{
if(hsd->Instance==SDMMC2)
{
/* USER CODE BEGIN SDMMC2_MspDeInit 0 */
/* USER CODE END SDMMC2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDMMC2_CLK_DISABLE();
/**SDMMC2 GPIO Configuration
PC1 ------> SDMMC2_CK
PB14 ------> SDMMC2_D0
PD7 ------> SDMMC2_CMD
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_7);
/* USER CODE BEGIN SDMMC2_MspDeInit 1 */
/* USER CODE END SDMMC2_MspDeInit 1 */
}
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(huart->Instance==UART5)
{
/* USER CODE BEGIN UART5_MspInit 0 */
/* USER CODE END UART5_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART5;
PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_UART5_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**UART5 GPIO Configuration
PB12 ------> UART5_RX
PB13 ------> UART5_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_UART5;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN UART5_MspInit 1 */
/* USER CODE END UART5_MspInit 1 */
}
else if(huart->Instance==USART10)
{
/* USER CODE BEGIN USART10_MspInit 0 */
/* USER CODE END USART10_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART10;
PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16910CLKSOURCE_D2PCLK2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_USART10_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
/**USART10 GPIO Configuration
PE2 ------> USART10_RX
PE3 ------> USART10_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF11_USART10;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/* USER CODE BEGIN USART10_MspInit 1 */
/* USER CODE END USART10_MspInit 1 */
}
}
/**
* @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==UART5)
{
/* USER CODE BEGIN UART5_MspDeInit 0 */
/* USER CODE END UART5_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_UART5_CLK_DISABLE();
/**UART5 GPIO Configuration
PB12 ------> UART5_RX
PB13 ------> UART5_TX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13);
/* USER CODE BEGIN UART5_MspDeInit 1 */
/* USER CODE END UART5_MspDeInit 1 */
}
else if(huart->Instance==USART10)
{
/* USER CODE BEGIN USART10_MspDeInit 0 */
/* USER CODE END USART10_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART10_CLK_DISABLE();
/**USART10 GPIO Configuration
PE2 ------> USART10_RX
PE3 ------> USART10_TX
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_3);
/* USER CODE BEGIN USART10_MspDeInit 1 */
/* USER CODE END USART10_MspDeInit 1 */
}
}
/**
* @brief PCD MSP Initialization
* This function configures the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hpcd->Instance==USB_OTG_HS)
{
/* USER CODE BEGIN USB_OTG_HS_MspInit 0 */
/* USER CODE END USB_OTG_HS_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Enable USB Voltage detector
*/
HAL_PWREx_EnableUSBVoltageDetector();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**USB_OTG_HS GPIO Configuration
PA9 ------> USB_OTG_HS_VBUS
PA11 ------> USB_OTG_HS_DM
PA12 ------> USB_OTG_HS_DP
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
/* USER CODE BEGIN USB_OTG_HS_MspInit 1 */
/* USER CODE END USB_OTG_HS_MspInit 1 */
}
}
/**
* @brief PCD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
{
if(hpcd->Instance==USB_OTG_HS)
{
/* USER CODE BEGIN USB_OTG_HS_MspDeInit 0 */
/* USER CODE END USB_OTG_HS_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USB_OTG_HS_CLK_DISABLE();
/**USB_OTG_HS GPIO Configuration
PA9 ------> USB_OTG_HS_VBUS
PA11 ------> USB_OTG_HS_DM
PA12 ------> USB_OTG_HS_DP
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_12);
/* USER CODE BEGIN USB_OTG_HS_MspDeInit 1 */
/* USER CODE END USB_OTG_HS_MspDeInit 1 */
}
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
if (FMC_Initialized) {
return;
}
FMC_Initialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
/** FMC GPIO Configuration
PF0 ------> FMC_A0
PF1 ------> FMC_A1
PF2 ------> FMC_A2
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PF5 ------> FMC_A5
PC2_C ------> FMC_SDNE0
PC3_C ------> FMC_SDCKE0
PA7 ------> FMC_SDNWE
PF11 ------> FMC_SDNRAS
PF12 ------> FMC_A6
PF13 ------> FMC_A7
PF14 ------> FMC_A8
PF15 ------> FMC_A9
PG0 ------> FMC_A10
PG1 ------> FMC_A11
PE7 ------> FMC_D4
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE10 ------> FMC_D7
PE11 ------> FMC_D8
PE12 ------> FMC_D9
PE13 ------> FMC_D10
PE14 ------> FMC_D11
PE15 ------> FMC_D12
PD8 ------> FMC_D13
PD9 ------> FMC_D14
PD10 ------> FMC_D15
PD14 ------> FMC_D0
PD15 ------> FMC_D1
PG2 ------> FMC_A12
PG4 ------> FMC_BA0
PG5 ------> FMC_BA1
PG8 ------> FMC_SDCLK
PD0 ------> FMC_D2
PD1 ------> FMC_D3
PG15 ------> FMC_SDNCAS
PE0 ------> FMC_NBL0
PE1 ------> FMC_NBL1
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
|GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(FMC_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(FMC_IRQn);
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
static uint32_t FMC_DeInitialized = 0;
static void HAL_FMC_MspDeInit(void){
/* USER CODE BEGIN FMC_MspDeInit 0 */
/* USER CODE END FMC_MspDeInit 0 */
if (FMC_DeInitialized) {
return;
}
FMC_DeInitialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_DISABLE();
/** FMC GPIO Configuration
PF0 ------> FMC_A0
PF1 ------> FMC_A1
PF2 ------> FMC_A2
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PF5 ------> FMC_A5
PC2_C ------> FMC_SDNE0
PC3_C ------> FMC_SDCKE0
PA7 ------> FMC_SDNWE
PF11 ------> FMC_SDNRAS
PF12 ------> FMC_A6
PF13 ------> FMC_A7
PF14 ------> FMC_A8
PF15 ------> FMC_A9
PG0 ------> FMC_A10
PG1 ------> FMC_A11
PE7 ------> FMC_D4
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE10 ------> FMC_D7
PE11 ------> FMC_D8
PE12 ------> FMC_D9
PE13 ------> FMC_D10
PE14 ------> FMC_D11
PE15 ------> FMC_D12
PD8 ------> FMC_D13
PD9 ------> FMC_D14
PD10 ------> FMC_D15
PD14 ------> FMC_D0
PD15 ------> FMC_D1
PG2 ------> FMC_A12
PG4 ------> FMC_BA0
PG5 ------> FMC_BA1
PG8 ------> FMC_SDCLK
PD0 ------> FMC_D2
PD1 ------> FMC_D3
PG15 ------> FMC_SDNCAS
PE0 ------> FMC_NBL0
PE1 ------> FMC_NBL1
*/
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
|GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
/* Peripheral interrupt DeInit */
HAL_NVIC_DisableIRQ(FMC_IRQn);
/* USER CODE BEGIN FMC_MspDeInit 1 */
/* USER CODE END FMC_MspDeInit 1 */
}
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN SDRAM_MspDeInit 0 */
/* USER CODE END SDRAM_MspDeInit 0 */
HAL_FMC_MspDeInit();
/* USER CODE BEGIN SDRAM_MspDeInit 1 */
/* USER CODE END SDRAM_MspDeInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

623
Software/FT23_Charger.ioc
View File

@ -1,623 +0,0 @@
#MicroXplorer Configuration settings - do not modify
CAD.formats=
CAD.pinconfig=
CAD.provider=
FDCAN1.CalculateBaudRateNominal=500000
FDCAN1.CalculateTimeBitNominal=2000
FDCAN1.CalculateTimeQuantumNominal=25.0
FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,StdFiltersNbr,RxFifo0ElmtsNbr,TxFifoQueueElmtsNbr,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2
FDCAN1.NominalPrescaler=2
FDCAN1.NominalTimeSeg1=63
FDCAN1.NominalTimeSeg2=16
FDCAN1.RxFifo0ElmtsNbr=16
FDCAN1.StdFiltersNbr=32
FDCAN1.TxFifoQueueElmtsNbr=1
FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3
FMC.ColumnBitsNumber1=FMC_SDRAM_COLUMN_BITS_NUM_9
FMC.ExitSelfRefreshDelay1=5
FMC.IPParameters=ReadBurst1,WriteProtection1,LoadToActiveDelay1,ExitSelfRefreshDelay1,CASLatency1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,RCDDelay1,RPDelay1,RPDelay2,WriteRecoveryTime1,ColumnBitsNumber1,ReadPipeDelay1,ReadPipeDelay2,SDClockPeriod1,SDClockPeriod2
FMC.LoadToActiveDelay1=2
FMC.RCDDelay1=2
FMC.RPDelay1=3
FMC.RPDelay2=3
FMC.ReadBurst1=FMC_SDRAM_RBURST_DISABLE
FMC.ReadPipeDelay1=FMC_SDRAM_RPIPE_DELAY_1
FMC.ReadPipeDelay2=FMC_SDRAM_RPIPE_DELAY_1
FMC.RowCycleDelay1=4
FMC.RowCycleDelay2=4
FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2
FMC.SDClockPeriod2=FMC_SDRAM_CLOCK_PERIOD_2
FMC.SelfRefreshTime1=3
FMC.WriteProtection1=FMC_SDRAM_WRITE_PROTECTION_DISABLE
FMC.WriteRecoveryTime1=3
File.Version=6
GPIO.groupedBy=Group By Peripherals
I2C4.IPParameters=Timing
I2C4.Timing=0x10909CEC
KeepUserPlacement=false
LTDC.ActiveH=600
LTDC.ActiveW=1024
LTDC.Blue_L0=100
LTDC.FBStartAdress_L0=201326592
LTDC.HBP=140
LTDC.HFP=160
LTDC.HSync=20
LTDC.IPParameters=ActiveW,ActiveH,HFP,HBP,HSync,VSync,VBP,VFP,Layers,FBStartAdress_L0,ImageWidth_L0,ImageHeight_L0,PixelFormat_L0,Blue_L0
LTDC.ImageHeight_L0=600
LTDC.ImageWidth_L0=1024
LTDC.Layers=0
LTDC.PixelFormat_L0=LTDC_PIXEL_FORMAT_RGB888
LTDC.VBP=20
LTDC.VFP=12
LTDC.VSync=3
Mcu.CPN=STM32H7A3ZIT6
Mcu.Family=STM32H7
Mcu.IP0=CORTEX_M7
Mcu.IP1=DEBUG
Mcu.IP10=UART5
Mcu.IP11=USART10
Mcu.IP12=USB_OTG_HS
Mcu.IP2=FDCAN1
Mcu.IP3=FMC
Mcu.IP4=I2C4
Mcu.IP5=LTDC
Mcu.IP6=NVIC
Mcu.IP7=RCC
Mcu.IP8=SDMMC2
Mcu.IP9=SYS
Mcu.IPNb=13
Mcu.Name=STM32H7A3Z(G-I)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PE2
Mcu.Pin1=PE3
Mcu.Pin10=PF6
Mcu.Pin11=PF7
Mcu.Pin12=PF10
Mcu.Pin13=PH0-OSC_IN
Mcu.Pin14=PH1-OSC_OUT
Mcu.Pin15=PC0
Mcu.Pin16=PC1
Mcu.Pin17=PC2_C
Mcu.Pin18=PC3_C
Mcu.Pin19=PA1
Mcu.Pin2=PC14-OSC32_IN
Mcu.Pin20=PA3
Mcu.Pin21=PA4
Mcu.Pin22=PA5
Mcu.Pin23=PA6
Mcu.Pin24=PA7
Mcu.Pin25=PC4
Mcu.Pin26=PB0
Mcu.Pin27=PB1
Mcu.Pin28=PF11
Mcu.Pin29=PF12
Mcu.Pin3=PC15-OSC32_OUT
Mcu.Pin30=PF13
Mcu.Pin31=PF14
Mcu.Pin32=PF15
Mcu.Pin33=PG0
Mcu.Pin34=PG1
Mcu.Pin35=PE7
Mcu.Pin36=PE8
Mcu.Pin37=PE9
Mcu.Pin38=PE10
Mcu.Pin39=PE11
Mcu.Pin4=PF0
Mcu.Pin40=PE12
Mcu.Pin41=PE13
Mcu.Pin42=PE14
Mcu.Pin43=PE15
Mcu.Pin44=PB10
Mcu.Pin45=PB11
Mcu.Pin46=PB12
Mcu.Pin47=PB13
Mcu.Pin48=PB14
Mcu.Pin49=PB15
Mcu.Pin5=PF1
Mcu.Pin50=PD8
Mcu.Pin51=PD9
Mcu.Pin52=PD10
Mcu.Pin53=PD14
Mcu.Pin54=PD15
Mcu.Pin55=PG2
Mcu.Pin56=PG4
Mcu.Pin57=PG5
Mcu.Pin58=PG7
Mcu.Pin59=PG8
Mcu.Pin6=PF2
Mcu.Pin60=PC6
Mcu.Pin61=PC7
Mcu.Pin62=PC8
Mcu.Pin63=PC9
Mcu.Pin64=PA8
Mcu.Pin65=PA9
Mcu.Pin66=PA10
Mcu.Pin67=PA11
Mcu.Pin68=PA12
Mcu.Pin69=PA13
Mcu.Pin7=PF3
Mcu.Pin70=PA14
Mcu.Pin71=PA15
Mcu.Pin72=PC10
Mcu.Pin73=PC11
Mcu.Pin74=PC12
Mcu.Pin75=PD0
Mcu.Pin76=PD1
Mcu.Pin77=PD2
Mcu.Pin78=PD6
Mcu.Pin79=PD7
Mcu.Pin8=PF4
Mcu.Pin80=PG9
Mcu.Pin81=PG11
Mcu.Pin82=PG12
Mcu.Pin83=PG13
Mcu.Pin84=PG14
Mcu.Pin85=PG15
Mcu.Pin86=PB3
Mcu.Pin87=PB4
Mcu.Pin88=PB5
Mcu.Pin89=PB6
Mcu.Pin9=PF5
Mcu.Pin90=PB7
Mcu.Pin91=PB8
Mcu.Pin92=PB9
Mcu.Pin93=PE0
Mcu.Pin94=PE1
Mcu.Pin95=VP_SYS_VS_Systick
Mcu.PinsNb=96
Mcu.ThirdParty0=STMicroelectronics.X-CUBE-TOUCHGFX.4.21.0
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32H7A3ZITx
MxCube.Version=6.7.0
MxDb.Version=DB.6.0.70
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.FDCAN1_IT0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.FDCAN1_IT1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.FDCAN_CAL_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.FMC_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.LTDC_ER_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.LTDC_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA1.Mode=RGB666
PA1.Signal=LTDC_R2
PA10.Mode=RGB666
PA10.Signal=LTDC_B4
PA11.Mode=Device_Only_FS
PA11.Signal=USB_OTG_HS_DM
PA12.Mode=Device_Only_FS
PA12.Signal=USB_OTG_HS_DP
PA13.Mode=Trace_Asynchronous_SW
PA13.Signal=DEBUG_JTMS-SWDIO
PA14.Mode=Trace_Asynchronous_SW
PA14.Signal=DEBUG_JTCK-SWCLK
PA15.Mode=RGB666
PA15.Signal=LTDC_B6
PA3.Mode=RGB666
PA3.Signal=LTDC_B5
PA4.Mode=RGB666
PA4.Signal=LTDC_VSYNC
PA5.Mode=RGB666
PA5.Signal=LTDC_R4
PA6.Mode=RGB666
PA6.Signal=LTDC_G2
PA7.Signal=FMC_SDNWE
PA8.Mode=RGB666
PA8.Signal=LTDC_B3
PA9.Mode=Activate_VBUS_FS
PA9.Signal=USB_OTG_HS_VBUS
PB0.Mode=RGB666
PB0.Signal=LTDC_R3
PB1.Mode=RGB666
PB1.Signal=LTDC_R6
PB10.Mode=RGB666
PB10.Signal=LTDC_G4
PB11.Mode=RGB666
PB11.Signal=LTDC_G5
PB12.Mode=Asynchronous
PB12.Signal=UART5_RX
PB13.Mode=Asynchronous
PB13.Signal=UART5_TX
PB14.Mode=SD_1_bit
PB14.Signal=SDMMC2_D0
PB15.Mode=RGB666
PB15.Signal=LTDC_G7
PB3.Mode=Trace_Asynchronous_SW
PB3.Signal=DEBUG_JTDO-SWO
PB4.GPIOParameters=GPIO_Label
PB4.GPIO_Label=Charger_AC_Fail
PB4.Locked=true
PB4.Signal=GPIO_Input
PB5.GPIOParameters=GPIO_Label
PB5.GPIO_Label=Charger_Remote_Shutdown
PB5.Locked=true
PB5.Signal=GPIO_Output
PB6.GPIOParameters=GPIO_Pu
PB6.GPIO_Pu=GPIO_PULLUP
PB6.Locked=true
PB6.Mode=I2C
PB6.Signal=I2C4_SCL
PB7.GPIOParameters=GPIO_Pu
PB7.GPIO_Pu=GPIO_PULLUP
PB7.Locked=true
PB7.Mode=I2C
PB7.Signal=I2C4_SDA
PB8.Mode=FDCAN_Activate
PB8.Signal=FDCAN1_RX
PB9.Mode=FDCAN_Activate
PB9.Signal=FDCAN1_TX
PC0.Mode=RGB666
PC0.Signal=LTDC_R5
PC1.Mode=SD_1_bit
PC1.Signal=SDMMC2_CK
PC10.GPIOParameters=GPIO_Label
PC10.GPIO_Label=Display_Standby
PC10.Locked=true
PC10.Signal=GPIO_Output
PC11.GPIOParameters=GPIO_Label
PC11.GPIO_Label=Display_Left_Right
PC11.Locked=true
PC11.Signal=GPIO_Output
PC12.GPIOParameters=GPIO_Label
PC12.GPIO_Label=Display_Up\:Down
PC12.Locked=true
PC12.Signal=GPIO_Output
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Mode=LSE-External-Oscillator
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
PC2_C.Mode=SdramChipSelect1_1
PC2_C.Signal=FMC_SDNE0
PC3_C.Mode=SdramChipSelect1_1
PC3_C.Signal=FMC_SDCKE0
PC4.Mode=RGB666
PC4.Signal=LTDC_R7
PC6.Mode=RGB666
PC6.Signal=LTDC_HSYNC
PC7.Mode=RGB666
PC7.Signal=LTDC_G6
PC8.GPIOParameters=GPIO_Label
PC8.GPIO_Label=Display_Reset
PC8.Locked=true
PC8.Signal=GPIO_Output
PC9.Mode=RGB666
PC9.Signal=LTDC_G3
PD0.Signal=FMC_D2_DA2
PD1.Signal=FMC_D3_DA3
PD10.Signal=FMC_D15_DA15
PD14.Signal=FMC_D0_DA0
PD15.Signal=FMC_D1_DA1
PD2.Mode=RGB666
PD2.Signal=LTDC_B7
PD6.Mode=RGB666
PD6.Signal=LTDC_B2
PD7.Mode=SD_1_bit
PD7.Signal=SDMMC2_CMD
PD8.Signal=FMC_D13_DA13
PD9.Signal=FMC_D14_DA14
PE0.Signal=FMC_NBL0
PE1.Signal=FMC_NBL1
PE10.Signal=FMC_D7_DA7
PE11.Signal=FMC_D8_DA8
PE12.Signal=FMC_D9_DA9
PE13.Signal=FMC_D10_DA10
PE14.Signal=FMC_D11_DA11
PE15.Signal=FMC_D12_DA12
PE2.Locked=true
PE2.Mode=Asynchronous
PE2.Signal=USART10_RX
PE3.Locked=true
PE3.Mode=Asynchronous
PE3.Signal=USART10_TX
PE7.Signal=FMC_D4_DA4
PE8.Signal=FMC_D5_DA5
PE9.Signal=FMC_D6_DA6
PF0.Signal=FMC_A0
PF1.Signal=FMC_A1
PF10.Mode=RGB666
PF10.Signal=LTDC_DE
PF11.Signal=FMC_SDNRAS
PF12.Signal=FMC_A6
PF13.Signal=FMC_A7
PF14.Signal=FMC_A8
PF15.Signal=FMC_A9
PF2.Signal=FMC_A2
PF3.Signal=FMC_A3
PF4.Signal=FMC_A4
PF5.Signal=FMC_A5
PF6.GPIOParameters=GPIO_Label
PF6.GPIO_Label=STATUS_LED_1
PF6.Locked=true
PF6.Signal=GPIO_Output
PF7.GPIOParameters=GPIO_Label
PF7.GPIO_Label=STATUS_LED_2
PF7.Locked=true
PF7.Signal=GPIO_Output
PG0.Signal=FMC_A10
PG1.Signal=FMC_A11
PG11.GPIOParameters=GPIO_Label
PG11.GPIO_Label=Charger_OT
PG11.Locked=true
PG11.Signal=GPIO_Input
PG12.GPIOParameters=GPIO_Label
PG12.GPIO_Label=Charger_LIM
PG12.Locked=true
PG12.Signal=GPIO_Input
PG13.GPIOParameters=GPIO_Label
PG13.GPIO_Label=Charger_DC_FAIL
PG13.Locked=true
PG13.Signal=GPIO_Input
PG14.GPIOParameters=GPIO_Label
PG14.GPIO_Label=Charger_Relay
PG14.Locked=true
PG14.Signal=GPIO_Output
PG15.Signal=FMC_SDNCAS
PG2.Signal=FMC_A12
PG4.Signal=FMC_A14_BA0
PG5.Signal=FMC_A15_BA1
PG7.Mode=RGB666
PG7.Signal=LTDC_CLK
PG8.Signal=FMC_SDCLK
PG9.GPIOParameters=GPIO_Label
PG9.GPIO_Label=Charger_CC_Status
PG9.Locked=true
PG9.Signal=GPIO_Input
PH0-OSC_IN.Mode=HSE-External-Oscillator
PH0-OSC_IN.Signal=RCC_OSC_IN
PH1-OSC_OUT.Mode=HSE-External-Oscillator
PH1-OSC_OUT.Signal=RCC_OSC_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32H7A3ZITx
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=FT23_Charger.ioc
ProjectManager.ProjectName=FT23_Charger
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_I2C4_Init-I2C4-false-HAL-true,6-MX_SDMMC2_SD_Init-SDMMC2-false-HAL-true,7-MX_USART10_UART_Init-USART10-false-HAL-true,8-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,9-MX_UART5_Init-UART5-false-HAL-true,10-MX_LTDC_Init-LTDC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_PLL2
RCC.ADCFreq_Value=160000000
RCC.AHB12Freq_Value=160000000
RCC.AHB4Freq_Value=160000000
RCC.APB1Freq_Value=80000000
RCC.APB2Freq_Value=80000000
RCC.APB3Freq_Value=80000000
RCC.APB4Freq_Value=80000000
RCC.AXIClockFreq_Value=160000000
RCC.CDCPRE=RCC_SYSCLK_DIV1
RCC.CDCPREFreq_Value=160000000
RCC.CDPPRE=RCC_APB3_DIV2
RCC.CDPPRE1=RCC_APB1_DIV2
RCC.CDPPRE2=RCC_APB2_DIV2
RCC.CECCLockSelection=RCC_CECCLKSOURCE_LSI
RCC.CECFreq_Value=32000
RCC.CKPERFreq_Value=64000000
RCC.CKPERSourceSelection=RCC_CLKPSOURCE_HSI
RCC.CSI_VALUE=4000000
RCC.CortexFreq_Value=160000000
RCC.Cortex_Div=SYSTICK_CLKSOURCE_HCLK
RCC.Cortex_DivARG=SystemCoreClock/1000
RCC.CpuClockFreq_Value=160000000
RCC.DAC1Freq_Value=32000
RCC.DAC2Freq_Value=32000
RCC.DFSDM2ACLkFreq_Value=80000000
RCC.DFSDM2Freq_Value=80000000
RCC.DFSDMACLkFreq_Value=80000000
RCC.DFSDMCLockSelection=RCC_DFSDM1CLKSOURCE_D2PCLK1
RCC.DFSDMFreq_Value=80000000
RCC.DIVM1=1
RCC.DIVM2=1
RCC.DIVM3=1
RCC.DIVN1=20
RCC.DIVN2=20
RCC.DIVN3=12
RCC.DIVP1=2
RCC.DIVP1Freq_Value=160000000
RCC.DIVP2=2
RCC.DIVP2Freq_Value=160000000
RCC.DIVP3=2
RCC.DIVP3Freq_Value=96000000
RCC.DIVQ1=4
RCC.DIVQ1Freq_Value=80000000
RCC.DIVQ2=4
RCC.DIVQ2Freq_Value=80000000
RCC.DIVQ3=3
RCC.DIVQ3Freq_Value=64000000
RCC.DIVR1=2
RCC.DIVR1Freq_Value=160000000
RCC.DIVR2Freq_Value=160000000
RCC.DIVR3=3
RCC.DIVR3Freq_Value=64000000
RCC.EXTERNAL_CLOCK_VALUE=12288000
RCC.FDCANFreq_Value=80000000
RCC.FMCCLockSelection=RCC_FMCCLKSOURCE_PLL2
RCC.FMCFreq_Value=160000000
RCC.FamilyName=M
RCC.HCLK3ClockFreq_Value=160000000
RCC.HCLKFreq_Value=160000000
RCC.HPRE=RCC_HCLK_DIV1
RCC.HSE_VALUE=16000000
RCC.HSI48_VALUE=48000000
RCC.HSIDiv=RCC_PLLSAIDIVR_1
RCC.HSI_VALUE=64000000
RCC.I2C123CLockSelection=RCC_I2C123CLKSOURCE_D2PCLK1
RCC.I2C123Freq_Value=80000000
RCC.I2C4CLockSelection=RCC_I2C4CLKSOURCE_D3PCLK1
RCC.I2C4Freq_Value=80000000
RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CDCPRE,CDCPREFreq_Value,CDPPRE,CDPPRE1,CDPPRE2,CECCLockSelection,CECFreq_Value,CKPERFreq_Value,CKPERSourceSelection,CSI_VALUE,CortexFreq_Value,Cortex_Div,Cortex_DivARG,CpuClockFreq_Value,DAC1Freq_Value,DAC2Freq_Value,DFSDM2ACLkFreq_Value,DFSDM2Freq_Value,DFSDMACLkFreq_Value,DFSDMCLockSelection,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1,DIVP1Freq_Value,DIVP2,DIVP2Freq_Value,DIVP3,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,EXTERNAL_CLOCK_VALUE,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C123CLockSelection,I2C123Freq_Value,I2C4CLockSelection,I2C4Freq_Value,LPTIM1CLockSelection,LPTIM1Freq_Value,LPTIM2CLockSelection,LPTIM2Freq_Value,LPTIM345CLockSelection,LPTIM345Freq_Value,LPUART1CLockSelection,LPUART1Freq_Value,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RCC_MCO1Source,RCC_MCO2Source,RCC_MCODiv1,RCC_MCODiv2,RCC_RTC_Clock_Source_FROM_HSE,RNGCLockSelection,RNGFreq_Value,RTCFreq_Value,SAI1CLockSelection,SAI1Freq_Value,SAI2AFreq_Value,SAI2BCLockSelection,SAI2BFreq_Value,SDMMC1CLockSelection,SDMMCFreq_Value,SPDIFCLockSelection,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6CLockSelection,SPI6Freq_Value,SRDPPRE,SWPCLockSelection,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16CLockSelection,USART16Freq_Value,USART234578CLockSelection,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,WatchDogFreq_Value
RCC.LPTIM1CLockSelection=RCC_LPTIM1CLKSOURCE_D2PCLK1
RCC.LPTIM1Freq_Value=80000000
RCC.LPTIM2CLockSelection=RCC_LPTIM2CLKSOURCE_D3PCLK1
RCC.LPTIM2Freq_Value=80000000
RCC.LPTIM345CLockSelection=RCC_LPTIM3CLKSOURCE_D3PCLK1
RCC.LPTIM345Freq_Value=80000000
RCC.LPUART1CLockSelection=RCC_LPUART1CLKSOURCE_D3PCLK1
RCC.LPUART1Freq_Value=80000000
RCC.LSI_VALUE=32000
RCC.LTDCFreq_Value=64000000
RCC.MCO1PinFreq_Value=64000000
RCC.MCO2PinFreq_Value=160000000
RCC.PLL2FRACN=0
RCC.PLL3FRACN=0
RCC.PLLFRACN=0
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.QSPICLockSelection=RCC_OSPICLKSOURCE_D1HCLK
RCC.QSPIFreq_Value=160000000
RCC.RCC_MCO1Source=RCC_MCO1SOURCE_HSI
RCC.RCC_MCO2Source=RCC_MCO2SOURCE_SYSCLK
RCC.RCC_MCODiv1=RCC_MCODIV_1
RCC.RCC_MCODiv2=RCC_MCODIV_1
RCC.RCC_RTC_Clock_Source_FROM_HSE=RCC_RTCCLKSOURCE_HSE_DIV2
RCC.RNGCLockSelection=RCC_RNGCLKSOURCE_HSI48
RCC.RNGFreq_Value=48000000
RCC.RTCFreq_Value=32000
RCC.SAI1CLockSelection=RCC_SAI1CLKSOURCE_PLL
RCC.SAI1Freq_Value=80000000
RCC.SAI2AFreq_Value=80000000
RCC.SAI2BCLockSelection=RCC_SAI2BCLKSOURCE_PLL
RCC.SAI2BFreq_Value=80000000
RCC.SDMMC1CLockSelection=RCC_SDMMCCLKSOURCE_PLL2
RCC.SDMMCFreq_Value=160000000
RCC.SPDIFCLockSelection=RCC_SPDIFRXCLKSOURCE_PLL
RCC.SPDIFRXFreq_Value=80000000
RCC.SPI123CLockSelection=RCC_SPI123CLKSOURCE_PLL
RCC.SPI123Freq_Value=80000000
RCC.SPI45Freq_Value=80000000
RCC.SPI6CLockSelection=RCC_SPI6CLKSOURCE_D3PCLK1
RCC.SPI6Freq_Value=80000000
RCC.SRDPPRE=RCC_APB4_DIV2
RCC.SWPCLockSelection=RCC_SWPMI1CLKSOURCE_D2PCLK1
RCC.SWPMI1Freq_Value=80000000
RCC.SYSCLKFreq_VALUE=160000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.Spi45ClockSelection=RCC_SPI45CLKSOURCE_D2PCLK1
RCC.Tim1OutputFreq_Value=160000000
RCC.Tim2OutputFreq_Value=160000000
RCC.TraceFreq_Value=160000000
RCC.USART16CLockSelection=RCC_USART16910CLKSOURCE_D2PCLK2
RCC.USART16Freq_Value=80000000
RCC.USART234578CLockSelection=RCC_USART234578CLKSOURCE_D2PCLK1
RCC.USART234578Freq_Value=80000000
RCC.USBCLockSelection=RCC_USBCLKSOURCE_HSI48
RCC.USBFreq_Value=48000000
RCC.VCO1OutputFreq_Value=320000000
RCC.VCO2OutputFreq_Value=320000000
RCC.VCO3OutputFreq_Value=192000000
RCC.VCOInput1Freq_Value=16000000
RCC.VCOInput2Freq_Value=16000000
RCC.VCOInput3Freq_Value=16000000
RCC.WatchDogFreq_Value=32000
SH.FMC_A0.0=FMC_A0,13b-sda1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,13b-sda1
SH.FMC_A1.ConfNb=1
SH.FMC_A10.0=FMC_A10,13b-sda1
SH.FMC_A10.ConfNb=1
SH.FMC_A11.0=FMC_A11,13b-sda1
SH.FMC_A11.ConfNb=1
SH.FMC_A12.0=FMC_A12,13b-sda1
SH.FMC_A12.ConfNb=1
SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
SH.FMC_A14_BA0.ConfNb=1
SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
SH.FMC_A15_BA1.ConfNb=1
SH.FMC_A2.0=FMC_A2,13b-sda1
SH.FMC_A2.ConfNb=1
SH.FMC_A3.0=FMC_A3,13b-sda1
SH.FMC_A3.ConfNb=1
SH.FMC_A4.0=FMC_A4,13b-sda1
SH.FMC_A4.ConfNb=1
SH.FMC_A5.0=FMC_A5,13b-sda1
SH.FMC_A5.ConfNb=1
SH.FMC_A6.0=FMC_A6,13b-sda1
SH.FMC_A6.ConfNb=1
SH.FMC_A7.0=FMC_A7,13b-sda1
SH.FMC_A7.ConfNb=1
SH.FMC_A8.0=FMC_A8,13b-sda1
SH.FMC_A8.ConfNb=1
SH.FMC_A9.0=FMC_A9,13b-sda1
SH.FMC_A9.ConfNb=1
SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1
SH.FMC_D0_DA0.ConfNb=1
SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1
SH.FMC_D10_DA10.ConfNb=1
SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1
SH.FMC_D11_DA11.ConfNb=1
SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1
SH.FMC_D12_DA12.ConfNb=1
SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
SH.FMC_D13_DA13.ConfNb=1
SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1
SH.FMC_D14_DA14.ConfNb=1
SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1
SH.FMC_D15_DA15.ConfNb=1
SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1
SH.FMC_D1_DA1.ConfNb=1
SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1
SH.FMC_D2_DA2.ConfNb=1
SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1
SH.FMC_D3_DA3.ConfNb=1
SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1
SH.FMC_D4_DA4.ConfNb=1
SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1
SH.FMC_D5_DA5.ConfNb=1
SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
SH.FMC_D6_DA6.ConfNb=1
SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1
SH.FMC_D7_DA7.ConfNb=1
SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1
SH.FMC_D8_DA8.ConfNb=1
SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1
SH.FMC_D9_DA9.ConfNb=1
SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
SH.FMC_NBL0.ConfNb=1
SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1
SH.FMC_NBL1.ConfNb=1
SH.FMC_SDCLK.0=FMC_SDCLK,13b-sda1
SH.FMC_SDCLK.ConfNb=1
SH.FMC_SDNCAS.0=FMC_SDNCAS,13b-sda1
SH.FMC_SDNCAS.ConfNb=1
SH.FMC_SDNRAS.0=FMC_SDNRAS,13b-sda1
SH.FMC_SDNRAS.ConfNb=1
SH.FMC_SDNWE.0=FMC_SDNWE,13b-sda1
SH.FMC_SDNWE.ConfNb=1
STMicroelectronics.X-CUBE-TOUCHGFX.4.21.0.GraphicsJjApplication_Checked=false
STMicroelectronics.X-CUBE-TOUCHGFX.4.21.0_IsPackSelfContextualization=true
STMicroelectronics.X-CUBE-TOUCHGFX.4.21.0_SwParameter=ApplicationCcGraphicsJjApplication\:TouchGFXOoGenerator;
USART10.IPParameters=VirtualMode-Asynchronous
USART10.VirtualMode-Asynchronous=VM_ASYNC
USB_OTG_HS.IPParameters=VirtualMode-Device_Only_FS
USB_OTG_HS.VirtualMode-Device_Only_FS=Device_Only_FS
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
isbadioc=false

78
Software/FT23_Charger.launch
View File

@ -1,78 +0,0 @@
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<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.divby0" value="true"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.unaligned" value="false"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.haltonexception" value="true"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
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<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
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<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_allow_halt" value="false"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_signal_halt" value="false"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_max_halt_delay" value="false"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="140"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="C:\Users\max\STM32CubeIDE\workspace_1.4.0\FT23_Charger\Debug\st-link_gdbserver_log.txt"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="connect_under_reset"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.watchdog_config" value="none"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkenable_rtos" value="false"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkrestart_configurations" value="{&quot;fVersion&quot;:1,&quot;fItems&quot;:[{&quot;fDisplayName&quot;:&quot;Reset&quot;,&quot;fIsSuppressible&quot;:false,&quot;fResetAttribute&quot;:&quot;Software system reset&quot;,&quot;fResetStrategies&quot;:[{&quot;fDisplayName&quot;:&quot;Software system reset&quot;,&quot;fLaunchAttribute&quot;:&quot;system_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Hardware reset&quot;,&quot;fLaunchAttribute&quot;:&quot;hardware_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset hardware\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Core reset&quot;,&quot;fLaunchAttribute&quot;:&quot;core_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset core\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;None&quot;,&quot;fLaunchAttribute&quot;:&quot;no_reset&quot;,&quot;fGdbCommands&quot;:[],&quot;fCmdOptions&quot;:[&quot;-g&quot;]}],&quot;fGdbCommandGroup&quot;:{&quot;name&quot;:&quot;Additional commands&quot;,&quot;commands&quot;:[]},&quot;fStartApplication&quot;:true}]}"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.enableRtosProxy" value="false"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyCustomProperties" value=""/>
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriver" value="threadx"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverAuto" value="false"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverPort" value="cortex_m0"/>
<intAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyPort" value="60000"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="com.st.stm32cube.ide.mcu.debug.stlink"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/FT23_Charger.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="FT23_Charger"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1019471104"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/FT23_Charger"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;"/>
<stringAttribute key="process_factory_id" value="com.st.stm32cube.ide.mcu.debug.launch.HardwareDebugProcessFactory"/>
</launchConfiguration>

25
Software/FT25-Charger/.mxproject Normal file
View File

File diff suppressed because one or more lines are too long

37
Software/Core/Inc/main.h → Software/FT25-Charger/Core/Inc/main.h
View File

@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2022 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -58,32 +57,6 @@ void Error_Handler(void);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define STATUS_LED_1_Pin GPIO_PIN_6
#define STATUS_LED_1_GPIO_Port GPIOF
#define STATUS_LED_2_Pin GPIO_PIN_7
#define STATUS_LED_2_GPIO_Port GPIOF
#define Display_Reset_Pin GPIO_PIN_8
#define Display_Reset_GPIO_Port GPIOC
#define Display_Standby_Pin GPIO_PIN_10
#define Display_Standby_GPIO_Port GPIOC
#define Display_Left_Right_Pin GPIO_PIN_11
#define Display_Left_Right_GPIO_Port GPIOC
#define Display_Up_Down_Pin GPIO_PIN_12
#define Display_Up_Down_GPIO_Port GPIOC
#define Charger_CC_Status_Pin GPIO_PIN_9
#define Charger_CC_Status_GPIO_Port GPIOG
#define Charger_OT_Pin GPIO_PIN_11
#define Charger_OT_GPIO_Port GPIOG
#define Charger_LIM_Pin GPIO_PIN_12
#define Charger_LIM_GPIO_Port GPIOG
#define Charger_DC_FAIL_Pin GPIO_PIN_13
#define Charger_DC_FAIL_GPIO_Port GPIOG
#define Charger_Relay_Pin GPIO_PIN_14
#define Charger_Relay_GPIO_Port GPIOG
#define Charger_AC_Fail_Pin GPIO_PIN_4
#define Charger_AC_Fail_GPIO_Port GPIOB
#define Charger_Remote_Shutdown_Pin GPIO_PIN_5
#define Charger_Remote_Shutdown_GPIO_Port GPIOB
/* USER CODE BEGIN Private defines */

27
Software/Core/Inc/stm32h7xx_hal_conf.h → Software/FT25-Charger/Core/Inc/stm32h7xx_hal_conf.h
View File

@ -45,12 +45,13 @@
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
/* #define HAL_ETH_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_OTFDEC_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
#define HAL_SDRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_HRTIM_MODULE_ENABLED */
/* #define HAL_HSEM_MODULE_ENABLED */
@ -58,29 +59,29 @@
/* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_OPAMP_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_XSPI_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
#define HAL_LTDC_MODULE_ENABLED
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_XSPI_MODULE_ENABLED */
/* #define HAL_RAMECC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_SPI_MODULE_ENABLED */
/* #define HAL_SWPMI_MODULE_ENABLED */
/* #define HAL_TIM_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/* #define HAL_UART_MODULE_ENABLED */
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED
/* #define HAL_PCD_MODULE_ENABLED */
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
@ -106,7 +107,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
@ -165,7 +166,7 @@
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority */
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
#define USE_RTOS 0
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
@ -220,8 +221,8 @@
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
/* ########################### Ethernet Configuration ######################### */
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
#define ETH_TX_DESC_CNT 4U /* number of Ethernet Tx DMA descriptors */
#define ETH_RX_DESC_CNT 4U /* number of Ethernet Rx DMA descriptors */
#define ETH_MAC_ADDR0 (0x02UL)
#define ETH_MAC_ADDR1 (0x00UL)
@ -286,6 +287,10 @@
#include "stm32h7xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
#include "stm32h7xx_hal_eth_legacy.h"
#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32h7xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */

17
Software/Core/Inc/stm32h7xx_it.h → Software/FT25-Charger/Core/Inc/stm32h7xx_it.h
View File

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2022 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -56,12 +55,6 @@ void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void FDCAN1_IT0_IRQHandler(void);
void FDCAN1_IT1_IRQHandler(void);
void FMC_IRQHandler(void);
void FDCAN_CAL_IRQHandler(void);
void LTDC_IRQHandler(void);
void LTDC_ER_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */

470
Software/FT25-Charger/Core/Src/main.c Normal file
View File

@ -0,0 +1,470 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "string.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma location=0x30000000
ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
#pragma location=0x30000200
ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
#elif defined ( __CC_ARM ) /* MDK ARM Compiler */
__attribute__((at(0x30000000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
__attribute__((at(0x30000200))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
#elif defined ( __GNUC__ ) /* GNU Compiler */
ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */
ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */
#endif
ETH_TxPacketConfig TxConfig;
ETH_HandleTypeDef heth;
FDCAN_HandleTypeDef hfdcan1;
LTDC_HandleTypeDef hltdc;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MPU_Config(void);
static void MX_GPIO_Init(void);
static void MX_LTDC_Init(void);
static void MX_ETH_Init(void);
static void MX_FDCAN1_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MPU Configuration--------------------------------------------------------*/
MPU_Config();
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_LTDC_Init();
MX_ETH_Init();
MX_FDCAN1_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 9;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 3;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
RCC_OscInitStruct.PLL.PLLFRACN = 3072;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief ETH Initialization Function
* @param None
* @retval None
*/
static void MX_ETH_Init(void)
{
/* USER CODE BEGIN ETH_Init 0 */
/* USER CODE END ETH_Init 0 */
static uint8_t MACAddr[6];
/* USER CODE BEGIN ETH_Init 1 */
/* USER CODE END ETH_Init 1 */
heth.Instance = ETH;
MACAddr[0] = 0x00;
MACAddr[1] = 0x80;
MACAddr[2] = 0xE1;
MACAddr[3] = 0x00;
MACAddr[4] = 0x00;
MACAddr[5] = 0x00;
heth.Init.MACAddr = &MACAddr[0];
heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
heth.Init.TxDesc = DMATxDscrTab;
heth.Init.RxDesc = DMARxDscrTab;
heth.Init.RxBuffLen = 1524;
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
if (HAL_ETH_Init(&heth) != HAL_OK)
{
Error_Handler();
}
memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
/* USER CODE BEGIN ETH_Init 2 */
/* USER CODE END ETH_Init 2 */
}
/**
* @brief FDCAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_FDCAN1_Init(void)
{
/* USER CODE BEGIN FDCAN1_Init 0 */
/* USER CODE END FDCAN1_Init 0 */
/* USER CODE BEGIN FDCAN1_Init 1 */
/* USER CODE END FDCAN1_Init 1 */
hfdcan1.Instance = FDCAN1;
hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
hfdcan1.Init.AutoRetransmission = DISABLE;
hfdcan1.Init.TransmitPause = DISABLE;
hfdcan1.Init.ProtocolException = DISABLE;
hfdcan1.Init.NominalPrescaler = 16;
hfdcan1.Init.NominalSyncJumpWidth = 1;
hfdcan1.Init.NominalTimeSeg1 = 2;
hfdcan1.Init.NominalTimeSeg2 = 2;
hfdcan1.Init.DataPrescaler = 1;
hfdcan1.Init.DataSyncJumpWidth = 1;
hfdcan1.Init.DataTimeSeg1 = 1;
hfdcan1.Init.DataTimeSeg2 = 1;
hfdcan1.Init.MessageRAMOffset = 0;
hfdcan1.Init.StdFiltersNbr = 0;
hfdcan1.Init.ExtFiltersNbr = 0;
hfdcan1.Init.RxFifo0ElmtsNbr = 0;
hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxFifo1ElmtsNbr = 0;
hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxBuffersNbr = 0;
hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.TxEventsNbr = 0;
hfdcan1.Init.TxBuffersNbr = 0;
hfdcan1.Init.TxFifoQueueElmtsNbr = 0;
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FDCAN1_Init 2 */
/* USER CODE END FDCAN1_Init 2 */
}
/**
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
LTDC_LayerCfgTypeDef pLayerCfg1 = {0};
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
hltdc.Init.HorizontalSync = 7;
hltdc.Init.VerticalSync = 3;
hltdc.Init.AccumulatedHBP = 14;
hltdc.Init.AccumulatedVBP = 5;
hltdc.Init.AccumulatedActiveW = 654;
hltdc.Init.AccumulatedActiveH = 485;
hltdc.Init.TotalWidth = 660;
hltdc.Init.TotalHeigh = 487;
hltdc.Init.Backcolor.Blue = 0;
hltdc.Init.Backcolor.Green = 0;
hltdc.Init.Backcolor.Red = 0;
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
{
Error_Handler();
}
pLayerCfg.WindowX0 = 0;
pLayerCfg.WindowX1 = 0;
pLayerCfg.WindowY0 = 0;
pLayerCfg.WindowY1 = 0;
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
pLayerCfg.Alpha = 0;
pLayerCfg.Alpha0 = 0;
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
pLayerCfg.FBStartAdress = 0;
pLayerCfg.ImageWidth = 0;
pLayerCfg.ImageHeight = 0;
pLayerCfg.Backcolor.Blue = 0;
pLayerCfg.Backcolor.Green = 0;
pLayerCfg.Backcolor.Red = 0;
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
{
Error_Handler();
}
pLayerCfg1.WindowX0 = 0;
pLayerCfg1.WindowX1 = 0;
pLayerCfg1.WindowY0 = 0;
pLayerCfg1.WindowY1 = 0;
pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
pLayerCfg1.Alpha = 0;
pLayerCfg1.Alpha0 = 0;
pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
pLayerCfg1.FBStartAdress = 0;
pLayerCfg1.ImageWidth = 0;
pLayerCfg1.ImageHeight = 0;
pLayerCfg1.Backcolor.Blue = 0;
pLayerCfg1.Backcolor.Green = 0;
pLayerCfg1.Backcolor.Red = 0;
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN LTDC_Init 2 */
/* USER CODE END LTDC_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/* MPU Configuration */
void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct = {0};
/* Disables the MPU */
HAL_MPU_Disable();
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.BaseAddress = 0x0;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Enables the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

499
Software/FT25-Charger/Core/Src/stm32h7xx_hal_msp.c Normal file
View File

@ -0,0 +1,499 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/**
* @brief ETH MSP Initialization
* This function configures the hardware resources used in this example
* @param heth: ETH handle pointer
* @retval None
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(heth->Instance==ETH)
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ETH1MAC_CLK_ENABLE();
__HAL_RCC_ETH1TX_CLK_ENABLE();
__HAL_RCC_ETH1RX_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**ETH GPIO Configuration
PC1 ------> ETH_MDC
PA1 ------> ETH_REF_CLK
PA2 ------> ETH_MDIO
PA7 ------> ETH_CRS_DV
PC4 ------> ETH_RXD0
PC5 ------> ETH_RXD1
PB11 ------> ETH_TX_EN
PB12 ------> ETH_TXD0
PB13 ------> ETH_TXD1
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN ETH_MspInit 1 */
/* USER CODE END ETH_MspInit 1 */
}
}
/**
* @brief ETH MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param heth: ETH handle pointer
* @retval None
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
{
if(heth->Instance==ETH)
{
/* USER CODE BEGIN ETH_MspDeInit 0 */
/* USER CODE END ETH_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ETH1MAC_CLK_DISABLE();
__HAL_RCC_ETH1TX_CLK_DISABLE();
__HAL_RCC_ETH1RX_CLK_DISABLE();
/**ETH GPIO Configuration
PC1 ------> ETH_MDC
PA1 ------> ETH_REF_CLK
PA2 ------> ETH_MDIO
PA7 ------> ETH_CRS_DV
PC4 ------> ETH_RXD0
PC5 ------> ETH_RXD1
PB11 ------> ETH_TX_EN
PB12 ------> ETH_TXD0
PB13 ------> ETH_TXD1
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13);
/* USER CODE BEGIN ETH_MspDeInit 1 */
/* USER CODE END ETH_MspDeInit 1 */
}
}
/**
* @brief FDCAN MSP Initialization
* This function configures the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspInit 0 */
/* USER CODE END FDCAN1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_FDCAN_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**FDCAN1 GPIO Configuration
PA11 ------> FDCAN1_RX
PA12 ------> FDCAN1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN FDCAN1_MspInit 1 */
/* USER CODE END FDCAN1_MspInit 1 */
}
}
/**
* @brief FDCAN MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
{
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspDeInit 0 */
/* USER CODE END FDCAN1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_FDCAN_CLK_DISABLE();
/**FDCAN1 GPIO Configuration
PA11 ------> FDCAN1_RX
PA12 ------> FDCAN1_TX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
/* USER CODE BEGIN FDCAN1_MspDeInit 1 */
/* USER CODE END FDCAN1_MspDeInit 1 */
}
}
/**
* @brief LTDC MSP Initialization
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hltdc->Instance==LTDC)
{
/* USER CODE BEGIN LTDC_MspInit 0 */
/* USER CODE END LTDC_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
PeriphClkInitStruct.PLL3.PLL3M = 1;
PeriphClkInitStruct.PLL3.PLL3N = 4;
PeriphClkInitStruct.PLL3.PLL3P = 2;
PeriphClkInitStruct.PLL3.PLL3Q = 2;
PeriphClkInitStruct.PLL3.PLL3R = 6;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/**LTDC GPIO Configuration
PE4 ------> LTDC_B0
PE5 ------> LTDC_G0
PE6 ------> LTDC_G1
PI9 ------> LTDC_VSYNC
PI10 ------> LTDC_HSYNC
PI11 ------> LTDC_G6
PF10 ------> LTDC_DE
PC0 ------> LTDC_R5
PH2 ------> LTDC_R0
PH3 ------> LTDC_R1
PH4 ------> LTDC_G5
PA3 ------> LTDC_B5
PA5 ------> LTDC_R4
PA6 ------> LTDC_G2
PB0 ------> LTDC_R3
PB1 ------> LTDC_R6
PE11 ------> LTDC_G3
PE12 ------> LTDC_B4
PE14 ------> LTDC_CLK
PE15 ------> LTDC_R7
PB10 ------> LTDC_G4
PH8 ------> LTDC_R2
PD10 ------> LTDC_B3
PG8 ------> LTDC_G7
PC9 ------> LTDC_B2
PA10 ------> LTDC_B1
PB8 ------> LTDC_B6
PB9 ------> LTDC_B7
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_11
|GPIO_PIN_12|GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_8|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
/* USER CODE BEGIN LTDC_MspInit 1 */
/* USER CODE END LTDC_MspInit 1 */
}
}
/**
* @brief LTDC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
{
if(hltdc->Instance==LTDC)
{
/* USER CODE BEGIN LTDC_MspDeInit 0 */
/* USER CODE END LTDC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_LTDC_CLK_DISABLE();
/**LTDC GPIO Configuration
PE4 ------> LTDC_B0
PE5 ------> LTDC_G0
PE6 ------> LTDC_G1
PI9 ------> LTDC_VSYNC
PI10 ------> LTDC_HSYNC
PI11 ------> LTDC_G6
PF10 ------> LTDC_DE
PC0 ------> LTDC_R5
PH2 ------> LTDC_R0
PH3 ------> LTDC_R1
PH4 ------> LTDC_G5
PA3 ------> LTDC_B5
PA5 ------> LTDC_R4
PA6 ------> LTDC_G2
PB0 ------> LTDC_R3
PB1 ------> LTDC_R6
PE11 ------> LTDC_G3
PE12 ------> LTDC_B4
PE14 ------> LTDC_CLK
PE15 ------> LTDC_R7
PB10 ------> LTDC_G4
PH8 ------> LTDC_R2
PD10 ------> LTDC_B3
PG8 ------> LTDC_G7
PC9 ------> LTDC_B2
PA10 ------> LTDC_B1
PB8 ------> LTDC_B6
PB9 ------> LTDC_B7
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_11
|GPIO_PIN_12|GPIO_PIN_14|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_8);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_8
|GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_8);
/* USER CODE BEGIN LTDC_MspDeInit 1 */
/* USER CODE END LTDC_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

101
Software/Core/Src/stm32h7xx_it.c → Software/FT25-Charger/Core/Src/stm32h7xx_it.c
View File

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2022 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -56,9 +55,7 @@
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern FDCAN_HandleTypeDef hfdcan1;
extern SDRAM_HandleTypeDef hsdram1;
extern LTDC_HandleTypeDef hltdc;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
@ -75,7 +72,7 @@ void NMI_Handler(void)
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
@ -201,90 +198,6 @@ void SysTick_Handler(void)
/* please refer to the startup file (startup_stm32h7xx.s). */
/******************************************************************************/
/**
* @brief This function handles FDCAN1 interrupt 0.
*/
void FDCAN1_IT0_IRQHandler(void)
{
/* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
/* USER CODE END FDCAN1_IT0_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan1);
/* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
/* USER CODE END FDCAN1_IT0_IRQn 1 */
}
/**
* @brief This function handles FDCAN1 interrupt 1.
*/
void FDCAN1_IT1_IRQHandler(void)
{
/* USER CODE BEGIN FDCAN1_IT1_IRQn 0 */
/* USER CODE END FDCAN1_IT1_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan1);
/* USER CODE BEGIN FDCAN1_IT1_IRQn 1 */
/* USER CODE END FDCAN1_IT1_IRQn 1 */
}
/**
* @brief This function handles FMC global interrupt.
*/
void FMC_IRQHandler(void)
{
/* USER CODE BEGIN FMC_IRQn 0 */
/* USER CODE END FMC_IRQn 0 */
HAL_SDRAM_IRQHandler(&hsdram1);
/* USER CODE BEGIN FMC_IRQn 1 */
/* USER CODE END FMC_IRQn 1 */
}
/**
* @brief This function handles FDCAN calibration unit interrupt.
*/
void FDCAN_CAL_IRQHandler(void)
{
/* USER CODE BEGIN FDCAN_CAL_IRQn 0 */
/* USER CODE END FDCAN_CAL_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan1);
/* USER CODE BEGIN FDCAN_CAL_IRQn 1 */
/* USER CODE END FDCAN_CAL_IRQn 1 */
}
/**
* @brief This function handles LTDC global interrupt.
*/
void LTDC_IRQHandler(void)
{
/* USER CODE BEGIN LTDC_IRQn 0 */
/* USER CODE END LTDC_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
/* USER CODE BEGIN LTDC_IRQn 1 */
/* USER CODE END LTDC_IRQn 1 */
}
/**
* @brief This function handles LTDC Error global Interrupt.
*/
void LTDC_ER_IRQHandler(void)
{
/* USER CODE BEGIN LTDC_ER_IRQn 0 */
/* USER CODE END LTDC_ER_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
/* USER CODE BEGIN LTDC_ER_IRQn 1 */
/* USER CODE END LTDC_ER_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

110
Software/Core/Src/syscalls.c → Software/FT25-Charger/Core/Src/syscalls.c
View File

@ -1,8 +1,8 @@
/**
******************************************************************************
* @file syscalls.c
* @author Auto-generated by STM32CubeIDE
* @brief STM32CubeIDE Minimal System calls file
* @author Auto-generated by STM32CubeMX
* @brief Minimal System calls file
*
* For more information about which c-functions
* need which of these lowlevel functions
@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2020-2024 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -48,109 +47,130 @@ void initialise_monitor_handles()
int _getpid(void)
{
return 1;
return 1;
}
int _kill(int pid, int sig)
{
errno = EINVAL;
return -1;
(void)pid;
(void)sig;
errno = EINVAL;
return -1;
}
void _exit (int status)
{
_kill(status, -1);
while (1) {} /* Make sure we hang here */
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
int DataIdx;
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
return len;
return len;
}
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
int DataIdx;
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
__io_putchar(*ptr++);
}
return len;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
__io_putchar(*ptr++);
}
return len;
}
int _close(int file)
{
return -1;
(void)file;
return -1;
}
int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _isatty(int file)
{
return 1;
(void)file;
return 1;
}
int _lseek(int file, int ptr, int dir)
{
return 0;
(void)file;
(void)ptr;
(void)dir;
return 0;
}
int _open(char *path, int flags, ...)
{
/* Pretend like we always fail */
return -1;
(void)path;
(void)flags;
/* Pretend like we always fail */
return -1;
}
int _wait(int *status)
{
errno = ECHILD;
return -1;
(void)status;
errno = ECHILD;
return -1;
}
int _unlink(char *name)
{
errno = ENOENT;
return -1;
(void)name;
errno = ENOENT;
return -1;
}
int _times(struct tms *buf)
{
return -1;
(void)buf;
return -1;
}
int _stat(char *file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _link(char *old, char *new)
{
errno = EMLINK;
return -1;
(void)old;
(void)new;
errno = EMLINK;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
errno = EAGAIN;
return -1;
}
int _execve(char *name, char **argv, char **env)
{
errno = ENOMEM;
return -1;
(void)name;
(void)argv;
(void)env;
errno = ENOMEM;
return -1;
}

15
Software/Core/Src/sysmem.c → Software/FT25-Charger/Core/Src/sysmem.c
View File

@ -1,8 +1,8 @@
/**
******************************************************************************
* @file sysmem.c
* @author Generated by STM32CubeIDE
* @brief STM32CubeIDE System Memory calls file
* @author Generated by STM32CubeMX
* @brief System Memory calls file
*
* For more information about which C functions
* need which of these lowlevel functions
@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/

31
Software/Core/Src/system_stm32h7xx.c → Software/FT25-Charger/Core/Src/system_stm32h7xx.c
View File

@ -46,6 +46,7 @@
#include "stm32h7xx.h"
#include <math.h>
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
@ -93,14 +94,14 @@
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
This value must be a multiple of 0x400. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
This value must be a multiple of 0x400. */
#endif /* VECT_TAB_SRAM */
#else
/*!< Uncomment the following line if you need to relocate your vector Table
@ -108,14 +109,14 @@
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
This value must be a multiple of 0x400. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
This value must be a multiple of 0x400. */
#endif /* VECT_TAB_SRAM */
#endif /* DUAL_CORE && CORE_CM4 */
#endif /* USER_VECT_TAB_ADDRESS */
@ -187,7 +188,7 @@ void SystemInit (void)
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Set HSION bit */
@ -198,12 +199,12 @@ void SystemInit (void)
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
#if defined(D3_SRAM_BASE)
@ -261,10 +262,10 @@ void SystemInit (void)
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
#endif
#endif /* STM32H7_DEV_ID */
#if defined (DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
@ -284,7 +285,6 @@ void SystemInit (void)
#endif /* USER_VECT_TAB_ADDRESS */
#else
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
@ -298,7 +298,6 @@ void SystemInit (void)
#endif /* USER_VECT_TAB_ADDRESS */
#endif /*DUAL_CORE && CORE_CM4*/
}
/**

0
Software/Drivers/CMSIS/Include/cmsis_armcc.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/cmsis_armcc.h
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0
Software/Drivers/CMSIS/Include/cmsis_armclang.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/cmsis_armclang.h
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0
Software/Drivers/CMSIS/Include/cmsis_armclang_ltm.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h
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0
Software/Drivers/CMSIS/Include/cmsis_compiler.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/cmsis_compiler.h
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0
Software/Drivers/CMSIS/Include/cmsis_gcc.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/cmsis_gcc.h
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0
Software/Drivers/CMSIS/Include/cmsis_iccarm.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/cmsis_iccarm.h
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0
Software/Drivers/CMSIS/Include/cmsis_version.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/cmsis_version.h
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0
Software/Drivers/CMSIS/Include/core_armv81mml.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_armv81mml.h
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0
Software/Drivers/CMSIS/Include/core_armv8mbl.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_armv8mbl.h
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0
Software/Drivers/CMSIS/Include/core_armv8mml.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_armv8mml.h
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0
Software/Drivers/CMSIS/Include/core_cm0.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm0.h
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0
Software/Drivers/CMSIS/Include/core_cm0plus.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm0plus.h
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0
Software/Drivers/CMSIS/Include/core_cm1.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm1.h
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0
Software/Drivers/CMSIS/Include/core_cm23.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm23.h
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0
Software/Drivers/CMSIS/Include/core_cm3.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm3.h
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0
Software/Drivers/CMSIS/Include/core_cm33.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm33.h
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0
Software/Drivers/CMSIS/Include/core_cm35p.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm35p.h
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0
Software/Drivers/CMSIS/Include/core_cm4.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm4.h
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0
Software/Drivers/CMSIS/Include/core_cm7.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_cm7.h
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0
Software/Drivers/CMSIS/Include/core_sc000.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_sc000.h
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0
Software/Drivers/CMSIS/Include/core_sc300.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/core_sc300.h
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0
Software/Drivers/CMSIS/Include/mpu_armv7.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/mpu_armv7.h
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0
Software/Drivers/CMSIS/Include/mpu_armv8.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/mpu_armv8.h
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0
Software/Drivers/CMSIS/Include/tz_context.h → Software/FT25-Charger/Drivers/CMSIS/Core/Include/tz_context.h
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58
Software/FT25-Charger/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c Normal file
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@ -0,0 +1,58 @@
/******************************************************************************
* @file main_s.c
* @brief Code template for secure main function
* @version V1.1.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Use CMSE intrinsics */
#include <arm_cmse.h>
#include "RTE_Components.h"
#include CMSIS_device_header
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (0x200000U)
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}

200
Software/FT25-Charger/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c Normal file
View File

@ -0,0 +1,200 @@
/******************************************************************************
* @file tz_context.c
* @brief Context Management for Armv8-M TrustZone - Sample implementation
* @version V1.1.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2016-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "tz_context.h"
/// Number of process slots (threads may call secure library code)
#ifndef TZ_PROCESS_STACK_SLOTS
#define TZ_PROCESS_STACK_SLOTS 8U
#endif
/// Stack size of the secure library code
#ifndef TZ_PROCESS_STACK_SIZE
#define TZ_PROCESS_STACK_SIZE 256U
#endif
typedef struct {
uint32_t sp_top; // stack space top
uint32_t sp_limit; // stack space limit
uint32_t sp; // current stack pointer
} stack_info_t;
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_InitContextSystem_S (void) {
uint32_t n;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
ProcessStackInfo[n].sp = 0U;
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
}
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
ProcessStackFreeSlot = 0U;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
// Privileged Thread Mode using PSP
__set_CONTROL(0x02U);
return 1U; // Success
}
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
__attribute__((cmse_nonsecure_entry))
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
uint32_t slot;
(void)module; // Ignore (fixed Stack size)
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
return 0U; // No slot available
}
slot = ProcessStackFreeSlot;
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
return (slot + 1U);
}
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
ProcessStackInfo[slot].sp = 0U;
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
ProcessStackFreeSlot = slot;
return 1U; // Success
}
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
// Setup process stack pointer and stack limit
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
__set_PSP (ProcessStackInfo[slot].sp);
return 1U; // Success
}
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
uint32_t slot;
uint32_t sp;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
sp = __get_PSP();
if ((sp < ProcessStackInfo[slot].sp_limit) ||
(sp > ProcessStackInfo[slot].sp_top)) {
return 0U; // SP out of range
}
ProcessStackInfo[slot].sp = sp;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
return 1U; // Success
}

547
Software/FT25-Charger/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h Normal file
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@ -0,0 +1,547 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.3
* @date 15. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1))
#define __ARM_ARCH_7A__ 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE __forceinline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ########################## Core Instruction Access ######################### */
/**
\brief No Operation
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
*/
#define __WFI __wfi
/**
\brief Wait For Event
*/
#define __WFE __wfe
/**
\brief Send Event
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/**
\brief Count leading zeros
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/* ########################### Core Function Access ########################### */
/**
\brief Get FPSCR (Floating Point Status/Control)
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR (Floating Point Status/Control)
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/** \brief Get CPSR (Current Program Status Register)
\return CPSR Register value
*/
__STATIC_INLINE uint32_t __get_CPSR(void)
{
register uint32_t __regCPSR __ASM("cpsr");
return(__regCPSR);
}
/** \brief Set CPSR (Current Program Status Register)
\param [in] cpsr CPSR value to set
*/
__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
{
register uint32_t __regCPSR __ASM("cpsr");
__regCPSR = cpsr;
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_INLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
{
MOV r1, lr
MSR CPSR_C, r0
BX r1
}
/** \brief Get Stack Pointer
\return Stack Pointer
*/
__STATIC_INLINE __ASM uint32_t __get_SP(void)
{
MOV r0, sp
BX lr
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
{
MOV sp, r0
BX lr
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYSStack Pointer
*/
__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
{
ARM
PRESERVE8
MRS R1, CPSR
CPS #0x1F ;no effect in USR mode
MOV R0, SP
MSR CPSR_c, R1 ;no effect in USR mode
ISB
BX LR
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
{
ARM
PRESERVE8
MRS R1, CPSR
CPS #0x1F ;no effect in USR mode
MOV SP, R0
MSR CPSR_c, R1 ;no effect in USR mode
ISB
BX LR
}
/** \brief Get FPEXC (Floating Point Exception Control Register)
\return Floating Point Exception Control Register value
*/
__STATIC_INLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpexc __ASM("fpexc");
return(__regfpexc);
#else
return(0);
#endif
}
/** \brief Set FPEXC (Floating Point Exception Control Register)
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpexc __ASM("fpexc");
__regfpexc = (fpexc);
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
#define __get_CP64(cp, op1, Rt, CRm) \
do { \
uint32_t ltmp, htmp; \
__ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
(Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
} while(0)
#define __set_CP64(cp, op1, Rt, CRm) \
do { \
const uint64_t tmp = (Rt); \
const uint32_t ltmp = (uint32_t)(tmp); \
const uint32_t htmp = (uint32_t)(tmp >> 32U); \
__ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
} while(0)
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE __ASM void __FPU_Enable(void)
{
ARM
//Permit access to VFP/NEON, registers by modifying CPACR
MRC p15,0,R1,c1,c0,2
ORR R1,R1,#0x00F00000
MCR p15,0,R1,c1,c0,2
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
ISB
//Enable VFP/NEON
VMRS R1,FPEXC
ORR R1,R1,#0x40000000
VMSR FPEXC,R1
//Initialise VFP/NEON registers to 0
MOV R2,#0
//Initialise D16 registers to 0
VMOV D0, R2,R2
VMOV D1, R2,R2
VMOV D2, R2,R2
VMOV D3, R2,R2
VMOV D4, R2,R2
VMOV D5, R2,R2
VMOV D6, R2,R2
VMOV D7, R2,R2
VMOV D8, R2,R2
VMOV D9, R2,R2
VMOV D10,R2,R2
VMOV D11,R2,R2
VMOV D12,R2,R2
VMOV D13,R2,R2
VMOV D14,R2,R2
VMOV D15,R2,R2
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
//Initialise D32 registers to 0
VMOV D16,R2,R2
VMOV D17,R2,R2
VMOV D18,R2,R2
VMOV D19,R2,R2
VMOV D20,R2,R2
VMOV D21,R2,R2
VMOV D22,R2,R2
VMOV D23,R2,R2
VMOV D24,R2,R2
VMOV D25,R2,R2
VMOV D26,R2,R2
VMOV D27,R2,R2
VMOV D28,R2,R2
VMOV D29,R2,R2
VMOV D30,R2,R2
VMOV D31,R2,R2
ENDIF
//Initialise FPSCR to a known state
VMRS R1,FPSCR
LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AND R1,R1,R2
VMSR FPSCR,R1
BX LR
}
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.1.1
* @date 15. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCLANG_H
#define __CMSIS_ARMCLANG_H
#pragma clang system_header /* treat file as system include file */
#ifndef __ARM_COMPAT_H
#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE __attribute__((always_inline))
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
/* ########################## Core Instruction Access ######################### */
/**
\brief No Operation
*/
#define __NOP __builtin_arm_nop
/**
\brief Wait For Interrupt
*/
#define __WFI __builtin_arm_wfi
/**
\brief Wait For Event
*/
#define __WFE __builtin_arm_wfe
/**
\brief Send Event
*/
#define __SEV __builtin_arm_sev
/**
\brief Instruction Synchronization Barrier
*/
#define __ISB() do {\
__schedule_barrier();\
__builtin_arm_isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
*/
#define __DSB() do {\
__schedule_barrier();\
__builtin_arm_dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
*/
#define __DMB() do {\
__schedule_barrier();\
__builtin_arm_dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV(value) __builtin_bswap32(value)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV16(value) __ROR(__REV(value), 16)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REVSH(value) (int16_t)__builtin_bswap16(value)
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
op2 %= 32U;
if (op2 == 0U)
{
return op1;
}
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __builtin_arm_rbit
/**
\brief Count leading zeros
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
{
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
__builtin_clz(0) is undefined behaviour, so handle this case specially.
This guarantees ARM-compatible results if happening to compile on a non-ARM
target, and ensures the compiler doesn't decide to activate any
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
{
return 32U;
}
return __builtin_clz(value);
}
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB (uint8_t)__builtin_arm_ldrex
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH (uint16_t)__builtin_arm_ldrex
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW (uint32_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB (uint32_t)__builtin_arm_strex
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH (uint32_t)__builtin_arm_strex
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW (uint32_t)__builtin_arm_strex
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __builtin_arm_clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __builtin_arm_ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __builtin_arm_usat
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
#define __QADD8 __builtin_arm_qadd8
#define __QSUB8 __builtin_arm_qsub8
#define __QADD16 __builtin_arm_qadd16
#define __SHADD16 __builtin_arm_shadd16
#define __QSUB16 __builtin_arm_qsub16
#define __SHSUB16 __builtin_arm_shsub16
#define __QASX __builtin_arm_qasx
#define __SHASX __builtin_arm_shasx
#define __QSAX __builtin_arm_qsax
#define __SHSAX __builtin_arm_shsax
#define __SXTB16 __builtin_arm_sxtb16
#define __SMUAD __builtin_arm_smuad
#define __SMUADX __builtin_arm_smuadx
#define __SMLAD __builtin_arm_smlad
#define __SMLADX __builtin_arm_smladx
#define __SMLALD __builtin_arm_smlald
#define __SMLALDX __builtin_arm_smlaldx
#define __SMUSD __builtin_arm_smusd
#define __SMUSDX __builtin_arm_smusdx
#define __SMLSDX __builtin_arm_smlsdx
__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#endif /* (__ARM_FEATURE_DSP == 1) */
/* ########################### Core Function Access ########################### */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
#define __get_FPSCR __builtin_arm_get_fpscr
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
#define __set_FPSCR __builtin_arm_set_fpscr
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP()
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr()
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV %1, sp \n"
"MSR cpsr_c, %0 \n" // no effect in USR mode
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
);
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV sp, %1 \n"
"MSR cpsr_c, %0 \n" // no effect in USR mode
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
);
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE void __FPU_Enable(void)
{
__ASM volatile(
//Permit access to VFP/NEON, registers by modifying CPACR
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
" ISB \n"
//Enable VFP/NEON
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
//Initialise VFP/NEON registers to 0
" MOV R2,#0 \n"
//Initialise D16 registers to 0
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#if __ARM_NEON == 1
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
//Initialise FPSCR to a known state
" VMRS R1,FPSCR \n"
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R1,R1,R2 \n"
" VMSR FPSCR,R1 "
: : : "cc", "r1", "r2"
);
}
#endif /* __CMSIS_ARMCLANG_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.2
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include "cmsis_iccarm.h"
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef CMSIS_DEPRECATED
#warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
#define CMSIS_DEPRECATED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_cp15.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.1
* @date 07. Sep 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_CP15_H
#define __CMSIS_CP15_H
/** \brief Get ACTLR
\return Auxiliary Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 1);
return(result);
}
/** \brief Set ACTLR
\param [in] actlr Auxiliary Control value to set
*/
__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
{
__set_CP(15, 0, actlr, 1, 0, 1);
}
/** \brief Get CPACR
\return Coprocessor Access Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 2);
return result;
}
/** \brief Set CPACR
\param [in] cpacr Coprocessor Access Control value to set
*/
__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
{
__set_CP(15, 0, cpacr, 1, 0, 2);
}
/** \brief Get DFSR
\return Data Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 0);
return result;
}
/** \brief Set DFSR
\param [in] dfsr Data Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
{
__set_CP(15, 0, dfsr, 5, 0, 0);
}
/** \brief Get IFSR
\return Instruction Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 1);
return result;
}
/** \brief Set IFSR
\param [in] ifsr Instruction Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
{
__set_CP(15, 0, ifsr, 5, 0, 1);
}
/** \brief Get ISR
\return Interrupt Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_ISR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 1, 0);
return result;
}
/** \brief Get CBAR
\return Configuration Base Address register value
*/
__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
{
uint32_t result;
__get_CP(15, 4, result, 15, 0, 0);
return result;
}
/** \brief Get TTBR0
This function returns the value of the Translation Table Base Register 0.
\return Translation Table Base Register 0 value
*/
__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
{
uint32_t result;
__get_CP(15, 0, result, 2, 0, 0);
return result;
}
/** \brief Set TTBR0
This function assigns the given value to the Translation Table Base Register 0.
\param [in] ttbr0 Translation Table Base Register 0 value to set
*/
__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
{
__set_CP(15, 0, ttbr0, 2, 0, 0);
}
/** \brief Get DACR
This function returns the value of the Domain Access Control Register.
\return Domain Access Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 3, 0, 0);
return result;
}
/** \brief Set DACR
This function assigns the given value to the Domain Access Control Register.
\param [in] dacr Domain Access Control Register value to set
*/
__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
{
__set_CP(15, 0, dacr, 3, 0, 0);
}
/** \brief Set SCTLR
This function assigns the given value to the System Control Register.
\param [in] sctlr System Control Register value to set
*/
__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
{
__set_CP(15, 0, sctlr, 1, 0, 0);
}
/** \brief Get SCTLR
\return System Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 0);
return result;
}
/** \brief Set ACTRL
\param [in] actrl Auxiliary Control Register value to set
*/
__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
{
__set_CP(15, 0, actrl, 1, 0, 1);
}
/** \brief Get ACTRL
\return Auxiliary Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 1);
return result;
}
/** \brief Get MPIDR
This function returns the value of the Multiprocessor Affinity Register.
\return Multiprocessor Affinity Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
{
uint32_t result;
__get_CP(15, 0, result, 0, 0, 5);
return result;
}
/** \brief Get VBAR
This function returns the value of the Vector Base Address Register.
\return Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 0);
return result;
}
/** \brief Set VBAR
This function assigns the given value to the Vector Base Address Register.
\param [in] vbar Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
{
__set_CP(15, 0, vbar, 12, 0, 0);
}
/** \brief Get MVBAR
This function returns the value of the Monitor Vector Base Address Register.
\return Monitor Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 1);
return result;
}
/** \brief Set MVBAR
This function assigns the given value to the Monitor Vector Base Address Register.
\param [in] mvbar Monitor Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
{
__set_CP(15, 0, mvbar, 12, 0, 1);
}
#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
defined(DOXYGEN)
/** \brief Set CNTFRQ
This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\param [in] value CNTFRQ Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
{
__set_CP(15, 0, value, 14, 0, 0);
}
/** \brief Get CNTFRQ
This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\return CNTFRQ Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 0 , 0);
return result;
}
/** \brief Set CNTP_TVAL
This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
\param [in] value CNTP_TVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 0);
}
/** \brief Get CNTP_TVAL
This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
\return CNTP_TVAL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 0);
return result;
}
/** \brief Get CNTPCT
This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
\return CNTPCT Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
{
uint64_t result;
__get_CP64(15, 0, result, 14);
return result;
}
/** \brief Set CNTP_CVAL
This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\param [in] value CNTP_CVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
{
__set_CP64(15, 2, value, 14);
}
/** \brief Get CNTP_CVAL
This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\return CNTP_CVAL Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
{
uint64_t result;
__get_CP64(15, 2, result, 14);
return result;
}
/** \brief Set CNTP_CTL
This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
\param [in] value CNTP_CTL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 1);
}
/** \brief Get CNTP_CTL register
\return CNTP_CTL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 1);
return result;
}
#endif
/** \brief Set TLBIALL
TLB Invalidate All
*/
__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
{
__set_CP(15, 0, value, 8, 7, 0);
}
/** \brief Set BPIALL.
Branch Predictor Invalidate All
*/
__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 6);
}
/** \brief Set ICIALLU
Instruction Cache Invalidate All
*/
__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 0);
}
/** \brief Set DCCMVAC
Data cache clean
*/
__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 10, 1);
}
/** \brief Set DCIMVAC
Data cache invalidate
*/
__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 6, 1);
}
/** \brief Set DCCIMVAC
Data cache clean and invalidate
*/
__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 14, 1);
}
/** \brief Set CSSELR
*/
__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
{
// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
__set_CP(15, 2, value, 0, 0, 0);
}
/** \brief Get CSSELR
\return CSSELR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
__get_CP(15, 2, result, 0, 0, 0);
return result;
}
/** \brief Set CCSIDR
\deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
*/
CMSIS_DEPRECATED
__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
{
__set_CSSELR(value);
}
/** \brief Get CCSIDR
\return CCSIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
__get_CP(15, 1, result, 0, 0, 0);
return result;
}
/** \brief Get CLIDR
\return CLIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
__get_CP(15, 1, result, 0, 0, 1);
return result;
}
/** \brief Set DCISW
*/
__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
{
// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
__set_CP(15, 0, value, 7, 6, 2);
}
/** \brief Set DCCSW
*/
__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
{
// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
__set_CP(15, 0, value, 7, 10, 2);
}
/** \brief Set DCCISW
*/
__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
{
// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
__set_CP(15, 0, value, 7, 14, 2);
}
#endif

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/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.2.0
* @date 17. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GCC_H
#define __CMSIS_GCC_H
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE __attribute__((always_inline))
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/* ########################## Core Instruction Access ######################### */
/**
\brief No Operation
*/
#define __NOP() __ASM volatile ("nop")
/**
\brief Wait For Interrupt
*/
#define __WFI() __ASM volatile ("wfi")
/**
\brief Wait For Event
*/
#define __WFE() __ASM volatile ("wfe")
/**
\brief Send Event
*/
#define __SEV() __ASM volatile ("sev")
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__STATIC_FORCEINLINE void __ISB(void)
{
__ASM volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
}
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return result;
#endif
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
return result;
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (int16_t)__builtin_bswap16(value);
#else
int16_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return result;
#endif
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
op2 %= 32U;
if (op2 == 0U) {
return op1;
}
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
#else
int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
}
/**
\brief Count leading zeros
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
{
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
__builtin_clz(0) is undefined behaviour, so handle this case specially.
This guarantees ARM-compatible results if happening to compile on a non-ARM
target, and ensures the compiler doesn't decide to activate any
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
{
return 32U;
}
return __builtin_clz(value);
}
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
__STATIC_FORCEINLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
__extension__ \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/* ########################### Core Function Access ########################### */
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#endif
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
#endif
#else
(void)fpscr;
#endif
}
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr = __get_CPSR();
uint32_t result;
__ASM volatile(
"CPS #0x1F \n"
"MOV %0, sp " : "=r"(result) : : "memory"
);
__set_CPSR(cpsr);
__ISB();
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr = __get_CPSR();
__ASM volatile(
"CPS #0x1F \n"
"MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
);
__set_CPSR(cpsr);
__ISB();
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE void __FPU_Enable(void)
{
__ASM volatile(
//Permit access to VFP/NEON, registers by modifying CPACR
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
" ISB \n"
//Enable VFP/NEON
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
//Initialise VFP/NEON registers to 0
" MOV R2,#0 \n"
//Initialise D16 registers to 0
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
//Initialise FPSCR to a known state
" VMRS R1,FPSCR \n"
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R1,R1,R2 \n"
" VMSR FPSCR,R1 "
: : : "cc", "r1", "r2"
);
}
#pragma GCC diagnostic pop
#endif /* __CMSIS_GCC_H */

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@ -0,0 +1,571 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 15. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
// Copyright (c) 2018-2019 Arm Limited
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#pragma language=extended
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_7A__
/* Macro already defined */
#else
#if defined(__ARM7A__)
#define __ARM_ARCH_7A__ 1
#endif
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
/* Needs IAR language extensions */
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
/* Needs IAR language extensions */
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
/* Needs IAR language extensions */
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#if 0
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __enable_irq __iar_builtin_enable_interrupt
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#if __FPU_PRESENT
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#else
#define __get_FPSCR() ( 0 )
#endif
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE))
#define __get_CPSR() (__arm_rsr("CPSR"))
#define __get_mode() (__get_CPSR() & 0x1FU)
#define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE)))
#define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE)))
#define __get_FPEXC() (__arm_rsr("FPEXC"))
#define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
#define __get_CP(cp, op1, RT, CRn, CRm, op2) \
((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
#define __set_CP(cp, op1, RT, CRn, CRm, op2) \
(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
#define __get_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#define __SSAT __iar_builtin_SSAT
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#define __USAT __iar_builtin_USAT
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if !__FPU_PRESENT
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if !__FPU_PRESENT
#define __get_FPSCR() (0)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#define __NOP __no_operation
#define __get_xPSR __get_PSR
__IAR_FT void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
__IAR_FT uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
__IAR_FT void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
__ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
__ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
__IAR_FT uint32_t __get_SP_usr(void)
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV %1, sp \n"
"MSR cpsr_c, %2 \n" // no effect in USR mode
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
);
return result;
}
__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV sp, %1 \n"
"MSR cpsr_c, %2 \n" // no effect in USR mode
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
);
}
#define __get_mode() (__get_CPSR() & 0x1FU)
__STATIC_INLINE
void __FPU_Enable(void)
{
__ASM volatile(
//Permit access to VFP/NEON, registers by modifying CPACR
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
" ISB \n"
//Enable VFP/NEON
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
//Initialise VFP/NEON registers to 0
" MOV R2,#0 \n"
//Initialise D16 registers to 0
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#ifdef __ARM_ADVANCED_SIMD__
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
//Initialise FPSCR to a known state
" VMRS R1,FPSCR \n"
" MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R1,R1,R2 \n"
" VMSR FPSCR,R1 \n"
: : : "cc", "r1", "r2"
);
}
#undef __IAR_FT
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file irq_ctrl.h
* @brief Interrupt Controller API header file
* @version V1.0.0
* @date 23. June 2017
******************************************************************************/
/*
* Copyright (c) 2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef IRQ_CTRL_H_
#define IRQ_CTRL_H_
#include <stdint.h>
#ifndef IRQHANDLER_T
#define IRQHANDLER_T
/// Interrupt handler data type
typedef void (*IRQHandler_t) (void);
#endif
#ifndef IRQN_ID_T
#define IRQN_ID_T
/// Interrupt ID number data type
typedef int32_t IRQn_ID_t;
#endif
/* Interrupt mode bit-masks */
#define IRQ_MODE_TRIG_Pos (0U)
#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
#define IRQ_MODE_TYPE_Pos (3U)
#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
#define IRQ_MODE_DOMAIN_Pos (4U)
#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
#define IRQ_MODE_CPU_Pos (5U)
#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
/* Interrupt priority bit-masks */
#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
/// Initialize interrupt controller.
/// \return 0 on success, -1 on error.
int32_t IRQ_Initialize (void);
/// Register interrupt handler.
/// \param[in] irqn interrupt ID number
/// \param[in] handler interrupt handler function address
/// \return 0 on success, -1 on error.
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
/// Get the registered interrupt handler.
/// \param[in] irqn interrupt ID number
/// \return registered interrupt handler function address.
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
/// Enable interrupt.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_Enable (IRQn_ID_t irqn);
/// Disable interrupt.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_Disable (IRQn_ID_t irqn);
/// Get interrupt enable state.
/// \param[in] irqn interrupt ID number
/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
/// Configure interrupt request mode.
/// \param[in] irqn interrupt ID number
/// \param[in] mode mode configuration
/// \return 0 on success, -1 on error.
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
/// Get interrupt mode configuration.
/// \param[in] irqn interrupt ID number
/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
uint32_t IRQ_GetMode (IRQn_ID_t irqn);
/// Get ID number of current interrupt request (IRQ).
/// \return interrupt ID number.
IRQn_ID_t IRQ_GetActiveIRQ (void);
/// Get ID number of current fast interrupt request (FIQ).
/// \return interrupt ID number.
IRQn_ID_t IRQ_GetActiveFIQ (void);
/// Signal end of interrupt processing.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
/// Set interrupt pending flag.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_SetPending (IRQn_ID_t irqn);
/// Get interrupt pending flag.
/// \param[in] irqn interrupt ID number
/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
uint32_t IRQ_GetPending (IRQn_ID_t irqn);
/// Clear interrupt pending flag.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_ClearPending (IRQn_ID_t irqn);
/// Set interrupt priority value.
/// \param[in] irqn interrupt ID number
/// \param[in] priority interrupt priority value
/// \return 0 on success, -1 on error.
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
/// Get interrupt priority.
/// \param[in] irqn interrupt ID number
/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
/// Set priority masking threshold.
/// \param[in] priority priority masking threshold value
/// \return 0 on success, -1 on error.
int32_t IRQ_SetPriorityMask (uint32_t priority);
/// Get priority masking threshold
/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
uint32_t IRQ_GetPriorityMask (void);
/// Set priority grouping field split point
/// \param[in] bits number of MSB bits included in the group priority field comparison
/// \return 0 on success, -1 on error.
int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
/// Get priority grouping field split point
/// \return current number of MSB bits included in the group priority field comparison with
/// optional IRQ_PRIORITY_ERROR bit set.
uint32_t IRQ_GetPriorityGroupBits (void);
#endif // IRQ_CTRL_H_

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/**************************************************************************//**
* @file irq_ctrl_gic.c
* @brief Interrupt controller handling implementation for GIC
* @version V1.0.1
* @date 9. April 2018
******************************************************************************/
/*
* Copyright (c) 2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "RTE_Components.h"
#include CMSIS_device_header
#include "irq_ctrl.h"
#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
/// Number of implemented interrupt lines
#ifndef IRQ_GIC_LINE_COUNT
#define IRQ_GIC_LINE_COUNT (1020U)
#endif
static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
static uint32_t IRQ_ID0;
/// Initialize interrupt controller.
__WEAK int32_t IRQ_Initialize (void) {
uint32_t i;
for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
IRQTable[i] = (IRQHandler_t)NULL;
}
GIC_Enable();
return (0);
}
/// Register interrupt handler.
__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
IRQTable[irqn] = handler;
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get the registered interrupt handler.
__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
IRQHandler_t h;
// Ignore CPUID field (software generated interrupts)
irqn &= 0x3FFU;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
h = IRQTable[irqn];
} else {
h = (IRQHandler_t)0;
}
return (h);
}
/// Enable interrupt.
__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_EnableIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Disable interrupt.
__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_DisableIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get interrupt enable state.
__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
uint32_t enable;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
} else {
enable = 0U;
}
return (enable);
}
/// Configure interrupt request mode.
__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
uint32_t val;
uint8_t cfg;
uint8_t secure;
uint8_t cpu;
int32_t status = 0;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
// Check triggering mode
val = (mode & IRQ_MODE_TRIG_Msk);
if (val == IRQ_MODE_TRIG_LEVEL) {
cfg = 0x00U;
} else if (val == IRQ_MODE_TRIG_EDGE) {
cfg = 0x02U;
} else {
cfg = 0x00U;
status = -1;
}
// Check interrupt type
val = mode & IRQ_MODE_TYPE_Msk;
if (val != IRQ_MODE_TYPE_IRQ) {
status = -1;
}
// Check interrupt domain
val = mode & IRQ_MODE_DOMAIN_Msk;
if (val == IRQ_MODE_DOMAIN_NONSECURE) {
secure = 0U;
} else {
// Check security extensions support
val = GIC_DistributorInfo() & (1UL << 10U);
if (val != 0U) {
// Security extensions are supported
secure = 1U;
} else {
secure = 0U;
status = -1;
}
}
// Check interrupt CPU targets
val = mode & IRQ_MODE_CPU_Msk;
if (val == IRQ_MODE_CPU_ALL) {
cpu = 0xFFU;
} else {
cpu = val >> IRQ_MODE_CPU_Pos;
}
// Apply configuration if no mode error
if (status == 0) {
GIC_SetConfiguration((IRQn_Type)irqn, cfg);
GIC_SetTarget ((IRQn_Type)irqn, cpu);
if (secure != 0U) {
GIC_SetGroup ((IRQn_Type)irqn, secure);
}
}
}
return (status);
}
/// Get interrupt mode configuration.
__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
uint32_t mode;
uint32_t val;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
mode = IRQ_MODE_TYPE_IRQ;
// Get trigger mode
val = GIC_GetConfiguration((IRQn_Type)irqn);
if ((val & 2U) != 0U) {
// Corresponding interrupt is edge triggered
mode |= IRQ_MODE_TRIG_EDGE;
} else {
// Corresponding interrupt is level triggered
mode |= IRQ_MODE_TRIG_LEVEL;
}
// Get interrupt CPU targets
mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
} else {
mode = IRQ_MODE_ERROR;
}
return (mode);
}
/// Get ID number of current interrupt request (IRQ).
__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
IRQn_ID_t irqn;
uint32_t prio;
/* Dummy read to avoid GIC 390 errata 801120 */
GIC_GetHighPendingIRQ();
irqn = GIC_AcknowledgePending();
__DSB();
/* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */
/* The following workaround code is for a single-core system. It would be */
/* different in a multi-core system. */
/* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
/* so unlock it, otherwise service the interrupt as normal. */
/* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */
/* so will not occur here. */
if ((irqn == 0) || (irqn >= 0x3FE)) {
/* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
prio = GIC_GetPriority((IRQn_Type)0);
GIC_SetPriority ((IRQn_Type)0, prio);
__DSB();
if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
/* If the ID is 0, is active and has not been seen before */
IRQ_ID0 = 1U;
}
/* End of Workaround GIC 390 errata 733075 */
}
return (irqn);
}
/// Get ID number of current fast interrupt request (FIQ).
__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
return ((IRQn_ID_t)-1);
}
/// Signal end of interrupt processing.
__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
int32_t status;
IRQn_Type irq = (IRQn_Type)irqn;
irqn &= 0x3FFU;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_EndInterrupt (irq);
if (irqn == 0) {
IRQ_ID0 = 0U;
}
status = 0;
} else {
status = -1;
}
return (status);
}
/// Set interrupt pending flag.
__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_SetPendingIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get interrupt pending flag.
__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
uint32_t pending;
if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
} else {
pending = 0U;
}
return (pending & 1U);
}
/// Clear interrupt pending flag.
__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_ClearPendingIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Set interrupt priority value.
__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_SetPriority ((IRQn_Type)irqn, priority);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get interrupt priority.
__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
uint32_t priority;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
priority = GIC_GetPriority ((IRQn_Type)irqn);
} else {
priority = IRQ_PRIORITY_ERROR;
}
return (priority);
}
/// Set priority masking threshold.
__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
GIC_SetInterfacePriorityMask (priority);
return (0);
}
/// Get priority masking threshold
__WEAK uint32_t IRQ_GetPriorityMask (void) {
return GIC_GetInterfacePriorityMask();
}
/// Set priority grouping field split point
__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
int32_t status;
if (bits == IRQ_PRIORITY_Msk) {
bits = 7U;
}
if (bits < 8U) {
GIC_SetBinaryPoint (7U - bits);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get priority grouping field split point
__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
uint32_t bp;
bp = GIC_GetBinaryPoint() & 0x07U;
return (7U - bp);
}
#endif

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cmake_minimum_required (VERSION 3.6)
cmake_policy(SET CMP0077 NEW)
# The tests are assuming that MATRIX_CHECK is enabled when building
# CMSIS-DSP.
set(MATRIXCHECK ON)
set(FASTMATHCOMPUTATIONS OFF)
option(DUMPPATTERN "Dump test patterns when test is failing" ON)
option(CUSTOMIZE_TESTS "Enable customizations of tests" ON)
option(BASICMATH_TESTS "Enable Basic Math testing" ON)
option(COMPLEXMATH_TESTS "Enable Complex Math testing" ON)
option(CONTROLLER_TESTS "Enable Controller testing" ON)
option(FASTMATH_TESTS "Enable Fast Math testing" ON)
option(INTRINSICS_TESTS "Enable Intrinsics testing" ON)
option(FILTERING_TESTS "Enable Filtering testing" ON)
option(MATRIX_TESTS "Enable Matrix testing" ON)
option(STATISTICS_TESTS "Enable Statistics testing" ON)
option(SUPPORT_TESTS "Enable Support testing" ON)
option(TRANSFORM_TESTS "Enable Transform testing" ON)
project(DSP_Lib_TestSuite)
# Needed to find the config modules
list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/..)
set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../..)
file(GLOB MAIN "Common/src/*.c")
file(GLOB BASICMATH_TESTS_SRC "Common/src/basic_math_tests/*.c")
file(GLOB COMPLEXMATH_TESTS_SRC "Common/src/complex_math_tests/*.c")
file(GLOB CONTROLLER_TESTS_SRC "Common/src/controller_tests/*.c")
file(GLOB FASTMATH_TESTS_SRC "Common/src/fast_math_tests/*.c")
file(GLOB FILTERING_TESTS_SRC "Common/src/filtering_tests/*.c")
file(GLOB INTRINSINCS_TESTS_SRC "Common/src/intrinsics_tests/*.c")
file(GLOB MATRIX_TESTS_SRC "Common/src/matrix_tests/*.c")
file(GLOB STATISTICS_TESTS_SRC "Common/src/statistics_tests/*.c")
file(GLOB SUPPORT_TESTS_SRC "Common/src/support_tests/*.c")
file(GLOB TRANSFORM_TESTS_SRC "Common/src/transform_tests/*.c")
file(GLOB JTEST_MAIN "Common/JTest/src/*.c")
set(TESTSRC ${MAIN}
${BASICMATH_TESTS_SRC}
${COMPLEXMATH_TESTS_SRC}
${CONTROLLER_TESTS_SRC}
${FASTMATH_TESTS_SRC}
${FILTERING_TESTS_SRC}
${INTRINSINCS_TESTS_SRC}
${MATRIX_TESTS_SRC}
${STATISTICS_TESTS_SRC}
${SUPPORT_TESTS_SRC}
${TRANSFORM_TESTS_SRC}
${JTEST_MAIN}
)
set(JINCS
Common/JTest/inc
Common/JTest/inc/arr_desc
Common/inc/basic_math_tests
Common/inc/complex_math_tests
Common/inc/controller_tests
Common/inc/fast_math_tests
Common/inc/filtering_tests
Common/inc/intrinsics_tests
Common/inc/matrix_tests
Common/inc/statistics_tests
Common/inc/support_tests
Common/inc/transform_tests
)
add_subdirectory(../Source bin_dsp)
add_subdirectory(RefLibs bin_ref)
add_executable(DSP_Lib_TestSuite)
if (CUSTOMIZE_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE CUSTOMIZE_TESTS)
endif()
if (BASICMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_BASICMATH_TESTS)
endif()
if (COMPLEXMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_COMPLEXMATH_TESTS)
endif()
if (CONTROLLER_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_CONTROLLER_TESTS)
endif()
if (FASTMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FASTMATH_TESTS)
endif()
if (FILTERING_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FILTERING_TESTS)
endif()
if (INTRINSICS_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_INTRINSICS_TESTS)
endif()
if (MATRIX_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_MATRIX_TESTS)
endif()
if (STATISTICS_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_STATISTICS_TESTS)
endif()
if (SUPPORT_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_SUPPORT_TESTS)
endif()
if (TRANSFORM_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_TRANSFORM_TESTS)
endif()
if (DUMPPATTERN)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE DUMPPATTERN)
endif()
# Change behavior of configBoot for scatter file
set(TESTFRAMEWORK ON)
include(configBoot)
file(COPY ${ROOT}/CMSIS/DSP/Examples/ARM/boot/RTE_Components.h DESTINATION tempLink)
target_link_libraries(DSP_Lib_TestSuite PRIVATE CMSISDSP)
target_link_libraries(DSP_Lib_TestSuite PRIVATE DspRefLibs)
target_sources(DSP_Lib_TestSuite PRIVATE ${TESTSRC})
### Includes
target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc")
target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc/templates")
target_include_directories(DSP_Lib_TestSuite PRIVATE ${JINCS})

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#ifndef _ARR_DESC_H_
#define _ARR_DESC_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include <stdint.h>
#include <string.h> /* memset() */
#include "../util/util.h" /* CONCAT() */
/*--------------------------------------------------------------------------------*/
/* Type Definitions */
/*--------------------------------------------------------------------------------*/
/**
* Array-descriptor struct.
*/
typedef struct ARR_DESC_struct
{
void * data_ptr; /* Pointer to the array contents. */
int32_t element_count; /* Number of current elements. */
int32_t element_size; /* Size of current elements in bytes. */
int32_t underlying_size; /* Size of underlying array in bytes. */
} ARR_DESC_t;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Prefix of the array variable's name when creating an array and an array
* descriptor at the same time.
*/
#define ARR_DESC_ARR_PREFIX ARR_DESC_ARR_
/**
* Evaluate to the array variable's name when creating an array and an array
* descriptor at the same time.
*/
#define ARR_DESC_ARR_NAME(name) \
CONCAT(ARR_DESC_ARR_PREFIX, name)
/**
* Define an #ARR_DESC_t by itself.
*
* @note The user must supply an array to store the data used by the
* #ARR_DESC_t.
*/
#define ARR_DESC_INTERNAL_DEFINE(name, data_ptr, \
element_count, element_size) \
ARR_DESC_t name = { \
data_ptr, \
element_count, \
element_size, \
element_count * element_size \
} \
/**
* Define both an array and an #ARR_DESC_t that describes it.
*
* @note Use the #CURLY() macro for the content field; it provides the curly
* braces necessary for an array initialization.
*/
#define ARR_DESC_DEFINE(type, name, element_count, content) \
type ARR_DESC_ARR_NAME(name)[element_count] = content; \
ARR_DESC_INTERNAL_DEFINE(name, \
&ARR_DESC_ARR_NAME(name), \
element_count, \
sizeof(type)) /* Note the lacking semicolon */
/**
* Create a #ARR_DESC_t which refers to a subset of the data in another.
*
* The new #ARR_DESC_t shares the same underlying array as the aliased
* #ARR_DESC_t, but only describes a subset of the originals values.
*/
#define ARR_DESC_DEFINE_SUBSET(name, original, element_cnt) \
ARR_DESC_INTERNAL_DEFINE(name, \
&ARR_DESC_ARR_NAME(original), \
element_cnt, \
sizeof(ARR_DESC_ARR_NAME(original)[0]) \
) /* Note the lacking semicolon */
/**
* Creat an #ARR_DESC_t which points to the data in an existing array.
*
* @param start_idx Offset in array_ptr of first element.
* @param element_cnt Number of elements to include in the #ARR_DESC_t.
*
* @example
*
* float my_floats[4] = {0.0f, 1.0f, 2.0f, 3.0f};
*
* ARR_DESC_DEFINE_USING_ARR(my_arr_desc, my_floats, 1, 3);
*
* printf("Element 0: %f\n", ARR_DESC_ELT(float, 0, &my_arr_desc));
* printf("Element 1: %f\n", ARR_DESC_ELT(float, 1, &my_arr_desc));
*
* Outputs:
*
* Element 0: 1.000000
* Element 1: 2.000000
*
* @warning There are no checks in place to catch invalid start indices; This
* is left to the user.
*/
#define ARR_DESC_DEFINE_USING_ARR(type, name, array_ptr, start_idx, element_cnt) \
ARR_DESC_INTERNAL_DEFINE( \
name, \
(type *) (array_ptr + start_idx), \
element_cnt, \
sizeof(type) \
) /* Note the lacking semicolon*/
/**
* Declare an #ARR_DESC_t object.
*/
#define ARR_DESC_DECLARE(name) \
extern ARR_DESC_t name /* Note the lacking semicolon */
/**
* Evaluate to the number of bytes stored in the #ARR_DESC_t.
*/
#define ARR_DESC_BYTES(arr_desc_ptr) \
((arr_desc_ptr)->element_count * (arr_desc_ptr)->element_size)
/**
* Set the contents of #ARR_DESC_t to value.
*/
#define ARR_DESC_MEMSET(arr_desc_ptr, value, bytes) \
do \
{ \
memset((arr_desc_ptr)->data_ptr, \
value, \
BOUND(0, \
(arr_desc_ptr)->underlying_size, \
bytes) \
); \
} while (0)
/**
* Perform a memcpy of 'bytes' bytes from the source #ARR_DESC_t to the
* destination #ARR_DESC_t.
*/
#define ARR_DESC_MEMCPY(arr_desc_dest_ptr, arr_desc_src_ptr, bytes) \
do \
{ \
memcpy((arr_desc_dest_ptr)->data_ptr, \
(arr_desc_src_ptr)->data_ptr, \
BOUND(0, \
(arr_desc_dest_ptr)->underlying_size, \
bytes)); \
} while (0)
/**
* Evaluate to true if the source #ARR_DESC_t contents will fit into the
* destination #ARR_DESC_t and false otherwise.
*/
#define ARR_DESC_COPYABLE(arr_desc_dest_ptr, arr_desc_src_ptr) \
(ARR_DESC_BYTES(arr_desc_src_ptr) <= \
(arr_desc_dest_ptr)->underlying_size)
/**
* Copy all the data from the source #ARR_DESC_t to the destination
* #ARR_DESC_t.
*
* @note If the destination #ARR_DESC_t is too small to fit the source data the
* copy is aborted and nothing happens.
*/
#define ARR_DESC_COPY(arr_desc_dest_ptr, arr_desc_src_ptr) \
do \
{ \
if (ARR_DESC_COPYABLE(arr_desc_dest_ptr, \
arr_desc_src_ptr)) \
{ \
ARR_DESC_MEMCPY(arr_desc_dest_ptr, \
arr_desc_src_ptr, \
ARR_DESC_BYTES(arr_desc_src_ptr)); \
/* Update the properties*/ \
(arr_desc_dest_ptr)->element_count = \
(arr_desc_src_ptr)->element_count; \
(arr_desc_dest_ptr)->element_size = \
(arr_desc_src_ptr)->element_size; \
} \
} while (0)
/**
* Compare the data in two #ARR_DESC_t structs for the specified number of
* bytes.
*/
#define ARR_DESC_MEMCMP(arr_desc_ptr_a, arr_desc_ptr_b, bytes) \
memcmp((arr_desc_ptr_a)->data_ptr, \
(arr_desc_ptr_b)->data_ptr, \
bytes) /* Note the lacking semicolon */ \
/**
* Zero out the contents of the #ARR_DESC_t.
*/
#define ARR_DESC_ZERO(arr_desc_ptr) \
ARR_DESC_MEMSET(arr_desc_ptr, \
0, \
(arr_desc_ptr)->underlying_size)
/**
* Evaluate to the data address in #ARR_DESC_t at offset.
*/
#define ARR_DESC_DATA_ADDR(type, arr_desc_ptr, offset) \
((void*)(((type *) \
((arr_desc_ptr)->data_ptr)) \
+ offset))
/**
* Evaluate to the element in #ARR_DESC_t with type at idx.
*/
#define ARR_DESC_ELT(type, idx, arr_desc_ptr) \
(*((type *) ARR_DESC_DATA_ADDR(type, \
arr_desc_ptr, \
idx)))
#endif /* _ARR_DESC_H_ */

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#ifndef _JTEST_H_
#define _JTEST_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_fw.h"
#include "jtest_test.h"
#include "jtest_test_define.h"
#include "jtest_test_call.h"
#include "jtest_group.h"
#include "jtest_group_define.h"
#include "jtest_group_call.h"
#include "jtest_cycle.h"
#endif /* _JTEST_H_ */

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#ifndef _JTEST_CYCLE_H_
#define _JTEST_CYCLE_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_fw.h" /* JTEST_DUMP_STRF() */
#include "jtest_systick.h"
#include "jtest_util.h" /* STR() */
/*--------------------------------------------------------------------------------*/
/* Declare Module Variables */
/*--------------------------------------------------------------------------------*/
extern const char * JTEST_CYCLE_STRF;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Wrap the function call, fn_call, to count execution cycles and display the
* results.
*/
/* skipp function name + param
#define JTEST_COUNT_CYCLES(fn_call) \
do \
{ \
uint32_t __jtest_cycle_end_count; \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_SYSTICK_START(SysTick); \
\
fn_call; \
\
__jtest_cycle_end_count = \
JTEST_SYSTICK_VALUE(SysTick); \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \
STR(fn_call), \
(JTEST_SYSTICK_INITIAL_VALUE - \
__jtest_cycle_end_count)); \
} while (0)
*/
#ifndef ARMv7A
#define JTEST_COUNT_CYCLES(fn_call) \
do \
{ \
uint32_t __jtest_cycle_end_count; \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_SYSTICK_START(SysTick); \
\
fn_call; \
\
__jtest_cycle_end_count = \
JTEST_SYSTICK_VALUE(SysTick); \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \
(JTEST_SYSTICK_INITIAL_VALUE - \
__jtest_cycle_end_count)); \
} while (0)
#else
/* TODO */
#define JTEST_COUNT_CYCLES(fn_call) \
do \
{ \
fn_call; \
} while (0)
#endif
#endif /* _JTEST_CYCLE_H_ */

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#ifndef _JTEST_DEFINE_H_
#define _JTEST_DEFINE_H_
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Makes a symbol for use as a struct name. Names made this way have two parts;
* the first parts is a prefix common to all structs of that class. The second
* is a specifier which differs for each instance of that struct type.
*/
#define JTEST_STRUCT_NAME(prefix, specifier) \
CONCAT(prefix, specifier)
/**
* Define a struct with type with a name generated by #JTEST_STRUCT_NAME().
*/
#define JTEST_DEFINE_STRUCT(type, struct_name) \
type struct_name
/**
* Declare a struct with type with a name generated by #JTEST_STRUCT_NAME().
*/
#define JTEST_DECLARE_STRUCT(struct_definition) \
extern struct_definition
/**
* Define and initialize a struct (created with JTEST_DEFINE_STRUCT()) and
* initialize it with init_values.
*/
#define JTEST_INIT_STRUCT(struct_definition, init_values) \
struct_definition = { \
init_values \
}
#endif /* _JTEST_DEFINE_H_ */

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#ifndef _JTEST_FW_H_
#define _JTEST_FW_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include <stdint.h> /* int32_t */
#include <string.h> /* strcpy() */
#include <stdio.h> /* sprintf() */
#include "jtest_pf.h" /* Extend JTEST_FW_t with Pass/Fail data */
#include "jtest_group.h"
/*--------------------------------------------------------------------------------*/
/* Type Definitions */
/*--------------------------------------------------------------------------------*/
/**
* A struct used to interface with the Keil Debugger.
*/
typedef struct JTEST_FW_struct
{
/* Action Triggers: The Keil debugger monitors these values for changes. In
* response to a change, the debugger executes code on the host. */
volatile int32_t test_start;
volatile int32_t test_end;
volatile int32_t group_start;
volatile int32_t group_end;
volatile int32_t dump_str;
volatile int32_t dump_data;
volatile int32_t exit_fw;
JTEST_GROUP_t * current_group_ptr;
/* Buffers: The C-code cannot send strings and data directly to the
* debugging framework. Instead, the debugger can be told to read 128 byte
* (by default) chunks of memory. Data received in this manner requires
* post-processing to be legible.*/
char * str_buffer;
char * data_buffer;
/* Pass/Fail Data */
JTEST_PF_MEMBERS;
} JTEST_FW_t;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Default name for the JTEST_FW struct.
*
* Define your own if you want the variable containing the #JTEST_FW_t to have
* a different name.
*/
#ifndef JTEST_FW
#define JTEST_FW JTEST_FW
#endif
/**
* Default name for the JTEST_FW_STR_BUFFER.
*
* Define your own if you want the variable containing the char buffer to have
* a different name.
*/
#ifndef JTEST_FW_STR_BUFFER
#define JTEST_FW_STR_BUFFER JTEST_FW_STR_BUFFER
#endif
/**
* Size of the #JTEST_FW_t, output string-buffer.
*
* If you change this value, make sure the "dump_str_fn" and "dump_data_fn"
* functions in jtest_fns.ini uses the same size. If you aren't sure, read the
* documentation Keil Debugger Command 'DISPLAY'.
*/
#define JTEST_BUF_SIZE 256
/**
* The maximum number of bytes output at once using #JTEST_DUMP_STRF().
*/
#define JTEST_STR_MAX_OUTPUT_SIZE 128
/**
* The maximum number of block transimissions needed to send a string from a
* buffer with JTEST_BUF_SIZE.
*/
#define JTEST_STR_MAX_OUTPUT_SEGMENTS \
(JTEST_BUF_SIZE / JTEST_STR_MAX_OUTPUT_SIZE)
/**
* Initialize the JTEST framework.
*/
#define JTEST_INIT() \
do \
{ \
JTEST_FW.str_buffer = JTEST_FW_STR_BUFFER; \
} while (0)
/* Debugger Action-triggering Macros */
/*--------------------------------------------------------------------------------*/
/**
* Dispatch macro to trigger various actions in the Keil Debugger.
*/
#define JTEST_TRIGGER_ACTION(action_name) \
do \
{ \
action_name(); \
} while (0)
/**
* Trigger the "Test Start" action in the Keil Debugger.
*/
#define JTEST_ACT_TEST_START() \
JTEST_TRIGGER_ACTION(test_start)
/**
* Trigger the "Test End" action in the Keil Debugger.
*/
#define JTEST_ACT_TEST_END() \
JTEST_TRIGGER_ACTION(test_end)
/**
* Trigger the "Group Start" action in the Keil Debugger.
*/
#define JTEST_ACT_GROUP_START() \
JTEST_TRIGGER_ACTION(group_start)
/**
* Trigger the "Group End" action in the Keil Debugger.
*/
#define JTEST_ACT_GROUP_END() \
JTEST_TRIGGER_ACTION(group_end)
/**
* Fill the buffer named buf_name with value and dump it to the Keil debugger
* using action.
*/
#if defined(ARMv7A) || defined(FILEIO)
#define JTEST_ACT_DUMP(action, buf_name, value) \
do \
{ \
JTEST_CLEAR_BUFFER(buf_name); \
printf("%s",value); \
strcpy(JTEST_FW.buf_name, (value)); \
JTEST_TRIGGER_ACTION(action); \
} while (0)
#else
#define JTEST_ACT_DUMP(action, buf_name, value) \
do \
{ \
JTEST_CLEAR_BUFFER(buf_name); \
strcpy(JTEST_FW.buf_name, (value)); \
JTEST_TRIGGER_ACTION(action); \
} while (0)
#endif
/**
* Trigger the "Exit Framework" action in the Keil Debugger.
*/
#define JTEST_ACT_EXIT_FW() \
do \
{ \
JTEST_TRIGGER_ACTION(exit_fw); \
} while (0)
/* Buffer Manipulation Macros */
/*--------------------------------------------------------------------------------*/
/**
* Clear the JTEST_FW buffer with name buf_name.
*/
#define JTEST_CLEAR_BUFFER(buf_name) \
do \
{ \
memset(JTEST_FW.buf_name, 0, JTEST_BUF_SIZE); \
} while (0)
/**
* Clear the memory needed for the JTEST_FW's string buffer.
*/
#define JTEST_CLEAR_STR_BUFFER() \
JTEST_CLEAR_BUFFER(str_buffer)
/**
* Clear the memory needed for the JTEST_FW's data buffer.
*/
#define JTEST_CLEAR_DATA_BUFFER() \
JTEST_CLEAR_BUFFER(data_buffer)
/**
* Dump the given string to the Keil Debugger.
*/
#define JTEST_DUMP_STR(string) \
JTEST_ACT_DUMP(dump_str, str_buffer, string)
/**
* Dump a formatted string to the Keil Debugger.
*/
#if defined(ARMv7A) || defined(FILEIO)
#define JTEST_DUMP_STRF(format_str, ... ) \
do \
{ \
JTEST_CLEAR_STR_BUFFER(); \
sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \
printf("%s",JTEST_FW.str_buffer); \
jtest_dump_str_segments(); \
} while (0)
#else
#define JTEST_DUMP_STRF(format_str, ... ) \
do \
{ \
JTEST_CLEAR_STR_BUFFER(); \
sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \
jtest_dump_str_segments(); \
} while (0)
#endif
/* Pass/Fail Macros */
/*--------------------------------------------------------------------------------*/
/**
* Increment the number of passed tests in #JTEST_FW.
*/
#define JTEST_FW_INC_PASSED(amount) \
JTEST_PF_INC_PASSED(&JTEST_FW, amount)
/**
* Increment the number of passed tests in #JTEST_FW.
*/
#define JTEST_FW_INC_FAILED(amount) \
JTEST_PF_INC_FAILED(&JTEST_FW, amount)
/* Manipulating the Current Group */
/*--------------------------------------------------------------------------------*/
/**
* Evaluate to the current_group_ptr in #JTEST_FW.
*/
#define JTEST_CURRENT_GROUP_PTR() \
(JTEST_FW.current_group_ptr)
#define JTEST_SET_CURRENT_GROUP(group_ptr) \
do \
{ \
JTEST_CURRENT_GROUP_PTR() = group_ptr; \
} while (0)
/*--------------------------------------------------------------------------------*/
/* Declare Global Variables */
/*--------------------------------------------------------------------------------*/
extern char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE];
extern volatile JTEST_FW_t JTEST_FW;
/*--------------------------------------------------------------------------------*/
/* Function Prototypes */
/*--------------------------------------------------------------------------------*/
void jtest_dump_str_segments(void);
void test_start (void);
void test_end (void);
void group_start (void);
void group_end (void);
void dump_str (void);
void dump_data (void);
void exit_fw (void);
#endif /* _JTEST_FW_H_ */

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#ifndef _JTEST_GROUP_H_
#define _JTEST_GROUP_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_pf.h"
#include "jtest_util.h"
/*--------------------------------------------------------------------------------*/
/* Type Definitions */
/*--------------------------------------------------------------------------------*/
/**
* A struct which represents a group of #JTEST_TEST_t structs. This struct is
* used to run the group of tests, and report on their outcomes.
*/
typedef struct JTEST_GROUP_struct
{
void (* group_fn_ptr) (void); /**< Pointer to the test group */
char * name_str; /**< Name of the group */
/* Extend the #JTEST_GROUP_t with Pass/Fail information.*/
JTEST_PF_MEMBERS;
} JTEST_GROUP_t;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Set the name of JTEST_GROUP_t.
*/
#define JTEST_GROUP_SET_NAME(group_ptr, name) \
JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, name_str, name)
#define JTEST_GROUP_SET_FN(group_ptr, fn_ptr) \
JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, group_fn_ptr, fn_ptr)
/**
* Increment the number of tests passed in the JTEST_GROUP_t pointed to by
* group_ptr.
*/
#define JTEST_GROUP_INC_PASSED(group_ptr, amount) \
JTEST_PF_INC_PASSED(group_ptr, amount)
/**
* Increment the number of tests failed in the JTEST_GROUP_t pointed to by
* group_ptr.
*/
#define JTEST_GROUP_INC_FAILED(group_ptr, amount) \
JTEST_PF_INC_FAILED(group_ptr, amount)
/**
* Reset the pass/fail information of the #JTEST_GROUP_t pointed to by
* group_ptr.
*/
#define JTEST_GROUP_RESET_PF(group_ptr) \
do \
{ \
JTEST_PF_RESET_PASSED(group_ptr); \
JTEST_PF_RESET_FAILED(group_ptr); \
} while (0)
#endif /* _JTEST_GROUP_H_ */

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#ifndef _JTEST_GROUP_CALL_H_
#define _JTEST_GROUP_CALL_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_fw.h"
#include <inttypes.h>
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Execute the test in the #JTEST_GROUP_t struct associated witht he identifier
* group_fn.
*/
#define JTEST_GROUP_RUN(group_fn) \
do \
{ \
JTEST_DUMP_STR("Group Name:\n"); \
JTEST_DUMP_STR(JTEST_GROUP_STRUCT_NAME(group_fn).name_str); \
JTEST_GROUP_STRUCT_NAME(group_fn).group_fn_ptr(); \
} while (0)
/**
* Update the enclosing #JTEST_GROUP_t's pass/fail information using the
* current #JTEST_GROUP_t's.
*
* @param group_ptr Pointer to the current #JTEST_GROUP_t.
* @param parent_ptr Pointer to the enclosing #JTEST_GROUP_t.
*
* @warning Only run this if the current #JTEST_GROUP_t is being called within
* the context of another #JTEST_GROUP_t.
*/
#define JTEST_GROUP_UPDATE_PARENT_GROUP_PF(group_ptr, parent_group_ptr) \
do \
{ \
JTEST_GROUP_INC_PASSED(parent_group_ptr, \
(group_ptr)->passed); \
JTEST_GROUP_INC_FAILED(parent_group_ptr, \
(group_ptr)->failed); \
} while (0)
/**
* Update the #JTEST_FW's pass/fail information using the current
* #JTEST_GROUP_t's.
*/
#define JTEST_GROUP_UPDATE_FW_PF(group_ptr) \
do \
{ \
JTEST_FW_INC_PASSED((group_ptr)->passed); \
JTEST_FW_INC_FAILED((group_ptr)->failed); \
} while (0)
/**
* Update the enclosing context with the current #JTEST_GROUP_t's pass/fail
* information. If this group isn't in an enclosing group, it updates the
* #JTEST_FW's pass/fail info by default.
*/
#define JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(group_ptr, \
parent_group_ptr) \
do \
{ \
/* Update the pass fail counts in the parent group */ \
if (parent_group_ptr /* Null implies Top*/) \
{ \
JTEST_GROUP_UPDATE_PARENT_GROUP_PF( \
group_ptr, \
parent_group_ptr); \
} else { \
JTEST_GROUP_UPDATE_FW_PF( \
group_ptr); \
} \
} while (0)
/**
* Dump the results of running the #JTEST_GROUP_t to the Keil Debugger.
*/
#define JTEST_GROUP_DUMP_RESULTS(group_ptr) \
do \
{ \
JTEST_DUMP_STRF( \
"Tests Run: %" PRIu32 "\n" \
"----------\n" \
" Passed: %" PRIu32 "\n" \
" Failed: %" PRIu32 "\n", \
(group_ptr)->passed + (group_ptr)->failed, \
(group_ptr)->passed, \
(group_ptr)->failed); \
} while (0)
/**
* Call the #JTEST_GROUP_t associated with the identifier group_fn.
*/
#define JTEST_GROUP_CALL(group_fn) \
do \
{ /* Save the current group from JTEST_FW_t before swapping */ \
/* it to this group (in order to restore it later )*/ \
JTEST_GROUP_t * __jtest_temp_group_ptr = \
JTEST_CURRENT_GROUP_PTR(); \
JTEST_SET_CURRENT_GROUP(&JTEST_GROUP_STRUCT_NAME(group_fn)); \
\
/* Reset this group's pass/fail count. Each group */ \
/* should only remember counts for its last execution. */ \
JTEST_GROUP_RESET_PF(JTEST_CURRENT_GROUP_PTR()); \
\
/* Run the current group */ \
JTEST_ACT_GROUP_START(); \
JTEST_GROUP_RUN(group_fn); \
JTEST_ACT_GROUP_END(); \
\
/* Update the pass fail counts in the parent group (or FW) */ \
JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF( \
JTEST_CURRENT_GROUP_PTR(), \
__jtest_temp_group_ptr); \
\
JTEST_GROUP_DUMP_RESULTS(JTEST_CURRENT_GROUP_PTR()); \
\
/* Restore the previously current group */ \
JTEST_SET_CURRENT_GROUP(__jtest_temp_group_ptr); \
} while (0)
#endif /* _JTEST_GROUP_CALL_H_ */

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#ifndef _JTEST_GROUP_DEFINE_H_
#define _JTEST_GROUP_DEFINE_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_util.h"
#include "jtest_define.h"
#include "jtest_group.h"
/* For defining macros with optional arguments */
#include "opt_arg/opt_arg.h"
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Prefix for all #JTEST_GROUP_t structs.
*/
#define JTEST_GROUP_STRUCT_NAME_PREFIX G_JTEST_GROUP_STRUCT_
/**
* Define test template used by #JTEST_GROUP_t tests.
*/
#define JTEST_GROUP_FN_TEMPLATE(group_fn) \
void group_fn(void)
#define JTEST_GROUP_FN_PROTOTYPE JTEST_GROUP_FN_TEMPLATE /**< Alias for
#JTEST_GROUP_FN_TEMPLATE. */
/**
* Evaluate to the name of the #JTEST_GROUP_t struct associated with group_fn.
*/
#define JTEST_GROUP_STRUCT_NAME(group_fn) \
JTEST_STRUCT_NAME(JTEST_GROUP_STRUCT_NAME_PREFIX, group_fn)
/**
* Define a #JTEST_GROUP_t struct based on the given group_fn.
*/
#define JTEST_GROUP_DEFINE_STRUCT(group_fn) \
JTEST_DEFINE_STRUCT(JTEST_GROUP_t, \
JTEST_GROUP_STRUCT_NAME(group_fn))
/**
* Declare a #JTEST_GROUP_t struct based on the given group_fn.
*/
#define JTEST_GROUP_DECLARE_STRUCT(group_fn) \
JTEST_DECLARE_STRUCT(JTEST_GROUP_DEFINE_STRUCT(group_fn))
/**
* Contents needed to initialize a JTEST_GROUP_t struct.
*/
#define JTEST_GROUP_STRUCT_INIT(group_fn) \
group_fn, \
STR_NL(group_fn), \
JTEST_PF_MEMBER_INIT
/**
* Initialize the contents of a #JTEST_GROUP_t struct.
*/
#define JTEST_GROUP_INIT(group_fn) \
JTEST_GROUP_DEFINE_STRUCT(group_fn) = { \
JTEST_GROUP_STRUCT_INIT(group_fn) \
}
/* Test Definition Macro */
/*--------------------------------------------------------------------------------*/
/**
* Define a #JTEST_GROUP_t object and a test function.
*/
#define JTEST_DEFINE_GROUP(group_fn) \
JTEST_GROUP_FN_PROTOTYPE(group_fn); \
JTEST_GROUP_INIT(group_fn); \
JTEST_GROUP_FN_PROTOTYPE(group_fn) /* Notice the lacking semicolon */
/**
* Declare a #JTEST_GROUP_t object and a test function prototype.
*/
#define JTEST_DECLARE_GROUP(group_fn) \
JTEST_GROUP_FN_PROTOTYPE(group_fn); \
JTEST_GROUP_DECLARE_STRUCT(group_fn) /* Note the lacking semicolon */
#endif /* _JTEST_GROUP_DEFINE_H_ */

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#ifndef _JTEST_PF_H_
#define _JTEST_PF_H_
/*--------------------------------------------------------------------------------*/
/* Purpose */
/*--------------------------------------------------------------------------------*/
/* jtest_pf.h Contains macros useful for capturing pass/fail data. */
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Members that can be added to other structs to extend them pass/fail data and
* corresponding functionality.
*/
#define JTEST_PF_MEMBERS \
uint32_t passed; \
uint32_t failed /* Note the lacking semicolon*/ \
/**
* Used for initializing JTEST_PF_MEMBERS in a struct declaration.
*/
#define JTEST_PF_MEMBER_INIT \
0, \
0
/* Member-Incrementing Macros */
/*--------------------------------------------------------------------------------*/
/**
* Dispatch macro for incrementing #JTEST_PF_MEMBERS.
*
* @param xxx Values: 'passed', 'failed'
*/
#define JTEST_PF_INC_XXX(xxx, struct_pf_ptr, amount) \
do \
{ \
((struct_pf_ptr)->xxx) += (amount); \
} while (0)
/**
* Specialization of the #JTEST_PF_INC_XXX macro to increment the passed
* member.
*/
#define JTEST_PF_INC_PASSED(struct_pf_ptr, amount) \
JTEST_PF_INC_XXX(passed, struct_pf_ptr, amount)
/**
* Specialization of the #JTEST_PF_INC_XXX macro to increment the failed
* member.
*/
#define JTEST_PF_INC_FAILED(struct_pf_ptr, amount) \
JTEST_PF_INC_XXX(failed, struct_pf_ptr, amount)
/* Member-Resetting Macros */
/*--------------------------------------------------------------------------------*/
/**
* Dispatch macro for setting #JTEST_PF_MEMBERS to zero.
*
* @param xxx Values: 'passed', 'failed'
*/
#define JTEST_PF_RESET_XXX(xxx, struct_pf_ptr) \
do \
{ \
((struct_pf_ptr)->xxx) = UINT32_C(0); \
} while (0)
/**
* Specialization of #JTEST_PF_RESET_XXX for the 'passed' member.
*/
#define JTEST_PF_RESET_PASSED(struct_pf_ptr) \
JTEST_PF_RESET_XXX(passed, struct_pf_ptr)
/**
* Specialization of #JTEST_PF_RESET_XXX for the 'failed' member.
*/
#define JTEST_PF_RESET_FAILED(struct_pf_ptr) \
JTEST_PF_RESET_XXX(failed, struct_pf_ptr)
#endif /* _JTEST_PF_H_ */

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#ifndef _JTEST_SYSTICK_H_
#define _JTEST_SYSTICK_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
/* Get access to the SysTick structure. */
#if defined ARMCM0
#include "ARMCM0.h"
#elif defined ARMCM0P
#include "ARMCM0plus.h"
#elif defined ARMCM0P_MPU
#include "ARMCM0plus_MPU.h"
#elif defined ARMCM3
#include "ARMCM3.h"
#elif defined ARMCM4
#include "ARMCM4.h"
#elif defined ARMCM4_FP
#include "ARMCM4_FP.h"
#elif defined ARMCM7
#include "ARMCM7.h"
#elif defined ARMCM7_SP
#include "ARMCM7_SP.h"
#elif defined ARMCM7_DP
#include "ARMCM7_DP.h"
#elif defined ARMSC000
#include "ARMSC000.h"
#elif defined ARMSC300
#include "ARMSC300.h"
#elif defined ARMv8MBL
#include "ARMv8MBL.h"
#elif defined ARMv8MML
#include "ARMv8MML.h"
#elif defined ARMv8MML_DSP
#include "ARMv8MML_DSP.h"
#elif defined ARMv8MML_SP
#include "ARMv8MML_SP.h"
#elif defined ARMv8MML_DSP_SP
#include "ARMv8MML_DSP_SP.h"
#elif defined ARMv8MML_DP
#include "ARMv8MML_DP.h"
#elif defined ARMv8MML_DSP_DP
#include "ARMv8MML_DSP_DP.h"
#elif defined ARMv7A
/* TODO */
#else
#warning "no appropriate header file found!"
#endif
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Initial value for the SysTick module.
*
* This is also the maximum value, important as SysTick is a decrementing counter.
*/
#define JTEST_SYSTICK_INITIAL_VALUE 0xFFFFFF
/**
* Reset the SysTick, decrementing timer to it's maximum value and disable it.
*
* This macro should leave the SysTick timer in a state that's ready for cycle
* counting.
*/
#define JTEST_SYSTICK_RESET(systick_ptr) \
do \
{ \
(systick_ptr)->CTRL = SysTick_CTRL_CLKSOURCE_Msk; \
\
(systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE; \
(systick_ptr)->VAL = JTEST_SYSTICK_INITIAL_VALUE; \
} while (0)
/**
* Start the SysTick timer, sourced by the processor clock.
*/
#define JTEST_SYSTICK_START(systick_ptr) \
do \
{ \
(systick_ptr)->CTRL = \
SysTick_CTRL_ENABLE_Msk | \
SysTick_CTRL_CLKSOURCE_Msk; \
} while (0)
/**
* Evaluate to the current value of the SysTick timer.
*/
#define JTEST_SYSTICK_VALUE(systick_ptr) \
((systick_ptr)->VAL)
#endif /* _JTEST_SYSTICK_H_ */

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#ifndef _JTEST_TEST_H_
#define _JTEST_TEST_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include <stdint.h>
#include "jtest_util.h"
#include "jtest_test_ret.h"
/*--------------------------------------------------------------------------------*/
/* Type Definitions */
/*--------------------------------------------------------------------------------*/
/**
* A struct which represents a Test in the JTEST framework. This struct is
* used to enable, run, and describe the test it represents.
*/
typedef struct JTEST_TEST_struct
{
JTEST_TEST_RET_t ( * test_fn_ptr)(void); /**< Pointer to the test function. */
char * test_fn_str; /**< Name of the test function */
char * fut_str; /**< Name of the function under test. */
/**
* Flags that govern how the #JTEST_TEST_t behaves.
*/
union {
struct {
unsigned enabled : 1;
unsigned unused : 7;
} bits;
uint8_t byte; /* Access all flags at once. */
} flags;
} JTEST_TEST_t;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Assign a test function to the #JTEST_TEST_t struct.
*/
#define JTEST_TEST_SET_FN(jtest_test_ptr, fn_ptr) \
JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, test_fn_ptr, fn_ptr)
/**
* Specify a function under test (FUT) for the #JTEST_TEST_t struct.
*/
#define JTEST_TEST_SET_FUT(jtest_test_ptr, str) \
JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, fut_str, str)
/* Macros concerning JTEST_TEST_t flags */
/*--------------------------------------------------------------------------------*/
#define JTEST_TEST_FLAG_SET 1 /**< Value of a set #JTEST_TEST_t flag. */
#define JTEST_TEST_FLAG_CLR 0 /**< Value of a cleared #JTEST_TEST_t flag. */
/**
* Evaluate to the flag in #JTEST_TEST_t having flag_name.
*/
#define JTEST_TEST_FLAG(jtest_test_ptr, flag_name) \
((jtest_test_ptr)->flags.bits.flag_name)
/**
* Dispatch macro for setting and clearing #JTEST_TEST_t flags.
*
* @param jtest_test_ptr Pointer to a #JTEST_TEST_t struct.
* @param flag_name Name of the flag to set in #JTEST_TEST_t.flags.bits
* @param xxx Vaid values: "SET" or "CLR"
*
* @note This function depends on JTEST_TEST_FLAG_SET and JTEST_TEST_FLAG_CLR.
*/
#define JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, xxx) \
do \
{ \
JTEST_TEST_FLAG(jtest_test_ptr, flag_name) = JTEST_TEST_FLAG_##xxx ; \
} while (0)
/**
* Specification of #JTEST_TEST_XXX_FLAG to set #JTEST_TEST_t flags.
*/
#define JTEST_TEST_SET_FLAG(jtest_test_ptr, flag_name) \
JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, SET)
/**
* Specification of #JTEST_TEST_XXX_FLAG to clear #JTEST_TEST_t flags.
*/
#define JTEST_TEST_CLR_FLAG(jtest_test_ptr, flag_name) \
JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, CLR)
/**
* Evaluate to true if the #JTEST_TEST_t is enabled.
*/
#define JTEST_TEST_IS_ENABLED(jtest_test_ptr) \
(JTEST_TEST_FLAG(jtest_test_ptr, enabled) == JTEST_TEST_FLAG_SET)
#endif /* _JTEST_TEST_H_ */

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#ifndef _JTEST_TEST_CALL_H_
#define _JTEST_TEST_CALL_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_test.h"
#include "jtest_test_define.h"
#include "jtest_fw.h"
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Exectute the test in the #JTEST_TEST_t struct associated with the identifier
* test_fn and store the result in retval.
*/
#define JTEST_TEST_RUN(retval, test_fn) \
do \
{ \
JTEST_DUMP_STR("Test Name:\n"); \
JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).test_fn_str); \
JTEST_DUMP_STR("Function Under Test:\n"); \
JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).fut_str); \
retval = JTEST_TEST_STRUCT_NAME(test_fn).test_fn_ptr(); \
} while (0)
/**
* Update the enclosing #JTEST_GROUP_t's pass/fail information based on
* test_retval.
*
* @param test_retval A #JTEST_TEST_RET_enum for the current test.
*
* @warning Only use if #JTEST_TEST_t is called in the context of a
* #JTEST_GROUP_t.
*/
#define JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval) \
do \
{ \
/* Update enclosing JTEST_GROUP_t with pass/fail info */ \
if (test_retval == JTEST_TEST_PASSED) \
{ \
JTEST_GROUP_INC_PASSED(JTEST_CURRENT_GROUP_PTR(), 1); \
} else { \
JTEST_GROUP_INC_FAILED(JTEST_CURRENT_GROUP_PTR(), 1); \
} \
} while (0)
/**
* Update the #JTEST_FW with pass/fail information based on test_retval.
*
* @param test_retval A #JTEST_TEST_RET_enum for the current test.
*/
#define JTEST_TEST_UPDATE_FW_PF(test_retval) \
do \
{ \
/* Update the JTEST_FW with pass/fail info */ \
if (test_retval == JTEST_TEST_PASSED) \
{ \
JTEST_FW_INC_PASSED( 1); \
} else { \
JTEST_FW_INC_FAILED(1); \
} \
} while (0)
/**
* Update the enclosing JTEST_GROUP_t's pass/fail information, or the
* #JTEST_FW's if this test has no enclosing #JTEST_GROUP_t.
*
* @param test_retval A #JTEST_TEST_RET_enum for the current test.
*/
#define JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(test_retval) \
do \
{ \
/* Update pass-fail information */ \
if (JTEST_CURRENT_GROUP_PTR() /* Non-null */) \
{ \
JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval); \
} else { \
JTEST_TEST_UPDATE_FW_PF(test_retval); \
} \
} while (0)
/**
* Dump the results of the test to the Keil Debugger.
*/
#define JTEST_TEST_DUMP_RESULTS(test_retval) \
do \
{ \
if (test_retval == JTEST_TEST_PASSED) \
{ \
JTEST_DUMP_STR("Test Passed\n"); \
} else { \
JTEST_DUMP_STR("Test Failed\n"); \
} \
} while (0)
/**
* Call the #JTEST_TEST_t assocaited with the identifier test_fn.
*/
#define JTEST_TEST_CALL(test_fn) \
do \
{ \
if (JTEST_TEST_IS_ENABLED(&JTEST_TEST_STRUCT_NAME(test_fn))) \
{ \
/* Default to failure */ \
JTEST_TEST_RET_t __jtest_test_ret = JTEST_TEST_FAILED; \
\
JTEST_ACT_TEST_START(); \
JTEST_TEST_RUN(__jtest_test_ret, test_fn); \
\
/* Update pass-fail information */ \
JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(__jtest_test_ret); \
\
JTEST_TEST_DUMP_RESULTS(__jtest_test_ret); \
JTEST_ACT_TEST_END(); \
} \
} while (0)
#endif /* _JTEST_TEST_CALL_H_ */

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#ifndef _JTEST_TEST_DEFINE_H_
#define _JTEST_TEST_DEFINE_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_util.h"
#include "jtest_define.h"
#include "jtest_test.h"
/* For defining macros with optional arguments */
#include "opt_arg/opt_arg.h"
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Prefix for all #JTEST_TEST_t structs.
*/
#define JTEST_TEST_STRUCT_NAME_PREFIX G_JTEST_TEST_STRUCT_
/**
* Define test template used by #JTEST_TEST_t tests.
*/
#define JTEST_TEST_FN_TEMPLATE(test_fn) \
JTEST_TEST_RET_t test_fn(void)
#define JTEST_TEST_FN_PROTOTYPE JTEST_TEST_FN_TEMPLATE /**< Alias for
* #JTEST_TEST_FN_TEMPLATE. */
/**
* Evaluate to the name of the #JTEST_TEST_t struct associated with test_fn.
*/
#define JTEST_TEST_STRUCT_NAME(test_fn) \
JTEST_STRUCT_NAME(JTEST_TEST_STRUCT_NAME_PREFIX, test_fn)
/**
* Define a #JTEST_TEST_t struct based on the given test_fn.
*/
#define JTEST_TEST_DEFINE_STRUCT(test_fn) \
JTEST_DEFINE_STRUCT(JTEST_TEST_t, \
JTEST_TEST_STRUCT_NAME(test_fn))
/**
* Declare a #JTEST_TEST_t struct based on the given test_fn.
*/
#define JTEST_TEST_DECLARE_STRUCT(test_fn) \
JTEST_DECLARE_STRUCT(JTEST_TEST_DEFINE_STRUCT(test_fn))
/**
* Contents needed to initialize a JTEST_TEST_t struct.
*/
#define JTEST_TEST_STRUCT_INIT(test_fn, fut, enable) \
test_fn, \
STR_NL(test_fn), \
STR_NL(fut), \
{ \
{ \
enable, \
0 \
} \
} \
/**
* Initialize the contents of a #JTEST_TEST_t struct.
*/
#define JTEST_TEST_INIT(test_fn, fut, enable) \
JTEST_TEST_DEFINE_STRUCT(test_fn) = { \
JTEST_TEST_STRUCT_INIT(test_fn, fut, enable) \
}
/* Test Definition Macro */
/*--------------------------------------------------------------------------------*/
/**
* Define a #JTEST_TEST_t object and a test function.
*/
#define _JTEST_DEFINE_TEST(test_fn, fut, enable) \
JTEST_TEST_FN_PROTOTYPE(test_fn); \
JTEST_TEST_INIT(test_fn, fut, enable); \
JTEST_TEST_FN_PROTOTYPE(test_fn) /* Notice the lacking semicolon */
/**
* Declare a #JTEST_TEST_t object and a test function prototype.
*/
#define JTEST_DECLARE_TEST(test_fn) \
JTEST_TEST_FN_PROTOTYPE(test_fn); \
JTEST_TEST_DECLARE_STRUCT(test_fn) /* Note the lacking semicolon */
/*--------------------------------------------------------------------------------*/
/* Macros with optional arguments */
/*--------------------------------------------------------------------------------*/
/* Top-level Interface */
#define JTEST_DEFINE_TEST(...) \
JTEST_DEFINE_TEST_(PP_NARG(__VA_ARGS__), ##__VA_ARGS__)
/* Dispatch Macro*/
#define JTEST_DEFINE_TEST_(N, ...) \
SPLICE(JTEST_DEFINE_TEST_, N)(__VA_ARGS__)
/* Default Arguments */
#define JTEST_DEFINE_TEST_DEFAULT_FUT /* Blank */
#define JTEST_DEFINE_TEST_DEFAULT_ENABLE \
JTEST_TRUE /* Tests enabled by
* default. */
/* Dispatch Cases*/
#define JTEST_DEFINE_TEST_1(_1) \
_JTEST_DEFINE_TEST( \
_1, \
JTEST_DEFINE_TEST_DEFAULT_FUT, \
JTEST_DEFINE_TEST_DEFAULT_ENABLE \
)
#define JTEST_DEFINE_TEST_2(_1, _2) \
_JTEST_DEFINE_TEST( \
_1, \
_2, \
JTEST_DEFINE_TEST_DEFAULT_ENABLE \
)
#define JTEST_DEFINE_TEST_3(_1, _2, _3) \
_JTEST_DEFINE_TEST( \
_1, \
_2, \
_3 \
)
#endif /* _JTEST_TEST_DEFINE_H_ */

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#ifndef _JTEST_TEST_RET_H_
#define _JTEST_TEST_RET_H_
/*--------------------------------------------------------------------------------*/
/* Type Definitions */
/*--------------------------------------------------------------------------------*/
/**
* Values a #JTEST_TEST_t can return.
*/
typedef enum JTEST_TEST_RET_enum
{
JTEST_TEST_PASSED,
JTEST_TEST_FAILED
} JTEST_TEST_RET_t;
#endif /* _JTEST_TEST_RET_H_ */

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#ifndef _JTEST_UTIL_H_
#define _JTEST_UTIL_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "util/util.h"
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/* Define boolean values for the framework. */
#define JTEST_TRUE 1 /**< Value used for TRUE in JTEST. */
#define JTEST_FALSE 0 /**< Value used for FALSE in JTEST. */
/**
* Set the value of the attribute in the struct to by struct_ptr to value.
*/
#define JTEST_SET_STRUCT_ATTRIBUTE(struct_ptr, attribute, value) \
do \
{ \
(struct_ptr)->attribute = (value); \
} while (0)
#endif /* _JTEST_UTIL_H_ */

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#ifndef _OPT_ARG_H_
#define _OPT_ARG_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "pp_narg.h"
#include "splice.h"
/* If you are Joseph Jaoudi, you have a snippet which expands into an
example. If you are not Joseph, but possess his code, study the examples. If
you have no examples, turn back contact Joseph. */
#endif /* _OPT_ARG_H_ */

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#ifndef _PP_NARG_H_
#define _PP_NARG_H_
#define PP_NARG(...) \
PP_NARG_(__VA_ARGS__,PP_RSEQ_N())
#define PP_NARG_(...) \
PP_ARG_N(__VA_ARGS__)
#define PP_ARG_N( \
_1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \
_11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
_21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
_31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
_41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
_51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
_61,_62,_63,N,...) N
#define PP_RSEQ_N() \
63,62,61,60, \
59,58,57,56,55,54,53,52,51,50, \
49,48,47,46,45,44,43,42,41,40, \
39,38,37,36,35,34,33,32,31,30, \
29,28,27,26,25,24,23,22,21,20, \
19,18,17,16,15,14,13,12,11,10, \
9,8,7,6,5,4,3,2,1,0
#endif /* _PP_NARG_H_ */

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#ifndef _SPLICE_H_
#define _SPLICE_H_
#define SPLICE(a,b) SPLICE_1(a,b)
#define SPLICE_1(a,b) SPLICE_2(a,b)
#define SPLICE_2(a,b) a##b
#endif /* _SPLICE_H_ */

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#ifndef _UTIL_H_
#define _UTIL_H_
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Convert a symbol to a string and add a 'NewLine'.
*/
#define STR_NL(x) STR1_NL(x)
#define STR1_NL(x) (STR2_NL(x)"\n")
#define STR2_NL(x) #x
/**
* Convert a symbol to a string.
*/
#define STR(x) STR1(x)
#define STR1(x) STR2(x)
#define STR2(x) #x
/**
* Concatenate two symbols.
*/
#define CONCAT(a, b) CONCAT1(a, b)
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a##b
/**
* Place curly braces around a varaible number of macro arguments.
*/
#define CURLY(...) {__VA_ARGS__}
/**
* Place parenthesis around a variable number of macro arguments.
*/
#define PAREN(...) (__VA_ARGS__)
/* Standard min/max macros. */
#define MIN(x,y) (((x) < (y)) ? (x) : (y) )
#define MAX(x,y) (((x) > (y)) ? (x) : (y) )
/**
* Bound value using low and high limits.
*
* Evaluate to a number in the range, endpoint inclusive.
*/
#define BOUND(low, high, value) \
MAX(MIN(high, value), low)
#endif /* _UTIL_H_ */

9
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#include "../inc/jtest_cycle.h"
#include <inttypes.h>
/*--------------------------------------------------------------------------------*/
/* Define Module Variables */
/*--------------------------------------------------------------------------------*/
/* const char * JTEST_CYCLE_STRF = "Running: %s\nCycles: %" PRIu32 "\n"; */
const char * JTEST_CYCLE_STRF = "Cycles: %" PRIu32 "\n"; /* function name + parameter string skipped */

36
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#include "jtest_fw.h"
/**
* Dump the JTEST_FW.str_buffer the Keil framework in pieces.
*
* The JTEST_FW.str_buffer contains more characters than the Keil framework can
* dump at once. This function dumps them in blocks.
*/
void jtest_dump_str_segments(void)
{
uint32_t seg_idx = 0;
uint32_t memmove_idx = 0;
uint32_t seg_cnt =
(strlen(JTEST_FW.str_buffer) / JTEST_STR_MAX_OUTPUT_SIZE) + 1;
for( seg_idx = 0; seg_idx < seg_cnt; ++seg_idx)
{
JTEST_TRIGGER_ACTION(dump_str);
if (seg_idx < JTEST_STR_MAX_OUTPUT_SEGMENTS)
{
memmove_idx = 0;
while (memmove_idx < (seg_cnt - seg_idx -1) )
{
memmove(
JTEST_FW.str_buffer+
(memmove_idx* JTEST_STR_MAX_OUTPUT_SIZE),
JTEST_FW.str_buffer+
((memmove_idx+1)*JTEST_STR_MAX_OUTPUT_SIZE),
JTEST_BUF_SIZE);
++memmove_idx;
}
}
}
return;
}

9
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#include "../inc/jtest.h"
/*--------------------------------------------------------------------------------*/
/* Define Global Variables */
/*--------------------------------------------------------------------------------*/
char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE] = {0};
volatile JTEST_FW_t JTEST_FW = {0};

37
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#include "jtest_fw.h"
void test_start (void) {
// ;
JTEST_FW.test_start++;
}
void test_end (void) {
// ;
JTEST_FW.test_end++;
}
void group_start (void) {
// ;
JTEST_FW.group_start++;
}
void group_end (void) {
// ;
JTEST_FW.group_end++;
}
void dump_str (void) {
// ;
JTEST_FW.dump_str++;
}
void dump_data (void) {
// ;
JTEST_FW.dump_data++;
}
void exit_fw (void) {
// ;
JTEST_FW.exit_fw++;
}

9
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#ifndef _ALL_TESTS_H_
#define _ALL_TESTS_H_
/*--------------------------------------------------------------------------------*/
/* Declare Test Groups */
/*--------------------------------------------------------------------------------*/
JTEST_DECLARE_GROUP(all_tests);
#endif /* _ALL_TESTS_H_ */

267
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#ifndef _BASIC_MATH_TEMPLATES_H_
#define _BASIC_MATH_TEMPLATES_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "test_templates.h"
/*--------------------------------------------------------------------------------*/
/* Group Specific Templates */
/*--------------------------------------------------------------------------------*/
/**
* Compare the outputs used by basic math tests for the function under test and
* the reference function.
*/
#define BASIC_MATH_COMPARE_INTERFACE(block_size, output_type) \
TEST_ASSERT_BUFFERS_EQUAL( \
basic_math_output_ref.data_ptr, \
basic_math_output_fut.data_ptr, \
block_size * sizeof(output_type))
/*
* Comparison SNR thresholds for the data types used in basic_math_tests.
*/
#define BASIC_MATH_SNR_THRESHOLD_float32_t 120
#define BASIC_MATH_SNR_THRESHOLD_q31_t 100
#define BASIC_MATH_SNR_THRESHOLD_q15_t 75
#define BASIC_MATH_SNR_THRESHOLD_q7_t 25
/**
* Compare reference and fut outputs using SNR.
*
* @note The outputs are converted to float32_t before comparison.
*/
#define BASIC_MATH_SNR_COMPARE_INTERFACE(block_size, output_type) \
do \
{ \
TEST_CONVERT_AND_ASSERT_SNR( \
basic_math_output_f32_ref, \
basic_math_output_ref.data_ptr, \
basic_math_output_f32_fut, \
basic_math_output_fut.data_ptr, \
block_size, \
output_type, \
BASIC_MATH_SNR_THRESHOLD_##output_type \
); \
} while (0)
/**
* Compare reference and fut outputs using SNR.
*
* @note The outputs are converted to float32_t before comparison.
*/
#define BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE(block_size, output_type) \
do \
{ \
TEST_CONVERT_AND_ASSERT_SNR( \
basic_math_output_f32_ref, \
basic_math_output_ref.data_ptr, \
basic_math_output_f32_fut, \
basic_math_output_fut.data_ptr, \
1, \
output_type, \
BASIC_MATH_SNR_THRESHOLD_##output_type \
); \
} while (0)
/*--------------------------------------------------------------------------------*/
/* Input Interfaces */
/*--------------------------------------------------------------------------------*/
/*
* General:
* Input interfaces provide inputs to functions inside test templates. They
* ONLY provide the inputs. The output variables should be hard coded.
*
* The input interfaces must have the following format:
*
* ARM_xxx_INPUT_INTERFACE() or
* REF_xxx_INPUT_INTERFACE()
*
* The xxx must be lowercase, and is intended to be the indentifying substring
* in the function's name. Acceptable values are 'sub' or 'add' from the
* functions arm_add_q31.
*/
#define ARM_abs_INPUT_INTERFACE(input, block_size) \
PAREN(input, basic_math_output_fut.data_ptr, block_size)
#define REF_abs_INPUT_INTERFACE(input, block_size) \
PAREN(input, basic_math_output_ref.data_ptr, block_size)
#define ARM_add_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
#define REF_add_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
#define ARM_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, block_size, basic_math_output_fut.data_ptr) \
#define REF_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, block_size, basic_math_output_ref.data_ptr) \
#define ARM_mult_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
#define REF_mult_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
#define ARM_negate_INPUT_INTERFACE(input, block_size) \
PAREN(input, basic_math_output_fut.data_ptr, block_size)
#define REF_negate_INPUT_INTERFACE(input, block_size) \
PAREN(input, basic_math_output_ref.data_ptr, block_size)
#define ARM_offset_INPUT_INTERFACE(input, elt, block_size) \
PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \
#define REF_offset_INPUT_INTERFACE(input, elt, block_size) \
PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \
#define ARM_shift_INPUT_INTERFACE(input, elt, block_size) \
PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \
#define REF_shift_INPUT_INTERFACE(input, elt, block_size) \
PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \
#define ARM_scale_float_INPUT_INTERFACE(input, elt, block_size) \
PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \
#define REF_scale_float_INPUT_INTERFACE(input, elt, block_size) \
PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \
/* These two are for the fixed point functions */
#define ARM_scale_INPUT_INTERFACE(input, elt1, elt2, block_size) \
PAREN(input, elt1, elt2, basic_math_output_fut.data_ptr, block_size) \
#define REF_scale_INPUT_INTERFACE(input, elt1, elt2, block_size) \
PAREN(input, elt1, elt2, basic_math_output_ref.data_ptr, block_size) \
#define ARM_sub_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
#define REF_sub_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
/*--------------------------------------------------------------------------------*/
/* Test Templates */
/*--------------------------------------------------------------------------------*/
/**
* Specialization of #TEST_TEMPLATE_BUF1_BLK() for basic math tests.
*
* @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
* REF_xxx_INPUT_INTERFACEs.
*/
#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \
suffix, \
input_type, \
output_type) \
JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
arm_##fn_name##_##suffix) \
{ \
TEST_TEMPLATE_BUF1_BLK( \
basic_math_f_all, \
basic_math_block_sizes, \
input_type, \
output_type, \
arm_##fn_name##_##suffix, \
ARM_##fn_name##_INPUT_INTERFACE, \
ref_##fn_name##_##suffix, \
REF_##fn_name##_INPUT_INTERFACE, \
BASIC_MATH_COMPARE_INTERFACE); \
}
/**
* Specialization of #TEST_TEMPLATE_BUF2_BLK() for basic math tests.
*
* @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
* REF_xxx_INPUT_INTERFACEs.
*/
#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name, \
suffix, \
input_type, \
output_type, \
comparison_interface) \
JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
arm_##fn_name##_##suffix) \
{ \
TEST_TEMPLATE_BUF2_BLK( \
basic_math_f_all, \
basic_math_f_all, \
basic_math_block_sizes, \
input_type, \
output_type, \
arm_##fn_name##_##suffix, \
ARM_##fn_name##_INPUT_INTERFACE, \
ref_##fn_name##_##suffix, \
REF_##fn_name##_INPUT_INTERFACE, \
comparison_interface); \
}
/**
* Specialization of #TEST_TEMPLATE_BUF1_ELT1_BLK() for basic math tests.
*
* @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
* REF_xxx_INPUT_INTERFACEs.
*/
#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK(fn_name, \
suffix, \
input_type, \
elt_type, \
output_type) \
JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
arm_##fn_name##_##suffix) \
{ \
TEST_TEMPLATE_BUF1_ELT1_BLK( \
basic_math_f_all, \
basic_math_elts, \
basic_math_block_sizes, \
input_type, \
elt_type, \
output_type, \
arm_##fn_name##_##suffix, \
ARM_##fn_name##_INPUT_INTERFACE, \
ref_##fn_name##_##suffix, \
REF_##fn_name##_INPUT_INTERFACE, \
BASIC_MATH_COMPARE_INTERFACE); \
}
/**
* Specialization of #TEST_TEMPLATE_BUF1_ELT2_BLK() for basic math tests.
*
* @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
* REF_xxx_INPUT_INTERFACEs.
*/
#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK(fn_name, \
suffix, \
input_type, \
elt1_type, \
elt2_type, \
output_type) \
JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
arm_##fn_name##_##suffix) \
{ \
TEST_TEMPLATE_BUF1_ELT2_BLK( \
basic_math_f_all, \
basic_math_elts, \
basic_math_elts2, \
basic_math_block_sizes, \
input_type, \
elt1_type, \
elt2_type, \
output_type, \
arm_##fn_name##_##suffix, \
ARM_##fn_name##_INPUT_INTERFACE, \
ref_##fn_name##_##suffix, \
REF_##fn_name##_INPUT_INTERFACE, \
BASIC_MATH_COMPARE_INTERFACE); \
}
#endif /* _BASIC_MATH_TEMPLATES_H_ */

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#ifndef ARM_BASIC_MATH_TEST_DATA_H
#define ARM_BASIC_MATH_TEST_DATA_H
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "arr_desc.h"
#include "arm_math.h"
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
#define BASIC_MATH_MAX_INPUT_ELEMENTS 32
#define BASIC_MATH_BIGGEST_INPUT_TYPE float32_t
/*--------------------------------------------------------------------------------*/
/* Declare Variables */
/*--------------------------------------------------------------------------------*/
/* Input/Output Buffers */
ARR_DESC_DECLARE(basic_math_output_fut);
ARR_DESC_DECLARE(basic_math_output_ref);
extern BASIC_MATH_BIGGEST_INPUT_TYPE
basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS];
extern BASIC_MATH_BIGGEST_INPUT_TYPE
basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS];
/* Block Sizes*/
ARR_DESC_DECLARE(basic_math_block_sizes);
/* Numbers */
ARR_DESC_DECLARE(basic_math_elts);
ARR_DESC_DECLARE(basic_math_elts2);
ARR_DESC_DECLARE(basic_math_eltsf);
/* Float Inputs */
ARR_DESC_DECLARE(basic_math_zeros);
ARR_DESC_DECLARE(basic_math_f_2);
ARR_DESC_DECLARE(basic_math_f_15);
ARR_DESC_DECLARE(basic_math_f_32);
ARR_DESC_DECLARE(basic_math_f_all);
#endif

9
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#ifndef _BASIC_MATH_TEST_GROUP_H_
#define _BASIC_MATH_TEST_GROUP_H_
/*--------------------------------------------------------------------------------*/
/* Declare Test Groups */
/*--------------------------------------------------------------------------------*/
JTEST_DECLARE_GROUP(basic_math_tests);
#endif /* _BASIC_MATH_TEST_GROUP_H_ */

17
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#ifndef _BASIC_MATH_TESTS_H_
#define _BASIC_MATH_TESTS_H_
/*--------------------------------------------------------------------------------*/
/* Test/Group Declarations */
/*--------------------------------------------------------------------------------*/
JTEST_DECLARE_GROUP(abs_tests);
JTEST_DECLARE_GROUP(add_tests);
JTEST_DECLARE_GROUP(dot_prod_tests);
JTEST_DECLARE_GROUP(mult_tests);
JTEST_DECLARE_GROUP(negate_tests);
JTEST_DECLARE_GROUP(offset_tests);
JTEST_DECLARE_GROUP(scale_tests);
JTEST_DECLARE_GROUP(shift_tests);
JTEST_DECLARE_GROUP(sub_tests);
#endif /* _BASIC_MATH_TESTS_H_ */

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#ifndef _COMPLEX_MATH_TEMPLATES_H_
#define _COMPLEX_MATH_TEMPLATES_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "test_templates.h"
/*--------------------------------------------------------------------------------*/
/* Group Specific Templates */
/*--------------------------------------------------------------------------------*/
/**
* Compare the real outputs from the function under test and the reference
* function.
*/
#define COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size, output_type) \
TEST_ASSERT_BUFFERS_EQUAL( \
complex_math_output_ref_a.data_ptr, \
complex_math_output_fut_a.data_ptr, \
block_size * sizeof(output_type))
/**
* Compare the real and imaginary outputs from the function under test and the
* reference function.
*/
#define COMPLEX_MATH_COMPARE_CMPLX_INTERFACE(block_size, output_type) \
do \
{ \
COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size * 2, output_type); \
} while (0)
/*
* Comparison SNR thresholds for the data types used in complex_math_tests.
*/
#define COMPLEX_MATH_SNR_THRESHOLD_float32_t 120
#define COMPLEX_MATH_SNR_THRESHOLD_q31_t 100
#define COMPLEX_MATH_SNR_THRESHOLD_q15_t 75
/**
* Compare reference and fut outputs using SNR.
*
* The output_suffix specifies which output buffers to use for the
* comparison. An output_suffix of 'a' expands to the following buffers:
*
* - complex_math_output_f32_ref_a
* - complex_math_output_f32_fut_a
* - complex_math_output_ref_a
* - complex_math_output_fut_a
*
* @note The outputs are converted to float32_t before comparison.
*/
#define COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \
output_type, \
output_suffix) \
do \
{ \
TEST_CONVERT_AND_ASSERT_SNR( \
complex_math_output_f32_ref_##output_suffix, \
complex_math_output_ref_##output_suffix.data_ptr, \
complex_math_output_f32_fut_##output_suffix, \
complex_math_output_fut_##output_suffix.data_ptr, \
block_size, \
output_type, \
COMPLEX_MATH_SNR_THRESHOLD_##output_type \
); \
} while (0)
/**
* Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for real outputs.
*/
#define COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE(block_size, \
output_type) \
COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \
output_type, \
a)
/**
* Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for complex outputs.
*/
#define COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE(block_size, \
output_type) \
COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size * 2, \
output_type, \
a)
/**
* Compare reference and fut split outputs using SNR.
*
* 'Split' refers to two separate output buffers; one for real and one for
* complex.
*/
#define COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE(block_size, \
output_type) \
do \
{ \
COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \
output_type, \
a); \
COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \
output_type, \
b); \
} while (0)
/*--------------------------------------------------------------------------------*/
/* Input Interfaces */
/*--------------------------------------------------------------------------------*/
/*
* General:
* Input interfaces provide inputs to functions inside test templates. They
* ONLY provide the inputs. The output variables should be hard coded.
*
* The input interfaces must have the following format:
*
* ARM_xxx_INPUT_INTERFACE() or
* REF_xxx_INPUT_INTERFACE()
*
* The xxx must be lowercase, and is intended to be the indentifying substring
* in the function's name. Acceptable values are 'sub' or 'add' from the
* functions arm_add_q31.
*/
#define ARM_cmplx_conj_INPUT_INTERFACE(input, block_size) \
PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
#define REF_cmplx_conj_INPUT_INTERFACE(input, block_size) \
PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
#define ARM_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, block_size, \
complex_math_output_fut_a.data_ptr, \
complex_math_output_fut_b.data_ptr)
#define REF_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, block_size, \
complex_math_output_ref_a.data_ptr, \
complex_math_output_ref_b.data_ptr)
#define ARM_cmplx_mag_INPUT_INTERFACE(input, block_size) \
PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
#define REF_cmplx_mag_INPUT_INTERFACE(input, block_size) \
PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
#define ARM_cmplx_mag_squared_INPUT_INTERFACE(input, block_size) \
PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
#define REF_cmplx_mag_squared_INPUT_INTERFACE(input, block_size) \
PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
#define ARM_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size)
#define REF_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size)
#define ARM_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size)
#define REF_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \
PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size)
/*--------------------------------------------------------------------------------*/
/* Test Templates */
/*--------------------------------------------------------------------------------*/
/**
* Specialization of #TEST_TEMPLATE_BUF1_BLK() for complex math tests.
*
* @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
* REF_xxx_INPUT_INTERFACEs.
*/
#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \
suffix, \
input_type, \
output_type, \
comparison_interface) \
JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
arm_##fn_name##_##suffix) \
{ \
TEST_TEMPLATE_BUF1_BLK( \
complex_math_f_all, \
complex_math_block_sizes, \
input_type, \
output_type, \
arm_##fn_name##_##suffix, \
ARM_##fn_name##_INPUT_INTERFACE, \
ref_##fn_name##_##suffix, \
REF_##fn_name##_INPUT_INTERFACE, \
comparison_interface); \
}
/**
* Specialization of #TEST_TEMPLATE_BUF2_BLK1() for complex math tests.
*
* @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
* REF_xxx_INPUT_INTERFACEs.
*/
#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name, \
suffix, \
input_type, \
output_type, \
comparison_interface) \
JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \
arm_##fn_name##_##suffix) \
{ \
TEST_TEMPLATE_BUF2_BLK( \
complex_math_f_all, \
complex_math_f_all, \
complex_math_block_sizes, \
input_type, \
output_type, \
arm_##fn_name##_##suffix, \
ARM_##fn_name##_INPUT_INTERFACE, \
ref_##fn_name##_##suffix, \
REF_##fn_name##_INPUT_INTERFACE, \
comparison_interface); \
}
#endif /* _COMPLEX_MATH_TEMPLATES_H_ */

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#ifndef _COMPLEX_MATH_TEST_DATA_H_
#define _COMPLEX_MATH_TEST_DATA_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "arr_desc.h"
#include "arm_math.h"
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
#define COMPLEX_MATH_MAX_INPUT_ELEMENTS 32
#define COMPLEX_MATH_BIGGEST_INPUT_TYPE float32_t
/*--------------------------------------------------------------------------------*/
/* Decalare Variables */
/*--------------------------------------------------------------------------------*/
/* Input/Output Buffers */
ARR_DESC_DECLARE(complex_math_output_fut_a);
ARR_DESC_DECLARE(complex_math_output_fut_b);
ARR_DESC_DECLARE(complex_math_output_ref_a);
ARR_DESC_DECLARE(complex_math_output_ref_b);
extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
/* Block Sizes*/
ARR_DESC_DECLARE(complex_math_block_sizes);
/* Float Inputs */
ARR_DESC_DECLARE(complex_math_zeros);
ARR_DESC_DECLARE(complex_math_f_2);
ARR_DESC_DECLARE(complex_math_f_15);
ARR_DESC_DECLARE(complex_math_f_32);
ARR_DESC_DECLARE(complex_math_f_all);
#endif /* _COMPLEX_MATH_TEST_DATA_H_ */

9
Software/FT25-Charger/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h Normal file
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#ifndef _COMPLEX_MATH_TEST_GROUP_H_
#define _COMPLEX_MATH_TEST_GROUP_H_
/*--------------------------------------------------------------------------------*/
/* Declare Test Groups */
/*--------------------------------------------------------------------------------*/
JTEST_DECLARE_GROUP(complex_math_tests);
#endif /* _COMPLEX_MATH_TEST_GROUP_H_ */

14
Software/FT25-Charger/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h Normal file
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#ifndef _COMPLEX_MATH_TESTS_H_
#define _COMPLEX_MATH_TESTS_H_
/*--------------------------------------------------------------------------------*/
/* Test/Group Declarations */
/*--------------------------------------------------------------------------------*/
JTEST_DECLARE_GROUP(cmplx_conj_tests);
JTEST_DECLARE_GROUP(cmplx_dot_prod_tests);
JTEST_DECLARE_GROUP(cmplx_mag_tests);
JTEST_DECLARE_GROUP(cmplx_mag_squared_tests);
JTEST_DECLARE_GROUP(cmplx_mult_cmplx_tests);
JTEST_DECLARE_GROUP(cmplx_mult_real_tests);
#endif /* _COMPLEX_MATH_TESTS_H_ */

46
Software/FT25-Charger/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h Normal file
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#ifndef _CONTROLLER_TEMPLATES_H_
#define _CONTROLLER_TEMPLATES_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "test_templates.h"
#include <string.h> /* memcpy() */
/*--------------------------------------------------------------------------------*/
/* Group Specific Templates */
/*--------------------------------------------------------------------------------*/
/**
* Comparison SNR thresholds for the data types used in transform_tests.
*/
#define CONTROLLER_SNR_THRESHOLD_float32_t 110
#define CONTROLLER_SNR_THRESHOLD_q31_t 100
#define CONTROLLER_SNR_THRESHOLD_q15_t 45
/**
* Compare the outputs from the function under test and the reference
* function using SNR.
*/
#define CONTROLLER_SNR_COMPARE_INTERFACE(block_size, \
output_type) \
do \
{ \
TEST_CONVERT_AND_ASSERT_SNR( \
controller_output_f32_ref, \
(output_type *) controller_output_ref, \
controller_output_f32_fut, \
(output_type *) controller_output_fut, \
block_size, \
output_type, \
CONTROLLER_SNR_THRESHOLD_##output_type \
); \
} while (0)
/*--------------------------------------------------------------------------------*/
/* TEST Templates */
/*--------------------------------------------------------------------------------*/
#endif /* _CONTROLLER_TEMPLATES_H_ */

33
Software/FT25-Charger/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h Normal file
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#ifndef _CONTROLLER_TEST_DATA_H_
#define _CONTROLLER_TEST_DATA_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "arm_math.h"
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
#define CONTROLLER_MAX_LEN 1024
#define CONTROLLER_MAX_COEFFS_LEN (12 * 3)
#define TRANFORM_BIGGEST_INPUT_TYPE float32_t
/*--------------------------------------------------------------------------------*/
/* Variable Declarations */
/*--------------------------------------------------------------------------------*/
extern float32_t controller_output_fut[CONTROLLER_MAX_LEN];
extern float32_t controller_output_ref[CONTROLLER_MAX_LEN];
extern float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN];
extern float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN];
extern const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN];
extern const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN];
extern const q15_t * controller_q15_inputs;
extern const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN];
extern const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN];
extern const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN];
#endif /* _CONTROLLER_TEST_DATA_H_ */

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