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FDCAN Timings and settings correctly configured

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This commit is contained in:
hamza
2024-05-20 20:37:53 +03:00
parent 7b976812ac
commit bfbecba2a6
78 changed files with 363 additions and 322 deletions
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2
Core/Inc/slave_monitoring.h
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@ -3,7 +3,7 @@
#include <stdint.h>
#define N_SLAVES 3
#define N_SLAVES 1
#define N_CELLS_SERIES 15
#define N_CELLS_PARALLEL 4
#define N_TEMP_SENSORS 32

2
Core/Inc/stm32h7xx_hal_conf.h
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@ -107,7 +107,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (24000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)

1
Core/Inc/stm32h7xx_it.h
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@ -55,6 +55,7 @@ void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void FDCAN1_IT0_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */