new nmos

Hardware/sim/IPW60R045CP.lib

@@ -0,0 +1,34 @@
+.SUBCKT IPW60R045CP_L0  drain  gate  source
+
+Lg     gate  g1    8n
+Ld     drain d1    3n
+Ls     source s1   8n
+Rs      s1    s2   1.5m
+
+Rg     g1    g2     1.3
+M1      d2    g2    s2    s2    DMOS    L=1u   W=1u
+.MODEL DMOS NMOS ( KP= 112.533  VTO=3.85  THETA=0  VMAX=1.5e5  ETA=0  LEVEL=3)
+Rd     d2    d1a    0.034 TC=13m
+.MODEL MVDR NMOS (KP=272.45 VTO=-1   LAMBDA=0.15)
+Mr d1 d2a d1a d1a MVDR W=1u L=1u
+Rx d2a d1a 1m
+Cds1 s2 d2 195.5p
+Dbd     s2    d2    Dbt
+.MODEL     Dbt    D(BV=600   M=0.85  CJO=88.84n  VJ=0.5V)
+Dbody   s2   21    DBODY
+.MODEL DBODY  D(IS=42.1p  N=1.08  RS=2u  EG=1.12  TT=750n)
+Rdiode  d1  21    1.69m TC=6m
+
+.MODEL   sw    NMOS(VTO=0  KP=10   LEVEL=1)
+Maux      g2   c    a    a   sw
+Maux2     b    d    g2    g2   sw
+Eaux      c    a    d2    g2   1
+Eaux2     d    g2   d2    g2   -1
+Cox       b    d2   5.51n
+.MODEL     DGD    D(M=1   CJO=5.51n   VJ=0.5)
+Rpar      b    d2   1Meg
+Dgd       a    d2   DGD
+Rpar2     d2   a    10Meg
+Cgs     g2    s2    6.81n
+
+.ENDS  IPW60R045CP_L0

Hardware/sim/IPW60R045CP_L0.asy

@@ -0,0 +1,17 @@
+Version 4
+SymbolType BLOCK
+RECTANGLE Normal -96 -40 112 40
+WINDOW 0 8 -40 Bottom 2
+WINDOW 3 8 40 Top 2
+SYMATTR Prefix X
+SYMATTR Value IPW60R045CP_L0
+SYMATTR ModelFile C:\Users\frede\OneDrive\Dokumente\Fasttube\FT25\TS-DCDC\Hardware\sim\IPW60R045CP.lib
+PIN -96 0 LEFT 8
+PINATTR PinName drain
+PINATTR SpiceOrder 1
+PIN 112 -16 RIGHT 8
+PINATTR PinName gate
+PINATTR SpiceOrder 2
+PIN 112 16 RIGHT 8
+PINATTR PinName source
+PINATTR SpiceOrder 3

Hardware/sim/precharge_sim.asc

@@ -1,46 +1,56 @@
 Version 4
-SHEET 1 880 680
-WIRE -32 96 -368 96
-WIRE 272 96 -32 96
-WIRE -32 128 -32 96
+SHEET 1 880 800
+WIRE -128 96 -368 96
+WIRE 464 96 -128 96
+WIRE -128 128 -128 96
 WIRE -368 192 -368 96
-WIRE 272 224 272 96
-WIRE -32 240 -32 208
-WIRE -32 240 -96 240
-WIRE 32 240 -32 240
-WIRE -32 256 -32 240
-WIRE -96 272 -96 240
-WIRE 32 368 32 240
-WIRE 48 368 32 368
-WIRE 272 384 272 288
-WIRE 272 384 256 384
+WIRE 464 208 464 96
+WIRE -128 240 -128 208
+WIRE -128 240 -224 240
+WIRE 80 240 -128 240
+WIRE 176 240 80 240
+WIRE -224 272 -224 240
+WIRE -128 272 -128 240
+WIRE 80 288 80 240
+WIRE 176 368 176 240
+WIRE 208 368 176 368
+WIRE 464 384 464 272
+WIRE 464 384 416 384
 WIRE -368 400 -368 272
 WIRE -336 400 -368 400
-WIRE -96 400 -96 336
-WIRE -96 400 -336 400
-WIRE -32 400 -32 336
-WIRE -32 400 -96 400
-WIRE 48 400 -32 400
+WIRE -224 400 -224 336
+WIRE -224 400 -336 400
+WIRE -128 400 -128 352
+WIRE -128 400 -224 400
+WIRE 80 400 80 352
+WIRE 80 400 -128 400
+WIRE 208 400 80 400
 WIRE -336 432 -336 400
 FLAG -336 432 0
 SYMBOL voltage -368 176 R0
 WINDOW 3 -65 -79 VRight 2
 WINDOW 123 0 0 Left 0
 WINDOW 39 0 0 Left 0
-SYMATTR Value PULSE(0 420 1 1<EFBFBD> 1<> 2 3 1)
+SYMATTR Value PULSE(0 400 1m 100u 100u 1 1)
 SYMATTR InstName V1
-SYMBOL cap 256 224 R0
+SYMBOL cap 448 208 R0
 SYMATTR InstName C1
-SYMATTR Value 44<EFBFBD>
-SYMBOL res -48 112 R0
+SYMATTR Value 20<EFBFBD>
+SYMBOL res -144 112 R0
 SYMATTR InstName R1
 SYMATTR Value 6.6Mega
-SYMBOL res -48 240 R0
+SYMBOL res -144 256 R0
 SYMATTR InstName R2
-SYMATTR Value 150k
-SYMBOL cap -112 272 R0
+SYMATTR Value 80k
+SYMBOL cap -240 272 R0
 SYMATTR InstName C2
-SYMATTR Value 3.3<EFBFBD>
-SYMBOL IPD60R 160 384 M0
-SYMATTR InstName U1
+SYMATTR Value 20<EFBFBD>
+SYMATTR SpiceLine Rser=0.01
+SYMBOL zener 96 352 R180
+WINDOW 0 24 64 Left 2
+WINDOW 3 24 0 Left 2
+SYMATTR InstName D1
+SYMATTR Value CDZV18B
+SYMBOL IPW60R045CP_L0 320 384 M0
+SYMATTR InstName U2
 TEXT -232 504 Left 2 !.tran 0 2 0.7 1m

Hardware/sim/precharge_sim.log

@@ -1,14 +1,15 @@
 LTspice 24.0.12 for Windows
 Circuit: * C:\Users\frede\OneDrive\Dokumente\Fasttube\FT25\TS-DCDC\Hardware\sim\precharge_sim.asc
-Start Time: Sun Mar  2 17:00:25 2025
+Start Time: Tue Apr  8 22:26:57 2025
 solver = Normal
 Maximum thread count: 8
 tnom = 27
 temp = 27
 method = modified trap
-Instance "m:u1:1:r": Length shorter than recommended for a level 1 MOSFET.
-Instance "m:u1:1:r": Width narrower than recommended for a level 1 MOSFET.
-Instance "m:u1:1:1": Width narrower than recommended for a level 3 MOSFET.
+WARNING: Specified period is not longer than the sum of Trise, Tfall, and Ton for v1.  Increasing period to 1.0002
+Instance "m:u2:r": Length shorter than recommended for a level 1 MOSFET.
+Instance "m:u2:r": Width narrower than recommended for a level 1 MOSFET.
+Instance "m:u2:1": Width narrower than recommended for a level 3 MOSFET.
 .OP point found by inspection.
-Total elapsed time: 0.097 seconds.
+Total elapsed time: 0.129 seconds.
 

Hardware/sim/sim_gpt.asc

@@ -0,0 +1,57 @@
+Version 4
+SHEET 1 880 680
+WIRE 96 80 48 80
+WIRE 224 80 176 80
+WIRE 224 144 224 80
+WIRE 96 160 96 80
+WIRE 224 160 96 160
+WIRE 96 208 96 160
+WIRE 224 208 224 160
+WIRE 224 256 224 208
+WIRE 224 256 96 256
+WIRE 96 256 96 208
+WIRE 96 304 96 256
+WIRE 96 304 48 304
+WIRE 224 304 224 256
+WIRE 224 304 272 304
+WIRE 272 304 272 160
+WIRE 272 160 304 160
+WIRE 96 160 48 160
+WIRE 48 160 48 80
+WIRE 304 160 304 80
+WIRE 304 80 224 80
+WIRE 96 304 96 352
+WIRE 96 352 224 352
+WIRE 224 352 224 304
+WIRE 224 160 272 160
+WIRE 272 160 272 96
+WIRE 272 96 352 96
+WIRE 352 96 352 304
+WIRE 352 304 304 304
+WIRE 304 304 304 160
+FLAG 48 304 0
+FLAG 352 304 0
+SYMBOL voltage 48 64 R0
+WINDOW 3 24 120 Left 2
+SYMATTR InstName V1
+SYMATTR Value 403
+SYMBOL cap 208 208 R0
+SYMATTR InstName C1
+SYMATTR Value 20u
+SYMBOL nmos 96 208 R270
+WINDOW 0 32 80 VBottom 0
+WINDOW 3 32 32 VTop 0
+SYMATTR InstName M1
+SYMATTR Value IPW60R045CPA
+SYMATTR Value2 IPW60R045CPA
+SYMATTR SpiceLine Rg=0
+SYMBOL res 272 80 R0
+SYMATTR InstName R1
+SYMATTR Value 100k
+SYMBOL res 304 144 R270
+SYMATTR InstName R2
+SYMATTR Value 3.3k
+SYMBOL cap 96 64 R270
+SYMATTR InstName C2
+SYMATTR Value 220n
+.END