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2022-01-17 00:41:01 +01:00
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2022-01-17 00:41:01 +01:00
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2021-12-16 15:38:42 +01:00
2022-01-17 00:41:01 +01:00
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2021-12-16 15:32:44 +01:00
2022-01-17 00:41:01 +01:00
2021-12-16 15:38:42 +01:00
2022-01-17 00:41:01 +01:00
2022-01-17 00:41:01 +01:00
2022-01-17 00:41:01 +01:00
2021-12-16 15:38:42 +01:00

SDCL

Shutdown Circuit Logic

Allows for the AS to control SDC closure/opening under certain circumstances using hard-wired logic.

Description
Shutdown Circuit Logic allows for the AS to close/open the SDC under certain circumstances using hard-wired logic. The PCB also facilitates EBS supervision monitoring, TSstart MUXing, and includes a mini AMI, buttons and indicators.
Readme 25 MiB
Languages
C 99.7%
Assembly 0.3%