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Re-added test function

This commit is contained in:
n.jayaprakash 2024-05-22 17:20:44 +02:00
parent b6758082eb
commit 5468095a79
32 changed files with 10 additions and 163125 deletions
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2
.gitignore vendored
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@ -1,3 +1,5 @@
build/
# ---> C
# Prerequisites
*.d

15
Core/Src/Channel_Control.c
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@ -39,13 +39,14 @@ void ChannelControl_UpdateGPIOs(PortExtenderGPIO UpdatePorts) { // ctrl + left c
PCA9535_setGPIOPortOutput(PC9535_PORTA, UpdatePorts.porta.porta);
PCA9535_setGPIOPortOutput(PC9535_PORTB, UpdatePorts.portb.portb);
UpdatePorts.porta.alwayson = 1;
// gpio_port_b testb={}; (testing code)
//testb.en16=1; (testing code)
//PCA9535_setGPIOPortOutput(PC9535_PORTB, testb.portb); (testing code)
// gpio_port_a testa={}; (testing code)
// testa.en1=1; (testing code)
// testa.en13=1; (testing code)
// PCA9535_setGPIOPortOutput(PC9535_PORTA, testa.porta); (testing code)
gpio_port_b testb={}; //(testing code)
testb.en16=1; //(testing code)
PCA9535_setGPIOPortOutput(PC9535_PORTB, testb.portb); //(testing code)
gpio_port_a testa={}; //(testing code)
testa.en1=1; //(testing code)
testa.en13=1; // (testing code)
PCA9535_setGPIOPortOutput(PC9535_PORTA, testa.porta); //(testing code)
}
void ChannelControl_UpdatePWMs(uint8_t radiatorfans,uint8_t tsacfans , uint8_t pwmaggregat,

403
build/CAN_Communication.lst
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@ -1,403 +0,0 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "CAN_Communication.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/CAN_Communication.c"
20 .section .text.can_init,"ax",%progbits
21 .align 1
22 .global can_init
23 .syntax unified
24 .thumb
25 .thumb_func
27 can_init:
28 .LVL0:
29 .LFB130:
1:Core/Src/CAN_Communication.c **** /*
2:Core/Src/CAN_Communication.c **** * CAN_Communication.c
3:Core/Src/CAN_Communication.c **** *
4:Core/Src/CAN_Communication.c **** * Created on: 24. April, 2024
5:Core/Src/CAN_Communication.c **** * Author: nived
6:Core/Src/CAN_Communication.c **** */
7:Core/Src/CAN_Communication.c **** #include "CAN_Communication.h"
8:Core/Src/CAN_Communication.c **** #include "Channel_Control.h"
9:Core/Src/CAN_Communication.c **** #include "Current_Monitoring.h"
10:Core/Src/CAN_Communication.c ****
11:Core/Src/CAN_Communication.c **** rx_status_frame rxstate = {};
12:Core/Src/CAN_Communication.c **** volatile uint8_t canmsg_received = 0;
13:Core/Src/CAN_Communication.c **** extern PortExtenderGPIO EN_Ports;
14:Core/Src/CAN_Communication.c **** extern CurrentMeasurements current_measurements_adc_val;
15:Core/Src/CAN_Communication.c ****
16:Core/Src/CAN_Communication.c **** void can_init(CAN_HandleTypeDef* hcan) {
30 .loc 1 16 40 view -0
31 .cfi_startproc
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 .loc 1 16 40 is_stmt 0 view .LVU1
35 0000 08B5 push {r3, lr}
36 .cfi_def_cfa_offset 8
37 .cfi_offset 3, -8
38 .cfi_offset 14, -4
17:Core/Src/CAN_Communication.c **** ftcan_init(hcan);
39 .loc 1 17 3 is_stmt 1 view .LVU2
40 0002 FFF7FEFF bl ftcan_init
41 .LVL1:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s page 2
18:Core/Src/CAN_Communication.c **** ftcan_add_filter(0x00, 0x00); // No Filter
42 .loc 1 18 3 view .LVU3
43 0006 0021 movs r1, #0
44 0008 0846 mov r0, r1
45 000a FFF7FEFF bl ftcan_add_filter
46 .LVL2:
19:Core/Src/CAN_Communication.c **** }
47 .loc 1 19 1 is_stmt 0 view .LVU4
48 000e 08BD pop {r3, pc}
49 .cfi_endproc
50 .LFE130:
52 .section .text.can_sendloop,"ax",%progbits
53 .align 1
54 .global can_sendloop
55 .syntax unified
56 .thumb
57 .thumb_func
59 can_sendloop:
60 .LFB131:
20:Core/Src/CAN_Communication.c ****
21:Core/Src/CAN_Communication.c **** void can_sendloop() {
61 .loc 1 21 21 is_stmt 1 view -0
62 .cfi_startproc
63 @ args = 0, pretend = 0, frame = 8
64 @ frame_needed = 0, uses_anonymous_args = 0
65 0000 00B5 push {lr}
66 .cfi_def_cfa_offset 4
67 .cfi_offset 14, -4
68 0002 83B0 sub sp, sp, #12
69 .cfi_def_cfa_offset 16
22:Core/Src/CAN_Communication.c **** static uint8_t additionaltxcouter = 0;
70 .loc 1 22 3 view .LVU6
23:Core/Src/CAN_Communication.c ****
24:Core/Src/CAN_Communication.c **** uint8_t status_data[7];
71 .loc 1 24 3 view .LVU7
25:Core/Src/CAN_Communication.c **** status_data[0] = EN_Ports.porta.porta;
72 .loc 1 25 3 view .LVU8
73 .loc 1 25 34 is_stmt 0 view .LVU9
74 0004 0F4B ldr r3, .L5
75 0006 1A78 ldrb r2, [r3] @ zero_extendqisi2
76 .loc 1 25 18 view .LVU10
77 0008 8DF80020 strb r2, [sp]
26:Core/Src/CAN_Communication.c **** status_data[1] = EN_Ports.portb.portb;
78 .loc 1 26 3 is_stmt 1 view .LVU11
79 .loc 1 26 34 is_stmt 0 view .LVU12
80 000c 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2
81 .loc 1 26 18 view .LVU13
82 000e 8DF80130 strb r3, [sp, #1]
27:Core/Src/CAN_Communication.c **** status_data[2] = rxstate.tsacfans;
83 .loc 1 27 3 is_stmt 1 view .LVU14
84 .loc 1 27 27 is_stmt 0 view .LVU15
85 0012 0D4B ldr r3, .L5+4
86 0014 DA78 ldrb r2, [r3, #3] @ zero_extendqisi2
87 .loc 1 27 18 view .LVU16
88 0016 8DF80220 strb r2, [sp, #2]
28:Core/Src/CAN_Communication.c **** status_data[3] = rxstate.radiatorfans;
89 .loc 1 28 3 is_stmt 1 view .LVU17
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s page 3
90 .loc 1 28 27 is_stmt 0 view .LVU18
91 001a 9A78 ldrb r2, [r3, #2] @ zero_extendqisi2
92 .loc 1 28 18 view .LVU19
93 001c 8DF80320 strb r2, [sp, #3]
29:Core/Src/CAN_Communication.c **** status_data[4] = rxstate.pwmaggregat;
94 .loc 1 29 3 is_stmt 1 view .LVU20
95 .loc 1 29 27 is_stmt 0 view .LVU21
96 0020 1A79 ldrb r2, [r3, #4] @ zero_extendqisi2
97 .loc 1 29 18 view .LVU22
98 0022 8DF80420 strb r2, [sp, #4]
30:Core/Src/CAN_Communication.c **** status_data[5] = rxstate.cooling_pump;
99 .loc 1 30 3 is_stmt 1 view .LVU23
100 .loc 1 30 27 is_stmt 0 view .LVU24
101 0026 5A79 ldrb r2, [r3, #5] @ zero_extendqisi2
102 .loc 1 30 18 view .LVU25
103 0028 8DF80520 strb r2, [sp, #5]
31:Core/Src/CAN_Communication.c **** status_data[6] = 0xFF ^ rxstate.checksum;
104 .loc 1 31 3 is_stmt 1 view .LVU26
105 .loc 1 31 34 is_stmt 0 view .LVU27
106 002c 9B79 ldrb r3, [r3, #6] @ zero_extendqisi2
107 .loc 1 31 18 view .LVU28
108 002e DB43 mvns r3, r3
109 0030 8DF80630 strb r3, [sp, #6]
32:Core/Src/CAN_Communication.c **** ftcan_transmit(TX_STATUS_MSG_ID, status_data, 7);
110 .loc 1 32 3 is_stmt 1 view .LVU29
111 0034 0722 movs r2, #7
112 0036 6946 mov r1, sp
113 0038 C920 movs r0, #201
114 003a FFF7FEFF bl ftcan_transmit
115 .LVL3:
33:Core/Src/CAN_Communication.c ****
34:Core/Src/CAN_Communication.c **** uint8_t data[8];
116 .loc 1 34 3 view .LVU30
35:Core/Src/CAN_Communication.c **** return;
117 .loc 1 35 1 view .LVU31
36:Core/Src/CAN_Communication.c **** if (additionaltxcouter < 4) {
37:Core/Src/CAN_Communication.c **** switch (additionaltxcouter) {
38:Core/Src/CAN_Communication.c **** case 0:
39:Core/Src/CAN_Communication.c ****
40:Core/Src/CAN_Communication.c **** data[0] = current_measurements_adc_val.always_on >> 8;
41:Core/Src/CAN_Communication.c **** data[1] = current_measurements_adc_val.always_on & 0xFF;
42:Core/Src/CAN_Communication.c **** data[2] = current_measurements_adc_val.misc >> 8;
43:Core/Src/CAN_Communication.c **** data[3] = current_measurements_adc_val.misc & 0xFF;
44:Core/Src/CAN_Communication.c **** data[4] = current_measurements_adc_val.inverters >> 8;
45:Core/Src/CAN_Communication.c **** data[5] = current_measurements_adc_val.inverters & 0xFF;
46:Core/Src/CAN_Communication.c **** data[6] = current_measurements_adc_val.sdc >> 8;
47:Core/Src/CAN_Communication.c **** data[7] = current_measurements_adc_val.sdc & 0xFF;
48:Core/Src/CAN_Communication.c **** ftcan_transmit(CUR_CHANNELS_1_ID, data, 8);
49:Core/Src/CAN_Communication.c ****
50:Core/Src/CAN_Communication.c **** break;
51:Core/Src/CAN_Communication.c **** case 1:
52:Core/Src/CAN_Communication.c ****
53:Core/Src/CAN_Communication.c **** data[0] = current_measurements_adc_val.tsac_fans >> 8;
54:Core/Src/CAN_Communication.c **** data[1] = current_measurements_adc_val.tsac_fans & 0xFF;
55:Core/Src/CAN_Communication.c **** data[2] = current_measurements_adc_val.cooling_pump >> 8;
56:Core/Src/CAN_Communication.c **** data[3] = current_measurements_adc_val.cooling_pump & 0xFF;
57:Core/Src/CAN_Communication.c **** data[4] = current_measurements_adc_val.aggregat >> 8;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s page 4
58:Core/Src/CAN_Communication.c **** data[5] = current_measurements_adc_val.aggregat & 0xFF;
59:Core/Src/CAN_Communication.c **** data[6] = current_measurements_adc_val.epsc >> 8;
60:Core/Src/CAN_Communication.c **** data[7] = current_measurements_adc_val.epsc & 0xFF;
61:Core/Src/CAN_Communication.c **** ftcan_transmit(CUR_CHANNELS_2_ID, data, 8);
62:Core/Src/CAN_Communication.c ****
63:Core/Src/CAN_Communication.c **** break;
64:Core/Src/CAN_Communication.c **** case 2:
65:Core/Src/CAN_Communication.c ****
66:Core/Src/CAN_Communication.c **** data[0] = current_measurements_adc_val.ebsvalve_a >> 8;
67:Core/Src/CAN_Communication.c **** data[1] = current_measurements_adc_val.ebsvalve_a & 0xFF;
68:Core/Src/CAN_Communication.c **** data[2] = current_measurements_adc_val.ebsvalve_b >> 8;
69:Core/Src/CAN_Communication.c **** data[3] = current_measurements_adc_val.ebsvalve_b & 0xFF;
70:Core/Src/CAN_Communication.c **** data[4] = current_measurements_adc_val.ebs_cs_valve >> 8;
71:Core/Src/CAN_Communication.c **** data[5] = current_measurements_adc_val.ebs_cs_valve & 0xFF;
72:Core/Src/CAN_Communication.c **** data[6] = current_measurements_adc_val.gss >> 8;
73:Core/Src/CAN_Communication.c **** data[7] = current_measurements_adc_val.gss & 0xFF;
74:Core/Src/CAN_Communication.c **** ftcan_transmit(CUR_CHANNELS_3_ID, data, 8);
75:Core/Src/CAN_Communication.c ****
76:Core/Src/CAN_Communication.c **** break;
77:Core/Src/CAN_Communication.c **** case 3:
78:Core/Src/CAN_Communication.c ****
79:Core/Src/CAN_Communication.c **** data[0] = current_measurements_adc_val.radiator_fans >> 8;
80:Core/Src/CAN_Communication.c **** data[1] = current_measurements_adc_val.radiator_fans & 0xFF;
81:Core/Src/CAN_Communication.c **** data[2] = current_measurements_adc_val.acu >> 8;
82:Core/Src/CAN_Communication.c **** data[3] = current_measurements_adc_val.acu & 0xFF;
83:Core/Src/CAN_Communication.c **** data[4] = current_measurements_adc_val.servos >> 8;
84:Core/Src/CAN_Communication.c **** data[5] = current_measurements_adc_val.servos & 0xFF;
85:Core/Src/CAN_Communication.c **** data[6] = current_measurements_adc_val.lidar >> 8;
86:Core/Src/CAN_Communication.c **** data[7] = current_measurements_adc_val.lidar & 0xFF;
87:Core/Src/CAN_Communication.c **** ftcan_transmit(CUR_CHANNELS_4_ID, data, 8);
88:Core/Src/CAN_Communication.c ****
89:Core/Src/CAN_Communication.c **** break;
90:Core/Src/CAN_Communication.c **** default:
91:Core/Src/CAN_Communication.c **** break;
92:Core/Src/CAN_Communication.c **** }
93:Core/Src/CAN_Communication.c **** additionaltxcouter++;
94:Core/Src/CAN_Communication.c **** } else {
95:Core/Src/CAN_Communication.c **** additionaltxcouter = 0;
96:Core/Src/CAN_Communication.c **** }
97:Core/Src/CAN_Communication.c **** }
118 .loc 1 97 1 is_stmt 0 view .LVU32
119 003e 03B0 add sp, sp, #12
120 .cfi_def_cfa_offset 4
121 @ sp needed
122 0040 5DF804FB ldr pc, [sp], #4
123 .L6:
124 .align 2
125 .L5:
126 0044 00000000 .word EN_Ports
127 0048 00000000 .word rxstate
128 .cfi_endproc
129 .LFE131:
131 .section .text.ftcan_msg_received_cb,"ax",%progbits
132 .align 1
133 .global ftcan_msg_received_cb
134 .syntax unified
135 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s page 5
136 .thumb_func
138 ftcan_msg_received_cb:
139 .LVL4:
140 .LFB132:
98:Core/Src/CAN_Communication.c ****
99:Core/Src/CAN_Communication.c **** void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data) {
141 .loc 1 99 78 is_stmt 1 view -0
142 .cfi_startproc
143 @ args = 0, pretend = 0, frame = 0
144 @ frame_needed = 0, uses_anonymous_args = 0
145 @ link register save eliminated.
100:Core/Src/CAN_Communication.c **** canmsg_received = 1;
146 .loc 1 100 3 view .LVU34
147 .loc 1 100 19 is_stmt 0 view .LVU35
148 0000 0C4B ldr r3, .L10
149 0002 4FF0010C mov ip, #1
150 0006 83F800C0 strb ip, [r3]
101:Core/Src/CAN_Communication.c **** if ((id == RX_STATUS_MSG_ID) && (datalen == 7)) {
151 .loc 1 101 3 is_stmt 1 view .LVU36
152 .loc 1 101 6 is_stmt 0 view .LVU37
153 000a C828 cmp r0, #200
154 000c 00D0 beq .L9
155 .LVL5:
156 .L7:
102:Core/Src/CAN_Communication.c **** rxstate.iostatus.porta.porta = data[0];
103:Core/Src/CAN_Communication.c **** rxstate.iostatus.portb.portb = data[1];
104:Core/Src/CAN_Communication.c **** rxstate.radiatorfans = data[2];
105:Core/Src/CAN_Communication.c **** rxstate.tsacfans = data[3];
106:Core/Src/CAN_Communication.c **** rxstate.pwmaggregat = data[4];
107:Core/Src/CAN_Communication.c **** rxstate.cooling_pump = data[5];
108:Core/Src/CAN_Communication.c **** rxstate.checksum = data[6];
109:Core/Src/CAN_Communication.c **** }
110:Core/Src/CAN_Communication.c **** }
157 .loc 1 110 1 view .LVU38
158 000e 7047 bx lr
159 .LVL6:
160 .L9:
101:Core/Src/CAN_Communication.c **** if ((id == RX_STATUS_MSG_ID) && (datalen == 7)) {
161 .loc 1 101 32 discriminator 1 view .LVU39
162 0010 0729 cmp r1, #7
163 0012 FCD1 bne .L7
102:Core/Src/CAN_Communication.c **** rxstate.iostatus.porta.porta = data[0];
164 .loc 1 102 5 is_stmt 1 view .LVU40
102:Core/Src/CAN_Communication.c **** rxstate.iostatus.porta.porta = data[0];
165 .loc 1 102 40 is_stmt 0 view .LVU41
166 0014 1178 ldrb r1, [r2] @ zero_extendqisi2
167 .LVL7:
102:Core/Src/CAN_Communication.c **** rxstate.iostatus.porta.porta = data[0];
168 .loc 1 102 34 view .LVU42
169 0016 084B ldr r3, .L10+4
170 0018 1970 strb r1, [r3]
103:Core/Src/CAN_Communication.c **** rxstate.radiatorfans = data[2];
171 .loc 1 103 5 is_stmt 1 view .LVU43
103:Core/Src/CAN_Communication.c **** rxstate.radiatorfans = data[2];
172 .loc 1 103 40 is_stmt 0 view .LVU44
173 001a 5178 ldrb r1, [r2, #1] @ zero_extendqisi2
103:Core/Src/CAN_Communication.c **** rxstate.radiatorfans = data[2];
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s page 6
174 .loc 1 103 34 view .LVU45
175 001c 5970 strb r1, [r3, #1]
104:Core/Src/CAN_Communication.c **** rxstate.tsacfans = data[3];
176 .loc 1 104 5 is_stmt 1 view .LVU46
104:Core/Src/CAN_Communication.c **** rxstate.tsacfans = data[3];
177 .loc 1 104 32 is_stmt 0 view .LVU47
178 001e 9178 ldrb r1, [r2, #2] @ zero_extendqisi2
104:Core/Src/CAN_Communication.c **** rxstate.tsacfans = data[3];
179 .loc 1 104 26 view .LVU48
180 0020 9970 strb r1, [r3, #2]
105:Core/Src/CAN_Communication.c **** rxstate.pwmaggregat = data[4];
181 .loc 1 105 5 is_stmt 1 view .LVU49
105:Core/Src/CAN_Communication.c **** rxstate.pwmaggregat = data[4];
182 .loc 1 105 28 is_stmt 0 view .LVU50
183 0022 D178 ldrb r1, [r2, #3] @ zero_extendqisi2
105:Core/Src/CAN_Communication.c **** rxstate.pwmaggregat = data[4];
184 .loc 1 105 22 view .LVU51
185 0024 D970 strb r1, [r3, #3]
106:Core/Src/CAN_Communication.c **** rxstate.cooling_pump = data[5];
186 .loc 1 106 5 is_stmt 1 view .LVU52
106:Core/Src/CAN_Communication.c **** rxstate.cooling_pump = data[5];
187 .loc 1 106 31 is_stmt 0 view .LVU53
188 0026 1179 ldrb r1, [r2, #4] @ zero_extendqisi2
106:Core/Src/CAN_Communication.c **** rxstate.cooling_pump = data[5];
189 .loc 1 106 25 view .LVU54
190 0028 1971 strb r1, [r3, #4]
107:Core/Src/CAN_Communication.c **** rxstate.checksum = data[6];
191 .loc 1 107 5 is_stmt 1 view .LVU55
107:Core/Src/CAN_Communication.c **** rxstate.checksum = data[6];
192 .loc 1 107 32 is_stmt 0 view .LVU56
193 002a 5179 ldrb r1, [r2, #5] @ zero_extendqisi2
107:Core/Src/CAN_Communication.c **** rxstate.checksum = data[6];
194 .loc 1 107 26 view .LVU57
195 002c 5971 strb r1, [r3, #5]
108:Core/Src/CAN_Communication.c **** }
196 .loc 1 108 5 is_stmt 1 view .LVU58
108:Core/Src/CAN_Communication.c **** }
197 .loc 1 108 28 is_stmt 0 view .LVU59
198 002e 9279 ldrb r2, [r2, #6] @ zero_extendqisi2
199 .LVL8:
108:Core/Src/CAN_Communication.c **** }
200 .loc 1 108 22 view .LVU60
201 0030 9A71 strb r2, [r3, #6]
202 .loc 1 110 1 view .LVU61
203 0032 ECE7 b .L7
204 .L11:
205 .align 2
206 .L10:
207 0034 00000000 .word canmsg_received
208 0038 00000000 .word rxstate
209 .cfi_endproc
210 .LFE132:
212 .global canmsg_received
213 .section .bss.canmsg_received,"aw",%nobits
216 canmsg_received:
217 0000 00 .space 1
218 .global rxstate
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s page 7
219 .section .bss.rxstate,"aw",%nobits
220 .align 2
223 rxstate:
224 0000 00000000 .space 8
224 00000000
225 .text
226 .Letext0:
227 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
228 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
229 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
230 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
231 .file 6 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
232 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
233 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h"
234 .file 9 "Core/Inc/Channel_Control.h"
235 .file 10 "Core/Inc/CAN_Communication.h"
236 .file 11 "Core/Inc/can-halal.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s page 8
DEFINED SYMBOLS
*ABS*:00000000 CAN_Communication.c
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:21 .text.can_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:27 .text.can_init:00000000 can_init
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:53 .text.can_sendloop:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:59 .text.can_sendloop:00000000 can_sendloop
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:126 .text.can_sendloop:00000044 $d
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:223 .bss.rxstate:00000000 rxstate
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:132 .text.ftcan_msg_received_cb:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:138 .text.ftcan_msg_received_cb:00000000 ftcan_msg_received_cb
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:207 .text.ftcan_msg_received_cb:00000034 $d
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:216 .bss.canmsg_received:00000000 canmsg_received
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:217 .bss.canmsg_received:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccbPzwCp.s:220 .bss.rxstate:00000000 $d
UNDEFINED SYMBOLS
ftcan_init
ftcan_add_filter
ftcan_transmit
EN_Ports

517
build/Channel_Control.lst
View File

@ -1,517 +0,0 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "Channel_Control.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/Channel_Control.c"
20 .section .text.ChannelControl_UpdateGPIOs,"ax",%progbits
21 .align 1
22 .global ChannelControl_UpdateGPIOs
23 .syntax unified
24 .thumb
25 .thumb_func
27 ChannelControl_UpdateGPIOs:
28 .LVL0:
29 .LFB131:
1:Core/Src/Channel_Control.c **** /*
2:Core/Src/Channel_Control.c **** * Channel_Control.c
3:Core/Src/Channel_Control.c **** *
4:Core/Src/Channel_Control.c **** * Created on: 24. April, 2024
5:Core/Src/Channel_Control.c **** * Author: nived
6:Core/Src/Channel_Control.c **** */
7:Core/Src/Channel_Control.c ****
8:Core/Src/Channel_Control.c **** #include "Channel_Control.h"
9:Core/Src/Channel_Control.c **** #include "PCA9535D_Driver.h"
10:Core/Src/Channel_Control.c ****
11:Core/Src/Channel_Control.c **** PortExtenderGPIO EN_Ports;
12:Core/Src/Channel_Control.c ****
13:Core/Src/Channel_Control.c **** uint8_t timer3_running = 0;
14:Core/Src/Channel_Control.c **** uint8_t timer2_running = 0;
15:Core/Src/Channel_Control.c **** TIM_HandleTypeDef* pwmtimer3;
16:Core/Src/Channel_Control.c **** TIM_HandleTypeDef* pwmtimer2;
17:Core/Src/Channel_Control.c ****
18:Core/Src/Channel_Control.c **** void ChannelControl_init(I2C_HandleTypeDef* hi2c, TIM_HandleTypeDef* timer3,
19:Core/Src/Channel_Control.c **** TIM_HandleTypeDef* timer2) {
20:Core/Src/Channel_Control.c ****
21:Core/Src/Channel_Control.c **** pwmtimer3 = timer3;
22:Core/Src/Channel_Control.c **** pwmtimer2 = timer2;
23:Core/Src/Channel_Control.c **** PCA9535_init(hi2c, 0);
24:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTA, 0x00);
25:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTB, 0x00);
26:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortDirection(PC9535_PORTA, 0x00);
27:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortDirection(PC9535_PORTB, 0x00);
28:Core/Src/Channel_Control.c ****
29:Core/Src/Channel_Control.c **** EN_Ports.porta.porta = 0;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 2
30:Core/Src/Channel_Control.c **** EN_Ports.portb.portb = 0;
31:Core/Src/Channel_Control.c **** EN_Ports.porta.alwayson = 1;
32:Core/Src/Channel_Control.c **** ChannelControl_UpdateGPIOs(EN_Ports);
33:Core/Src/Channel_Control.c **** ChannelControl_UpdatePWMs(0, 0, 0, 0);
34:Core/Src/Channel_Control.c **** }
35:Core/Src/Channel_Control.c ****
36:Core/Src/Channel_Control.c **** void ChannelControl_UpdateGPIOs(PortExtenderGPIO UpdatePorts) { // ctrl + left click auf portextend
30 .loc 1 36 63 view -0
31 .cfi_startproc
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 .loc 1 36 63 is_stmt 0 view .LVU1
35 0000 10B5 push {r4, lr}
36 .cfi_def_cfa_offset 8
37 .cfi_offset 4, -8
38 .cfi_offset 14, -4
37:Core/Src/Channel_Control.c **** EN_Ports = UpdatePorts;
39 .loc 1 37 3 is_stmt 1 view .LVU2
40 .loc 1 37 12 is_stmt 0 view .LVU3
41 0002 074B ldr r3, .L3
42 0004 1880 strh r0, [r3] @ movhi
38:Core/Src/Channel_Control.c **** UpdatePorts.porta.alwayson = 1;// Always on stays always on
43 .loc 1 38 3 is_stmt 1 view .LVU4
44 .loc 1 38 30 is_stmt 0 view .LVU5
45 0006 40F08004 orr r4, r0, #128
39:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTA, UpdatePorts.porta.porta);
46 .loc 1 39 2 is_stmt 1 view .LVU6
47 000a E1B2 uxtb r1, r4
48 000c 0020 movs r0, #0
49 .LVL1:
50 .loc 1 39 2 is_stmt 0 view .LVU7
51 000e FFF7FEFF bl PCA9535_setGPIOPortOutput
52 .LVL2:
40:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTB, UpdatePorts.portb.portb);
53 .loc 1 40 2 is_stmt 1 view .LVU8
54 0012 C4F30721 ubfx r1, r4, #8, #8
55 0016 0120 movs r0, #1
56 0018 FFF7FEFF bl PCA9535_setGPIOPortOutput
57 .LVL3:
41:Core/Src/Channel_Control.c **** UpdatePorts.porta.alwayson = 1;
58 .loc 1 41 3 view .LVU9
42:Core/Src/Channel_Control.c **** // gpio_port_b testb={}; (testing code)
43:Core/Src/Channel_Control.c **** //testb.en16=1; (testing code)
44:Core/Src/Channel_Control.c **** //PCA9535_setGPIOPortOutput(PC9535_PORTB, testb.portb); (testing code)
45:Core/Src/Channel_Control.c **** // gpio_port_a testa={}; (testing code)
46:Core/Src/Channel_Control.c **** // testa.en1=1; (testing code)
47:Core/Src/Channel_Control.c **** // testa.en13=1; (testing code)
48:Core/Src/Channel_Control.c **** // PCA9535_setGPIOPortOutput(PC9535_PORTA, testa.porta); (testing code)
49:Core/Src/Channel_Control.c **** }
59 .loc 1 49 1 is_stmt 0 view .LVU10
60 001c 10BD pop {r4, pc}
61 .L4:
62 001e 00BF .align 2
63 .L3:
64 0020 00000000 .word EN_Ports
65 .cfi_endproc
66 .LFE131:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 3
68 .section .text.ChannelControl_UpdatePWMs,"ax",%progbits
69 .align 1
70 .global ChannelControl_UpdatePWMs
71 .syntax unified
72 .thumb
73 .thumb_func
75 ChannelControl_UpdatePWMs:
76 .LVL4:
77 .LFB132:
50:Core/Src/Channel_Control.c ****
51:Core/Src/Channel_Control.c **** void ChannelControl_UpdatePWMs(uint8_t radiatorfans,uint8_t tsacfans , uint8_t pwmaggregat,
52:Core/Src/Channel_Control.c **** uint8_t pwmpumps){
78 .loc 1 52 49 is_stmt 1 view -0
79 .cfi_startproc
80 @ args = 0, pretend = 0, frame = 0
81 @ frame_needed = 0, uses_anonymous_args = 0
82 .loc 1 52 49 is_stmt 0 view .LVU12
83 0000 38B5 push {r3, r4, r5, lr}
84 .cfi_def_cfa_offset 16
85 .cfi_offset 3, -16
86 .cfi_offset 4, -12
87 .cfi_offset 5, -8
88 .cfi_offset 14, -4
89 0002 0246 mov r2, r0
90 .LVL5:
91 .loc 1 52 49 view .LVU13
92 0004 0C46 mov r4, r1
53:Core/Src/Channel_Control.c ****
54:Core/Src/Channel_Control.c ****
55:Core/Src/Channel_Control.c **** pwmtimer3->Instance->CCR4 = pwmpumps << 8;
93 .loc 1 55 3 is_stmt 1 view .LVU14
94 .loc 1 55 12 is_stmt 0 view .LVU15
95 0006 2249 ldr r1, .L13
96 .LVL6:
97 .loc 1 55 12 view .LVU16
98 0008 0868 ldr r0, [r1]
99 .LVL7:
100 .loc 1 55 12 view .LVU17
101 000a 0168 ldr r1, [r0]
102 .loc 1 55 40 view .LVU18
103 000c 1D02 lsls r5, r3, #8
104 .loc 1 55 29 view .LVU19
105 000e 0D64 str r5, [r1, #64]
56:Core/Src/Channel_Control.c **** pwmtimer3->Instance->CCR1 = radiatorfans << 8;
106 .loc 1 56 3 is_stmt 1 view .LVU20
107 .loc 1 56 12 is_stmt 0 view .LVU21
108 0010 0168 ldr r1, [r0]
109 .loc 1 56 44 view .LVU22
110 0012 1502 lsls r5, r2, #8
111 .loc 1 56 29 view .LVU23
112 0014 4D63 str r5, [r1, #52]
57:Core/Src/Channel_Control.c **** pwmtimer2->Instance->CCR2 = tsacfans << 8;
113 .loc 1 57 3 is_stmt 1 view .LVU24
114 .loc 1 57 12 is_stmt 0 view .LVU25
115 0016 1F49 ldr r1, .L13+4
116 0018 0968 ldr r1, [r1]
117 001a 0968 ldr r1, [r1]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 4
118 .loc 1 57 40 view .LVU26
119 001c 2502 lsls r5, r4, #8
120 .loc 1 57 29 view .LVU27
121 001e 8D63 str r5, [r1, #56]
58:Core/Src/Channel_Control.c ****
59:Core/Src/Channel_Control.c **** if (timer3_running) {
122 .loc 1 59 3 is_stmt 1 view .LVU28
123 .loc 1 59 7 is_stmt 0 view .LVU29
124 0020 1D49 ldr r1, .L13+8
125 0022 0978 ldrb r1, [r1] @ zero_extendqisi2
126 .loc 1 59 6 view .LVU30
127 0024 69B1 cbz r1, .L6
60:Core/Src/Channel_Control.c **** if ((pwmpumps == 0) && (radiatorfans == 0)) {
128 .loc 1 60 5 is_stmt 1 view .LVU31
129 .loc 1 60 8 is_stmt 0 view .LVU32
130 0026 CBB9 cbnz r3, .L7
131 .loc 1 60 25 discriminator 1 view .LVU33
132 0028 C2B9 cbnz r2, .L7
61:Core/Src/Channel_Control.c **** timer3_running = 0;
133 .loc 1 61 7 is_stmt 1 view .LVU34
134 .loc 1 61 22 is_stmt 0 view .LVU35
135 002a 0025 movs r5, #0
136 002c 1A4B ldr r3, .L13+8
137 .LVL8:
138 .loc 1 61 22 view .LVU36
139 002e 1D70 strb r5, [r3]
62:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer3, TIM_CHANNEL_4);
140 .loc 1 62 7 is_stmt 1 view .LVU37
141 0030 0C21 movs r1, #12
142 0032 FFF7FEFF bl HAL_TIM_PWM_Stop
143 .LVL9:
63:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer3, TIM_CHANNEL_1);
144 .loc 1 63 7 view .LVU38
145 0036 2946 mov r1, r5
146 0038 154B ldr r3, .L13
147 003a 1868 ldr r0, [r3]
148 003c FFF7FEFF bl HAL_TIM_PWM_Stop
149 .LVL10:
150 0040 0CE0 b .L7
151 .LVL11:
152 .L6:
64:Core/Src/Channel_Control.c **** }
65:Core/Src/Channel_Control.c **** } else {
66:Core/Src/Channel_Control.c **** if ( (pwmpumps != 0) || (radiatorfans != 0)) {
153 .loc 1 66 5 view .LVU39
154 .loc 1 66 8 is_stmt 0 view .LVU40
155 0042 03B9 cbnz r3, .L8
156 .loc 1 66 26 discriminator 1 view .LVU41
157 0044 52B1 cbz r2, .L7
158 .L8:
67:Core/Src/Channel_Control.c **** timer3_running = 1;
159 .loc 1 67 7 is_stmt 1 view .LVU42
160 .loc 1 67 22 is_stmt 0 view .LVU43
161 0046 144B ldr r3, .L13+8
162 .LVL12:
163 .loc 1 67 22 view .LVU44
164 0048 0122 movs r2, #1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 5
165 004a 1A70 strb r2, [r3]
68:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer3, TIM_CHANNEL_4);
166 .loc 1 68 7 is_stmt 1 view .LVU45
167 004c 0C21 movs r1, #12
168 004e FFF7FEFF bl HAL_TIM_PWM_Start
169 .LVL13:
69:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer3, TIM_CHANNEL_1);
170 .loc 1 69 7 view .LVU46
171 0052 0021 movs r1, #0
172 0054 0E4B ldr r3, .L13
173 0056 1868 ldr r0, [r3]
174 0058 FFF7FEFF bl HAL_TIM_PWM_Start
175 .LVL14:
176 .L7:
70:Core/Src/Channel_Control.c **** }
71:Core/Src/Channel_Control.c **** }
72:Core/Src/Channel_Control.c ****
73:Core/Src/Channel_Control.c **** if (timer2_running) {
177 .loc 1 73 3 view .LVU47
178 .loc 1 73 7 is_stmt 0 view .LVU48
179 005c 0F4B ldr r3, .L13+12
180 005e 1B78 ldrb r3, [r3] @ zero_extendqisi2
181 .loc 1 73 6 view .LVU49
182 0060 53B1 cbz r3, .L9
74:Core/Src/Channel_Control.c **** if (tsacfans == 0) {
183 .loc 1 74 5 is_stmt 1 view .LVU50
184 .loc 1 74 8 is_stmt 0 view .LVU51
185 0062 04B1 cbz r4, .L12
186 .L5:
75:Core/Src/Channel_Control.c **** timer2_running = 0;
76:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Stop(pwmtimer2, TIM_CHANNEL_2);
77:Core/Src/Channel_Control.c **** }
78:Core/Src/Channel_Control.c **** } else {
79:Core/Src/Channel_Control.c **** if (tsacfans != 0) {
80:Core/Src/Channel_Control.c **** timer2_running = 1;
81:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer2, TIM_CHANNEL_2);
82:Core/Src/Channel_Control.c **** }
83:Core/Src/Channel_Control.c **** }
84:Core/Src/Channel_Control.c ****
85:Core/Src/Channel_Control.c ****
86:Core/Src/Channel_Control.c **** }
187 .loc 1 86 1 view .LVU52
188 0064 38BD pop {r3, r4, r5, pc}
189 .L12:
75:Core/Src/Channel_Control.c **** timer2_running = 0;
190 .loc 1 75 7 is_stmt 1 view .LVU53
75:Core/Src/Channel_Control.c **** timer2_running = 0;
191 .loc 1 75 22 is_stmt 0 view .LVU54
192 0066 0D4B ldr r3, .L13+12
193 0068 0022 movs r2, #0
194 006a 1A70 strb r2, [r3]
76:Core/Src/Channel_Control.c **** }
195 .loc 1 76 7 is_stmt 1 view .LVU55
196 006c 0421 movs r1, #4
197 006e 094B ldr r3, .L13+4
198 0070 1868 ldr r0, [r3]
199 0072 FFF7FEFF bl HAL_TIM_PWM_Stop
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 6
200 .LVL15:
201 0076 F5E7 b .L5
202 .L9:
79:Core/Src/Channel_Control.c **** timer2_running = 1;
203 .loc 1 79 5 view .LVU56
79:Core/Src/Channel_Control.c **** timer2_running = 1;
204 .loc 1 79 8 is_stmt 0 view .LVU57
205 0078 002C cmp r4, #0
206 007a F3D0 beq .L5
80:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer2, TIM_CHANNEL_2);
207 .loc 1 80 7 is_stmt 1 view .LVU58
80:Core/Src/Channel_Control.c **** HAL_TIM_PWM_Start(pwmtimer2, TIM_CHANNEL_2);
208 .loc 1 80 22 is_stmt 0 view .LVU59
209 007c 074B ldr r3, .L13+12
210 007e 0122 movs r2, #1
211 0080 1A70 strb r2, [r3]
81:Core/Src/Channel_Control.c **** }
212 .loc 1 81 7 is_stmt 1 view .LVU60
213 0082 0421 movs r1, #4
214 0084 034B ldr r3, .L13+4
215 0086 1868 ldr r0, [r3]
216 0088 FFF7FEFF bl HAL_TIM_PWM_Start
217 .LVL16:
218 .loc 1 86 1 is_stmt 0 view .LVU61
219 008c EAE7 b .L5
220 .L14:
221 008e 00BF .align 2
222 .L13:
223 0090 00000000 .word pwmtimer3
224 0094 00000000 .word pwmtimer2
225 0098 00000000 .word timer3_running
226 009c 00000000 .word timer2_running
227 .cfi_endproc
228 .LFE132:
230 .section .text.ChannelControl_init,"ax",%progbits
231 .align 1
232 .global ChannelControl_init
233 .syntax unified
234 .thumb
235 .thumb_func
237 ChannelControl_init:
238 .LVL17:
239 .LFB130:
19:Core/Src/Channel_Control.c ****
240 .loc 1 19 53 is_stmt 1 view -0
241 .cfi_startproc
242 @ args = 0, pretend = 0, frame = 0
243 @ frame_needed = 0, uses_anonymous_args = 0
19:Core/Src/Channel_Control.c ****
244 .loc 1 19 53 is_stmt 0 view .LVU63
245 0000 10B5 push {r4, lr}
246 .cfi_def_cfa_offset 8
247 .cfi_offset 4, -8
248 .cfi_offset 14, -4
21:Core/Src/Channel_Control.c **** pwmtimer2 = timer2;
249 .loc 1 21 3 is_stmt 1 view .LVU64
21:Core/Src/Channel_Control.c **** pwmtimer2 = timer2;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 7
250 .loc 1 21 13 is_stmt 0 view .LVU65
251 0002 134B ldr r3, .L17
252 0004 1960 str r1, [r3]
22:Core/Src/Channel_Control.c **** PCA9535_init(hi2c, 0);
253 .loc 1 22 3 is_stmt 1 view .LVU66
22:Core/Src/Channel_Control.c **** PCA9535_init(hi2c, 0);
254 .loc 1 22 13 is_stmt 0 view .LVU67
255 0006 134B ldr r3, .L17+4
256 0008 1A60 str r2, [r3]
23:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTA, 0x00);
257 .loc 1 23 3 is_stmt 1 view .LVU68
258 000a 0021 movs r1, #0
259 .LVL18:
23:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTA, 0x00);
260 .loc 1 23 3 is_stmt 0 view .LVU69
261 000c FFF7FEFF bl PCA9535_init
262 .LVL19:
24:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortOutput(PC9535_PORTB, 0x00);
263 .loc 1 24 3 is_stmt 1 view .LVU70
264 0010 0021 movs r1, #0
265 0012 0846 mov r0, r1
266 0014 FFF7FEFF bl PCA9535_setGPIOPortOutput
267 .LVL20:
25:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortDirection(PC9535_PORTA, 0x00);
268 .loc 1 25 3 view .LVU71
269 0018 0021 movs r1, #0
270 001a 0120 movs r0, #1
271 001c FFF7FEFF bl PCA9535_setGPIOPortOutput
272 .LVL21:
26:Core/Src/Channel_Control.c **** PCA9535_setGPIOPortDirection(PC9535_PORTB, 0x00);
273 .loc 1 26 3 view .LVU72
274 0020 0021 movs r1, #0
275 0022 0846 mov r0, r1
276 0024 FFF7FEFF bl PCA9535_setGPIOPortDirection
277 .LVL22:
27:Core/Src/Channel_Control.c ****
278 .loc 1 27 3 view .LVU73
279 0028 0021 movs r1, #0
280 002a 0120 movs r0, #1
281 002c FFF7FEFF bl PCA9535_setGPIOPortDirection
282 .LVL23:
29:Core/Src/Channel_Control.c **** EN_Ports.portb.portb = 0;
283 .loc 1 29 3 view .LVU74
29:Core/Src/Channel_Control.c **** EN_Ports.portb.portb = 0;
284 .loc 1 29 24 is_stmt 0 view .LVU75
285 0030 094B ldr r3, .L17+8
286 0032 0024 movs r4, #0
287 0034 1C70 strb r4, [r3]
30:Core/Src/Channel_Control.c **** EN_Ports.porta.alwayson = 1;
288 .loc 1 30 3 is_stmt 1 view .LVU76
30:Core/Src/Channel_Control.c **** EN_Ports.porta.alwayson = 1;
289 .loc 1 30 24 is_stmt 0 view .LVU77
290 0036 5C70 strb r4, [r3, #1]
31:Core/Src/Channel_Control.c **** ChannelControl_UpdateGPIOs(EN_Ports);
291 .loc 1 31 3 is_stmt 1 view .LVU78
31:Core/Src/Channel_Control.c **** ChannelControl_UpdateGPIOs(EN_Ports);
292 .loc 1 31 27 is_stmt 0 view .LVU79
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 8
293 0038 8022 movs r2, #128
294 003a 1A70 strb r2, [r3]
32:Core/Src/Channel_Control.c **** ChannelControl_UpdatePWMs(0, 0, 0, 0);
295 .loc 1 32 3 is_stmt 1 view .LVU80
296 003c 1888 ldrh r0, [r3]
297 003e FFF7FEFF bl ChannelControl_UpdateGPIOs
298 .LVL24:
33:Core/Src/Channel_Control.c **** }
299 .loc 1 33 3 view .LVU81
300 0042 2346 mov r3, r4
301 0044 2246 mov r2, r4
302 0046 2146 mov r1, r4
303 0048 2046 mov r0, r4
304 004a FFF7FEFF bl ChannelControl_UpdatePWMs
305 .LVL25:
34:Core/Src/Channel_Control.c ****
306 .loc 1 34 1 is_stmt 0 view .LVU82
307 004e 10BD pop {r4, pc}
308 .L18:
309 .align 2
310 .L17:
311 0050 00000000 .word pwmtimer3
312 0054 00000000 .word pwmtimer2
313 0058 00000000 .word EN_Ports
314 .cfi_endproc
315 .LFE130:
317 .global pwmtimer2
318 .section .bss.pwmtimer2,"aw",%nobits
319 .align 2
322 pwmtimer2:
323 0000 00000000 .space 4
324 .global pwmtimer3
325 .section .bss.pwmtimer3,"aw",%nobits
326 .align 2
329 pwmtimer3:
330 0000 00000000 .space 4
331 .global timer2_running
332 .section .bss.timer2_running,"aw",%nobits
335 timer2_running:
336 0000 00 .space 1
337 .global timer3_running
338 .section .bss.timer3_running,"aw",%nobits
341 timer3_running:
342 0000 00 .space 1
343 .global EN_Ports
344 .section .bss.EN_Ports,"aw",%nobits
345 .align 2
348 EN_Ports:
349 0000 0000 .space 2
350 .text
351 .Letext0:
352 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
353 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
354 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
355 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
356 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
357 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 9
358 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h"
359 .file 9 "Core/Inc/Channel_Control.h"
360 .file 10 "Core/Inc/PCA9535D_Driver.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s page 10
DEFINED SYMBOLS
*ABS*:00000000 Channel_Control.c
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:21 .text.ChannelControl_UpdateGPIOs:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:27 .text.ChannelControl_UpdateGPIOs:00000000 ChannelControl_UpdateGPIOs
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:64 .text.ChannelControl_UpdateGPIOs:00000020 $d
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:348 .bss.EN_Ports:00000000 EN_Ports
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:69 .text.ChannelControl_UpdatePWMs:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:75 .text.ChannelControl_UpdatePWMs:00000000 ChannelControl_UpdatePWMs
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:223 .text.ChannelControl_UpdatePWMs:00000090 $d
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:329 .bss.pwmtimer3:00000000 pwmtimer3
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:322 .bss.pwmtimer2:00000000 pwmtimer2
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:341 .bss.timer3_running:00000000 timer3_running
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:335 .bss.timer2_running:00000000 timer2_running
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:231 .text.ChannelControl_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:237 .text.ChannelControl_init:00000000 ChannelControl_init
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:311 .text.ChannelControl_init:00000050 $d
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:319 .bss.pwmtimer2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:326 .bss.pwmtimer3:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:336 .bss.timer2_running:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:342 .bss.timer3_running:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccKLLyRV.s:345 .bss.EN_Ports:00000000 $d
UNDEFINED SYMBOLS
PCA9535_setGPIOPortOutput
HAL_TIM_PWM_Stop
HAL_TIM_PWM_Start
PCA9535_init
PCA9535_setGPIOPortDirection

841
build/Current_Monitoring.lst
View File

@ -1,841 +0,0 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "Current_Monitoring.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/Current_Monitoring.c"
20 .section .text.currentMonitor_init,"ax",%progbits
21 .align 1
22 .global currentMonitor_init
23 .syntax unified
24 .thumb
25 .thumb_func
27 currentMonitor_init:
28 .LVL0:
29 .LFB130:
1:Core/Src/Current_Monitoring.c **** /*
2:Core/Src/Current_Monitoring.c **** * Current_Monitoring.c
3:Core/Src/Current_Monitoring.c **** *
4:Core/Src/Current_Monitoring.c **** * Created on: 24. April, 2024
5:Core/Src/Current_Monitoring.c **** * Author: nived
6:Core/Src/Current_Monitoring.c **** */
7:Core/Src/Current_Monitoring.c ****
8:Core/Src/Current_Monitoring.c **** #include "Current_Monitoring.h"
9:Core/Src/Current_Monitoring.c **** #include "main.h"
10:Core/Src/Current_Monitoring.c ****
11:Core/Src/Current_Monitoring.c **** volatile union adc1_channels {
12:Core/Src/Current_Monitoring.c **** struct {
13:Core/Src/Current_Monitoring.c **** uint16_t isense12; // acu
14:Core/Src/Current_Monitoring.c **** uint16_t isense11; // epsc
15:Core/Src/Current_Monitoring.c **** uint16_t isense6; // radiator fans
16:Core/Src/Current_Monitoring.c **** uint16_t isense13; // tsac fans
17:Core/Src/Current_Monitoring.c **** uint16_t isense5; // gss and lidar
18:Core/Src/Current_Monitoring.c **** uint16_t isense3; // sdc and always on
19:Core/Src/Current_Monitoring.c **** uint16_t isense7; // misc and inverters
20:Core/Src/Current_Monitoring.c **** } adcbank1;
21:Core/Src/Current_Monitoring.c ****
22:Core/Src/Current_Monitoring.c **** uint16_t adcbuffer[7]; // array 7*16 bit
23:Core/Src/Current_Monitoring.c ****
24:Core/Src/Current_Monitoring.c **** } adc_channels1;
25:Core/Src/Current_Monitoring.c **** // ADC's anpassen adc1 - 9, adc2 ist halt 5 , buffer anpassen und namen auch ( isense usw)
26:Core/Src/Current_Monitoring.c **** volatile union adc2_channels {
27:Core/Src/Current_Monitoring.c **** struct {
28:Core/Src/Current_Monitoring.c **** uint16_t isense2; // ebs valve a and ebs valve b
29:Core/Src/Current_Monitoring.c **** uint16_t isense1; // ebs cs valve
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 2
30:Core/Src/Current_Monitoring.c **** uint16_t isense10; // hyr aggregat
31:Core/Src/Current_Monitoring.c **** uint16_t isense4; // cooling pump and reserved
32:Core/Src/Current_Monitoring.c ****
33:Core/Src/Current_Monitoring.c **** } adcbank1;
34:Core/Src/Current_Monitoring.c ****
35:Core/Src/Current_Monitoring.c **** uint16_t adcbuffer[4];
36:Core/Src/Current_Monitoring.c ****
37:Core/Src/Current_Monitoring.c **** } adc_channels2;
38:Core/Src/Current_Monitoring.c ****
39:Core/Src/Current_Monitoring.c **** CurrentMeasurements current_measurements_adc_val;
40:Core/Src/Current_Monitoring.c ****
41:Core/Src/Current_Monitoring.c **** GPIO_PinState adcbank1 = GPIO_PIN_RESET;
42:Core/Src/Current_Monitoring.c **** GPIO_PinState adcbank2 = GPIO_PIN_RESET;
43:Core/Src/Current_Monitoring.c ****
44:Core/Src/Current_Monitoring.c **** ADC_HandleTypeDef* adc1;
45:Core/Src/Current_Monitoring.c **** ADC_HandleTypeDef* adc2;
46:Core/Src/Current_Monitoring.c ****
47:Core/Src/Current_Monitoring.c **** void currentMonitor_init(ADC_HandleTypeDef* hadc1, ADC_HandleTypeDef* hadc2, // init ist initilisie
48:Core/Src/Current_Monitoring.c **** TIM_HandleTypeDef* trigtim) {
30 .loc 1 48 54 view -0
31 .cfi_startproc
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 .loc 1 48 54 is_stmt 0 view .LVU1
35 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr}
36 .cfi_def_cfa_offset 32
37 .cfi_offset 3, -32
38 .cfi_offset 4, -28
39 .cfi_offset 5, -24
40 .cfi_offset 6, -20
41 .cfi_offset 7, -16
42 .cfi_offset 8, -12
43 .cfi_offset 9, -8
44 .cfi_offset 14, -4
45 0004 0546 mov r5, r0
46 0006 0C46 mov r4, r1
47 0008 1746 mov r7, r2
49:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_3_GPIO_Port, DSEL_3_Pin, adcbank2); //DSELs zu adc's neu zuordnen
48 .loc 1 49 3 is_stmt 1 view .LVU2
49 000a DFF88880 ldr r8, .L3+20
50 000e 1C4E ldr r6, .L3
51 0010 98F80020 ldrb r2, [r8] @ zero_extendqisi2
52 .LVL1:
53 .loc 1 49 3 is_stmt 0 view .LVU3
54 0014 4FF48051 mov r1, #4096
55 .LVL2:
56 .loc 1 49 3 view .LVU4
57 0018 3046 mov r0, r6
58 .LVL3:
59 .loc 1 49 3 view .LVU5
60 001a FFF7FEFF bl HAL_GPIO_WritePin
61 .LVL4:
50:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_4_GPIO_Port, DSEL_4_Pin, adcbank2);
62 .loc 1 50 3 is_stmt 1 view .LVU6
63 001e 98F80020 ldrb r2, [r8] @ zero_extendqisi2
64 0022 4FF40051 mov r1, #8192
65 0026 3046 mov r0, r6
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 3
66 0028 FFF7FEFF bl HAL_GPIO_WritePin
67 .LVL5:
51:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_5_GPIO_Port, DSEL_5_Pin, adcbank1);
68 .loc 1 51 3 view .LVU7
69 002c DFF86890 ldr r9, .L3+24
70 0030 99F80020 ldrb r2, [r9] @ zero_extendqisi2
71 0034 4FF48041 mov r1, #16384
72 0038 3046 mov r0, r6
73 003a FFF7FEFF bl HAL_GPIO_WritePin
74 .LVL6:
52:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_7_GPIO_Port, DSEL_7_Pin, adcbank1);
75 .loc 1 52 3 view .LVU8
76 003e 99F80020 ldrb r2, [r9] @ zero_extendqisi2
77 0042 4FF40071 mov r1, #512
78 0046 3046 mov r0, r6
79 0048 FFF7FEFF bl HAL_GPIO_WritePin
80 .LVL7:
53:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_8_GPIO_Port, DSEL_8_Pin, adcbank2);
81 .loc 1 53 3 view .LVU9
82 004c 98F80020 ldrb r2, [r8] @ zero_extendqisi2
83 0050 0121 movs r1, #1
84 0052 4FF09040 mov r0, #1207959552
85 0056 FFF7FEFF bl HAL_GPIO_WritePin
86 .LVL8:
54:Core/Src/Current_Monitoring.c **** adc1 = hadc1;
87 .loc 1 54 3 view .LVU10
88 .loc 1 54 8 is_stmt 0 view .LVU11
89 005a 0A4B ldr r3, .L3+4
90 005c 1D60 str r5, [r3]
55:Core/Src/Current_Monitoring.c **** adc2 = hadc2;
91 .loc 1 55 3 is_stmt 1 view .LVU12
92 .loc 1 55 8 is_stmt 0 view .LVU13
93 005e 0A4B ldr r3, .L3+8
94 0060 1C60 str r4, [r3]
56:Core/Src/Current_Monitoring.c **** HAL_TIM_Base_Start(trigtim);
95 .loc 1 56 3 is_stmt 1 view .LVU14
96 0062 3846 mov r0, r7
97 0064 FFF7FEFF bl HAL_TIM_Base_Start
98 .LVL9:
57:Core/Src/Current_Monitoring.c **** HAL_ADC_Start_DMA(hadc1, (uint32_t*)adc_channels1.adcbuffer, 7);
99 .loc 1 57 3 view .LVU15
100 0068 0722 movs r2, #7
101 006a 0849 ldr r1, .L3+12
102 006c 2846 mov r0, r5
103 006e FFF7FEFF bl HAL_ADC_Start_DMA
104 .LVL10:
58:Core/Src/Current_Monitoring.c **** HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 7); // wie adc mit dma geht , red mi
105 .loc 1 58 3 view .LVU16
106 0072 0722 movs r2, #7
107 0074 0649 ldr r1, .L3+16
108 0076 2046 mov r0, r4
109 0078 FFF7FEFF bl HAL_ADC_Start_DMA
110 .LVL11:
59:Core/Src/Current_Monitoring.c **** }
111 .loc 1 59 1 is_stmt 0 view .LVU17
112 007c BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc}
113 .LVL12:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 4
114 .L4:
115 .loc 1 59 1 view .LVU18
116 .align 2
117 .L3:
118 0080 00040048 .word 1207960576
119 0084 00000000 .word adc1
120 0088 00000000 .word adc2
121 008c 00000000 .word adc_channels1
122 0090 00000000 .word adc_channels2
123 0094 00000000 .word adcbank2
124 0098 00000000 .word adcbank1
125 .cfi_endproc
126 .LFE130:
128 .section .text.currentMonitor_checklimits,"ax",%progbits
129 .align 1
130 .global currentMonitor_checklimits
131 .syntax unified
132 .thumb
133 .thumb_func
135 currentMonitor_checklimits:
136 .LFB131:
60:Core/Src/Current_Monitoring.c ****
61:Core/Src/Current_Monitoring.c **** uint8_t currentMonitor_checklimits() { return 0; }
137 .loc 1 61 38 is_stmt 1 view -0
138 .cfi_startproc
139 @ args = 0, pretend = 0, frame = 0
140 @ frame_needed = 0, uses_anonymous_args = 0
141 @ link register save eliminated.
142 .loc 1 61 40 view .LVU20
143 .loc 1 61 50 is_stmt 0 view .LVU21
144 0000 0020 movs r0, #0
145 0002 7047 bx lr
146 .cfi_endproc
147 .LFE131:
149 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits
150 .align 1
151 .global HAL_ADC_ConvCpltCallback
152 .syntax unified
153 .thumb
154 .thumb_func
156 HAL_ADC_ConvCpltCallback:
157 .LVL13:
158 .LFB132:
62:Core/Src/Current_Monitoring.c ****
63:Core/Src/Current_Monitoring.c **** void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) {
159 .loc 1 63 56 is_stmt 1 view -0
160 .cfi_startproc
161 @ args = 0, pretend = 0, frame = 0
162 @ frame_needed = 0, uses_anonymous_args = 0
163 .loc 1 63 56 is_stmt 0 view .LVU23
164 0000 38B5 push {r3, r4, r5, lr}
165 .cfi_def_cfa_offset 16
166 .cfi_offset 3, -16
167 .cfi_offset 4, -12
168 .cfi_offset 5, -8
169 .cfi_offset 14, -4
170 0002 0446 mov r4, r0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 5
64:Core/Src/Current_Monitoring.c **** if (hadc == adc2) {
171 .loc 1 64 3 is_stmt 1 view .LVU24
172 .loc 1 64 12 is_stmt 0 view .LVU25
173 0004 9A4B ldr r3, .L16
174 0006 1B68 ldr r3, [r3]
175 .loc 1 64 6 view .LVU26
176 0008 8342 cmp r3, r0
177 000a 04D0 beq .L14
178 .LVL14:
179 .L7:
65:Core/Src/Current_Monitoring.c **** if (adcbank2 == GPIO_PIN_RESET) {
66:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.ebsvalve_a =
67:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense2 * CURR_SENSE_FACTOR_5A;
68:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.cooling_pump =
69:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense4 * CURR_SENSE_FACTOR_7_5A;
70:Core/Src/Current_Monitoring.c **** adcbank2 = GPIO_PIN_SET;
71:Core/Src/Current_Monitoring.c **** } else {
72:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.ebsvalve_b =
73:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense2 * CURR_SENSE_FACTOR_5A;
74:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.reserved =
75:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense4 * CURR_SENSE_FACTOR_7_5A;
76:Core/Src/Current_Monitoring.c **** adcbank2 = GPIO_PIN_RESET;
77:Core/Src/Current_Monitoring.c **** }
78:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.ebs_cs_valve =
79:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense1 * CURR_SENSE_FACTOR_5A;
80:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.aggregat =
81:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense10 * CURR_SENSE_FACTOR_21A;
82:Core/Src/Current_Monitoring.c ****
83:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_3_GPIO_Port, DSEL_3_Pin,
84:Core/Src/Current_Monitoring.c **** adcbank2);
85:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_8_GPIO_Port, DSEL_8_Pin,
86:Core/Src/Current_Monitoring.c **** adcbank2);
87:Core/Src/Current_Monitoring.c **** }
88:Core/Src/Current_Monitoring.c ****
89:Core/Src/Current_Monitoring.c **** if (hadc == adc1) {
180 .loc 1 89 3 is_stmt 1 view .LVU27
181 .loc 1 89 12 is_stmt 0 view .LVU28
182 000c 994B ldr r3, .L16+4
183 000e 1B68 ldr r3, [r3]
184 .loc 1 89 6 view .LVU29
185 0010 A342 cmp r3, r4
186 0012 79D0 beq .L15
187 .LVL15:
188 .L6:
90:Core/Src/Current_Monitoring.c **** if (adcbank1 == GPIO_PIN_RESET) {
91:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.sdc=
92:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense3 * CURR_SENSE_FACTOR_5A;
93:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.misc=
94:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense7 * CURR_SENSE_FACTOR_7_5A;
95:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.gss=
96:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense5 * CURR_SENSE_FACTOR_7_5A;
97:Core/Src/Current_Monitoring.c ****
98:Core/Src/Current_Monitoring.c **** adcbank1 = GPIO_PIN_SET;
99:Core/Src/Current_Monitoring.c **** } else {
100:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.always_on =
101:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense3 * CURR_SENSE_FACTOR_5A;
102:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.inverters =
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 6
103:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense7 * CURR_SENSE_FACTOR_7_5A;
104:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.lidar=
105:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense5 * CURR_SENSE_FACTOR_7_5A;
106:Core/Src/Current_Monitoring.c **** adcbank1 = GPIO_PIN_RESET;
107:Core/Src/Current_Monitoring.c **** }
108:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.acu=
109:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense12 * CURR_SENSE_FACTOR_31A;
110:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.epsc =
111:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_21A;
112:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.tsac_fans =
113:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense13 * CURR_SENSE_FACTOR_31A;
114:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.radiator_fans=
115:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_21A;
116:Core/Src/Current_Monitoring.c ****
117:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_4_GPIO_Port, DSEL_4_Pin,
118:Core/Src/Current_Monitoring.c **** adcbank1);
119:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_5_GPIO_Port, DSEL_5_Pin,
120:Core/Src/Current_Monitoring.c **** adcbank1);
121:Core/Src/Current_Monitoring.c **** HAL_GPIO_WritePin(DSEL_7_GPIO_Port, DSEL_7_Pin,
122:Core/Src/Current_Monitoring.c **** adcbank1);
123:Core/Src/Current_Monitoring.c **** }
124:Core/Src/Current_Monitoring.c **** }
189 .loc 1 124 1 view .LVU30
190 0014 38BD pop {r3, r4, r5, pc}
191 .LVL16:
192 .L14:
65:Core/Src/Current_Monitoring.c **** if (adcbank2 == GPIO_PIN_RESET) {
193 .loc 1 65 5 is_stmt 1 view .LVU31
65:Core/Src/Current_Monitoring.c **** if (adcbank2 == GPIO_PIN_RESET) {
194 .loc 1 65 18 is_stmt 0 view .LVU32
195 0016 984B ldr r3, .L16+8
196 0018 1B78 ldrb r3, [r3] @ zero_extendqisi2
65:Core/Src/Current_Monitoring.c **** if (adcbank2 == GPIO_PIN_RESET) {
197 .loc 1 65 8 view .LVU33
198 001a 002B cmp r3, #0
199 001c 50D1 bne .L8
66:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense2 * CURR_SENSE_FACTOR_5A;
200 .loc 1 66 7 is_stmt 1 view .LVU34
67:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.cooling_pump =
201 .loc 1 67 33 is_stmt 0 view .LVU35
202 001e 9749 ldr r1, .L16+12
203 0020 0B88 ldrh r3, [r1]
204 0022 9BB2 uxth r3, r3
205 0024 07EE903A vmov s15, r3 @ int
67:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.cooling_pump =
206 .loc 1 67 42 view .LVU36
207 0028 F8EEE77A vcvt.f32.s32 s15, s15
208 002c 9FED947A vldr.32 s14, .L16+16
209 0030 67EE877A vmul.f32 s15, s15, s14
66:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense2 * CURR_SENSE_FACTOR_5A;
210 .loc 1 66 47 view .LVU37
211 0034 934A ldr r2, .L16+20
212 0036 FCEEE77A vcvt.u32.f32 s15, s15
213 003a 17EE903A vmov r3, s15 @ int
214 003e 9383 strh r3, [r2, #28] @ movhi
68:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense4 * CURR_SENSE_FACTOR_7_5A;
215 .loc 1 68 7 is_stmt 1 view .LVU38
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 7
69:Core/Src/Current_Monitoring.c **** adcbank2 = GPIO_PIN_SET;
216 .loc 1 69 33 is_stmt 0 view .LVU39
217 0040 CB88 ldrh r3, [r1, #6]
218 0042 9BB2 uxth r3, r3
219 0044 07EE903A vmov s15, r3 @ int
69:Core/Src/Current_Monitoring.c **** adcbank2 = GPIO_PIN_SET;
220 .loc 1 69 42 view .LVU40
221 0048 F8EEE77A vcvt.f32.s32 s15, s15
222 004c 9FED8E7A vldr.32 s14, .L16+24
223 0050 67EE877A vmul.f32 s15, s15, s14
68:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense4 * CURR_SENSE_FACTOR_7_5A;
224 .loc 1 68 49 view .LVU41
225 0054 FCEEE77A vcvt.u32.f32 s15, s15
226 0058 17EE903A vmov r3, s15 @ int
227 005c 1384 strh r3, [r2, #32] @ movhi
70:Core/Src/Current_Monitoring.c **** } else {
228 .loc 1 70 7 is_stmt 1 view .LVU42
70:Core/Src/Current_Monitoring.c **** } else {
229 .loc 1 70 16 is_stmt 0 view .LVU43
230 005e 864B ldr r3, .L16+8
231 0060 0122 movs r2, #1
232 0062 1A70 strb r2, [r3]
233 .L9:
78:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense1 * CURR_SENSE_FACTOR_5A;
234 .loc 1 78 5 is_stmt 1 view .LVU44
79:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.aggregat =
235 .loc 1 79 31 is_stmt 0 view .LVU45
236 0064 8549 ldr r1, .L16+12
237 0066 4B88 ldrh r3, [r1, #2]
238 0068 9BB2 uxth r3, r3
239 006a 07EE903A vmov s15, r3 @ int
79:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.aggregat =
240 .loc 1 79 40 view .LVU46
241 006e F8EEE77A vcvt.f32.s32 s15, s15
242 0072 9FED837A vldr.32 s14, .L16+16
243 0076 67EE877A vmul.f32 s15, s15, s14
78:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense1 * CURR_SENSE_FACTOR_5A;
244 .loc 1 78 47 view .LVU47
245 007a 824A ldr r2, .L16+20
246 007c FCEEE77A vcvt.u32.f32 s15, s15
247 0080 17EE903A vmov r3, s15 @ int
248 0084 1383 strh r3, [r2, #24] @ movhi
80:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense10 * CURR_SENSE_FACTOR_21A;
249 .loc 1 80 5 is_stmt 1 view .LVU48
81:Core/Src/Current_Monitoring.c ****
250 .loc 1 81 31 is_stmt 0 view .LVU49
251 0086 8B88 ldrh r3, [r1, #4]
252 0088 9BB2 uxth r3, r3
253 008a 07EE903A vmov s15, r3 @ int
81:Core/Src/Current_Monitoring.c ****
254 .loc 1 81 41 view .LVU50
255 008e F8EEE77A vcvt.f32.s32 s15, s15
256 0092 9FED7E7A vldr.32 s14, .L16+28
257 0096 67EE877A vmul.f32 s15, s15, s14
80:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense10 * CURR_SENSE_FACTOR_21A;
258 .loc 1 80 43 view .LVU51
259 009a FCEEE77A vcvt.u32.f32 s15, s15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 8
260 009e 17EE903A vmov r3, s15 @ int
261 00a2 5382 strh r3, [r2, #18] @ movhi
83:Core/Src/Current_Monitoring.c **** adcbank2);
262 .loc 1 83 5 is_stmt 1 view .LVU52
263 00a4 744D ldr r5, .L16+8
264 00a6 2A78 ldrb r2, [r5] @ zero_extendqisi2
265 00a8 4FF48051 mov r1, #4096
266 00ac 7848 ldr r0, .L16+32
267 .LVL17:
83:Core/Src/Current_Monitoring.c **** adcbank2);
268 .loc 1 83 5 is_stmt 0 view .LVU53
269 00ae FFF7FEFF bl HAL_GPIO_WritePin
270 .LVL18:
85:Core/Src/Current_Monitoring.c **** adcbank2);
271 .loc 1 85 5 is_stmt 1 view .LVU54
272 00b2 2A78 ldrb r2, [r5] @ zero_extendqisi2
273 00b4 0121 movs r1, #1
274 00b6 4FF09040 mov r0, #1207959552
275 00ba FFF7FEFF bl HAL_GPIO_WritePin
276 .LVL19:
277 00be A5E7 b .L7
278 .LVL20:
279 .L8:
72:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense2 * CURR_SENSE_FACTOR_5A;
280 .loc 1 72 7 view .LVU55
73:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.reserved =
281 .loc 1 73 33 is_stmt 0 view .LVU56
282 00c0 6E49 ldr r1, .L16+12
283 00c2 0B88 ldrh r3, [r1]
284 00c4 9BB2 uxth r3, r3
285 00c6 07EE903A vmov s15, r3 @ int
73:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.reserved =
286 .loc 1 73 42 view .LVU57
287 00ca F8EEE77A vcvt.f32.s32 s15, s15
288 00ce 9FED6C7A vldr.32 s14, .L16+16
289 00d2 67EE877A vmul.f32 s15, s15, s14
72:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense2 * CURR_SENSE_FACTOR_5A;
290 .loc 1 72 47 view .LVU58
291 00d6 6B4A ldr r2, .L16+20
292 00d8 FCEEE77A vcvt.u32.f32 s15, s15
293 00dc 17EE903A vmov r3, s15 @ int
294 00e0 D383 strh r3, [r2, #30] @ movhi
74:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense4 * CURR_SENSE_FACTOR_7_5A;
295 .loc 1 74 7 is_stmt 1 view .LVU59
75:Core/Src/Current_Monitoring.c **** adcbank2 = GPIO_PIN_RESET;
296 .loc 1 75 33 is_stmt 0 view .LVU60
297 00e2 CB88 ldrh r3, [r1, #6]
298 00e4 9BB2 uxth r3, r3
299 00e6 07EE903A vmov s15, r3 @ int
75:Core/Src/Current_Monitoring.c **** adcbank2 = GPIO_PIN_RESET;
300 .loc 1 75 42 view .LVU61
301 00ea F8EEE77A vcvt.f32.s32 s15, s15
302 00ee 9FED667A vldr.32 s14, .L16+24
303 00f2 67EE877A vmul.f32 s15, s15, s14
74:Core/Src/Current_Monitoring.c **** adc_channels2.adcbank1.isense4 * CURR_SENSE_FACTOR_7_5A;
304 .loc 1 74 45 view .LVU62
305 00f6 FCEEE77A vcvt.u32.f32 s15, s15
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 9
306 00fa 17EE903A vmov r3, s15 @ int
307 00fe 5383 strh r3, [r2, #26] @ movhi
76:Core/Src/Current_Monitoring.c **** }
308 .loc 1 76 7 is_stmt 1 view .LVU63
76:Core/Src/Current_Monitoring.c **** }
309 .loc 1 76 16 is_stmt 0 view .LVU64
310 0100 5D4B ldr r3, .L16+8
311 0102 0022 movs r2, #0
312 0104 1A70 strb r2, [r3]
313 0106 ADE7 b .L9
314 .LVL21:
315 .L15:
90:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.sdc=
316 .loc 1 90 5 is_stmt 1 view .LVU65
90:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.sdc=
317 .loc 1 90 18 is_stmt 0 view .LVU66
318 0108 624B ldr r3, .L16+36
319 010a 1B78 ldrb r3, [r3] @ zero_extendqisi2
90:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.sdc=
320 .loc 1 90 8 view .LVU67
321 010c 002B cmp r3, #0
322 010e 7ED1 bne .L11
91:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense3 * CURR_SENSE_FACTOR_5A;
323 .loc 1 91 7 is_stmt 1 view .LVU68
92:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.misc=
324 .loc 1 92 33 is_stmt 0 view .LVU69
325 0110 6149 ldr r1, .L16+40
326 0112 4B89 ldrh r3, [r1, #10]
327 0114 9BB2 uxth r3, r3
328 0116 07EE903A vmov s15, r3 @ int
92:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.misc=
329 .loc 1 92 42 view .LVU70
330 011a F8EEE77A vcvt.f32.s32 s15, s15
331 011e 9FED587A vldr.32 s14, .L16+16
332 0122 67EE877A vmul.f32 s15, s15, s14
91:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense3 * CURR_SENSE_FACTOR_5A;
333 .loc 1 91 39 view .LVU71
334 0126 574A ldr r2, .L16+20
335 0128 FCEEE77A vcvt.u32.f32 s15, s15
336 012c 17EE903A vmov r3, s15 @ int
337 0130 9381 strh r3, [r2, #12] @ movhi
93:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense7 * CURR_SENSE_FACTOR_7_5A;
338 .loc 1 93 7 is_stmt 1 view .LVU72
94:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.gss=
339 .loc 1 94 33 is_stmt 0 view .LVU73
340 0132 8B89 ldrh r3, [r1, #12]
341 0134 9BB2 uxth r3, r3
342 0136 07EE903A vmov s15, r3 @ int
94:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.gss=
343 .loc 1 94 42 view .LVU74
344 013a F8EEE77A vcvt.f32.s32 s15, s15
345 013e 9FED527A vldr.32 s14, .L16+24
346 0142 67EE877A vmul.f32 s15, s15, s14
93:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense7 * CURR_SENSE_FACTOR_7_5A;
347 .loc 1 93 40 view .LVU75
348 0146 FCEEE77A vcvt.u32.f32 s15, s15
349 014a 17EE903A vmov r3, s15 @ int
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 10
350 014e 9382 strh r3, [r2, #20] @ movhi
95:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense5 * CURR_SENSE_FACTOR_7_5A;
351 .loc 1 95 7 is_stmt 1 view .LVU76
96:Core/Src/Current_Monitoring.c ****
352 .loc 1 96 33 is_stmt 0 view .LVU77
353 0150 0B89 ldrh r3, [r1, #8]
354 0152 9BB2 uxth r3, r3
355 0154 07EE903A vmov s15, r3 @ int
96:Core/Src/Current_Monitoring.c ****
356 .loc 1 96 42 view .LVU78
357 0158 F8EEE77A vcvt.f32.s32 s15, s15
358 015c 67EE877A vmul.f32 s15, s15, s14
95:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense5 * CURR_SENSE_FACTOR_7_5A;
359 .loc 1 95 39 view .LVU79
360 0160 FCEEE77A vcvt.u32.f32 s15, s15
361 0164 17EE903A vmov r3, s15 @ int
362 0168 1381 strh r3, [r2, #8] @ movhi
98:Core/Src/Current_Monitoring.c **** } else {
363 .loc 1 98 7 is_stmt 1 view .LVU80
98:Core/Src/Current_Monitoring.c **** } else {
364 .loc 1 98 16 is_stmt 0 view .LVU81
365 016a 4A4B ldr r3, .L16+36
366 016c 0122 movs r2, #1
367 016e 1A70 strb r2, [r3]
368 .L12:
108:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense12 * CURR_SENSE_FACTOR_31A;
369 .loc 1 108 5 is_stmt 1 view .LVU82
109:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.epsc =
370 .loc 1 109 31 is_stmt 0 view .LVU83
371 0170 4949 ldr r1, .L16+40
372 0172 0B88 ldrh r3, [r1]
373 0174 9BB2 uxth r3, r3
374 0176 07EE903A vmov s15, r3 @ int
109:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.epsc =
375 .loc 1 109 41 view .LVU84
376 017a F8EEE77A vcvt.f32.s32 s15, s15
377 017e DFED476A vldr.32 s13, .L16+44
378 0182 67EEA67A vmul.f32 s15, s15, s13
108:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense12 * CURR_SENSE_FACTOR_31A;
379 .loc 1 108 37 view .LVU85
380 0186 3F4A ldr r2, .L16+20
381 0188 FCEEE77A vcvt.u32.f32 s15, s15
382 018c 17EE903A vmov r3, s15 @ int
383 0190 1380 strh r3, [r2] @ movhi
110:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_21A;
384 .loc 1 110 5 is_stmt 1 view .LVU86
111:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.tsac_fans =
385 .loc 1 111 31 is_stmt 0 view .LVU87
386 0192 4B88 ldrh r3, [r1, #2]
387 0194 9BB2 uxth r3, r3
388 0196 07EE903A vmov s15, r3 @ int
111:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.tsac_fans =
389 .loc 1 111 41 view .LVU88
390 019a F8EEE77A vcvt.f32.s32 s15, s15
391 019e 9FED3B7A vldr.32 s14, .L16+28
392 01a2 67EE877A vmul.f32 s15, s15, s14
110:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_21A;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 11
393 .loc 1 110 39 view .LVU89
394 01a6 FCEEE77A vcvt.u32.f32 s15, s15
395 01aa 17EE903A vmov r3, s15 @ int
396 01ae 5380 strh r3, [r2, #2] @ movhi
112:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense13 * CURR_SENSE_FACTOR_31A;
397 .loc 1 112 5 is_stmt 1 view .LVU90
113:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.radiator_fans=
398 .loc 1 113 31 is_stmt 0 view .LVU91
399 01b0 CB88 ldrh r3, [r1, #6]
400 01b2 9BB2 uxth r3, r3
401 01b4 07EE903A vmov s15, r3 @ int
113:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.radiator_fans=
402 .loc 1 113 41 view .LVU92
403 01b8 F8EEE77A vcvt.f32.s32 s15, s15
404 01bc 67EEA67A vmul.f32 s15, s15, s13
112:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense13 * CURR_SENSE_FACTOR_31A;
405 .loc 1 112 44 view .LVU93
406 01c0 FCEEE77A vcvt.u32.f32 s15, s15
407 01c4 17EE903A vmov r3, s15 @ int
408 01c8 D380 strh r3, [r2, #6] @ movhi
114:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_21A;
409 .loc 1 114 5 is_stmt 1 view .LVU94
115:Core/Src/Current_Monitoring.c ****
410 .loc 1 115 33 is_stmt 0 view .LVU95
411 01ca 8B88 ldrh r3, [r1, #4]
412 01cc 9BB2 uxth r3, r3
413 01ce 07EE903A vmov s15, r3 @ int
115:Core/Src/Current_Monitoring.c ****
414 .loc 1 115 42 view .LVU96
415 01d2 F8EEE77A vcvt.f32.s32 s15, s15
416 01d6 67EE877A vmul.f32 s15, s15, s14
114:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_21A;
417 .loc 1 114 47 view .LVU97
418 01da FCEEE77A vcvt.u32.f32 s15, s15
419 01de 17EE903A vmov r3, s15 @ int
420 01e2 9380 strh r3, [r2, #4] @ movhi
117:Core/Src/Current_Monitoring.c **** adcbank1);
421 .loc 1 117 5 is_stmt 1 view .LVU98
422 01e4 2B4D ldr r5, .L16+36
423 01e6 2A4C ldr r4, .L16+32
424 .LVL22:
117:Core/Src/Current_Monitoring.c **** adcbank1);
425 .loc 1 117 5 is_stmt 0 view .LVU99
426 01e8 2A78 ldrb r2, [r5] @ zero_extendqisi2
427 01ea 4FF40051 mov r1, #8192
428 01ee 2046 mov r0, r4
429 01f0 FFF7FEFF bl HAL_GPIO_WritePin
430 .LVL23:
119:Core/Src/Current_Monitoring.c **** adcbank1);
431 .loc 1 119 5 is_stmt 1 view .LVU100
432 01f4 2A78 ldrb r2, [r5] @ zero_extendqisi2
433 01f6 4FF48041 mov r1, #16384
434 01fa 2046 mov r0, r4
435 01fc FFF7FEFF bl HAL_GPIO_WritePin
436 .LVL24:
121:Core/Src/Current_Monitoring.c **** adcbank1);
437 .loc 1 121 5 view .LVU101
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 12
438 0200 2A78 ldrb r2, [r5] @ zero_extendqisi2
439 0202 4FF40071 mov r1, #512
440 0206 2046 mov r0, r4
441 0208 FFF7FEFF bl HAL_GPIO_WritePin
442 .LVL25:
443 .loc 1 124 1 is_stmt 0 view .LVU102
444 020c 02E7 b .L6
445 .LVL26:
446 .L11:
100:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense3 * CURR_SENSE_FACTOR_5A;
447 .loc 1 100 7 is_stmt 1 view .LVU103
101:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.inverters =
448 .loc 1 101 33 is_stmt 0 view .LVU104
449 020e 2249 ldr r1, .L16+40
450 0210 4B89 ldrh r3, [r1, #10]
451 0212 9BB2 uxth r3, r3
452 0214 07EE903A vmov s15, r3 @ int
101:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.inverters =
453 .loc 1 101 42 view .LVU105
454 0218 F8EEE77A vcvt.f32.s32 s15, s15
455 021c 9FED187A vldr.32 s14, .L16+16
456 0220 67EE877A vmul.f32 s15, s15, s14
100:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense3 * CURR_SENSE_FACTOR_5A;
457 .loc 1 100 46 view .LVU106
458 0224 174A ldr r2, .L16+20
459 0226 FCEEE77A vcvt.u32.f32 s15, s15
460 022a 17EE903A vmov r3, s15 @ int
461 022e D382 strh r3, [r2, #22] @ movhi
102:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense7 * CURR_SENSE_FACTOR_7_5A;
462 .loc 1 102 7 is_stmt 1 view .LVU107
103:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.lidar=
463 .loc 1 103 33 is_stmt 0 view .LVU108
464 0230 8B89 ldrh r3, [r1, #12]
465 0232 9BB2 uxth r3, r3
466 0234 07EE903A vmov s15, r3 @ int
103:Core/Src/Current_Monitoring.c **** current_measurements_adc_val.lidar=
467 .loc 1 103 42 view .LVU109
468 0238 F8EEE77A vcvt.f32.s32 s15, s15
469 023c 9FED127A vldr.32 s14, .L16+24
470 0240 67EE877A vmul.f32 s15, s15, s14
102:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense7 * CURR_SENSE_FACTOR_7_5A;
471 .loc 1 102 46 view .LVU110
472 0244 FCEEE77A vcvt.u32.f32 s15, s15
473 0248 17EE903A vmov r3, s15 @ int
474 024c D381 strh r3, [r2, #14] @ movhi
104:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense5 * CURR_SENSE_FACTOR_7_5A;
475 .loc 1 104 7 is_stmt 1 view .LVU111
105:Core/Src/Current_Monitoring.c **** adcbank1 = GPIO_PIN_RESET;
476 .loc 1 105 33 is_stmt 0 view .LVU112
477 024e 0B89 ldrh r3, [r1, #8]
478 0250 9BB2 uxth r3, r3
479 0252 07EE903A vmov s15, r3 @ int
105:Core/Src/Current_Monitoring.c **** adcbank1 = GPIO_PIN_RESET;
480 .loc 1 105 42 view .LVU113
481 0256 F8EEE77A vcvt.f32.s32 s15, s15
482 025a 67EE877A vmul.f32 s15, s15, s14
104:Core/Src/Current_Monitoring.c **** adc_channels1.adcbank1.isense5 * CURR_SENSE_FACTOR_7_5A;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 13
483 .loc 1 104 41 view .LVU114
484 025e FCEEE77A vcvt.u32.f32 s15, s15
485 0262 17EE903A vmov r3, s15 @ int
486 0266 5381 strh r3, [r2, #10] @ movhi
106:Core/Src/Current_Monitoring.c **** }
487 .loc 1 106 7 is_stmt 1 view .LVU115
106:Core/Src/Current_Monitoring.c **** }
488 .loc 1 106 16 is_stmt 0 view .LVU116
489 0268 0A4B ldr r3, .L16+36
490 026a 0022 movs r2, #0
491 026c 1A70 strb r2, [r3]
492 026e 7FE7 b .L12
493 .L17:
494 .align 2
495 .L16:
496 0270 00000000 .word adc2
497 0274 00000000 .word adc1
498 0278 00000000 .word adcbank2
499 027c 00000000 .word adc_channels2
500 0280 FFFB1E40 .word 1075772415
501 0284 00000000 .word current_measurements_adc_val
502 0288 FF2D6A40 .word 1080700415
503 028c FFD87341 .word 1098111231
504 0290 00040048 .word 1207960576
505 0294 00000000 .word adcbank1
506 0298 00000000 .word adc_channels1
507 029c 7F27B741 .word 1102522239
508 .cfi_endproc
509 .LFE132:
511 .global adc2
512 .section .bss.adc2,"aw",%nobits
513 .align 2
516 adc2:
517 0000 00000000 .space 4
518 .global adc1
519 .section .bss.adc1,"aw",%nobits
520 .align 2
523 adc1:
524 0000 00000000 .space 4
525 .global adcbank2
526 .section .bss.adcbank2,"aw",%nobits
529 adcbank2:
530 0000 00 .space 1
531 .global adcbank1
532 .section .bss.adcbank1,"aw",%nobits
535 adcbank1:
536 0000 00 .space 1
537 .global current_measurements_adc_val
538 .section .bss.current_measurements_adc_val,"aw",%nobits
539 .align 2
542 current_measurements_adc_val:
543 0000 00000000 .space 34
543 00000000
543 00000000
543 00000000
543 00000000
544 .global adc_channels2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 14
545 .section .bss.adc_channels2,"aw",%nobits
546 .align 2
549 adc_channels2:
550 0000 00000000 .space 8
550 00000000
551 .global adc_channels1
552 .section .bss.adc_channels1,"aw",%nobits
553 .align 2
556 adc_channels1:
557 0000 00000000 .space 14
557 00000000
557 00000000
557 0000
558 .text
559 .Letext0:
560 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
561 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
562 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
563 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
564 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
565 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h"
566 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
567 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h"
568 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h"
569 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h"
570 .file 12 "Core/Inc/Current_Monitoring.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s page 15
DEFINED SYMBOLS
*ABS*:00000000 Current_Monitoring.c
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:21 .text.currentMonitor_init:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:27 .text.currentMonitor_init:00000000 currentMonitor_init
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:118 .text.currentMonitor_init:00000080 $d
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:523 .bss.adc1:00000000 adc1
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:516 .bss.adc2:00000000 adc2
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:556 .bss.adc_channels1:00000000 adc_channels1
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:549 .bss.adc_channels2:00000000 adc_channels2
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:529 .bss.adcbank2:00000000 adcbank2
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:535 .bss.adcbank1:00000000 adcbank1
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:129 .text.currentMonitor_checklimits:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:135 .text.currentMonitor_checklimits:00000000 currentMonitor_checklimits
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:150 .text.HAL_ADC_ConvCpltCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:156 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:496 .text.HAL_ADC_ConvCpltCallback:00000270 $d
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:542 .bss.current_measurements_adc_val:00000000 current_measurements_adc_val
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:513 .bss.adc2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:520 .bss.adc1:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:530 .bss.adcbank2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:536 .bss.adcbank1:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:539 .bss.current_measurements_adc_val:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:546 .bss.adc_channels2:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccJmvYKq.s:553 .bss.adc_channels1:00000000 $d
UNDEFINED SYMBOLS
HAL_GPIO_WritePin
HAL_TIM_Base_Start
HAL_ADC_Start_DMA

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ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f3xx_hal_i2c_ex.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c"
20 .section .text.HAL_I2CEx_ConfigAnalogFilter,"ax",%progbits
21 .align 1
22 .global HAL_I2CEx_ConfigAnalogFilter
23 .syntax unified
24 .thumb
25 .thumb_func
27 HAL_I2CEx_ConfigAnalogFilter:
28 .LVL0:
29 .LFB130:
1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ******************************************************************************
3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @file stm32f3xx_hal_i2c_ex.c
4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @author MCD Application Team
5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver.
6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * functionalities of I2C Extended peripheral:
8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + Filter Mode Functions
9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + WakeUp Mode Functions
10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + FastModePlus Functions
11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *
12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ******************************************************************************
13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @attention
14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *
15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * Copyright (c) 2016 STMicroelectronics.
16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * All rights reserved.
17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *
18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This software is licensed under terms that can be found in the LICENSE file
19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * in the root directory of this software component.
20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *
22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ******************************************************************************
23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim
24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ==============================================================================
25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### I2C peripheral Extended features #####
26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ==============================================================================
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] Comparing to other previous devices, the I2C interface for STM32F3xx
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** devices contains the following additional features
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 2
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Possibility to disable or enable Analog Noise Filter
32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Use of a configured Digital Noise Filter
33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Disable or enable wakeup from Stop mode(s)
34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Disable or enable Fast Mode Plus
35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### How to use this driver #####
37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ==============================================================================
38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This driver provides functions to configure Noise Filter and Wake Up Feature
39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableWakeUp()
43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableWakeUp()
44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure the enable or disable of fast mode plus driving capability using the functions :
45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableFastModePlus()
46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableFastModePlus()
47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim
48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/
51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** #include "stm32f3xx_hal.h"
52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver
54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{
55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx
58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver
59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{
60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED
63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/
65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/
66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/
67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/
68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/
69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/
70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{
73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Filter Mode Functions
77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *
78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim
79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ===============================================================================
80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### Filter Mode Functions #####
81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ===============================================================================
82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to:
83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Noise Filters
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 3
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Configure I2C Analog noise filter.
91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral.
93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param AnalogFilter New state of the Analog filter.
94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status
95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
30 .loc 1 97 1 view -0
31 .cfi_startproc
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
35 .loc 1 97 1 is_stmt 0 view .LVU1
36 0000 0346 mov r3, r0
98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */
99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
37 .loc 1 99 3 is_stmt 1 view .LVU2
100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
38 .loc 1 100 3 view .LVU3
101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY)
39 .loc 1 102 3 view .LVU4
40 .loc 1 102 11 is_stmt 0 view .LVU5
41 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2
42 0006 D2B2 uxtb r2, r2
43 .loc 1 102 6 view .LVU6
44 0008 202A cmp r2, #32
45 000a 23D1 bne .L3
103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */
105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c);
46 .loc 1 105 5 is_stmt 1 view .LVU7
47 .loc 1 105 5 view .LVU8
48 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2
49 0010 012A cmp r2, #1
50 0012 21D0 beq .L4
51 .loc 1 105 5 discriminator 2 view .LVU9
52 0014 0122 movs r2, #1
53 0016 80F84020 strb r2, [r0, #64]
54 .loc 1 105 5 discriminator 2 view .LVU10
106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY;
55 .loc 1 107 5 discriminator 2 view .LVU11
56 .loc 1 107 17 is_stmt 0 discriminator 2 view .LVU12
57 001a 2422 movs r2, #36
58 001c 80F84120 strb r2, [r0, #65]
108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */
110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c);
59 .loc 1 110 5 is_stmt 1 discriminator 2 view .LVU13
60 0020 0068 ldr r0, [r0]
61 .LVL1:
62 .loc 1 110 5 is_stmt 0 discriminator 2 view .LVU14
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 4
63 0022 0268 ldr r2, [r0]
64 0024 22F00102 bic r2, r2, #1
65 0028 0260 str r2, [r0]
111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Reset I2Cx ANOFF bit */
113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
66 .loc 1 113 5 is_stmt 1 discriminator 2 view .LVU15
67 .loc 1 113 9 is_stmt 0 discriminator 2 view .LVU16
68 002a 1868 ldr r0, [r3]
69 .loc 1 113 19 discriminator 2 view .LVU17
70 002c 0268 ldr r2, [r0]
71 .loc 1 113 25 discriminator 2 view .LVU18
72 002e 22F48052 bic r2, r2, #4096
73 0032 0260 str r2, [r0]
114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Set analog filter bit*/
116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= AnalogFilter;
74 .loc 1 116 5 is_stmt 1 discriminator 2 view .LVU19
75 .loc 1 116 9 is_stmt 0 discriminator 2 view .LVU20
76 0034 1868 ldr r0, [r3]
77 .loc 1 116 19 discriminator 2 view .LVU21
78 0036 0268 ldr r2, [r0]
79 .loc 1 116 25 discriminator 2 view .LVU22
80 0038 1143 orrs r1, r1, r2
81 .LVL2:
82 .loc 1 116 25 discriminator 2 view .LVU23
83 003a 0160 str r1, [r0]
117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c);
84 .loc 1 118 5 is_stmt 1 discriminator 2 view .LVU24
85 003c 1968 ldr r1, [r3]
86 003e 0A68 ldr r2, [r1]
87 0040 42F00102 orr r2, r2, #1
88 0044 0A60 str r2, [r1]
119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY;
89 .loc 1 120 5 discriminator 2 view .LVU25
90 .loc 1 120 17 is_stmt 0 discriminator 2 view .LVU26
91 0046 2022 movs r2, #32
92 0048 83F84120 strb r2, [r3, #65]
121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */
123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c);
93 .loc 1 123 5 is_stmt 1 discriminator 2 view .LVU27
94 .loc 1 123 5 discriminator 2 view .LVU28
95 004c 0020 movs r0, #0
96 004e 83F84000 strb r0, [r3, #64]
97 .loc 1 123 5 discriminator 2 view .LVU29
124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK;
98 .loc 1 125 5 discriminator 2 view .LVU30
99 .loc 1 125 12 is_stmt 0 discriminator 2 view .LVU31
100 0052 7047 bx lr
101 .LVL3:
102 .L3:
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 5
128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY;
103 .loc 1 129 12 view .LVU32
104 0054 0220 movs r0, #2
105 .LVL4:
106 .loc 1 129 12 view .LVU33
107 0056 7047 bx lr
108 .LVL5:
109 .L4:
105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
110 .loc 1 105 5 view .LVU34
111 0058 0220 movs r0, #2
112 .LVL6:
130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
113 .loc 1 131 1 view .LVU35
114 005a 7047 bx lr
115 .cfi_endproc
116 .LFE130:
118 .section .text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits
119 .align 1
120 .global HAL_I2CEx_ConfigDigitalFilter
121 .syntax unified
122 .thumb
123 .thumb_func
125 HAL_I2CEx_ConfigDigitalFilter:
126 .LVL7:
127 .LFB131:
132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Configure I2C Digital noise filter.
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral.
137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x
138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status
139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
128 .loc 1 141 1 is_stmt 1 view -0
129 .cfi_startproc
130 @ args = 0, pretend = 0, frame = 0
131 @ frame_needed = 0, uses_anonymous_args = 0
132 @ link register save eliminated.
133 .loc 1 141 1 is_stmt 0 view .LVU37
134 0000 0346 mov r3, r0
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** uint32_t tmpreg;
135 .loc 1 142 3 is_stmt 1 view .LVU38
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
136 .loc 1 145 3 view .LVU39
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
137 .loc 1 146 3 view .LVU40
147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY)
138 .loc 1 148 3 view .LVU41
139 .loc 1 148 11 is_stmt 0 view .LVU42
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 6
140 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2
141 0006 D2B2 uxtb r2, r2
142 .loc 1 148 6 view .LVU43
143 0008 202A cmp r2, #32
144 000a 21D1 bne .L7
149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c);
145 .loc 1 151 5 is_stmt 1 view .LVU44
146 .loc 1 151 5 view .LVU45
147 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2
148 0010 012A cmp r2, #1
149 0012 1FD0 beq .L8
150 .loc 1 151 5 discriminator 2 view .LVU46
151 0014 0122 movs r2, #1
152 0016 80F84020 strb r2, [r0, #64]
153 .loc 1 151 5 discriminator 2 view .LVU47
152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY;
154 .loc 1 153 5 discriminator 2 view .LVU48
155 .loc 1 153 17 is_stmt 0 discriminator 2 view .LVU49
156 001a 2422 movs r2, #36
157 001c 80F84120 strb r2, [r0, #65]
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */
156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c);
158 .loc 1 156 5 is_stmt 1 discriminator 2 view .LVU50
159 0020 0068 ldr r0, [r0]
160 .LVL8:
161 .loc 1 156 5 is_stmt 0 discriminator 2 view .LVU51
162 0022 0268 ldr r2, [r0]
163 0024 22F00102 bic r2, r2, #1
164 0028 0260 str r2, [r0]
157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Get the old register value */
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg = hi2c->Instance->CR1;
165 .loc 1 159 5 is_stmt 1 discriminator 2 view .LVU52
166 .loc 1 159 18 is_stmt 0 discriminator 2 view .LVU53
167 002a 1868 ldr r0, [r3]
168 .loc 1 159 12 discriminator 2 view .LVU54
169 002c 0268 ldr r2, [r0]
170 .LVL9:
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Reset I2Cx DNF bits [11:8] */
162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg &= ~(I2C_CR1_DNF);
171 .loc 1 162 5 is_stmt 1 discriminator 2 view .LVU55
172 .loc 1 162 12 is_stmt 0 discriminator 2 view .LVU56
173 002e 22F47062 bic r2, r2, #3840
174 .LVL10:
163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Set I2Cx DNF coefficient */
165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg |= DigitalFilter << 8U;
175 .loc 1 165 5 is_stmt 1 discriminator 2 view .LVU57
176 .loc 1 165 12 is_stmt 0 discriminator 2 view .LVU58
177 0032 42EA0122 orr r2, r2, r1, lsl #8
178 .LVL11:
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 7
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Store the new register value */
168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 = tmpreg;
179 .loc 1 168 5 is_stmt 1 discriminator 2 view .LVU59
180 .loc 1 168 25 is_stmt 0 discriminator 2 view .LVU60
181 0036 0260 str r2, [r0]
169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c);
182 .loc 1 170 5 is_stmt 1 discriminator 2 view .LVU61
183 0038 1968 ldr r1, [r3]
184 .LVL12:
185 .loc 1 170 5 is_stmt 0 discriminator 2 view .LVU62
186 003a 0A68 ldr r2, [r1]
187 .LVL13:
188 .loc 1 170 5 discriminator 2 view .LVU63
189 003c 42F00102 orr r2, r2, #1
190 0040 0A60 str r2, [r1]
191 .LVL14:
171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY;
192 .loc 1 172 5 is_stmt 1 discriminator 2 view .LVU64
193 .loc 1 172 17 is_stmt 0 discriminator 2 view .LVU65
194 0042 2022 movs r2, #32
195 0044 83F84120 strb r2, [r3, #65]
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c);
196 .loc 1 175 5 is_stmt 1 discriminator 2 view .LVU66
197 .loc 1 175 5 discriminator 2 view .LVU67
198 0048 0020 movs r0, #0
199 004a 83F84000 strb r0, [r3, #64]
200 .loc 1 175 5 discriminator 2 view .LVU68
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK;
201 .loc 1 177 5 discriminator 2 view .LVU69
202 .loc 1 177 12 is_stmt 0 discriminator 2 view .LVU70
203 004e 7047 bx lr
204 .LVL15:
205 .L7:
178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY;
206 .loc 1 181 12 view .LVU71
207 0050 0220 movs r0, #2
208 .LVL16:
209 .loc 1 181 12 view .LVU72
210 0052 7047 bx lr
211 .LVL17:
212 .L8:
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
213 .loc 1 151 5 view .LVU73
214 0054 0220 movs r0, #2
215 .LVL18:
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
216 .loc 1 183 1 view .LVU74
217 0056 7047 bx lr
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 8
218 .cfi_endproc
219 .LFE131:
221 .section .text.HAL_I2CEx_EnableWakeUp,"ax",%progbits
222 .align 1
223 .global HAL_I2CEx_EnableWakeUp
224 .syntax unified
225 .thumb
226 .thumb_func
228 HAL_I2CEx_EnableWakeUp:
229 .LVL19:
230 .LFB132:
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @}
186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief WakeUp Mode Functions
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *
191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ===============================================================================
193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### WakeUp Mode Functions #####
194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ===============================================================================
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to:
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Wake Up Feature
197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Enable I2C wakeup from Stop mode(s).
204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral.
206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status
207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
231 .loc 1 209 1 is_stmt 1 view -0
232 .cfi_startproc
233 @ args = 0, pretend = 0, frame = 0
234 @ frame_needed = 0, uses_anonymous_args = 0
235 @ link register save eliminated.
236 .loc 1 209 1 is_stmt 0 view .LVU76
237 0000 0346 mov r3, r0
210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */
211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
238 .loc 1 211 3 is_stmt 1 view .LVU77
212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY)
239 .loc 1 213 3 view .LVU78
240 .loc 1 213 11 is_stmt 0 view .LVU79
241 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2
242 0006 D2B2 uxtb r2, r2
243 .loc 1 213 6 view .LVU80
244 0008 202A cmp r2, #32
245 000a 1FD1 bne .L11
214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 9
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */
216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c);
246 .loc 1 216 5 is_stmt 1 view .LVU81
247 .loc 1 216 5 view .LVU82
248 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2
249 0010 012A cmp r2, #1
250 0012 1DD0 beq .L12
251 .loc 1 216 5 discriminator 2 view .LVU83
252 0014 0122 movs r2, #1
253 0016 80F84020 strb r2, [r0, #64]
254 .loc 1 216 5 discriminator 2 view .LVU84
217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY;
255 .loc 1 218 5 discriminator 2 view .LVU85
256 .loc 1 218 17 is_stmt 0 discriminator 2 view .LVU86
257 001a 2422 movs r2, #36
258 001c 80F84120 strb r2, [r0, #65]
219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */
221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c);
259 .loc 1 221 5 is_stmt 1 discriminator 2 view .LVU87
260 0020 0168 ldr r1, [r0]
261 0022 0A68 ldr r2, [r1]
262 0024 22F00102 bic r2, r2, #1
263 0028 0A60 str r2, [r1]
222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */
224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
264 .loc 1 224 5 discriminator 2 view .LVU88
265 .loc 1 224 9 is_stmt 0 discriminator 2 view .LVU89
266 002a 0168 ldr r1, [r0]
267 .loc 1 224 19 discriminator 2 view .LVU90
268 002c 0A68 ldr r2, [r1]
269 .loc 1 224 25 discriminator 2 view .LVU91
270 002e 42F48022 orr r2, r2, #262144
271 0032 0A60 str r2, [r1]
225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c);
272 .loc 1 226 5 is_stmt 1 discriminator 2 view .LVU92
273 0034 0168 ldr r1, [r0]
274 0036 0A68 ldr r2, [r1]
275 0038 42F00102 orr r2, r2, #1
276 003c 0A60 str r2, [r1]
227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY;
277 .loc 1 228 5 discriminator 2 view .LVU93
278 .loc 1 228 17 is_stmt 0 discriminator 2 view .LVU94
279 003e 2022 movs r2, #32
280 0040 80F84120 strb r2, [r0, #65]
229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */
231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c);
281 .loc 1 231 5 is_stmt 1 discriminator 2 view .LVU95
282 .loc 1 231 5 discriminator 2 view .LVU96
283 0044 0020 movs r0, #0
284 .LVL20:
285 .loc 1 231 5 is_stmt 0 discriminator 2 view .LVU97
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 10
286 0046 83F84000 strb r0, [r3, #64]
287 .loc 1 231 5 is_stmt 1 discriminator 2 view .LVU98
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK;
288 .loc 1 233 5 discriminator 2 view .LVU99
289 .loc 1 233 12 is_stmt 0 discriminator 2 view .LVU100
290 004a 7047 bx lr
291 .LVL21:
292 .L11:
234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else
236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY;
293 .loc 1 237 12 view .LVU101
294 004c 0220 movs r0, #2
295 .LVL22:
296 .loc 1 237 12 view .LVU102
297 004e 7047 bx lr
298 .LVL23:
299 .L12:
216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
300 .loc 1 216 5 view .LVU103
301 0050 0220 movs r0, #2
302 .LVL24:
238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
303 .loc 1 239 1 view .LVU104
304 0052 7047 bx lr
305 .cfi_endproc
306 .LFE132:
308 .section .text.HAL_I2CEx_DisableWakeUp,"ax",%progbits
309 .align 1
310 .global HAL_I2CEx_DisableWakeUp
311 .syntax unified
312 .thumb
313 .thumb_func
315 HAL_I2CEx_DisableWakeUp:
316 .LVL25:
317 .LFB133:
240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Disable I2C wakeup from Stop mode(s).
243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral.
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status
246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
318 .loc 1 248 1 is_stmt 1 view -0
319 .cfi_startproc
320 @ args = 0, pretend = 0, frame = 0
321 @ frame_needed = 0, uses_anonymous_args = 0
322 @ link register save eliminated.
323 .loc 1 248 1 is_stmt 0 view .LVU106
324 0000 0346 mov r3, r0
249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 11
325 .loc 1 250 3 is_stmt 1 view .LVU107
251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY)
326 .loc 1 252 3 view .LVU108
327 .loc 1 252 11 is_stmt 0 view .LVU109
328 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2
329 0006 D2B2 uxtb r2, r2
330 .loc 1 252 6 view .LVU110
331 0008 202A cmp r2, #32
332 000a 1FD1 bne .L15
253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c);
333 .loc 1 255 5 is_stmt 1 view .LVU111
334 .loc 1 255 5 view .LVU112
335 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2
336 0010 012A cmp r2, #1
337 0012 1DD0 beq .L16
338 .loc 1 255 5 discriminator 2 view .LVU113
339 0014 0122 movs r2, #1
340 0016 80F84020 strb r2, [r0, #64]
341 .loc 1 255 5 discriminator 2 view .LVU114
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY;
342 .loc 1 257 5 discriminator 2 view .LVU115
343 .loc 1 257 17 is_stmt 0 discriminator 2 view .LVU116
344 001a 2422 movs r2, #36
345 001c 80F84120 strb r2, [r0, #65]
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */
260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c);
346 .loc 1 260 5 is_stmt 1 discriminator 2 view .LVU117
347 0020 0168 ldr r1, [r0]
348 0022 0A68 ldr r2, [r1]
349 0024 22F00102 bic r2, r2, #1
350 0028 0A60 str r2, [r1]
261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */
263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
351 .loc 1 263 5 discriminator 2 view .LVU118
352 .loc 1 263 9 is_stmt 0 discriminator 2 view .LVU119
353 002a 0168 ldr r1, [r0]
354 .loc 1 263 19 discriminator 2 view .LVU120
355 002c 0A68 ldr r2, [r1]
356 .loc 1 263 25 discriminator 2 view .LVU121
357 002e 22F48022 bic r2, r2, #262144
358 0032 0A60 str r2, [r1]
264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c);
359 .loc 1 265 5 is_stmt 1 discriminator 2 view .LVU122
360 0034 0168 ldr r1, [r0]
361 0036 0A68 ldr r2, [r1]
362 0038 42F00102 orr r2, r2, #1
363 003c 0A60 str r2, [r1]
266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY;
364 .loc 1 267 5 discriminator 2 view .LVU123
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 12
365 .loc 1 267 17 is_stmt 0 discriminator 2 view .LVU124
366 003e 2022 movs r2, #32
367 0040 80F84120 strb r2, [r0, #65]
268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */
270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c);
368 .loc 1 270 5 is_stmt 1 discriminator 2 view .LVU125
369 .loc 1 270 5 discriminator 2 view .LVU126
370 0044 0020 movs r0, #0
371 .LVL26:
372 .loc 1 270 5 is_stmt 0 discriminator 2 view .LVU127
373 0046 83F84000 strb r0, [r3, #64]
374 .loc 1 270 5 is_stmt 1 discriminator 2 view .LVU128
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK;
375 .loc 1 272 5 discriminator 2 view .LVU129
376 .loc 1 272 12 is_stmt 0 discriminator 2 view .LVU130
377 004a 7047 bx lr
378 .LVL27:
379 .L15:
273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else
275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY;
380 .loc 1 276 12 view .LVU131
381 004c 0220 movs r0, #2
382 .LVL28:
383 .loc 1 276 12 view .LVU132
384 004e 7047 bx lr
385 .LVL29:
386 .L16:
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
387 .loc 1 255 5 view .LVU133
388 0050 0220 movs r0, #2
389 .LVL30:
277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
390 .loc 1 278 1 view .LVU134
391 0052 7047 bx lr
392 .cfi_endproc
393 .LFE133:
395 .section .text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits
396 .align 1
397 .global HAL_I2CEx_EnableFastModePlus
398 .syntax unified
399 .thumb
400 .thumb_func
402 HAL_I2CEx_EnableFastModePlus:
403 .LVL31:
404 .LFB134:
279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @}
281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Fast Mode Plus Functions
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 13
286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim
287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ===============================================================================
288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### Fast Mode Plus Functions #####
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ===============================================================================
290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to:
291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Fast Mode Plus
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim
294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{
295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Enable the I2C fast mode plus driving capability.
299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin.
300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values
301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be enabled on all selected
302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9.
304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be enabled
307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter.
308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be enabled
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter.
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval None
311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
405 .loc 1 313 1 is_stmt 1 view -0
406 .cfi_startproc
407 @ args = 0, pretend = 0, frame = 8
408 @ frame_needed = 0, uses_anonymous_args = 0
409 @ link register save eliminated.
410 .loc 1 313 1 is_stmt 0 view .LVU136
411 0000 82B0 sub sp, sp, #8
412 .cfi_def_cfa_offset 8
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameter */
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
413 .loc 1 315 3 is_stmt 1 view .LVU137
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */
318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
414 .loc 1 318 3 view .LVU138
415 .LBB2:
416 .loc 1 318 3 view .LVU139
417 .loc 1 318 3 view .LVU140
418 0002 084B ldr r3, .L19
419 0004 9A69 ldr r2, [r3, #24]
420 0006 42F00102 orr r2, r2, #1
421 000a 9A61 str r2, [r3, #24]
422 .loc 1 318 3 view .LVU141
423 000c 9B69 ldr r3, [r3, #24]
424 000e 03F00103 and r3, r3, #1
425 0012 0193 str r3, [sp, #4]
426 .loc 1 318 3 view .LVU142
427 0014 019B ldr r3, [sp, #4]
428 .LBE2:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 14
429 .loc 1 318 3 view .LVU143
319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable fast mode plus driving capability for selected pin */
321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
430 .loc 1 321 3 view .LVU144
431 0016 044A ldr r2, .L19+4
432 0018 1368 ldr r3, [r2]
433 001a 0343 orrs r3, r3, r0
434 001c 1360 str r3, [r2]
322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
435 .loc 1 322 1 is_stmt 0 view .LVU145
436 001e 02B0 add sp, sp, #8
437 .cfi_def_cfa_offset 0
438 @ sp needed
439 0020 7047 bx lr
440 .L20:
441 0022 00BF .align 2
442 .L19:
443 0024 00100240 .word 1073876992
444 0028 00000140 .word 1073807360
445 .cfi_endproc
446 .LFE134:
448 .section .text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits
449 .align 1
450 .global HAL_I2CEx_DisableFastModePlus
451 .syntax unified
452 .thumb
453 .thumb_func
455 HAL_I2CEx_DisableFastModePlus:
456 .LVL32:
457 .LFB135:
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /**
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Disable the I2C fast mode plus driving capability.
326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin.
327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be disabled on all selected
329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9.
331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be disabled
334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter.
335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be disabled
336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter.
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval None
338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */
339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** {
458 .loc 1 340 1 is_stmt 1 view -0
459 .cfi_startproc
460 @ args = 0, pretend = 0, frame = 8
461 @ frame_needed = 0, uses_anonymous_args = 0
462 @ link register save eliminated.
463 .loc 1 340 1 is_stmt 0 view .LVU147
464 0000 82B0 sub sp, sp, #8
465 .cfi_def_cfa_offset 8
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 15
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameter */
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
466 .loc 1 342 3 is_stmt 1 view .LVU148
343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */
345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
467 .loc 1 345 3 view .LVU149
468 .LBB3:
469 .loc 1 345 3 view .LVU150
470 .loc 1 345 3 view .LVU151
471 0002 084B ldr r3, .L23
472 0004 9A69 ldr r2, [r3, #24]
473 0006 42F00102 orr r2, r2, #1
474 000a 9A61 str r2, [r3, #24]
475 .loc 1 345 3 view .LVU152
476 000c 9B69 ldr r3, [r3, #24]
477 000e 03F00103 and r3, r3, #1
478 0012 0193 str r3, [sp, #4]
479 .loc 1 345 3 view .LVU153
480 0014 019B ldr r3, [sp, #4]
481 .LBE3:
482 .loc 1 345 3 view .LVU154
346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ****
347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable fast mode plus driving capability for selected pin */
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
483 .loc 1 348 3 view .LVU155
484 0016 044A ldr r2, .L23+4
485 0018 1368 ldr r3, [r2]
486 001a 23EA0003 bic r3, r3, r0
487 001e 1360 str r3, [r2]
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** }
488 .loc 1 349 1 is_stmt 0 view .LVU156
489 0020 02B0 add sp, sp, #8
490 .cfi_def_cfa_offset 0
491 @ sp needed
492 0022 7047 bx lr
493 .L24:
494 .align 2
495 .L23:
496 0024 00100240 .word 1073876992
497 0028 00000140 .word 1073807360
498 .cfi_endproc
499 .LFE135:
501 .text
502 .Letext0:
503 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
504 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
505 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
506 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
507 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
508 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s page 16
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_i2c_ex.c
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:21 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:27 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 HAL_I2CEx_ConfigAnalogFilter
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:119 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:125 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 HAL_I2CEx_ConfigDigitalFilter
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:222 .text.HAL_I2CEx_EnableWakeUp:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:228 .text.HAL_I2CEx_EnableWakeUp:00000000 HAL_I2CEx_EnableWakeUp
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:309 .text.HAL_I2CEx_DisableWakeUp:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:315 .text.HAL_I2CEx_DisableWakeUp:00000000 HAL_I2CEx_DisableWakeUp
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:396 .text.HAL_I2CEx_EnableFastModePlus:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:402 .text.HAL_I2CEx_EnableFastModePlus:00000000 HAL_I2CEx_EnableFastModePlus
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:443 .text.HAL_I2CEx_EnableFastModePlus:00000024 $d
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:449 .text.HAL_I2CEx_DisableFastModePlus:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:455 .text.HAL_I2CEx_DisableFastModePlus:00000000 HAL_I2CEx_DisableFastModePlus
C:\Users\nived\AppData\Local\Temp\ccsv8JoW.s:496 .text.HAL_I2CEx_DisableFastModePlus:00000024 $d
NO UNDEFINED SYMBOLS

2675
build/stm32f3xx_hal_msp.lst
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ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f3xx_hal_pwr.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c"
20 .section .text.HAL_PWR_DeInit,"ax",%progbits
21 .align 1
22 .global HAL_PWR_DeInit
23 .syntax unified
24 .thumb
25 .thumb_func
27 HAL_PWR_DeInit:
28 .LFB130:
1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @file stm32f3xx_hal_pwr.c
4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @author MCD Application Team
5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver.
6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Initialization/de-initialization functions
9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Peripheral Control functions
10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @attention
13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Copyright (c) 2016 STMicroelectronics.
15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * All rights reserved.
16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file
18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * in the root directory of this software component.
19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #include "stm32f3xx_hal.h"
26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @addtogroup STM32F3xx_HAL_Driver
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 2
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR
32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver
33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data
58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted
59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** write accesses.
60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values.
71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
29 .loc 1 74 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
34 .loc 1 75 3 view .LVU1
35 0000 044B ldr r3, .L2
36 0002 1A69 ldr r2, [r3, #16]
37 0004 42F08052 orr r2, r2, #268435456
38 0008 1A61 str r2, [r3, #16]
76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
39 .loc 1 76 3 view .LVU2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 3
40 000a 1A69 ldr r2, [r3, #16]
41 000c 22F08052 bic r2, r2, #268435456
42 0010 1A61 str r2, [r3, #16]
77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
43 .loc 1 77 1 is_stmt 0 view .LVU3
44 0012 7047 bx lr
45 .L3:
46 .align 2
47 .L2:
48 0014 00100240 .word 1073876992
49 .cfi_endproc
50 .LFE130:
52 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
53 .align 1
54 .global HAL_PWR_EnableBkUpAccess
55 .syntax unified
56 .thumb
57 .thumb_func
59 HAL_PWR_EnableBkUpAccess:
60 .LFB131:
78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC
81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
61 .loc 1 87 1 is_stmt 1 view -0
62 .cfi_startproc
63 @ args = 0, pretend = 0, frame = 0
64 @ frame_needed = 0, uses_anonymous_args = 0
65 @ link register save eliminated.
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP);
66 .loc 1 88 3 view .LVU5
67 0000 024A ldr r2, .L5
68 0002 1368 ldr r3, [r2]
69 0004 43F48073 orr r3, r3, #256
70 0008 1360 str r3, [r2]
89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
71 .loc 1 89 1 is_stmt 0 view .LVU6
72 000a 7047 bx lr
73 .L6:
74 .align 2
75 .L5:
76 000c 00700040 .word 1073770496
77 .cfi_endproc
78 .LFE131:
80 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
81 .align 1
82 .global HAL_PWR_DisableBkUpAccess
83 .syntax unified
84 .thumb
85 .thumb_func
87 HAL_PWR_DisableBkUpAccess:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 4
88 .LFB132:
90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC
93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
89 .loc 1 99 1 is_stmt 1 view -0
90 .cfi_startproc
91 @ args = 0, pretend = 0, frame = 0
92 @ frame_needed = 0, uses_anonymous_args = 0
93 @ link register save eliminated.
100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP);
94 .loc 1 100 3 view .LVU8
95 0000 024A ldr r2, .L8
96 0002 1368 ldr r3, [r2]
97 0004 23F48073 bic r3, r3, #256
98 0008 1360 str r3, [r2]
101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
99 .loc 1 101 1 is_stmt 0 view .LVU9
100 000a 7047 bx lr
101 .L9:
102 .align 2
103 .L8:
104 000c 00700040 .word 1073770496
105 .cfi_endproc
106 .LFE132:
108 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
109 .align 1
110 .global HAL_PWR_EnableWakeUpPin
111 .syntax unified
112 .thumb
113 .thumb_func
115 HAL_PWR_EnableWakeUpPin:
116 .LVL0:
117 .LFB133:
102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @}
105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Low Power modes configuration functions
109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Peripheral Control functions #####
114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** WakeUp pin configuration ***
117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================
118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 5
119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** forced in input pull down configuration and is active on rising edges.
121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) There are up to three WakeUp pins:
122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 1 on PA.00.
123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 3 on PE.06.
125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Main and Backup Regulators configuration ***
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================================
128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to
131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** save battery life.
132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** protected to prevent confidential data, such as cryptographic private
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** key, from being accessed. The backup SRAM can be erased only through
136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the Flash interface when a protection level change from level 1 to
137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** level 0 is requested.
138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** -@- Refer to the description of Read protection (RDP) in the Flash
139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programming manual.
140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Refer to the datasheets for more details.
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Low Power modes configuration ***
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =====================================
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The devices feature 3 low-power modes:
147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator
149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** in low power mode
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Sleep mode ***
153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ==================
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** functions with
158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode.
164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Stop mode ***
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =================
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** are preserved.
171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode to minimize the co
172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** function with:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 6
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Main regulator ON or
177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Low Power regulator ON.
178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** when programmed in wakeup mode (the peripheral must be
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programmed in wakeup mode and the corresponding interrupt vector
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** must be enabled in the NVIC).
186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Standby mode ***
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ====================
189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based
191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost
194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** circuitry.
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator is OFF.
197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================
206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event,
209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode).
210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the
218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT()
222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode
224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c
227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling
228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function.
229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the comparator to generate the event.
230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 7
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality.
236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be value of :
238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
118 .loc 1 242 1 is_stmt 1 view -0
119 .cfi_startproc
120 @ args = 0, pretend = 0, frame = 0
121 @ frame_needed = 0, uses_anonymous_args = 0
122 @ link register save eliminated.
243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
123 .loc 1 244 3 view .LVU11
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Enable the EWUPx pin */
246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx);
124 .loc 1 246 3 view .LVU12
125 0000 024A ldr r2, .L11
126 0002 5368 ldr r3, [r2, #4]
127 0004 0343 orrs r3, r3, r0
128 0006 5360 str r3, [r2, #4]
247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
129 .loc 1 247 1 is_stmt 0 view .LVU13
130 0008 7047 bx lr
131 .L12:
132 000a 00BF .align 2
133 .L11:
134 000c 00700040 .word 1073770496
135 .cfi_endproc
136 .LFE133:
138 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
139 .align 1
140 .global HAL_PWR_DisableWakeUpPin
141 .syntax unified
142 .thumb
143 .thumb_func
145 HAL_PWR_DisableWakeUpPin:
146 .LVL1:
147 .LFB134:
248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality.
251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be values of :
253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
148 .loc 1 257 1 is_stmt 1 view -0
149 .cfi_startproc
150 @ args = 0, pretend = 0, frame = 0
151 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 8
152 @ link register save eliminated.
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
153 .loc 1 259 3 view .LVU15
260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Disable the EWUPx pin */
261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx);
154 .loc 1 261 3 view .LVU16
155 0000 024A ldr r2, .L14
156 0002 5368 ldr r3, [r2, #4]
157 0004 23EA0003 bic r3, r3, r0
158 0008 5360 str r3, [r2, #4]
262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
159 .loc 1 262 1 is_stmt 0 view .LVU17
160 000a 7047 bx lr
161 .L15:
162 .align 2
163 .L14:
164 000c 00700040 .word 1073770496
165 .cfi_endproc
166 .LFE134:
168 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
169 .align 1
170 .global HAL_PWR_EnterSLEEPMode
171 .syntax unified
172 .thumb
173 .thumb_func
175 HAL_PWR_EnterSLEEPMode:
176 .LVL2:
177 .LFB135:
263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters Sleep mode.
266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode.
268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note This parameter has no effect in F3 family and is just maintained to
272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * offer full portability of other STM32 families software.
273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as
275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the interrupt wake up source.
276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
178 .loc 1 282 1 is_stmt 1 view -0
179 .cfi_startproc
180 @ args = 0, pretend = 0, frame = 0
181 @ frame_needed = 0, uses_anonymous_args = 0
182 @ link register save eliminated.
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
183 .loc 1 284 3 view .LVU19
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 9
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
184 .loc 1 287 3 view .LVU20
185 .loc 1 287 6 is_stmt 0 view .LVU21
186 0000 064A ldr r2, .L20
187 0002 1369 ldr r3, [r2, #16]
188 .loc 1 287 12 view .LVU22
189 0004 23F00403 bic r3, r3, #4
190 0008 1361 str r3, [r2, #16]
288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
191 .loc 1 290 3 is_stmt 1 view .LVU23
192 .loc 1 290 5 is_stmt 0 view .LVU24
193 000a 0129 cmp r1, #1
194 000c 03D0 beq .L19
291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
195 .loc 1 298 5 is_stmt 1 view .LVU25
196 .syntax unified
197 @ 298 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
198 000e 40BF sev
199 @ 0 "" 2
299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
200 .loc 1 299 5 view .LVU26
201 @ 299 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
202 0010 20BF wfe
203 @ 0 "" 2
300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
204 .loc 1 300 5 view .LVU27
205 @ 300 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
206 0012 20BF wfe
207 @ 0 "" 2
301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
208 .loc 1 302 1 is_stmt 0 view .LVU28
209 .thumb
210 .syntax unified
211 0014 7047 bx lr
212 .L19:
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
213 .loc 1 293 5 is_stmt 1 view .LVU29
214 .syntax unified
215 @ 293 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
216 0016 30BF wfi
217 @ 0 "" 2
218 .thumb
219 .syntax unified
220 0018 7047 bx lr
221 .L21:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 10
222 001a 00BF .align 2
223 .L20:
224 001c 00ED00E0 .word -536810240
225 .cfi_endproc
226 .LFE135:
228 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
229 .align 1
230 .global HAL_PWR_EnterSTOPMode
231 .syntax unified
232 .thumb
233 .thumb_func
235 HAL_PWR_EnterSTOPMode:
236 .LVL3:
237 .LFB136:
303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STOP mode.
306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock.
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode.
311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption
312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * is higher although the startup time is reduced.
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in STOP mode.
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
238 .loc 1 324 1 view -0
239 .cfi_startproc
240 @ args = 0, pretend = 0, frame = 0
241 @ frame_needed = 0, uses_anonymous_args = 0
242 @ link register save eliminated.
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** uint32_t tmpreg = 0U;
243 .loc 1 325 3 view .LVU31
326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
244 .loc 1 328 3 view .LVU32
329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
245 .loc 1 329 3 view .LVU33
330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select the regulator state in STOP mode ---------------------------------*/
332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg = PWR->CR;
246 .loc 1 332 3 view .LVU34
247 .loc 1 332 10 is_stmt 0 view .LVU35
248 0000 0B4A ldr r2, .L26
249 0002 1368 ldr r3, [r2]
250 .LVL4:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 11
333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */
335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
251 .loc 1 335 3 is_stmt 1 view .LVU36
252 .loc 1 335 10 is_stmt 0 view .LVU37
253 0004 23F00303 bic r3, r3, #3
254 .LVL5:
336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set LPDS bit according to Regulator value */
338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg |= Regulator;
255 .loc 1 338 3 is_stmt 1 view .LVU38
256 .loc 1 338 10 is_stmt 0 view .LVU39
257 0008 0343 orrs r3, r3, r0
258 .LVL6:
339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Store the new value */
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR = tmpreg;
259 .loc 1 341 3 is_stmt 1 view .LVU40
260 .loc 1 341 11 is_stmt 0 view .LVU41
261 000a 1360 str r3, [r2]
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
262 .loc 1 344 3 is_stmt 1 view .LVU42
263 .loc 1 344 6 is_stmt 0 view .LVU43
264 000c 094A ldr r2, .L26+4
265 000e 1369 ldr r3, [r2, #16]
266 .LVL7:
267 .loc 1 344 12 view .LVU44
268 0010 43F00403 orr r3, r3, #4
269 0014 1361 str r3, [r2, #16]
270 .LVL8:
345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STOP mode entry --------------------------------------------------*/
347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI)
271 .loc 1 347 3 is_stmt 1 view .LVU45
272 .loc 1 347 5 is_stmt 0 view .LVU46
273 0016 0129 cmp r1, #1
274 0018 08D0 beq .L25
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
275 .loc 1 355 5 is_stmt 1 view .LVU47
276 .syntax unified
277 @ 355 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
278 001a 40BF sev
279 @ 0 "" 2
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
280 .loc 1 356 5 view .LVU48
281 @ 356 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
282 001c 20BF wfe
283 @ 0 "" 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 12
357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
284 .loc 1 357 5 view .LVU49
285 @ 357 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
286 001e 20BF wfe
287 @ 0 "" 2
288 .thumb
289 .syntax unified
290 .L24:
358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */
361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
291 .loc 1 361 3 view .LVU50
292 .loc 1 361 6 is_stmt 0 view .LVU51
293 0020 044A ldr r2, .L26+4
294 0022 1369 ldr r3, [r2, #16]
295 .loc 1 361 12 view .LVU52
296 0024 23F00403 bic r3, r3, #4
297 0028 1361 str r3, [r2, #16]
362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
298 .loc 1 362 1 view .LVU53
299 002a 7047 bx lr
300 .L25:
350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
301 .loc 1 350 5 is_stmt 1 view .LVU54
302 .syntax unified
303 @ 350 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
304 002c 30BF wfi
305 @ 0 "" 2
306 .thumb
307 .syntax unified
308 002e F7E7 b .L24
309 .L27:
310 .align 2
311 .L26:
312 0030 00700040 .word 1073770496
313 0034 00ED00E0 .word -536810240
314 .cfi_endproc
315 .LFE136:
317 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
318 .align 1
319 .global HAL_PWR_EnterSTANDBYMode
320 .syntax unified
321 .thumb
322 .thumb_func
324 HAL_PWR_EnterSTANDBYMode:
325 .LFB137:
363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STANDBY mode.
366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for:
367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - Reset pad (still available),
368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - RTC alternate function pins if configured for tamper, time-stamp, RTC
369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out,
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - WKUP pins if enabled.
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 13
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
326 .loc 1 374 1 view -0
327 .cfi_startproc
328 @ args = 0, pretend = 0, frame = 0
329 @ frame_needed = 0, uses_anonymous_args = 0
330 @ link register save eliminated.
375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STANDBY mode */
376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR |= PWR_CR_PDDS;
331 .loc 1 376 3 view .LVU56
332 .loc 1 376 6 is_stmt 0 view .LVU57
333 0000 054A ldr r2, .L29
334 0002 1368 ldr r3, [r2]
335 .loc 1 376 11 view .LVU58
336 0004 43F00203 orr r3, r3, #2
337 0008 1360 str r3, [r2]
377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
338 .loc 1 379 3 is_stmt 1 view .LVU59
339 .loc 1 379 6 is_stmt 0 view .LVU60
340 000a 044A ldr r2, .L29+4
341 000c 1369 ldr r3, [r2, #16]
342 .loc 1 379 12 view .LVU61
343 000e 43F00403 orr r3, r3, #4
344 0012 1361 str r3, [r2, #16]
380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #if defined ( __CC_ARM)
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __force_stores();
384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #endif
385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
345 .loc 1 386 3 is_stmt 1 view .LVU62
346 .syntax unified
347 @ 386 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
348 0014 30BF wfi
349 @ 0 "" 2
387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
350 .loc 1 387 1 is_stmt 0 view .LVU63
351 .thumb
352 .syntax unified
353 0016 7047 bx lr
354 .L30:
355 .align 2
356 .L29:
357 0018 00700040 .word 1073770496
358 001c 00ED00E0 .word -536810240
359 .cfi_endproc
360 .LFE137:
362 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
363 .align 1
364 .global HAL_PWR_EnableSleepOnExit
365 .syntax unified
366 .thumb
367 .thumb_func
369 HAL_PWR_EnableSleepOnExit:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 14
370 .LFB138:
388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * interruptions handling.
395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
371 .loc 1 398 1 is_stmt 1 view -0
372 .cfi_startproc
373 @ args = 0, pretend = 0, frame = 0
374 @ frame_needed = 0, uses_anonymous_args = 0
375 @ link register save eliminated.
399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
376 .loc 1 400 3 view .LVU65
377 0000 024A ldr r2, .L32
378 0002 1369 ldr r3, [r2, #16]
379 0004 43F00203 orr r3, r3, #2
380 0008 1361 str r3, [r2, #16]
401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
381 .loc 1 401 1 is_stmt 0 view .LVU66
382 000a 7047 bx lr
383 .L33:
384 .align 2
385 .L32:
386 000c 00ED00E0 .word -536810240
387 .cfi_endproc
388 .LFE138:
390 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
391 .align 1
392 .global HAL_PWR_DisableSleepOnExit
393 .syntax unified
394 .thumb
395 .thumb_func
397 HAL_PWR_DisableSleepOnExit:
398 .LFB139:
402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
399 .loc 1 411 1 is_stmt 1 view -0
400 .cfi_startproc
401 @ args = 0, pretend = 0, frame = 0
402 @ frame_needed = 0, uses_anonymous_args = 0
403 @ link register save eliminated.
412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 15
413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
404 .loc 1 413 3 view .LVU68
405 0000 024A ldr r2, .L35
406 0002 1369 ldr r3, [r2, #16]
407 0004 23F00203 bic r3, r3, #2
408 0008 1361 str r3, [r2, #16]
414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
409 .loc 1 414 1 is_stmt 0 view .LVU69
410 000a 7047 bx lr
411 .L36:
412 .align 2
413 .L35:
414 000c 00ED00E0 .word -536810240
415 .cfi_endproc
416 .LFE139:
418 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
419 .align 1
420 .global HAL_PWR_EnableSEVOnPend
421 .syntax unified
422 .thumb
423 .thumb_func
425 HAL_PWR_EnableSEVOnPend:
426 .LFB140:
415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit.
420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
427 .loc 1 425 1 is_stmt 1 view -0
428 .cfi_startproc
429 @ args = 0, pretend = 0, frame = 0
430 @ frame_needed = 0, uses_anonymous_args = 0
431 @ link register save eliminated.
426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
432 .loc 1 427 3 view .LVU71
433 0000 024A ldr r2, .L38
434 0002 1369 ldr r3, [r2, #16]
435 0004 43F01003 orr r3, r3, #16
436 0008 1361 str r3, [r2, #16]
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
437 .loc 1 428 1 is_stmt 0 view .LVU72
438 000a 7047 bx lr
439 .L39:
440 .align 2
441 .L38:
442 000c 00ED00E0 .word -536810240
443 .cfi_endproc
444 .LFE140:
446 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
447 .align 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 16
448 .global HAL_PWR_DisableSEVOnPend
449 .syntax unified
450 .thumb
451 .thumb_func
453 HAL_PWR_DisableSEVOnPend:
454 .LFB141:
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit.
433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
455 .loc 1 438 1 is_stmt 1 view -0
456 .cfi_startproc
457 @ args = 0, pretend = 0, frame = 0
458 @ frame_needed = 0, uses_anonymous_args = 0
459 @ link register save eliminated.
439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
460 .loc 1 440 3 view .LVU74
461 0000 024A ldr r2, .L41
462 0002 1369 ldr r3, [r2, #16]
463 0004 23F01003 bic r3, r3, #16
464 0008 1361 str r3, [r2, #16]
441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
465 .loc 1 441 1 is_stmt 0 view .LVU75
466 000a 7047 bx lr
467 .L42:
468 .align 2
469 .L41:
470 000c 00ED00E0 .word -536810240
471 .cfi_endproc
472 .LFE141:
474 .text
475 .Letext0:
476 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
477 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
478 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
479 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 17
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_pwr.c
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:21 .text.HAL_PWR_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:27 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:48 .text.HAL_PWR_DeInit:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:53 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:59 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:76 .text.HAL_PWR_EnableBkUpAccess:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:81 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:87 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:104 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:109 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:115 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:134 .text.HAL_PWR_EnableWakeUpPin:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:139 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:145 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:164 .text.HAL_PWR_DisableWakeUpPin:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:169 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:175 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:224 .text.HAL_PWR_EnterSLEEPMode:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:229 .text.HAL_PWR_EnterSTOPMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:235 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:312 .text.HAL_PWR_EnterSTOPMode:00000030 $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:318 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:324 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:357 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:363 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:369 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:386 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:391 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:397 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:414 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:419 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:425 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:442 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:447 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:453 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:470 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
NO UNDEFINED SYMBOLS

498
build/stm32f3xx_hal_pwr_ex.lst
View File

@ -1,498 +0,0 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f3xx_hal_pwr_ex.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c"
20 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits
21 .align 1
22 .global HAL_PWR_ConfigPVD
23 .syntax unified
24 .thumb
25 .thumb_func
27 HAL_PWR_ConfigPVD:
28 .LVL0:
29 .LFB130:
1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /**
2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ******************************************************************************
3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @file stm32f3xx_hal_pwr_ex.c
4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @author MCD Application Team
5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver.
6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * functionalities of the Power Controller (PWR) peripheral:
8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + Extended Initialization and de-initialization functions
9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + Extended Peripheral Control functions
10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *
11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ******************************************************************************
12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @attention
13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *
14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * Copyright (c) 2016 STMicroelectronics.
15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * All rights reserved.
16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *
17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * This software is licensed under terms that can be found in the LICENSE file
18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * in the root directory of this software component.
19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *
21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ******************************************************************************
22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/
25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #include "stm32f3xx_hal.h"
26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 2
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx
32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief PWREx HAL module driver
33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{
34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED
37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/
39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/
40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Private_Constants PWR Extended Private Constants
41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{
42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_MODE_IT (0x00010000U)
44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_MODE_EVT (0x00020000U)
45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_RISING_EDGE (0x00000001U)
46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_FALLING_EDGE (0x00000002U)
47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /**
48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @}
49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/
52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/
53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/
54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Exported functions ---------------------------------------------------------*/
55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{
58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Extended Peripheral Control functions
62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *
63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** @verbatim
64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ===============================================================================
66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ##### Peripheral Extended control functions #####
67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ===============================================================================
68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** PVD configuration (present on all other devices than STM32F3x8 devices) ***
69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** =========================
70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..]
71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a
72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** than the PVD threshold. This event is internally connected to the EXTI
75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** line16 and can generate an interrupt if enabled. This is done through
76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is stopped in Standby mode.
78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** -@- PVD is not available on STM32F3x8 Product Line
79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** Voltage regulator ***
82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** =========================
83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..]
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The voltage regulator is always enabled after Reset. It works in three different
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** modes.
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Run mode, the regulator supplies full power to the 1.8V domain (core, memories
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 3
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** and digital peripherals).
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Stop mode, the regulator supplies low power to the 1.8V domain, preserving
89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** contents of registers and SRAM.
90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Stop mode, the regulator is powered off. The contents of the registers and SRAM
91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** are lost except for the Standby circuitry and the Backup Domain.
92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the
93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage.
94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** than the PVD threshold. This event is internally connected to the EXTI
98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** line16 and can generate an interrupt if enabled. This is done through
99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is stopped in Standby mode.
101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** SDADC power configuration ***
104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ================================
105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..]
106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) On STM32F373xC/STM32F378xx devices, there are up to
107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** 3 SDADC instances that can be enabled/disabled.
108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** @endverbatim
110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{
111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || \
114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F302xC) || defined(STM32F303xC) || \
115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F303x8) || defined(STM32F334x8) || \
116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F301x8) || defined(STM32F302x8) || \
117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F373xC)
118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /**
120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * information for the PVD.
123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @note Refer to the electrical characteristics of your device datasheet for
124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * more details about the voltage threshold corresponding to each
125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * detection level.
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
30 .loc 1 129 1 view -0
31 .cfi_startproc
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Check the parameters */
131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
35 .loc 1 131 3 view .LVU1
132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
36 .loc 1 132 3 view .LVU2
133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Set PLS[7:5] bits according to PVDLevel value */
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
37 .loc 1 135 3 view .LVU3
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 4
38 0000 1E4A ldr r2, .L6
39 0002 1368 ldr r3, [r2]
40 0004 23F0E003 bic r3, r3, #224
41 0008 0168 ldr r1, [r0]
42 000a 0B43 orrs r3, r3, r1
43 000c 1360 str r3, [r2]
136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */
138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
44 .loc 1 138 3 view .LVU4
45 000e 1C4B ldr r3, .L6+4
46 0010 5A68 ldr r2, [r3, #4]
47 0012 22F48032 bic r2, r2, #65536
48 0016 5A60 str r2, [r3, #4]
139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT();
49 .loc 1 139 3 view .LVU5
50 0018 1A68 ldr r2, [r3]
51 001a 22F48032 bic r2, r2, #65536
52 001e 1A60 str r2, [r3]
140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
53 .loc 1 140 3 view .LVU6
54 0020 9A68 ldr r2, [r3, #8]
55 0022 22F48032 bic r2, r2, #65536
56 0026 9A60 str r2, [r3, #8]
57 .loc 1 140 44 view .LVU7
58 0028 DA68 ldr r2, [r3, #12]
59 002a 22F48032 bic r2, r2, #65536
60 002e DA60 str r2, [r3, #12]
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure interrupt mode */
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
61 .loc 1 143 3 view .LVU8
62 .loc 1 143 17 is_stmt 0 view .LVU9
63 0030 4368 ldr r3, [r0, #4]
64 .loc 1 143 5 view .LVU10
65 0032 13F4803F tst r3, #65536
66 0036 04D0 beq .L2
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT();
67 .loc 1 145 5 is_stmt 1 view .LVU11
68 0038 114A ldr r2, .L6+4
69 003a 1368 ldr r3, [r2]
70 003c 43F48033 orr r3, r3, #65536
71 0040 1360 str r3, [r2]
72 .L2:
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure event mode */
149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
73 .loc 1 149 3 view .LVU12
74 .loc 1 149 17 is_stmt 0 view .LVU13
75 0042 4368 ldr r3, [r0, #4]
76 .loc 1 149 5 view .LVU14
77 0044 13F4003F tst r3, #131072
78 0048 04D0 beq .L3
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 5
79 .loc 1 151 5 is_stmt 1 view .LVU15
80 004a 0D4A ldr r2, .L6+4
81 004c 5368 ldr r3, [r2, #4]
82 004e 43F48033 orr r3, r3, #65536
83 0052 5360 str r3, [r2, #4]
84 .L3:
152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure the edge */
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
85 .loc 1 155 3 view .LVU16
86 .loc 1 155 17 is_stmt 0 view .LVU17
87 0054 4368 ldr r3, [r0, #4]
88 .loc 1 155 5 view .LVU18
89 0056 13F0010F tst r3, #1
90 005a 04D0 beq .L4
156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
91 .loc 1 157 5 is_stmt 1 view .LVU19
92 005c 084A ldr r2, .L6+4
93 005e 9368 ldr r3, [r2, #8]
94 0060 43F48033 orr r3, r3, #65536
95 0064 9360 str r3, [r2, #8]
96 .L4:
158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
97 .loc 1 160 3 view .LVU20
98 .loc 1 160 17 is_stmt 0 view .LVU21
99 0066 4368 ldr r3, [r0, #4]
100 .loc 1 160 5 view .LVU22
101 0068 13F0020F tst r3, #2
102 006c 04D0 beq .L1
161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
103 .loc 1 162 5 is_stmt 1 view .LVU23
104 006e 044A ldr r2, .L6+4
105 0070 D368 ldr r3, [r2, #12]
106 0072 43F48033 orr r3, r3, #65536
107 0076 D360 str r3, [r2, #12]
108 .L1:
163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
109 .loc 1 164 1 is_stmt 0 view .LVU24
110 0078 7047 bx lr
111 .L7:
112 007a 00BF .align 2
113 .L6:
114 007c 00700040 .word 1073770496
115 0080 00040140 .word 1073808384
116 .cfi_endproc
117 .LFE130:
119 .section .text.HAL_PWR_EnablePVD,"ax",%progbits
120 .align 1
121 .global HAL_PWR_EnablePVD
122 .syntax unified
123 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 6
124 .thumb_func
126 HAL_PWR_EnablePVD:
127 .LFB131:
165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /**
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Enables the Power Voltage Detector(PVD).
168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None
169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_EnablePVD(void)
171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
128 .loc 1 171 1 is_stmt 1 view -0
129 .cfi_startproc
130 @ args = 0, pretend = 0, frame = 0
131 @ frame_needed = 0, uses_anonymous_args = 0
132 @ link register save eliminated.
172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** SET_BIT(PWR->CR, PWR_CR_PVDE);
133 .loc 1 172 3 view .LVU26
134 0000 024A ldr r2, .L9
135 0002 1368 ldr r3, [r2]
136 0004 43F01003 orr r3, r3, #16
137 0008 1360 str r3, [r2]
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
138 .loc 1 173 1 is_stmt 0 view .LVU27
139 000a 7047 bx lr
140 .L10:
141 .align 2
142 .L9:
143 000c 00700040 .word 1073770496
144 .cfi_endproc
145 .LFE131:
147 .section .text.HAL_PWR_DisablePVD,"ax",%progbits
148 .align 1
149 .global HAL_PWR_DisablePVD
150 .syntax unified
151 .thumb
152 .thumb_func
154 HAL_PWR_DisablePVD:
155 .LFB132:
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /**
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Disables the Power Voltage Detector(PVD).
177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None
178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_DisablePVD(void)
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
156 .loc 1 180 1 is_stmt 1 view -0
157 .cfi_startproc
158 @ args = 0, pretend = 0, frame = 0
159 @ frame_needed = 0, uses_anonymous_args = 0
160 @ link register save eliminated.
181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
161 .loc 1 181 3 view .LVU29
162 0000 024A ldr r2, .L12
163 0002 1368 ldr r3, [r2]
164 0004 23F01003 bic r3, r3, #16
165 0008 1360 str r3, [r2]
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 7
166 .loc 1 182 1 is_stmt 0 view .LVU30
167 000a 7047 bx lr
168 .L13:
169 .align 2
170 .L12:
171 000c 00700040 .word 1073770496
172 .cfi_endproc
173 .LFE132:
175 .section .text.HAL_PWR_PVDCallback,"ax",%progbits
176 .align 1
177 .weak HAL_PWR_PVDCallback
178 .syntax unified
179 .thumb
180 .thumb_func
182 HAL_PWR_PVDCallback:
183 .LFB134:
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /**
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief This function handles the PWR PVD interrupt request.
186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @note This API should be called under the PVD_IRQHandler().
187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_PVD_IRQHandler(void)
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Check PWR exti flag */
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* PWR PVD interrupt user callback */
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** HAL_PWR_PVDCallback();
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Clear PWR Exti pending bit */
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /**
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief PWR PVD interrupt callback
204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None
205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __weak void HAL_PWR_PVDCallback(void)
207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
184 .loc 1 207 1 is_stmt 1 view -0
185 .cfi_startproc
186 @ args = 0, pretend = 0, frame = 0
187 @ frame_needed = 0, uses_anonymous_args = 0
188 @ link register save eliminated.
208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* NOTE : This function Should not be modified, when the callback is needed,
209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** the HAL_PWR_PVDCallback could be implemented in the user file
210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */
211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
189 .loc 1 211 1 view .LVU32
190 0000 7047 bx lr
191 .cfi_endproc
192 .LFE134:
194 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits
195 .align 1
196 .global HAL_PWR_PVD_IRQHandler
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 8
197 .syntax unified
198 .thumb
199 .thumb_func
201 HAL_PWR_PVD_IRQHandler:
202 .LFB133:
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Check PWR exti flag */
203 .loc 1 190 1 view -0
204 .cfi_startproc
205 @ args = 0, pretend = 0, frame = 0
206 @ frame_needed = 0, uses_anonymous_args = 0
207 0000 08B5 push {r3, lr}
208 .cfi_def_cfa_offset 8
209 .cfi_offset 3, -8
210 .cfi_offset 14, -4
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
211 .loc 1 192 3 view .LVU34
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
212 .loc 1 192 6 is_stmt 0 view .LVU35
213 0002 064B ldr r3, .L19
214 0004 5B69 ldr r3, [r3, #20]
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** {
215 .loc 1 192 5 view .LVU36
216 0006 13F4803F tst r3, #65536
217 000a 00D1 bne .L18
218 .L15:
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
219 .loc 1 200 1 view .LVU37
220 000c 08BD pop {r3, pc}
221 .L18:
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
222 .loc 1 195 5 is_stmt 1 view .LVU38
223 000e FFF7FEFF bl HAL_PWR_PVDCallback
224 .LVL1:
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** }
225 .loc 1 198 5 view .LVU39
226 0012 024B ldr r3, .L19
227 0014 4FF48032 mov r2, #65536
228 0018 5A61 str r2, [r3, #20]
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ****
229 .loc 1 200 1 is_stmt 0 view .LVU40
230 001a F7E7 b .L15
231 .L20:
232 .align 2
233 .L19:
234 001c 00040140 .word 1073808384
235 .cfi_endproc
236 .LFE133:
238 .text
239 .Letext0:
240 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
241 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
242 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
243 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h"
244 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s page 9
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_pwr_ex.c
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:21 .text.HAL_PWR_ConfigPVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:27 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:114 .text.HAL_PWR_ConfigPVD:0000007c $d
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:120 .text.HAL_PWR_EnablePVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:126 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:143 .text.HAL_PWR_EnablePVD:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:148 .text.HAL_PWR_DisablePVD:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:154 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:171 .text.HAL_PWR_DisablePVD:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:176 .text.HAL_PWR_PVDCallback:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:182 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:195 .text.HAL_PWR_PVD_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:201 .text.HAL_PWR_PVD_IRQHandler:00000000 HAL_PWR_PVD_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccq8UzNd.s:234 .text.HAL_PWR_PVD_IRQHandler:0000001c $d
NO UNDEFINED SYMBOLS

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ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f3xx_it.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/stm32f3xx_it.c"
20 .section .text.NMI_Handler,"ax",%progbits
21 .align 1
22 .global NMI_Handler
23 .syntax unified
24 .thumb
25 .thumb_func
27 NMI_Handler:
28 .LFB130:
1:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f3xx_it.c **** /**
3:Core/Src/stm32f3xx_it.c **** ******************************************************************************
4:Core/Src/stm32f3xx_it.c **** * @file stm32f3xx_it.c
5:Core/Src/stm32f3xx_it.c **** * @brief Interrupt Service Routines.
6:Core/Src/stm32f3xx_it.c **** ******************************************************************************
7:Core/Src/stm32f3xx_it.c **** * @attention
8:Core/Src/stm32f3xx_it.c **** *
9:Core/Src/stm32f3xx_it.c **** * Copyright (c) 2024 STMicroelectronics.
10:Core/Src/stm32f3xx_it.c **** * All rights reserved.
11:Core/Src/stm32f3xx_it.c **** *
12:Core/Src/stm32f3xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file
13:Core/Src/stm32f3xx_it.c **** * in the root directory of this software component.
14:Core/Src/stm32f3xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
15:Core/Src/stm32f3xx_it.c **** *
16:Core/Src/stm32f3xx_it.c **** ******************************************************************************
17:Core/Src/stm32f3xx_it.c **** */
18:Core/Src/stm32f3xx_it.c **** /* USER CODE END Header */
19:Core/Src/stm32f3xx_it.c ****
20:Core/Src/stm32f3xx_it.c **** /* Includes ------------------------------------------------------------------*/
21:Core/Src/stm32f3xx_it.c **** #include "main.h"
22:Core/Src/stm32f3xx_it.c **** #include "stm32f3xx_it.h"
23:Core/Src/stm32f3xx_it.c **** /* Private includes ----------------------------------------------------------*/
24:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN Includes */
25:Core/Src/stm32f3xx_it.c **** /* USER CODE END Includes */
26:Core/Src/stm32f3xx_it.c ****
27:Core/Src/stm32f3xx_it.c **** /* Private typedef -----------------------------------------------------------*/
28:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN TD */
29:Core/Src/stm32f3xx_it.c ****
30:Core/Src/stm32f3xx_it.c **** /* USER CODE END TD */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 2
31:Core/Src/stm32f3xx_it.c ****
32:Core/Src/stm32f3xx_it.c **** /* Private define ------------------------------------------------------------*/
33:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PD */
34:Core/Src/stm32f3xx_it.c ****
35:Core/Src/stm32f3xx_it.c **** /* USER CODE END PD */
36:Core/Src/stm32f3xx_it.c ****
37:Core/Src/stm32f3xx_it.c **** /* Private macro -------------------------------------------------------------*/
38:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PM */
39:Core/Src/stm32f3xx_it.c ****
40:Core/Src/stm32f3xx_it.c **** /* USER CODE END PM */
41:Core/Src/stm32f3xx_it.c ****
42:Core/Src/stm32f3xx_it.c **** /* Private variables ---------------------------------------------------------*/
43:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PV */
44:Core/Src/stm32f3xx_it.c ****
45:Core/Src/stm32f3xx_it.c **** /* USER CODE END PV */
46:Core/Src/stm32f3xx_it.c ****
47:Core/Src/stm32f3xx_it.c **** /* Private function prototypes -----------------------------------------------*/
48:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PFP */
49:Core/Src/stm32f3xx_it.c ****
50:Core/Src/stm32f3xx_it.c **** /* USER CODE END PFP */
51:Core/Src/stm32f3xx_it.c ****
52:Core/Src/stm32f3xx_it.c **** /* Private user code ---------------------------------------------------------*/
53:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN 0 */
54:Core/Src/stm32f3xx_it.c ****
55:Core/Src/stm32f3xx_it.c **** /* USER CODE END 0 */
56:Core/Src/stm32f3xx_it.c ****
57:Core/Src/stm32f3xx_it.c **** /* External variables --------------------------------------------------------*/
58:Core/Src/stm32f3xx_it.c **** extern DMA_HandleTypeDef hdma_adc1;
59:Core/Src/stm32f3xx_it.c **** extern DMA_HandleTypeDef hdma_adc2;
60:Core/Src/stm32f3xx_it.c **** extern CAN_HandleTypeDef hcan;
61:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN EV */
62:Core/Src/stm32f3xx_it.c ****
63:Core/Src/stm32f3xx_it.c **** /* USER CODE END EV */
64:Core/Src/stm32f3xx_it.c ****
65:Core/Src/stm32f3xx_it.c **** /******************************************************************************/
66:Core/Src/stm32f3xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */
67:Core/Src/stm32f3xx_it.c **** /******************************************************************************/
68:Core/Src/stm32f3xx_it.c **** /**
69:Core/Src/stm32f3xx_it.c **** * @brief This function handles Non maskable interrupt.
70:Core/Src/stm32f3xx_it.c **** */
71:Core/Src/stm32f3xx_it.c **** void NMI_Handler(void)
72:Core/Src/stm32f3xx_it.c **** {
29 .loc 1 72 1 view -0
30 .cfi_startproc
31 @ Volatile: function does not return.
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 0000 08B5 push {r3, lr}
35 .cfi_def_cfa_offset 8
36 .cfi_offset 3, -8
37 .cfi_offset 14, -4
73:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
74:Core/Src/stm32f3xx_it.c ****
75:Core/Src/stm32f3xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */
76:Core/Src/stm32f3xx_it.c **** HAL_RCC_NMI_IRQHandler();
38 .loc 1 76 3 view .LVU1
39 0002 FFF7FEFF bl HAL_RCC_NMI_IRQHandler
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 3
40 .LVL0:
41 .L2:
77:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
78:Core/Src/stm32f3xx_it.c **** while (1)
42 .loc 1 78 3 discriminator 1 view .LVU2
79:Core/Src/stm32f3xx_it.c **** {
80:Core/Src/stm32f3xx_it.c **** }
43 .loc 1 80 3 discriminator 1 view .LVU3
78:Core/Src/stm32f3xx_it.c **** {
44 .loc 1 78 9 discriminator 1 view .LVU4
45 0006 FEE7 b .L2
46 .cfi_endproc
47 .LFE130:
49 .section .text.HardFault_Handler,"ax",%progbits
50 .align 1
51 .global HardFault_Handler
52 .syntax unified
53 .thumb
54 .thumb_func
56 HardFault_Handler:
57 .LFB131:
81:Core/Src/stm32f3xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */
82:Core/Src/stm32f3xx_it.c **** }
83:Core/Src/stm32f3xx_it.c ****
84:Core/Src/stm32f3xx_it.c **** /**
85:Core/Src/stm32f3xx_it.c **** * @brief This function handles Hard fault interrupt.
86:Core/Src/stm32f3xx_it.c **** */
87:Core/Src/stm32f3xx_it.c **** void HardFault_Handler(void)
88:Core/Src/stm32f3xx_it.c **** {
58 .loc 1 88 1 view -0
59 .cfi_startproc
60 @ Volatile: function does not return.
61 @ args = 0, pretend = 0, frame = 0
62 @ frame_needed = 0, uses_anonymous_args = 0
63 @ link register save eliminated.
64 .L5:
89:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */
90:Core/Src/stm32f3xx_it.c ****
91:Core/Src/stm32f3xx_it.c **** /* USER CODE END HardFault_IRQn 0 */
92:Core/Src/stm32f3xx_it.c **** while (1)
65 .loc 1 92 3 discriminator 1 view .LVU6
93:Core/Src/stm32f3xx_it.c **** {
94:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */
95:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */
96:Core/Src/stm32f3xx_it.c **** }
66 .loc 1 96 3 discriminator 1 view .LVU7
92:Core/Src/stm32f3xx_it.c **** {
67 .loc 1 92 9 discriminator 1 view .LVU8
68 0000 FEE7 b .L5
69 .cfi_endproc
70 .LFE131:
72 .section .text.MemManage_Handler,"ax",%progbits
73 .align 1
74 .global MemManage_Handler
75 .syntax unified
76 .thumb
77 .thumb_func
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 4
79 MemManage_Handler:
80 .LFB132:
97:Core/Src/stm32f3xx_it.c **** }
98:Core/Src/stm32f3xx_it.c ****
99:Core/Src/stm32f3xx_it.c **** /**
100:Core/Src/stm32f3xx_it.c **** * @brief This function handles Memory management fault.
101:Core/Src/stm32f3xx_it.c **** */
102:Core/Src/stm32f3xx_it.c **** void MemManage_Handler(void)
103:Core/Src/stm32f3xx_it.c **** {
81 .loc 1 103 1 view -0
82 .cfi_startproc
83 @ Volatile: function does not return.
84 @ args = 0, pretend = 0, frame = 0
85 @ frame_needed = 0, uses_anonymous_args = 0
86 @ link register save eliminated.
87 .L7:
104:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */
105:Core/Src/stm32f3xx_it.c ****
106:Core/Src/stm32f3xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */
107:Core/Src/stm32f3xx_it.c **** while (1)
88 .loc 1 107 3 discriminator 1 view .LVU10
108:Core/Src/stm32f3xx_it.c **** {
109:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
110:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */
111:Core/Src/stm32f3xx_it.c **** }
89 .loc 1 111 3 discriminator 1 view .LVU11
107:Core/Src/stm32f3xx_it.c **** {
90 .loc 1 107 9 discriminator 1 view .LVU12
91 0000 FEE7 b .L7
92 .cfi_endproc
93 .LFE132:
95 .section .text.BusFault_Handler,"ax",%progbits
96 .align 1
97 .global BusFault_Handler
98 .syntax unified
99 .thumb
100 .thumb_func
102 BusFault_Handler:
103 .LFB133:
112:Core/Src/stm32f3xx_it.c **** }
113:Core/Src/stm32f3xx_it.c ****
114:Core/Src/stm32f3xx_it.c **** /**
115:Core/Src/stm32f3xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault.
116:Core/Src/stm32f3xx_it.c **** */
117:Core/Src/stm32f3xx_it.c **** void BusFault_Handler(void)
118:Core/Src/stm32f3xx_it.c **** {
104 .loc 1 118 1 view -0
105 .cfi_startproc
106 @ Volatile: function does not return.
107 @ args = 0, pretend = 0, frame = 0
108 @ frame_needed = 0, uses_anonymous_args = 0
109 @ link register save eliminated.
110 .L9:
119:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */
120:Core/Src/stm32f3xx_it.c ****
121:Core/Src/stm32f3xx_it.c **** /* USER CODE END BusFault_IRQn 0 */
122:Core/Src/stm32f3xx_it.c **** while (1)
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 5
111 .loc 1 122 3 discriminator 1 view .LVU14
123:Core/Src/stm32f3xx_it.c **** {
124:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */
125:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */
126:Core/Src/stm32f3xx_it.c **** }
112 .loc 1 126 3 discriminator 1 view .LVU15
122:Core/Src/stm32f3xx_it.c **** {
113 .loc 1 122 9 discriminator 1 view .LVU16
114 0000 FEE7 b .L9
115 .cfi_endproc
116 .LFE133:
118 .section .text.UsageFault_Handler,"ax",%progbits
119 .align 1
120 .global UsageFault_Handler
121 .syntax unified
122 .thumb
123 .thumb_func
125 UsageFault_Handler:
126 .LFB134:
127:Core/Src/stm32f3xx_it.c **** }
128:Core/Src/stm32f3xx_it.c ****
129:Core/Src/stm32f3xx_it.c **** /**
130:Core/Src/stm32f3xx_it.c **** * @brief This function handles Undefined instruction or illegal state.
131:Core/Src/stm32f3xx_it.c **** */
132:Core/Src/stm32f3xx_it.c **** void UsageFault_Handler(void)
133:Core/Src/stm32f3xx_it.c **** {
127 .loc 1 133 1 view -0
128 .cfi_startproc
129 @ Volatile: function does not return.
130 @ args = 0, pretend = 0, frame = 0
131 @ frame_needed = 0, uses_anonymous_args = 0
132 @ link register save eliminated.
133 .L11:
134:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */
135:Core/Src/stm32f3xx_it.c ****
136:Core/Src/stm32f3xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */
137:Core/Src/stm32f3xx_it.c **** while (1)
134 .loc 1 137 3 discriminator 1 view .LVU18
138:Core/Src/stm32f3xx_it.c **** {
139:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
140:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */
141:Core/Src/stm32f3xx_it.c **** }
135 .loc 1 141 3 discriminator 1 view .LVU19
137:Core/Src/stm32f3xx_it.c **** {
136 .loc 1 137 9 discriminator 1 view .LVU20
137 0000 FEE7 b .L11
138 .cfi_endproc
139 .LFE134:
141 .section .text.SVC_Handler,"ax",%progbits
142 .align 1
143 .global SVC_Handler
144 .syntax unified
145 .thumb
146 .thumb_func
148 SVC_Handler:
149 .LFB135:
142:Core/Src/stm32f3xx_it.c **** }
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 6
143:Core/Src/stm32f3xx_it.c ****
144:Core/Src/stm32f3xx_it.c **** /**
145:Core/Src/stm32f3xx_it.c **** * @brief This function handles System service call via SWI instruction.
146:Core/Src/stm32f3xx_it.c **** */
147:Core/Src/stm32f3xx_it.c **** void SVC_Handler(void)
148:Core/Src/stm32f3xx_it.c **** {
150 .loc 1 148 1 view -0
151 .cfi_startproc
152 @ args = 0, pretend = 0, frame = 0
153 @ frame_needed = 0, uses_anonymous_args = 0
154 @ link register save eliminated.
149:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */
150:Core/Src/stm32f3xx_it.c ****
151:Core/Src/stm32f3xx_it.c **** /* USER CODE END SVCall_IRQn 0 */
152:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */
153:Core/Src/stm32f3xx_it.c ****
154:Core/Src/stm32f3xx_it.c **** /* USER CODE END SVCall_IRQn 1 */
155:Core/Src/stm32f3xx_it.c **** }
155 .loc 1 155 1 view .LVU22
156 0000 7047 bx lr
157 .cfi_endproc
158 .LFE135:
160 .section .text.DebugMon_Handler,"ax",%progbits
161 .align 1
162 .global DebugMon_Handler
163 .syntax unified
164 .thumb
165 .thumb_func
167 DebugMon_Handler:
168 .LFB136:
156:Core/Src/stm32f3xx_it.c ****
157:Core/Src/stm32f3xx_it.c **** /**
158:Core/Src/stm32f3xx_it.c **** * @brief This function handles Debug monitor.
159:Core/Src/stm32f3xx_it.c **** */
160:Core/Src/stm32f3xx_it.c **** void DebugMon_Handler(void)
161:Core/Src/stm32f3xx_it.c **** {
169 .loc 1 161 1 view -0
170 .cfi_startproc
171 @ args = 0, pretend = 0, frame = 0
172 @ frame_needed = 0, uses_anonymous_args = 0
173 @ link register save eliminated.
162:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */
163:Core/Src/stm32f3xx_it.c ****
164:Core/Src/stm32f3xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */
165:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */
166:Core/Src/stm32f3xx_it.c ****
167:Core/Src/stm32f3xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */
168:Core/Src/stm32f3xx_it.c **** }
174 .loc 1 168 1 view .LVU24
175 0000 7047 bx lr
176 .cfi_endproc
177 .LFE136:
179 .section .text.PendSV_Handler,"ax",%progbits
180 .align 1
181 .global PendSV_Handler
182 .syntax unified
183 .thumb
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 7
184 .thumb_func
186 PendSV_Handler:
187 .LFB137:
169:Core/Src/stm32f3xx_it.c ****
170:Core/Src/stm32f3xx_it.c **** /**
171:Core/Src/stm32f3xx_it.c **** * @brief This function handles Pendable request for system service.
172:Core/Src/stm32f3xx_it.c **** */
173:Core/Src/stm32f3xx_it.c **** void PendSV_Handler(void)
174:Core/Src/stm32f3xx_it.c **** {
188 .loc 1 174 1 view -0
189 .cfi_startproc
190 @ args = 0, pretend = 0, frame = 0
191 @ frame_needed = 0, uses_anonymous_args = 0
192 @ link register save eliminated.
175:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */
176:Core/Src/stm32f3xx_it.c ****
177:Core/Src/stm32f3xx_it.c **** /* USER CODE END PendSV_IRQn 0 */
178:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */
179:Core/Src/stm32f3xx_it.c ****
180:Core/Src/stm32f3xx_it.c **** /* USER CODE END PendSV_IRQn 1 */
181:Core/Src/stm32f3xx_it.c **** }
193 .loc 1 181 1 view .LVU26
194 0000 7047 bx lr
195 .cfi_endproc
196 .LFE137:
198 .section .text.SysTick_Handler,"ax",%progbits
199 .align 1
200 .global SysTick_Handler
201 .syntax unified
202 .thumb
203 .thumb_func
205 SysTick_Handler:
206 .LFB138:
182:Core/Src/stm32f3xx_it.c ****
183:Core/Src/stm32f3xx_it.c **** /**
184:Core/Src/stm32f3xx_it.c **** * @brief This function handles System tick timer.
185:Core/Src/stm32f3xx_it.c **** */
186:Core/Src/stm32f3xx_it.c **** void SysTick_Handler(void)
187:Core/Src/stm32f3xx_it.c **** {
207 .loc 1 187 1 view -0
208 .cfi_startproc
209 @ args = 0, pretend = 0, frame = 0
210 @ frame_needed = 0, uses_anonymous_args = 0
211 0000 08B5 push {r3, lr}
212 .cfi_def_cfa_offset 8
213 .cfi_offset 3, -8
214 .cfi_offset 14, -4
188:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */
189:Core/Src/stm32f3xx_it.c ****
190:Core/Src/stm32f3xx_it.c **** /* USER CODE END SysTick_IRQn 0 */
191:Core/Src/stm32f3xx_it.c **** HAL_IncTick();
215 .loc 1 191 3 view .LVU28
216 0002 FFF7FEFF bl HAL_IncTick
217 .LVL1:
192:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */
193:Core/Src/stm32f3xx_it.c ****
194:Core/Src/stm32f3xx_it.c **** /* USER CODE END SysTick_IRQn 1 */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 8
195:Core/Src/stm32f3xx_it.c **** }
218 .loc 1 195 1 is_stmt 0 view .LVU29
219 0006 08BD pop {r3, pc}
220 .cfi_endproc
221 .LFE138:
223 .section .text.DMA1_Channel1_IRQHandler,"ax",%progbits
224 .align 1
225 .global DMA1_Channel1_IRQHandler
226 .syntax unified
227 .thumb
228 .thumb_func
230 DMA1_Channel1_IRQHandler:
231 .LFB139:
196:Core/Src/stm32f3xx_it.c ****
197:Core/Src/stm32f3xx_it.c **** /******************************************************************************/
198:Core/Src/stm32f3xx_it.c **** /* STM32F3xx Peripheral Interrupt Handlers */
199:Core/Src/stm32f3xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */
200:Core/Src/stm32f3xx_it.c **** /* For the available peripheral interrupt handler names, */
201:Core/Src/stm32f3xx_it.c **** /* please refer to the startup file (startup_stm32f3xx.s). */
202:Core/Src/stm32f3xx_it.c **** /******************************************************************************/
203:Core/Src/stm32f3xx_it.c ****
204:Core/Src/stm32f3xx_it.c **** /**
205:Core/Src/stm32f3xx_it.c **** * @brief This function handles DMA1 channel1 global interrupt.
206:Core/Src/stm32f3xx_it.c **** */
207:Core/Src/stm32f3xx_it.c **** void DMA1_Channel1_IRQHandler(void)
208:Core/Src/stm32f3xx_it.c **** {
232 .loc 1 208 1 is_stmt 1 view -0
233 .cfi_startproc
234 @ args = 0, pretend = 0, frame = 0
235 @ frame_needed = 0, uses_anonymous_args = 0
236 0000 08B5 push {r3, lr}
237 .cfi_def_cfa_offset 8
238 .cfi_offset 3, -8
239 .cfi_offset 14, -4
209:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
210:Core/Src/stm32f3xx_it.c ****
211:Core/Src/stm32f3xx_it.c **** /* USER CODE END DMA1_Channel1_IRQn 0 */
212:Core/Src/stm32f3xx_it.c **** HAL_DMA_IRQHandler(&hdma_adc1);
240 .loc 1 212 3 view .LVU31
241 0002 0248 ldr r0, .L19
242 0004 FFF7FEFF bl HAL_DMA_IRQHandler
243 .LVL2:
213:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
214:Core/Src/stm32f3xx_it.c ****
215:Core/Src/stm32f3xx_it.c **** /* USER CODE END DMA1_Channel1_IRQn 1 */
216:Core/Src/stm32f3xx_it.c **** }
244 .loc 1 216 1 is_stmt 0 view .LVU32
245 0008 08BD pop {r3, pc}
246 .L20:
247 000a 00BF .align 2
248 .L19:
249 000c 00000000 .word hdma_adc1
250 .cfi_endproc
251 .LFE139:
253 .section .text.USB_LP_CAN_RX0_IRQHandler,"ax",%progbits
254 .align 1
255 .global USB_LP_CAN_RX0_IRQHandler
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 9
256 .syntax unified
257 .thumb
258 .thumb_func
260 USB_LP_CAN_RX0_IRQHandler:
261 .LFB140:
217:Core/Src/stm32f3xx_it.c ****
218:Core/Src/stm32f3xx_it.c **** /**
219:Core/Src/stm32f3xx_it.c **** * @brief This function handles USB low priority or CAN_RX0 interrupts.
220:Core/Src/stm32f3xx_it.c **** */
221:Core/Src/stm32f3xx_it.c **** void USB_LP_CAN_RX0_IRQHandler(void)
222:Core/Src/stm32f3xx_it.c **** {
262 .loc 1 222 1 is_stmt 1 view -0
263 .cfi_startproc
264 @ args = 0, pretend = 0, frame = 0
265 @ frame_needed = 0, uses_anonymous_args = 0
266 0000 08B5 push {r3, lr}
267 .cfi_def_cfa_offset 8
268 .cfi_offset 3, -8
269 .cfi_offset 14, -4
223:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */
224:Core/Src/stm32f3xx_it.c ****
225:Core/Src/stm32f3xx_it.c **** /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */
226:Core/Src/stm32f3xx_it.c **** HAL_CAN_IRQHandler(&hcan);
270 .loc 1 226 3 view .LVU34
271 0002 0248 ldr r0, .L23
272 0004 FFF7FEFF bl HAL_CAN_IRQHandler
273 .LVL3:
227:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */
228:Core/Src/stm32f3xx_it.c ****
229:Core/Src/stm32f3xx_it.c **** /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */
230:Core/Src/stm32f3xx_it.c **** }
274 .loc 1 230 1 is_stmt 0 view .LVU35
275 0008 08BD pop {r3, pc}
276 .L24:
277 000a 00BF .align 2
278 .L23:
279 000c 00000000 .word hcan
280 .cfi_endproc
281 .LFE140:
283 .section .text.CAN_RX1_IRQHandler,"ax",%progbits
284 .align 1
285 .global CAN_RX1_IRQHandler
286 .syntax unified
287 .thumb
288 .thumb_func
290 CAN_RX1_IRQHandler:
291 .LFB141:
231:Core/Src/stm32f3xx_it.c ****
232:Core/Src/stm32f3xx_it.c **** /**
233:Core/Src/stm32f3xx_it.c **** * @brief This function handles CAN RX1 interrupt.
234:Core/Src/stm32f3xx_it.c **** */
235:Core/Src/stm32f3xx_it.c **** void CAN_RX1_IRQHandler(void)
236:Core/Src/stm32f3xx_it.c **** {
292 .loc 1 236 1 is_stmt 1 view -0
293 .cfi_startproc
294 @ args = 0, pretend = 0, frame = 0
295 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 10
296 0000 08B5 push {r3, lr}
297 .cfi_def_cfa_offset 8
298 .cfi_offset 3, -8
299 .cfi_offset 14, -4
237:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN CAN_RX1_IRQn 0 */
238:Core/Src/stm32f3xx_it.c ****
239:Core/Src/stm32f3xx_it.c **** /* USER CODE END CAN_RX1_IRQn 0 */
240:Core/Src/stm32f3xx_it.c **** HAL_CAN_IRQHandler(&hcan);
300 .loc 1 240 3 view .LVU37
301 0002 0248 ldr r0, .L27
302 0004 FFF7FEFF bl HAL_CAN_IRQHandler
303 .LVL4:
241:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN CAN_RX1_IRQn 1 */
242:Core/Src/stm32f3xx_it.c ****
243:Core/Src/stm32f3xx_it.c **** /* USER CODE END CAN_RX1_IRQn 1 */
244:Core/Src/stm32f3xx_it.c **** }
304 .loc 1 244 1 is_stmt 0 view .LVU38
305 0008 08BD pop {r3, pc}
306 .L28:
307 000a 00BF .align 2
308 .L27:
309 000c 00000000 .word hcan
310 .cfi_endproc
311 .LFE141:
313 .section .text.CAN_SCE_IRQHandler,"ax",%progbits
314 .align 1
315 .global CAN_SCE_IRQHandler
316 .syntax unified
317 .thumb
318 .thumb_func
320 CAN_SCE_IRQHandler:
321 .LFB142:
245:Core/Src/stm32f3xx_it.c ****
246:Core/Src/stm32f3xx_it.c **** /**
247:Core/Src/stm32f3xx_it.c **** * @brief This function handles CAN SCE interrupt.
248:Core/Src/stm32f3xx_it.c **** */
249:Core/Src/stm32f3xx_it.c **** void CAN_SCE_IRQHandler(void)
250:Core/Src/stm32f3xx_it.c **** {
322 .loc 1 250 1 is_stmt 1 view -0
323 .cfi_startproc
324 @ args = 0, pretend = 0, frame = 0
325 @ frame_needed = 0, uses_anonymous_args = 0
326 0000 08B5 push {r3, lr}
327 .cfi_def_cfa_offset 8
328 .cfi_offset 3, -8
329 .cfi_offset 14, -4
251:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN CAN_SCE_IRQn 0 */
252:Core/Src/stm32f3xx_it.c ****
253:Core/Src/stm32f3xx_it.c **** /* USER CODE END CAN_SCE_IRQn 0 */
254:Core/Src/stm32f3xx_it.c **** HAL_CAN_IRQHandler(&hcan);
330 .loc 1 254 3 view .LVU40
331 0002 0248 ldr r0, .L31
332 0004 FFF7FEFF bl HAL_CAN_IRQHandler
333 .LVL5:
255:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN CAN_SCE_IRQn 1 */
256:Core/Src/stm32f3xx_it.c ****
257:Core/Src/stm32f3xx_it.c **** /* USER CODE END CAN_SCE_IRQn 1 */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 11
258:Core/Src/stm32f3xx_it.c **** }
334 .loc 1 258 1 is_stmt 0 view .LVU41
335 0008 08BD pop {r3, pc}
336 .L32:
337 000a 00BF .align 2
338 .L31:
339 000c 00000000 .word hcan
340 .cfi_endproc
341 .LFE142:
343 .section .text.DMA2_Channel1_IRQHandler,"ax",%progbits
344 .align 1
345 .global DMA2_Channel1_IRQHandler
346 .syntax unified
347 .thumb
348 .thumb_func
350 DMA2_Channel1_IRQHandler:
351 .LFB143:
259:Core/Src/stm32f3xx_it.c ****
260:Core/Src/stm32f3xx_it.c **** /**
261:Core/Src/stm32f3xx_it.c **** * @brief This function handles DMA2 channel1 global interrupt.
262:Core/Src/stm32f3xx_it.c **** */
263:Core/Src/stm32f3xx_it.c **** void DMA2_Channel1_IRQHandler(void)
264:Core/Src/stm32f3xx_it.c **** {
352 .loc 1 264 1 is_stmt 1 view -0
353 .cfi_startproc
354 @ args = 0, pretend = 0, frame = 0
355 @ frame_needed = 0, uses_anonymous_args = 0
356 0000 08B5 push {r3, lr}
357 .cfi_def_cfa_offset 8
358 .cfi_offset 3, -8
359 .cfi_offset 14, -4
265:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DMA2_Channel1_IRQn 0 */
266:Core/Src/stm32f3xx_it.c ****
267:Core/Src/stm32f3xx_it.c **** /* USER CODE END DMA2_Channel1_IRQn 0 */
268:Core/Src/stm32f3xx_it.c **** HAL_DMA_IRQHandler(&hdma_adc2);
360 .loc 1 268 3 view .LVU43
361 0002 0248 ldr r0, .L35
362 0004 FFF7FEFF bl HAL_DMA_IRQHandler
363 .LVL6:
269:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DMA2_Channel1_IRQn 1 */
270:Core/Src/stm32f3xx_it.c ****
271:Core/Src/stm32f3xx_it.c **** /* USER CODE END DMA2_Channel1_IRQn 1 */
272:Core/Src/stm32f3xx_it.c **** }
364 .loc 1 272 1 is_stmt 0 view .LVU44
365 0008 08BD pop {r3, pc}
366 .L36:
367 000a 00BF .align 2
368 .L35:
369 000c 00000000 .word hdma_adc2
370 .cfi_endproc
371 .LFE143:
373 .text
374 .Letext0:
375 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
376 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
377 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
378 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 12
379 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
380 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
381 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h"
382 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h"
383 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s page 13
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_it.c
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:21 .text.NMI_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:27 .text.NMI_Handler:00000000 NMI_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:50 .text.HardFault_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:56 .text.HardFault_Handler:00000000 HardFault_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:73 .text.MemManage_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:79 .text.MemManage_Handler:00000000 MemManage_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:96 .text.BusFault_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:102 .text.BusFault_Handler:00000000 BusFault_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:119 .text.UsageFault_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:125 .text.UsageFault_Handler:00000000 UsageFault_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:142 .text.SVC_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:148 .text.SVC_Handler:00000000 SVC_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:161 .text.DebugMon_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:167 .text.DebugMon_Handler:00000000 DebugMon_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:180 .text.PendSV_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:186 .text.PendSV_Handler:00000000 PendSV_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:199 .text.SysTick_Handler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:205 .text.SysTick_Handler:00000000 SysTick_Handler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:224 .text.DMA1_Channel1_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:230 .text.DMA1_Channel1_IRQHandler:00000000 DMA1_Channel1_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:249 .text.DMA1_Channel1_IRQHandler:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:254 .text.USB_LP_CAN_RX0_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:260 .text.USB_LP_CAN_RX0_IRQHandler:00000000 USB_LP_CAN_RX0_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:279 .text.USB_LP_CAN_RX0_IRQHandler:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:284 .text.CAN_RX1_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:290 .text.CAN_RX1_IRQHandler:00000000 CAN_RX1_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:309 .text.CAN_RX1_IRQHandler:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:314 .text.CAN_SCE_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:320 .text.CAN_SCE_IRQHandler:00000000 CAN_SCE_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:339 .text.CAN_SCE_IRQHandler:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:344 .text.DMA2_Channel1_IRQHandler:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:350 .text.DMA2_Channel1_IRQHandler:00000000 DMA2_Channel1_IRQHandler
C:\Users\nived\AppData\Local\Temp\ccPDYdRP.s:369 .text.DMA2_Channel1_IRQHandler:0000000c $d
UNDEFINED SYMBOLS
HAL_RCC_NMI_IRQHandler
HAL_IncTick
HAL_DMA_IRQHandler
hdma_adc1
HAL_CAN_IRQHandler
hcan
hdma_adc2

574
build/system_stm32f3xx.lst
View File

@ -1,574 +0,0 @@
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "system_stm32f3xx.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Core/Src/system_stm32f3xx.c"
20 .section .text.SystemInit,"ax",%progbits
21 .align 1
22 .global SystemInit
23 .syntax unified
24 .thumb
25 .thumb_func
27 SystemInit:
28 .LFB130:
1:Core/Src/system_stm32f3xx.c **** /**
2:Core/Src/system_stm32f3xx.c **** ******************************************************************************
3:Core/Src/system_stm32f3xx.c **** * @file system_stm32f3xx.c
4:Core/Src/system_stm32f3xx.c **** * @author MCD Application Team
5:Core/Src/system_stm32f3xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
6:Core/Src/system_stm32f3xx.c **** *
7:Core/Src/system_stm32f3xx.c **** * 1. This file provides two functions and one global variable to be called from
8:Core/Src/system_stm32f3xx.c **** * user application:
9:Core/Src/system_stm32f3xx.c **** * - SystemInit(): This function is called at startup just after reset and
10:Core/Src/system_stm32f3xx.c **** * before branch to main program. This call is made inside
11:Core/Src/system_stm32f3xx.c **** * the "startup_stm32f3xx.s" file.
12:Core/Src/system_stm32f3xx.c **** *
13:Core/Src/system_stm32f3xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14:Core/Src/system_stm32f3xx.c **** * by the user application to setup the SysTick
15:Core/Src/system_stm32f3xx.c **** * timer or configure other parameters.
16:Core/Src/system_stm32f3xx.c **** *
17:Core/Src/system_stm32f3xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18:Core/Src/system_stm32f3xx.c **** * be called whenever the core clock is changed
19:Core/Src/system_stm32f3xx.c **** * during program execution.
20:Core/Src/system_stm32f3xx.c **** *
21:Core/Src/system_stm32f3xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source.
22:Core/Src/system_stm32f3xx.c **** * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
23:Core/Src/system_stm32f3xx.c **** * configure the system clock before to branch to main program.
24:Core/Src/system_stm32f3xx.c **** *
25:Core/Src/system_stm32f3xx.c **** * 3. This file configures the system clock as follows:
26:Core/Src/system_stm32f3xx.c **** *=============================================================================
27:Core/Src/system_stm32f3xx.c **** * Supported STM32F3xx device
28:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
29:Core/Src/system_stm32f3xx.c **** * System Clock source | HSI
30:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 2
31:Core/Src/system_stm32f3xx.c **** * SYSCLK(Hz) | 8000000
32:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
33:Core/Src/system_stm32f3xx.c **** * HCLK(Hz) | 8000000
34:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
35:Core/Src/system_stm32f3xx.c **** * AHB Prescaler | 1
36:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
37:Core/Src/system_stm32f3xx.c **** * APB2 Prescaler | 1
38:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
39:Core/Src/system_stm32f3xx.c **** * APB1 Prescaler | 1
40:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
41:Core/Src/system_stm32f3xx.c **** * USB Clock | DISABLE
42:Core/Src/system_stm32f3xx.c **** *-----------------------------------------------------------------------------
43:Core/Src/system_stm32f3xx.c **** *=============================================================================
44:Core/Src/system_stm32f3xx.c **** ******************************************************************************
45:Core/Src/system_stm32f3xx.c **** * @attention
46:Core/Src/system_stm32f3xx.c **** *
47:Core/Src/system_stm32f3xx.c **** * Copyright (c) 2016 STMicroelectronics.
48:Core/Src/system_stm32f3xx.c **** * All rights reserved.
49:Core/Src/system_stm32f3xx.c **** *
50:Core/Src/system_stm32f3xx.c **** * This software is licensed under terms that can be found in the LICENSE file
51:Core/Src/system_stm32f3xx.c **** * in the root directory of this software component.
52:Core/Src/system_stm32f3xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
53:Core/Src/system_stm32f3xx.c **** *
54:Core/Src/system_stm32f3xx.c **** ******************************************************************************
55:Core/Src/system_stm32f3xx.c **** */
56:Core/Src/system_stm32f3xx.c ****
57:Core/Src/system_stm32f3xx.c **** /** @addtogroup CMSIS
58:Core/Src/system_stm32f3xx.c **** * @{
59:Core/Src/system_stm32f3xx.c **** */
60:Core/Src/system_stm32f3xx.c ****
61:Core/Src/system_stm32f3xx.c **** /** @addtogroup stm32f3xx_system
62:Core/Src/system_stm32f3xx.c **** * @{
63:Core/Src/system_stm32f3xx.c **** */
64:Core/Src/system_stm32f3xx.c ****
65:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Includes
66:Core/Src/system_stm32f3xx.c **** * @{
67:Core/Src/system_stm32f3xx.c **** */
68:Core/Src/system_stm32f3xx.c ****
69:Core/Src/system_stm32f3xx.c **** #include "stm32f3xx.h"
70:Core/Src/system_stm32f3xx.c ****
71:Core/Src/system_stm32f3xx.c **** /**
72:Core/Src/system_stm32f3xx.c **** * @}
73:Core/Src/system_stm32f3xx.c **** */
74:Core/Src/system_stm32f3xx.c ****
75:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
76:Core/Src/system_stm32f3xx.c **** * @{
77:Core/Src/system_stm32f3xx.c **** */
78:Core/Src/system_stm32f3xx.c ****
79:Core/Src/system_stm32f3xx.c **** /**
80:Core/Src/system_stm32f3xx.c **** * @}
81:Core/Src/system_stm32f3xx.c **** */
82:Core/Src/system_stm32f3xx.c ****
83:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Defines
84:Core/Src/system_stm32f3xx.c **** * @{
85:Core/Src/system_stm32f3xx.c **** */
86:Core/Src/system_stm32f3xx.c **** #if !defined (HSE_VALUE)
87:Core/Src/system_stm32f3xx.c **** #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 3
88:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user
89:Core/Src/system_stm32f3xx.c **** #endif /* HSE_VALUE */
90:Core/Src/system_stm32f3xx.c ****
91:Core/Src/system_stm32f3xx.c **** #if !defined (HSI_VALUE)
92:Core/Src/system_stm32f3xx.c **** #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
93:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user
94:Core/Src/system_stm32f3xx.c **** #endif /* HSI_VALUE */
95:Core/Src/system_stm32f3xx.c ****
96:Core/Src/system_stm32f3xx.c **** /* Note: Following vector table addresses must be defined in line with linker
97:Core/Src/system_stm32f3xx.c **** configuration. */
98:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
99:Core/Src/system_stm32f3xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
100:Core/Src/system_stm32f3xx.c **** remap of boot address selected */
101:Core/Src/system_stm32f3xx.c **** /* #define USER_VECT_TAB_ADDRESS */
102:Core/Src/system_stm32f3xx.c ****
103:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
104:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
105:Core/Src/system_stm32f3xx.c **** in Sram else user remap will be done in Flash. */
106:Core/Src/system_stm32f3xx.c **** /* #define VECT_TAB_SRAM */
107:Core/Src/system_stm32f3xx.c **** #if defined(VECT_TAB_SRAM)
108:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
109:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
110:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
111:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
112:Core/Src/system_stm32f3xx.c **** #else
113:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
114:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
115:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
116:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */
117:Core/Src/system_stm32f3xx.c **** #endif /* VECT_TAB_SRAM */
118:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
119:Core/Src/system_stm32f3xx.c ****
120:Core/Src/system_stm32f3xx.c **** /******************************************************************************/
121:Core/Src/system_stm32f3xx.c **** /**
122:Core/Src/system_stm32f3xx.c **** * @}
123:Core/Src/system_stm32f3xx.c **** */
124:Core/Src/system_stm32f3xx.c ****
125:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Macros
126:Core/Src/system_stm32f3xx.c **** * @{
127:Core/Src/system_stm32f3xx.c **** */
128:Core/Src/system_stm32f3xx.c ****
129:Core/Src/system_stm32f3xx.c **** /**
130:Core/Src/system_stm32f3xx.c **** * @}
131:Core/Src/system_stm32f3xx.c **** */
132:Core/Src/system_stm32f3xx.c ****
133:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Variables
134:Core/Src/system_stm32f3xx.c **** * @{
135:Core/Src/system_stm32f3xx.c **** */
136:Core/Src/system_stm32f3xx.c **** /* This variable is updated in three ways:
137:Core/Src/system_stm32f3xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
138:Core/Src/system_stm32f3xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
139:Core/Src/system_stm32f3xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
140:Core/Src/system_stm32f3xx.c **** Note: If you use this function to configure the system clock there is no need to
141:Core/Src/system_stm32f3xx.c **** call the 2 first functions listed above, since SystemCoreClock variable is
142:Core/Src/system_stm32f3xx.c **** updated automatically.
143:Core/Src/system_stm32f3xx.c **** */
144:Core/Src/system_stm32f3xx.c **** uint32_t SystemCoreClock = 8000000;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 4
145:Core/Src/system_stm32f3xx.c ****
146:Core/Src/system_stm32f3xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
147:Core/Src/system_stm32f3xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
148:Core/Src/system_stm32f3xx.c ****
149:Core/Src/system_stm32f3xx.c **** /**
150:Core/Src/system_stm32f3xx.c **** * @}
151:Core/Src/system_stm32f3xx.c **** */
152:Core/Src/system_stm32f3xx.c ****
153:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
154:Core/Src/system_stm32f3xx.c **** * @{
155:Core/Src/system_stm32f3xx.c **** */
156:Core/Src/system_stm32f3xx.c ****
157:Core/Src/system_stm32f3xx.c **** /**
158:Core/Src/system_stm32f3xx.c **** * @}
159:Core/Src/system_stm32f3xx.c **** */
160:Core/Src/system_stm32f3xx.c ****
161:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Functions
162:Core/Src/system_stm32f3xx.c **** * @{
163:Core/Src/system_stm32f3xx.c **** */
164:Core/Src/system_stm32f3xx.c ****
165:Core/Src/system_stm32f3xx.c **** /**
166:Core/Src/system_stm32f3xx.c **** * @brief Setup the microcontroller system
167:Core/Src/system_stm32f3xx.c **** * @param None
168:Core/Src/system_stm32f3xx.c **** * @retval None
169:Core/Src/system_stm32f3xx.c **** */
170:Core/Src/system_stm32f3xx.c **** void SystemInit(void)
171:Core/Src/system_stm32f3xx.c **** {
29 .loc 1 171 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
172:Core/Src/system_stm32f3xx.c **** /* FPU settings --------------------------------------------------------------*/
173:Core/Src/system_stm32f3xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
174:Core/Src/system_stm32f3xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
34 .loc 1 174 3 view .LVU1
35 .loc 1 174 6 is_stmt 0 view .LVU2
36 0000 034A ldr r2, .L2
37 0002 D2F88830 ldr r3, [r2, #136]
38 .loc 1 174 14 view .LVU3
39 0006 43F47003 orr r3, r3, #15728640
40 000a C2F88830 str r3, [r2, #136]
175:Core/Src/system_stm32f3xx.c **** #endif
176:Core/Src/system_stm32f3xx.c ****
177:Core/Src/system_stm32f3xx.c **** /* Configure the Vector Table location -------------------------------------*/
178:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
179:Core/Src/system_stm32f3xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM
180:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
181:Core/Src/system_stm32f3xx.c **** }
41 .loc 1 181 1 view .LVU4
42 000e 7047 bx lr
43 .L3:
44 .align 2
45 .L2:
46 0010 00ED00E0 .word -536810240
47 .cfi_endproc
48 .LFE130:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 5
50 .section .text.SystemCoreClockUpdate,"ax",%progbits
51 .align 1
52 .global SystemCoreClockUpdate
53 .syntax unified
54 .thumb
55 .thumb_func
57 SystemCoreClockUpdate:
58 .LFB131:
182:Core/Src/system_stm32f3xx.c ****
183:Core/Src/system_stm32f3xx.c **** /**
184:Core/Src/system_stm32f3xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
185:Core/Src/system_stm32f3xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
186:Core/Src/system_stm32f3xx.c **** * be used by the user application to setup the SysTick timer or configure
187:Core/Src/system_stm32f3xx.c **** * other parameters.
188:Core/Src/system_stm32f3xx.c **** *
189:Core/Src/system_stm32f3xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
190:Core/Src/system_stm32f3xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
191:Core/Src/system_stm32f3xx.c **** * based on this variable will be incorrect.
192:Core/Src/system_stm32f3xx.c **** *
193:Core/Src/system_stm32f3xx.c **** * @note - The system frequency computed by this function is not the real
194:Core/Src/system_stm32f3xx.c **** * frequency in the chip. It is calculated based on the predefined
195:Core/Src/system_stm32f3xx.c **** * constant and the selected clock source:
196:Core/Src/system_stm32f3xx.c **** *
197:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
198:Core/Src/system_stm32f3xx.c **** *
199:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
200:Core/Src/system_stm32f3xx.c **** *
201:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
202:Core/Src/system_stm32f3xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
203:Core/Src/system_stm32f3xx.c **** *
204:Core/Src/system_stm32f3xx.c **** * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
205:Core/Src/system_stm32f3xx.c **** * 8 MHz) but the real value may vary depending on the variations
206:Core/Src/system_stm32f3xx.c **** * in voltage and temperature.
207:Core/Src/system_stm32f3xx.c **** *
208:Core/Src/system_stm32f3xx.c **** * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
209:Core/Src/system_stm32f3xx.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real
210:Core/Src/system_stm32f3xx.c **** * frequency of the crystal used. Otherwise, this function may
211:Core/Src/system_stm32f3xx.c **** * have wrong result.
212:Core/Src/system_stm32f3xx.c **** *
213:Core/Src/system_stm32f3xx.c **** * - The result of this function could be not correct when using fractional
214:Core/Src/system_stm32f3xx.c **** * value for HSE crystal.
215:Core/Src/system_stm32f3xx.c **** *
216:Core/Src/system_stm32f3xx.c **** * @param None
217:Core/Src/system_stm32f3xx.c **** * @retval None
218:Core/Src/system_stm32f3xx.c **** */
219:Core/Src/system_stm32f3xx.c **** void SystemCoreClockUpdate (void)
220:Core/Src/system_stm32f3xx.c **** {
59 .loc 1 220 1 is_stmt 1 view -0
60 .cfi_startproc
61 @ args = 0, pretend = 0, frame = 0
62 @ frame_needed = 0, uses_anonymous_args = 0
63 @ link register save eliminated.
221:Core/Src/system_stm32f3xx.c **** uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
64 .loc 1 221 3 view .LVU6
65 .LVL0:
222:Core/Src/system_stm32f3xx.c ****
223:Core/Src/system_stm32f3xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 6
224:Core/Src/system_stm32f3xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
66 .loc 1 224 3 view .LVU7
67 .loc 1 224 12 is_stmt 0 view .LVU8
68 0000 1D4B ldr r3, .L11
69 0002 5B68 ldr r3, [r3, #4]
70 .loc 1 224 7 view .LVU9
71 0004 03F00C03 and r3, r3, #12
72 .LVL1:
225:Core/Src/system_stm32f3xx.c ****
226:Core/Src/system_stm32f3xx.c **** switch (tmp)
73 .loc 1 226 3 is_stmt 1 view .LVU10
74 0008 042B cmp r3, #4
75 000a 14D0 beq .L5
76 000c 082B cmp r3, #8
77 000e 16D0 beq .L6
78 0010 1BB1 cbz r3, .L10
227:Core/Src/system_stm32f3xx.c **** {
228:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
229:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE;
230:Core/Src/system_stm32f3xx.c **** break;
231:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
232:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSE_VALUE;
233:Core/Src/system_stm32f3xx.c **** break;
234:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
235:Core/Src/system_stm32f3xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/
236:Core/Src/system_stm32f3xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
237:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
238:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2;
239:Core/Src/system_stm32f3xx.c ****
240:Core/Src/system_stm32f3xx.c **** #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
241:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
242:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
243:Core/Src/system_stm32f3xx.c **** {
244:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
245:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
246:Core/Src/system_stm32f3xx.c **** }
247:Core/Src/system_stm32f3xx.c **** else
248:Core/Src/system_stm32f3xx.c **** {
249:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock selected as PREDIV1 clock entry */
250:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
251:Core/Src/system_stm32f3xx.c **** }
252:Core/Src/system_stm32f3xx.c **** #else
253:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
254:Core/Src/system_stm32f3xx.c **** {
255:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
256:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
257:Core/Src/system_stm32f3xx.c **** }
258:Core/Src/system_stm32f3xx.c **** else
259:Core/Src/system_stm32f3xx.c **** {
260:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
262:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
263:Core/Src/system_stm32f3xx.c **** }
264:Core/Src/system_stm32f3xx.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
265:Core/Src/system_stm32f3xx.c **** break;
266:Core/Src/system_stm32f3xx.c **** default: /* HSI used as system clock */
267:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE;
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 7
79 .loc 1 267 7 view .LVU11
80 .loc 1 267 23 is_stmt 0 view .LVU12
81 0012 1A4B ldr r3, .L11+4
82 .LVL2:
83 .loc 1 267 23 view .LVU13
84 0014 1A4A ldr r2, .L11+8
85 0016 1A60 str r2, [r3]
268:Core/Src/system_stm32f3xx.c **** break;
86 .loc 1 268 7 is_stmt 1 view .LVU14
87 0018 02E0 b .L8
88 .LVL3:
89 .L10:
229:Core/Src/system_stm32f3xx.c **** break;
90 .loc 1 229 7 view .LVU15
229:Core/Src/system_stm32f3xx.c **** break;
91 .loc 1 229 23 is_stmt 0 view .LVU16
92 001a 184B ldr r3, .L11+4
93 .LVL4:
229:Core/Src/system_stm32f3xx.c **** break;
94 .loc 1 229 23 view .LVU17
95 001c 184A ldr r2, .L11+8
96 001e 1A60 str r2, [r3]
230:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
97 .loc 1 230 7 is_stmt 1 view .LVU18
98 .LVL5:
99 .L8:
269:Core/Src/system_stm32f3xx.c **** }
270:Core/Src/system_stm32f3xx.c **** /* Compute HCLK clock frequency ----------------*/
271:Core/Src/system_stm32f3xx.c **** /* Get HCLK prescaler */
272:Core/Src/system_stm32f3xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
100 .loc 1 272 3 view .LVU19
101 .loc 1 272 28 is_stmt 0 view .LVU20
102 0020 154B ldr r3, .L11
103 0022 5B68 ldr r3, [r3, #4]
104 .loc 1 272 52 view .LVU21
105 0024 C3F30313 ubfx r3, r3, #4, #4
106 .loc 1 272 22 view .LVU22
107 0028 164A ldr r2, .L11+12
108 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2
109 .LVL6:
273:Core/Src/system_stm32f3xx.c **** /* HCLK clock frequency */
274:Core/Src/system_stm32f3xx.c **** SystemCoreClock >>= tmp;
110 .loc 1 274 3 is_stmt 1 view .LVU23
111 .loc 1 274 19 is_stmt 0 view .LVU24
112 002c 134A ldr r2, .L11+4
113 002e 1368 ldr r3, [r2]
114 0030 CB40 lsrs r3, r3, r1
115 0032 1360 str r3, [r2]
275:Core/Src/system_stm32f3xx.c **** }
116 .loc 1 275 1 view .LVU25
117 0034 7047 bx lr
118 .LVL7:
119 .L5:
232:Core/Src/system_stm32f3xx.c **** break;
120 .loc 1 232 7 is_stmt 1 view .LVU26
232:Core/Src/system_stm32f3xx.c **** break;
121 .loc 1 232 23 is_stmt 0 view .LVU27
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 8
122 0036 114B ldr r3, .L11+4
123 .LVL8:
232:Core/Src/system_stm32f3xx.c **** break;
124 .loc 1 232 23 view .LVU28
125 0038 134A ldr r2, .L11+16
126 003a 1A60 str r2, [r3]
233:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
127 .loc 1 233 7 is_stmt 1 view .LVU29
128 003c F0E7 b .L8
129 .LVL9:
130 .L6:
236:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
131 .loc 1 236 7 view .LVU30
236:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
132 .loc 1 236 20 is_stmt 0 view .LVU31
133 003e 0E4A ldr r2, .L11
134 0040 5368 ldr r3, [r2, #4]
135 .LVL10:
237:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2;
136 .loc 1 237 7 is_stmt 1 view .LVU32
237:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2;
137 .loc 1 237 22 is_stmt 0 view .LVU33
138 0042 5268 ldr r2, [r2, #4]
139 .LVL11:
238:Core/Src/system_stm32f3xx.c ****
140 .loc 1 238 7 is_stmt 1 view .LVU34
238:Core/Src/system_stm32f3xx.c ****
141 .loc 1 238 27 is_stmt 0 view .LVU35
142 0044 C3F38343 ubfx r3, r3, #18, #4
143 .LVL12:
238:Core/Src/system_stm32f3xx.c ****
144 .loc 1 238 15 view .LVU36
145 0048 0233 adds r3, r3, #2
146 .LVL13:
253:Core/Src/system_stm32f3xx.c **** {
147 .loc 1 253 7 is_stmt 1 view .LVU37
253:Core/Src/system_stm32f3xx.c **** {
148 .loc 1 253 10 is_stmt 0 view .LVU38
149 004a 12F4803F tst r2, #65536
150 004e 05D1 bne .L9
256:Core/Src/system_stm32f3xx.c **** }
151 .loc 1 256 9 is_stmt 1 view .LVU39
256:Core/Src/system_stm32f3xx.c **** }
152 .loc 1 256 44 is_stmt 0 view .LVU40
153 0050 0E4A ldr r2, .L11+20
154 .LVL14:
256:Core/Src/system_stm32f3xx.c **** }
155 .loc 1 256 44 view .LVU41
156 0052 02FB03F3 mul r3, r2, r3
157 .LVL15:
256:Core/Src/system_stm32f3xx.c **** }
158 .loc 1 256 25 view .LVU42
159 0056 094A ldr r2, .L11+4
160 0058 1360 str r3, [r2]
161 005a E1E7 b .L8
162 .LVL16:
163 .L9:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 9
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
164 .loc 1 260 9 is_stmt 1 view .LVU43
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
165 .loc 1 260 28 is_stmt 0 view .LVU44
166 005c 064A ldr r2, .L11
167 .LVL17:
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
168 .loc 1 260 28 view .LVU45
169 005e D16A ldr r1, [r2, #44]
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
170 .loc 1 260 36 view .LVU46
171 0060 01F00F01 and r1, r1, #15
260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
172 .loc 1 260 22 view .LVU47
173 0064 0131 adds r1, r1, #1
174 .LVL18:
262:Core/Src/system_stm32f3xx.c **** }
175 .loc 1 262 9 is_stmt 1 view .LVU48
262:Core/Src/system_stm32f3xx.c **** }
176 .loc 1 262 38 is_stmt 0 view .LVU49
177 0066 084A ldr r2, .L11+16
178 0068 B2FBF1F2 udiv r2, r2, r1
262:Core/Src/system_stm32f3xx.c **** }
179 .loc 1 262 54 view .LVU50
180 006c 02FB03F3 mul r3, r2, r3
181 .LVL19:
262:Core/Src/system_stm32f3xx.c **** }
182 .loc 1 262 25 view .LVU51
183 0070 024A ldr r2, .L11+4
184 0072 1360 str r3, [r2]
185 0074 D4E7 b .L8
186 .L12:
187 0076 00BF .align 2
188 .L11:
189 0078 00100240 .word 1073876992
190 007c 00000000 .word SystemCoreClock
191 0080 00127A00 .word 8000000
192 0084 00000000 .word AHBPrescTable
193 0088 0024F400 .word 16000000
194 008c 00093D00 .word 4000000
195 .cfi_endproc
196 .LFE131:
198 .global APBPrescTable
199 .section .rodata.APBPrescTable,"a"
200 .align 2
203 APBPrescTable:
204 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
204 01020304
205 .global AHBPrescTable
206 .section .rodata.AHBPrescTable,"a"
207 .align 2
210 AHBPrescTable:
211 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
211 00000000
211 01020304
211 06
212 000d 070809 .ascii "\007\010\011"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 10
213 .global SystemCoreClock
214 .section .data.SystemCoreClock,"aw"
215 .align 2
218 SystemCoreClock:
219 0000 00127A00 .word 8000000
220 .text
221 .Letext0:
222 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
223 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
224 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
225 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h"
226 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s page 11
DEFINED SYMBOLS
*ABS*:00000000 system_stm32f3xx.c
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:21 .text.SystemInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:27 .text.SystemInit:00000000 SystemInit
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:46 .text.SystemInit:00000010 $d
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:51 .text.SystemCoreClockUpdate:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:57 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:189 .text.SystemCoreClockUpdate:00000078 $d
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:218 .data.SystemCoreClock:00000000 SystemCoreClock
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:210 .rodata.AHBPrescTable:00000000 AHBPrescTable
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:203 .rodata.APBPrescTable:00000000 APBPrescTable
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:200 .rodata.APBPrescTable:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:207 .rodata.AHBPrescTable:00000000 $d
C:\Users\nived\AppData\Local\Temp\ccPXvr5S.s:215 .data.SystemCoreClock:00000000 $d
NO UNDEFINED SYMBOLS