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PDU_Code/build/stm32f3xx_hal_pwr.lst

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ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f3xx_hal_pwr.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c"
20 .section .text.HAL_PWR_DeInit,"ax",%progbits
21 .align 1
22 .global HAL_PWR_DeInit
23 .syntax unified
24 .thumb
25 .thumb_func
27 HAL_PWR_DeInit:
28 .LFB130:
1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @file stm32f3xx_hal_pwr.c
4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @author MCD Application Team
5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver.
6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Initialization/de-initialization functions
9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Peripheral Control functions
10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @attention
13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Copyright (c) 2016 STMicroelectronics.
15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * All rights reserved.
16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file
18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * in the root directory of this software component.
19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #include "stm32f3xx_hal.h"
26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @addtogroup STM32F3xx_HAL_Driver
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 2
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR
32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver
33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data
58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted
59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** write accesses.
60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values.
71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
29 .loc 1 74 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
34 .loc 1 75 3 view .LVU1
35 0000 044B ldr r3, .L2
36 0002 1A69 ldr r2, [r3, #16]
37 0004 42F08052 orr r2, r2, #268435456
38 0008 1A61 str r2, [r3, #16]
76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
39 .loc 1 76 3 view .LVU2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 3
40 000a 1A69 ldr r2, [r3, #16]
41 000c 22F08052 bic r2, r2, #268435456
42 0010 1A61 str r2, [r3, #16]
77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
43 .loc 1 77 1 is_stmt 0 view .LVU3
44 0012 7047 bx lr
45 .L3:
46 .align 2
47 .L2:
48 0014 00100240 .word 1073876992
49 .cfi_endproc
50 .LFE130:
52 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
53 .align 1
54 .global HAL_PWR_EnableBkUpAccess
55 .syntax unified
56 .thumb
57 .thumb_func
59 HAL_PWR_EnableBkUpAccess:
60 .LFB131:
78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC
81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
61 .loc 1 87 1 is_stmt 1 view -0
62 .cfi_startproc
63 @ args = 0, pretend = 0, frame = 0
64 @ frame_needed = 0, uses_anonymous_args = 0
65 @ link register save eliminated.
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP);
66 .loc 1 88 3 view .LVU5
67 0000 024A ldr r2, .L5
68 0002 1368 ldr r3, [r2]
69 0004 43F48073 orr r3, r3, #256
70 0008 1360 str r3, [r2]
89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
71 .loc 1 89 1 is_stmt 0 view .LVU6
72 000a 7047 bx lr
73 .L6:
74 .align 2
75 .L5:
76 000c 00700040 .word 1073770496
77 .cfi_endproc
78 .LFE131:
80 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
81 .align 1
82 .global HAL_PWR_DisableBkUpAccess
83 .syntax unified
84 .thumb
85 .thumb_func
87 HAL_PWR_DisableBkUpAccess:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 4
88 .LFB132:
90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC
93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
89 .loc 1 99 1 is_stmt 1 view -0
90 .cfi_startproc
91 @ args = 0, pretend = 0, frame = 0
92 @ frame_needed = 0, uses_anonymous_args = 0
93 @ link register save eliminated.
100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP);
94 .loc 1 100 3 view .LVU8
95 0000 024A ldr r2, .L8
96 0002 1368 ldr r3, [r2]
97 0004 23F48073 bic r3, r3, #256
98 0008 1360 str r3, [r2]
101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
99 .loc 1 101 1 is_stmt 0 view .LVU9
100 000a 7047 bx lr
101 .L9:
102 .align 2
103 .L8:
104 000c 00700040 .word 1073770496
105 .cfi_endproc
106 .LFE132:
108 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
109 .align 1
110 .global HAL_PWR_EnableWakeUpPin
111 .syntax unified
112 .thumb
113 .thumb_func
115 HAL_PWR_EnableWakeUpPin:
116 .LVL0:
117 .LFB133:
102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @}
105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Low Power modes configuration functions
109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Peripheral Control functions #####
114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** WakeUp pin configuration ***
117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================
118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 5
119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** forced in input pull down configuration and is active on rising edges.
121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) There are up to three WakeUp pins:
122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 1 on PA.00.
123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 3 on PE.06.
125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Main and Backup Regulators configuration ***
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================================
128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to
131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** save battery life.
132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** protected to prevent confidential data, such as cryptographic private
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** key, from being accessed. The backup SRAM can be erased only through
136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the Flash interface when a protection level change from level 1 to
137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** level 0 is requested.
138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** -@- Refer to the description of Read protection (RDP) in the Flash
139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programming manual.
140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Refer to the datasheets for more details.
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Low Power modes configuration ***
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =====================================
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The devices feature 3 low-power modes:
147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator
149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** in low power mode
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Sleep mode ***
153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ==================
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** functions with
158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode.
164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Stop mode ***
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =================
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** are preserved.
171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode to minimize the co
172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** function with:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 6
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Main regulator ON or
177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Low Power regulator ON.
178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** when programmed in wakeup mode (the peripheral must be
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programmed in wakeup mode and the corresponding interrupt vector
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** must be enabled in the NVIC).
186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Standby mode ***
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ====================
189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based
191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost
194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** circuitry.
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator is OFF.
197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================
206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event,
209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode).
210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the
218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT()
222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode
224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c
227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling
228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function.
229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the comparator to generate the event.
230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 7
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality.
236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be value of :
238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
118 .loc 1 242 1 is_stmt 1 view -0
119 .cfi_startproc
120 @ args = 0, pretend = 0, frame = 0
121 @ frame_needed = 0, uses_anonymous_args = 0
122 @ link register save eliminated.
243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
123 .loc 1 244 3 view .LVU11
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Enable the EWUPx pin */
246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx);
124 .loc 1 246 3 view .LVU12
125 0000 024A ldr r2, .L11
126 0002 5368 ldr r3, [r2, #4]
127 0004 0343 orrs r3, r3, r0
128 0006 5360 str r3, [r2, #4]
247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
129 .loc 1 247 1 is_stmt 0 view .LVU13
130 0008 7047 bx lr
131 .L12:
132 000a 00BF .align 2
133 .L11:
134 000c 00700040 .word 1073770496
135 .cfi_endproc
136 .LFE133:
138 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
139 .align 1
140 .global HAL_PWR_DisableWakeUpPin
141 .syntax unified
142 .thumb
143 .thumb_func
145 HAL_PWR_DisableWakeUpPin:
146 .LVL1:
147 .LFB134:
248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality.
251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be values of :
253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
148 .loc 1 257 1 is_stmt 1 view -0
149 .cfi_startproc
150 @ args = 0, pretend = 0, frame = 0
151 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 8
152 @ link register save eliminated.
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
153 .loc 1 259 3 view .LVU15
260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Disable the EWUPx pin */
261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx);
154 .loc 1 261 3 view .LVU16
155 0000 024A ldr r2, .L14
156 0002 5368 ldr r3, [r2, #4]
157 0004 23EA0003 bic r3, r3, r0
158 0008 5360 str r3, [r2, #4]
262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
159 .loc 1 262 1 is_stmt 0 view .LVU17
160 000a 7047 bx lr
161 .L15:
162 .align 2
163 .L14:
164 000c 00700040 .word 1073770496
165 .cfi_endproc
166 .LFE134:
168 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
169 .align 1
170 .global HAL_PWR_EnterSLEEPMode
171 .syntax unified
172 .thumb
173 .thumb_func
175 HAL_PWR_EnterSLEEPMode:
176 .LVL2:
177 .LFB135:
263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters Sleep mode.
266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode.
268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note This parameter has no effect in F3 family and is just maintained to
272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * offer full portability of other STM32 families software.
273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as
275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the interrupt wake up source.
276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
178 .loc 1 282 1 is_stmt 1 view -0
179 .cfi_startproc
180 @ args = 0, pretend = 0, frame = 0
181 @ frame_needed = 0, uses_anonymous_args = 0
182 @ link register save eliminated.
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
183 .loc 1 284 3 view .LVU19
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 9
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
184 .loc 1 287 3 view .LVU20
185 .loc 1 287 6 is_stmt 0 view .LVU21
186 0000 064A ldr r2, .L20
187 0002 1369 ldr r3, [r2, #16]
188 .loc 1 287 12 view .LVU22
189 0004 23F00403 bic r3, r3, #4
190 0008 1361 str r3, [r2, #16]
288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
191 .loc 1 290 3 is_stmt 1 view .LVU23
192 .loc 1 290 5 is_stmt 0 view .LVU24
193 000a 0129 cmp r1, #1
194 000c 03D0 beq .L19
291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
195 .loc 1 298 5 is_stmt 1 view .LVU25
196 .syntax unified
197 @ 298 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
198 000e 40BF sev
199 @ 0 "" 2
299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
200 .loc 1 299 5 view .LVU26
201 @ 299 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
202 0010 20BF wfe
203 @ 0 "" 2
300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
204 .loc 1 300 5 view .LVU27
205 @ 300 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
206 0012 20BF wfe
207 @ 0 "" 2
301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
208 .loc 1 302 1 is_stmt 0 view .LVU28
209 .thumb
210 .syntax unified
211 0014 7047 bx lr
212 .L19:
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
213 .loc 1 293 5 is_stmt 1 view .LVU29
214 .syntax unified
215 @ 293 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
216 0016 30BF wfi
217 @ 0 "" 2
218 .thumb
219 .syntax unified
220 0018 7047 bx lr
221 .L21:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 10
222 001a 00BF .align 2
223 .L20:
224 001c 00ED00E0 .word -536810240
225 .cfi_endproc
226 .LFE135:
228 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
229 .align 1
230 .global HAL_PWR_EnterSTOPMode
231 .syntax unified
232 .thumb
233 .thumb_func
235 HAL_PWR_EnterSTOPMode:
236 .LVL3:
237 .LFB136:
303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STOP mode.
306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock.
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode.
311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption
312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * is higher although the startup time is reduced.
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in STOP mode.
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
238 .loc 1 324 1 view -0
239 .cfi_startproc
240 @ args = 0, pretend = 0, frame = 0
241 @ frame_needed = 0, uses_anonymous_args = 0
242 @ link register save eliminated.
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** uint32_t tmpreg = 0U;
243 .loc 1 325 3 view .LVU31
326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
244 .loc 1 328 3 view .LVU32
329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
245 .loc 1 329 3 view .LVU33
330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select the regulator state in STOP mode ---------------------------------*/
332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg = PWR->CR;
246 .loc 1 332 3 view .LVU34
247 .loc 1 332 10 is_stmt 0 view .LVU35
248 0000 0B4A ldr r2, .L26
249 0002 1368 ldr r3, [r2]
250 .LVL4:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 11
333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */
335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
251 .loc 1 335 3 is_stmt 1 view .LVU36
252 .loc 1 335 10 is_stmt 0 view .LVU37
253 0004 23F00303 bic r3, r3, #3
254 .LVL5:
336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set LPDS bit according to Regulator value */
338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg |= Regulator;
255 .loc 1 338 3 is_stmt 1 view .LVU38
256 .loc 1 338 10 is_stmt 0 view .LVU39
257 0008 0343 orrs r3, r3, r0
258 .LVL6:
339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Store the new value */
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR = tmpreg;
259 .loc 1 341 3 is_stmt 1 view .LVU40
260 .loc 1 341 11 is_stmt 0 view .LVU41
261 000a 1360 str r3, [r2]
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
262 .loc 1 344 3 is_stmt 1 view .LVU42
263 .loc 1 344 6 is_stmt 0 view .LVU43
264 000c 094A ldr r2, .L26+4
265 000e 1369 ldr r3, [r2, #16]
266 .LVL7:
267 .loc 1 344 12 view .LVU44
268 0010 43F00403 orr r3, r3, #4
269 0014 1361 str r3, [r2, #16]
270 .LVL8:
345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STOP mode entry --------------------------------------------------*/
347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI)
271 .loc 1 347 3 is_stmt 1 view .LVU45
272 .loc 1 347 5 is_stmt 0 view .LVU46
273 0016 0129 cmp r1, #1
274 0018 08D0 beq .L25
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
275 .loc 1 355 5 is_stmt 1 view .LVU47
276 .syntax unified
277 @ 355 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
278 001a 40BF sev
279 @ 0 "" 2
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
280 .loc 1 356 5 view .LVU48
281 @ 356 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
282 001c 20BF wfe
283 @ 0 "" 2
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 12
357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
284 .loc 1 357 5 view .LVU49
285 @ 357 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
286 001e 20BF wfe
287 @ 0 "" 2
288 .thumb
289 .syntax unified
290 .L24:
358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */
361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
291 .loc 1 361 3 view .LVU50
292 .loc 1 361 6 is_stmt 0 view .LVU51
293 0020 044A ldr r2, .L26+4
294 0022 1369 ldr r3, [r2, #16]
295 .loc 1 361 12 view .LVU52
296 0024 23F00403 bic r3, r3, #4
297 0028 1361 str r3, [r2, #16]
362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
298 .loc 1 362 1 view .LVU53
299 002a 7047 bx lr
300 .L25:
350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
301 .loc 1 350 5 is_stmt 1 view .LVU54
302 .syntax unified
303 @ 350 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
304 002c 30BF wfi
305 @ 0 "" 2
306 .thumb
307 .syntax unified
308 002e F7E7 b .L24
309 .L27:
310 .align 2
311 .L26:
312 0030 00700040 .word 1073770496
313 0034 00ED00E0 .word -536810240
314 .cfi_endproc
315 .LFE136:
317 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
318 .align 1
319 .global HAL_PWR_EnterSTANDBYMode
320 .syntax unified
321 .thumb
322 .thumb_func
324 HAL_PWR_EnterSTANDBYMode:
325 .LFB137:
363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STANDBY mode.
366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for:
367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - Reset pad (still available),
368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - RTC alternate function pins if configured for tamper, time-stamp, RTC
369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out,
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - WKUP pins if enabled.
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 13
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
326 .loc 1 374 1 view -0
327 .cfi_startproc
328 @ args = 0, pretend = 0, frame = 0
329 @ frame_needed = 0, uses_anonymous_args = 0
330 @ link register save eliminated.
375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STANDBY mode */
376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR |= PWR_CR_PDDS;
331 .loc 1 376 3 view .LVU56
332 .loc 1 376 6 is_stmt 0 view .LVU57
333 0000 054A ldr r2, .L29
334 0002 1368 ldr r3, [r2]
335 .loc 1 376 11 view .LVU58
336 0004 43F00203 orr r3, r3, #2
337 0008 1360 str r3, [r2]
377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
338 .loc 1 379 3 is_stmt 1 view .LVU59
339 .loc 1 379 6 is_stmt 0 view .LVU60
340 000a 044A ldr r2, .L29+4
341 000c 1369 ldr r3, [r2, #16]
342 .loc 1 379 12 view .LVU61
343 000e 43F00403 orr r3, r3, #4
344 0012 1361 str r3, [r2, #16]
380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #if defined ( __CC_ARM)
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __force_stores();
384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #endif
385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
345 .loc 1 386 3 is_stmt 1 view .LVU62
346 .syntax unified
347 @ 386 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
348 0014 30BF wfi
349 @ 0 "" 2
387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
350 .loc 1 387 1 is_stmt 0 view .LVU63
351 .thumb
352 .syntax unified
353 0016 7047 bx lr
354 .L30:
355 .align 2
356 .L29:
357 0018 00700040 .word 1073770496
358 001c 00ED00E0 .word -536810240
359 .cfi_endproc
360 .LFE137:
362 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
363 .align 1
364 .global HAL_PWR_EnableSleepOnExit
365 .syntax unified
366 .thumb
367 .thumb_func
369 HAL_PWR_EnableSleepOnExit:
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 14
370 .LFB138:
388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * interruptions handling.
395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
371 .loc 1 398 1 is_stmt 1 view -0
372 .cfi_startproc
373 @ args = 0, pretend = 0, frame = 0
374 @ frame_needed = 0, uses_anonymous_args = 0
375 @ link register save eliminated.
399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
376 .loc 1 400 3 view .LVU65
377 0000 024A ldr r2, .L32
378 0002 1369 ldr r3, [r2, #16]
379 0004 43F00203 orr r3, r3, #2
380 0008 1361 str r3, [r2, #16]
401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
381 .loc 1 401 1 is_stmt 0 view .LVU66
382 000a 7047 bx lr
383 .L33:
384 .align 2
385 .L32:
386 000c 00ED00E0 .word -536810240
387 .cfi_endproc
388 .LFE138:
390 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
391 .align 1
392 .global HAL_PWR_DisableSleepOnExit
393 .syntax unified
394 .thumb
395 .thumb_func
397 HAL_PWR_DisableSleepOnExit:
398 .LFB139:
402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
399 .loc 1 411 1 is_stmt 1 view -0
400 .cfi_startproc
401 @ args = 0, pretend = 0, frame = 0
402 @ frame_needed = 0, uses_anonymous_args = 0
403 @ link register save eliminated.
412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 15
413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
404 .loc 1 413 3 view .LVU68
405 0000 024A ldr r2, .L35
406 0002 1369 ldr r3, [r2, #16]
407 0004 23F00203 bic r3, r3, #2
408 0008 1361 str r3, [r2, #16]
414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
409 .loc 1 414 1 is_stmt 0 view .LVU69
410 000a 7047 bx lr
411 .L36:
412 .align 2
413 .L35:
414 000c 00ED00E0 .word -536810240
415 .cfi_endproc
416 .LFE139:
418 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
419 .align 1
420 .global HAL_PWR_EnableSEVOnPend
421 .syntax unified
422 .thumb
423 .thumb_func
425 HAL_PWR_EnableSEVOnPend:
426 .LFB140:
415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit.
420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
427 .loc 1 425 1 is_stmt 1 view -0
428 .cfi_startproc
429 @ args = 0, pretend = 0, frame = 0
430 @ frame_needed = 0, uses_anonymous_args = 0
431 @ link register save eliminated.
426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
432 .loc 1 427 3 view .LVU71
433 0000 024A ldr r2, .L38
434 0002 1369 ldr r3, [r2, #16]
435 0004 43F01003 orr r3, r3, #16
436 0008 1361 str r3, [r2, #16]
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
437 .loc 1 428 1 is_stmt 0 view .LVU72
438 000a 7047 bx lr
439 .L39:
440 .align 2
441 .L38:
442 000c 00ED00E0 .word -536810240
443 .cfi_endproc
444 .LFE140:
446 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
447 .align 1
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 16
448 .global HAL_PWR_DisableSEVOnPend
449 .syntax unified
450 .thumb
451 .thumb_func
453 HAL_PWR_DisableSEVOnPend:
454 .LFB141:
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit.
433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
455 .loc 1 438 1 is_stmt 1 view -0
456 .cfi_startproc
457 @ args = 0, pretend = 0, frame = 0
458 @ frame_needed = 0, uses_anonymous_args = 0
459 @ link register save eliminated.
439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
460 .loc 1 440 3 view .LVU74
461 0000 024A ldr r2, .L41
462 0002 1369 ldr r3, [r2, #16]
463 0004 23F01003 bic r3, r3, #16
464 0008 1361 str r3, [r2, #16]
441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
465 .loc 1 441 1 is_stmt 0 view .LVU75
466 000a 7047 bx lr
467 .L42:
468 .align 2
469 .L41:
470 000c 00ED00E0 .word -536810240
471 .cfi_endproc
472 .LFE141:
474 .text
475 .Letext0:
476 .file 2 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
477 .file 3 "c:\\users\\nived\\appdata\\roaming\\code\\user\\globalstorage\\bmd.stm32-for-vscode\\@xpa
478 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
479 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
ARM GAS C:\Users\nived\AppData\Local\Temp\ccGMN715.s page 17
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_pwr.c
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:21 .text.HAL_PWR_DeInit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:27 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:48 .text.HAL_PWR_DeInit:00000014 $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:53 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:59 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:76 .text.HAL_PWR_EnableBkUpAccess:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:81 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:87 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:104 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:109 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:115 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:134 .text.HAL_PWR_EnableWakeUpPin:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:139 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:145 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:164 .text.HAL_PWR_DisableWakeUpPin:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:169 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:175 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:224 .text.HAL_PWR_EnterSLEEPMode:0000001c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:229 .text.HAL_PWR_EnterSTOPMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:235 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:312 .text.HAL_PWR_EnterSTOPMode:00000030 $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:318 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:324 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:357 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:363 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:369 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:386 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:391 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:397 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:414 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:419 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:425 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:442 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:447 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:453 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
C:\Users\nived\AppData\Local\Temp\ccGMN715.s:470 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
NO UNDEFINED SYMBOLS
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