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Richard Koeppe 2024-06-06 11:36:00 +02:00
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257." name="/" resourcePath="">
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1541132968" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1018873086" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F302CBTx" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1708237435" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.303405219" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.82284604" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1171738222" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1242352816" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1743363792" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F302CBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32F3xx_HAL_Driver/Inc | ../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F3xx/Include | ../Drivers/CMSIS/Include || || || USE_HAL_DRIVER | STM32F302xC || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32F302CBTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || || || " valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.2007101975" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="16" valueType="string"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.681433073" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
<builder buildPath="${workspace_loc:/vn200}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1628238581" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1182306613" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.919925241" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.907737188" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="DEBUG"/>
</option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1173795593" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1030194027" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.713361179" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.287371090" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1025392306" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="DEBUG"/>
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
<listOptionValue builtIn="false" value="STM32F302xC"/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.434650223" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="../Core/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32F3xx_HAL_Driver/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F3xx/Include"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
<listOptionValue builtIn="false" value="../Converter/Inc"/>
<listOptionValue builtIn="false" value="/usr/local/include"/>
</option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1424894625" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1470060334" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1105197191" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.353699893" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols.1749177801" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="DEBUG"/>
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
<listOptionValue builtIn="false" value="STM32F302xC"/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.includepaths.1781147079" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="../Core/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32F3xx_HAL_Driver/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F3xx/Include"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
<listOptionValue builtIn="false" value="../Converter/Inc"/>
<listOptionValue builtIn="false" value="/usr/local/include"/>
</option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.238492915" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1417031510" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.979366948" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.1940164997" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F302CBTX_FLASH.ld}" valueType="string"/>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input.939254580" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1047138244" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.404275905" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.676818712" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1503763839" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1455670147" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.713991710" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1452067465" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.2015991819" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706." name="/" resourcePath="">
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.2050427844" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.408824865" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F302CBTx" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.952174163" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.37344129" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.1644324945" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.930604402" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.13868023" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1725746287" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F302CBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32F3xx_HAL_Driver/Inc | ../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F3xx/Include | ../Drivers/CMSIS/Include || || || USE_HAL_DRIVER | STM32F302xC || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32F302CBTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || || || " valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1622386512" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="16" valueType="string"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1886613476" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
<builder buildPath="${workspace_loc:/vn200}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.799638896" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.196843564" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1186771435" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.836642027" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1210460122" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1453485670" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1751927047" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1427988124" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
<listOptionValue builtIn="false" value="STM32F302xC"/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.860589034" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="../Core/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32F3xx_HAL_Driver/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F3xx/Include"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
</option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.382850113" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1585808867" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1513143532" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1145480558" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols.1818626468" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
<listOptionValue builtIn="false" value="STM32F302xC"/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.includepaths.1178325775" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="../Core/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32F3xx_HAL_Driver/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F3xx/Include"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
</option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.184868859" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1344283214" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.337536051" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.996420626" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F302CBTX_FLASH.ld}" valueType="string"/>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input.1896726598" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.424895305" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.209981923" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.369751799" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.932558241" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1894856063" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1416658596" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.549447363" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1018932209" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="vn200.null.437387398" name="vn200"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1470060334;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.238492915">
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1585808867;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.184868859">
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1030194027;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1424894625">
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1210460122;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.382850113">
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="refreshScope"/>
</cproject>

33
vn200/.project Normal file
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@ -0,0 +1,33 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>vn200</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

2
vn200/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs Normal file
View File

@ -0,0 +1,2 @@
eclipse.preferences.version=1
sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}}

25
vn200/.settings/language.settings.xml Normal file
View File

@ -0,0 +1,25 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.418201257" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="916997735105874892" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.424504706" name="Release">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="916997735105874892" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
</project>

4
vn200/.settings/stm32cubeide.project.prefs Normal file
View File

@ -0,0 +1,4 @@
66BE74F758C12D739921AEA421D593D3=0
8DF89ED150041C4CBC7CB9A9CAA90856=0FE3A692F5297FEB83FC6C4A28927594
DC22A860405A8BF2F2C095E5B6529F12=0FE3A692F5297FEB83FC6C4A28927594
eclipse.preferences.version=1

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vn200/Converter/Inc/Converter.h Normal file
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#include <stm32f302xc.h>
#include <stm32f3xx_hal.h>
#include <stm32f3xx_hal_conf.h>
#include <vn-interface/helper.h>
#include <vn-interface/registers.h>
#include "canhalal.h"
#include "can1.h"
#include "endec.hpp"
template <typename payload_t>
HAL_StatusTypeDef spi_read(SPI_HandleTypeDef *hspi, vn::pkg_request_read_t *pRequestMOSI, vn::pkg_response_t<payload_t> *pResponseMISO){
HAL_StatusTypeDef status = HAL_OK;
vn::header_t::response_t requestMISO;
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
status = HAL_SPI_TransmitReceive(hspi,
(uint8_t *)(pRequestMOSI),
(uint8_t *)(&requestMISO), // not relevant, but there to function
sizeof(*pRequestMOSI), 100);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
HAL_Delay(1);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
vn::pkg_response_t<payload_t> responseMOSI;
status = HAL_SPI_TransmitReceive(hspi,
(uint8_t *)(&responseMOSI), // just empty byte to allow the slave to transmit
(uint8_t *)(pResponseMISO),
sizeof(*pResponseMISO), 100);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
return status;
}
template <typename payload_t>
HAL_StatusTypeDef spi_write(SPI_HandleTypeDef *hspi, vn::pkg_request_write_t<payload_t> *pRequestMOSI, vn::pkg_response_t<payload_t> *pResponseMISO){
HAL_StatusTypeDef status = HAL_OK;
vn::header_t::response_t requestMISO;
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
status = HAL_SPI_TransmitReceive(hspi,
(uint8_t *)(pRequestMOSI),
(uint8_t *)(&requestMISO), // not relevant, but there to function
sizeof(*pRequestMOSI), 100);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
HAL_Delay(1);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
vn::pkg_response_t<payload_t> responseMOSI;
status = HAL_SPI_TransmitReceive(hspi,
(uint8_t *)(&responseMOSI), // just empty byte to allow the slave to transmit
(uint8_t *)(pResponseMISO),
sizeof(*pResponseMISO), 100);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
return status;
}
template <typename payload_t>
HAL_StatusTypeDef spi2can(SPI_HandleTypeDef *hspi, CAN_HandleTypeDef *hcan, const uint16_t& id){
auto request = vn::pkg_request_read_t(id);
auto response = vn::pkg_response_t<payload_t>();
size_t datalen = 8;
uint16_t can_id = 0;
uint8_t *data = nullptr;
spi_read(hspi, &request, &response);
switch (id) {
case vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterID:
{
can_id = CAN1_VN200_YPR_FRAME_ID;
vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister payload;
payload = response.payload;
//canlib::encode::can1::vn200_ypr(canlib::frame::decoded::can1::vn200_ypr_t((double) payload.yawPitchRoll.x, (double) payload.yawPitchRoll.y, (double) payload.yawPitchRoll.z));
}
break;
default:
break;
}
ftcan_transmit(hcan, can_id, data, datalen);
return HAL_OK;
}

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vn200/Converter/Inc/can1.h Normal file
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/**
* The MIT License (MIT)
*
* Copyright (c) 2018-2019 Erik Moqvist
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/**
* This file was generated by cantools version 0.1.dev1740+ge714fab Tue Jun 4 14:20:13 2024.
*/
#ifndef CAN1_H
#define CAN1_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#ifndef EINVAL
# define EINVAL 22
#endif
/* Frame ids. */
#define CAN1_VN200_INS_FRAME_ID (0x01u)
#define CAN1_VN200_IMU_FRAME_ID (0x02u)
#define CAN1_VN200_YPR_FRAME_ID (0x05u)
/* Frame lengths in bytes. */
#define CAN1_VN200_INS_LENGTH (8u)
#define CAN1_VN200_IMU_LENGTH (8u)
#define CAN1_VN200_YPR_LENGTH (8u)
/* Extended or standard frame types. */
#define CAN1_VN200_INS_IS_EXTENDED (0)
#define CAN1_VN200_IMU_IS_EXTENDED (0)
#define CAN1_VN200_YPR_IS_EXTENDED (0)
/* Frame cycle times in milliseconds. */
/* Signal choices. */
/* Frame Names. */
#define CAN1_VN200_INS_NAME "VN200_INS"
#define CAN1_VN200_IMU_NAME "VN200_IMU"
#define CAN1_VN200_YPR_NAME "VN200_YPR"
/* Signal Names. */
#define CAN1_VN200_INS_YAW_NAME "Yaw"
#define CAN1_VN200_IMU_MULTIPLEXER_NAME "multiplexer"
#define CAN1_VN200_IMU_ACCX_NAME "accx"
#define CAN1_VN200_IMU_ACCY_NAME "accy"
#define CAN1_VN200_IMU_ACCZ_NAME "accz"
#define CAN1_VN200_IMU_ANGX_NAME "angx"
#define CAN1_VN200_IMU_ANGY_NAME "angy"
#define CAN1_VN200_IMU_ANGZ_NAME "angz"
#define CAN1_VN200_YPR_YAW_NAME "yaw"
#define CAN1_VN200_YPR_PITCH_NAME "pitch"
#define CAN1_VN200_YPR_ROLL_NAME "roll"
/**
* Signals in message VN200_INS.
*
* VN200 INS - Measurements with sensor fusion
*
* All signal values are as on the CAN bus.
*/
struct can1_vn200_ins_t {
/**
* Range: 0..64255 (0..8031.875 rpm)
* Scale: 0.125
* Offset: 0
*/
uint16_t yaw;
};
/**
* Signals in message VN200_IMU.
*
* VN200 IMU - Measurements only IMU without algorithms
*
* All signal values are as on the CAN bus.
*/
struct can1_vn200_imu_t {
/**
* Range: -
* Scale: 0
* Offset: 0
*/
uint8_t multiplexer;
/**
* Range: -
* Scale: 0.06
* Offset: 0
*/
int16_t accx;
/**
* Range: -
* Scale: 0.06
* Offset: 0
*/
int16_t accy;
/**
* Range: -
* Scale: 0.06
* Offset: 0
*/
int16_t accz;
/**
* Range: -
* Scale: 0.002
* Offset: 0
*/
int16_t angx;
/**
* Range: -
* Scale: 0.002
* Offset: 0
*/
int16_t angy;
/**
* Range: -
* Scale: 0.002
* Offset: 0
*/
int16_t angz;
};
/**
* Signals in message VN200_YPR.
*
* All signal values are as on the CAN bus.
*/
struct can1_vn200_ypr_t {
/**
* Range: -
* Scale: 0.006
* Offset: 0
*/
uint16_t yaw;
/**
* Range: -
* Scale: 0.006
* Offset: 0
*/
uint16_t pitch;
/**
* Range: -
* Scale: 0.006
* Offset: 0
*/
uint16_t roll;
};
/**
* Pack message VN200_INS.
*
* @param[out] dst_p Buffer to pack the message into.
* @param[in] src_p Data to pack.
* @param[in] size Size of dst_p.
*
* @return Size of packed data, or negative error code.
*/
int can1_vn200_ins_pack(
uint8_t *dst_p,
const struct can1_vn200_ins_t *src_p,
size_t size);
/**
* Unpack message VN200_INS.
*
* @param[out] dst_p Object to unpack the message into.
* @param[in] src_p Message to unpack.
* @param[in] size Size of src_p.
*
* @return zero(0) or negative error code.
*/
int can1_vn200_ins_unpack(
struct can1_vn200_ins_t *dst_p,
const uint8_t *src_p,
size_t size);
/**
* Init message fields to default values from VN200_INS.
*
* @param[in] msg_p Message to init.
*
* @return zero(0) on success or (-1) in case of nullptr argument.
*/
int can1_vn200_ins_init(struct can1_vn200_ins_t *msg_p);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
uint16_t can1_vn200_ins_yaw_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_ins_yaw_decode(uint16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_ins_yaw_is_in_range(uint16_t value);
/**
* Pack message VN200_IMU.
*
* @param[out] dst_p Buffer to pack the message into.
* @param[in] src_p Data to pack.
* @param[in] size Size of dst_p.
*
* @return Size of packed data, or negative error code.
*/
int can1_vn200_imu_pack(
uint8_t *dst_p,
const struct can1_vn200_imu_t *src_p,
size_t size);
/**
* Unpack message VN200_IMU.
*
* @param[out] dst_p Object to unpack the message into.
* @param[in] src_p Message to unpack.
* @param[in] size Size of src_p.
*
* @return zero(0) or negative error code.
*/
int can1_vn200_imu_unpack(
struct can1_vn200_imu_t *dst_p,
const uint8_t *src_p,
size_t size);
/**
* Init message fields to default values from VN200_IMU.
*
* @param[in] msg_p Message to init.
*
* @return zero(0) on success or (-1) in case of nullptr argument.
*/
int can1_vn200_imu_init(struct can1_vn200_imu_t *msg_p);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
uint8_t can1_vn200_imu_multiplexer_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_imu_multiplexer_decode(uint8_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_imu_multiplexer_is_in_range(uint8_t value);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
int16_t can1_vn200_imu_accx_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_imu_accx_decode(int16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_imu_accx_is_in_range(int16_t value);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
int16_t can1_vn200_imu_accy_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_imu_accy_decode(int16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_imu_accy_is_in_range(int16_t value);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
int16_t can1_vn200_imu_accz_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_imu_accz_decode(int16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_imu_accz_is_in_range(int16_t value);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
int16_t can1_vn200_imu_angx_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_imu_angx_decode(int16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_imu_angx_is_in_range(int16_t value);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
int16_t can1_vn200_imu_angy_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_imu_angy_decode(int16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_imu_angy_is_in_range(int16_t value);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
int16_t can1_vn200_imu_angz_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_imu_angz_decode(int16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_imu_angz_is_in_range(int16_t value);
/**
* Pack message VN200_YPR.
*
* @param[out] dst_p Buffer to pack the message into.
* @param[in] src_p Data to pack.
* @param[in] size Size of dst_p.
*
* @return Size of packed data, or negative error code.
*/
int can1_vn200_ypr_pack(
uint8_t *dst_p,
const struct can1_vn200_ypr_t *src_p,
size_t size);
/**
* Unpack message VN200_YPR.
*
* @param[out] dst_p Object to unpack the message into.
* @param[in] src_p Message to unpack.
* @param[in] size Size of src_p.
*
* @return zero(0) or negative error code.
*/
int can1_vn200_ypr_unpack(
struct can1_vn200_ypr_t *dst_p,
const uint8_t *src_p,
size_t size);
/**
* Init message fields to default values from VN200_YPR.
*
* @param[in] msg_p Message to init.
*
* @return zero(0) on success or (-1) in case of nullptr argument.
*/
int can1_vn200_ypr_init(struct can1_vn200_ypr_t *msg_p);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
uint16_t can1_vn200_ypr_yaw_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_ypr_yaw_decode(uint16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_ypr_yaw_is_in_range(uint16_t value);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
uint16_t can1_vn200_ypr_pitch_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_ypr_pitch_decode(uint16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_ypr_pitch_is_in_range(uint16_t value);
/**
* Encode given signal by applying scaling and offset.
*
* @param[in] value Signal to encode.
*
* @return Encoded signal.
*/
uint16_t can1_vn200_ypr_roll_encode(double value);
/**
* Decode given signal by applying scaling and offset.
*
* @param[in] value Signal to decode.
*
* @return Decoded signal.
*/
double can1_vn200_ypr_roll_decode(uint16_t value);
/**
* Check that given signal is in allowed range.
*
* @param[in] value Signal to check.
*
* @return true if in range, false otherwise.
*/
bool can1_vn200_ypr_roll_is_in_range(uint16_t value);
#ifdef __cplusplus
}
#endif
#endif

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vn200/Converter/Inc/canhalal.h Normal file
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#include <stm32f302xc.h>
#include <stm32f3xx_hal.h>
#include <stm32f3xx_hal_conf.h>
HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef ftcan_transmit(CAN_HandleTypeDef *hcan, uint16_t id, const uint8_t *data, size_t datalen);

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vn200/Converter/Inc/endec.hpp Normal file
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#ifndef _ENDEC_HPP_
#define _ENDEC_HPP_
#include "can1.h"
#include <functional>
namespace canlib {
// frame structures
namespace frame {
namespace decoded {
namespace can1 {
struct vn200_ins_t {
double yaw;
vn200_ins_t() {
this->yaw = 0.0;
}
vn200_ins_t(
double yaw) {
this->yaw = yaw;
}
};
struct vn200_imu_t {
double multiplexer;
double accx;
double accy;
double accz;
double angx;
double angy;
double angz;
vn200_imu_t() {
this->multiplexer = 0.0;
this->accx = 0.0;
this->accy = 0.0;
this->accz = 0.0;
this->angx = 0.0;
this->angy = 0.0;
this->angz = 0.0;
}
vn200_imu_t(
double multiplexer,
double accx,
double accy,
double accz,
double angx,
double angy,
double angz) {
this->multiplexer = multiplexer;
this->accx = accx;
this->accy = accy;
this->accz = accz;
this->angx = angx;
this->angy = angy;
this->angz = angz;
}
};
struct vn200_ypr_t {
double yaw;
double pitch;
double roll;
vn200_ypr_t() {
this->yaw = 0.0;
this->pitch = 0.0;
this->roll = 0.0;
}
vn200_ypr_t(
double yaw,
double pitch,
double roll) {
this->yaw = yaw;
this->pitch = pitch;
this->roll = roll;
}
};
}
}
}
// encode functions
namespace encode {
namespace can1 {
inline can1_vn200_ins_t vn200_ins(const frame::decoded::can1::vn200_ins_t frame_decoded) {
can1_vn200_ins_t frame_encoded;
frame_encoded.yaw = can1_vn200_ins_yaw_encode(frame_decoded.yaw);
return frame_encoded;
}
inline can1_vn200_imu_t vn200_imu(const frame::decoded::can1::vn200_imu_t frame_decoded) {
can1_vn200_imu_t frame_encoded;
frame_encoded.multiplexer = can1_vn200_imu_multiplexer_encode(frame_decoded.multiplexer);
frame_encoded.accx = can1_vn200_imu_accx_encode(frame_decoded.accx);
frame_encoded.accy = can1_vn200_imu_accy_encode(frame_decoded.accy);
frame_encoded.accz = can1_vn200_imu_accz_encode(frame_decoded.accz);
frame_encoded.angx = can1_vn200_imu_angx_encode(frame_decoded.angx);
frame_encoded.angy = can1_vn200_imu_angy_encode(frame_decoded.angy);
frame_encoded.angz = can1_vn200_imu_angz_encode(frame_decoded.angz);
return frame_encoded;
}
inline can1_vn200_ypr_t vn200_ypr(const frame::decoded::can1::vn200_ypr_t frame_decoded) {
can1_vn200_ypr_t frame_encoded;
frame_encoded.yaw = can1_vn200_ypr_yaw_encode(frame_decoded.yaw);
frame_encoded.pitch = can1_vn200_ypr_pitch_encode(frame_decoded.pitch);
frame_encoded.roll = can1_vn200_ypr_roll_encode(frame_decoded.roll);
return frame_encoded;
}
}
}
// decode functions
namespace decode {
namespace can1 {
inline frame::decoded::can1::vn200_ins_t vn200_ins(const can1_vn200_ins_t frame_encoded) {
frame::decoded::can1::vn200_ins_t frame_decoded;
frame_decoded.yaw = can1_vn200_ins_yaw_decode(frame_encoded.yaw);
return frame_decoded;
}
inline frame::decoded::can1::vn200_imu_t vn200_imu(const can1_vn200_imu_t frame_encoded) {
frame::decoded::can1::vn200_imu_t frame_decoded;
frame_decoded.multiplexer = can1_vn200_imu_multiplexer_decode(frame_encoded.multiplexer);
frame_decoded.accx = can1_vn200_imu_accx_decode(frame_encoded.accx);
frame_decoded.accy = can1_vn200_imu_accy_decode(frame_encoded.accy);
frame_decoded.accz = can1_vn200_imu_accz_decode(frame_encoded.accz);
frame_decoded.angx = can1_vn200_imu_angx_decode(frame_encoded.angx);
frame_decoded.angy = can1_vn200_imu_angy_decode(frame_encoded.angy);
frame_decoded.angz = can1_vn200_imu_angz_decode(frame_encoded.angz);
return frame_decoded;
}
inline frame::decoded::can1::vn200_ypr_t vn200_ypr(const can1_vn200_ypr_t frame_encoded) {
frame::decoded::can1::vn200_ypr_t frame_decoded;
frame_decoded.yaw = can1_vn200_ypr_yaw_decode(frame_encoded.yaw);
frame_decoded.pitch = can1_vn200_ypr_pitch_decode(frame_encoded.pitch);
frame_decoded.roll = can1_vn200_ypr_roll_decode(frame_encoded.roll);
return frame_decoded;
}
}
}
// callback structure
namespace callback {
namespace can1 {
inline std::function<void(can1_vn200_ins_t, frame::decoded::can1::vn200_ins_t)> vn200_ins = NULL;
inline std::function<void(can1_vn200_imu_t, frame::decoded::can1::vn200_imu_t)> vn200_imu = NULL;
inline std::function<void(can1_vn200_ypr_t, frame::decoded::can1::vn200_ypr_t)> vn200_ypr = NULL;
}
}
}
#endif // _ENDEC_HPP_

2
vn200/Converter/Src/Converter.cpp Normal file
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#include "Converter.h"

461
vn200/Converter/Src/can1.cpp Normal file
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/**
* The MIT License (MIT)
*
* Copyright (c) 2018-2019 Erik Moqvist
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/**
* This file was generated by cantools version 0.1.dev1740+ge714fab Tue Jun 4 14:20:13 2024.
*/
#include <string.h>
#include "can1.h"
static inline uint8_t pack_left_shift_u8(
uint8_t value,
uint8_t shift,
uint8_t mask)
{
return (uint8_t)((uint8_t)(value << shift) & mask);
}
static inline uint8_t pack_left_shift_u16(
uint16_t value,
uint8_t shift,
uint8_t mask)
{
return (uint8_t)((uint8_t)(value << shift) & mask);
}
static inline uint8_t pack_right_shift_u16(
uint16_t value,
uint8_t shift,
uint8_t mask)
{
return (uint8_t)((uint8_t)(value >> shift) & mask);
}
static inline uint16_t unpack_left_shift_u16(
uint8_t value,
uint8_t shift,
uint8_t mask)
{
return (uint16_t)((uint16_t)(value & mask) << shift);
}
static inline uint8_t unpack_right_shift_u8(
uint8_t value,
uint8_t shift,
uint8_t mask)
{
return (uint8_t)((uint8_t)(value & mask) >> shift);
}
static inline uint16_t unpack_right_shift_u16(
uint8_t value,
uint8_t shift,
uint8_t mask)
{
return (uint16_t)((uint16_t)(value & mask) >> shift);
}
int can1_vn200_ins_pack(
uint8_t *dst_p,
const struct can1_vn200_ins_t *src_p,
size_t size)
{
if (size < 8u) {
return (-EINVAL);
}
memset(&dst_p[0], 0, 8);
dst_p[3] |= pack_left_shift_u16(src_p->yaw, 0u, 0xffu);
dst_p[4] |= pack_right_shift_u16(src_p->yaw, 8u, 0xffu);
return (8);
}
int can1_vn200_ins_unpack(
struct can1_vn200_ins_t *dst_p,
const uint8_t *src_p,
size_t size)
{
if (size < 8u) {
return (-EINVAL);
}
dst_p->yaw = unpack_right_shift_u16(src_p[3], 0u, 0xffu);
dst_p->yaw |= unpack_left_shift_u16(src_p[4], 8u, 0xffu);
return (0);
}
int can1_vn200_ins_init(struct can1_vn200_ins_t *msg_p)
{
if (msg_p == NULL) return -1;
memset(msg_p, 0, sizeof(struct can1_vn200_ins_t));
return 0;
}
uint16_t can1_vn200_ins_yaw_encode(double value)
{
return (uint16_t)(value / 0.125);
}
double can1_vn200_ins_yaw_decode(uint16_t value)
{
return ((double)value * 0.125);
}
bool can1_vn200_ins_yaw_is_in_range(uint16_t value)
{
return (value <= 64255u);
}
int can1_vn200_imu_pack(
uint8_t *dst_p,
const struct can1_vn200_imu_t *src_p,
size_t size)
{
uint16_t accx;
uint16_t accy;
uint16_t accz;
uint16_t angx;
uint16_t angy;
uint16_t angz;
if (size < 8u) {
return (-EINVAL);
}
memset(&dst_p[0], 0, 8);
dst_p[0] |= pack_left_shift_u8(src_p->multiplexer, 0u, 0x0fu);
accx = (uint16_t)src_p->accx;
dst_p[0] |= pack_left_shift_u16(accx, 4u, 0xf0u);
dst_p[1] |= pack_right_shift_u16(accx, 4u, 0x3fu);
accy = (uint16_t)src_p->accy;
dst_p[1] |= pack_left_shift_u16(accy, 6u, 0xc0u);
dst_p[2] |= pack_right_shift_u16(accy, 2u, 0xffu);
accz = (uint16_t)src_p->accz;
dst_p[3] |= pack_left_shift_u16(accz, 0u, 0xffu);
dst_p[4] |= pack_right_shift_u16(accz, 8u, 0x03u);
angx = (uint16_t)src_p->angx;
dst_p[4] |= pack_left_shift_u16(angx, 2u, 0xfcu);
dst_p[5] |= pack_right_shift_u16(angx, 6u, 0x0fu);
angy = (uint16_t)src_p->angy;
dst_p[5] |= pack_left_shift_u16(angy, 4u, 0xf0u);
dst_p[6] |= pack_right_shift_u16(angy, 4u, 0x3fu);
angz = (uint16_t)src_p->angz;
dst_p[6] |= pack_left_shift_u16(angz, 6u, 0xc0u);
dst_p[7] |= pack_right_shift_u16(angz, 2u, 0xffu);
return (8);
}
int can1_vn200_imu_unpack(
struct can1_vn200_imu_t *dst_p,
const uint8_t *src_p,
size_t size)
{
uint16_t accx;
uint16_t accy;
uint16_t accz;
uint16_t angx;
uint16_t angy;
uint16_t angz;
if (size < 8u) {
return (-EINVAL);
}
dst_p->multiplexer = unpack_right_shift_u8(src_p[0], 0u, 0x0fu);
accx = unpack_right_shift_u16(src_p[0], 4u, 0xf0u);
accx |= unpack_left_shift_u16(src_p[1], 4u, 0x3fu);
if ((accx & (1u << 9)) != 0u) {
accx |= 0xfc00u;
}
dst_p->accx = (int16_t)accx;
accy = unpack_right_shift_u16(src_p[1], 6u, 0xc0u);
accy |= unpack_left_shift_u16(src_p[2], 2u, 0xffu);
if ((accy & (1u << 9)) != 0u) {
accy |= 0xfc00u;
}
dst_p->accy = (int16_t)accy;
accz = unpack_right_shift_u16(src_p[3], 0u, 0xffu);
accz |= unpack_left_shift_u16(src_p[4], 8u, 0x03u);
if ((accz & (1u << 9)) != 0u) {
accz |= 0xfc00u;
}
dst_p->accz = (int16_t)accz;
angx = unpack_right_shift_u16(src_p[4], 2u, 0xfcu);
angx |= unpack_left_shift_u16(src_p[5], 6u, 0x0fu);
if ((angx & (1u << 9)) != 0u) {
angx |= 0xfc00u;
}
dst_p->angx = (int16_t)angx;
angy = unpack_right_shift_u16(src_p[5], 4u, 0xf0u);
angy |= unpack_left_shift_u16(src_p[6], 4u, 0x3fu);
if ((angy & (1u << 9)) != 0u) {
angy |= 0xfc00u;
}
dst_p->angy = (int16_t)angy;
angz = unpack_right_shift_u16(src_p[6], 6u, 0xc0u);
angz |= unpack_left_shift_u16(src_p[7], 2u, 0xffu);
if ((angz & (1u << 9)) != 0u) {
angz |= 0xfc00u;
}
dst_p->angz = (int16_t)angz;
return (0);
}
int can1_vn200_imu_init(struct can1_vn200_imu_t *msg_p)
{
if (msg_p == NULL) return -1;
memset(msg_p, 0, sizeof(struct can1_vn200_imu_t));
return 0;
}
uint8_t can1_vn200_imu_multiplexer_encode(double value)
{
return (uint8_t)(value / 0.0);
}
double can1_vn200_imu_multiplexer_decode(uint8_t value)
{
return ((double)value * 0.0);
}
bool can1_vn200_imu_multiplexer_is_in_range(uint8_t value)
{
return (value <= 15u);
}
int16_t can1_vn200_imu_accx_encode(double value)
{
return (int16_t)(value / 0.06);
}
double can1_vn200_imu_accx_decode(int16_t value)
{
return ((double)value * 0.06);
}
bool can1_vn200_imu_accx_is_in_range(int16_t value)
{
return ((value >= -512) && (value <= 511));
}
int16_t can1_vn200_imu_accy_encode(double value)
{
return (int16_t)(value / 0.06);
}
double can1_vn200_imu_accy_decode(int16_t value)
{
return ((double)value * 0.06);
}
bool can1_vn200_imu_accy_is_in_range(int16_t value)
{
return ((value >= -512) && (value <= 511));
}
int16_t can1_vn200_imu_accz_encode(double value)
{
return (int16_t)(value / 0.06);
}
double can1_vn200_imu_accz_decode(int16_t value)
{
return ((double)value * 0.06);
}
bool can1_vn200_imu_accz_is_in_range(int16_t value)
{
return ((value >= -512) && (value <= 511));
}
int16_t can1_vn200_imu_angx_encode(double value)
{
return (int16_t)(value / 0.002);
}
double can1_vn200_imu_angx_decode(int16_t value)
{
return ((double)value * 0.002);
}
bool can1_vn200_imu_angx_is_in_range(int16_t value)
{
return ((value >= -512) && (value <= 511));
}
int16_t can1_vn200_imu_angy_encode(double value)
{
return (int16_t)(value / 0.002);
}
double can1_vn200_imu_angy_decode(int16_t value)
{
return ((double)value * 0.002);
}
bool can1_vn200_imu_angy_is_in_range(int16_t value)
{
return ((value >= -512) && (value <= 511));
}
int16_t can1_vn200_imu_angz_encode(double value)
{
return (int16_t)(value / 0.002);
}
double can1_vn200_imu_angz_decode(int16_t value)
{
return ((double)value * 0.002);
}
bool can1_vn200_imu_angz_is_in_range(int16_t value)
{
return ((value >= -512) && (value <= 511));
}
int can1_vn200_ypr_pack(
uint8_t *dst_p,
const struct can1_vn200_ypr_t *src_p,
size_t size)
{
if (size < 8u) {
return (-EINVAL);
}
memset(&dst_p[0], 0, 8);
dst_p[0] |= pack_left_shift_u16(src_p->yaw, 0u, 0xffu);
dst_p[1] |= pack_right_shift_u16(src_p->yaw, 8u, 0xffu);
dst_p[2] |= pack_left_shift_u16(src_p->pitch, 0u, 0xffu);
dst_p[3] |= pack_right_shift_u16(src_p->pitch, 8u, 0xffu);
dst_p[4] |= pack_left_shift_u16(src_p->roll, 0u, 0xffu);
dst_p[5] |= pack_right_shift_u16(src_p->roll, 8u, 0xffu);
return (8);
}
int can1_vn200_ypr_unpack(
struct can1_vn200_ypr_t *dst_p,
const uint8_t *src_p,
size_t size)
{
if (size < 8u) {
return (-EINVAL);
}
dst_p->yaw = unpack_right_shift_u16(src_p[0], 0u, 0xffu);
dst_p->yaw |= unpack_left_shift_u16(src_p[1], 8u, 0xffu);
dst_p->pitch = unpack_right_shift_u16(src_p[2], 0u, 0xffu);
dst_p->pitch |= unpack_left_shift_u16(src_p[3], 8u, 0xffu);
dst_p->roll = unpack_right_shift_u16(src_p[4], 0u, 0xffu);
dst_p->roll |= unpack_left_shift_u16(src_p[5], 8u, 0xffu);
return (0);
}
int can1_vn200_ypr_init(struct can1_vn200_ypr_t *msg_p)
{
if (msg_p == NULL) return -1;
memset(msg_p, 0, sizeof(struct can1_vn200_ypr_t));
return 0;
}
uint16_t can1_vn200_ypr_yaw_encode(double value)
{
return (uint16_t)(value / 0.006);
}
double can1_vn200_ypr_yaw_decode(uint16_t value)
{
return ((double)value * 0.006);
}
bool can1_vn200_ypr_yaw_is_in_range(uint16_t value)
{
(void)value;
return (true);
}
uint16_t can1_vn200_ypr_pitch_encode(double value)
{
return (uint16_t)(value / 0.006);
}
double can1_vn200_ypr_pitch_decode(uint16_t value)
{
return ((double)value * 0.006);
}
bool can1_vn200_ypr_pitch_is_in_range(uint16_t value)
{
(void)value;
return (true);
}
uint16_t can1_vn200_ypr_roll_encode(double value)
{
return (uint16_t)(value / 0.006);
}
double can1_vn200_ypr_roll_decode(uint16_t value)
{
return ((double)value * 0.006);
}
bool can1_vn200_ypr_roll_is_in_range(uint16_t value)
{
(void)value;
return (true);
}

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#include "canhalal.h"
HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) {
HAL_StatusTypeDef status = HAL_CAN_ActivateNotification(handle, CAN_IT_RX_FIFO0_MSG_PENDING);
if (status != HAL_OK) {
return status;
}
return HAL_CAN_Start(handle);
}
HAL_StatusTypeDef ftcan_transmit(CAN_HandleTypeDef *handle, uint16_t id, const uint8_t *data, size_t datalen) {
static CAN_TxHeaderTypeDef header;
header.StdId = id;
header.IDE = CAN_ID_STD;
header.RTR = CAN_RTR_DATA;
header.DLC = datalen;
uint32_t mailbox;
return HAL_CAN_AddTxMessage(handle, &header, data, &mailbox);
}

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define SPI1_CS_Pin GPIO_PIN_9
#define SPI1_CS_GPIO_Port GPIOA
#define NRST_VN_Pin GPIO_PIN_10
#define NRST_VN_GPIO_Port GPIOA
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */

359
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f3xx_hal_conf.h
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CONF_H
#define __STM32F3xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
#define HAL_CAN_MODULE_ENABLED
/*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_PCCARD_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_HRTIM_MODULE_ENABLED */
/*#define HAL_OPAMP_MODULE_ENABLED */
/*#define HAL_SDADC_MODULE_ENABLED */
/*#define HAL_TSC_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_UART_MODULE_ENABLED */
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)16000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
* Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
* Timeout value
*/
#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
*/
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
* - External clock not generated on EVAL 373
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)15) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 0
#define DATA_CACHE_ENABLE 0
#define USE_SPI_CRC 0U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* OPAMP register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f3xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f3xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f3xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f3xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f3xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f3xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f3xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "stm32f3xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f3xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32f3xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f3xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f3xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f3xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f3xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f3xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f3xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f3xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32f3xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f3xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f3xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f3xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f3xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32f3xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f3xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f3xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f3xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SDADC_MODULE_ENABLED
#include "stm32f3xx_hal_sdadc.h"
#endif /* HAL_SDADC_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f3xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f3xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f3xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f3xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32f3xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f3xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f3xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f3xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CONF_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f3xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_IT_H
#define __STM32F3xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void CAN_RX1_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_IT_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "Converter.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
CAN_HandleTypeDef hcan;
SPI_HandleTypeDef hspi1;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_CAN_Init(void);
static void MX_SPI1_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_CAN_Init();
MX_SPI1_Init();
/* USER CODE BEGIN 2 */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
/*
auto request = vn::pkg_request_read_t(vn::ImuMeasurementsRegisterID);
auto response = vn::pkg_response_t<vn::ImuMeasurementsRegister>();
response.payload.accel.x = 0.0;
response.payload.accel.y = 0.0;
response.payload.accel.z = 0.0;
response.payload.gyro.x = 0.0;
response.payload.gyro.y = 0.0;
response.payload.gyro.z = 0.0;
response.payload.mag.x = 0.0;
response.payload.mag.y = 0.0;
response.payload.mag.z = 0.0;
response.payload.pressure = 0.0;
response.payload.temp = 0.0;
*/
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
spi2can<vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister>(&hspi1, &hcan, vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterID);
HAL_Delay(1);
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief CAN Initialization Function
* @param None
* @retval None
*/
static void MX_CAN_Init(void)
{
/* USER CODE BEGIN CAN_Init 0 */
/* USER CODE END CAN_Init 0 */
/* USER CODE BEGIN CAN_Init 1 */
/* USER CODE END CAN_Init 1 */
hcan.Instance = CAN;
hcan.Init.Prescaler = 8;
hcan.Init.Mode = CAN_MODE_NORMAL;
hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
hcan.Init.TimeSeg1 = CAN_BS1_2TQ;
hcan.Init.TimeSeg2 = CAN_BS2_1TQ;
hcan.Init.TimeTriggeredMode = DISABLE;
hcan.Init.AutoBusOff = DISABLE;
hcan.Init.AutoWakeUp = DISABLE;
hcan.Init.AutoRetransmission = DISABLE;
hcan.Init.ReceiveFifoLocked = DISABLE;
hcan.Init.TransmitFifoPriority = DISABLE;
if (HAL_CAN_Init(&hcan) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN CAN_Init 2 */
/* USER CODE END CAN_Init 2 */
}
/**
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
/* USER CODE BEGIN SPI1_Init 0 */
/* USER CODE END SPI1_Init 0 */
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi1.Init.CRCPolynomial = 7;
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
if (HAL_SPI_Init(&hspi1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, SPI1_CS_Pin|NRST_VN_Pin, GPIO_PIN_SET);
/*Configure GPIO pins : SPI1_CS_Pin NRST_VN_Pin */
GPIO_InitStruct.Pin = SPI1_CS_Pin|NRST_VN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f3xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/**
* @brief CAN MSP Initialization
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hcan->Instance==CAN)
{
/* USER CODE BEGIN CAN_MspInit 0 */
/* USER CODE END CAN_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* CAN interrupt Init */
HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
/* USER CODE BEGIN CAN_MspInit 1 */
/* USER CODE END CAN_MspInit 1 */
}
}
/**
* @brief CAN MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
{
if(hcan->Instance==CAN)
{
/* USER CODE BEGIN CAN_MspDeInit 0 */
/* USER CODE END CAN_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_CAN1_CLK_DISABLE();
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
/* CAN interrupt DeInit */
HAL_NVIC_DisableIRQ(CAN_RX1_IRQn);
/* USER CODE BEGIN CAN_MspDeInit 1 */
/* USER CODE END CAN_MspDeInit 1 */
}
}
/**
* @brief SPI MSP Initialization
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hspi->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
/**
* @brief SPI MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
{
if(hspi->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspDeInit 0 */
/* USER CODE END SPI1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI1_CLK_DISABLE();
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
/* USER CODE BEGIN SPI1_MspDeInit 1 */
/* USER CODE END SPI1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f3xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f3xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern CAN_HandleTypeDef hcan;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32F3xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f3xx.s). */
/******************************************************************************/
/**
* @brief This function handles CAN RX1 interrupt.
*/
void CAN_RX1_IRQHandler(void)
{
/* USER CODE BEGIN CAN_RX1_IRQn 0 */
/* USER CODE END CAN_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
/* USER CODE BEGIN CAN_RX1_IRQn 1 */
/* USER CODE END CAN_RX1_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/**
******************************************************************************
* @file syscalls.c
* @author Auto-generated by STM32CubeIDE
* @brief STM32CubeIDE Minimal System calls file
*
* For more information about which c-functions
* need which of these lowlevel functions
* please consult the Newlib libc-manual
******************************************************************************
* @attention
*
* Copyright (c) 2020-2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <sys/stat.h>
#include <stdlib.h>
#include <errno.h>
#include <stdio.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <sys/times.h>
/* Variables */
extern int __io_putchar(int ch) __attribute__((weak));
extern int __io_getchar(void) __attribute__((weak));
char *__env[1] = { 0 };
char **environ = __env;
/* Functions */
void initialise_monitor_handles()
{
}
int _getpid(void)
{
return 1;
}
int _kill(int pid, int sig)
{
(void)pid;
(void)sig;
errno = EINVAL;
return -1;
}
void _exit (int status)
{
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
return len;
}
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
__io_putchar(*ptr++);
}
return len;
}
int _close(int file)
{
(void)file;
return -1;
}
int _fstat(int file, struct stat *st)
{
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _isatty(int file)
{
(void)file;
return 1;
}
int _lseek(int file, int ptr, int dir)
{
(void)file;
(void)ptr;
(void)dir;
return 0;
}
int _open(char *path, int flags, ...)
{
(void)path;
(void)flags;
/* Pretend like we always fail */
return -1;
}
int _wait(int *status)
{
(void)status;
errno = ECHILD;
return -1;
}
int _unlink(char *name)
{
(void)name;
errno = ENOENT;
return -1;
}
int _times(struct tms *buf)
{
(void)buf;
return -1;
}
int _stat(char *file, struct stat *st)
{
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _link(char *old, char *new)
{
(void)old;
(void)new;
errno = EMLINK;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
}
int _execve(char *name, char **argv, char **env)
{
(void)name;
(void)argv;
(void)env;
errno = ENOMEM;
return -1;
}

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/**
******************************************************************************
* @file sysmem.c
* @author Generated by STM32CubeIDE
* @brief STM32CubeIDE System Memory calls file
*
* For more information about which C functions
* need which of these lowlevel functions
* please consult the newlib libc manual
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <errno.h>
#include <stdint.h>
/**
* Pointer to the current high watermark of the heap usage
*/
static uint8_t *__sbrk_heap_end = NULL;
/**
* @brief _sbrk() allocates memory to the newlib heap and is used by malloc
* and others from the C library
*
* @verbatim
* ############################################################################
* # .data # .bss # newlib heap # MSP stack #
* # # # # Reserved by _Min_Stack_Size #
* ############################################################################
* ^-- RAM start ^-- _end _estack, RAM end --^
* @endverbatim
*
* This implementation starts allocating at the '_end' linker symbol
* The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
* The implementation considers '_estack' linker symbol to be RAM end
* NOTE: If the MSP stack, at any point during execution, grows larger than the
* reserved size, please increase the '_Min_Stack_Size'.
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
const uint8_t *max_heap = (uint8_t *)stack_limit;
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
{
__sbrk_heap_end = &_end;
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
{
errno = ENOMEM;
return (void *)-1;
}
prev_heap_end = __sbrk_heap_end;
__sbrk_heap_end += incr;
return (void *)prev_heap_end;
}

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/**
******************************************************************************
* @file system_stm32f3xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f3xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. This file configures the system clock as follows:
*=============================================================================
* Supported STM32F3xx device
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 8000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 8000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* USB Clock | DISABLE
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f3xx_system
* @{
*/
/** @addtogroup STM32F3xx_System_Private_Includes
* @{
*/
#include "stm32f3xx.h"
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock there is no need to
call the 2 first functions listed above, since SystemCoreClock variable is
updated automatically.
*/
uint32_t SystemCoreClock = 8000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings --------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
{
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
}
else
{
/* HSI oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
}
#else
if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
}
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
break;
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file startup_stm32f302xc.s
* @author MCD Application Team
* @brief STM32F302xB/STM32F302xC devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMP_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TSC_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN_TX_IRQHandler
.word USB_LP_CAN_RX0_IRQHandler
.word CAN_RX1_IRQHandler
.word CAN_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word 0
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word 0
.word COMP1_2_IRQHandler
.word COMP4_6_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TSC_IRQHandler
.thumb_set EXTI2_TSC_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN_TX_IRQHandler
.thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN_RX0_IRQHandler
.thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
.weak CAN_RX1_IRQHandler
.thumb_set CAN_RX1_IRQHandler,Default_Handler
.weak CAN_SCE_IRQHandler
.thumb_set CAN_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak COMP1_2_IRQHandler
.thumb_set COMP1_2_IRQHandler,Default_Handler
.weak COMP4_6_IRQHandler
.thumb_set COMP4_6_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/usr/local/include/vn-interface/helper.h:21:5:vn::header_t::request_t::request_t(uint8_t, uint8_t) 1
/usr/local/include/vn-interface/helper.h:31:5:vn::header_t::response_t::response_t() 1
/usr/local/include/vn-interface/helper.h:45:3:vn::pkg_request_read_t::pkg_request_read_t(uint8_t) 1
/usr/local/include/vn-interface/math/vector.h:28:3:vec3f::vec3f() 1
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:241:5:std::_Function_base::~_Function_base() 2
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:334:11:std::function<void(can1_vn200_ins_t, canlib::frame::decoded::can1::vn200_ins_t)>::~function() 1
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:334:11:std::function<void(can1_vn200_imu_t, canlib::frame::decoded::can1::vn200_imu_t)>::~function() 1
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:334:11:std::function<void(can1_vn200_ypr_t, canlib::frame::decoded::can1::vn200_ypr_t)>::~function() 1
../Core/Src/main.cpp:70:5:int main() 1
../Core/Src/main.cpp:134:6:void SystemClock_Config() 3
../Core/Src/main.cpp:171:13:void MX_CAN_Init() 2
../Core/Src/main.cpp:208:13:void MX_SPI1_Init() 2
../Core/Src/main.cpp:248:13:void MX_GPIO_Init() 1
../Core/Src/main.cpp:280:6:void Error_Handler() 1
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:239:5:constexpr std::_Function_base::_Function_base() 1
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:375:7:)>::function(std::nullptr_t) [with _Res = void; _ArgTypes = {can1_vn200_ins_t, canlib::frame::decoded::can1::vn200_ins_t}] 1
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:375:7:)>::function(std::nullptr_t) [with _Res = void; _ArgTypes = {can1_vn200_imu_t, canlib::frame::decoded::can1::vn200_imu_t}] 1
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:375:7:)>::function(std::nullptr_t) [with _Res = void; _ArgTypes = {can1_vn200_ypr_t, canlib::frame::decoded::can1::vn200_ypr_t}] 1
/usr/local/include/vn-interface/registers.h:826:3:vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister() 1
../Converter/Inc/Converter.h:68:19:HAL_StatusTypeDef spi2can(SPI_HandleTypeDef*, CAN_HandleTypeDef*, const uint16_t&) [with payload_t = vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister] 2
/usr/local/include/vn-interface/helper.h:52:3:vn::pkg_response_t<payload_t>::pkg_response_t() [with payload_t = vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister] 1
../Converter/Inc/Converter.h:12:19:HAL_StatusTypeDef spi_read(SPI_HandleTypeDef*, vn::pkg_request_read_t*, vn::pkg_response_t<payload_t>*) [with payload_t = vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister] 1
../Core/Src/main.cpp:289:1:void __static_initialization_and_destruction_0(int, int) 11
../Core/Src/main.cpp:289:1:cpp) 1
../Core/Src/main.cpp:289:1:cpp) 1

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/usr/local/include/vn-interface/helper.h:21:5:vn::header_t::request_t::request_t(uint8_t, uint8_t) 16 static
/usr/local/include/vn-interface/helper.h:31:5:vn::header_t::response_t::response_t() 16 static
/usr/local/include/vn-interface/helper.h:45:3:vn::pkg_request_read_t::pkg_request_read_t(uint8_t) 16 static
/usr/local/include/vn-interface/math/vector.h:28:3:vec3f::vec3f() 16 static
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:241:5:std::_Function_base::~_Function_base() 16 static
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:334:11:std::function<void(can1_vn200_ins_t, canlib::frame::decoded::can1::vn200_ins_t)>::~function() 16 static
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:334:11:std::function<void(can1_vn200_imu_t, canlib::frame::decoded::can1::vn200_imu_t)>::~function() 16 static
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:334:11:std::function<void(can1_vn200_ypr_t, canlib::frame::decoded::can1::vn200_ypr_t)>::~function() 16 static
../Core/Src/main.cpp:70:5:int main() 8 static
../Core/Src/main.cpp:134:6:void SystemClock_Config() 72 static
../Core/Src/main.cpp:171:13:void MX_CAN_Init() 8 static
../Core/Src/main.cpp:208:13:void MX_SPI1_Init() 8 static
../Core/Src/main.cpp:248:13:void MX_GPIO_Init() 40 static
../Core/Src/main.cpp:280:6:void Error_Handler() 4 static,ignoring_inline_asm
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:239:5:constexpr std::_Function_base::_Function_base() 16 static
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:375:7:)>::function(std::nullptr_t) [with _Res = void; _ArgTypes = {can1_vn200_ins_t, canlib::frame::decoded::can1::vn200_ins_t}] 16 static
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:375:7:)>::function(std::nullptr_t) [with _Res = void; _ArgTypes = {can1_vn200_imu_t, canlib::frame::decoded::can1::vn200_imu_t}] 16 static
/opt/st/stm32cubeide_1.15.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.linux64_1.0.100.202403111256/tools/arm-none-eabi/include/c++/12.3.1/bits/std_function.h:375:7:)>::function(std::nullptr_t) [with _Res = void; _ArgTypes = {can1_vn200_ypr_t, canlib::frame::decoded::can1::vn200_ypr_t}] 16 static
/usr/local/include/vn-interface/registers.h:826:3:vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister() 16 static
../Converter/Inc/Converter.h:68:19:HAL_StatusTypeDef spi2can(SPI_HandleTypeDef*, CAN_HandleTypeDef*, const uint16_t&) [with payload_t = vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister] 128 static
/usr/local/include/vn-interface/helper.h:52:3:vn::pkg_response_t<payload_t>::pkg_response_t() [with payload_t = vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister] 16 static
../Converter/Inc/Converter.h:12:19:HAL_StatusTypeDef spi_read(SPI_HandleTypeDef*, vn::pkg_request_read_t*, vn::pkg_response_t<payload_t>*) [with payload_t = vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister] 80 static
../Core/Src/main.cpp:289:1:void __static_initialization_and_destruction_0(int, int) 16 static
../Core/Src/main.cpp:289:1:cpp) 8 static
../Core/Src/main.cpp:289:1:cpp) 8 static

5
vn200/Debug/Core/Src/stm32f3xx_hal_msp.cyclo Normal file
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@ -0,0 +1,5 @@
../Core/Src/stm32f3xx_hal_msp.c:64:6:HAL_MspInit 1
../Core/Src/stm32f3xx_hal_msp.c:86:6:HAL_CAN_MspInit 2
../Core/Src/stm32f3xx_hal_msp.c:125:6:HAL_CAN_MspDeInit 2
../Core/Src/stm32f3xx_hal_msp.c:156:6:HAL_SPI_MspInit 2
../Core/Src/stm32f3xx_hal_msp.c:193:6:HAL_SPI_MspDeInit 2

5
vn200/Debug/Core/Src/stm32f3xx_hal_msp.su Normal file
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@ -0,0 +1,5 @@
../Core/Src/stm32f3xx_hal_msp.c:64:6:HAL_MspInit 16 static
../Core/Src/stm32f3xx_hal_msp.c:86:6:HAL_CAN_MspInit 48 static
../Core/Src/stm32f3xx_hal_msp.c:125:6:HAL_CAN_MspDeInit 16 static
../Core/Src/stm32f3xx_hal_msp.c:156:6:HAL_SPI_MspInit 48 static
../Core/Src/stm32f3xx_hal_msp.c:193:6:HAL_SPI_MspDeInit 16 static

10
vn200/Debug/Core/Src/stm32f3xx_it.cyclo Normal file
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@ -0,0 +1,10 @@
../Core/Src/stm32f3xx_it.c:69:6:NMI_Handler 1
../Core/Src/stm32f3xx_it.c:84:6:HardFault_Handler 1
../Core/Src/stm32f3xx_it.c:99:6:MemManage_Handler 1
../Core/Src/stm32f3xx_it.c:114:6:BusFault_Handler 1
../Core/Src/stm32f3xx_it.c:129:6:UsageFault_Handler 1
../Core/Src/stm32f3xx_it.c:144:6:SVC_Handler 1
../Core/Src/stm32f3xx_it.c:157:6:DebugMon_Handler 1
../Core/Src/stm32f3xx_it.c:170:6:PendSV_Handler 1
../Core/Src/stm32f3xx_it.c:183:6:SysTick_Handler 1
../Core/Src/stm32f3xx_it.c:204:6:CAN_RX1_IRQHandler 1

10
vn200/Debug/Core/Src/stm32f3xx_it.su Normal file
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@ -0,0 +1,10 @@
../Core/Src/stm32f3xx_it.c:69:6:NMI_Handler 4 static
../Core/Src/stm32f3xx_it.c:84:6:HardFault_Handler 4 static
../Core/Src/stm32f3xx_it.c:99:6:MemManage_Handler 4 static
../Core/Src/stm32f3xx_it.c:114:6:BusFault_Handler 4 static
../Core/Src/stm32f3xx_it.c:129:6:UsageFault_Handler 4 static
../Core/Src/stm32f3xx_it.c:144:6:SVC_Handler 4 static
../Core/Src/stm32f3xx_it.c:157:6:DebugMon_Handler 4 static
../Core/Src/stm32f3xx_it.c:170:6:PendSV_Handler 4 static
../Core/Src/stm32f3xx_it.c:183:6:SysTick_Handler 8 static
../Core/Src/stm32f3xx_it.c:204:6:CAN_RX1_IRQHandler 8 static

48
vn200/Debug/Core/Src/subdir.mk Normal file
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@ -0,0 +1,48 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
CPP_SRCS += \
../Core/Src/main.cpp
C_SRCS += \
../Core/Src/stm32f3xx_hal_msp.c \
../Core/Src/stm32f3xx_it.c \
../Core/Src/syscalls.c \
../Core/Src/sysmem.c \
../Core/Src/system_stm32f3xx.c
C_DEPS += \
./Core/Src/stm32f3xx_hal_msp.d \
./Core/Src/stm32f3xx_it.d \
./Core/Src/syscalls.d \
./Core/Src/sysmem.d \
./Core/Src/system_stm32f3xx.d
OBJS += \
./Core/Src/main.o \
./Core/Src/stm32f3xx_hal_msp.o \
./Core/Src/stm32f3xx_it.o \
./Core/Src/syscalls.o \
./Core/Src/sysmem.o \
./Core/Src/system_stm32f3xx.o
CPP_DEPS += \
./Core/Src/main.d
# Each subdirectory must supply rules for building sources it contributes
Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.cpp Core/Src/subdir.mk
arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F302xC -c -I../Core/Inc -I../Drivers/STM32F3xx_HAL_Driver/Inc -I../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F3xx/Include -I../Drivers/CMSIS/Include -I../Converter/Inc -I/usr/local/include -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F302xC -c -I../Core/Inc -I../Drivers/STM32F3xx_HAL_Driver/Inc -I../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F3xx/Include -I../Drivers/CMSIS/Include -I../Converter/Inc -I/usr/local/include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
clean: clean-Core-2f-Src
clean-Core-2f-Src:
-$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f3xx_hal_msp.cyclo ./Core/Src/stm32f3xx_hal_msp.d ./Core/Src/stm32f3xx_hal_msp.o ./Core/Src/stm32f3xx_hal_msp.su ./Core/Src/stm32f3xx_it.cyclo ./Core/Src/stm32f3xx_it.d ./Core/Src/stm32f3xx_it.o ./Core/Src/stm32f3xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f3xx.cyclo ./Core/Src/system_stm32f3xx.d ./Core/Src/system_stm32f3xx.o ./Core/Src/system_stm32f3xx.su
.PHONY: clean-Core-2f-Src

18
vn200/Debug/Core/Src/syscalls.cyclo Normal file
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@ -0,0 +1,18 @@
../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1
../Core/Src/syscalls.c:48:5:_getpid 1
../Core/Src/syscalls.c:53:5:_kill 1
../Core/Src/syscalls.c:61:6:_exit 1
../Core/Src/syscalls.c:67:27:_read 2
../Core/Src/syscalls.c:80:27:_write 2
../Core/Src/syscalls.c:92:5:_close 1
../Core/Src/syscalls.c:99:5:_fstat 1
../Core/Src/syscalls.c:106:5:_isatty 1
../Core/Src/syscalls.c:112:5:_lseek 1
../Core/Src/syscalls.c:120:5:_open 1
../Core/Src/syscalls.c:128:5:_wait 1
../Core/Src/syscalls.c:135:5:_unlink 1
../Core/Src/syscalls.c:142:5:_times 1
../Core/Src/syscalls.c:148:5:_stat 1
../Core/Src/syscalls.c:155:5:_link 1
../Core/Src/syscalls.c:163:5:_fork 1
../Core/Src/syscalls.c:169:5:_execve 1

18
vn200/Debug/Core/Src/syscalls.su Normal file
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@ -0,0 +1,18 @@
../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static
../Core/Src/syscalls.c:48:5:_getpid 4 static
../Core/Src/syscalls.c:53:5:_kill 16 static
../Core/Src/syscalls.c:61:6:_exit 16 static
../Core/Src/syscalls.c:67:27:_read 32 static
../Core/Src/syscalls.c:80:27:_write 32 static
../Core/Src/syscalls.c:92:5:_close 16 static
../Core/Src/syscalls.c:99:5:_fstat 16 static
../Core/Src/syscalls.c:106:5:_isatty 16 static
../Core/Src/syscalls.c:112:5:_lseek 24 static
../Core/Src/syscalls.c:120:5:_open 12 static
../Core/Src/syscalls.c:128:5:_wait 16 static
../Core/Src/syscalls.c:135:5:_unlink 16 static
../Core/Src/syscalls.c:142:5:_times 16 static
../Core/Src/syscalls.c:148:5:_stat 16 static
../Core/Src/syscalls.c:155:5:_link 16 static
../Core/Src/syscalls.c:163:5:_fork 8 static
../Core/Src/syscalls.c:169:5:_execve 24 static

1
vn200/Debug/Core/Src/sysmem.cyclo Normal file
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@ -0,0 +1 @@
../Core/Src/sysmem.c:53:7:_sbrk 3

1
vn200/Debug/Core/Src/sysmem.su Normal file
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@ -0,0 +1 @@
../Core/Src/sysmem.c:53:7:_sbrk 32 static

2
vn200/Debug/Core/Src/system_stm32f3xx.cyclo Normal file
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@ -0,0 +1,2 @@
../Core/Src/system_stm32f3xx.c:170:6:SystemInit 1
../Core/Src/system_stm32f3xx.c:219:6:SystemCoreClockUpdate 6

2
vn200/Debug/Core/Src/system_stm32f3xx.su Normal file
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@ -0,0 +1,2 @@
../Core/Src/system_stm32f3xx.c:170:6:SystemInit 4 static
../Core/Src/system_stm32f3xx.c:219:6:SystemCoreClockUpdate 24 static

27
vn200/Debug/Core/Startup/subdir.mk Normal file
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@ -0,0 +1,27 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
S_SRCS += \
../Core/Startup/startup_stm32f302cbtx.s
S_DEPS += \
./Core/Startup/startup_stm32f302cbtx.d
OBJS += \
./Core/Startup/startup_stm32f302cbtx.o
# Each subdirectory must supply rules for building sources it contributes
Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
clean: clean-Core-2f-Startup
clean-Core-2f-Startup:
-$(RM) ./Core/Startup/startup_stm32f302cbtx.d ./Core/Startup/startup_stm32f302cbtx.o
.PHONY: clean-Core-2f-Startup

25
vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.cyclo Normal file
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@ -0,0 +1,25 @@
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:138:19:HAL_Init 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:163:19:HAL_DeInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:186:13:HAL_MspInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:197:13:HAL_MspDeInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:220:26:HAL_InitTick 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:278:13:HAL_IncTick 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:289:17:HAL_GetTick 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:298:10:HAL_GetTickPrio 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:307:19:HAL_SetTickFreq 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:340:21:HAL_GetTickFreq 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:356:13:HAL_Delay 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:382:13:HAL_SuspendTick 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:400:13:HAL_ResumeTick 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:411:10:HAL_GetHalVersion 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:420:10:HAL_GetREVID 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:429:10:HAL_GetDEVID 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:438:10:HAL_GetUIDw0 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:447:10:HAL_GetUIDw1 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:456:10:HAL_GetUIDw2 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:465:6:HAL_DBGMCU_EnableDBGSleepMode 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:474:6:HAL_DBGMCU_DisableDBGSleepMode 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:483:6:HAL_DBGMCU_EnableDBGStopMode 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:492:6:HAL_DBGMCU_DisableDBGStopMode 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:501:6:HAL_DBGMCU_EnableDBGStandbyMode 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:510:6:HAL_DBGMCU_DisableDBGStandbyMode 1

25
vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.su Normal file
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@ -0,0 +1,25 @@
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:138:19:HAL_Init 8 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:163:19:HAL_DeInit 8 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:186:13:HAL_MspInit 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:197:13:HAL_MspDeInit 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:220:26:HAL_InitTick 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:278:13:HAL_IncTick 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:289:17:HAL_GetTick 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:298:10:HAL_GetTickPrio 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:307:19:HAL_SetTickFreq 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:340:21:HAL_GetTickFreq 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:356:13:HAL_Delay 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:382:13:HAL_SuspendTick 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:400:13:HAL_ResumeTick 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:411:10:HAL_GetHalVersion 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:420:10:HAL_GetREVID 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:429:10:HAL_GetDEVID 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:438:10:HAL_GetUIDw0 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:447:10:HAL_GetUIDw1 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:456:10:HAL_GetUIDw2 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:465:6:HAL_DBGMCU_EnableDBGSleepMode 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:474:6:HAL_DBGMCU_DisableDBGSleepMode 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:483:6:HAL_DBGMCU_EnableDBGStopMode 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:492:6:HAL_DBGMCU_DisableDBGStopMode 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:501:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c:510:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static

36
vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.cyclo Normal file
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@ -0,0 +1,36 @@
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:274:19:HAL_CAN_Init 13
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:459:19:HAL_CAN_DeInit 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:506:13:HAL_CAN_MspInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:522:13:HAL_CAN_MspDeInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:839:19:HAL_CAN_ConfigFilter 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:989:19:HAL_CAN_Start 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1041:19:HAL_CAN_Stop 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1096:19:HAL_CAN_RequestSleep 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1127:19:HAL_CAN_WakeUp 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1176:10:HAL_CAN_IsSleepActive 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1207:19:HAL_CAN_AddTxMessage 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1307:19:HAL_CAN_AbortTxRequest 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1356:10:HAL_CAN_GetTxMailboxesFreeLevel 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1399:10:HAL_CAN_IsTxMessagePending 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1431:10:HAL_CAN_GetTxTimestamp 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1465:19:HAL_CAN_GetRxMessage 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1565:10:HAL_CAN_GetRxFifoFillLevel 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1618:19:HAL_CAN_ActivateNotification 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1651:19:HAL_CAN_DeactivateNotification 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1682:6:HAL_CAN_IRQHandler 51
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2093:13:HAL_CAN_TxMailbox0CompleteCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2110:13:HAL_CAN_TxMailbox1CompleteCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2127:13:HAL_CAN_TxMailbox2CompleteCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2144:13:HAL_CAN_TxMailbox0AbortCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2161:13:HAL_CAN_TxMailbox1AbortCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2178:13:HAL_CAN_TxMailbox2AbortCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2195:13:HAL_CAN_RxFifo0MsgPendingCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2212:13:HAL_CAN_RxFifo0FullCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2229:13:HAL_CAN_RxFifo1MsgPendingCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2246:13:HAL_CAN_RxFifo1FullCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2263:13:HAL_CAN_SleepCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2279:13:HAL_CAN_WakeUpFromRxMsgCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2296:13:HAL_CAN_ErrorCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2333:22:HAL_CAN_GetState 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2368:10:HAL_CAN_GetError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2380:19:HAL_CAN_ResetError 3

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:274:19:HAL_CAN_Init 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:459:19:HAL_CAN_DeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:506:13:HAL_CAN_MspInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:522:13:HAL_CAN_MspDeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:839:19:HAL_CAN_ConfigFilter 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:989:19:HAL_CAN_Start 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1041:19:HAL_CAN_Stop 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1096:19:HAL_CAN_RequestSleep 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1127:19:HAL_CAN_WakeUp 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1176:10:HAL_CAN_IsSleepActive 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1207:19:HAL_CAN_AddTxMessage 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1307:19:HAL_CAN_AbortTxRequest 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1356:10:HAL_CAN_GetTxMailboxesFreeLevel 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1399:10:HAL_CAN_IsTxMessagePending 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1431:10:HAL_CAN_GetTxTimestamp 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1465:19:HAL_CAN_GetRxMessage 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1565:10:HAL_CAN_GetRxFifoFillLevel 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1618:19:HAL_CAN_ActivateNotification 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1651:19:HAL_CAN_DeactivateNotification 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:1682:6:HAL_CAN_IRQHandler 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2093:13:HAL_CAN_TxMailbox0CompleteCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2110:13:HAL_CAN_TxMailbox1CompleteCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2127:13:HAL_CAN_TxMailbox2CompleteCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2144:13:HAL_CAN_TxMailbox0AbortCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2161:13:HAL_CAN_TxMailbox1AbortCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2178:13:HAL_CAN_TxMailbox2AbortCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2195:13:HAL_CAN_RxFifo0MsgPendingCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2212:13:HAL_CAN_RxFifo0FullCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2229:13:HAL_CAN_RxFifo1MsgPendingCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2246:13:HAL_CAN_RxFifo1FullCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2263:13:HAL_CAN_SleepCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2279:13:HAL_CAN_WakeUpFromRxMsgCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2296:13:HAL_CAN_ErrorCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2333:22:HAL_CAN_GetState 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2368:10:HAL_CAN_GetError 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c:2380:19:HAL_CAN_ResetError 24 static

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../Drivers/CMSIS/Include/core_cm4.h:1657:22:__NVIC_SetPriorityGrouping 1
../Drivers/CMSIS/Include/core_cm4.h:1676:26:__NVIC_GetPriorityGrouping 1
../Drivers/CMSIS/Include/core_cm4.h:1688:22:__NVIC_EnableIRQ 2
../Drivers/CMSIS/Include/core_cm4.h:1724:22:__NVIC_DisableIRQ 2
../Drivers/CMSIS/Include/core_cm4.h:1743:26:__NVIC_GetPendingIRQ 2
../Drivers/CMSIS/Include/core_cm4.h:1762:22:__NVIC_SetPendingIRQ 2
../Drivers/CMSIS/Include/core_cm4.h:1777:22:__NVIC_ClearPendingIRQ 2
../Drivers/CMSIS/Include/core_cm4.h:1794:26:__NVIC_GetActive 2
../Drivers/CMSIS/Include/core_cm4.h:1816:22:__NVIC_SetPriority 2
../Drivers/CMSIS/Include/core_cm4.h:1838:26:__NVIC_GetPriority 2
../Drivers/CMSIS/Include/core_cm4.h:1863:26:NVIC_EncodePriority 2
../Drivers/CMSIS/Include/core_cm4.h:1890:22:NVIC_DecodePriority 2
../Drivers/CMSIS/Include/core_cm4.h:1939:34:__NVIC_SystemReset 1
../Drivers/CMSIS/Include/core_cm4.h:2022:26:SysTick_Config 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:168:6:HAL_NVIC_SetPriorityGrouping 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:190:6:HAL_NVIC_SetPriority 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:212:6:HAL_NVIC_EnableIRQ 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:228:6:HAL_NVIC_DisableIRQ 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:241:6:HAL_NVIC_SystemReset 0
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:254:10:HAL_SYSTICK_Config 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:284:6:HAL_MPU_Disable 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:304:6:HAL_MPU_Enable 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:319:6:HAL_MPU_ConfigRegion 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:363:10:HAL_NVIC_GetPriorityGrouping 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:390:6:HAL_NVIC_GetPriority 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:405:6:HAL_NVIC_SetPendingIRQ 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:420:10:HAL_NVIC_GetPendingIRQ 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:433:6:HAL_NVIC_ClearPendingIRQ 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:447:10:HAL_NVIC_GetActive 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:461:6:HAL_SYSTICK_CLKSourceConfig 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:479:6:HAL_SYSTICK_IRQHandler 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:488:13:HAL_SYSTICK_Callback 1

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../Drivers/CMSIS/Include/core_cm4.h:1657:22:__NVIC_SetPriorityGrouping 24 static
../Drivers/CMSIS/Include/core_cm4.h:1676:26:__NVIC_GetPriorityGrouping 4 static
../Drivers/CMSIS/Include/core_cm4.h:1688:22:__NVIC_EnableIRQ 16 static
../Drivers/CMSIS/Include/core_cm4.h:1724:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm
../Drivers/CMSIS/Include/core_cm4.h:1743:26:__NVIC_GetPendingIRQ 16 static
../Drivers/CMSIS/Include/core_cm4.h:1762:22:__NVIC_SetPendingIRQ 16 static
../Drivers/CMSIS/Include/core_cm4.h:1777:22:__NVIC_ClearPendingIRQ 16 static
../Drivers/CMSIS/Include/core_cm4.h:1794:26:__NVIC_GetActive 16 static
../Drivers/CMSIS/Include/core_cm4.h:1816:22:__NVIC_SetPriority 16 static
../Drivers/CMSIS/Include/core_cm4.h:1838:26:__NVIC_GetPriority 16 static
../Drivers/CMSIS/Include/core_cm4.h:1863:26:NVIC_EncodePriority 40 static
../Drivers/CMSIS/Include/core_cm4.h:1890:22:NVIC_DecodePriority 40 static
../Drivers/CMSIS/Include/core_cm4.h:1939:34:__NVIC_SystemReset 4 static,ignoring_inline_asm
../Drivers/CMSIS/Include/core_cm4.h:2022:26:SysTick_Config 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:168:6:HAL_NVIC_SetPriorityGrouping 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:190:6:HAL_NVIC_SetPriority 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:212:6:HAL_NVIC_EnableIRQ 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:228:6:HAL_NVIC_DisableIRQ 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:241:6:HAL_NVIC_SystemReset 8 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:254:10:HAL_SYSTICK_Config 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:284:6:HAL_MPU_Disable 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:304:6:HAL_MPU_Enable 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:319:6:HAL_MPU_ConfigRegion 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:363:10:HAL_NVIC_GetPriorityGrouping 8 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:390:6:HAL_NVIC_GetPriority 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:405:6:HAL_NVIC_SetPendingIRQ 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:420:10:HAL_NVIC_GetPendingIRQ 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:433:6:HAL_NVIC_ClearPendingIRQ 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:447:10:HAL_NVIC_GetActive 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:461:6:HAL_SYSTICK_CLKSourceConfig 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:479:6:HAL_SYSTICK_IRQHandler 8 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c:488:13:HAL_SYSTICK_Callback 4 static

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:136:19:HAL_DMA_Init 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:198:19:HAL_DMA_DeInit 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:280:19:HAL_DMA_Start 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:327:19:HAL_DMA_Start_IT 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:383:19:HAL_DMA_Abort 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:421:19:HAL_DMA_Abort_IT 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:467:19:HAL_DMA_PollForTransfer 10
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:568:6:HAL_DMA_IRQHandler 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:660:19:HAL_DMA_RegisterCallback 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:711:19:HAL_DMA_UnRegisterCallback 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:787:22:HAL_DMA_GetState 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:798:10:HAL_DMA_GetError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:824:13:DMA_SetConfig 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:858:13:DMA_CalcBaseAndBitshift 2

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:136:19:HAL_DMA_Init 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:198:19:HAL_DMA_DeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:280:19:HAL_DMA_Start 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:327:19:HAL_DMA_Start_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:383:19:HAL_DMA_Abort 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:421:19:HAL_DMA_Abort_IT 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:467:19:HAL_DMA_PollForTransfer 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:568:6:HAL_DMA_IRQHandler 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:660:19:HAL_DMA_RegisterCallback 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:711:19:HAL_DMA_UnRegisterCallback 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:787:22:HAL_DMA_GetState 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:798:10:HAL_DMA_GetError 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:824:13:DMA_SetConfig 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:858:13:DMA_CalcBaseAndBitshift 16 static

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:264:19:HAL_EXTI_GetConfigLine 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:357:19:HAL_EXTI_ClearConfigLine 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:422:19:HAL_EXTI_RegisterCallback 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:447:19:HAL_EXTI_GetHandle 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:487:6:HAL_EXTI_IRQHandler 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:524:10:HAL_EXTI_GetPending 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:558:6:HAL_EXTI_ClearPending 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:585:6:HAL_EXTI_GenerateSWI 1

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:264:19:HAL_EXTI_GetConfigLine 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:357:19:HAL_EXTI_ClearConfigLine 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:422:19:HAL_EXTI_RegisterCallback 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:447:19:HAL_EXTI_GetHandle 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:487:6:HAL_EXTI_IRQHandler 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:524:10:HAL_EXTI_GetPending 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:558:6:HAL_EXTI_ClearPending 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:585:6:HAL_EXTI_GenerateSWI 32 static

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:166:19:HAL_FLASH_Program 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:238:19:HAL_FLASH_Program_IT 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:284:6:HAL_FLASH_IRQHandler 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:427:13:HAL_FLASH_EndOfOperationCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:445:13:HAL_FLASH_OperationErrorCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:478:19:HAL_FLASH_Unlock 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:502:19:HAL_FLASH_Lock 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:514:19:HAL_FLASH_OB_Unlock 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:534:19:HAL_FLASH_OB_Lock 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:547:19:HAL_FLASH_OB_Launch 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:579:10:HAL_FLASH_GetError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:602:13:FLASH_Program_HalfWord 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:619:19:FLASH_WaitForLastOperation 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:662:13:FLASH_SetErrorCode 3

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:166:19:HAL_FLASH_Program 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:238:19:HAL_FLASH_Program_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:284:6:HAL_FLASH_IRQHandler 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:427:13:HAL_FLASH_EndOfOperationCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:445:13:HAL_FLASH_OperationErrorCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:478:19:HAL_FLASH_Unlock 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:502:19:HAL_FLASH_Lock 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:514:19:HAL_FLASH_OB_Unlock 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:534:19:HAL_FLASH_OB_Lock 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:547:19:HAL_FLASH_OB_Launch 8 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:579:10:HAL_FLASH_GetError 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:602:13:FLASH_Program_HalfWord 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:619:19:FLASH_WaitForLastOperation 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c:662:13:FLASH_SetErrorCode 16 static

16
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:157:19:HAL_FLASHEx_Erase 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:238:19:HAL_FLASHEx_Erase_IT 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:311:19:HAL_FLASHEx_OBErase 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:360:19:HAL_FLASHEx_OBProgram 11
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:441:6:HAL_FLASHEx_OBGetConfig 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:463:10:HAL_FLASHEx_OBGetUserData 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:498:13:FLASH_MassErase 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:519:26:FLASH_OB_EnableWRP 10
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:631:26:FLASH_OB_DisableWRP 10
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:741:26:FLASH_OB_RDP_LevelConfig 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:792:26:FLASH_OB_UserConfig 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:846:26:FLASH_OB_ProgramData 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:879:17:FLASH_OB_GetWRP 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:893:17:FLASH_OB_GetRDP 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:928:16:FLASH_OB_GetUser 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:957:6:FLASH_PageErase 1

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:157:19:HAL_FLASHEx_Erase 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:238:19:HAL_FLASHEx_Erase_IT 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:311:19:HAL_FLASHEx_OBErase 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:360:19:HAL_FLASHEx_OBProgram 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:441:6:HAL_FLASHEx_OBGetConfig 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:463:10:HAL_FLASHEx_OBGetUserData 40 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:498:13:FLASH_MassErase 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:519:26:FLASH_OB_EnableWRP 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:631:26:FLASH_OB_DisableWRP 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:741:26:FLASH_OB_RDP_LevelConfig 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:792:26:FLASH_OB_UserConfig 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:846:26:FLASH_OB_ProgramData 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:879:17:FLASH_OB_GetWRP 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:893:17:FLASH_OB_GetRDP 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:928:16:FLASH_OB_GetUser 16 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c:957:6:FLASH_PageErase 16 static

8
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:171:6:HAL_GPIO_Init 17
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:301:6:HAL_GPIO_DeInit 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:383:15:HAL_GPIO_ReadPin 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:417:6:HAL_GPIO_WritePin 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:439:6:HAL_GPIO_TogglePin 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:464:19:HAL_GPIO_LockPin 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:499:6:HAL_GPIO_EXTI_IRQHandler 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:514:13:HAL_GPIO_EXTI_Callback 1

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:171:6:HAL_GPIO_Init 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:301:6:HAL_GPIO_DeInit 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:383:15:HAL_GPIO_ReadPin 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:417:6:HAL_GPIO_WritePin 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:439:6:HAL_GPIO_TogglePin 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:464:19:HAL_GPIO_LockPin 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:499:6:HAL_GPIO_EXTI_IRQHandler 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c:514:13:HAL_GPIO_EXTI_Callback 16 static

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:535:19:HAL_I2C_Init 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:645:19:HAL_I2C_DeInit 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:691:13:HAL_I2C_MspInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:707:13:HAL_I2C_MspDeInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1114:19:HAL_I2C_Master_Transmit 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1233:19:HAL_I2C_Master_Receive 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1351:19:HAL_I2C_Slave_Transmit 15
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1507:19:HAL_I2C_Slave_Receive 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1637:19:HAL_I2C_Master_Transmit_IT 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1708:19:HAL_I2C_Master_Receive_IT 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1777:19:HAL_I2C_Slave_Transmit_IT 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1841:19:HAL_I2C_Slave_Receive_IT 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1893:19:HAL_I2C_Master_Transmit_DMA 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2040:19:HAL_I2C_Master_Receive_DMA 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2185:19:HAL_I2C_Slave_Transmit_DMA 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2321:19:HAL_I2C_Slave_Receive_DMA 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2430:19:HAL_I2C_Mem_Write 15
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2567:19:HAL_I2C_Mem_Read 15
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2704:19:HAL_I2C_Mem_Write_IT 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2791:19:HAL_I2C_Mem_Read_IT 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2878:19:HAL_I2C_Mem_Write_DMA 10
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3024:19:HAL_I2C_Mem_Read_DMA 10
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3169:19:HAL_I2C_IsDeviceReady 16
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3311:19:HAL_I2C_Master_Seq_Transmit_IT 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3402:19:HAL_I2C_Master_Seq_Transmit_DMA 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3570:19:HAL_I2C_Master_Seq_Receive_IT 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3657:19:HAL_I2C_Master_Seq_Receive_DMA 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3823:19:HAL_I2C_Slave_Seq_Transmit_IT 11
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3923:19:HAL_I2C_Slave_Seq_Transmit_DMA 17
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4107:19:HAL_I2C_Slave_Seq_Receive_IT 11
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4207:19:HAL_I2C_Slave_Seq_Receive_DMA 17
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4387:19:HAL_I2C_EnableListen_IT 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4411:19:HAL_I2C_DisableListen_IT 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4444:19:HAL_I2C_Master_Abort_IT 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4506:6:HAL_I2C_EV_IRQHandler 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4525:6:HAL_I2C_ER_IRQHandler 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4577:13:HAL_I2C_MasterTxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4593:13:HAL_I2C_MasterRxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4608:13:HAL_I2C_SlaveTxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4624:13:HAL_I2C_SlaveRxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4642:13:HAL_I2C_AddrCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4660:13:HAL_I2C_ListenCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4676:13:HAL_I2C_MemTxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4692:13:HAL_I2C_MemRxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4708:13:HAL_I2C_ErrorCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4724:13:HAL_I2C_AbortCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4759:22:HAL_I2C_GetState 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4771:21:HAL_I2C_GetMode 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4782:10:HAL_I2C_GetError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4807:26:I2C_Master_ISR_IT 22
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4953:26:I2C_Mem_ISR_IT 20
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5090:26:I2C_Slave_ISR_IT 25
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5231:26:I2C_Master_ISR_DMA 18
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5371:26:I2C_Mem_ISR_DMA 18
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5510:26:I2C_Slave_ISR_DMA 27
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5655:26:I2C_RequestMemoryWrite 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5710:26:I2C_RequestMemoryRead 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5759:13:I2C_ITAddrCplt 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5854:13:I2C_ITMasterSeqCplt 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5907:13:I2C_ITSlaveSeqCplt 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5981:13:I2C_ITMasterCplt 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6124:13:I2C_ITSlaveCplt 16
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6283:13:I2C_ITListenCplt 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6334:13:I2C_ITError 19
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6465:13:I2C_TreatErrorCallback 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6503:13:I2C_Flush_TXDR 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6524:13:I2C_DMAMasterTransmitCplt 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6575:13:I2C_DMASlaveTransmitCplt 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6604:13:I2C_DMAMasterReceiveCplt 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6655:13:I2C_DMASlaveReceiveCplt 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6684:13:I2C_DMAError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6703:13:I2C_DMAAbort 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6733:26:I2C_WaitOnFlagUntilTimeout 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6767:26:I2C_WaitOnTXISFlagUntilTimeout 7
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6808:26:I2C_WaitOnSTOPFlagUntilTimeout 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6846:26:I2C_WaitOnRXNEFlagUntilTimeout 10
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6922:26:I2C_IsErrorOccurred 17
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:7063:13:I2C_TransferConfig 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:7090:13:I2C_Enable_IRQ 16
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:7181:13:I2C_Disable_IRQ 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:7244:13:I2C_ConvertOtherXferOptions 3

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:535:19:HAL_I2C_Init 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:645:19:HAL_I2C_DeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:691:13:HAL_I2C_MspInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:707:13:HAL_I2C_MspDeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1114:19:HAL_I2C_Master_Transmit 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1233:19:HAL_I2C_Master_Receive 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1351:19:HAL_I2C_Slave_Transmit 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1507:19:HAL_I2C_Slave_Receive 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1637:19:HAL_I2C_Master_Transmit_IT 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1708:19:HAL_I2C_Master_Receive_IT 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1777:19:HAL_I2C_Slave_Transmit_IT 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1841:19:HAL_I2C_Slave_Receive_IT 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:1893:19:HAL_I2C_Master_Transmit_DMA 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2040:19:HAL_I2C_Master_Receive_DMA 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2185:19:HAL_I2C_Slave_Transmit_DMA 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2321:19:HAL_I2C_Slave_Receive_DMA 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2430:19:HAL_I2C_Mem_Write 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2567:19:HAL_I2C_Mem_Read 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2704:19:HAL_I2C_Mem_Write_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2791:19:HAL_I2C_Mem_Read_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:2878:19:HAL_I2C_Mem_Write_DMA 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3024:19:HAL_I2C_Mem_Read_DMA 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3169:19:HAL_I2C_IsDeviceReady 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3311:19:HAL_I2C_Master_Seq_Transmit_IT 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3402:19:HAL_I2C_Master_Seq_Transmit_DMA 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3570:19:HAL_I2C_Master_Seq_Receive_IT 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3657:19:HAL_I2C_Master_Seq_Receive_DMA 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3823:19:HAL_I2C_Slave_Seq_Transmit_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:3923:19:HAL_I2C_Slave_Seq_Transmit_DMA 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4107:19:HAL_I2C_Slave_Seq_Receive_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4207:19:HAL_I2C_Slave_Seq_Receive_DMA 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4387:19:HAL_I2C_EnableListen_IT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4411:19:HAL_I2C_DisableListen_IT 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4444:19:HAL_I2C_Master_Abort_IT 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4506:6:HAL_I2C_EV_IRQHandler 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4525:6:HAL_I2C_ER_IRQHandler 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4577:13:HAL_I2C_MasterTxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4593:13:HAL_I2C_MasterRxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4608:13:HAL_I2C_SlaveTxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4624:13:HAL_I2C_SlaveRxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4642:13:HAL_I2C_AddrCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4660:13:HAL_I2C_ListenCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4676:13:HAL_I2C_MemTxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4692:13:HAL_I2C_MemRxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4708:13:HAL_I2C_ErrorCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4724:13:HAL_I2C_AbortCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4759:22:HAL_I2C_GetState 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4771:21:HAL_I2C_GetMode 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4782:10:HAL_I2C_GetError 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4807:26:I2C_Master_ISR_IT 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:4953:26:I2C_Mem_ISR_IT 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5090:26:I2C_Slave_ISR_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5231:26:I2C_Master_ISR_DMA 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5371:26:I2C_Mem_ISR_DMA 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5510:26:I2C_Slave_ISR_DMA 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5655:26:I2C_RequestMemoryWrite 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5710:26:I2C_RequestMemoryRead 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5759:13:I2C_ITAddrCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5854:13:I2C_ITMasterSeqCplt 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5907:13:I2C_ITSlaveSeqCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:5981:13:I2C_ITMasterCplt 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6124:13:I2C_ITSlaveCplt 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6283:13:I2C_ITListenCplt 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6334:13:I2C_ITError 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6465:13:I2C_TreatErrorCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6503:13:I2C_Flush_TXDR 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6524:13:I2C_DMAMasterTransmitCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6575:13:I2C_DMASlaveTransmitCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6604:13:I2C_DMAMasterReceiveCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6655:13:I2C_DMASlaveReceiveCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6684:13:I2C_DMAError 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6703:13:I2C_DMAAbort 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6733:26:I2C_WaitOnFlagUntilTimeout 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6767:26:I2C_WaitOnTXISFlagUntilTimeout 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6808:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6846:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:6922:26:I2C_IsErrorOccurred 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:7063:13:I2C_TransferConfig 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:7090:13:I2C_Enable_IRQ 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:7181:13:I2C_Disable_IRQ 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c:7244:13:I2C_ConvertOtherXferOptions 16 static

6
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:96:19:HAL_I2CEx_ConfigAnalogFilter 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:140:19:HAL_I2CEx_ConfigDigitalFilter 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:208:19:HAL_I2CEx_EnableWakeUp 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:247:19:HAL_I2CEx_DisableWakeUp 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:312:6:HAL_I2CEx_EnableFastModePlus 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:339:6:HAL_I2CEx_DisableFastModePlus 1

6
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:96:19:HAL_I2CEx_ConfigAnalogFilter 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:140:19:HAL_I2CEx_ConfigDigitalFilter 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:208:19:HAL_I2CEx_EnableWakeUp 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:247:19:HAL_I2CEx_DisableWakeUp 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:312:6:HAL_I2CEx_EnableFastModePlus 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c:339:6:HAL_I2CEx_DisableFastModePlus 24 static

12
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:73:6:HAL_PWR_DeInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:86:6:HAL_PWR_EnableBkUpAccess 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:98:6:HAL_PWR_DisableBkUpAccess 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:241:6:HAL_PWR_EnableWakeUpPin 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:256:6:HAL_PWR_DisableWakeUpPin 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:281:6:HAL_PWR_EnterSLEEPMode 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:323:6:HAL_PWR_EnterSTOPMode 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:373:6:HAL_PWR_EnterSTANDBYMode 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:397:6:HAL_PWR_EnableSleepOnExit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:410:6:HAL_PWR_DisableSleepOnExit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:424:6:HAL_PWR_EnableSEVOnPend 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:437:6:HAL_PWR_DisableSEVOnPend 1

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vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.su Normal file
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:73:6:HAL_PWR_DeInit 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:86:6:HAL_PWR_EnableBkUpAccess 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:98:6:HAL_PWR_DisableBkUpAccess 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:241:6:HAL_PWR_EnableWakeUpPin 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:256:6:HAL_PWR_DisableWakeUpPin 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:281:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:323:6:HAL_PWR_EnterSTOPMode 24 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:373:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:397:6:HAL_PWR_EnableSleepOnExit 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:410:6:HAL_PWR_DisableSleepOnExit 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:424:6:HAL_PWR_EnableSEVOnPend 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c:437:6:HAL_PWR_DisableSEVOnPend 4 static

5
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:128:6:HAL_PWR_ConfigPVD 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:170:6:HAL_PWR_EnablePVD 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:179:6:HAL_PWR_DisablePVD 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:189:6:HAL_PWR_PVD_IRQHandler 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:206:13:HAL_PWR_PVDCallback 1

5
vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.su Normal file
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:128:6:HAL_PWR_ConfigPVD 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:170:6:HAL_PWR_EnablePVD 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:179:6:HAL_PWR_DisablePVD 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:189:6:HAL_PWR_PVD_IRQHandler 8 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c:206:13:HAL_PWR_PVDCallback 4 static

14
vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.cyclo Normal file
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:214:19:HAL_RCC_DeInit 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:314:19:HAL_RCC_OscConfig 70
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:694:19:HAL_RCC_ClockConfig 20
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:886:6:HAL_RCC_MCOConfig 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:920:6:HAL_RCC_EnableCSS 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:929:6:HAL_RCC_DisableCSS 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:963:10:HAL_RCC_GetSysClockFreq 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1027:10:HAL_RCC_GetHCLKFreq 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1038:10:HAL_RCC_GetPCLK1Freq 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1050:10:HAL_RCC_GetPCLK2Freq 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1063:6:HAL_RCC_GetOscConfig 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1151:6:HAL_RCC_GetClockConfig 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1181:6:HAL_RCC_NMI_IRQHandler 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1198:13:HAL_RCC_CSSCallback 1

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:214:19:HAL_RCC_DeInit 24 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:314:19:HAL_RCC_OscConfig 520 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:694:19:HAL_RCC_ClockConfig 128 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:886:6:HAL_RCC_MCOConfig 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:920:6:HAL_RCC_EnableCSS 16 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:929:6:HAL_RCC_DisableCSS 16 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:963:10:HAL_RCC_GetSysClockFreq 48 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1027:10:HAL_RCC_GetHCLKFreq 4 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1038:10:HAL_RCC_GetPCLK1Freq 16 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1050:10:HAL_RCC_GetPCLK2Freq 16 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1063:6:HAL_RCC_GetOscConfig 24 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1151:6:HAL_RCC_GetClockConfig 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1181:6:HAL_RCC_NMI_IRQHandler 8 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c:1198:13:HAL_RCC_CSSCallback 4 static

4
vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.cyclo Normal file
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c:105:19:HAL_RCCEx_PeriphCLKConfig 24
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c:573:6:HAL_RCCEx_GetPeriphCLKConfig 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c:944:10:HAL_RCCEx_GetPeriphCLKFreq 71
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c:1531:17:RCC_GetPLLCLKFreq 2

4
vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.su Normal file
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c:105:19:HAL_RCCEx_PeriphCLKConfig 80 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c:573:6:HAL_RCCEx_GetPeriphCLKConfig 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c:944:10:HAL_RCCEx_GetPeriphCLKFreq 32 static,ignoring_inline_asm
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c:1531:17:RCC_GetPLLCLKFreq 24 static

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vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.cyclo Normal file
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:314:19:HAL_SPI_Init 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:489:19:HAL_SPI_DeInit 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:533:13:HAL_SPI_MspInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:549:13:HAL_SPI_MspDeInit 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:821:19:HAL_SPI_Transmit 27
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1011:19:HAL_SPI_Receive 23
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1256:19:HAL_SPI_TransmitReceive 43
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1575:19:HAL_SPI_Transmit_IT 8
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1660:19:HAL_SPI_Receive_IT 10
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1768:19:HAL_SPI_TransmitReceive_IT 14
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1877:19:HAL_SPI_Transmit_DMA 11
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2001:19:HAL_SPI_Receive_DMA 15
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2154:19:HAL_SPI_TransmitReceive_DMA 21
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2354:19:HAL_SPI_Abort 18
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2514:19:HAL_SPI_Abort_IT 19
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2675:19:HAL_SPI_DMAPause 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2695:19:HAL_SPI_DMAResume 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2715:19:HAL_SPI_DMAStop 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2755:6:HAL_SPI_IRQHandler 21
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2862:13:HAL_SPI_TxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2878:13:HAL_SPI_RxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2894:13:HAL_SPI_TxRxCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2910:13:HAL_SPI_TxHalfCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2926:13:HAL_SPI_RxHalfCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2942:13:HAL_SPI_TxRxHalfCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2958:13:HAL_SPI_ErrorCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2976:13:HAL_SPI_AbortCpltCallback 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3011:22:HAL_SPI_GetState 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3023:10:HAL_SPI_GetError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3048:13:SPI_DMATransmitCplt 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3105:13:SPI_DMAReceiveCplt 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3222:13:SPI_DMATransmitReceiveCplt 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3322:13:SPI_DMAHalfTransmitCplt 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3340:13:SPI_DMAHalfReceiveCplt 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3358:13:SPI_DMAHalfTransmitReceiveCplt 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3376:13:SPI_DMAError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3399:13:SPI_DMAAbortOnError 1
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3421:13:SPI_DMATxAbortCallback 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3487:13:SPI_DMARxAbortCallback 6
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3552:13:SPI_2linesRxISR_8BIT 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3637:13:SPI_2linesTxISR_8BIT 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3684:13:SPI_2linesRxISR_16BIT 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3740:13:SPI_2linesTxISR_16BIT 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3805:13:SPI_RxISR_8BIT 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3861:13:SPI_RxISR_16BIT 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3894:13:SPI_TxISR_8BIT 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3919:13:SPI_TxISR_16BIT 2
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3949:26:SPI_WaitFlagStateUntilTimeout 10
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4018:26:SPI_WaitFifoStateUntilTimeout 12
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4098:26:SPI_EndRxTransaction 9
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4134:26:SPI_EndRxTxTransaction 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4166:13:SPI_CloseRxTx_ISR 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4243:13:SPI_CloseRx_ISR 3
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4300:13:SPI_CloseTx_ISR 4
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4349:13:SPI_AbortRx_ISR 5
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4393:13:SPI_AbortTx_ISR 10

56
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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:314:19:HAL_SPI_Init 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:489:19:HAL_SPI_DeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:533:13:HAL_SPI_MspInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:549:13:HAL_SPI_MspDeInit 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:821:19:HAL_SPI_Transmit 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1011:19:HAL_SPI_Receive 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1256:19:HAL_SPI_TransmitReceive 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1575:19:HAL_SPI_Transmit_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1660:19:HAL_SPI_Receive_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1768:19:HAL_SPI_TransmitReceive_IT 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:1877:19:HAL_SPI_Transmit_DMA 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2001:19:HAL_SPI_Receive_DMA 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2154:19:HAL_SPI_TransmitReceive_DMA 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2354:19:HAL_SPI_Abort 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2514:19:HAL_SPI_Abort_IT 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2675:19:HAL_SPI_DMAPause 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2695:19:HAL_SPI_DMAResume 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2715:19:HAL_SPI_DMAStop 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2755:6:HAL_SPI_IRQHandler 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2862:13:HAL_SPI_TxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2878:13:HAL_SPI_RxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2894:13:HAL_SPI_TxRxCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2910:13:HAL_SPI_TxHalfCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2926:13:HAL_SPI_RxHalfCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2942:13:HAL_SPI_TxRxHalfCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2958:13:HAL_SPI_ErrorCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:2976:13:HAL_SPI_AbortCpltCallback 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3011:22:HAL_SPI_GetState 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3023:10:HAL_SPI_GetError 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3048:13:SPI_DMATransmitCplt 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3105:13:SPI_DMAReceiveCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3222:13:SPI_DMATransmitReceiveCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3322:13:SPI_DMAHalfTransmitCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3340:13:SPI_DMAHalfReceiveCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3358:13:SPI_DMAHalfTransmitReceiveCplt 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3376:13:SPI_DMAError 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3399:13:SPI_DMAAbortOnError 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3421:13:SPI_DMATxAbortCallback 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3487:13:SPI_DMARxAbortCallback 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3552:13:SPI_2linesRxISR_8BIT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3637:13:SPI_2linesTxISR_8BIT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3684:13:SPI_2linesRxISR_16BIT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3740:13:SPI_2linesTxISR_16BIT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3805:13:SPI_RxISR_8BIT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3861:13:SPI_RxISR_16BIT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3894:13:SPI_TxISR_8BIT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3919:13:SPI_TxISR_16BIT 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:3949:26:SPI_WaitFlagStateUntilTimeout 40 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4018:26:SPI_WaitFifoStateUntilTimeout 48 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4098:26:SPI_EndRxTransaction 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4134:26:SPI_EndRxTxTransaction 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4166:13:SPI_CloseRxTx_ISR 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4243:13:SPI_CloseRx_ISR 16 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4300:13:SPI_CloseTx_ISR 24 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4349:13:SPI_AbortRx_ISR 32 static
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c:4393:13:SPI_AbortTx_ISR 32 static

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c:79:19:HAL_SPIEx_FlushRxFifo 3

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../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c:79:19:HAL_SPIEx_FlushRxFifo 24 static

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vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.cyclo Normal file
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vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.su Normal file
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vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.cyclo Normal file
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vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.su Normal file
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vn200/Debug/Drivers/STM32F3xx_HAL_Driver/Src/subdir.mk Normal file
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################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c \
../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
C_DEPS += \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.d \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.d
OBJS += \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o \
./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o
# Each subdirectory must supply rules for building sources it contributes
Drivers/STM32F3xx_HAL_Driver/Src/%.o Drivers/STM32F3xx_HAL_Driver/Src/%.su Drivers/STM32F3xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F3xx_HAL_Driver/Src/%.c Drivers/STM32F3xx_HAL_Driver/Src/subdir.mk
arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F302xC -c -I../Core/Inc -I../Drivers/STM32F3xx_HAL_Driver/Inc -I../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F3xx/Include -I../Drivers/CMSIS/Include -I../Converter/Inc -I/usr/local/include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
clean: clean-Drivers-2f-STM32F3xx_HAL_Driver-2f-Src
clean-Drivers-2f-STM32F3xx_HAL_Driver-2f-Src:
-$(RM) ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.su ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.cyclo ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.su
.PHONY: clean-Drivers-2f-STM32F3xx_HAL_Driver-2f-Src

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################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include Drivers/STM32F3xx_HAL_Driver/Src/subdir.mk
-include Core/Startup/subdir.mk
-include Core/Src/subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(CC_DEPS)),)
-include $(CC_DEPS)
endif
ifneq ($(strip $(C++_DEPS)),)
-include $(C++_DEPS)
endif
ifneq ($(strip $(CCM_DEPS)),)
-include $(CCM_DEPS)
endif
ifneq ($(strip $(C_UPPER_DEPS)),)
-include $(C_UPPER_DEPS)
endif
ifneq ($(strip $(CXX_DEPS)),)
-include $(CXX_DEPS)
endif
ifneq ($(strip $(S_DEPS)),)
-include $(S_DEPS)
endif
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
ifneq ($(strip $(CXXM_DEPS)),)
-include $(CXXM_DEPS)
endif
ifneq ($(strip $(C++M_DEPS)),)
-include $(C++M_DEPS)
endif
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(CPP_DEPS)),)
-include $(CPP_DEPS)
endif
endif
-include ../makefile.defs
OPTIONAL_TOOL_DEPS := \
$(wildcard ../makefile.defs) \
$(wildcard ../makefile.init) \
$(wildcard ../makefile.targets) \
BUILD_ARTIFACT_NAME := vn200
BUILD_ARTIFACT_EXTENSION := elf
BUILD_ARTIFACT_PREFIX :=
BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
# Add inputs and outputs from these tool invocations to the build variables
EXECUTABLES += \
vn200.elf \
MAP_FILES += \
vn200.map \
SIZE_OUTPUT += \
default.size.stdout \
OBJDUMP_LIST += \
vn200.list \
# All Target
all: main-build
# Main-build Target
main-build: vn200.elf secondary-outputs
# Tool invocations
vn200.elf vn200.map: $(OBJS) $(USER_OBJS) /home/richard/Uni/FaSTTUBe/INS-VN-200/vn200/STM32F302CBTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
arm-none-eabi-g++ -o "vn200.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/home/richard/Uni/FaSTTUBe/INS-VN-200/vn200/STM32F302CBTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="vn200.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
@echo 'Finished building target: $@'
@echo ' '
default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
arm-none-eabi-size $(EXECUTABLES)
@echo 'Finished building: $@'
@echo ' '
vn200.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
arm-none-eabi-objdump -h -S $(EXECUTABLES) > "vn200.list"
@echo 'Finished building: $@'
@echo ' '
# Other Targets
clean:
-$(RM) default.size.stdout vn200.elf vn200.list vn200.map
-@echo ' '
secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
fail-specified-linker-script-missing:
@echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.'
@exit 2
warn-no-linker-script-specified:
@echo 'Warning: No linker script specified. Check the linker settings in the build configuration.'
.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified
-include ../makefile.targets

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"./Core/Src/main.o"
"./Core/Src/stm32f3xx_hal_msp.o"
"./Core/Src/stm32f3xx_it.o"
"./Core/Src/syscalls.o"
"./Core/Src/sysmem.o"
"./Core/Src/system_stm32f3xx.o"
"./Core/Startup/startup_stm32f302cbtx.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o"
"./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o"

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vn200/Debug/objects.mk Normal file
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################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
USER_OBJS :=
LIBS :=

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@ -0,0 +1,44 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (12.3.rel1)
################################################################################
C++M_SRCS :=
CPP_SRCS :=
S_UPPER_SRCS :=
O_SRCS :=
ELF_SRCS :=
C_UPPER_SRCS :=
CXX_SRCS :=
CCM_SRCS :=
C++_SRCS :=
OBJ_SRCS :=
S_SRCS :=
CC_SRCS :=
C_SRCS :=
CXXM_SRCS :=
CYCLO_FILES :=
OBJDUMP_LIST :=
CCM_DEPS :=
C_UPPER_DEPS :=
S_DEPS :=
CXXM_DEPS :=
C_DEPS :=
CC_DEPS :=
SIZE_OUTPUT :=
C++_DEPS :=
SU_FILES :=
EXECUTABLES :=
OBJS :=
CXX_DEPS :=
MAP_FILES :=
S_UPPER_DEPS :=
C++M_DEPS :=
CPP_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
Core/Src \
Core/Startup \
Drivers/STM32F3xx_HAL_Driver/Src \

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/**
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F3xx device used in the target application
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f3xx
* @{
*/
#ifndef __STM32F3xx_H
#define __STM32F3xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F3)
#define STM32F3
#endif /* STM32F3 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
!defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \
!defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
!defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
!defined (STM32F373xC) && !defined (STM32F378xx)
/* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
STM32F301R6 and STM32F301R8 Devices */
/* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
STM32F302R6 and STM32F302R8 Devices */
/* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC,
STM32F302VB and STM32F302VC Devices */
/* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD,
STM32F302VD and STM32F302ZD Devices */
/* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
STM32F303R6 and STM32F303R8 Devices */
/* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC,
STM32F303VB and STM32F303VC Devices */
/* #define STM32F303xE */ /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD,
STM32F303VD and STM32F303ZD Devices */
/* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC,
STM32F373R8, STM32F373RB, STM32F373RC,
STM32F373V8, STM32F373VB and STM32F373VC Devices */
/* #define STM32F334x8 */ /*!< STM32F334K4, STM32F334K6, STM32F334K8,
STM32F334C4, STM32F334C6, STM32F334C8,
STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
/* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
/* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
/* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
/* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
/* #define STM32F398xx */ /*!< STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.7
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F3_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F3_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F301x8)
#include "stm32f301x8.h"
#elif defined(STM32F302x8)
#include "stm32f302x8.h"
#elif defined(STM32F302xC)
#include "stm32f302xc.h"
#elif defined(STM32F302xE)
#include "stm32f302xe.h"
#elif defined(STM32F303x8)
#include "stm32f303x8.h"
#elif defined(STM32F303xC)
#include "stm32f303xc.h"
#elif defined(STM32F303xE)
#include "stm32f303xe.h"
#elif defined(STM32F373xC)
#include "stm32f373xc.h"
#elif defined(STM32F334x8)
#include "stm32f334x8.h"
#elif defined(STM32F318xx)
#include "stm32f318xx.h"
#elif defined(STM32F328xx)
#include "stm32f328xx.h"
#elif defined(STM32F358xx)
#include "stm32f358xx.h"
#elif defined(STM32F378xx)
#include "stm32f378xx.h"
#elif defined(STM32F398xx)
#include "stm32f398xx.h"
#else
#error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f3xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F3xx_H */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ******************************************************************************
* @attention
*
******************************************************************************
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f3xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F3XX_H
#define __SYSTEM_STM32F3XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F3xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
3) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) by calling HAL API function HAL_RCC_ClockConfig()
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F3xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F3XX_H */
/**
* @}
*/
/**
* @}
*/

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This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the Apache-2.0 license shall apply.
You may obtain a copy of the Apache-2.0 at:
https://opensource.org/licenses/Apache-2.0

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.5
* @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.0
* @date 23. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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