FaSTTUBe/INS-VN-200
61
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
INS-VN-200/vn200/Debug/vn200.list
r.koeppe c5f5e6fb98 vn200 stm project
2024-06-06 11:36:00 +02:00

7808 lines
293 KiB
Plaintext
Raw Blame History

vn200.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000030a0 08000188 08000188 00001188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000030 08003228 08003228 00004228 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08003258 08003258 0000500c 2**0
CONTENTS
4 .ARM 00000000 08003258 08003258 0000500c 2**0
CONTENTS
5 .preinit_array 00000000 08003258 08003258 0000500c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08003258 08003258 00004258 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800325c 0800325c 0000425c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08003260 00005000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000ac 2000000c 0800326c 0000500c 2**2
ALLOC
10 ._user_heap_stack 00000600 200000b8 0800326c 000050b8 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000500c 2**0
CONTENTS, READONLY
12 .debug_info 00008230 00000000 00000000 0000503c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001858 00000000 00000000 0000d26c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000768 00000000 00000000 0000eac8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 0000058a 00000000 00000000 0000f230 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001e211 00000000 00000000 0000f7ba 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00008cd5 00000000 00000000 0002d9cb 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000a7990 00000000 00000000 000366a0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000de030 2**0
CONTENTS, READONLY
20 .debug_frame 00001db0 00000000 00000000 000de074 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000005a 00000000 00000000 000dfe24 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000000c .word 0x2000000c
80001a4: 00000000 .word 0x00000000
80001a8: 08003210 .word 0x08003210
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000010 .word 0x20000010
80001c4: 08003210 .word 0x08003210
080001c8 <_ZN2vn8header_t9request_tC1Ehh>:
union header_t {
struct request_t {
uint8_t Cmd = 0; /* Defined in VN_SPI_READ */
uint8_t ID = 0; /* Register ID */
uint16_t Empty = 0; /* Spacer */
request_t(uint8_t ID, uint8_t Cmd) {
80001c8: b480 push {r7}
80001ca: b083 sub sp, #12
80001cc: af00 add r7, sp, #0
80001ce: 6078 str r0, [r7, #4]
80001d0: 460b mov r3, r1
80001d2: 70fb strb r3, [r7, #3]
80001d4: 4613 mov r3, r2
80001d6: 70bb strb r3, [r7, #2]
80001d8: 687b ldr r3, [r7, #4]
80001da: 2200 movs r2, #0
80001dc: 701a strb r2, [r3, #0]
80001de: 687b ldr r3, [r7, #4]
80001e0: 2200 movs r2, #0
80001e2: 705a strb r2, [r3, #1]
80001e4: 687b ldr r3, [r7, #4]
80001e6: 2200 movs r2, #0
80001e8: 805a strh r2, [r3, #2]
this->ID = ID;
80001ea: 687b ldr r3, [r7, #4]
80001ec: 78fa ldrb r2, [r7, #3]
80001ee: 705a strb r2, [r3, #1]
this->Cmd = Cmd;
80001f0: 687b ldr r3, [r7, #4]
80001f2: 78ba ldrb r2, [r7, #2]
80001f4: 701a strb r2, [r3, #0]
};
80001f6: 687b ldr r3, [r7, #4]
80001f8: 4618 mov r0, r3
80001fa: 370c adds r7, #12
80001fc: 46bd mov sp, r7
80001fe: f85d 7b04 ldr.w r7, [sp], #4
8000202: 4770 bx lr
08000204 <_ZN2vn8header_t10response_tC1Ev>:
struct response_t {
uint8_t Empty1 = 0; /* Spacer */
uint8_t Cmd = 0; /* Defined in VN_SPI_READ */
uint8_t ID = 0; /* Register ID */
uint8_t Empty2 = 0; /* Spacer */
response_t(){};
8000204: b480 push {r7}
8000206: b083 sub sp, #12
8000208: af00 add r7, sp, #0
800020a: 6078 str r0, [r7, #4]
800020c: 687b ldr r3, [r7, #4]
800020e: 2200 movs r2, #0
8000210: 701a strb r2, [r3, #0]
8000212: 687b ldr r3, [r7, #4]
8000214: 2200 movs r2, #0
8000216: 705a strb r2, [r3, #1]
8000218: 687b ldr r3, [r7, #4]
800021a: 2200 movs r2, #0
800021c: 709a strb r2, [r3, #2]
800021e: 687b ldr r3, [r7, #4]
8000220: 2200 movs r2, #0
8000222: 70da strb r2, [r3, #3]
8000224: 687b ldr r3, [r7, #4]
8000226: 4618 mov r0, r3
8000228: 370c adds r7, #12
800022a: 46bd mov sp, r7
800022c: f85d 7b04 ldr.w r7, [sp], #4
8000230: 4770 bx lr
08000232 <_ZN2vn18pkg_request_read_tC1Eh>:
};
/** \brief Requests the specified register to read from */
struct pkg_request_read_t {
struct header_t::request_t header;
pkg_request_read_t(uint8_t ID) : header(ID, VN_SPI_READ){};
8000232: b580 push {r7, lr}
8000234: b082 sub sp, #8
8000236: af00 add r7, sp, #0
8000238: 6078 str r0, [r7, #4]
800023a: 460b mov r3, r1
800023c: 70fb strb r3, [r7, #3]
800023e: 687b ldr r3, [r7, #4]
8000240: 78f9 ldrb r1, [r7, #3]
8000242: 2201 movs r2, #1
8000244: 4618 mov r0, r3
8000246: f7ff ffbf bl 80001c8 <_ZN2vn8header_t9request_tC1Ehh>
800024a: 687b ldr r3, [r7, #4]
800024c: 4618 mov r0, r3
800024e: 3708 adds r7, #8
8000250: 46bd mov sp, r7
8000252: bd80 pop {r7, pc}
08000254 <_ZN5vec3fC1Ev>:
struct {
float c0; /**< Component 0. */
float c1; /**< Component 1. */
float c2; /**< Component 2. */
};
vec3f() { std::memset(this, 0, sizeof(vec3f)); }
8000254: b580 push {r7, lr}
8000256: b082 sub sp, #8
8000258: af00 add r7, sp, #0
800025a: 6078 str r0, [r7, #4]
800025c: 220c movs r2, #12
800025e: 2100 movs r1, #0
8000260: 6878 ldr r0, [r7, #4]
8000262: f002 ffa9 bl 80031b8 <memset>
8000266: 687b ldr r3, [r7, #4]
8000268: 4618 mov r0, r3
800026a: 3708 adds r7, #8
800026c: 46bd mov sp, r7
800026e: bd80 pop {r7, pc}
08000270 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000270: b580 push {r7, lr}
8000272: b08c sub sp, #48 @ 0x30
8000274: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000276: f000 fae5 bl 8000844 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800027a: f000 f82d bl 80002d8 <_Z18SystemClock_Configv>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800027e: f000 f8ed bl 800045c <_ZL12MX_GPIO_Initv>
MX_CAN_Init();
8000282: f000 f86f bl 8000364 <_ZL11MX_CAN_Initv>
MX_SPI1_Init();
8000286: f000 f8a7 bl 80003d8 <_ZL12MX_SPI1_Initv>
/* USER CODE BEGIN 2 */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
800028a: 2201 movs r2, #1
800028c: f44f 7100 mov.w r1, #512 @ 0x200
8000290: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000294: f001 f920 bl 80014d8 <HAL_GPIO_WritePin>
response.payload.mag.z = 0.0;
response.payload.pressure = 0.0;
response.payload.temp = 0.0;
*/
auto request = vn::pkg_request_read_t(vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterID);
8000298: f107 032c add.w r3, r7, #44 @ 0x2c
800029c: 21ef movs r1, #239 @ 0xef
800029e: 4618 mov r0, r3
80002a0: f7ff ffc7 bl 8000232 <_ZN2vn18pkg_request_read_tC1Eh>
auto response = vn::pkg_response_t<vn::YawPitchRollTrueBodyAccelerationAndAngularRatesRegister>();
80002a4: 1d3b adds r3, r7, #4
80002a6: 4618 mov r0, r3
80002a8: f000 f935 bl 8000516 <_ZN2vn14pkg_response_tINS_55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterEEC1Ev>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
spi_read(&hspi1, &request, &response);
80002ac: 1d3a adds r2, r7, #4
80002ae: f107 032c add.w r3, r7, #44 @ 0x2c
80002b2: 4619 mov r1, r3
80002b4: 4806 ldr r0, [pc, #24] @ (80002d0 <main+0x60>)
80002b6: f000 f940 bl 800053a <_Z8spi_readIN2vn55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefPNS0_18pkg_request_read_tEPNS0_14pkg_response_tIT_EE>
spi2can(&hspi1, &hcan, &response);
80002ba: 1d3b adds r3, r7, #4
80002bc: 461a mov r2, r3
80002be: 4905 ldr r1, [pc, #20] @ (80002d4 <main+0x64>)
80002c0: 4803 ldr r0, [pc, #12] @ (80002d0 <main+0x60>)
80002c2: f000 f98a bl 80005da <_Z7spi2canIN2vn55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefP19__CAN_HandleTypeDefPNS0_14pkg_response_tIT_EE>
HAL_Delay(1);
80002c6: 2001 movs r0, #1
80002c8: f000 fb22 bl 8000910 <HAL_Delay>
spi_read(&hspi1, &request, &response);
80002cc: bf00 nop
80002ce: e7ed b.n 80002ac <main+0x3c>
80002d0: 20000050 .word 0x20000050
80002d4: 20000028 .word 0x20000028
080002d8 <_Z18SystemClock_Configv>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80002d8: b580 push {r7, lr}
80002da: b090 sub sp, #64 @ 0x40
80002dc: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80002de: f107 0318 add.w r3, r7, #24
80002e2: 2228 movs r2, #40 @ 0x28
80002e4: 2100 movs r1, #0
80002e6: 4618 mov r0, r3
80002e8: f002 ff66 bl 80031b8 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80002ec: 1d3b adds r3, r7, #4
80002ee: 2200 movs r2, #0
80002f0: 601a str r2, [r3, #0]
80002f2: 605a str r2, [r3, #4]
80002f4: 609a str r2, [r3, #8]
80002f6: 60da str r2, [r3, #12]
80002f8: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80002fa: 2301 movs r3, #1
80002fc: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80002fe: f44f 3380 mov.w r3, #65536 @ 0x10000
8000302: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000304: 2301 movs r3, #1
8000306: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000308: 2300 movs r3, #0
800030a: 637b str r3, [r7, #52] @ 0x34
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800030c: f107 0318 add.w r3, r7, #24
8000310: 4618 mov r0, r3
8000312: f001 f8f9 bl 8001508 <HAL_RCC_OscConfig>
8000316: 4603 mov r3, r0
8000318: 2b00 cmp r3, #0
800031a: bf14 ite ne
800031c: 2301 movne r3, #1
800031e: 2300 moveq r3, #0
8000320: b2db uxtb r3, r3
8000322: 2b00 cmp r3, #0
8000324: d001 beq.n 800032a <_Z18SystemClock_Configv+0x52>
{
Error_Handler();
8000326: f000 f8d9 bl 80004dc <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800032a: 230f movs r3, #15
800032c: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
800032e: 2301 movs r3, #1
8000330: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000332: 2300 movs r3, #0
8000334: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000336: 2300 movs r3, #0
8000338: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
800033a: 2300 movs r3, #0
800033c: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
800033e: 1d3b adds r3, r7, #4
8000340: 2100 movs r1, #0
8000342: 4618 mov r0, r3
8000344: f002 f91e bl 8002584 <HAL_RCC_ClockConfig>
8000348: 4603 mov r3, r0
800034a: 2b00 cmp r3, #0
800034c: bf14 ite ne
800034e: 2301 movne r3, #1
8000350: 2300 moveq r3, #0
8000352: b2db uxtb r3, r3
8000354: 2b00 cmp r3, #0
8000356: d001 beq.n 800035c <_Z18SystemClock_Configv+0x84>
{
Error_Handler();
8000358: f000 f8c0 bl 80004dc <Error_Handler>
}
}
800035c: bf00 nop
800035e: 3740 adds r7, #64 @ 0x40
8000360: 46bd mov sp, r7
8000362: bd80 pop {r7, pc}
08000364 <_ZL11MX_CAN_Initv>:
* @brief CAN Initialization Function
* @param None
* @retval None
*/
static void MX_CAN_Init(void)
{
8000364: b580 push {r7, lr}
8000366: af00 add r7, sp, #0
/* USER CODE END CAN_Init 0 */
/* USER CODE BEGIN CAN_Init 1 */
/* USER CODE END CAN_Init 1 */
hcan.Instance = CAN;
8000368: 4b19 ldr r3, [pc, #100] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
800036a: 4a1a ldr r2, [pc, #104] @ (80003d4 <_ZL11MX_CAN_Initv+0x70>)
800036c: 601a str r2, [r3, #0]
hcan.Init.Prescaler = 8;
800036e: 4b18 ldr r3, [pc, #96] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
8000370: 2208 movs r2, #8
8000372: 605a str r2, [r3, #4]
hcan.Init.Mode = CAN_MODE_NORMAL;
8000374: 4b16 ldr r3, [pc, #88] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
8000376: 2200 movs r2, #0
8000378: 609a str r2, [r3, #8]
hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
800037a: 4b15 ldr r3, [pc, #84] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
800037c: 2200 movs r2, #0
800037e: 60da str r2, [r3, #12]
hcan.Init.TimeSeg1 = CAN_BS1_2TQ;
8000380: 4b13 ldr r3, [pc, #76] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
8000382: f44f 3280 mov.w r2, #65536 @ 0x10000
8000386: 611a str r2, [r3, #16]
hcan.Init.TimeSeg2 = CAN_BS2_1TQ;
8000388: 4b11 ldr r3, [pc, #68] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
800038a: 2200 movs r2, #0
800038c: 615a str r2, [r3, #20]
hcan.Init.TimeTriggeredMode = DISABLE;
800038e: 4b10 ldr r3, [pc, #64] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
8000390: 2200 movs r2, #0
8000392: 761a strb r2, [r3, #24]
hcan.Init.AutoBusOff = DISABLE;
8000394: 4b0e ldr r3, [pc, #56] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
8000396: 2200 movs r2, #0
8000398: 765a strb r2, [r3, #25]
hcan.Init.AutoWakeUp = DISABLE;
800039a: 4b0d ldr r3, [pc, #52] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
800039c: 2200 movs r2, #0
800039e: 769a strb r2, [r3, #26]
hcan.Init.AutoRetransmission = DISABLE;
80003a0: 4b0b ldr r3, [pc, #44] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
80003a2: 2200 movs r2, #0
80003a4: 76da strb r2, [r3, #27]
hcan.Init.ReceiveFifoLocked = DISABLE;
80003a6: 4b0a ldr r3, [pc, #40] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
80003a8: 2200 movs r2, #0
80003aa: 771a strb r2, [r3, #28]
hcan.Init.TransmitFifoPriority = DISABLE;
80003ac: 4b08 ldr r3, [pc, #32] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
80003ae: 2200 movs r2, #0
80003b0: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan) != HAL_OK)
80003b2: 4807 ldr r0, [pc, #28] @ (80003d0 <_ZL11MX_CAN_Initv+0x6c>)
80003b4: f000 fad0 bl 8000958 <HAL_CAN_Init>
80003b8: 4603 mov r3, r0
80003ba: 2b00 cmp r3, #0
80003bc: bf14 ite ne
80003be: 2301 movne r3, #1
80003c0: 2300 moveq r3, #0
80003c2: b2db uxtb r3, r3
80003c4: 2b00 cmp r3, #0
80003c6: d001 beq.n 80003cc <_ZL11MX_CAN_Initv+0x68>
{
Error_Handler();
80003c8: f000 f888 bl 80004dc <Error_Handler>
}
/* USER CODE BEGIN CAN_Init 2 */
/* USER CODE END CAN_Init 2 */
}
80003cc: bf00 nop
80003ce: bd80 pop {r7, pc}
80003d0: 20000028 .word 0x20000028
80003d4: 40006400 .word 0x40006400
080003d8 <_ZL12MX_SPI1_Initv>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
80003d8: b580 push {r7, lr}
80003da: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
80003dc: 4b1d ldr r3, [pc, #116] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
80003de: 4a1e ldr r2, [pc, #120] @ (8000458 <_ZL12MX_SPI1_Initv+0x80>)
80003e0: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
80003e2: 4b1c ldr r3, [pc, #112] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
80003e4: f44f 7282 mov.w r2, #260 @ 0x104
80003e8: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
80003ea: 4b1a ldr r3, [pc, #104] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
80003ec: 2200 movs r2, #0
80003ee: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
80003f0: 4b18 ldr r3, [pc, #96] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
80003f2: f44f 62e0 mov.w r2, #1792 @ 0x700
80003f6: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
80003f8: 4b16 ldr r3, [pc, #88] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
80003fa: 2202 movs r2, #2
80003fc: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
80003fe: 4b15 ldr r3, [pc, #84] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
8000400: 2201 movs r2, #1
8000402: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
8000404: 4b13 ldr r3, [pc, #76] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
8000406: f44f 7200 mov.w r2, #512 @ 0x200
800040a: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
800040c: 4b11 ldr r3, [pc, #68] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
800040e: 2200 movs r2, #0
8000410: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000412: 4b10 ldr r3, [pc, #64] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
8000414: 2200 movs r2, #0
8000416: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8000418: 4b0e ldr r3, [pc, #56] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
800041a: 2200 movs r2, #0
800041c: 625a str r2, [r3, #36] @ 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
800041e: 4b0d ldr r3, [pc, #52] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
8000420: 2200 movs r2, #0
8000422: 629a str r2, [r3, #40] @ 0x28
hspi1.Init.CRCPolynomial = 7;
8000424: 4b0b ldr r3, [pc, #44] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
8000426: 2207 movs r2, #7
8000428: 62da str r2, [r3, #44] @ 0x2c
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
800042a: 4b0a ldr r3, [pc, #40] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
800042c: 2200 movs r2, #0
800042e: 631a str r2, [r3, #48] @ 0x30
hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
8000430: 4b08 ldr r3, [pc, #32] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
8000432: 2200 movs r2, #0
8000434: 635a str r2, [r3, #52] @ 0x34
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8000436: 4807 ldr r0, [pc, #28] @ (8000454 <_ZL12MX_SPI1_Initv+0x7c>)
8000438: f002 fa8c bl 8002954 <HAL_SPI_Init>
800043c: 4603 mov r3, r0
800043e: 2b00 cmp r3, #0
8000440: bf14 ite ne
8000442: 2301 movne r3, #1
8000444: 2300 moveq r3, #0
8000446: b2db uxtb r3, r3
8000448: 2b00 cmp r3, #0
800044a: d001 beq.n 8000450 <_ZL12MX_SPI1_Initv+0x78>
{
Error_Handler();
800044c: f000 f846 bl 80004dc <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
8000450: bf00 nop
8000452: bd80 pop {r7, pc}
8000454: 20000050 .word 0x20000050
8000458: 40013000 .word 0x40013000
0800045c <_ZL12MX_GPIO_Initv>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
800045c: b580 push {r7, lr}
800045e: b088 sub sp, #32
8000460: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000462: f107 030c add.w r3, r7, #12
8000466: 2200 movs r2, #0
8000468: 601a str r2, [r3, #0]
800046a: 605a str r2, [r3, #4]
800046c: 609a str r2, [r3, #8]
800046e: 60da str r2, [r3, #12]
8000470: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
8000472: 4b19 ldr r3, [pc, #100] @ (80004d8 <_ZL12MX_GPIO_Initv+0x7c>)
8000474: 695b ldr r3, [r3, #20]
8000476: 4a18 ldr r2, [pc, #96] @ (80004d8 <_ZL12MX_GPIO_Initv+0x7c>)
8000478: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
800047c: 6153 str r3, [r2, #20]
800047e: 4b16 ldr r3, [pc, #88] @ (80004d8 <_ZL12MX_GPIO_Initv+0x7c>)
8000480: 695b ldr r3, [r3, #20]
8000482: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8000486: 60bb str r3, [r7, #8]
8000488: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800048a: 4b13 ldr r3, [pc, #76] @ (80004d8 <_ZL12MX_GPIO_Initv+0x7c>)
800048c: 695b ldr r3, [r3, #20]
800048e: 4a12 ldr r2, [pc, #72] @ (80004d8 <_ZL12MX_GPIO_Initv+0x7c>)
8000490: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000494: 6153 str r3, [r2, #20]
8000496: 4b10 ldr r3, [pc, #64] @ (80004d8 <_ZL12MX_GPIO_Initv+0x7c>)
8000498: 695b ldr r3, [r3, #20]
800049a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800049e: 607b str r3, [r7, #4]
80004a0: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, SPI1_CS_Pin|NRST_VN_Pin, GPIO_PIN_SET);
80004a2: 2201 movs r2, #1
80004a4: f44f 61c0 mov.w r1, #1536 @ 0x600
80004a8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80004ac: f001 f814 bl 80014d8 <HAL_GPIO_WritePin>
/*Configure GPIO pins : SPI1_CS_Pin NRST_VN_Pin */
GPIO_InitStruct.Pin = SPI1_CS_Pin|NRST_VN_Pin;
80004b0: f44f 63c0 mov.w r3, #1536 @ 0x600
80004b4: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80004b6: 2301 movs r3, #1
80004b8: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80004ba: 2301 movs r3, #1
80004bc: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80004be: 2303 movs r3, #3
80004c0: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80004c2: f107 030c add.w r3, r7, #12
80004c6: 4619 mov r1, r3
80004c8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80004cc: f000 fe8a bl 80011e4 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80004d0: bf00 nop
80004d2: 3720 adds r7, #32
80004d4: 46bd mov sp, r7
80004d6: bd80 pop {r7, pc}
80004d8: 40021000 .word 0x40021000
080004dc <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80004dc: b480 push {r7}
80004de: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80004e0: b672 cpsid i
}
80004e2: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80004e4: bf00 nop
80004e6: e7fd b.n 80004e4 <Error_Handler+0x8>
080004e8 <_ZN2vn55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterC1Ev>:
vec3f bodyAccel;
/** \brief The Gyro field. */
vec3f gyro;
} YawPitchRollTrueBodyAccelerationAndAngularRatesRegister;
80004e8: b580 push {r7, lr}
80004ea: b082 sub sp, #8
80004ec: af00 add r7, sp, #0
80004ee: 6078 str r0, [r7, #4]
80004f0: 687b ldr r3, [r7, #4]
80004f2: 4618 mov r0, r3
80004f4: f7ff feae bl 8000254 <_ZN5vec3fC1Ev>
80004f8: 687b ldr r3, [r7, #4]
80004fa: 330c adds r3, #12
80004fc: 4618 mov r0, r3
80004fe: f7ff fea9 bl 8000254 <_ZN5vec3fC1Ev>
8000502: 687b ldr r3, [r7, #4]
8000504: 3318 adds r3, #24
8000506: 4618 mov r0, r3
8000508: f7ff fea4 bl 8000254 <_ZN5vec3fC1Ev>
800050c: 687b ldr r3, [r7, #4]
800050e: 4618 mov r0, r3
8000510: 3708 adds r7, #8
8000512: 46bd mov sp, r7
8000514: bd80 pop {r7, pc}
08000516 <_ZN2vn14pkg_response_tINS_55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterEEC1Ev>:
/** \brief Response structure for the specified register */
template <typename payload_t> struct pkg_response_t {
struct header_t::response_t header;
payload_t payload;
pkg_response_t() : header(){};
8000516: b580 push {r7, lr}
8000518: b082 sub sp, #8
800051a: af00 add r7, sp, #0
800051c: 6078 str r0, [r7, #4]
800051e: 687b ldr r3, [r7, #4]
8000520: 4618 mov r0, r3
8000522: f7ff fe6f bl 8000204 <_ZN2vn8header_t10response_tC1Ev>
8000526: 687b ldr r3, [r7, #4]
8000528: 3304 adds r3, #4
800052a: 4618 mov r0, r3
800052c: f7ff ffdc bl 80004e8 <_ZN2vn55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterC1Ev>
8000530: 687b ldr r3, [r7, #4]
8000532: 4618 mov r0, r3
8000534: 3708 adds r7, #8
8000536: 46bd mov sp, r7
8000538: bd80 pop {r7, pc}
0800053a <_Z8spi_readIN2vn55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefPNS0_18pkg_request_read_tEPNS0_14pkg_response_tIT_EE>:
HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef ftcan_transmit(CAN_HandleTypeDef *hcan, uint16_t id, const uint8_t *data, size_t datalen);
template <typename payload_t>
HAL_StatusTypeDef spi_read(SPI_HandleTypeDef *hspi, vn::pkg_request_read_t *pRequestMOSI, vn::pkg_response_t<payload_t> *pResponseMISO){
800053a: b580 push {r7, lr}
800053c: b092 sub sp, #72 @ 0x48
800053e: af02 add r7, sp, #8
8000540: 60f8 str r0, [r7, #12]
8000542: 60b9 str r1, [r7, #8]
8000544: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000546: 2300 movs r3, #0
8000548: f887 303f strb.w r3, [r7, #63] @ 0x3f
vn::header_t::response_t requestMISO;
800054c: f107 0338 add.w r3, r7, #56 @ 0x38
8000550: 4618 mov r0, r3
8000552: f7ff fe57 bl 8000204 <_ZN2vn8header_t10response_tC1Ev>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
8000556: 2200 movs r2, #0
8000558: f44f 7100 mov.w r1, #512 @ 0x200
800055c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000560: f000 ffba bl 80014d8 <HAL_GPIO_WritePin>
status = HAL_SPI_TransmitReceive(hspi,
8000564: f107 0238 add.w r2, r7, #56 @ 0x38
8000568: 2364 movs r3, #100 @ 0x64
800056a: 9300 str r3, [sp, #0]
800056c: 2304 movs r3, #4
800056e: 68b9 ldr r1, [r7, #8]
8000570: 68f8 ldr r0, [r7, #12]
8000572: f002 fa9a bl 8002aaa <HAL_SPI_TransmitReceive>
8000576: 4603 mov r3, r0
8000578: f887 303f strb.w r3, [r7, #63] @ 0x3f
(uint8_t *)(pRequestMOSI),
(uint8_t *)(&requestMISO), // not relevant, but there to function
sizeof(*pRequestMOSI), 100);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
800057c: 2201 movs r2, #1
800057e: f44f 7100 mov.w r1, #512 @ 0x200
8000582: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000586: f000 ffa7 bl 80014d8 <HAL_GPIO_WritePin>
HAL_Delay(1);
800058a: 2001 movs r0, #1
800058c: f000 f9c0 bl 8000910 <HAL_Delay>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_RESET);
8000590: 2200 movs r2, #0
8000592: f44f 7100 mov.w r1, #512 @ 0x200
8000596: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800059a: f000 ff9d bl 80014d8 <HAL_GPIO_WritePin>
vn::pkg_response_t<payload_t> responseMOSI;
800059e: f107 0310 add.w r3, r7, #16
80005a2: 4618 mov r0, r3
80005a4: f7ff ffb7 bl 8000516 <_ZN2vn14pkg_response_tINS_55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterEEC1Ev>
status = HAL_SPI_TransmitReceive(hspi,
80005a8: f107 0110 add.w r1, r7, #16
80005ac: 2364 movs r3, #100 @ 0x64
80005ae: 9300 str r3, [sp, #0]
80005b0: 2328 movs r3, #40 @ 0x28
80005b2: 687a ldr r2, [r7, #4]
80005b4: 68f8 ldr r0, [r7, #12]
80005b6: f002 fa78 bl 8002aaa <HAL_SPI_TransmitReceive>
80005ba: 4603 mov r3, r0
80005bc: f887 303f strb.w r3, [r7, #63] @ 0x3f
(uint8_t *)(&responseMOSI), // just empty byte to allow the slave to transmit
(uint8_t *)(pResponseMISO),
sizeof(*pResponseMISO), 100);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
80005c0: 2201 movs r2, #1
80005c2: f44f 7100 mov.w r1, #512 @ 0x200
80005c6: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80005ca: f000 ff85 bl 80014d8 <HAL_GPIO_WritePin>
return status;
80005ce: f897 303f ldrb.w r3, [r7, #63] @ 0x3f
}
80005d2: 4618 mov r0, r3
80005d4: 3740 adds r7, #64 @ 0x40
80005d6: 46bd mov sp, r7
80005d8: bd80 pop {r7, pc}
080005da <_Z7spi2canIN2vn55YawPitchRollTrueBodyAccelerationAndAngularRatesRegisterEE17HAL_StatusTypeDefP19__SPI_HandleTypeDefP19__CAN_HandleTypeDefPNS0_14pkg_response_tIT_EE>:
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, GPIO_PIN_SET);
return status;
}
template <typename payload_t>
HAL_StatusTypeDef spi2can(SPI_HandleTypeDef *hspi, CAN_HandleTypeDef *hcan, vn::pkg_response_t<payload_t> *pResponse){
80005da: b480 push {r7}
80005dc: b085 sub sp, #20
80005de: af00 add r7, sp, #0
80005e0: 60f8 str r0, [r7, #12]
80005e2: 60b9 str r1, [r7, #8]
80005e4: 607a str r2, [r7, #4]
//spi_read(hspi, &request, pResponse);
//can_transmit(hcan);
return HAL_OK;
80005e6: 2300 movs r3, #0
}
80005e8: 4618 mov r0, r3
80005ea: 3714 adds r7, #20
80005ec: 46bd mov sp, r7
80005ee: f85d 7b04 ldr.w r7, [sp], #4
80005f2: 4770 bx lr
080005f4 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80005f4: b480 push {r7}
80005f6: b083 sub sp, #12
80005f8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80005fa: 4b0f ldr r3, [pc, #60] @ (8000638 <HAL_MspInit+0x44>)
80005fc: 699b ldr r3, [r3, #24]
80005fe: 4a0e ldr r2, [pc, #56] @ (8000638 <HAL_MspInit+0x44>)
8000600: f043 0301 orr.w r3, r3, #1
8000604: 6193 str r3, [r2, #24]
8000606: 4b0c ldr r3, [pc, #48] @ (8000638 <HAL_MspInit+0x44>)
8000608: 699b ldr r3, [r3, #24]
800060a: f003 0301 and.w r3, r3, #1
800060e: 607b str r3, [r7, #4]
8000610: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000612: 4b09 ldr r3, [pc, #36] @ (8000638 <HAL_MspInit+0x44>)
8000614: 69db ldr r3, [r3, #28]
8000616: 4a08 ldr r2, [pc, #32] @ (8000638 <HAL_MspInit+0x44>)
8000618: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800061c: 61d3 str r3, [r2, #28]
800061e: 4b06 ldr r3, [pc, #24] @ (8000638 <HAL_MspInit+0x44>)
8000620: 69db ldr r3, [r3, #28]
8000622: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000626: 603b str r3, [r7, #0]
8000628: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800062a: bf00 nop
800062c: 370c adds r7, #12
800062e: 46bd mov sp, r7
8000630: f85d 7b04 ldr.w r7, [sp], #4
8000634: 4770 bx lr
8000636: bf00 nop
8000638: 40021000 .word 0x40021000
0800063c <HAL_CAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
800063c: b580 push {r7, lr}
800063e: b08a sub sp, #40 @ 0x28
8000640: af00 add r7, sp, #0
8000642: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000644: f107 0314 add.w r3, r7, #20
8000648: 2200 movs r2, #0
800064a: 601a str r2, [r3, #0]
800064c: 605a str r2, [r3, #4]
800064e: 609a str r2, [r3, #8]
8000650: 60da str r2, [r3, #12]
8000652: 611a str r2, [r3, #16]
if(hcan->Instance==CAN)
8000654: 687b ldr r3, [r7, #4]
8000656: 681b ldr r3, [r3, #0]
8000658: 4a1c ldr r2, [pc, #112] @ (80006cc <HAL_CAN_MspInit+0x90>)
800065a: 4293 cmp r3, r2
800065c: d131 bne.n 80006c2 <HAL_CAN_MspInit+0x86>
{
/* USER CODE BEGIN CAN_MspInit 0 */
/* USER CODE END CAN_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
800065e: 4b1c ldr r3, [pc, #112] @ (80006d0 <HAL_CAN_MspInit+0x94>)
8000660: 69db ldr r3, [r3, #28]
8000662: 4a1b ldr r2, [pc, #108] @ (80006d0 <HAL_CAN_MspInit+0x94>)
8000664: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8000668: 61d3 str r3, [r2, #28]
800066a: 4b19 ldr r3, [pc, #100] @ (80006d0 <HAL_CAN_MspInit+0x94>)
800066c: 69db ldr r3, [r3, #28]
800066e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8000672: 613b str r3, [r7, #16]
8000674: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000676: 4b16 ldr r3, [pc, #88] @ (80006d0 <HAL_CAN_MspInit+0x94>)
8000678: 695b ldr r3, [r3, #20]
800067a: 4a15 ldr r2, [pc, #84] @ (80006d0 <HAL_CAN_MspInit+0x94>)
800067c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000680: 6153 str r3, [r2, #20]
8000682: 4b13 ldr r3, [pc, #76] @ (80006d0 <HAL_CAN_MspInit+0x94>)
8000684: 695b ldr r3, [r3, #20]
8000686: f403 3300 and.w r3, r3, #131072 @ 0x20000
800068a: 60fb str r3, [r7, #12]
800068c: 68fb ldr r3, [r7, #12]
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
800068e: f44f 53c0 mov.w r3, #6144 @ 0x1800
8000692: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000694: 2302 movs r3, #2
8000696: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000698: 2300 movs r3, #0
800069a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
800069c: 2303 movs r3, #3
800069e: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
80006a0: 2309 movs r3, #9
80006a2: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80006a4: f107 0314 add.w r3, r7, #20
80006a8: 4619 mov r1, r3
80006aa: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
80006ae: f000 fd99 bl 80011e4 <HAL_GPIO_Init>
/* CAN interrupt Init */
HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
80006b2: 2200 movs r2, #0
80006b4: 2100 movs r1, #0
80006b6: 2015 movs r0, #21
80006b8: f000 fd5d bl 8001176 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
80006bc: 2015 movs r0, #21
80006be: f000 fd76 bl 80011ae <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN CAN_MspInit 1 */
/* USER CODE END CAN_MspInit 1 */
}
}
80006c2: bf00 nop
80006c4: 3728 adds r7, #40 @ 0x28
80006c6: 46bd mov sp, r7
80006c8: bd80 pop {r7, pc}
80006ca: bf00 nop
80006cc: 40006400 .word 0x40006400
80006d0: 40021000 .word 0x40021000
080006d4 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80006d4: b580 push {r7, lr}
80006d6: b08a sub sp, #40 @ 0x28
80006d8: af00 add r7, sp, #0
80006da: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006dc: f107 0314 add.w r3, r7, #20
80006e0: 2200 movs r2, #0
80006e2: 601a str r2, [r3, #0]
80006e4: 605a str r2, [r3, #4]
80006e6: 609a str r2, [r3, #8]
80006e8: 60da str r2, [r3, #12]
80006ea: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
80006ec: 687b ldr r3, [r7, #4]
80006ee: 681b ldr r3, [r3, #0]
80006f0: 4a17 ldr r2, [pc, #92] @ (8000750 <HAL_SPI_MspInit+0x7c>)
80006f2: 4293 cmp r3, r2
80006f4: d128 bne.n 8000748 <HAL_SPI_MspInit+0x74>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
80006f6: 4b17 ldr r3, [pc, #92] @ (8000754 <HAL_SPI_MspInit+0x80>)
80006f8: 699b ldr r3, [r3, #24]
80006fa: 4a16 ldr r2, [pc, #88] @ (8000754 <HAL_SPI_MspInit+0x80>)
80006fc: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8000700: 6193 str r3, [r2, #24]
8000702: 4b14 ldr r3, [pc, #80] @ (8000754 <HAL_SPI_MspInit+0x80>)
8000704: 699b ldr r3, [r3, #24]
8000706: f403 5380 and.w r3, r3, #4096 @ 0x1000
800070a: 613b str r3, [r7, #16]
800070c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800070e: 4b11 ldr r3, [pc, #68] @ (8000754 <HAL_SPI_MspInit+0x80>)
8000710: 695b ldr r3, [r3, #20]
8000712: 4a10 ldr r2, [pc, #64] @ (8000754 <HAL_SPI_MspInit+0x80>)
8000714: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000718: 6153 str r3, [r2, #20]
800071a: 4b0e ldr r3, [pc, #56] @ (8000754 <HAL_SPI_MspInit+0x80>)
800071c: 695b ldr r3, [r3, #20]
800071e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000722: 60fb str r3, [r7, #12]
8000724: 68fb ldr r3, [r7, #12]
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
8000726: 23e0 movs r3, #224 @ 0xe0
8000728: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800072a: 2302 movs r3, #2
800072c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800072e: 2300 movs r3, #0
8000730: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000732: 2303 movs r3, #3
8000734: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000736: 2305 movs r3, #5
8000738: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800073a: f107 0314 add.w r3, r7, #20
800073e: 4619 mov r1, r3
8000740: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8000744: f000 fd4e bl 80011e4 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
8000748: bf00 nop
800074a: 3728 adds r7, #40 @ 0x28
800074c: 46bd mov sp, r7
800074e: bd80 pop {r7, pc}
8000750: 40013000 .word 0x40013000
8000754: 40021000 .word 0x40021000
08000758 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000758: b480 push {r7}
800075a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800075c: bf00 nop
800075e: e7fd b.n 800075c <NMI_Handler+0x4>
08000760 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000760: b480 push {r7}
8000762: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000764: bf00 nop
8000766: e7fd b.n 8000764 <HardFault_Handler+0x4>
08000768 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000768: b480 push {r7}
800076a: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
800076c: bf00 nop
800076e: e7fd b.n 800076c <MemManage_Handler+0x4>
08000770 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000770: b480 push {r7}
8000772: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000774: bf00 nop
8000776: e7fd b.n 8000774 <BusFault_Handler+0x4>
08000778 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000778: b480 push {r7}
800077a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
800077c: bf00 nop
800077e: e7fd b.n 800077c <UsageFault_Handler+0x4>
08000780 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000780: b480 push {r7}
8000782: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000784: bf00 nop
8000786: 46bd mov sp, r7
8000788: f85d 7b04 ldr.w r7, [sp], #4
800078c: 4770 bx lr
0800078e <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
800078e: b480 push {r7}
8000790: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000792: bf00 nop
8000794: 46bd mov sp, r7
8000796: f85d 7b04 ldr.w r7, [sp], #4
800079a: 4770 bx lr
0800079c <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800079c: b480 push {r7}
800079e: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80007a0: bf00 nop
80007a2: 46bd mov sp, r7
80007a4: f85d 7b04 ldr.w r7, [sp], #4
80007a8: 4770 bx lr
080007aa <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80007aa: b580 push {r7, lr}
80007ac: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80007ae: f000 f88f bl 80008d0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80007b2: bf00 nop
80007b4: bd80 pop {r7, pc}
...
080007b8 <CAN_RX1_IRQHandler>:
/**
* @brief This function handles CAN RX1 interrupt.
*/
void CAN_RX1_IRQHandler(void)
{
80007b8: b580 push {r7, lr}
80007ba: af00 add r7, sp, #0
/* USER CODE BEGIN CAN_RX1_IRQn 0 */
/* USER CODE END CAN_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
80007bc: 4802 ldr r0, [pc, #8] @ (80007c8 <CAN_RX1_IRQHandler+0x10>)
80007be: f000 f9c6 bl 8000b4e <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN_RX1_IRQn 1 */
/* USER CODE END CAN_RX1_IRQn 1 */
}
80007c2: bf00 nop
80007c4: bd80 pop {r7, pc}
80007c6: bf00 nop
80007c8: 20000028 .word 0x20000028
080007cc <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
80007cc: b480 push {r7}
80007ce: af00 add r7, sp, #0
/* FPU settings --------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80007d0: 4b06 ldr r3, [pc, #24] @ (80007ec <SystemInit+0x20>)
80007d2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80007d6: 4a05 ldr r2, [pc, #20] @ (80007ec <SystemInit+0x20>)
80007d8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80007dc: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80007e0: bf00 nop
80007e2: 46bd mov sp, r7
80007e4: f85d 7b04 ldr.w r7, [sp], #4
80007e8: 4770 bx lr
80007ea: bf00 nop
80007ec: e000ed00 .word 0xe000ed00
080007f0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
80007f0: f8df d034 ldr.w sp, [pc, #52] @ 8000828 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
80007f4: f7ff ffea bl 80007cc <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80007f8: 480c ldr r0, [pc, #48] @ (800082c <LoopForever+0x6>)
ldr r1, =_edata
80007fa: 490d ldr r1, [pc, #52] @ (8000830 <LoopForever+0xa>)
ldr r2, =_sidata
80007fc: 4a0d ldr r2, [pc, #52] @ (8000834 <LoopForever+0xe>)
movs r3, #0
80007fe: 2300 movs r3, #0
b LoopCopyDataInit
8000800: e002 b.n 8000808 <LoopCopyDataInit>
08000802 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000802: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000804: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000806: 3304 adds r3, #4
08000808 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000808: 18c4 adds r4, r0, r3
cmp r4, r1
800080a: 428c cmp r4, r1
bcc CopyDataInit
800080c: d3f9 bcc.n 8000802 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800080e: 4a0a ldr r2, [pc, #40] @ (8000838 <LoopForever+0x12>)
ldr r4, =_ebss
8000810: 4c0a ldr r4, [pc, #40] @ (800083c <LoopForever+0x16>)
movs r3, #0
8000812: 2300 movs r3, #0
b LoopFillZerobss
8000814: e001 b.n 800081a <LoopFillZerobss>
08000816 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000816: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000818: 3204 adds r2, #4
0800081a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800081a: 42a2 cmp r2, r4
bcc FillZerobss
800081c: d3fb bcc.n 8000816 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800081e: f002 fcd3 bl 80031c8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000822: f7ff fd25 bl 8000270 <main>
08000826 <LoopForever>:
LoopForever:
b LoopForever
8000826: e7fe b.n 8000826 <LoopForever>
ldr sp, =_estack /* Atollic update: set stack pointer */
8000828: 20008000 .word 0x20008000
ldr r0, =_sdata
800082c: 20000000 .word 0x20000000
ldr r1, =_edata
8000830: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000834: 08003260 .word 0x08003260
ldr r2, =_sbss
8000838: 2000000c .word 0x2000000c
ldr r4, =_ebss
800083c: 200000b8 .word 0x200000b8
08000840 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000840: e7fe b.n 8000840 <ADC1_2_IRQHandler>
...
08000844 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000844: b580 push {r7, lr}
8000846: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000848: 4b08 ldr r3, [pc, #32] @ (800086c <HAL_Init+0x28>)
800084a: 681b ldr r3, [r3, #0]
800084c: 4a07 ldr r2, [pc, #28] @ (800086c <HAL_Init+0x28>)
800084e: f043 0310 orr.w r3, r3, #16
8000852: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000854: 2003 movs r0, #3
8000856: f000 fc83 bl 8001160 <HAL_NVIC_SetPriorityGrouping>
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
800085a: 200f movs r0, #15
800085c: f000 f808 bl 8000870 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000860: f7ff fec8 bl 80005f4 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000864: 2300 movs r3, #0
}
8000866: 4618 mov r0, r3
8000868: bd80 pop {r7, pc}
800086a: bf00 nop
800086c: 40022000 .word 0x40022000
08000870 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000870: b580 push {r7, lr}
8000872: b082 sub sp, #8
8000874: af00 add r7, sp, #0
8000876: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000878: 4b12 ldr r3, [pc, #72] @ (80008c4 <HAL_InitTick+0x54>)
800087a: 681a ldr r2, [r3, #0]
800087c: 4b12 ldr r3, [pc, #72] @ (80008c8 <HAL_InitTick+0x58>)
800087e: 781b ldrb r3, [r3, #0]
8000880: 4619 mov r1, r3
8000882: f44f 737a mov.w r3, #1000 @ 0x3e8
8000886: fbb3 f3f1 udiv r3, r3, r1
800088a: fbb2 f3f3 udiv r3, r2, r3
800088e: 4618 mov r0, r3
8000890: f000 fc9b bl 80011ca <HAL_SYSTICK_Config>
8000894: 4603 mov r3, r0
8000896: 2b00 cmp r3, #0
8000898: d001 beq.n 800089e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800089a: 2301 movs r3, #1
800089c: e00e b.n 80008bc <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800089e: 687b ldr r3, [r7, #4]
80008a0: 2b0f cmp r3, #15
80008a2: d80a bhi.n 80008ba <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80008a4: 2200 movs r2, #0
80008a6: 6879 ldr r1, [r7, #4]
80008a8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80008ac: f000 fc63 bl 8001176 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80008b0: 4a06 ldr r2, [pc, #24] @ (80008cc <HAL_InitTick+0x5c>)
80008b2: 687b ldr r3, [r7, #4]
80008b4: 6013 str r3, [r2, #0]
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80008b6: 2300 movs r3, #0
80008b8: e000 b.n 80008bc <HAL_InitTick+0x4c>
return HAL_ERROR;
80008ba: 2301 movs r3, #1
}
80008bc: 4618 mov r0, r3
80008be: 3708 adds r7, #8
80008c0: 46bd mov sp, r7
80008c2: bd80 pop {r7, pc}
80008c4: 20000000 .word 0x20000000
80008c8: 20000008 .word 0x20000008
80008cc: 20000004 .word 0x20000004
080008d0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80008d0: b480 push {r7}
80008d2: af00 add r7, sp, #0
uwTick += uwTickFreq;
80008d4: 4b06 ldr r3, [pc, #24] @ (80008f0 <HAL_IncTick+0x20>)
80008d6: 781b ldrb r3, [r3, #0]
80008d8: 461a mov r2, r3
80008da: 4b06 ldr r3, [pc, #24] @ (80008f4 <HAL_IncTick+0x24>)
80008dc: 681b ldr r3, [r3, #0]
80008de: 4413 add r3, r2
80008e0: 4a04 ldr r2, [pc, #16] @ (80008f4 <HAL_IncTick+0x24>)
80008e2: 6013 str r3, [r2, #0]
}
80008e4: bf00 nop
80008e6: 46bd mov sp, r7
80008e8: f85d 7b04 ldr.w r7, [sp], #4
80008ec: 4770 bx lr
80008ee: bf00 nop
80008f0: 20000008 .word 0x20000008
80008f4: 200000b4 .word 0x200000b4
080008f8 <HAL_GetTick>:
* @note The function is declared as __Weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80008f8: b480 push {r7}
80008fa: af00 add r7, sp, #0
return uwTick;
80008fc: 4b03 ldr r3, [pc, #12] @ (800090c <HAL_GetTick+0x14>)
80008fe: 681b ldr r3, [r3, #0]
}
8000900: 4618 mov r0, r3
8000902: 46bd mov sp, r7
8000904: f85d 7b04 ldr.w r7, [sp], #4
8000908: 4770 bx lr
800090a: bf00 nop
800090c: 200000b4 .word 0x200000b4
08000910 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000910: b580 push {r7, lr}
8000912: b084 sub sp, #16
8000914: af00 add r7, sp, #0
8000916: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000918: f7ff ffee bl 80008f8 <HAL_GetTick>
800091c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
800091e: 687b ldr r3, [r7, #4]
8000920: 60fb str r3, [r7, #12]
/* Add freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8000922: 68fb ldr r3, [r7, #12]
8000924: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8000928: d005 beq.n 8000936 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
800092a: 4b0a ldr r3, [pc, #40] @ (8000954 <HAL_Delay+0x44>)
800092c: 781b ldrb r3, [r3, #0]
800092e: 461a mov r2, r3
8000930: 68fb ldr r3, [r7, #12]
8000932: 4413 add r3, r2
8000934: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8000936: bf00 nop
8000938: f7ff ffde bl 80008f8 <HAL_GetTick>
800093c: 4602 mov r2, r0
800093e: 68bb ldr r3, [r7, #8]
8000940: 1ad3 subs r3, r2, r3
8000942: 68fa ldr r2, [r7, #12]
8000944: 429a cmp r2, r3
8000946: d8f7 bhi.n 8000938 <HAL_Delay+0x28>
{
}
}
8000948: bf00 nop
800094a: bf00 nop
800094c: 3710 adds r7, #16
800094e: 46bd mov sp, r7
8000950: bd80 pop {r7, pc}
8000952: bf00 nop
8000954: 20000008 .word 0x20000008
08000958 <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
8000958: b580 push {r7, lr}
800095a: b084 sub sp, #16
800095c: af00 add r7, sp, #0
800095e: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
8000960: 687b ldr r3, [r7, #4]
8000962: 2b00 cmp r3, #0
8000964: d101 bne.n 800096a <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
8000966: 2301 movs r3, #1
8000968: e0ed b.n 8000b46 <HAL_CAN_Init+0x1ee>
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
}
#else
if (hcan->State == HAL_CAN_STATE_RESET)
800096a: 687b ldr r3, [r7, #4]
800096c: f893 3020 ldrb.w r3, [r3, #32]
8000970: b2db uxtb r3, r3
8000972: 2b00 cmp r3, #0
8000974: d102 bne.n 800097c <HAL_CAN_Init+0x24>
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
8000976: 6878 ldr r0, [r7, #4]
8000978: f7ff fe60 bl 800063c <HAL_CAN_MspInit>
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
800097c: 687b ldr r3, [r7, #4]
800097e: 681b ldr r3, [r3, #0]
8000980: 681a ldr r2, [r3, #0]
8000982: 687b ldr r3, [r7, #4]
8000984: 681b ldr r3, [r3, #0]
8000986: f042 0201 orr.w r2, r2, #1
800098a: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
800098c: f7ff ffb4 bl 80008f8 <HAL_GetTick>
8000990: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000992: e012 b.n 80009ba <HAL_CAN_Init+0x62>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000994: f7ff ffb0 bl 80008f8 <HAL_GetTick>
8000998: 4602 mov r2, r0
800099a: 68fb ldr r3, [r7, #12]
800099c: 1ad3 subs r3, r2, r3
800099e: 2b0a cmp r3, #10
80009a0: d90b bls.n 80009ba <HAL_CAN_Init+0x62>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
80009a2: 687b ldr r3, [r7, #4]
80009a4: 6a5b ldr r3, [r3, #36] @ 0x24
80009a6: f443 3200 orr.w r2, r3, #131072 @ 0x20000
80009aa: 687b ldr r3, [r7, #4]
80009ac: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
80009ae: 687b ldr r3, [r7, #4]
80009b0: 2205 movs r2, #5
80009b2: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
80009b6: 2301 movs r3, #1
80009b8: e0c5 b.n 8000b46 <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
80009ba: 687b ldr r3, [r7, #4]
80009bc: 681b ldr r3, [r3, #0]
80009be: 685b ldr r3, [r3, #4]
80009c0: f003 0301 and.w r3, r3, #1
80009c4: 2b00 cmp r3, #0
80009c6: d0e5 beq.n 8000994 <HAL_CAN_Init+0x3c>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
80009c8: 687b ldr r3, [r7, #4]
80009ca: 681b ldr r3, [r3, #0]
80009cc: 681a ldr r2, [r3, #0]
80009ce: 687b ldr r3, [r7, #4]
80009d0: 681b ldr r3, [r3, #0]
80009d2: f022 0202 bic.w r2, r2, #2
80009d6: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
80009d8: f7ff ff8e bl 80008f8 <HAL_GetTick>
80009dc: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
80009de: e012 b.n 8000a06 <HAL_CAN_Init+0xae>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
80009e0: f7ff ff8a bl 80008f8 <HAL_GetTick>
80009e4: 4602 mov r2, r0
80009e6: 68fb ldr r3, [r7, #12]
80009e8: 1ad3 subs r3, r2, r3
80009ea: 2b0a cmp r3, #10
80009ec: d90b bls.n 8000a06 <HAL_CAN_Init+0xae>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
80009ee: 687b ldr r3, [r7, #4]
80009f0: 6a5b ldr r3, [r3, #36] @ 0x24
80009f2: f443 3200 orr.w r2, r3, #131072 @ 0x20000
80009f6: 687b ldr r3, [r7, #4]
80009f8: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
80009fa: 687b ldr r3, [r7, #4]
80009fc: 2205 movs r2, #5
80009fe: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000a02: 2301 movs r3, #1
8000a04: e09f b.n 8000b46 <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000a06: 687b ldr r3, [r7, #4]
8000a08: 681b ldr r3, [r3, #0]
8000a0a: 685b ldr r3, [r3, #4]
8000a0c: f003 0302 and.w r3, r3, #2
8000a10: 2b00 cmp r3, #0
8000a12: d1e5 bne.n 80009e0 <HAL_CAN_Init+0x88>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
8000a14: 687b ldr r3, [r7, #4]
8000a16: 7e1b ldrb r3, [r3, #24]
8000a18: 2b01 cmp r3, #1
8000a1a: d108 bne.n 8000a2e <HAL_CAN_Init+0xd6>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000a1c: 687b ldr r3, [r7, #4]
8000a1e: 681b ldr r3, [r3, #0]
8000a20: 681a ldr r2, [r3, #0]
8000a22: 687b ldr r3, [r7, #4]
8000a24: 681b ldr r3, [r3, #0]
8000a26: f042 0280 orr.w r2, r2, #128 @ 0x80
8000a2a: 601a str r2, [r3, #0]
8000a2c: e007 b.n 8000a3e <HAL_CAN_Init+0xe6>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000a2e: 687b ldr r3, [r7, #4]
8000a30: 681b ldr r3, [r3, #0]
8000a32: 681a ldr r2, [r3, #0]
8000a34: 687b ldr r3, [r7, #4]
8000a36: 681b ldr r3, [r3, #0]
8000a38: f022 0280 bic.w r2, r2, #128 @ 0x80
8000a3c: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
8000a3e: 687b ldr r3, [r7, #4]
8000a40: 7e5b ldrb r3, [r3, #25]
8000a42: 2b01 cmp r3, #1
8000a44: d108 bne.n 8000a58 <HAL_CAN_Init+0x100>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000a46: 687b ldr r3, [r7, #4]
8000a48: 681b ldr r3, [r3, #0]
8000a4a: 681a ldr r2, [r3, #0]
8000a4c: 687b ldr r3, [r7, #4]
8000a4e: 681b ldr r3, [r3, #0]
8000a50: f042 0240 orr.w r2, r2, #64 @ 0x40
8000a54: 601a str r2, [r3, #0]
8000a56: e007 b.n 8000a68 <HAL_CAN_Init+0x110>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000a58: 687b ldr r3, [r7, #4]
8000a5a: 681b ldr r3, [r3, #0]
8000a5c: 681a ldr r2, [r3, #0]
8000a5e: 687b ldr r3, [r7, #4]
8000a60: 681b ldr r3, [r3, #0]
8000a62: f022 0240 bic.w r2, r2, #64 @ 0x40
8000a66: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
8000a68: 687b ldr r3, [r7, #4]
8000a6a: 7e9b ldrb r3, [r3, #26]
8000a6c: 2b01 cmp r3, #1
8000a6e: d108 bne.n 8000a82 <HAL_CAN_Init+0x12a>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000a70: 687b ldr r3, [r7, #4]
8000a72: 681b ldr r3, [r3, #0]
8000a74: 681a ldr r2, [r3, #0]
8000a76: 687b ldr r3, [r7, #4]
8000a78: 681b ldr r3, [r3, #0]
8000a7a: f042 0220 orr.w r2, r2, #32
8000a7e: 601a str r2, [r3, #0]
8000a80: e007 b.n 8000a92 <HAL_CAN_Init+0x13a>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000a82: 687b ldr r3, [r7, #4]
8000a84: 681b ldr r3, [r3, #0]
8000a86: 681a ldr r2, [r3, #0]
8000a88: 687b ldr r3, [r7, #4]
8000a8a: 681b ldr r3, [r3, #0]
8000a8c: f022 0220 bic.w r2, r2, #32
8000a90: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
8000a92: 687b ldr r3, [r7, #4]
8000a94: 7edb ldrb r3, [r3, #27]
8000a96: 2b01 cmp r3, #1
8000a98: d108 bne.n 8000aac <HAL_CAN_Init+0x154>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000a9a: 687b ldr r3, [r7, #4]
8000a9c: 681b ldr r3, [r3, #0]
8000a9e: 681a ldr r2, [r3, #0]
8000aa0: 687b ldr r3, [r7, #4]
8000aa2: 681b ldr r3, [r3, #0]
8000aa4: f022 0210 bic.w r2, r2, #16
8000aa8: 601a str r2, [r3, #0]
8000aaa: e007 b.n 8000abc <HAL_CAN_Init+0x164>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000aac: 687b ldr r3, [r7, #4]
8000aae: 681b ldr r3, [r3, #0]
8000ab0: 681a ldr r2, [r3, #0]
8000ab2: 687b ldr r3, [r7, #4]
8000ab4: 681b ldr r3, [r3, #0]
8000ab6: f042 0210 orr.w r2, r2, #16
8000aba: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
8000abc: 687b ldr r3, [r7, #4]
8000abe: 7f1b ldrb r3, [r3, #28]
8000ac0: 2b01 cmp r3, #1
8000ac2: d108 bne.n 8000ad6 <HAL_CAN_Init+0x17e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000ac4: 687b ldr r3, [r7, #4]
8000ac6: 681b ldr r3, [r3, #0]
8000ac8: 681a ldr r2, [r3, #0]
8000aca: 687b ldr r3, [r7, #4]
8000acc: 681b ldr r3, [r3, #0]
8000ace: f042 0208 orr.w r2, r2, #8
8000ad2: 601a str r2, [r3, #0]
8000ad4: e007 b.n 8000ae6 <HAL_CAN_Init+0x18e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000ad6: 687b ldr r3, [r7, #4]
8000ad8: 681b ldr r3, [r3, #0]
8000ada: 681a ldr r2, [r3, #0]
8000adc: 687b ldr r3, [r7, #4]
8000ade: 681b ldr r3, [r3, #0]
8000ae0: f022 0208 bic.w r2, r2, #8
8000ae4: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
8000ae6: 687b ldr r3, [r7, #4]
8000ae8: 7f5b ldrb r3, [r3, #29]
8000aea: 2b01 cmp r3, #1
8000aec: d108 bne.n 8000b00 <HAL_CAN_Init+0x1a8>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000aee: 687b ldr r3, [r7, #4]
8000af0: 681b ldr r3, [r3, #0]
8000af2: 681a ldr r2, [r3, #0]
8000af4: 687b ldr r3, [r7, #4]
8000af6: 681b ldr r3, [r3, #0]
8000af8: f042 0204 orr.w r2, r2, #4
8000afc: 601a str r2, [r3, #0]
8000afe: e007 b.n 8000b10 <HAL_CAN_Init+0x1b8>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000b00: 687b ldr r3, [r7, #4]
8000b02: 681b ldr r3, [r3, #0]
8000b04: 681a ldr r2, [r3, #0]
8000b06: 687b ldr r3, [r7, #4]
8000b08: 681b ldr r3, [r3, #0]
8000b0a: f022 0204 bic.w r2, r2, #4
8000b0e: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
8000b10: 687b ldr r3, [r7, #4]
8000b12: 689a ldr r2, [r3, #8]
8000b14: 687b ldr r3, [r7, #4]
8000b16: 68db ldr r3, [r3, #12]
8000b18: 431a orrs r2, r3
8000b1a: 687b ldr r3, [r7, #4]
8000b1c: 691b ldr r3, [r3, #16]
8000b1e: 431a orrs r2, r3
8000b20: 687b ldr r3, [r7, #4]
8000b22: 695b ldr r3, [r3, #20]
8000b24: ea42 0103 orr.w r1, r2, r3
8000b28: 687b ldr r3, [r7, #4]
8000b2a: 685b ldr r3, [r3, #4]
8000b2c: 1e5a subs r2, r3, #1
8000b2e: 687b ldr r3, [r7, #4]
8000b30: 681b ldr r3, [r3, #0]
8000b32: 430a orrs r2, r1
8000b34: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8000b36: 687b ldr r3, [r7, #4]
8000b38: 2200 movs r2, #0
8000b3a: 625a str r2, [r3, #36] @ 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
8000b3c: 687b ldr r3, [r7, #4]
8000b3e: 2201 movs r2, #1
8000b40: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
8000b44: 2300 movs r3, #0
}
8000b46: 4618 mov r0, r3
8000b48: 3710 adds r7, #16
8000b4a: 46bd mov sp, r7
8000b4c: bd80 pop {r7, pc}
08000b4e <HAL_CAN_IRQHandler>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
8000b4e: b580 push {r7, lr}
8000b50: b08a sub sp, #40 @ 0x28
8000b52: af00 add r7, sp, #0
8000b54: 6078 str r0, [r7, #4]
uint32_t errorcode = HAL_CAN_ERROR_NONE;
8000b56: 2300 movs r3, #0
8000b58: 627b str r3, [r7, #36] @ 0x24
uint32_t interrupts = READ_REG(hcan->Instance->IER);
8000b5a: 687b ldr r3, [r7, #4]
8000b5c: 681b ldr r3, [r3, #0]
8000b5e: 695b ldr r3, [r3, #20]
8000b60: 623b str r3, [r7, #32]
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
8000b62: 687b ldr r3, [r7, #4]
8000b64: 681b ldr r3, [r3, #0]
8000b66: 685b ldr r3, [r3, #4]
8000b68: 61fb str r3, [r7, #28]
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
8000b6a: 687b ldr r3, [r7, #4]
8000b6c: 681b ldr r3, [r3, #0]
8000b6e: 689b ldr r3, [r3, #8]
8000b70: 61bb str r3, [r7, #24]
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
8000b72: 687b ldr r3, [r7, #4]
8000b74: 681b ldr r3, [r3, #0]
8000b76: 68db ldr r3, [r3, #12]
8000b78: 617b str r3, [r7, #20]
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
8000b7a: 687b ldr r3, [r7, #4]
8000b7c: 681b ldr r3, [r3, #0]
8000b7e: 691b ldr r3, [r3, #16]
8000b80: 613b str r3, [r7, #16]
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
8000b82: 687b ldr r3, [r7, #4]
8000b84: 681b ldr r3, [r3, #0]
8000b86: 699b ldr r3, [r3, #24]
8000b88: 60fb str r3, [r7, #12]
/* Transmit Mailbox empty interrupt management *****************************/
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
8000b8a: 6a3b ldr r3, [r7, #32]
8000b8c: f003 0301 and.w r3, r3, #1
8000b90: 2b00 cmp r3, #0
8000b92: d07c beq.n 8000c8e <HAL_CAN_IRQHandler+0x140>
{
/* Transmit Mailbox 0 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
8000b94: 69bb ldr r3, [r7, #24]
8000b96: f003 0301 and.w r3, r3, #1
8000b9a: 2b00 cmp r3, #0
8000b9c: d023 beq.n 8000be6 <HAL_CAN_IRQHandler+0x98>
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
8000b9e: 687b ldr r3, [r7, #4]
8000ba0: 681b ldr r3, [r3, #0]
8000ba2: 2201 movs r2, #1
8000ba4: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
8000ba6: 69bb ldr r3, [r7, #24]
8000ba8: f003 0302 and.w r3, r3, #2
8000bac: 2b00 cmp r3, #0
8000bae: d003 beq.n 8000bb8 <HAL_CAN_IRQHandler+0x6a>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
8000bb0: 6878 ldr r0, [r7, #4]
8000bb2: f000 f983 bl 8000ebc <HAL_CAN_TxMailbox0CompleteCallback>
8000bb6: e016 b.n 8000be6 <HAL_CAN_IRQHandler+0x98>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST0) != 0U)
8000bb8: 69bb ldr r3, [r7, #24]
8000bba: f003 0304 and.w r3, r3, #4
8000bbe: 2b00 cmp r3, #0
8000bc0: d004 beq.n 8000bcc <HAL_CAN_IRQHandler+0x7e>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
8000bc2: 6a7b ldr r3, [r7, #36] @ 0x24
8000bc4: f443 6300 orr.w r3, r3, #2048 @ 0x800
8000bc8: 627b str r3, [r7, #36] @ 0x24
8000bca: e00c b.n 8000be6 <HAL_CAN_IRQHandler+0x98>
}
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
8000bcc: 69bb ldr r3, [r7, #24]
8000bce: f003 0308 and.w r3, r3, #8
8000bd2: 2b00 cmp r3, #0
8000bd4: d004 beq.n 8000be0 <HAL_CAN_IRQHandler+0x92>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
8000bd6: 6a7b ldr r3, [r7, #36] @ 0x24
8000bd8: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8000bdc: 627b str r3, [r7, #36] @ 0x24
8000bde: e002 b.n 8000be6 <HAL_CAN_IRQHandler+0x98>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
8000be0: 6878 ldr r0, [r7, #4]
8000be2: f000 f989 bl 8000ef8 <HAL_CAN_TxMailbox0AbortCallback>
}
}
}
/* Transmit Mailbox 1 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
8000be6: 69bb ldr r3, [r7, #24]
8000be8: f403 7380 and.w r3, r3, #256 @ 0x100
8000bec: 2b00 cmp r3, #0
8000bee: d024 beq.n 8000c3a <HAL_CAN_IRQHandler+0xec>
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
8000bf0: 687b ldr r3, [r7, #4]
8000bf2: 681b ldr r3, [r3, #0]
8000bf4: f44f 7280 mov.w r2, #256 @ 0x100
8000bf8: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
8000bfa: 69bb ldr r3, [r7, #24]
8000bfc: f403 7300 and.w r3, r3, #512 @ 0x200
8000c00: 2b00 cmp r3, #0
8000c02: d003 beq.n 8000c0c <HAL_CAN_IRQHandler+0xbe>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
8000c04: 6878 ldr r0, [r7, #4]
8000c06: f000 f963 bl 8000ed0 <HAL_CAN_TxMailbox1CompleteCallback>
8000c0a: e016 b.n 8000c3a <HAL_CAN_IRQHandler+0xec>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST1) != 0U)
8000c0c: 69bb ldr r3, [r7, #24]
8000c0e: f403 6380 and.w r3, r3, #1024 @ 0x400
8000c12: 2b00 cmp r3, #0
8000c14: d004 beq.n 8000c20 <HAL_CAN_IRQHandler+0xd2>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
8000c16: 6a7b ldr r3, [r7, #36] @ 0x24
8000c18: f443 5300 orr.w r3, r3, #8192 @ 0x2000
8000c1c: 627b str r3, [r7, #36] @ 0x24
8000c1e: e00c b.n 8000c3a <HAL_CAN_IRQHandler+0xec>
}
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
8000c20: 69bb ldr r3, [r7, #24]
8000c22: f403 6300 and.w r3, r3, #2048 @ 0x800
8000c26: 2b00 cmp r3, #0
8000c28: d004 beq.n 8000c34 <HAL_CAN_IRQHandler+0xe6>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
8000c2a: 6a7b ldr r3, [r7, #36] @ 0x24
8000c2c: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8000c30: 627b str r3, [r7, #36] @ 0x24
8000c32: e002 b.n 8000c3a <HAL_CAN_IRQHandler+0xec>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
8000c34: 6878 ldr r0, [r7, #4]
8000c36: f000 f969 bl 8000f0c <HAL_CAN_TxMailbox1AbortCallback>
}
}
}
/* Transmit Mailbox 2 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
8000c3a: 69bb ldr r3, [r7, #24]
8000c3c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000c40: 2b00 cmp r3, #0
8000c42: d024 beq.n 8000c8e <HAL_CAN_IRQHandler+0x140>
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
8000c44: 687b ldr r3, [r7, #4]
8000c46: 681b ldr r3, [r3, #0]
8000c48: f44f 3280 mov.w r2, #65536 @ 0x10000
8000c4c: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
8000c4e: 69bb ldr r3, [r7, #24]
8000c50: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000c54: 2b00 cmp r3, #0
8000c56: d003 beq.n 8000c60 <HAL_CAN_IRQHandler+0x112>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
8000c58: 6878 ldr r0, [r7, #4]
8000c5a: f000 f943 bl 8000ee4 <HAL_CAN_TxMailbox2CompleteCallback>
8000c5e: e016 b.n 8000c8e <HAL_CAN_IRQHandler+0x140>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST2) != 0U)
8000c60: 69bb ldr r3, [r7, #24]
8000c62: f403 2380 and.w r3, r3, #262144 @ 0x40000
8000c66: 2b00 cmp r3, #0
8000c68: d004 beq.n 8000c74 <HAL_CAN_IRQHandler+0x126>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
8000c6a: 6a7b ldr r3, [r7, #36] @ 0x24
8000c6c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8000c70: 627b str r3, [r7, #36] @ 0x24
8000c72: e00c b.n 8000c8e <HAL_CAN_IRQHandler+0x140>
}
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
8000c74: 69bb ldr r3, [r7, #24]
8000c76: f403 2300 and.w r3, r3, #524288 @ 0x80000
8000c7a: 2b00 cmp r3, #0
8000c7c: d004 beq.n 8000c88 <HAL_CAN_IRQHandler+0x13a>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
8000c7e: 6a7b ldr r3, [r7, #36] @ 0x24
8000c80: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000c84: 627b str r3, [r7, #36] @ 0x24
8000c86: e002 b.n 8000c8e <HAL_CAN_IRQHandler+0x140>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
8000c88: 6878 ldr r0, [r7, #4]
8000c8a: f000 f949 bl 8000f20 <HAL_CAN_TxMailbox2AbortCallback>
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
8000c8e: 6a3b ldr r3, [r7, #32]
8000c90: f003 0308 and.w r3, r3, #8
8000c94: 2b00 cmp r3, #0
8000c96: d00c beq.n 8000cb2 <HAL_CAN_IRQHandler+0x164>
{
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
8000c98: 697b ldr r3, [r7, #20]
8000c9a: f003 0310 and.w r3, r3, #16
8000c9e: 2b00 cmp r3, #0
8000ca0: d007 beq.n 8000cb2 <HAL_CAN_IRQHandler+0x164>
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
8000ca2: 6a7b ldr r3, [r7, #36] @ 0x24
8000ca4: f443 7300 orr.w r3, r3, #512 @ 0x200
8000ca8: 627b str r3, [r7, #36] @ 0x24
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
8000caa: 687b ldr r3, [r7, #4]
8000cac: 681b ldr r3, [r3, #0]
8000cae: 2210 movs r2, #16
8000cb0: 60da str r2, [r3, #12]
}
}
/* Receive FIFO 0 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
8000cb2: 6a3b ldr r3, [r7, #32]
8000cb4: f003 0304 and.w r3, r3, #4
8000cb8: 2b00 cmp r3, #0
8000cba: d00b beq.n 8000cd4 <HAL_CAN_IRQHandler+0x186>
{
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
8000cbc: 697b ldr r3, [r7, #20]
8000cbe: f003 0308 and.w r3, r3, #8
8000cc2: 2b00 cmp r3, #0
8000cc4: d006 beq.n 8000cd4 <HAL_CAN_IRQHandler+0x186>
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
8000cc6: 687b ldr r3, [r7, #4]
8000cc8: 681b ldr r3, [r3, #0]
8000cca: 2208 movs r2, #8
8000ccc: 60da str r2, [r3, #12]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
8000cce: 6878 ldr r0, [r7, #4]
8000cd0: f000 f93a bl 8000f48 <HAL_CAN_RxFifo0FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
8000cd4: 6a3b ldr r3, [r7, #32]
8000cd6: f003 0302 and.w r3, r3, #2
8000cda: 2b00 cmp r3, #0
8000cdc: d009 beq.n 8000cf2 <HAL_CAN_IRQHandler+0x1a4>
{
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
8000cde: 687b ldr r3, [r7, #4]
8000ce0: 681b ldr r3, [r3, #0]
8000ce2: 68db ldr r3, [r3, #12]
8000ce4: f003 0303 and.w r3, r3, #3
8000ce8: 2b00 cmp r3, #0
8000cea: d002 beq.n 8000cf2 <HAL_CAN_IRQHandler+0x1a4>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
8000cec: 6878 ldr r0, [r7, #4]
8000cee: f000 f921 bl 8000f34 <HAL_CAN_RxFifo0MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
8000cf2: 6a3b ldr r3, [r7, #32]
8000cf4: f003 0340 and.w r3, r3, #64 @ 0x40
8000cf8: 2b00 cmp r3, #0
8000cfa: d00c beq.n 8000d16 <HAL_CAN_IRQHandler+0x1c8>
{
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
8000cfc: 693b ldr r3, [r7, #16]
8000cfe: f003 0310 and.w r3, r3, #16
8000d02: 2b00 cmp r3, #0
8000d04: d007 beq.n 8000d16 <HAL_CAN_IRQHandler+0x1c8>
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
8000d06: 6a7b ldr r3, [r7, #36] @ 0x24
8000d08: f443 6380 orr.w r3, r3, #1024 @ 0x400
8000d0c: 627b str r3, [r7, #36] @ 0x24
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
8000d0e: 687b ldr r3, [r7, #4]
8000d10: 681b ldr r3, [r3, #0]
8000d12: 2210 movs r2, #16
8000d14: 611a str r2, [r3, #16]
}
}
/* Receive FIFO 1 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
8000d16: 6a3b ldr r3, [r7, #32]
8000d18: f003 0320 and.w r3, r3, #32
8000d1c: 2b00 cmp r3, #0
8000d1e: d00b beq.n 8000d38 <HAL_CAN_IRQHandler+0x1ea>
{
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
8000d20: 693b ldr r3, [r7, #16]
8000d22: f003 0308 and.w r3, r3, #8
8000d26: 2b00 cmp r3, #0
8000d28: d006 beq.n 8000d38 <HAL_CAN_IRQHandler+0x1ea>
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
8000d2a: 687b ldr r3, [r7, #4]
8000d2c: 681b ldr r3, [r3, #0]
8000d2e: 2208 movs r2, #8
8000d30: 611a str r2, [r3, #16]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
8000d32: 6878 ldr r0, [r7, #4]
8000d34: f000 f91c bl 8000f70 <HAL_CAN_RxFifo1FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
8000d38: 6a3b ldr r3, [r7, #32]
8000d3a: f003 0310 and.w r3, r3, #16
8000d3e: 2b00 cmp r3, #0
8000d40: d009 beq.n 8000d56 <HAL_CAN_IRQHandler+0x208>
{
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
8000d42: 687b ldr r3, [r7, #4]
8000d44: 681b ldr r3, [r3, #0]
8000d46: 691b ldr r3, [r3, #16]
8000d48: f003 0303 and.w r3, r3, #3
8000d4c: 2b00 cmp r3, #0
8000d4e: d002 beq.n 8000d56 <HAL_CAN_IRQHandler+0x208>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
8000d50: 6878 ldr r0, [r7, #4]
8000d52: f000 f903 bl 8000f5c <HAL_CAN_RxFifo1MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
8000d56: 6a3b ldr r3, [r7, #32]
8000d58: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000d5c: 2b00 cmp r3, #0
8000d5e: d00b beq.n 8000d78 <HAL_CAN_IRQHandler+0x22a>
{
if ((msrflags & CAN_MSR_SLAKI) != 0U)
8000d60: 69fb ldr r3, [r7, #28]
8000d62: f003 0310 and.w r3, r3, #16
8000d66: 2b00 cmp r3, #0
8000d68: d006 beq.n 8000d78 <HAL_CAN_IRQHandler+0x22a>
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
8000d6a: 687b ldr r3, [r7, #4]
8000d6c: 681b ldr r3, [r3, #0]
8000d6e: 2210 movs r2, #16
8000d70: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->SleepCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
8000d72: 6878 ldr r0, [r7, #4]
8000d74: f000 f906 bl 8000f84 <HAL_CAN_SleepCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
if ((interrupts & CAN_IT_WAKEUP) != 0U)
8000d78: 6a3b ldr r3, [r7, #32]
8000d7a: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000d7e: 2b00 cmp r3, #0
8000d80: d00b beq.n 8000d9a <HAL_CAN_IRQHandler+0x24c>
{
if ((msrflags & CAN_MSR_WKUI) != 0U)
8000d82: 69fb ldr r3, [r7, #28]
8000d84: f003 0308 and.w r3, r3, #8
8000d88: 2b00 cmp r3, #0
8000d8a: d006 beq.n 8000d9a <HAL_CAN_IRQHandler+0x24c>
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
8000d8c: 687b ldr r3, [r7, #4]
8000d8e: 681b ldr r3, [r3, #0]
8000d90: 2208 movs r2, #8
8000d92: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->WakeUpFromRxMsgCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
8000d94: 6878 ldr r0, [r7, #4]
8000d96: f000 f8ff bl 8000f98 <HAL_CAN_WakeUpFromRxMsgCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
if ((interrupts & CAN_IT_ERROR) != 0U)
8000d9a: 6a3b ldr r3, [r7, #32]
8000d9c: f403 4300 and.w r3, r3, #32768 @ 0x8000
8000da0: 2b00 cmp r3, #0
8000da2: d07b beq.n 8000e9c <HAL_CAN_IRQHandler+0x34e>
{
if ((msrflags & CAN_MSR_ERRI) != 0U)
8000da4: 69fb ldr r3, [r7, #28]
8000da6: f003 0304 and.w r3, r3, #4
8000daa: 2b00 cmp r3, #0
8000dac: d072 beq.n 8000e94 <HAL_CAN_IRQHandler+0x346>
{
/* Check Error Warning Flag */
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
8000dae: 6a3b ldr r3, [r7, #32]
8000db0: f403 7380 and.w r3, r3, #256 @ 0x100
8000db4: 2b00 cmp r3, #0
8000db6: d008 beq.n 8000dca <HAL_CAN_IRQHandler+0x27c>
((esrflags & CAN_ESR_EWGF) != 0U))
8000db8: 68fb ldr r3, [r7, #12]
8000dba: f003 0301 and.w r3, r3, #1
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
8000dbe: 2b00 cmp r3, #0
8000dc0: d003 beq.n 8000dca <HAL_CAN_IRQHandler+0x27c>
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
8000dc2: 6a7b ldr r3, [r7, #36] @ 0x24
8000dc4: f043 0301 orr.w r3, r3, #1
8000dc8: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Warning Flag as read-only */
}
/* Check Error Passive Flag */
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8000dca: 6a3b ldr r3, [r7, #32]
8000dcc: f403 7300 and.w r3, r3, #512 @ 0x200
8000dd0: 2b00 cmp r3, #0
8000dd2: d008 beq.n 8000de6 <HAL_CAN_IRQHandler+0x298>
((esrflags & CAN_ESR_EPVF) != 0U))
8000dd4: 68fb ldr r3, [r7, #12]
8000dd6: f003 0302 and.w r3, r3, #2
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8000dda: 2b00 cmp r3, #0
8000ddc: d003 beq.n 8000de6 <HAL_CAN_IRQHandler+0x298>
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
8000dde: 6a7b ldr r3, [r7, #36] @ 0x24
8000de0: f043 0302 orr.w r3, r3, #2
8000de4: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Passive Flag as read-only */
}
/* Check Bus-off Flag */
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
8000de6: 6a3b ldr r3, [r7, #32]
8000de8: f403 6380 and.w r3, r3, #1024 @ 0x400
8000dec: 2b00 cmp r3, #0
8000dee: d008 beq.n 8000e02 <HAL_CAN_IRQHandler+0x2b4>
((esrflags & CAN_ESR_BOFF) != 0U))
8000df0: 68fb ldr r3, [r7, #12]
8000df2: f003 0304 and.w r3, r3, #4
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
8000df6: 2b00 cmp r3, #0
8000df8: d003 beq.n 8000e02 <HAL_CAN_IRQHandler+0x2b4>
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
8000dfa: 6a7b ldr r3, [r7, #36] @ 0x24
8000dfc: f043 0304 orr.w r3, r3, #4
8000e00: 627b str r3, [r7, #36] @ 0x24
/* No need for clear of Error Bus-Off as read-only */
}
/* Check Last Error Code Flag */
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
8000e02: 6a3b ldr r3, [r7, #32]
8000e04: f403 6300 and.w r3, r3, #2048 @ 0x800
8000e08: 2b00 cmp r3, #0
8000e0a: d043 beq.n 8000e94 <HAL_CAN_IRQHandler+0x346>
((esrflags & CAN_ESR_LEC) != 0U))
8000e0c: 68fb ldr r3, [r7, #12]
8000e0e: f003 0370 and.w r3, r3, #112 @ 0x70
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
8000e12: 2b00 cmp r3, #0
8000e14: d03e beq.n 8000e94 <HAL_CAN_IRQHandler+0x346>
{
switch (esrflags & CAN_ESR_LEC)
8000e16: 68fb ldr r3, [r7, #12]
8000e18: f003 0370 and.w r3, r3, #112 @ 0x70
8000e1c: 2b60 cmp r3, #96 @ 0x60
8000e1e: d02b beq.n 8000e78 <HAL_CAN_IRQHandler+0x32a>
8000e20: 2b60 cmp r3, #96 @ 0x60
8000e22: d82e bhi.n 8000e82 <HAL_CAN_IRQHandler+0x334>
8000e24: 2b50 cmp r3, #80 @ 0x50
8000e26: d022 beq.n 8000e6e <HAL_CAN_IRQHandler+0x320>
8000e28: 2b50 cmp r3, #80 @ 0x50
8000e2a: d82a bhi.n 8000e82 <HAL_CAN_IRQHandler+0x334>
8000e2c: 2b40 cmp r3, #64 @ 0x40
8000e2e: d019 beq.n 8000e64 <HAL_CAN_IRQHandler+0x316>
8000e30: 2b40 cmp r3, #64 @ 0x40
8000e32: d826 bhi.n 8000e82 <HAL_CAN_IRQHandler+0x334>
8000e34: 2b30 cmp r3, #48 @ 0x30
8000e36: d010 beq.n 8000e5a <HAL_CAN_IRQHandler+0x30c>
8000e38: 2b30 cmp r3, #48 @ 0x30
8000e3a: d822 bhi.n 8000e82 <HAL_CAN_IRQHandler+0x334>
8000e3c: 2b10 cmp r3, #16
8000e3e: d002 beq.n 8000e46 <HAL_CAN_IRQHandler+0x2f8>
8000e40: 2b20 cmp r3, #32
8000e42: d005 beq.n 8000e50 <HAL_CAN_IRQHandler+0x302>
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
/* Set CAN error code to CRC error */
errorcode |= HAL_CAN_ERROR_CRC;
break;
default:
break;
8000e44: e01d b.n 8000e82 <HAL_CAN_IRQHandler+0x334>
errorcode |= HAL_CAN_ERROR_STF;
8000e46: 6a7b ldr r3, [r7, #36] @ 0x24
8000e48: f043 0308 orr.w r3, r3, #8
8000e4c: 627b str r3, [r7, #36] @ 0x24
break;
8000e4e: e019 b.n 8000e84 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_FOR;
8000e50: 6a7b ldr r3, [r7, #36] @ 0x24
8000e52: f043 0310 orr.w r3, r3, #16
8000e56: 627b str r3, [r7, #36] @ 0x24
break;
8000e58: e014 b.n 8000e84 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_ACK;
8000e5a: 6a7b ldr r3, [r7, #36] @ 0x24
8000e5c: f043 0320 orr.w r3, r3, #32
8000e60: 627b str r3, [r7, #36] @ 0x24
break;
8000e62: e00f b.n 8000e84 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BR;
8000e64: 6a7b ldr r3, [r7, #36] @ 0x24
8000e66: f043 0340 orr.w r3, r3, #64 @ 0x40
8000e6a: 627b str r3, [r7, #36] @ 0x24
break;
8000e6c: e00a b.n 8000e84 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BD;
8000e6e: 6a7b ldr r3, [r7, #36] @ 0x24
8000e70: f043 0380 orr.w r3, r3, #128 @ 0x80
8000e74: 627b str r3, [r7, #36] @ 0x24
break;
8000e76: e005 b.n 8000e84 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_CRC;
8000e78: 6a7b ldr r3, [r7, #36] @ 0x24
8000e7a: f443 7380 orr.w r3, r3, #256 @ 0x100
8000e7e: 627b str r3, [r7, #36] @ 0x24
break;
8000e80: e000 b.n 8000e84 <HAL_CAN_IRQHandler+0x336>
break;
8000e82: bf00 nop
}
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
8000e84: 687b ldr r3, [r7, #4]
8000e86: 681b ldr r3, [r3, #0]
8000e88: 699a ldr r2, [r3, #24]
8000e8a: 687b ldr r3, [r7, #4]
8000e8c: 681b ldr r3, [r3, #0]
8000e8e: f022 0270 bic.w r2, r2, #112 @ 0x70
8000e92: 619a str r2, [r3, #24]
}
}
/* Clear ERRI Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
8000e94: 687b ldr r3, [r7, #4]
8000e96: 681b ldr r3, [r3, #0]
8000e98: 2204 movs r2, #4
8000e9a: 605a str r2, [r3, #4]
}
/* Call the Error call Back in case of Errors */
if (errorcode != HAL_CAN_ERROR_NONE)
8000e9c: 6a7b ldr r3, [r7, #36] @ 0x24
8000e9e: 2b00 cmp r3, #0
8000ea0: d008 beq.n 8000eb4 <HAL_CAN_IRQHandler+0x366>
{
/* Update error code in handle */
hcan->ErrorCode |= errorcode;
8000ea2: 687b ldr r3, [r7, #4]
8000ea4: 6a5a ldr r2, [r3, #36] @ 0x24
8000ea6: 6a7b ldr r3, [r7, #36] @ 0x24
8000ea8: 431a orrs r2, r3
8000eaa: 687b ldr r3, [r7, #4]
8000eac: 625a str r2, [r3, #36] @ 0x24
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->ErrorCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
8000eae: 6878 ldr r0, [r7, #4]
8000eb0: f000 f87c bl 8000fac <HAL_CAN_ErrorCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
8000eb4: bf00 nop
8000eb6: 3728 adds r7, #40 @ 0x28
8000eb8: 46bd mov sp, r7
8000eba: bd80 pop {r7, pc}
08000ebc <HAL_CAN_TxMailbox0CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
8000ebc: b480 push {r7}
8000ebe: b083 sub sp, #12
8000ec0: af00 add r7, sp, #0
8000ec2: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
user file
*/
}
8000ec4: bf00 nop
8000ec6: 370c adds r7, #12
8000ec8: 46bd mov sp, r7
8000eca: f85d 7b04 ldr.w r7, [sp], #4
8000ece: 4770 bx lr
08000ed0 <HAL_CAN_TxMailbox1CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
8000ed0: b480 push {r7}
8000ed2: b083 sub sp, #12
8000ed4: af00 add r7, sp, #0
8000ed6: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
user file
*/
}
8000ed8: bf00 nop
8000eda: 370c adds r7, #12
8000edc: 46bd mov sp, r7
8000ede: f85d 7b04 ldr.w r7, [sp], #4
8000ee2: 4770 bx lr
08000ee4 <HAL_CAN_TxMailbox2CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
8000ee4: b480 push {r7}
8000ee6: b083 sub sp, #12
8000ee8: af00 add r7, sp, #0
8000eea: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
user file
*/
}
8000eec: bf00 nop
8000eee: 370c adds r7, #12
8000ef0: 46bd mov sp, r7
8000ef2: f85d 7b04 ldr.w r7, [sp], #4
8000ef6: 4770 bx lr
08000ef8 <HAL_CAN_TxMailbox0AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
8000ef8: b480 push {r7}
8000efa: b083 sub sp, #12
8000efc: af00 add r7, sp, #0
8000efe: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
user file
*/
}
8000f00: bf00 nop
8000f02: 370c adds r7, #12
8000f04: 46bd mov sp, r7
8000f06: f85d 7b04 ldr.w r7, [sp], #4
8000f0a: 4770 bx lr
08000f0c <HAL_CAN_TxMailbox1AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
8000f0c: b480 push {r7}
8000f0e: b083 sub sp, #12
8000f10: af00 add r7, sp, #0
8000f12: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
user file
*/
}
8000f14: bf00 nop
8000f16: 370c adds r7, #12
8000f18: 46bd mov sp, r7
8000f1a: f85d 7b04 ldr.w r7, [sp], #4
8000f1e: 4770 bx lr
08000f20 <HAL_CAN_TxMailbox2AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
8000f20: b480 push {r7}
8000f22: b083 sub sp, #12
8000f24: af00 add r7, sp, #0
8000f26: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
user file
*/
}
8000f28: bf00 nop
8000f2a: 370c adds r7, #12
8000f2c: 46bd mov sp, r7
8000f2e: f85d 7b04 ldr.w r7, [sp], #4
8000f32: 4770 bx lr
08000f34 <HAL_CAN_RxFifo0MsgPendingCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
8000f34: b480 push {r7}
8000f36: b083 sub sp, #12
8000f38: af00 add r7, sp, #0
8000f3a: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
user file
*/
}
8000f3c: bf00 nop
8000f3e: 370c adds r7, #12
8000f40: 46bd mov sp, r7
8000f42: f85d 7b04 ldr.w r7, [sp], #4
8000f46: 4770 bx lr
08000f48 <HAL_CAN_RxFifo0FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
8000f48: b480 push {r7}
8000f4a: b083 sub sp, #12
8000f4c: af00 add r7, sp, #0
8000f4e: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
file
*/
}
8000f50: bf00 nop
8000f52: 370c adds r7, #12
8000f54: 46bd mov sp, r7
8000f56: f85d 7b04 ldr.w r7, [sp], #4
8000f5a: 4770 bx lr
08000f5c <HAL_CAN_RxFifo1MsgPendingCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
8000f5c: b480 push {r7}
8000f5e: b083 sub sp, #12
8000f60: af00 add r7, sp, #0
8000f62: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
user file
*/
}
8000f64: bf00 nop
8000f66: 370c adds r7, #12
8000f68: 46bd mov sp, r7
8000f6a: f85d 7b04 ldr.w r7, [sp], #4
8000f6e: 4770 bx lr
08000f70 <HAL_CAN_RxFifo1FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
8000f70: b480 push {r7}
8000f72: b083 sub sp, #12
8000f74: af00 add r7, sp, #0
8000f76: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
file
*/
}
8000f78: bf00 nop
8000f7a: 370c adds r7, #12
8000f7c: 46bd mov sp, r7
8000f7e: f85d 7b04 ldr.w r7, [sp], #4
8000f82: 4770 bx lr
08000f84 <HAL_CAN_SleepCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
8000f84: b480 push {r7}
8000f86: b083 sub sp, #12
8000f88: af00 add r7, sp, #0
8000f8a: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_SleepCallback could be implemented in the user file
*/
}
8000f8c: bf00 nop
8000f8e: 370c adds r7, #12
8000f90: 46bd mov sp, r7
8000f92: f85d 7b04 ldr.w r7, [sp], #4
8000f96: 4770 bx lr
08000f98 <HAL_CAN_WakeUpFromRxMsgCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
8000f98: b480 push {r7}
8000f9a: b083 sub sp, #12
8000f9c: af00 add r7, sp, #0
8000f9e: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
user file
*/
}
8000fa0: bf00 nop
8000fa2: 370c adds r7, #12
8000fa4: 46bd mov sp, r7
8000fa6: f85d 7b04 ldr.w r7, [sp], #4
8000faa: 4770 bx lr
08000fac <HAL_CAN_ErrorCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
8000fac: b480 push {r7}
8000fae: b083 sub sp, #12
8000fb0: af00 add r7, sp, #0
8000fb2: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
8000fb4: bf00 nop
8000fb6: 370c adds r7, #12
8000fb8: 46bd mov sp, r7
8000fba: f85d 7b04 ldr.w r7, [sp], #4
8000fbe: 4770 bx lr
08000fc0 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000fc0: b480 push {r7}
8000fc2: b085 sub sp, #20
8000fc4: af00 add r7, sp, #0
8000fc6: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000fc8: 687b ldr r3, [r7, #4]
8000fca: f003 0307 and.w r3, r3, #7
8000fce: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000fd0: 4b0c ldr r3, [pc, #48] @ (8001004 <__NVIC_SetPriorityGrouping+0x44>)
8000fd2: 68db ldr r3, [r3, #12]
8000fd4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000fd6: 68ba ldr r2, [r7, #8]
8000fd8: f64f 03ff movw r3, #63743 @ 0xf8ff
8000fdc: 4013 ands r3, r2
8000fde: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000fe0: 68fb ldr r3, [r7, #12]
8000fe2: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000fe4: 68bb ldr r3, [r7, #8]
8000fe6: 4313 orrs r3, r2
reg_value = (reg_value |
8000fe8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8000fec: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000ff0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000ff2: 4a04 ldr r2, [pc, #16] @ (8001004 <__NVIC_SetPriorityGrouping+0x44>)
8000ff4: 68bb ldr r3, [r7, #8]
8000ff6: 60d3 str r3, [r2, #12]
}
8000ff8: bf00 nop
8000ffa: 3714 adds r7, #20
8000ffc: 46bd mov sp, r7
8000ffe: f85d 7b04 ldr.w r7, [sp], #4
8001002: 4770 bx lr
8001004: e000ed00 .word 0xe000ed00
08001008 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8001008: b480 push {r7}
800100a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
800100c: 4b04 ldr r3, [pc, #16] @ (8001020 <__NVIC_GetPriorityGrouping+0x18>)
800100e: 68db ldr r3, [r3, #12]
8001010: 0a1b lsrs r3, r3, #8
8001012: f003 0307 and.w r3, r3, #7
}
8001016: 4618 mov r0, r3
8001018: 46bd mov sp, r7
800101a: f85d 7b04 ldr.w r7, [sp], #4
800101e: 4770 bx lr
8001020: e000ed00 .word 0xe000ed00
08001024 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001024: b480 push {r7}
8001026: b083 sub sp, #12
8001028: af00 add r7, sp, #0
800102a: 4603 mov r3, r0
800102c: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800102e: f997 3007 ldrsb.w r3, [r7, #7]
8001032: 2b00 cmp r3, #0
8001034: db0b blt.n 800104e <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8001036: 79fb ldrb r3, [r7, #7]
8001038: f003 021f and.w r2, r3, #31
800103c: 4907 ldr r1, [pc, #28] @ (800105c <__NVIC_EnableIRQ+0x38>)
800103e: f997 3007 ldrsb.w r3, [r7, #7]
8001042: 095b lsrs r3, r3, #5
8001044: 2001 movs r0, #1
8001046: fa00 f202 lsl.w r2, r0, r2
800104a: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
800104e: bf00 nop
8001050: 370c adds r7, #12
8001052: 46bd mov sp, r7
8001054: f85d 7b04 ldr.w r7, [sp], #4
8001058: 4770 bx lr
800105a: bf00 nop
800105c: e000e100 .word 0xe000e100
08001060 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001060: b480 push {r7}
8001062: b083 sub sp, #12
8001064: af00 add r7, sp, #0
8001066: 4603 mov r3, r0
8001068: 6039 str r1, [r7, #0]
800106a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800106c: f997 3007 ldrsb.w r3, [r7, #7]
8001070: 2b00 cmp r3, #0
8001072: db0a blt.n 800108a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001074: 683b ldr r3, [r7, #0]
8001076: b2da uxtb r2, r3
8001078: 490c ldr r1, [pc, #48] @ (80010ac <__NVIC_SetPriority+0x4c>)
800107a: f997 3007 ldrsb.w r3, [r7, #7]
800107e: 0112 lsls r2, r2, #4
8001080: b2d2 uxtb r2, r2
8001082: 440b add r3, r1
8001084: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001088: e00a b.n 80010a0 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800108a: 683b ldr r3, [r7, #0]
800108c: b2da uxtb r2, r3
800108e: 4908 ldr r1, [pc, #32] @ (80010b0 <__NVIC_SetPriority+0x50>)
8001090: 79fb ldrb r3, [r7, #7]
8001092: f003 030f and.w r3, r3, #15
8001096: 3b04 subs r3, #4
8001098: 0112 lsls r2, r2, #4
800109a: b2d2 uxtb r2, r2
800109c: 440b add r3, r1
800109e: 761a strb r2, [r3, #24]
}
80010a0: bf00 nop
80010a2: 370c adds r7, #12
80010a4: 46bd mov sp, r7
80010a6: f85d 7b04 ldr.w r7, [sp], #4
80010aa: 4770 bx lr
80010ac: e000e100 .word 0xe000e100
80010b0: e000ed00 .word 0xe000ed00
080010b4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80010b4: b480 push {r7}
80010b6: b089 sub sp, #36 @ 0x24
80010b8: af00 add r7, sp, #0
80010ba: 60f8 str r0, [r7, #12]
80010bc: 60b9 str r1, [r7, #8]
80010be: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80010c0: 68fb ldr r3, [r7, #12]
80010c2: f003 0307 and.w r3, r3, #7
80010c6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80010c8: 69fb ldr r3, [r7, #28]
80010ca: f1c3 0307 rsb r3, r3, #7
80010ce: 2b04 cmp r3, #4
80010d0: bf28 it cs
80010d2: 2304 movcs r3, #4
80010d4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80010d6: 69fb ldr r3, [r7, #28]
80010d8: 3304 adds r3, #4
80010da: 2b06 cmp r3, #6
80010dc: d902 bls.n 80010e4 <NVIC_EncodePriority+0x30>
80010de: 69fb ldr r3, [r7, #28]
80010e0: 3b03 subs r3, #3
80010e2: e000 b.n 80010e6 <NVIC_EncodePriority+0x32>
80010e4: 2300 movs r3, #0
80010e6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80010e8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80010ec: 69bb ldr r3, [r7, #24]
80010ee: fa02 f303 lsl.w r3, r2, r3
80010f2: 43da mvns r2, r3
80010f4: 68bb ldr r3, [r7, #8]
80010f6: 401a ands r2, r3
80010f8: 697b ldr r3, [r7, #20]
80010fa: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80010fc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8001100: 697b ldr r3, [r7, #20]
8001102: fa01 f303 lsl.w r3, r1, r3
8001106: 43d9 mvns r1, r3
8001108: 687b ldr r3, [r7, #4]
800110a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800110c: 4313 orrs r3, r2
);
}
800110e: 4618 mov r0, r3
8001110: 3724 adds r7, #36 @ 0x24
8001112: 46bd mov sp, r7
8001114: f85d 7b04 ldr.w r7, [sp], #4
8001118: 4770 bx lr
...
0800111c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
800111c: b580 push {r7, lr}
800111e: b082 sub sp, #8
8001120: af00 add r7, sp, #0
8001122: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001124: 687b ldr r3, [r7, #4]
8001126: 3b01 subs r3, #1
8001128: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
800112c: d301 bcc.n 8001132 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800112e: 2301 movs r3, #1
8001130: e00f b.n 8001152 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001132: 4a0a ldr r2, [pc, #40] @ (800115c <SysTick_Config+0x40>)
8001134: 687b ldr r3, [r7, #4]
8001136: 3b01 subs r3, #1
8001138: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800113a: 210f movs r1, #15
800113c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8001140: f7ff ff8e bl 8001060 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001144: 4b05 ldr r3, [pc, #20] @ (800115c <SysTick_Config+0x40>)
8001146: 2200 movs r2, #0
8001148: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800114a: 4b04 ldr r3, [pc, #16] @ (800115c <SysTick_Config+0x40>)
800114c: 2207 movs r2, #7
800114e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001150: 2300 movs r3, #0
}
8001152: 4618 mov r0, r3
8001154: 3708 adds r7, #8
8001156: 46bd mov sp, r7
8001158: bd80 pop {r7, pc}
800115a: bf00 nop
800115c: e000e010 .word 0xe000e010
08001160 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001160: b580 push {r7, lr}
8001162: b082 sub sp, #8
8001164: af00 add r7, sp, #0
8001166: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001168: 6878 ldr r0, [r7, #4]
800116a: f7ff ff29 bl 8000fc0 <__NVIC_SetPriorityGrouping>
}
800116e: bf00 nop
8001170: 3708 adds r7, #8
8001172: 46bd mov sp, r7
8001174: bd80 pop {r7, pc}
08001176 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001176: b580 push {r7, lr}
8001178: b086 sub sp, #24
800117a: af00 add r7, sp, #0
800117c: 4603 mov r3, r0
800117e: 60b9 str r1, [r7, #8]
8001180: 607a str r2, [r7, #4]
8001182: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8001184: 2300 movs r3, #0
8001186: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001188: f7ff ff3e bl 8001008 <__NVIC_GetPriorityGrouping>
800118c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800118e: 687a ldr r2, [r7, #4]
8001190: 68b9 ldr r1, [r7, #8]
8001192: 6978 ldr r0, [r7, #20]
8001194: f7ff ff8e bl 80010b4 <NVIC_EncodePriority>
8001198: 4602 mov r2, r0
800119a: f997 300f ldrsb.w r3, [r7, #15]
800119e: 4611 mov r1, r2
80011a0: 4618 mov r0, r3
80011a2: f7ff ff5d bl 8001060 <__NVIC_SetPriority>
}
80011a6: bf00 nop
80011a8: 3718 adds r7, #24
80011aa: 46bd mov sp, r7
80011ac: bd80 pop {r7, pc}
080011ae <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80011ae: b580 push {r7, lr}
80011b0: b082 sub sp, #8
80011b2: af00 add r7, sp, #0
80011b4: 4603 mov r3, r0
80011b6: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80011b8: f997 3007 ldrsb.w r3, [r7, #7]
80011bc: 4618 mov r0, r3
80011be: f7ff ff31 bl 8001024 <__NVIC_EnableIRQ>
}
80011c2: bf00 nop
80011c4: 3708 adds r7, #8
80011c6: 46bd mov sp, r7
80011c8: bd80 pop {r7, pc}
080011ca <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80011ca: b580 push {r7, lr}
80011cc: b082 sub sp, #8
80011ce: af00 add r7, sp, #0
80011d0: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80011d2: 6878 ldr r0, [r7, #4]
80011d4: f7ff ffa2 bl 800111c <SysTick_Config>
80011d8: 4603 mov r3, r0
}
80011da: 4618 mov r0, r3
80011dc: 3708 adds r7, #8
80011de: 46bd mov sp, r7
80011e0: bd80 pop {r7, pc}
...
080011e4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80011e4: b480 push {r7}
80011e6: b087 sub sp, #28
80011e8: af00 add r7, sp, #0
80011ea: 6078 str r0, [r7, #4]
80011ec: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80011ee: 2300 movs r3, #0
80011f0: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80011f2: e154 b.n 800149e <HAL_GPIO_Init+0x2ba>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
80011f4: 683b ldr r3, [r7, #0]
80011f6: 681a ldr r2, [r3, #0]
80011f8: 2101 movs r1, #1
80011fa: 697b ldr r3, [r7, #20]
80011fc: fa01 f303 lsl.w r3, r1, r3
8001200: 4013 ands r3, r2
8001202: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001204: 68fb ldr r3, [r7, #12]
8001206: 2b00 cmp r3, #0
8001208: f000 8146 beq.w 8001498 <HAL_GPIO_Init+0x2b4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
800120c: 683b ldr r3, [r7, #0]
800120e: 685b ldr r3, [r3, #4]
8001210: f003 0303 and.w r3, r3, #3
8001214: 2b01 cmp r3, #1
8001216: d005 beq.n 8001224 <HAL_GPIO_Init+0x40>
8001218: 683b ldr r3, [r7, #0]
800121a: 685b ldr r3, [r3, #4]
800121c: f003 0303 and.w r3, r3, #3
8001220: 2b02 cmp r3, #2
8001222: d130 bne.n 8001286 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001224: 687b ldr r3, [r7, #4]
8001226: 689b ldr r3, [r3, #8]
8001228: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
800122a: 697b ldr r3, [r7, #20]
800122c: 005b lsls r3, r3, #1
800122e: 2203 movs r2, #3
8001230: fa02 f303 lsl.w r3, r2, r3
8001234: 43db mvns r3, r3
8001236: 693a ldr r2, [r7, #16]
8001238: 4013 ands r3, r2
800123a: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
800123c: 683b ldr r3, [r7, #0]
800123e: 68da ldr r2, [r3, #12]
8001240: 697b ldr r3, [r7, #20]
8001242: 005b lsls r3, r3, #1
8001244: fa02 f303 lsl.w r3, r2, r3
8001248: 693a ldr r2, [r7, #16]
800124a: 4313 orrs r3, r2
800124c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800124e: 687b ldr r3, [r7, #4]
8001250: 693a ldr r2, [r7, #16]
8001252: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001254: 687b ldr r3, [r7, #4]
8001256: 685b ldr r3, [r3, #4]
8001258: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
800125a: 2201 movs r2, #1
800125c: 697b ldr r3, [r7, #20]
800125e: fa02 f303 lsl.w r3, r2, r3
8001262: 43db mvns r3, r3
8001264: 693a ldr r2, [r7, #16]
8001266: 4013 ands r3, r2
8001268: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800126a: 683b ldr r3, [r7, #0]
800126c: 685b ldr r3, [r3, #4]
800126e: 091b lsrs r3, r3, #4
8001270: f003 0201 and.w r2, r3, #1
8001274: 697b ldr r3, [r7, #20]
8001276: fa02 f303 lsl.w r3, r2, r3
800127a: 693a ldr r2, [r7, #16]
800127c: 4313 orrs r3, r2
800127e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001280: 687b ldr r3, [r7, #4]
8001282: 693a ldr r2, [r7, #16]
8001284: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001286: 683b ldr r3, [r7, #0]
8001288: 685b ldr r3, [r3, #4]
800128a: f003 0303 and.w r3, r3, #3
800128e: 2b03 cmp r3, #3
8001290: d017 beq.n 80012c2 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001292: 687b ldr r3, [r7, #4]
8001294: 68db ldr r3, [r3, #12]
8001296: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8001298: 697b ldr r3, [r7, #20]
800129a: 005b lsls r3, r3, #1
800129c: 2203 movs r2, #3
800129e: fa02 f303 lsl.w r3, r2, r3
80012a2: 43db mvns r3, r3
80012a4: 693a ldr r2, [r7, #16]
80012a6: 4013 ands r3, r2
80012a8: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80012aa: 683b ldr r3, [r7, #0]
80012ac: 689a ldr r2, [r3, #8]
80012ae: 697b ldr r3, [r7, #20]
80012b0: 005b lsls r3, r3, #1
80012b2: fa02 f303 lsl.w r3, r2, r3
80012b6: 693a ldr r2, [r7, #16]
80012b8: 4313 orrs r3, r2
80012ba: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80012bc: 687b ldr r3, [r7, #4]
80012be: 693a ldr r2, [r7, #16]
80012c0: 60da str r2, [r3, #12]
}
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80012c2: 683b ldr r3, [r7, #0]
80012c4: 685b ldr r3, [r3, #4]
80012c6: f003 0303 and.w r3, r3, #3
80012ca: 2b02 cmp r3, #2
80012cc: d123 bne.n 8001316 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
80012ce: 697b ldr r3, [r7, #20]
80012d0: 08da lsrs r2, r3, #3
80012d2: 687b ldr r3, [r7, #4]
80012d4: 3208 adds r2, #8
80012d6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80012da: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
80012dc: 697b ldr r3, [r7, #20]
80012de: f003 0307 and.w r3, r3, #7
80012e2: 009b lsls r3, r3, #2
80012e4: 220f movs r2, #15
80012e6: fa02 f303 lsl.w r3, r2, r3
80012ea: 43db mvns r3, r3
80012ec: 693a ldr r2, [r7, #16]
80012ee: 4013 ands r3, r2
80012f0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
80012f2: 683b ldr r3, [r7, #0]
80012f4: 691a ldr r2, [r3, #16]
80012f6: 697b ldr r3, [r7, #20]
80012f8: f003 0307 and.w r3, r3, #7
80012fc: 009b lsls r3, r3, #2
80012fe: fa02 f303 lsl.w r3, r2, r3
8001302: 693a ldr r2, [r7, #16]
8001304: 4313 orrs r3, r2
8001306: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001308: 697b ldr r3, [r7, #20]
800130a: 08da lsrs r2, r3, #3
800130c: 687b ldr r3, [r7, #4]
800130e: 3208 adds r2, #8
8001310: 6939 ldr r1, [r7, #16]
8001312: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001316: 687b ldr r3, [r7, #4]
8001318: 681b ldr r3, [r3, #0]
800131a: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
800131c: 697b ldr r3, [r7, #20]
800131e: 005b lsls r3, r3, #1
8001320: 2203 movs r2, #3
8001322: fa02 f303 lsl.w r3, r2, r3
8001326: 43db mvns r3, r3
8001328: 693a ldr r2, [r7, #16]
800132a: 4013 ands r3, r2
800132c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
800132e: 683b ldr r3, [r7, #0]
8001330: 685b ldr r3, [r3, #4]
8001332: f003 0203 and.w r2, r3, #3
8001336: 697b ldr r3, [r7, #20]
8001338: 005b lsls r3, r3, #1
800133a: fa02 f303 lsl.w r3, r2, r3
800133e: 693a ldr r2, [r7, #16]
8001340: 4313 orrs r3, r2
8001342: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001344: 687b ldr r3, [r7, #4]
8001346: 693a ldr r2, [r7, #16]
8001348: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800134a: 683b ldr r3, [r7, #0]
800134c: 685b ldr r3, [r3, #4]
800134e: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001352: 2b00 cmp r3, #0
8001354: f000 80a0 beq.w 8001498 <HAL_GPIO_Init+0x2b4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001358: 4b58 ldr r3, [pc, #352] @ (80014bc <HAL_GPIO_Init+0x2d8>)
800135a: 699b ldr r3, [r3, #24]
800135c: 4a57 ldr r2, [pc, #348] @ (80014bc <HAL_GPIO_Init+0x2d8>)
800135e: f043 0301 orr.w r3, r3, #1
8001362: 6193 str r3, [r2, #24]
8001364: 4b55 ldr r3, [pc, #340] @ (80014bc <HAL_GPIO_Init+0x2d8>)
8001366: 699b ldr r3, [r3, #24]
8001368: f003 0301 and.w r3, r3, #1
800136c: 60bb str r3, [r7, #8]
800136e: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8001370: 4a53 ldr r2, [pc, #332] @ (80014c0 <HAL_GPIO_Init+0x2dc>)
8001372: 697b ldr r3, [r7, #20]
8001374: 089b lsrs r3, r3, #2
8001376: 3302 adds r3, #2
8001378: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800137c: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
800137e: 697b ldr r3, [r7, #20]
8001380: f003 0303 and.w r3, r3, #3
8001384: 009b lsls r3, r3, #2
8001386: 220f movs r2, #15
8001388: fa02 f303 lsl.w r3, r2, r3
800138c: 43db mvns r3, r3
800138e: 693a ldr r2, [r7, #16]
8001390: 4013 ands r3, r2
8001392: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8001394: 687b ldr r3, [r7, #4]
8001396: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
800139a: d019 beq.n 80013d0 <HAL_GPIO_Init+0x1ec>
800139c: 687b ldr r3, [r7, #4]
800139e: 4a49 ldr r2, [pc, #292] @ (80014c4 <HAL_GPIO_Init+0x2e0>)
80013a0: 4293 cmp r3, r2
80013a2: d013 beq.n 80013cc <HAL_GPIO_Init+0x1e8>
80013a4: 687b ldr r3, [r7, #4]
80013a6: 4a48 ldr r2, [pc, #288] @ (80014c8 <HAL_GPIO_Init+0x2e4>)
80013a8: 4293 cmp r3, r2
80013aa: d00d beq.n 80013c8 <HAL_GPIO_Init+0x1e4>
80013ac: 687b ldr r3, [r7, #4]
80013ae: 4a47 ldr r2, [pc, #284] @ (80014cc <HAL_GPIO_Init+0x2e8>)
80013b0: 4293 cmp r3, r2
80013b2: d007 beq.n 80013c4 <HAL_GPIO_Init+0x1e0>
80013b4: 687b ldr r3, [r7, #4]
80013b6: 4a46 ldr r2, [pc, #280] @ (80014d0 <HAL_GPIO_Init+0x2ec>)
80013b8: 4293 cmp r3, r2
80013ba: d101 bne.n 80013c0 <HAL_GPIO_Init+0x1dc>
80013bc: 2304 movs r3, #4
80013be: e008 b.n 80013d2 <HAL_GPIO_Init+0x1ee>
80013c0: 2305 movs r3, #5
80013c2: e006 b.n 80013d2 <HAL_GPIO_Init+0x1ee>
80013c4: 2303 movs r3, #3
80013c6: e004 b.n 80013d2 <HAL_GPIO_Init+0x1ee>
80013c8: 2302 movs r3, #2
80013ca: e002 b.n 80013d2 <HAL_GPIO_Init+0x1ee>
80013cc: 2301 movs r3, #1
80013ce: e000 b.n 80013d2 <HAL_GPIO_Init+0x1ee>
80013d0: 2300 movs r3, #0
80013d2: 697a ldr r2, [r7, #20]
80013d4: f002 0203 and.w r2, r2, #3
80013d8: 0092 lsls r2, r2, #2
80013da: 4093 lsls r3, r2
80013dc: 693a ldr r2, [r7, #16]
80013de: 4313 orrs r3, r2
80013e0: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
80013e2: 4937 ldr r1, [pc, #220] @ (80014c0 <HAL_GPIO_Init+0x2dc>)
80013e4: 697b ldr r3, [r7, #20]
80013e6: 089b lsrs r3, r3, #2
80013e8: 3302 adds r3, #2
80013ea: 693a ldr r2, [r7, #16]
80013ec: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80013f0: 4b38 ldr r3, [pc, #224] @ (80014d4 <HAL_GPIO_Init+0x2f0>)
80013f2: 689b ldr r3, [r3, #8]
80013f4: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80013f6: 68fb ldr r3, [r7, #12]
80013f8: 43db mvns r3, r3
80013fa: 693a ldr r2, [r7, #16]
80013fc: 4013 ands r3, r2
80013fe: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001400: 683b ldr r3, [r7, #0]
8001402: 685b ldr r3, [r3, #4]
8001404: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001408: 2b00 cmp r3, #0
800140a: d003 beq.n 8001414 <HAL_GPIO_Init+0x230>
{
temp |= iocurrent;
800140c: 693a ldr r2, [r7, #16]
800140e: 68fb ldr r3, [r7, #12]
8001410: 4313 orrs r3, r2
8001412: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8001414: 4a2f ldr r2, [pc, #188] @ (80014d4 <HAL_GPIO_Init+0x2f0>)
8001416: 693b ldr r3, [r7, #16]
8001418: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
800141a: 4b2e ldr r3, [pc, #184] @ (80014d4 <HAL_GPIO_Init+0x2f0>)
800141c: 68db ldr r3, [r3, #12]
800141e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001420: 68fb ldr r3, [r7, #12]
8001422: 43db mvns r3, r3
8001424: 693a ldr r2, [r7, #16]
8001426: 4013 ands r3, r2
8001428: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
800142a: 683b ldr r3, [r7, #0]
800142c: 685b ldr r3, [r3, #4]
800142e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001432: 2b00 cmp r3, #0
8001434: d003 beq.n 800143e <HAL_GPIO_Init+0x25a>
{
temp |= iocurrent;
8001436: 693a ldr r2, [r7, #16]
8001438: 68fb ldr r3, [r7, #12]
800143a: 4313 orrs r3, r2
800143c: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
800143e: 4a25 ldr r2, [pc, #148] @ (80014d4 <HAL_GPIO_Init+0x2f0>)
8001440: 693b ldr r3, [r7, #16]
8001442: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001444: 4b23 ldr r3, [pc, #140] @ (80014d4 <HAL_GPIO_Init+0x2f0>)
8001446: 685b ldr r3, [r3, #4]
8001448: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800144a: 68fb ldr r3, [r7, #12]
800144c: 43db mvns r3, r3
800144e: 693a ldr r2, [r7, #16]
8001450: 4013 ands r3, r2
8001452: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001454: 683b ldr r3, [r7, #0]
8001456: 685b ldr r3, [r3, #4]
8001458: f403 3300 and.w r3, r3, #131072 @ 0x20000
800145c: 2b00 cmp r3, #0
800145e: d003 beq.n 8001468 <HAL_GPIO_Init+0x284>
{
temp |= iocurrent;
8001460: 693a ldr r2, [r7, #16]
8001462: 68fb ldr r3, [r7, #12]
8001464: 4313 orrs r3, r2
8001466: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8001468: 4a1a ldr r2, [pc, #104] @ (80014d4 <HAL_GPIO_Init+0x2f0>)
800146a: 693b ldr r3, [r7, #16]
800146c: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
800146e: 4b19 ldr r3, [pc, #100] @ (80014d4 <HAL_GPIO_Init+0x2f0>)
8001470: 681b ldr r3, [r3, #0]
8001472: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001474: 68fb ldr r3, [r7, #12]
8001476: 43db mvns r3, r3
8001478: 693a ldr r2, [r7, #16]
800147a: 4013 ands r3, r2
800147c: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
800147e: 683b ldr r3, [r7, #0]
8001480: 685b ldr r3, [r3, #4]
8001482: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001486: 2b00 cmp r3, #0
8001488: d003 beq.n 8001492 <HAL_GPIO_Init+0x2ae>
{
temp |= iocurrent;
800148a: 693a ldr r2, [r7, #16]
800148c: 68fb ldr r3, [r7, #12]
800148e: 4313 orrs r3, r2
8001490: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8001492: 4a10 ldr r2, [pc, #64] @ (80014d4 <HAL_GPIO_Init+0x2f0>)
8001494: 693b ldr r3, [r7, #16]
8001496: 6013 str r3, [r2, #0]
}
}
position++;
8001498: 697b ldr r3, [r7, #20]
800149a: 3301 adds r3, #1
800149c: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
800149e: 683b ldr r3, [r7, #0]
80014a0: 681a ldr r2, [r3, #0]
80014a2: 697b ldr r3, [r7, #20]
80014a4: fa22 f303 lsr.w r3, r2, r3
80014a8: 2b00 cmp r3, #0
80014aa: f47f aea3 bne.w 80011f4 <HAL_GPIO_Init+0x10>
}
}
80014ae: bf00 nop
80014b0: bf00 nop
80014b2: 371c adds r7, #28
80014b4: 46bd mov sp, r7
80014b6: f85d 7b04 ldr.w r7, [sp], #4
80014ba: 4770 bx lr
80014bc: 40021000 .word 0x40021000
80014c0: 40010000 .word 0x40010000
80014c4: 48000400 .word 0x48000400
80014c8: 48000800 .word 0x48000800
80014cc: 48000c00 .word 0x48000c00
80014d0: 48001000 .word 0x48001000
80014d4: 40010400 .word 0x40010400
080014d8 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80014d8: b480 push {r7}
80014da: b083 sub sp, #12
80014dc: af00 add r7, sp, #0
80014de: 6078 str r0, [r7, #4]
80014e0: 460b mov r3, r1
80014e2: 807b strh r3, [r7, #2]
80014e4: 4613 mov r3, r2
80014e6: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80014e8: 787b ldrb r3, [r7, #1]
80014ea: 2b00 cmp r3, #0
80014ec: d003 beq.n 80014f6 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
80014ee: 887a ldrh r2, [r7, #2]
80014f0: 687b ldr r3, [r7, #4]
80014f2: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
80014f4: e002 b.n 80014fc <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
80014f6: 887a ldrh r2, [r7, #2]
80014f8: 687b ldr r3, [r7, #4]
80014fa: 629a str r2, [r3, #40] @ 0x28
}
80014fc: bf00 nop
80014fe: 370c adds r7, #12
8001500: 46bd mov sp, r7
8001502: f85d 7b04 ldr.w r7, [sp], #4
8001506: 4770 bx lr
08001508 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001508: b580 push {r7, lr}
800150a: f5ad 7d00 sub.w sp, sp, #512 @ 0x200
800150e: af00 add r7, sp, #0
8001510: f507 7300 add.w r3, r7, #512 @ 0x200
8001514: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001518: 6018 str r0, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
uint32_t pll_config2;
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
800151a: f507 7300 add.w r3, r7, #512 @ 0x200
800151e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001522: 681b ldr r3, [r3, #0]
8001524: 2b00 cmp r3, #0
8001526: d102 bne.n 800152e <HAL_RCC_OscConfig+0x26>
{
return HAL_ERROR;
8001528: 2301 movs r3, #1
800152a: f001 b823 b.w 8002574 <HAL_RCC_OscConfig+0x106c>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800152e: f507 7300 add.w r3, r7, #512 @ 0x200
8001532: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001536: 681b ldr r3, [r3, #0]
8001538: 681b ldr r3, [r3, #0]
800153a: f003 0301 and.w r3, r3, #1
800153e: 2b00 cmp r3, #0
8001540: f000 817d beq.w 800183e <HAL_RCC_OscConfig+0x336>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001544: 4bbc ldr r3, [pc, #752] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001546: 685b ldr r3, [r3, #4]
8001548: f003 030c and.w r3, r3, #12
800154c: 2b04 cmp r3, #4
800154e: d00c beq.n 800156a <HAL_RCC_OscConfig+0x62>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8001550: 4bb9 ldr r3, [pc, #740] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001552: 685b ldr r3, [r3, #4]
8001554: f003 030c and.w r3, r3, #12
8001558: 2b08 cmp r3, #8
800155a: d15c bne.n 8001616 <HAL_RCC_OscConfig+0x10e>
800155c: 4bb6 ldr r3, [pc, #728] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800155e: 685b ldr r3, [r3, #4]
8001560: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001564: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001568: d155 bne.n 8001616 <HAL_RCC_OscConfig+0x10e>
800156a: f44f 3300 mov.w r3, #131072 @ 0x20000
800156e: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001572: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0
8001576: fa93 f3a3 rbit r3, r3
800157a: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
800157e: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001582: fab3 f383 clz r3, r3
8001586: b2db uxtb r3, r3
8001588: 095b lsrs r3, r3, #5
800158a: b2db uxtb r3, r3
800158c: f043 0301 orr.w r3, r3, #1
8001590: b2db uxtb r3, r3
8001592: 2b01 cmp r3, #1
8001594: d102 bne.n 800159c <HAL_RCC_OscConfig+0x94>
8001596: 4ba8 ldr r3, [pc, #672] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001598: 681b ldr r3, [r3, #0]
800159a: e015 b.n 80015c8 <HAL_RCC_OscConfig+0xc0>
800159c: f44f 3300 mov.w r3, #131072 @ 0x20000
80015a0: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80015a4: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8
80015a8: fa93 f3a3 rbit r3, r3
80015ac: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4
80015b0: f44f 3300 mov.w r3, #131072 @ 0x20000
80015b4: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0
80015b8: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0
80015bc: fa93 f3a3 rbit r3, r3
80015c0: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc
80015c4: 4b9c ldr r3, [pc, #624] @ (8001838 <HAL_RCC_OscConfig+0x330>)
80015c6: 6a5b ldr r3, [r3, #36] @ 0x24
80015c8: f44f 3200 mov.w r2, #131072 @ 0x20000
80015cc: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8
80015d0: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8
80015d4: fa92 f2a2 rbit r2, r2
80015d8: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4
return result;
80015dc: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4
80015e0: fab2 f282 clz r2, r2
80015e4: b2d2 uxtb r2, r2
80015e6: f042 0220 orr.w r2, r2, #32
80015ea: b2d2 uxtb r2, r2
80015ec: f002 021f and.w r2, r2, #31
80015f0: 2101 movs r1, #1
80015f2: fa01 f202 lsl.w r2, r1, r2
80015f6: 4013 ands r3, r2
80015f8: 2b00 cmp r3, #0
80015fa: f000 811f beq.w 800183c <HAL_RCC_OscConfig+0x334>
80015fe: f507 7300 add.w r3, r7, #512 @ 0x200
8001602: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001606: 681b ldr r3, [r3, #0]
8001608: 685b ldr r3, [r3, #4]
800160a: 2b00 cmp r3, #0
800160c: f040 8116 bne.w 800183c <HAL_RCC_OscConfig+0x334>
{
return HAL_ERROR;
8001610: 2301 movs r3, #1
8001612: f000 bfaf b.w 8002574 <HAL_RCC_OscConfig+0x106c>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001616: f507 7300 add.w r3, r7, #512 @ 0x200
800161a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800161e: 681b ldr r3, [r3, #0]
8001620: 685b ldr r3, [r3, #4]
8001622: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001626: d106 bne.n 8001636 <HAL_RCC_OscConfig+0x12e>
8001628: 4b83 ldr r3, [pc, #524] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800162a: 681b ldr r3, [r3, #0]
800162c: 4a82 ldr r2, [pc, #520] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800162e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001632: 6013 str r3, [r2, #0]
8001634: e036 b.n 80016a4 <HAL_RCC_OscConfig+0x19c>
8001636: f507 7300 add.w r3, r7, #512 @ 0x200
800163a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800163e: 681b ldr r3, [r3, #0]
8001640: 685b ldr r3, [r3, #4]
8001642: 2b00 cmp r3, #0
8001644: d10c bne.n 8001660 <HAL_RCC_OscConfig+0x158>
8001646: 4b7c ldr r3, [pc, #496] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001648: 681b ldr r3, [r3, #0]
800164a: 4a7b ldr r2, [pc, #492] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800164c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001650: 6013 str r3, [r2, #0]
8001652: 4b79 ldr r3, [pc, #484] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001654: 681b ldr r3, [r3, #0]
8001656: 4a78 ldr r2, [pc, #480] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001658: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800165c: 6013 str r3, [r2, #0]
800165e: e021 b.n 80016a4 <HAL_RCC_OscConfig+0x19c>
8001660: f507 7300 add.w r3, r7, #512 @ 0x200
8001664: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001668: 681b ldr r3, [r3, #0]
800166a: 685b ldr r3, [r3, #4]
800166c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8001670: d10c bne.n 800168c <HAL_RCC_OscConfig+0x184>
8001672: 4b71 ldr r3, [pc, #452] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001674: 681b ldr r3, [r3, #0]
8001676: 4a70 ldr r2, [pc, #448] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001678: f443 2380 orr.w r3, r3, #262144 @ 0x40000
800167c: 6013 str r3, [r2, #0]
800167e: 4b6e ldr r3, [pc, #440] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001680: 681b ldr r3, [r3, #0]
8001682: 4a6d ldr r2, [pc, #436] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001684: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001688: 6013 str r3, [r2, #0]
800168a: e00b b.n 80016a4 <HAL_RCC_OscConfig+0x19c>
800168c: 4b6a ldr r3, [pc, #424] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800168e: 681b ldr r3, [r3, #0]
8001690: 4a69 ldr r2, [pc, #420] @ (8001838 <HAL_RCC_OscConfig+0x330>)
8001692: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001696: 6013 str r3, [r2, #0]
8001698: 4b67 ldr r3, [pc, #412] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800169a: 681b ldr r3, [r3, #0]
800169c: 4a66 ldr r2, [pc, #408] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800169e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80016a2: 6013 str r3, [r2, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
/* Configure the HSE predivision factor --------------------------------*/
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
80016a4: 4b64 ldr r3, [pc, #400] @ (8001838 <HAL_RCC_OscConfig+0x330>)
80016a6: 6adb ldr r3, [r3, #44] @ 0x2c
80016a8: f023 020f bic.w r2, r3, #15
80016ac: f507 7300 add.w r3, r7, #512 @ 0x200
80016b0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80016b4: 681b ldr r3, [r3, #0]
80016b6: 689b ldr r3, [r3, #8]
80016b8: 495f ldr r1, [pc, #380] @ (8001838 <HAL_RCC_OscConfig+0x330>)
80016ba: 4313 orrs r3, r2
80016bc: 62cb str r3, [r1, #44] @ 0x2c
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80016be: f507 7300 add.w r3, r7, #512 @ 0x200
80016c2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80016c6: 681b ldr r3, [r3, #0]
80016c8: 685b ldr r3, [r3, #4]
80016ca: 2b00 cmp r3, #0
80016cc: d059 beq.n 8001782 <HAL_RCC_OscConfig+0x27a>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80016ce: f7ff f913 bl 80008f8 <HAL_GetTick>
80016d2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80016d6: e00a b.n 80016ee <HAL_RCC_OscConfig+0x1e6>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80016d8: f7ff f90e bl 80008f8 <HAL_GetTick>
80016dc: 4602 mov r2, r0
80016de: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80016e2: 1ad3 subs r3, r2, r3
80016e4: 2b64 cmp r3, #100 @ 0x64
80016e6: d902 bls.n 80016ee <HAL_RCC_OscConfig+0x1e6>
{
return HAL_TIMEOUT;
80016e8: 2303 movs r3, #3
80016ea: f000 bf43 b.w 8002574 <HAL_RCC_OscConfig+0x106c>
80016ee: f44f 3300 mov.w r3, #131072 @ 0x20000
80016f2: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80016f6: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0
80016fa: fa93 f3a3 rbit r3, r3
80016fe: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc
return result;
8001702: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001706: fab3 f383 clz r3, r3
800170a: b2db uxtb r3, r3
800170c: 095b lsrs r3, r3, #5
800170e: b2db uxtb r3, r3
8001710: f043 0301 orr.w r3, r3, #1
8001714: b2db uxtb r3, r3
8001716: 2b01 cmp r3, #1
8001718: d102 bne.n 8001720 <HAL_RCC_OscConfig+0x218>
800171a: 4b47 ldr r3, [pc, #284] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800171c: 681b ldr r3, [r3, #0]
800171e: e015 b.n 800174c <HAL_RCC_OscConfig+0x244>
8001720: f44f 3300 mov.w r3, #131072 @ 0x20000
8001724: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001728: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8
800172c: fa93 f3a3 rbit r3, r3
8001730: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4
8001734: f44f 3300 mov.w r3, #131072 @ 0x20000
8001738: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0
800173c: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0
8001740: fa93 f3a3 rbit r3, r3
8001744: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc
8001748: 4b3b ldr r3, [pc, #236] @ (8001838 <HAL_RCC_OscConfig+0x330>)
800174a: 6a5b ldr r3, [r3, #36] @ 0x24
800174c: f44f 3200 mov.w r2, #131072 @ 0x20000
8001750: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8
8001754: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8
8001758: fa92 f2a2 rbit r2, r2
800175c: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4
return result;
8001760: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4
8001764: fab2 f282 clz r2, r2
8001768: b2d2 uxtb r2, r2
800176a: f042 0220 orr.w r2, r2, #32
800176e: b2d2 uxtb r2, r2
8001770: f002 021f and.w r2, r2, #31
8001774: 2101 movs r1, #1
8001776: fa01 f202 lsl.w r2, r1, r2
800177a: 4013 ands r3, r2
800177c: 2b00 cmp r3, #0
800177e: d0ab beq.n 80016d8 <HAL_RCC_OscConfig+0x1d0>
8001780: e05d b.n 800183e <HAL_RCC_OscConfig+0x336>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001782: f7ff f8b9 bl 80008f8 <HAL_GetTick>
8001786: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800178a: e00a b.n 80017a2 <HAL_RCC_OscConfig+0x29a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800178c: f7ff f8b4 bl 80008f8 <HAL_GetTick>
8001790: 4602 mov r2, r0
8001792: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8001796: 1ad3 subs r3, r2, r3
8001798: 2b64 cmp r3, #100 @ 0x64
800179a: d902 bls.n 80017a2 <HAL_RCC_OscConfig+0x29a>
{
return HAL_TIMEOUT;
800179c: 2303 movs r3, #3
800179e: f000 bee9 b.w 8002574 <HAL_RCC_OscConfig+0x106c>
80017a2: f44f 3300 mov.w r3, #131072 @ 0x20000
80017a6: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80017aa: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0
80017ae: fa93 f3a3 rbit r3, r3
80017b2: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac
return result;
80017b6: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80017ba: fab3 f383 clz r3, r3
80017be: b2db uxtb r3, r3
80017c0: 095b lsrs r3, r3, #5
80017c2: b2db uxtb r3, r3
80017c4: f043 0301 orr.w r3, r3, #1
80017c8: b2db uxtb r3, r3
80017ca: 2b01 cmp r3, #1
80017cc: d102 bne.n 80017d4 <HAL_RCC_OscConfig+0x2cc>
80017ce: 4b1a ldr r3, [pc, #104] @ (8001838 <HAL_RCC_OscConfig+0x330>)
80017d0: 681b ldr r3, [r3, #0]
80017d2: e015 b.n 8001800 <HAL_RCC_OscConfig+0x2f8>
80017d4: f44f 3300 mov.w r3, #131072 @ 0x20000
80017d8: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80017dc: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8
80017e0: fa93 f3a3 rbit r3, r3
80017e4: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4
80017e8: f44f 3300 mov.w r3, #131072 @ 0x20000
80017ec: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0
80017f0: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0
80017f4: fa93 f3a3 rbit r3, r3
80017f8: f8c7 319c str.w r3, [r7, #412] @ 0x19c
80017fc: 4b0e ldr r3, [pc, #56] @ (8001838 <HAL_RCC_OscConfig+0x330>)
80017fe: 6a5b ldr r3, [r3, #36] @ 0x24
8001800: f44f 3200 mov.w r2, #131072 @ 0x20000
8001804: f8c7 2198 str.w r2, [r7, #408] @ 0x198
8001808: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198
800180c: fa92 f2a2 rbit r2, r2
8001810: f8c7 2194 str.w r2, [r7, #404] @ 0x194
return result;
8001814: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194
8001818: fab2 f282 clz r2, r2
800181c: b2d2 uxtb r2, r2
800181e: f042 0220 orr.w r2, r2, #32
8001822: b2d2 uxtb r2, r2
8001824: f002 021f and.w r2, r2, #31
8001828: 2101 movs r1, #1
800182a: fa01 f202 lsl.w r2, r1, r2
800182e: 4013 ands r3, r2
8001830: 2b00 cmp r3, #0
8001832: d1ab bne.n 800178c <HAL_RCC_OscConfig+0x284>
8001834: e003 b.n 800183e <HAL_RCC_OscConfig+0x336>
8001836: bf00 nop
8001838: 40021000 .word 0x40021000
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800183c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800183e: f507 7300 add.w r3, r7, #512 @ 0x200
8001842: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001846: 681b ldr r3, [r3, #0]
8001848: 681b ldr r3, [r3, #0]
800184a: f003 0302 and.w r3, r3, #2
800184e: 2b00 cmp r3, #0
8001850: f000 817d beq.w 8001b4e <HAL_RCC_OscConfig+0x646>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8001854: 4ba6 ldr r3, [pc, #664] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
8001856: 685b ldr r3, [r3, #4]
8001858: f003 030c and.w r3, r3, #12
800185c: 2b00 cmp r3, #0
800185e: d00b beq.n 8001878 <HAL_RCC_OscConfig+0x370>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8001860: 4ba3 ldr r3, [pc, #652] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
8001862: 685b ldr r3, [r3, #4]
8001864: f003 030c and.w r3, r3, #12
8001868: 2b08 cmp r3, #8
800186a: d172 bne.n 8001952 <HAL_RCC_OscConfig+0x44a>
800186c: 4ba0 ldr r3, [pc, #640] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
800186e: 685b ldr r3, [r3, #4]
8001870: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001874: 2b00 cmp r3, #0
8001876: d16c bne.n 8001952 <HAL_RCC_OscConfig+0x44a>
8001878: 2302 movs r3, #2
800187a: f8c7 3190 str.w r3, [r7, #400] @ 0x190
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800187e: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190
8001882: fa93 f3a3 rbit r3, r3
8001886: f8c7 318c str.w r3, [r7, #396] @ 0x18c
return result;
800188a: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800188e: fab3 f383 clz r3, r3
8001892: b2db uxtb r3, r3
8001894: 095b lsrs r3, r3, #5
8001896: b2db uxtb r3, r3
8001898: f043 0301 orr.w r3, r3, #1
800189c: b2db uxtb r3, r3
800189e: 2b01 cmp r3, #1
80018a0: d102 bne.n 80018a8 <HAL_RCC_OscConfig+0x3a0>
80018a2: 4b93 ldr r3, [pc, #588] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
80018a4: 681b ldr r3, [r3, #0]
80018a6: e013 b.n 80018d0 <HAL_RCC_OscConfig+0x3c8>
80018a8: 2302 movs r3, #2
80018aa: f8c7 3188 str.w r3, [r7, #392] @ 0x188
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80018ae: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188
80018b2: fa93 f3a3 rbit r3, r3
80018b6: f8c7 3184 str.w r3, [r7, #388] @ 0x184
80018ba: 2302 movs r3, #2
80018bc: f8c7 3180 str.w r3, [r7, #384] @ 0x180
80018c0: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180
80018c4: fa93 f3a3 rbit r3, r3
80018c8: f8c7 317c str.w r3, [r7, #380] @ 0x17c
80018cc: 4b88 ldr r3, [pc, #544] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
80018ce: 6a5b ldr r3, [r3, #36] @ 0x24
80018d0: 2202 movs r2, #2
80018d2: f8c7 2178 str.w r2, [r7, #376] @ 0x178
80018d6: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178
80018da: fa92 f2a2 rbit r2, r2
80018de: f8c7 2174 str.w r2, [r7, #372] @ 0x174
return result;
80018e2: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174
80018e6: fab2 f282 clz r2, r2
80018ea: b2d2 uxtb r2, r2
80018ec: f042 0220 orr.w r2, r2, #32
80018f0: b2d2 uxtb r2, r2
80018f2: f002 021f and.w r2, r2, #31
80018f6: 2101 movs r1, #1
80018f8: fa01 f202 lsl.w r2, r1, r2
80018fc: 4013 ands r3, r2
80018fe: 2b00 cmp r3, #0
8001900: d00a beq.n 8001918 <HAL_RCC_OscConfig+0x410>
8001902: f507 7300 add.w r3, r7, #512 @ 0x200
8001906: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800190a: 681b ldr r3, [r3, #0]
800190c: 691b ldr r3, [r3, #16]
800190e: 2b01 cmp r3, #1
8001910: d002 beq.n 8001918 <HAL_RCC_OscConfig+0x410>
{
return HAL_ERROR;
8001912: 2301 movs r3, #1
8001914: f000 be2e b.w 8002574 <HAL_RCC_OscConfig+0x106c>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001918: 4b75 ldr r3, [pc, #468] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
800191a: 681b ldr r3, [r3, #0]
800191c: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8001920: f507 7300 add.w r3, r7, #512 @ 0x200
8001924: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001928: 681b ldr r3, [r3, #0]
800192a: 695b ldr r3, [r3, #20]
800192c: 21f8 movs r1, #248 @ 0xf8
800192e: f8c7 1170 str.w r1, [r7, #368] @ 0x170
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001932: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170
8001936: fa91 f1a1 rbit r1, r1
800193a: f8c7 116c str.w r1, [r7, #364] @ 0x16c
return result;
800193e: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c
8001942: fab1 f181 clz r1, r1
8001946: b2c9 uxtb r1, r1
8001948: 408b lsls r3, r1
800194a: 4969 ldr r1, [pc, #420] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
800194c: 4313 orrs r3, r2
800194e: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001950: e0fd b.n 8001b4e <HAL_RCC_OscConfig+0x646>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8001952: f507 7300 add.w r3, r7, #512 @ 0x200
8001956: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800195a: 681b ldr r3, [r3, #0]
800195c: 691b ldr r3, [r3, #16]
800195e: 2b00 cmp r3, #0
8001960: f000 8088 beq.w 8001a74 <HAL_RCC_OscConfig+0x56c>
8001964: 2301 movs r3, #1
8001966: f8c7 3168 str.w r3, [r7, #360] @ 0x168
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800196a: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168
800196e: fa93 f3a3 rbit r3, r3
8001972: f8c7 3164 str.w r3, [r7, #356] @ 0x164
return result;
8001976: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800197a: fab3 f383 clz r3, r3
800197e: b2db uxtb r3, r3
8001980: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8001984: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8001988: 009b lsls r3, r3, #2
800198a: 461a mov r2, r3
800198c: 2301 movs r3, #1
800198e: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001990: f7fe ffb2 bl 80008f8 <HAL_GetTick>
8001994: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001998: e00a b.n 80019b0 <HAL_RCC_OscConfig+0x4a8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800199a: f7fe ffad bl 80008f8 <HAL_GetTick>
800199e: 4602 mov r2, r0
80019a0: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80019a4: 1ad3 subs r3, r2, r3
80019a6: 2b02 cmp r3, #2
80019a8: d902 bls.n 80019b0 <HAL_RCC_OscConfig+0x4a8>
{
return HAL_TIMEOUT;
80019aa: 2303 movs r3, #3
80019ac: f000 bde2 b.w 8002574 <HAL_RCC_OscConfig+0x106c>
80019b0: 2302 movs r3, #2
80019b2: f8c7 3160 str.w r3, [r7, #352] @ 0x160
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80019b6: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160
80019ba: fa93 f3a3 rbit r3, r3
80019be: f8c7 315c str.w r3, [r7, #348] @ 0x15c
return result;
80019c2: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80019c6: fab3 f383 clz r3, r3
80019ca: b2db uxtb r3, r3
80019cc: 095b lsrs r3, r3, #5
80019ce: b2db uxtb r3, r3
80019d0: f043 0301 orr.w r3, r3, #1
80019d4: b2db uxtb r3, r3
80019d6: 2b01 cmp r3, #1
80019d8: d102 bne.n 80019e0 <HAL_RCC_OscConfig+0x4d8>
80019da: 4b45 ldr r3, [pc, #276] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
80019dc: 681b ldr r3, [r3, #0]
80019de: e013 b.n 8001a08 <HAL_RCC_OscConfig+0x500>
80019e0: 2302 movs r3, #2
80019e2: f8c7 3158 str.w r3, [r7, #344] @ 0x158
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80019e6: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158
80019ea: fa93 f3a3 rbit r3, r3
80019ee: f8c7 3154 str.w r3, [r7, #340] @ 0x154
80019f2: 2302 movs r3, #2
80019f4: f8c7 3150 str.w r3, [r7, #336] @ 0x150
80019f8: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150
80019fc: fa93 f3a3 rbit r3, r3
8001a00: f8c7 314c str.w r3, [r7, #332] @ 0x14c
8001a04: 4b3a ldr r3, [pc, #232] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
8001a06: 6a5b ldr r3, [r3, #36] @ 0x24
8001a08: 2202 movs r2, #2
8001a0a: f8c7 2148 str.w r2, [r7, #328] @ 0x148
8001a0e: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148
8001a12: fa92 f2a2 rbit r2, r2
8001a16: f8c7 2144 str.w r2, [r7, #324] @ 0x144
return result;
8001a1a: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144
8001a1e: fab2 f282 clz r2, r2
8001a22: b2d2 uxtb r2, r2
8001a24: f042 0220 orr.w r2, r2, #32
8001a28: b2d2 uxtb r2, r2
8001a2a: f002 021f and.w r2, r2, #31
8001a2e: 2101 movs r1, #1
8001a30: fa01 f202 lsl.w r2, r1, r2
8001a34: 4013 ands r3, r2
8001a36: 2b00 cmp r3, #0
8001a38: d0af beq.n 800199a <HAL_RCC_OscConfig+0x492>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001a3a: 4b2d ldr r3, [pc, #180] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
8001a3c: 681b ldr r3, [r3, #0]
8001a3e: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8001a42: f507 7300 add.w r3, r7, #512 @ 0x200
8001a46: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001a4a: 681b ldr r3, [r3, #0]
8001a4c: 695b ldr r3, [r3, #20]
8001a4e: 21f8 movs r1, #248 @ 0xf8
8001a50: f8c7 1140 str.w r1, [r7, #320] @ 0x140
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001a54: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140
8001a58: fa91 f1a1 rbit r1, r1
8001a5c: f8c7 113c str.w r1, [r7, #316] @ 0x13c
return result;
8001a60: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c
8001a64: fab1 f181 clz r1, r1
8001a68: b2c9 uxtb r1, r1
8001a6a: 408b lsls r3, r1
8001a6c: 4920 ldr r1, [pc, #128] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
8001a6e: 4313 orrs r3, r2
8001a70: 600b str r3, [r1, #0]
8001a72: e06c b.n 8001b4e <HAL_RCC_OscConfig+0x646>
8001a74: 2301 movs r3, #1
8001a76: f8c7 3138 str.w r3, [r7, #312] @ 0x138
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001a7a: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138
8001a7e: fa93 f3a3 rbit r3, r3
8001a82: f8c7 3134 str.w r3, [r7, #308] @ 0x134
return result;
8001a86: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001a8a: fab3 f383 clz r3, r3
8001a8e: b2db uxtb r3, r3
8001a90: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8001a94: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8001a98: 009b lsls r3, r3, #2
8001a9a: 461a mov r2, r3
8001a9c: 2300 movs r3, #0
8001a9e: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001aa0: f7fe ff2a bl 80008f8 <HAL_GetTick>
8001aa4: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001aa8: e00a b.n 8001ac0 <HAL_RCC_OscConfig+0x5b8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001aaa: f7fe ff25 bl 80008f8 <HAL_GetTick>
8001aae: 4602 mov r2, r0
8001ab0: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8001ab4: 1ad3 subs r3, r2, r3
8001ab6: 2b02 cmp r3, #2
8001ab8: d902 bls.n 8001ac0 <HAL_RCC_OscConfig+0x5b8>
{
return HAL_TIMEOUT;
8001aba: 2303 movs r3, #3
8001abc: f000 bd5a b.w 8002574 <HAL_RCC_OscConfig+0x106c>
8001ac0: 2302 movs r3, #2
8001ac2: f8c7 3130 str.w r3, [r7, #304] @ 0x130
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001ac6: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130
8001aca: fa93 f3a3 rbit r3, r3
8001ace: f8c7 312c str.w r3, [r7, #300] @ 0x12c
return result;
8001ad2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001ad6: fab3 f383 clz r3, r3
8001ada: b2db uxtb r3, r3
8001adc: 095b lsrs r3, r3, #5
8001ade: b2db uxtb r3, r3
8001ae0: f043 0301 orr.w r3, r3, #1
8001ae4: b2db uxtb r3, r3
8001ae6: 2b01 cmp r3, #1
8001ae8: d104 bne.n 8001af4 <HAL_RCC_OscConfig+0x5ec>
8001aea: 4b01 ldr r3, [pc, #4] @ (8001af0 <HAL_RCC_OscConfig+0x5e8>)
8001aec: 681b ldr r3, [r3, #0]
8001aee: e015 b.n 8001b1c <HAL_RCC_OscConfig+0x614>
8001af0: 40021000 .word 0x40021000
8001af4: 2302 movs r3, #2
8001af6: f8c7 3128 str.w r3, [r7, #296] @ 0x128
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001afa: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128
8001afe: fa93 f3a3 rbit r3, r3
8001b02: f8c7 3124 str.w r3, [r7, #292] @ 0x124
8001b06: 2302 movs r3, #2
8001b08: f8c7 3120 str.w r3, [r7, #288] @ 0x120
8001b0c: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120
8001b10: fa93 f3a3 rbit r3, r3
8001b14: f8c7 311c str.w r3, [r7, #284] @ 0x11c
8001b18: 4bc8 ldr r3, [pc, #800] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001b1a: 6a5b ldr r3, [r3, #36] @ 0x24
8001b1c: 2202 movs r2, #2
8001b1e: f8c7 2118 str.w r2, [r7, #280] @ 0x118
8001b22: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118
8001b26: fa92 f2a2 rbit r2, r2
8001b2a: f8c7 2114 str.w r2, [r7, #276] @ 0x114
return result;
8001b2e: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114
8001b32: fab2 f282 clz r2, r2
8001b36: b2d2 uxtb r2, r2
8001b38: f042 0220 orr.w r2, r2, #32
8001b3c: b2d2 uxtb r2, r2
8001b3e: f002 021f and.w r2, r2, #31
8001b42: 2101 movs r1, #1
8001b44: fa01 f202 lsl.w r2, r1, r2
8001b48: 4013 ands r3, r2
8001b4a: 2b00 cmp r3, #0
8001b4c: d1ad bne.n 8001aaa <HAL_RCC_OscConfig+0x5a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001b4e: f507 7300 add.w r3, r7, #512 @ 0x200
8001b52: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001b56: 681b ldr r3, [r3, #0]
8001b58: 681b ldr r3, [r3, #0]
8001b5a: f003 0308 and.w r3, r3, #8
8001b5e: 2b00 cmp r3, #0
8001b60: f000 8110 beq.w 8001d84 <HAL_RCC_OscConfig+0x87c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001b64: f507 7300 add.w r3, r7, #512 @ 0x200
8001b68: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001b6c: 681b ldr r3, [r3, #0]
8001b6e: 699b ldr r3, [r3, #24]
8001b70: 2b00 cmp r3, #0
8001b72: d079 beq.n 8001c68 <HAL_RCC_OscConfig+0x760>
8001b74: 2301 movs r3, #1
8001b76: f8c7 3110 str.w r3, [r7, #272] @ 0x110
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001b7a: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110
8001b7e: fa93 f3a3 rbit r3, r3
8001b82: f8c7 310c str.w r3, [r7, #268] @ 0x10c
return result;
8001b86: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001b8a: fab3 f383 clz r3, r3
8001b8e: b2db uxtb r3, r3
8001b90: 461a mov r2, r3
8001b92: 4bab ldr r3, [pc, #684] @ (8001e40 <HAL_RCC_OscConfig+0x938>)
8001b94: 4413 add r3, r2
8001b96: 009b lsls r3, r3, #2
8001b98: 461a mov r2, r3
8001b9a: 2301 movs r3, #1
8001b9c: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001b9e: f7fe feab bl 80008f8 <HAL_GetTick>
8001ba2: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001ba6: e00a b.n 8001bbe <HAL_RCC_OscConfig+0x6b6>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001ba8: f7fe fea6 bl 80008f8 <HAL_GetTick>
8001bac: 4602 mov r2, r0
8001bae: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8001bb2: 1ad3 subs r3, r2, r3
8001bb4: 2b02 cmp r3, #2
8001bb6: d902 bls.n 8001bbe <HAL_RCC_OscConfig+0x6b6>
{
return HAL_TIMEOUT;
8001bb8: 2303 movs r3, #3
8001bba: f000 bcdb b.w 8002574 <HAL_RCC_OscConfig+0x106c>
8001bbe: 2302 movs r3, #2
8001bc0: f8c7 3108 str.w r3, [r7, #264] @ 0x108
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001bc4: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108
8001bc8: fa93 f3a3 rbit r3, r3
8001bcc: f8c7 3104 str.w r3, [r7, #260] @ 0x104
8001bd0: f507 7300 add.w r3, r7, #512 @ 0x200
8001bd4: f5a3 7380 sub.w r3, r3, #256 @ 0x100
8001bd8: 2202 movs r2, #2
8001bda: 601a str r2, [r3, #0]
8001bdc: f507 7300 add.w r3, r7, #512 @ 0x200
8001be0: f5a3 7380 sub.w r3, r3, #256 @ 0x100
8001be4: 681b ldr r3, [r3, #0]
8001be6: fa93 f2a3 rbit r2, r3
8001bea: f507 7300 add.w r3, r7, #512 @ 0x200
8001bee: f5a3 7382 sub.w r3, r3, #260 @ 0x104
8001bf2: 601a str r2, [r3, #0]
8001bf4: f507 7300 add.w r3, r7, #512 @ 0x200
8001bf8: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8001bfc: 2202 movs r2, #2
8001bfe: 601a str r2, [r3, #0]
8001c00: f507 7300 add.w r3, r7, #512 @ 0x200
8001c04: f5a3 7384 sub.w r3, r3, #264 @ 0x108
8001c08: 681b ldr r3, [r3, #0]
8001c0a: fa93 f2a3 rbit r2, r3
8001c0e: f507 7300 add.w r3, r7, #512 @ 0x200
8001c12: f5a3 7386 sub.w r3, r3, #268 @ 0x10c
8001c16: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001c18: 4b88 ldr r3, [pc, #544] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001c1a: 6a5a ldr r2, [r3, #36] @ 0x24
8001c1c: f507 7300 add.w r3, r7, #512 @ 0x200
8001c20: f5a3 7388 sub.w r3, r3, #272 @ 0x110
8001c24: 2102 movs r1, #2
8001c26: 6019 str r1, [r3, #0]
8001c28: f507 7300 add.w r3, r7, #512 @ 0x200
8001c2c: f5a3 7388 sub.w r3, r3, #272 @ 0x110
8001c30: 681b ldr r3, [r3, #0]
8001c32: fa93 f1a3 rbit r1, r3
8001c36: f507 7300 add.w r3, r7, #512 @ 0x200
8001c3a: f5a3 738a sub.w r3, r3, #276 @ 0x114
8001c3e: 6019 str r1, [r3, #0]
return result;
8001c40: f507 7300 add.w r3, r7, #512 @ 0x200
8001c44: f5a3 738a sub.w r3, r3, #276 @ 0x114
8001c48: 681b ldr r3, [r3, #0]
8001c4a: fab3 f383 clz r3, r3
8001c4e: b2db uxtb r3, r3
8001c50: f043 0360 orr.w r3, r3, #96 @ 0x60
8001c54: b2db uxtb r3, r3
8001c56: f003 031f and.w r3, r3, #31
8001c5a: 2101 movs r1, #1
8001c5c: fa01 f303 lsl.w r3, r1, r3
8001c60: 4013 ands r3, r2
8001c62: 2b00 cmp r3, #0
8001c64: d0a0 beq.n 8001ba8 <HAL_RCC_OscConfig+0x6a0>
8001c66: e08d b.n 8001d84 <HAL_RCC_OscConfig+0x87c>
8001c68: f507 7300 add.w r3, r7, #512 @ 0x200
8001c6c: f5a3 738c sub.w r3, r3, #280 @ 0x118
8001c70: 2201 movs r2, #1
8001c72: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001c74: f507 7300 add.w r3, r7, #512 @ 0x200
8001c78: f5a3 738c sub.w r3, r3, #280 @ 0x118
8001c7c: 681b ldr r3, [r3, #0]
8001c7e: fa93 f2a3 rbit r2, r3
8001c82: f507 7300 add.w r3, r7, #512 @ 0x200
8001c86: f5a3 738e sub.w r3, r3, #284 @ 0x11c
8001c8a: 601a str r2, [r3, #0]
return result;
8001c8c: f507 7300 add.w r3, r7, #512 @ 0x200
8001c90: f5a3 738e sub.w r3, r3, #284 @ 0x11c
8001c94: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001c96: fab3 f383 clz r3, r3
8001c9a: b2db uxtb r3, r3
8001c9c: 461a mov r2, r3
8001c9e: 4b68 ldr r3, [pc, #416] @ (8001e40 <HAL_RCC_OscConfig+0x938>)
8001ca0: 4413 add r3, r2
8001ca2: 009b lsls r3, r3, #2
8001ca4: 461a mov r2, r3
8001ca6: 2300 movs r3, #0
8001ca8: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001caa: f7fe fe25 bl 80008f8 <HAL_GetTick>
8001cae: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001cb2: e00a b.n 8001cca <HAL_RCC_OscConfig+0x7c2>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001cb4: f7fe fe20 bl 80008f8 <HAL_GetTick>
8001cb8: 4602 mov r2, r0
8001cba: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8001cbe: 1ad3 subs r3, r2, r3
8001cc0: 2b02 cmp r3, #2
8001cc2: d902 bls.n 8001cca <HAL_RCC_OscConfig+0x7c2>
{
return HAL_TIMEOUT;
8001cc4: 2303 movs r3, #3
8001cc6: f000 bc55 b.w 8002574 <HAL_RCC_OscConfig+0x106c>
8001cca: f507 7300 add.w r3, r7, #512 @ 0x200
8001cce: f5a3 7390 sub.w r3, r3, #288 @ 0x120
8001cd2: 2202 movs r2, #2
8001cd4: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001cd6: f507 7300 add.w r3, r7, #512 @ 0x200
8001cda: f5a3 7390 sub.w r3, r3, #288 @ 0x120
8001cde: 681b ldr r3, [r3, #0]
8001ce0: fa93 f2a3 rbit r2, r3
8001ce4: f507 7300 add.w r3, r7, #512 @ 0x200
8001ce8: f5a3 7392 sub.w r3, r3, #292 @ 0x124
8001cec: 601a str r2, [r3, #0]
8001cee: f507 7300 add.w r3, r7, #512 @ 0x200
8001cf2: f5a3 7394 sub.w r3, r3, #296 @ 0x128
8001cf6: 2202 movs r2, #2
8001cf8: 601a str r2, [r3, #0]
8001cfa: f507 7300 add.w r3, r7, #512 @ 0x200
8001cfe: f5a3 7394 sub.w r3, r3, #296 @ 0x128
8001d02: 681b ldr r3, [r3, #0]
8001d04: fa93 f2a3 rbit r2, r3
8001d08: f507 7300 add.w r3, r7, #512 @ 0x200
8001d0c: f5a3 7396 sub.w r3, r3, #300 @ 0x12c
8001d10: 601a str r2, [r3, #0]
8001d12: f507 7300 add.w r3, r7, #512 @ 0x200
8001d16: f5a3 7398 sub.w r3, r3, #304 @ 0x130
8001d1a: 2202 movs r2, #2
8001d1c: 601a str r2, [r3, #0]
8001d1e: f507 7300 add.w r3, r7, #512 @ 0x200
8001d22: f5a3 7398 sub.w r3, r3, #304 @ 0x130
8001d26: 681b ldr r3, [r3, #0]
8001d28: fa93 f2a3 rbit r2, r3
8001d2c: f507 7300 add.w r3, r7, #512 @ 0x200
8001d30: f5a3 739a sub.w r3, r3, #308 @ 0x134
8001d34: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001d36: 4b41 ldr r3, [pc, #260] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001d38: 6a5a ldr r2, [r3, #36] @ 0x24
8001d3a: f507 7300 add.w r3, r7, #512 @ 0x200
8001d3e: f5a3 739c sub.w r3, r3, #312 @ 0x138
8001d42: 2102 movs r1, #2
8001d44: 6019 str r1, [r3, #0]
8001d46: f507 7300 add.w r3, r7, #512 @ 0x200
8001d4a: f5a3 739c sub.w r3, r3, #312 @ 0x138
8001d4e: 681b ldr r3, [r3, #0]
8001d50: fa93 f1a3 rbit r1, r3
8001d54: f507 7300 add.w r3, r7, #512 @ 0x200
8001d58: f5a3 739e sub.w r3, r3, #316 @ 0x13c
8001d5c: 6019 str r1, [r3, #0]
return result;
8001d5e: f507 7300 add.w r3, r7, #512 @ 0x200
8001d62: f5a3 739e sub.w r3, r3, #316 @ 0x13c
8001d66: 681b ldr r3, [r3, #0]
8001d68: fab3 f383 clz r3, r3
8001d6c: b2db uxtb r3, r3
8001d6e: f043 0360 orr.w r3, r3, #96 @ 0x60
8001d72: b2db uxtb r3, r3
8001d74: f003 031f and.w r3, r3, #31
8001d78: 2101 movs r1, #1
8001d7a: fa01 f303 lsl.w r3, r1, r3
8001d7e: 4013 ands r3, r2
8001d80: 2b00 cmp r3, #0
8001d82: d197 bne.n 8001cb4 <HAL_RCC_OscConfig+0x7ac>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001d84: f507 7300 add.w r3, r7, #512 @ 0x200
8001d88: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001d8c: 681b ldr r3, [r3, #0]
8001d8e: 681b ldr r3, [r3, #0]
8001d90: f003 0304 and.w r3, r3, #4
8001d94: 2b00 cmp r3, #0
8001d96: f000 81a1 beq.w 80020dc <HAL_RCC_OscConfig+0xbd4>
{
FlagStatus pwrclkchanged = RESET;
8001d9a: 2300 movs r3, #0
8001d9c: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8001da0: 4b26 ldr r3, [pc, #152] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001da2: 69db ldr r3, [r3, #28]
8001da4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001da8: 2b00 cmp r3, #0
8001daa: d116 bne.n 8001dda <HAL_RCC_OscConfig+0x8d2>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001dac: 4b23 ldr r3, [pc, #140] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001dae: 69db ldr r3, [r3, #28]
8001db0: 4a22 ldr r2, [pc, #136] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001db2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001db6: 61d3 str r3, [r2, #28]
8001db8: 4b20 ldr r3, [pc, #128] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001dba: 69db ldr r3, [r3, #28]
8001dbc: f003 5280 and.w r2, r3, #268435456 @ 0x10000000
8001dc0: f507 7300 add.w r3, r7, #512 @ 0x200
8001dc4: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
8001dc8: 601a str r2, [r3, #0]
8001dca: f507 7300 add.w r3, r7, #512 @ 0x200
8001dce: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
8001dd2: 681b ldr r3, [r3, #0]
pwrclkchanged = SET;
8001dd4: 2301 movs r3, #1
8001dd6: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001dda: 4b1a ldr r3, [pc, #104] @ (8001e44 <HAL_RCC_OscConfig+0x93c>)
8001ddc: 681b ldr r3, [r3, #0]
8001dde: f403 7380 and.w r3, r3, #256 @ 0x100
8001de2: 2b00 cmp r3, #0
8001de4: d11a bne.n 8001e1c <HAL_RCC_OscConfig+0x914>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001de6: 4b17 ldr r3, [pc, #92] @ (8001e44 <HAL_RCC_OscConfig+0x93c>)
8001de8: 681b ldr r3, [r3, #0]
8001dea: 4a16 ldr r2, [pc, #88] @ (8001e44 <HAL_RCC_OscConfig+0x93c>)
8001dec: f443 7380 orr.w r3, r3, #256 @ 0x100
8001df0: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001df2: f7fe fd81 bl 80008f8 <HAL_GetTick>
8001df6: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001dfa: e009 b.n 8001e10 <HAL_RCC_OscConfig+0x908>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001dfc: f7fe fd7c bl 80008f8 <HAL_GetTick>
8001e00: 4602 mov r2, r0
8001e02: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8001e06: 1ad3 subs r3, r2, r3
8001e08: 2b64 cmp r3, #100 @ 0x64
8001e0a: d901 bls.n 8001e10 <HAL_RCC_OscConfig+0x908>
{
return HAL_TIMEOUT;
8001e0c: 2303 movs r3, #3
8001e0e: e3b1 b.n 8002574 <HAL_RCC_OscConfig+0x106c>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001e10: 4b0c ldr r3, [pc, #48] @ (8001e44 <HAL_RCC_OscConfig+0x93c>)
8001e12: 681b ldr r3, [r3, #0]
8001e14: f403 7380 and.w r3, r3, #256 @ 0x100
8001e18: 2b00 cmp r3, #0
8001e1a: d0ef beq.n 8001dfc <HAL_RCC_OscConfig+0x8f4>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001e1c: f507 7300 add.w r3, r7, #512 @ 0x200
8001e20: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001e24: 681b ldr r3, [r3, #0]
8001e26: 68db ldr r3, [r3, #12]
8001e28: 2b01 cmp r3, #1
8001e2a: d10d bne.n 8001e48 <HAL_RCC_OscConfig+0x940>
8001e2c: 4b03 ldr r3, [pc, #12] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001e2e: 6a1b ldr r3, [r3, #32]
8001e30: 4a02 ldr r2, [pc, #8] @ (8001e3c <HAL_RCC_OscConfig+0x934>)
8001e32: f043 0301 orr.w r3, r3, #1
8001e36: 6213 str r3, [r2, #32]
8001e38: e03c b.n 8001eb4 <HAL_RCC_OscConfig+0x9ac>
8001e3a: bf00 nop
8001e3c: 40021000 .word 0x40021000
8001e40: 10908120 .word 0x10908120
8001e44: 40007000 .word 0x40007000
8001e48: f507 7300 add.w r3, r7, #512 @ 0x200
8001e4c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001e50: 681b ldr r3, [r3, #0]
8001e52: 68db ldr r3, [r3, #12]
8001e54: 2b00 cmp r3, #0
8001e56: d10c bne.n 8001e72 <HAL_RCC_OscConfig+0x96a>
8001e58: 4bc1 ldr r3, [pc, #772] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e5a: 6a1b ldr r3, [r3, #32]
8001e5c: 4ac0 ldr r2, [pc, #768] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e5e: f023 0301 bic.w r3, r3, #1
8001e62: 6213 str r3, [r2, #32]
8001e64: 4bbe ldr r3, [pc, #760] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e66: 6a1b ldr r3, [r3, #32]
8001e68: 4abd ldr r2, [pc, #756] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e6a: f023 0304 bic.w r3, r3, #4
8001e6e: 6213 str r3, [r2, #32]
8001e70: e020 b.n 8001eb4 <HAL_RCC_OscConfig+0x9ac>
8001e72: f507 7300 add.w r3, r7, #512 @ 0x200
8001e76: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001e7a: 681b ldr r3, [r3, #0]
8001e7c: 68db ldr r3, [r3, #12]
8001e7e: 2b05 cmp r3, #5
8001e80: d10c bne.n 8001e9c <HAL_RCC_OscConfig+0x994>
8001e82: 4bb7 ldr r3, [pc, #732] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e84: 6a1b ldr r3, [r3, #32]
8001e86: 4ab6 ldr r2, [pc, #728] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e88: f043 0304 orr.w r3, r3, #4
8001e8c: 6213 str r3, [r2, #32]
8001e8e: 4bb4 ldr r3, [pc, #720] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e90: 6a1b ldr r3, [r3, #32]
8001e92: 4ab3 ldr r2, [pc, #716] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e94: f043 0301 orr.w r3, r3, #1
8001e98: 6213 str r3, [r2, #32]
8001e9a: e00b b.n 8001eb4 <HAL_RCC_OscConfig+0x9ac>
8001e9c: 4bb0 ldr r3, [pc, #704] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001e9e: 6a1b ldr r3, [r3, #32]
8001ea0: 4aaf ldr r2, [pc, #700] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001ea2: f023 0301 bic.w r3, r3, #1
8001ea6: 6213 str r3, [r2, #32]
8001ea8: 4bad ldr r3, [pc, #692] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001eaa: 6a1b ldr r3, [r3, #32]
8001eac: 4aac ldr r2, [pc, #688] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001eae: f023 0304 bic.w r3, r3, #4
8001eb2: 6213 str r3, [r2, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001eb4: f507 7300 add.w r3, r7, #512 @ 0x200
8001eb8: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8001ebc: 681b ldr r3, [r3, #0]
8001ebe: 68db ldr r3, [r3, #12]
8001ec0: 2b00 cmp r3, #0
8001ec2: f000 8081 beq.w 8001fc8 <HAL_RCC_OscConfig+0xac0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001ec6: f7fe fd17 bl 80008f8 <HAL_GetTick>
8001eca: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001ece: e00b b.n 8001ee8 <HAL_RCC_OscConfig+0x9e0>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001ed0: f7fe fd12 bl 80008f8 <HAL_GetTick>
8001ed4: 4602 mov r2, r0
8001ed6: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8001eda: 1ad3 subs r3, r2, r3
8001edc: f241 3288 movw r2, #5000 @ 0x1388
8001ee0: 4293 cmp r3, r2
8001ee2: d901 bls.n 8001ee8 <HAL_RCC_OscConfig+0x9e0>
{
return HAL_TIMEOUT;
8001ee4: 2303 movs r3, #3
8001ee6: e345 b.n 8002574 <HAL_RCC_OscConfig+0x106c>
8001ee8: f507 7300 add.w r3, r7, #512 @ 0x200
8001eec: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
8001ef0: 2202 movs r2, #2
8001ef2: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001ef4: f507 7300 add.w r3, r7, #512 @ 0x200
8001ef8: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
8001efc: 681b ldr r3, [r3, #0]
8001efe: fa93 f2a3 rbit r2, r3
8001f02: f507 7300 add.w r3, r7, #512 @ 0x200
8001f06: f5a3 73a2 sub.w r3, r3, #324 @ 0x144
8001f0a: 601a str r2, [r3, #0]
8001f0c: f507 7300 add.w r3, r7, #512 @ 0x200
8001f10: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
8001f14: 2202 movs r2, #2
8001f16: 601a str r2, [r3, #0]
8001f18: f507 7300 add.w r3, r7, #512 @ 0x200
8001f1c: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
8001f20: 681b ldr r3, [r3, #0]
8001f22: fa93 f2a3 rbit r2, r3
8001f26: f507 7300 add.w r3, r7, #512 @ 0x200
8001f2a: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
8001f2e: 601a str r2, [r3, #0]
return result;
8001f30: f507 7300 add.w r3, r7, #512 @ 0x200
8001f34: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
8001f38: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001f3a: fab3 f383 clz r3, r3
8001f3e: b2db uxtb r3, r3
8001f40: 095b lsrs r3, r3, #5
8001f42: b2db uxtb r3, r3
8001f44: f043 0302 orr.w r3, r3, #2
8001f48: b2db uxtb r3, r3
8001f4a: 2b02 cmp r3, #2
8001f4c: d102 bne.n 8001f54 <HAL_RCC_OscConfig+0xa4c>
8001f4e: 4b84 ldr r3, [pc, #528] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001f50: 6a1b ldr r3, [r3, #32]
8001f52: e013 b.n 8001f7c <HAL_RCC_OscConfig+0xa74>
8001f54: f507 7300 add.w r3, r7, #512 @ 0x200
8001f58: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
8001f5c: 2202 movs r2, #2
8001f5e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001f60: f507 7300 add.w r3, r7, #512 @ 0x200
8001f64: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
8001f68: 681b ldr r3, [r3, #0]
8001f6a: fa93 f2a3 rbit r2, r3
8001f6e: f507 7300 add.w r3, r7, #512 @ 0x200
8001f72: f5a3 73aa sub.w r3, r3, #340 @ 0x154
8001f76: 601a str r2, [r3, #0]
8001f78: 4b79 ldr r3, [pc, #484] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8001f7a: 6a5b ldr r3, [r3, #36] @ 0x24
8001f7c: f507 7200 add.w r2, r7, #512 @ 0x200
8001f80: f5a2 72ac sub.w r2, r2, #344 @ 0x158
8001f84: 2102 movs r1, #2
8001f86: 6011 str r1, [r2, #0]
8001f88: f507 7200 add.w r2, r7, #512 @ 0x200
8001f8c: f5a2 72ac sub.w r2, r2, #344 @ 0x158
8001f90: 6812 ldr r2, [r2, #0]
8001f92: fa92 f1a2 rbit r1, r2
8001f96: f507 7200 add.w r2, r7, #512 @ 0x200
8001f9a: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
8001f9e: 6011 str r1, [r2, #0]
return result;
8001fa0: f507 7200 add.w r2, r7, #512 @ 0x200
8001fa4: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
8001fa8: 6812 ldr r2, [r2, #0]
8001faa: fab2 f282 clz r2, r2
8001fae: b2d2 uxtb r2, r2
8001fb0: f042 0240 orr.w r2, r2, #64 @ 0x40
8001fb4: b2d2 uxtb r2, r2
8001fb6: f002 021f and.w r2, r2, #31
8001fba: 2101 movs r1, #1
8001fbc: fa01 f202 lsl.w r2, r1, r2
8001fc0: 4013 ands r3, r2
8001fc2: 2b00 cmp r3, #0
8001fc4: d084 beq.n 8001ed0 <HAL_RCC_OscConfig+0x9c8>
8001fc6: e07f b.n 80020c8 <HAL_RCC_OscConfig+0xbc0>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001fc8: f7fe fc96 bl 80008f8 <HAL_GetTick>
8001fcc: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001fd0: e00b b.n 8001fea <HAL_RCC_OscConfig+0xae2>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001fd2: f7fe fc91 bl 80008f8 <HAL_GetTick>
8001fd6: 4602 mov r2, r0
8001fd8: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
8001fdc: 1ad3 subs r3, r2, r3
8001fde: f241 3288 movw r2, #5000 @ 0x1388
8001fe2: 4293 cmp r3, r2
8001fe4: d901 bls.n 8001fea <HAL_RCC_OscConfig+0xae2>
{
return HAL_TIMEOUT;
8001fe6: 2303 movs r3, #3
8001fe8: e2c4 b.n 8002574 <HAL_RCC_OscConfig+0x106c>
8001fea: f507 7300 add.w r3, r7, #512 @ 0x200
8001fee: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
8001ff2: 2202 movs r2, #2
8001ff4: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001ff6: f507 7300 add.w r3, r7, #512 @ 0x200
8001ffa: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
8001ffe: 681b ldr r3, [r3, #0]
8002000: fa93 f2a3 rbit r2, r3
8002004: f507 7300 add.w r3, r7, #512 @ 0x200
8002008: f5a3 73b2 sub.w r3, r3, #356 @ 0x164
800200c: 601a str r2, [r3, #0]
800200e: f507 7300 add.w r3, r7, #512 @ 0x200
8002012: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
8002016: 2202 movs r2, #2
8002018: 601a str r2, [r3, #0]
800201a: f507 7300 add.w r3, r7, #512 @ 0x200
800201e: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
8002022: 681b ldr r3, [r3, #0]
8002024: fa93 f2a3 rbit r2, r3
8002028: f507 7300 add.w r3, r7, #512 @ 0x200
800202c: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
8002030: 601a str r2, [r3, #0]
return result;
8002032: f507 7300 add.w r3, r7, #512 @ 0x200
8002036: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
800203a: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800203c: fab3 f383 clz r3, r3
8002040: b2db uxtb r3, r3
8002042: 095b lsrs r3, r3, #5
8002044: b2db uxtb r3, r3
8002046: f043 0302 orr.w r3, r3, #2
800204a: b2db uxtb r3, r3
800204c: 2b02 cmp r3, #2
800204e: d102 bne.n 8002056 <HAL_RCC_OscConfig+0xb4e>
8002050: 4b43 ldr r3, [pc, #268] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
8002052: 6a1b ldr r3, [r3, #32]
8002054: e013 b.n 800207e <HAL_RCC_OscConfig+0xb76>
8002056: f507 7300 add.w r3, r7, #512 @ 0x200
800205a: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
800205e: 2202 movs r2, #2
8002060: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002062: f507 7300 add.w r3, r7, #512 @ 0x200
8002066: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
800206a: 681b ldr r3, [r3, #0]
800206c: fa93 f2a3 rbit r2, r3
8002070: f507 7300 add.w r3, r7, #512 @ 0x200
8002074: f5a3 73ba sub.w r3, r3, #372 @ 0x174
8002078: 601a str r2, [r3, #0]
800207a: 4b39 ldr r3, [pc, #228] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
800207c: 6a5b ldr r3, [r3, #36] @ 0x24
800207e: f507 7200 add.w r2, r7, #512 @ 0x200
8002082: f5a2 72bc sub.w r2, r2, #376 @ 0x178
8002086: 2102 movs r1, #2
8002088: 6011 str r1, [r2, #0]
800208a: f507 7200 add.w r2, r7, #512 @ 0x200
800208e: f5a2 72bc sub.w r2, r2, #376 @ 0x178
8002092: 6812 ldr r2, [r2, #0]
8002094: fa92 f1a2 rbit r1, r2
8002098: f507 7200 add.w r2, r7, #512 @ 0x200
800209c: f5a2 72be sub.w r2, r2, #380 @ 0x17c
80020a0: 6011 str r1, [r2, #0]
return result;
80020a2: f507 7200 add.w r2, r7, #512 @ 0x200
80020a6: f5a2 72be sub.w r2, r2, #380 @ 0x17c
80020aa: 6812 ldr r2, [r2, #0]
80020ac: fab2 f282 clz r2, r2
80020b0: b2d2 uxtb r2, r2
80020b2: f042 0240 orr.w r2, r2, #64 @ 0x40
80020b6: b2d2 uxtb r2, r2
80020b8: f002 021f and.w r2, r2, #31
80020bc: 2101 movs r1, #1
80020be: fa01 f202 lsl.w r2, r1, r2
80020c2: 4013 ands r3, r2
80020c4: 2b00 cmp r3, #0
80020c6: d184 bne.n 8001fd2 <HAL_RCC_OscConfig+0xaca>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80020c8: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff
80020cc: 2b01 cmp r3, #1
80020ce: d105 bne.n 80020dc <HAL_RCC_OscConfig+0xbd4>
{
__HAL_RCC_PWR_CLK_DISABLE();
80020d0: 4b23 ldr r3, [pc, #140] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
80020d2: 69db ldr r3, [r3, #28]
80020d4: 4a22 ldr r2, [pc, #136] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
80020d6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80020da: 61d3 str r3, [r2, #28]
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80020dc: f507 7300 add.w r3, r7, #512 @ 0x200
80020e0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
80020e4: 681b ldr r3, [r3, #0]
80020e6: 69db ldr r3, [r3, #28]
80020e8: 2b00 cmp r3, #0
80020ea: f000 8242 beq.w 8002572 <HAL_RCC_OscConfig+0x106a>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80020ee: 4b1c ldr r3, [pc, #112] @ (8002160 <HAL_RCC_OscConfig+0xc58>)
80020f0: 685b ldr r3, [r3, #4]
80020f2: f003 030c and.w r3, r3, #12
80020f6: 2b08 cmp r3, #8
80020f8: f000 8213 beq.w 8002522 <HAL_RCC_OscConfig+0x101a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80020fc: f507 7300 add.w r3, r7, #512 @ 0x200
8002100: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002104: 681b ldr r3, [r3, #0]
8002106: 69db ldr r3, [r3, #28]
8002108: 2b02 cmp r3, #2
800210a: f040 8162 bne.w 80023d2 <HAL_RCC_OscConfig+0xeca>
800210e: f507 7300 add.w r3, r7, #512 @ 0x200
8002112: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
8002116: f04f 7280 mov.w r2, #16777216 @ 0x1000000
800211a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800211c: f507 7300 add.w r3, r7, #512 @ 0x200
8002120: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
8002124: 681b ldr r3, [r3, #0]
8002126: fa93 f2a3 rbit r2, r3
800212a: f507 7300 add.w r3, r7, #512 @ 0x200
800212e: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
8002132: 601a str r2, [r3, #0]
return result;
8002134: f507 7300 add.w r3, r7, #512 @ 0x200
8002138: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
800213c: 681b ldr r3, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800213e: fab3 f383 clz r3, r3
8002142: b2db uxtb r3, r3
8002144: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
8002148: f503 1384 add.w r3, r3, #1081344 @ 0x108000
800214c: 009b lsls r3, r3, #2
800214e: 461a mov r2, r3
8002150: 2300 movs r3, #0
8002152: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002154: f7fe fbd0 bl 80008f8 <HAL_GetTick>
8002158: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800215c: e00c b.n 8002178 <HAL_RCC_OscConfig+0xc70>
800215e: bf00 nop
8002160: 40021000 .word 0x40021000
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002164: f7fe fbc8 bl 80008f8 <HAL_GetTick>
8002168: 4602 mov r2, r0
800216a: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
800216e: 1ad3 subs r3, r2, r3
8002170: 2b02 cmp r3, #2
8002172: d901 bls.n 8002178 <HAL_RCC_OscConfig+0xc70>
{
return HAL_TIMEOUT;
8002174: 2303 movs r3, #3
8002176: e1fd b.n 8002574 <HAL_RCC_OscConfig+0x106c>
8002178: f507 7300 add.w r3, r7, #512 @ 0x200
800217c: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
8002180: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002184: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002186: f507 7300 add.w r3, r7, #512 @ 0x200
800218a: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
800218e: 681b ldr r3, [r3, #0]
8002190: fa93 f2a3 rbit r2, r3
8002194: f507 7300 add.w r3, r7, #512 @ 0x200
8002198: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
800219c: 601a str r2, [r3, #0]
return result;
800219e: f507 7300 add.w r3, r7, #512 @ 0x200
80021a2: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
80021a6: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80021a8: fab3 f383 clz r3, r3
80021ac: b2db uxtb r3, r3
80021ae: 095b lsrs r3, r3, #5
80021b0: b2db uxtb r3, r3
80021b2: f043 0301 orr.w r3, r3, #1
80021b6: b2db uxtb r3, r3
80021b8: 2b01 cmp r3, #1
80021ba: d102 bne.n 80021c2 <HAL_RCC_OscConfig+0xcba>
80021bc: 4bb0 ldr r3, [pc, #704] @ (8002480 <HAL_RCC_OscConfig+0xf78>)
80021be: 681b ldr r3, [r3, #0]
80021c0: e027 b.n 8002212 <HAL_RCC_OscConfig+0xd0a>
80021c2: f507 7300 add.w r3, r7, #512 @ 0x200
80021c6: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
80021ca: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80021ce: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80021d0: f507 7300 add.w r3, r7, #512 @ 0x200
80021d4: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
80021d8: 681b ldr r3, [r3, #0]
80021da: fa93 f2a3 rbit r2, r3
80021de: f507 7300 add.w r3, r7, #512 @ 0x200
80021e2: f5a3 73ca sub.w r3, r3, #404 @ 0x194
80021e6: 601a str r2, [r3, #0]
80021e8: f507 7300 add.w r3, r7, #512 @ 0x200
80021ec: f5a3 73cc sub.w r3, r3, #408 @ 0x198
80021f0: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80021f4: 601a str r2, [r3, #0]
80021f6: f507 7300 add.w r3, r7, #512 @ 0x200
80021fa: f5a3 73cc sub.w r3, r3, #408 @ 0x198
80021fe: 681b ldr r3, [r3, #0]
8002200: fa93 f2a3 rbit r2, r3
8002204: f507 7300 add.w r3, r7, #512 @ 0x200
8002208: f5a3 73ce sub.w r3, r3, #412 @ 0x19c
800220c: 601a str r2, [r3, #0]
800220e: 4b9c ldr r3, [pc, #624] @ (8002480 <HAL_RCC_OscConfig+0xf78>)
8002210: 6a5b ldr r3, [r3, #36] @ 0x24
8002212: f507 7200 add.w r2, r7, #512 @ 0x200
8002216: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
800221a: f04f 7100 mov.w r1, #33554432 @ 0x2000000
800221e: 6011 str r1, [r2, #0]
8002220: f507 7200 add.w r2, r7, #512 @ 0x200
8002224: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
8002228: 6812 ldr r2, [r2, #0]
800222a: fa92 f1a2 rbit r1, r2
800222e: f507 7200 add.w r2, r7, #512 @ 0x200
8002232: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
8002236: 6011 str r1, [r2, #0]
return result;
8002238: f507 7200 add.w r2, r7, #512 @ 0x200
800223c: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
8002240: 6812 ldr r2, [r2, #0]
8002242: fab2 f282 clz r2, r2
8002246: b2d2 uxtb r2, r2
8002248: f042 0220 orr.w r2, r2, #32
800224c: b2d2 uxtb r2, r2
800224e: f002 021f and.w r2, r2, #31
8002252: 2101 movs r1, #1
8002254: fa01 f202 lsl.w r2, r1, r2
8002258: 4013 ands r3, r2
800225a: 2b00 cmp r3, #0
800225c: d182 bne.n 8002164 <HAL_RCC_OscConfig+0xc5c>
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
#else
/* Configure the main PLL clock source and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
800225e: 4b88 ldr r3, [pc, #544] @ (8002480 <HAL_RCC_OscConfig+0xf78>)
8002260: 685b ldr r3, [r3, #4]
8002262: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
8002266: f507 7300 add.w r3, r7, #512 @ 0x200
800226a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800226e: 681b ldr r3, [r3, #0]
8002270: 6a59 ldr r1, [r3, #36] @ 0x24
8002272: f507 7300 add.w r3, r7, #512 @ 0x200
8002276: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800227a: 681b ldr r3, [r3, #0]
800227c: 6a1b ldr r3, [r3, #32]
800227e: 430b orrs r3, r1
8002280: 497f ldr r1, [pc, #508] @ (8002480 <HAL_RCC_OscConfig+0xf78>)
8002282: 4313 orrs r3, r2
8002284: 604b str r3, [r1, #4]
8002286: f507 7300 add.w r3, r7, #512 @ 0x200
800228a: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
800228e: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8002292: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002294: f507 7300 add.w r3, r7, #512 @ 0x200
8002298: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
800229c: 681b ldr r3, [r3, #0]
800229e: fa93 f2a3 rbit r2, r3
80022a2: f507 7300 add.w r3, r7, #512 @ 0x200
80022a6: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
80022aa: 601a str r2, [r3, #0]
return result;
80022ac: f507 7300 add.w r3, r7, #512 @ 0x200
80022b0: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
80022b4: 681b ldr r3, [r3, #0]
RCC_OscInitStruct->PLL.PLLMUL);
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80022b6: fab3 f383 clz r3, r3
80022ba: b2db uxtb r3, r3
80022bc: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
80022c0: f503 1384 add.w r3, r3, #1081344 @ 0x108000
80022c4: 009b lsls r3, r3, #2
80022c6: 461a mov r2, r3
80022c8: 2301 movs r3, #1
80022ca: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80022cc: f7fe fb14 bl 80008f8 <HAL_GetTick>
80022d0: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80022d4: e009 b.n 80022ea <HAL_RCC_OscConfig+0xde2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80022d6: f7fe fb0f bl 80008f8 <HAL_GetTick>
80022da: 4602 mov r2, r0
80022dc: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
80022e0: 1ad3 subs r3, r2, r3
80022e2: 2b02 cmp r3, #2
80022e4: d901 bls.n 80022ea <HAL_RCC_OscConfig+0xde2>
{
return HAL_TIMEOUT;
80022e6: 2303 movs r3, #3
80022e8: e144 b.n 8002574 <HAL_RCC_OscConfig+0x106c>
80022ea: f507 7300 add.w r3, r7, #512 @ 0x200
80022ee: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
80022f2: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80022f6: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80022f8: f507 7300 add.w r3, r7, #512 @ 0x200
80022fc: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
8002300: 681b ldr r3, [r3, #0]
8002302: fa93 f2a3 rbit r2, r3
8002306: f507 7300 add.w r3, r7, #512 @ 0x200
800230a: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
800230e: 601a str r2, [r3, #0]
return result;
8002310: f507 7300 add.w r3, r7, #512 @ 0x200
8002314: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
8002318: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800231a: fab3 f383 clz r3, r3
800231e: b2db uxtb r3, r3
8002320: 095b lsrs r3, r3, #5
8002322: b2db uxtb r3, r3
8002324: f043 0301 orr.w r3, r3, #1
8002328: b2db uxtb r3, r3
800232a: 2b01 cmp r3, #1
800232c: d102 bne.n 8002334 <HAL_RCC_OscConfig+0xe2c>
800232e: 4b54 ldr r3, [pc, #336] @ (8002480 <HAL_RCC_OscConfig+0xf78>)
8002330: 681b ldr r3, [r3, #0]
8002332: e027 b.n 8002384 <HAL_RCC_OscConfig+0xe7c>
8002334: f507 7300 add.w r3, r7, #512 @ 0x200
8002338: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
800233c: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002340: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002342: f507 7300 add.w r3, r7, #512 @ 0x200
8002346: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
800234a: 681b ldr r3, [r3, #0]
800234c: fa93 f2a3 rbit r2, r3
8002350: f507 7300 add.w r3, r7, #512 @ 0x200
8002354: f5a3 73de sub.w r3, r3, #444 @ 0x1bc
8002358: 601a str r2, [r3, #0]
800235a: f507 7300 add.w r3, r7, #512 @ 0x200
800235e: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
8002362: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002366: 601a str r2, [r3, #0]
8002368: f507 7300 add.w r3, r7, #512 @ 0x200
800236c: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
8002370: 681b ldr r3, [r3, #0]
8002372: fa93 f2a3 rbit r2, r3
8002376: f507 7300 add.w r3, r7, #512 @ 0x200
800237a: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4
800237e: 601a str r2, [r3, #0]
8002380: 4b3f ldr r3, [pc, #252] @ (8002480 <HAL_RCC_OscConfig+0xf78>)
8002382: 6a5b ldr r3, [r3, #36] @ 0x24
8002384: f507 7200 add.w r2, r7, #512 @ 0x200
8002388: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
800238c: f04f 7100 mov.w r1, #33554432 @ 0x2000000
8002390: 6011 str r1, [r2, #0]
8002392: f507 7200 add.w r2, r7, #512 @ 0x200
8002396: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
800239a: 6812 ldr r2, [r2, #0]
800239c: fa92 f1a2 rbit r1, r2
80023a0: f507 7200 add.w r2, r7, #512 @ 0x200
80023a4: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
80023a8: 6011 str r1, [r2, #0]
return result;
80023aa: f507 7200 add.w r2, r7, #512 @ 0x200
80023ae: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
80023b2: 6812 ldr r2, [r2, #0]
80023b4: fab2 f282 clz r2, r2
80023b8: b2d2 uxtb r2, r2
80023ba: f042 0220 orr.w r2, r2, #32
80023be: b2d2 uxtb r2, r2
80023c0: f002 021f and.w r2, r2, #31
80023c4: 2101 movs r1, #1
80023c6: fa01 f202 lsl.w r2, r1, r2
80023ca: 4013 ands r3, r2
80023cc: 2b00 cmp r3, #0
80023ce: d082 beq.n 80022d6 <HAL_RCC_OscConfig+0xdce>
80023d0: e0cf b.n 8002572 <HAL_RCC_OscConfig+0x106a>
80023d2: f507 7300 add.w r3, r7, #512 @ 0x200
80023d6: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
80023da: f04f 7280 mov.w r2, #16777216 @ 0x1000000
80023de: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80023e0: f507 7300 add.w r3, r7, #512 @ 0x200
80023e4: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
80023e8: 681b ldr r3, [r3, #0]
80023ea: fa93 f2a3 rbit r2, r3
80023ee: f507 7300 add.w r3, r7, #512 @ 0x200
80023f2: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
80023f6: 601a str r2, [r3, #0]
return result;
80023f8: f507 7300 add.w r3, r7, #512 @ 0x200
80023fc: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
8002400: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002402: fab3 f383 clz r3, r3
8002406: b2db uxtb r3, r3
8002408: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
800240c: f503 1384 add.w r3, r3, #1081344 @ 0x108000
8002410: 009b lsls r3, r3, #2
8002412: 461a mov r2, r3
8002414: 2300 movs r3, #0
8002416: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002418: f7fe fa6e bl 80008f8 <HAL_GetTick>
800241c: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002420: e009 b.n 8002436 <HAL_RCC_OscConfig+0xf2e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002422: f7fe fa69 bl 80008f8 <HAL_GetTick>
8002426: 4602 mov r2, r0
8002428: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
800242c: 1ad3 subs r3, r2, r3
800242e: 2b02 cmp r3, #2
8002430: d901 bls.n 8002436 <HAL_RCC_OscConfig+0xf2e>
{
return HAL_TIMEOUT;
8002432: 2303 movs r3, #3
8002434: e09e b.n 8002574 <HAL_RCC_OscConfig+0x106c>
8002436: f507 7300 add.w r3, r7, #512 @ 0x200
800243a: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
800243e: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002442: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002444: f507 7300 add.w r3, r7, #512 @ 0x200
8002448: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
800244c: 681b ldr r3, [r3, #0]
800244e: fa93 f2a3 rbit r2, r3
8002452: f507 7300 add.w r3, r7, #512 @ 0x200
8002456: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
800245a: 601a str r2, [r3, #0]
return result;
800245c: f507 7300 add.w r3, r7, #512 @ 0x200
8002460: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
8002464: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002466: fab3 f383 clz r3, r3
800246a: b2db uxtb r3, r3
800246c: 095b lsrs r3, r3, #5
800246e: b2db uxtb r3, r3
8002470: f043 0301 orr.w r3, r3, #1
8002474: b2db uxtb r3, r3
8002476: 2b01 cmp r3, #1
8002478: d104 bne.n 8002484 <HAL_RCC_OscConfig+0xf7c>
800247a: 4b01 ldr r3, [pc, #4] @ (8002480 <HAL_RCC_OscConfig+0xf78>)
800247c: 681b ldr r3, [r3, #0]
800247e: e029 b.n 80024d4 <HAL_RCC_OscConfig+0xfcc>
8002480: 40021000 .word 0x40021000
8002484: f507 7300 add.w r3, r7, #512 @ 0x200
8002488: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
800248c: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002490: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002492: f507 7300 add.w r3, r7, #512 @ 0x200
8002496: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
800249a: 681b ldr r3, [r3, #0]
800249c: fa93 f2a3 rbit r2, r3
80024a0: f507 7300 add.w r3, r7, #512 @ 0x200
80024a4: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4
80024a8: 601a str r2, [r3, #0]
80024aa: f507 7300 add.w r3, r7, #512 @ 0x200
80024ae: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
80024b2: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80024b6: 601a str r2, [r3, #0]
80024b8: f507 7300 add.w r3, r7, #512 @ 0x200
80024bc: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
80024c0: 681b ldr r3, [r3, #0]
80024c2: fa93 f2a3 rbit r2, r3
80024c6: f507 7300 add.w r3, r7, #512 @ 0x200
80024ca: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec
80024ce: 601a str r2, [r3, #0]
80024d0: 4b2b ldr r3, [pc, #172] @ (8002580 <HAL_RCC_OscConfig+0x1078>)
80024d2: 6a5b ldr r3, [r3, #36] @ 0x24
80024d4: f507 7200 add.w r2, r7, #512 @ 0x200
80024d8: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
80024dc: f04f 7100 mov.w r1, #33554432 @ 0x2000000
80024e0: 6011 str r1, [r2, #0]
80024e2: f507 7200 add.w r2, r7, #512 @ 0x200
80024e6: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
80024ea: 6812 ldr r2, [r2, #0]
80024ec: fa92 f1a2 rbit r1, r2
80024f0: f507 7200 add.w r2, r7, #512 @ 0x200
80024f4: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
80024f8: 6011 str r1, [r2, #0]
return result;
80024fa: f507 7200 add.w r2, r7, #512 @ 0x200
80024fe: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
8002502: 6812 ldr r2, [r2, #0]
8002504: fab2 f282 clz r2, r2
8002508: b2d2 uxtb r2, r2
800250a: f042 0220 orr.w r2, r2, #32
800250e: b2d2 uxtb r2, r2
8002510: f002 021f and.w r2, r2, #31
8002514: 2101 movs r1, #1
8002516: fa01 f202 lsl.w r2, r1, r2
800251a: 4013 ands r3, r2
800251c: 2b00 cmp r3, #0
800251e: d180 bne.n 8002422 <HAL_RCC_OscConfig+0xf1a>
8002520: e027 b.n 8002572 <HAL_RCC_OscConfig+0x106a>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002522: f507 7300 add.w r3, r7, #512 @ 0x200
8002526: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800252a: 681b ldr r3, [r3, #0]
800252c: 69db ldr r3, [r3, #28]
800252e: 2b01 cmp r3, #1
8002530: d101 bne.n 8002536 <HAL_RCC_OscConfig+0x102e>
{
return HAL_ERROR;
8002532: 2301 movs r3, #1
8002534: e01e b.n 8002574 <HAL_RCC_OscConfig+0x106c>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8002536: 4b12 ldr r3, [pc, #72] @ (8002580 <HAL_RCC_OscConfig+0x1078>)
8002538: 685b ldr r3, [r3, #4]
800253a: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4
pll_config2 = RCC->CFGR2;
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
#else
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800253e: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
8002542: f403 3280 and.w r2, r3, #65536 @ 0x10000
8002546: f507 7300 add.w r3, r7, #512 @ 0x200
800254a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
800254e: 681b ldr r3, [r3, #0]
8002550: 6a1b ldr r3, [r3, #32]
8002552: 429a cmp r2, r3
8002554: d10b bne.n 800256e <HAL_RCC_OscConfig+0x1066>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8002556: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
800255a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
800255e: f507 7300 add.w r3, r7, #512 @ 0x200
8002562: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
8002566: 681b ldr r3, [r3, #0]
8002568: 6a5b ldr r3, [r3, #36] @ 0x24
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800256a: 429a cmp r2, r3
800256c: d001 beq.n 8002572 <HAL_RCC_OscConfig+0x106a>
#endif
{
return HAL_ERROR;
800256e: 2301 movs r3, #1
8002570: e000 b.n 8002574 <HAL_RCC_OscConfig+0x106c>
}
}
}
}
return HAL_OK;
8002572: 2300 movs r3, #0
}
8002574: 4618 mov r0, r3
8002576: f507 7700 add.w r7, r7, #512 @ 0x200
800257a: 46bd mov sp, r7
800257c: bd80 pop {r7, pc}
800257e: bf00 nop
8002580: 40021000 .word 0x40021000
08002584 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002584: b580 push {r7, lr}
8002586: b09e sub sp, #120 @ 0x78
8002588: af00 add r7, sp, #0
800258a: 6078 str r0, [r7, #4]
800258c: 6039 str r1, [r7, #0]
uint32_t tickstart = 0U;
800258e: 2300 movs r3, #0
8002590: 677b str r3, [r7, #116] @ 0x74
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002592: 687b ldr r3, [r7, #4]
8002594: 2b00 cmp r3, #0
8002596: d101 bne.n 800259c <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002598: 2301 movs r3, #1
800259a: e162 b.n 8002862 <HAL_RCC_ClockConfig+0x2de>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
800259c: 4b90 ldr r3, [pc, #576] @ (80027e0 <HAL_RCC_ClockConfig+0x25c>)
800259e: 681b ldr r3, [r3, #0]
80025a0: f003 0307 and.w r3, r3, #7
80025a4: 683a ldr r2, [r7, #0]
80025a6: 429a cmp r2, r3
80025a8: d910 bls.n 80025cc <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80025aa: 4b8d ldr r3, [pc, #564] @ (80027e0 <HAL_RCC_ClockConfig+0x25c>)
80025ac: 681b ldr r3, [r3, #0]
80025ae: f023 0207 bic.w r2, r3, #7
80025b2: 498b ldr r1, [pc, #556] @ (80027e0 <HAL_RCC_ClockConfig+0x25c>)
80025b4: 683b ldr r3, [r7, #0]
80025b6: 4313 orrs r3, r2
80025b8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80025ba: 4b89 ldr r3, [pc, #548] @ (80027e0 <HAL_RCC_ClockConfig+0x25c>)
80025bc: 681b ldr r3, [r3, #0]
80025be: f003 0307 and.w r3, r3, #7
80025c2: 683a ldr r2, [r7, #0]
80025c4: 429a cmp r2, r3
80025c6: d001 beq.n 80025cc <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
80025c8: 2301 movs r3, #1
80025ca: e14a b.n 8002862 <HAL_RCC_ClockConfig+0x2de>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80025cc: 687b ldr r3, [r7, #4]
80025ce: 681b ldr r3, [r3, #0]
80025d0: f003 0302 and.w r3, r3, #2
80025d4: 2b00 cmp r3, #0
80025d6: d008 beq.n 80025ea <HAL_RCC_ClockConfig+0x66>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80025d8: 4b82 ldr r3, [pc, #520] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
80025da: 685b ldr r3, [r3, #4]
80025dc: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80025e0: 687b ldr r3, [r7, #4]
80025e2: 689b ldr r3, [r3, #8]
80025e4: 497f ldr r1, [pc, #508] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
80025e6: 4313 orrs r3, r2
80025e8: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80025ea: 687b ldr r3, [r7, #4]
80025ec: 681b ldr r3, [r3, #0]
80025ee: f003 0301 and.w r3, r3, #1
80025f2: 2b00 cmp r3, #0
80025f4: f000 80dc beq.w 80027b0 <HAL_RCC_ClockConfig+0x22c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80025f8: 687b ldr r3, [r7, #4]
80025fa: 685b ldr r3, [r3, #4]
80025fc: 2b01 cmp r3, #1
80025fe: d13c bne.n 800267a <HAL_RCC_ClockConfig+0xf6>
8002600: f44f 3300 mov.w r3, #131072 @ 0x20000
8002604: 673b str r3, [r7, #112] @ 0x70
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002606: 6f3b ldr r3, [r7, #112] @ 0x70
8002608: fa93 f3a3 rbit r3, r3
800260c: 66fb str r3, [r7, #108] @ 0x6c
return result;
800260e: 6efb ldr r3, [r7, #108] @ 0x6c
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002610: fab3 f383 clz r3, r3
8002614: b2db uxtb r3, r3
8002616: 095b lsrs r3, r3, #5
8002618: b2db uxtb r3, r3
800261a: f043 0301 orr.w r3, r3, #1
800261e: b2db uxtb r3, r3
8002620: 2b01 cmp r3, #1
8002622: d102 bne.n 800262a <HAL_RCC_ClockConfig+0xa6>
8002624: 4b6f ldr r3, [pc, #444] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
8002626: 681b ldr r3, [r3, #0]
8002628: e00f b.n 800264a <HAL_RCC_ClockConfig+0xc6>
800262a: f44f 3300 mov.w r3, #131072 @ 0x20000
800262e: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002630: 6ebb ldr r3, [r7, #104] @ 0x68
8002632: fa93 f3a3 rbit r3, r3
8002636: 667b str r3, [r7, #100] @ 0x64
8002638: f44f 3300 mov.w r3, #131072 @ 0x20000
800263c: 663b str r3, [r7, #96] @ 0x60
800263e: 6e3b ldr r3, [r7, #96] @ 0x60
8002640: fa93 f3a3 rbit r3, r3
8002644: 65fb str r3, [r7, #92] @ 0x5c
8002646: 4b67 ldr r3, [pc, #412] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
8002648: 6a5b ldr r3, [r3, #36] @ 0x24
800264a: f44f 3200 mov.w r2, #131072 @ 0x20000
800264e: 65ba str r2, [r7, #88] @ 0x58
8002650: 6dba ldr r2, [r7, #88] @ 0x58
8002652: fa92 f2a2 rbit r2, r2
8002656: 657a str r2, [r7, #84] @ 0x54
return result;
8002658: 6d7a ldr r2, [r7, #84] @ 0x54
800265a: fab2 f282 clz r2, r2
800265e: b2d2 uxtb r2, r2
8002660: f042 0220 orr.w r2, r2, #32
8002664: b2d2 uxtb r2, r2
8002666: f002 021f and.w r2, r2, #31
800266a: 2101 movs r1, #1
800266c: fa01 f202 lsl.w r2, r1, r2
8002670: 4013 ands r3, r2
8002672: 2b00 cmp r3, #0
8002674: d17b bne.n 800276e <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8002676: 2301 movs r3, #1
8002678: e0f3 b.n 8002862 <HAL_RCC_ClockConfig+0x2de>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800267a: 687b ldr r3, [r7, #4]
800267c: 685b ldr r3, [r3, #4]
800267e: 2b02 cmp r3, #2
8002680: d13c bne.n 80026fc <HAL_RCC_ClockConfig+0x178>
8002682: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8002686: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002688: 6d3b ldr r3, [r7, #80] @ 0x50
800268a: fa93 f3a3 rbit r3, r3
800268e: 64fb str r3, [r7, #76] @ 0x4c
return result;
8002690: 6cfb ldr r3, [r7, #76] @ 0x4c
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002692: fab3 f383 clz r3, r3
8002696: b2db uxtb r3, r3
8002698: 095b lsrs r3, r3, #5
800269a: b2db uxtb r3, r3
800269c: f043 0301 orr.w r3, r3, #1
80026a0: b2db uxtb r3, r3
80026a2: 2b01 cmp r3, #1
80026a4: d102 bne.n 80026ac <HAL_RCC_ClockConfig+0x128>
80026a6: 4b4f ldr r3, [pc, #316] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
80026a8: 681b ldr r3, [r3, #0]
80026aa: e00f b.n 80026cc <HAL_RCC_ClockConfig+0x148>
80026ac: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80026b0: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80026b2: 6cbb ldr r3, [r7, #72] @ 0x48
80026b4: fa93 f3a3 rbit r3, r3
80026b8: 647b str r3, [r7, #68] @ 0x44
80026ba: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80026be: 643b str r3, [r7, #64] @ 0x40
80026c0: 6c3b ldr r3, [r7, #64] @ 0x40
80026c2: fa93 f3a3 rbit r3, r3
80026c6: 63fb str r3, [r7, #60] @ 0x3c
80026c8: 4b46 ldr r3, [pc, #280] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
80026ca: 6a5b ldr r3, [r3, #36] @ 0x24
80026cc: f04f 7200 mov.w r2, #33554432 @ 0x2000000
80026d0: 63ba str r2, [r7, #56] @ 0x38
80026d2: 6bba ldr r2, [r7, #56] @ 0x38
80026d4: fa92 f2a2 rbit r2, r2
80026d8: 637a str r2, [r7, #52] @ 0x34
return result;
80026da: 6b7a ldr r2, [r7, #52] @ 0x34
80026dc: fab2 f282 clz r2, r2
80026e0: b2d2 uxtb r2, r2
80026e2: f042 0220 orr.w r2, r2, #32
80026e6: b2d2 uxtb r2, r2
80026e8: f002 021f and.w r2, r2, #31
80026ec: 2101 movs r1, #1
80026ee: fa01 f202 lsl.w r2, r1, r2
80026f2: 4013 ands r3, r2
80026f4: 2b00 cmp r3, #0
80026f6: d13a bne.n 800276e <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
80026f8: 2301 movs r3, #1
80026fa: e0b2 b.n 8002862 <HAL_RCC_ClockConfig+0x2de>
80026fc: 2302 movs r3, #2
80026fe: 633b str r3, [r7, #48] @ 0x30
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002700: 6b3b ldr r3, [r7, #48] @ 0x30
8002702: fa93 f3a3 rbit r3, r3
8002706: 62fb str r3, [r7, #44] @ 0x2c
return result;
8002708: 6afb ldr r3, [r7, #44] @ 0x2c
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800270a: fab3 f383 clz r3, r3
800270e: b2db uxtb r3, r3
8002710: 095b lsrs r3, r3, #5
8002712: b2db uxtb r3, r3
8002714: f043 0301 orr.w r3, r3, #1
8002718: b2db uxtb r3, r3
800271a: 2b01 cmp r3, #1
800271c: d102 bne.n 8002724 <HAL_RCC_ClockConfig+0x1a0>
800271e: 4b31 ldr r3, [pc, #196] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
8002720: 681b ldr r3, [r3, #0]
8002722: e00d b.n 8002740 <HAL_RCC_ClockConfig+0x1bc>
8002724: 2302 movs r3, #2
8002726: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002728: 6abb ldr r3, [r7, #40] @ 0x28
800272a: fa93 f3a3 rbit r3, r3
800272e: 627b str r3, [r7, #36] @ 0x24
8002730: 2302 movs r3, #2
8002732: 623b str r3, [r7, #32]
8002734: 6a3b ldr r3, [r7, #32]
8002736: fa93 f3a3 rbit r3, r3
800273a: 61fb str r3, [r7, #28]
800273c: 4b29 ldr r3, [pc, #164] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
800273e: 6a5b ldr r3, [r3, #36] @ 0x24
8002740: 2202 movs r2, #2
8002742: 61ba str r2, [r7, #24]
8002744: 69ba ldr r2, [r7, #24]
8002746: fa92 f2a2 rbit r2, r2
800274a: 617a str r2, [r7, #20]
return result;
800274c: 697a ldr r2, [r7, #20]
800274e: fab2 f282 clz r2, r2
8002752: b2d2 uxtb r2, r2
8002754: f042 0220 orr.w r2, r2, #32
8002758: b2d2 uxtb r2, r2
800275a: f002 021f and.w r2, r2, #31
800275e: 2101 movs r1, #1
8002760: fa01 f202 lsl.w r2, r1, r2
8002764: 4013 ands r3, r2
8002766: 2b00 cmp r3, #0
8002768: d101 bne.n 800276e <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
800276a: 2301 movs r3, #1
800276c: e079 b.n 8002862 <HAL_RCC_ClockConfig+0x2de>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800276e: 4b1d ldr r3, [pc, #116] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
8002770: 685b ldr r3, [r3, #4]
8002772: f023 0203 bic.w r2, r3, #3
8002776: 687b ldr r3, [r7, #4]
8002778: 685b ldr r3, [r3, #4]
800277a: 491a ldr r1, [pc, #104] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
800277c: 4313 orrs r3, r2
800277e: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002780: f7fe f8ba bl 80008f8 <HAL_GetTick>
8002784: 6778 str r0, [r7, #116] @ 0x74
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002786: e00a b.n 800279e <HAL_RCC_ClockConfig+0x21a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002788: f7fe f8b6 bl 80008f8 <HAL_GetTick>
800278c: 4602 mov r2, r0
800278e: 6f7b ldr r3, [r7, #116] @ 0x74
8002790: 1ad3 subs r3, r2, r3
8002792: f241 3288 movw r2, #5000 @ 0x1388
8002796: 4293 cmp r3, r2
8002798: d901 bls.n 800279e <HAL_RCC_ClockConfig+0x21a>
{
return HAL_TIMEOUT;
800279a: 2303 movs r3, #3
800279c: e061 b.n 8002862 <HAL_RCC_ClockConfig+0x2de>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800279e: 4b11 ldr r3, [pc, #68] @ (80027e4 <HAL_RCC_ClockConfig+0x260>)
80027a0: 685b ldr r3, [r3, #4]
80027a2: f003 020c and.w r2, r3, #12
80027a6: 687b ldr r3, [r7, #4]
80027a8: 685b ldr r3, [r3, #4]
80027aa: 009b lsls r3, r3, #2
80027ac: 429a cmp r2, r3
80027ae: d1eb bne.n 8002788 <HAL_RCC_ClockConfig+0x204>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80027b0: 4b0b ldr r3, [pc, #44] @ (80027e0 <HAL_RCC_ClockConfig+0x25c>)
80027b2: 681b ldr r3, [r3, #0]
80027b4: f003 0307 and.w r3, r3, #7
80027b8: 683a ldr r2, [r7, #0]
80027ba: 429a cmp r2, r3
80027bc: d214 bcs.n 80027e8 <HAL_RCC_ClockConfig+0x264>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80027be: 4b08 ldr r3, [pc, #32] @ (80027e0 <HAL_RCC_ClockConfig+0x25c>)
80027c0: 681b ldr r3, [r3, #0]
80027c2: f023 0207 bic.w r2, r3, #7
80027c6: 4906 ldr r1, [pc, #24] @ (80027e0 <HAL_RCC_ClockConfig+0x25c>)
80027c8: 683b ldr r3, [r7, #0]
80027ca: 4313 orrs r3, r2
80027cc: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80027ce: 4b04 ldr r3, [pc, #16] @ (80027e0 <HAL_RCC_ClockConfig+0x25c>)
80027d0: 681b ldr r3, [r3, #0]
80027d2: f003 0307 and.w r3, r3, #7
80027d6: 683a ldr r2, [r7, #0]
80027d8: 429a cmp r2, r3
80027da: d005 beq.n 80027e8 <HAL_RCC_ClockConfig+0x264>
{
return HAL_ERROR;
80027dc: 2301 movs r3, #1
80027de: e040 b.n 8002862 <HAL_RCC_ClockConfig+0x2de>
80027e0: 40022000 .word 0x40022000
80027e4: 40021000 .word 0x40021000
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80027e8: 687b ldr r3, [r7, #4]
80027ea: 681b ldr r3, [r3, #0]
80027ec: f003 0304 and.w r3, r3, #4
80027f0: 2b00 cmp r3, #0
80027f2: d008 beq.n 8002806 <HAL_RCC_ClockConfig+0x282>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80027f4: 4b1d ldr r3, [pc, #116] @ (800286c <HAL_RCC_ClockConfig+0x2e8>)
80027f6: 685b ldr r3, [r3, #4]
80027f8: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80027fc: 687b ldr r3, [r7, #4]
80027fe: 68db ldr r3, [r3, #12]
8002800: 491a ldr r1, [pc, #104] @ (800286c <HAL_RCC_ClockConfig+0x2e8>)
8002802: 4313 orrs r3, r2
8002804: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002806: 687b ldr r3, [r7, #4]
8002808: 681b ldr r3, [r3, #0]
800280a: f003 0308 and.w r3, r3, #8
800280e: 2b00 cmp r3, #0
8002810: d009 beq.n 8002826 <HAL_RCC_ClockConfig+0x2a2>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8002812: 4b16 ldr r3, [pc, #88] @ (800286c <HAL_RCC_ClockConfig+0x2e8>)
8002814: 685b ldr r3, [r3, #4]
8002816: f423 5260 bic.w r2, r3, #14336 @ 0x3800
800281a: 687b ldr r3, [r7, #4]
800281c: 691b ldr r3, [r3, #16]
800281e: 00db lsls r3, r3, #3
8002820: 4912 ldr r1, [pc, #72] @ (800286c <HAL_RCC_ClockConfig+0x2e8>)
8002822: 4313 orrs r3, r2
8002824: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8002826: f000 f829 bl 800287c <HAL_RCC_GetSysClockFreq>
800282a: 4601 mov r1, r0
800282c: 4b0f ldr r3, [pc, #60] @ (800286c <HAL_RCC_ClockConfig+0x2e8>)
800282e: 685b ldr r3, [r3, #4]
8002830: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002834: 22f0 movs r2, #240 @ 0xf0
8002836: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002838: 693a ldr r2, [r7, #16]
800283a: fa92 f2a2 rbit r2, r2
800283e: 60fa str r2, [r7, #12]
return result;
8002840: 68fa ldr r2, [r7, #12]
8002842: fab2 f282 clz r2, r2
8002846: b2d2 uxtb r2, r2
8002848: 40d3 lsrs r3, r2
800284a: 4a09 ldr r2, [pc, #36] @ (8002870 <HAL_RCC_ClockConfig+0x2ec>)
800284c: 5cd3 ldrb r3, [r2, r3]
800284e: fa21 f303 lsr.w r3, r1, r3
8002852: 4a08 ldr r2, [pc, #32] @ (8002874 <HAL_RCC_ClockConfig+0x2f0>)
8002854: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (uwTickPrio);
8002856: 4b08 ldr r3, [pc, #32] @ (8002878 <HAL_RCC_ClockConfig+0x2f4>)
8002858: 681b ldr r3, [r3, #0]
800285a: 4618 mov r0, r3
800285c: f7fe f808 bl 8000870 <HAL_InitTick>
return HAL_OK;
8002860: 2300 movs r3, #0
}
8002862: 4618 mov r0, r3
8002864: 3778 adds r7, #120 @ 0x78
8002866: 46bd mov sp, r7
8002868: bd80 pop {r7, pc}
800286a: bf00 nop
800286c: 40021000 .word 0x40021000
8002870: 08003228 .word 0x08003228
8002874: 20000000 .word 0x20000000
8002878: 20000004 .word 0x20000004
0800287c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800287c: b480 push {r7}
800287e: b08b sub sp, #44 @ 0x2c
8002880: af00 add r7, sp, #0
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8002882: 2300 movs r3, #0
8002884: 61fb str r3, [r7, #28]
8002886: 2300 movs r3, #0
8002888: 61bb str r3, [r7, #24]
800288a: 2300 movs r3, #0
800288c: 627b str r3, [r7, #36] @ 0x24
800288e: 2300 movs r3, #0
8002890: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
8002892: 2300 movs r3, #0
8002894: 623b str r3, [r7, #32]
tmpreg = RCC->CFGR;
8002896: 4b29 ldr r3, [pc, #164] @ (800293c <HAL_RCC_GetSysClockFreq+0xc0>)
8002898: 685b ldr r3, [r3, #4]
800289a: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
800289c: 69fb ldr r3, [r7, #28]
800289e: f003 030c and.w r3, r3, #12
80028a2: 2b04 cmp r3, #4
80028a4: d002 beq.n 80028ac <HAL_RCC_GetSysClockFreq+0x30>
80028a6: 2b08 cmp r3, #8
80028a8: d003 beq.n 80028b2 <HAL_RCC_GetSysClockFreq+0x36>
80028aa: e03c b.n 8002926 <HAL_RCC_GetSysClockFreq+0xaa>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80028ac: 4b24 ldr r3, [pc, #144] @ (8002940 <HAL_RCC_GetSysClockFreq+0xc4>)
80028ae: 623b str r3, [r7, #32]
break;
80028b0: e03c b.n 800292c <HAL_RCC_GetSysClockFreq+0xb0>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
80028b2: 69fb ldr r3, [r7, #28]
80028b4: f403 1370 and.w r3, r3, #3932160 @ 0x3c0000
80028b8: f44f 1270 mov.w r2, #3932160 @ 0x3c0000
80028bc: 60ba str r2, [r7, #8]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80028be: 68ba ldr r2, [r7, #8]
80028c0: fa92 f2a2 rbit r2, r2
80028c4: 607a str r2, [r7, #4]
return result;
80028c6: 687a ldr r2, [r7, #4]
80028c8: fab2 f282 clz r2, r2
80028cc: b2d2 uxtb r2, r2
80028ce: 40d3 lsrs r3, r2
80028d0: 4a1c ldr r2, [pc, #112] @ (8002944 <HAL_RCC_GetSysClockFreq+0xc8>)
80028d2: 5cd3 ldrb r3, [r2, r3]
80028d4: 617b str r3, [r7, #20]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
80028d6: 4b19 ldr r3, [pc, #100] @ (800293c <HAL_RCC_GetSysClockFreq+0xc0>)
80028d8: 6adb ldr r3, [r3, #44] @ 0x2c
80028da: f003 030f and.w r3, r3, #15
80028de: 220f movs r2, #15
80028e0: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80028e2: 693a ldr r2, [r7, #16]
80028e4: fa92 f2a2 rbit r2, r2
80028e8: 60fa str r2, [r7, #12]
return result;
80028ea: 68fa ldr r2, [r7, #12]
80028ec: fab2 f282 clz r2, r2
80028f0: b2d2 uxtb r2, r2
80028f2: 40d3 lsrs r3, r2
80028f4: 4a14 ldr r2, [pc, #80] @ (8002948 <HAL_RCC_GetSysClockFreq+0xcc>)
80028f6: 5cd3 ldrb r3, [r2, r3]
80028f8: 61bb str r3, [r7, #24]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
80028fa: 69fb ldr r3, [r7, #28]
80028fc: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002900: 2b00 cmp r3, #0
8002902: d008 beq.n 8002916 <HAL_RCC_GetSysClockFreq+0x9a>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
8002904: 4a0e ldr r2, [pc, #56] @ (8002940 <HAL_RCC_GetSysClockFreq+0xc4>)
8002906: 69bb ldr r3, [r7, #24]
8002908: fbb2 f2f3 udiv r2, r2, r3
800290c: 697b ldr r3, [r7, #20]
800290e: fb02 f303 mul.w r3, r2, r3
8002912: 627b str r3, [r7, #36] @ 0x24
8002914: e004 b.n 8002920 <HAL_RCC_GetSysClockFreq+0xa4>
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
8002916: 697b ldr r3, [r7, #20]
8002918: 4a0c ldr r2, [pc, #48] @ (800294c <HAL_RCC_GetSysClockFreq+0xd0>)
800291a: fb02 f303 mul.w r3, r2, r3
800291e: 627b str r3, [r7, #36] @ 0x24
{
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
}
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
sysclockfreq = pllclk;
8002920: 6a7b ldr r3, [r7, #36] @ 0x24
8002922: 623b str r3, [r7, #32]
break;
8002924: e002 b.n 800292c <HAL_RCC_GetSysClockFreq+0xb0>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8002926: 4b0a ldr r3, [pc, #40] @ (8002950 <HAL_RCC_GetSysClockFreq+0xd4>)
8002928: 623b str r3, [r7, #32]
break;
800292a: bf00 nop
}
}
return sysclockfreq;
800292c: 6a3b ldr r3, [r7, #32]
}
800292e: 4618 mov r0, r3
8002930: 372c adds r7, #44 @ 0x2c
8002932: 46bd mov sp, r7
8002934: f85d 7b04 ldr.w r7, [sp], #4
8002938: 4770 bx lr
800293a: bf00 nop
800293c: 40021000 .word 0x40021000
8002940: 00f42400 .word 0x00f42400
8002944: 08003238 .word 0x08003238
8002948: 08003248 .word 0x08003248
800294c: 003d0900 .word 0x003d0900
8002950: 007a1200 .word 0x007a1200
08002954 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8002954: b580 push {r7, lr}
8002956: b084 sub sp, #16
8002958: af00 add r7, sp, #0
800295a: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
800295c: 687b ldr r3, [r7, #4]
800295e: 2b00 cmp r3, #0
8002960: d101 bne.n 8002966 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8002962: 2301 movs r3, #1
8002964: e09d b.n 8002aa2 <HAL_SPI_Init+0x14e>
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8002966: 687b ldr r3, [r7, #4]
8002968: 6a5b ldr r3, [r3, #36] @ 0x24
800296a: 2b00 cmp r3, #0
800296c: d108 bne.n 8002980 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
800296e: 687b ldr r3, [r7, #4]
8002970: 685b ldr r3, [r3, #4]
8002972: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002976: d009 beq.n 800298c <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8002978: 687b ldr r3, [r7, #4]
800297a: 2200 movs r2, #0
800297c: 61da str r2, [r3, #28]
800297e: e005 b.n 800298c <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8002980: 687b ldr r3, [r7, #4]
8002982: 2200 movs r2, #0
8002984: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8002986: 687b ldr r3, [r7, #4]
8002988: 2200 movs r2, #0
800298a: 615a str r2, [r3, #20]
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
800298c: 687b ldr r3, [r7, #4]
800298e: 2200 movs r2, #0
8002990: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8002992: 687b ldr r3, [r7, #4]
8002994: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
8002998: b2db uxtb r3, r3
800299a: 2b00 cmp r3, #0
800299c: d106 bne.n 80029ac <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
800299e: 687b ldr r3, [r7, #4]
80029a0: 2200 movs r2, #0
80029a2: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
80029a6: 6878 ldr r0, [r7, #4]
80029a8: f7fd fe94 bl 80006d4 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
80029ac: 687b ldr r3, [r7, #4]
80029ae: 2202 movs r2, #2
80029b0: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80029b4: 687b ldr r3, [r7, #4]
80029b6: 681b ldr r3, [r3, #0]
80029b8: 681a ldr r2, [r3, #0]
80029ba: 687b ldr r3, [r7, #4]
80029bc: 681b ldr r3, [r3, #0]
80029be: f022 0240 bic.w r2, r2, #64 @ 0x40
80029c2: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
80029c4: 687b ldr r3, [r7, #4]
80029c6: 68db ldr r3, [r3, #12]
80029c8: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
80029cc: d902 bls.n 80029d4 <HAL_SPI_Init+0x80>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
80029ce: 2300 movs r3, #0
80029d0: 60fb str r3, [r7, #12]
80029d2: e002 b.n 80029da <HAL_SPI_Init+0x86>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
80029d4: f44f 5380 mov.w r3, #4096 @ 0x1000
80029d8: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
80029da: 687b ldr r3, [r7, #4]
80029dc: 68db ldr r3, [r3, #12]
80029de: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
80029e2: d007 beq.n 80029f4 <HAL_SPI_Init+0xa0>
80029e4: 687b ldr r3, [r7, #4]
80029e6: 68db ldr r3, [r3, #12]
80029e8: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
80029ec: d002 beq.n 80029f4 <HAL_SPI_Init+0xa0>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80029ee: 687b ldr r3, [r7, #4]
80029f0: 2200 movs r2, #0
80029f2: 629a str r2, [r3, #40] @ 0x28
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
80029f4: 687b ldr r3, [r7, #4]
80029f6: 685b ldr r3, [r3, #4]
80029f8: f403 7282 and.w r2, r3, #260 @ 0x104
80029fc: 687b ldr r3, [r7, #4]
80029fe: 689b ldr r3, [r3, #8]
8002a00: f403 4304 and.w r3, r3, #33792 @ 0x8400
8002a04: 431a orrs r2, r3
8002a06: 687b ldr r3, [r7, #4]
8002a08: 691b ldr r3, [r3, #16]
8002a0a: f003 0302 and.w r3, r3, #2
8002a0e: 431a orrs r2, r3
8002a10: 687b ldr r3, [r7, #4]
8002a12: 695b ldr r3, [r3, #20]
8002a14: f003 0301 and.w r3, r3, #1
8002a18: 431a orrs r2, r3
8002a1a: 687b ldr r3, [r7, #4]
8002a1c: 699b ldr r3, [r3, #24]
8002a1e: f403 7300 and.w r3, r3, #512 @ 0x200
8002a22: 431a orrs r2, r3
8002a24: 687b ldr r3, [r7, #4]
8002a26: 69db ldr r3, [r3, #28]
8002a28: f003 0338 and.w r3, r3, #56 @ 0x38
8002a2c: 431a orrs r2, r3
8002a2e: 687b ldr r3, [r7, #4]
8002a30: 6a1b ldr r3, [r3, #32]
8002a32: f003 0380 and.w r3, r3, #128 @ 0x80
8002a36: ea42 0103 orr.w r1, r2, r3
8002a3a: 687b ldr r3, [r7, #4]
8002a3c: 6a9b ldr r3, [r3, #40] @ 0x28
8002a3e: f403 5200 and.w r2, r3, #8192 @ 0x2000
8002a42: 687b ldr r3, [r7, #4]
8002a44: 681b ldr r3, [r3, #0]
8002a46: 430a orrs r2, r1
8002a48: 601a str r2, [r3, #0]
}
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
8002a4a: 687b ldr r3, [r7, #4]
8002a4c: 699b ldr r3, [r3, #24]
8002a4e: 0c1b lsrs r3, r3, #16
8002a50: f003 0204 and.w r2, r3, #4
8002a54: 687b ldr r3, [r7, #4]
8002a56: 6a5b ldr r3, [r3, #36] @ 0x24
8002a58: f003 0310 and.w r3, r3, #16
8002a5c: 431a orrs r2, r3
8002a5e: 687b ldr r3, [r7, #4]
8002a60: 6b5b ldr r3, [r3, #52] @ 0x34
8002a62: f003 0308 and.w r3, r3, #8
8002a66: 431a orrs r2, r3
8002a68: 687b ldr r3, [r7, #4]
8002a6a: 68db ldr r3, [r3, #12]
8002a6c: f403 6370 and.w r3, r3, #3840 @ 0xf00
8002a70: ea42 0103 orr.w r1, r2, r3
8002a74: 68fb ldr r3, [r7, #12]
8002a76: f403 5280 and.w r2, r3, #4096 @ 0x1000
8002a7a: 687b ldr r3, [r7, #4]
8002a7c: 681b ldr r3, [r3, #0]
8002a7e: 430a orrs r2, r1
8002a80: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8002a82: 687b ldr r3, [r7, #4]
8002a84: 681b ldr r3, [r3, #0]
8002a86: 69da ldr r2, [r3, #28]
8002a88: 687b ldr r3, [r7, #4]
8002a8a: 681b ldr r3, [r3, #0]
8002a8c: f422 6200 bic.w r2, r2, #2048 @ 0x800
8002a90: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8002a92: 687b ldr r3, [r7, #4]
8002a94: 2200 movs r2, #0
8002a96: 661a str r2, [r3, #96] @ 0x60
hspi->State = HAL_SPI_STATE_READY;
8002a98: 687b ldr r3, [r7, #4]
8002a9a: 2201 movs r2, #1
8002a9c: f883 205d strb.w r2, [r3, #93] @ 0x5d
return HAL_OK;
8002aa0: 2300 movs r3, #0
}
8002aa2: 4618 mov r0, r3
8002aa4: 3710 adds r7, #16
8002aa6: 46bd mov sp, r7
8002aa8: bd80 pop {r7, pc}
08002aaa <HAL_SPI_TransmitReceive>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
8002aaa: b580 push {r7, lr}
8002aac: b08a sub sp, #40 @ 0x28
8002aae: af00 add r7, sp, #0
8002ab0: 60f8 str r0, [r7, #12]
8002ab2: 60b9 str r1, [r7, #8]
8002ab4: 607a str r2, [r7, #4]
8002ab6: 807b strh r3, [r7, #2]
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
8002ab8: 2301 movs r3, #1
8002aba: 627b str r3, [r7, #36] @ 0x24
HAL_StatusTypeDef errorcode = HAL_OK;
8002abc: 2300 movs r3, #0
8002abe: f887 3023 strb.w r3, [r7, #35] @ 0x23
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
8002ac2: 68fb ldr r3, [r7, #12]
8002ac4: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
8002ac8: 2b01 cmp r3, #1
8002aca: d101 bne.n 8002ad0 <HAL_SPI_TransmitReceive+0x26>
8002acc: 2302 movs r3, #2
8002ace: e20a b.n 8002ee6 <HAL_SPI_TransmitReceive+0x43c>
8002ad0: 68fb ldr r3, [r7, #12]
8002ad2: 2201 movs r2, #1
8002ad4: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8002ad8: f7fd ff0e bl 80008f8 <HAL_GetTick>
8002adc: 61f8 str r0, [r7, #28]
/* Init temporary variables */
tmp_state = hspi->State;
8002ade: 68fb ldr r3, [r7, #12]
8002ae0: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
8002ae4: 76fb strb r3, [r7, #27]
tmp_mode = hspi->Init.Mode;
8002ae6: 68fb ldr r3, [r7, #12]
8002ae8: 685b ldr r3, [r3, #4]
8002aea: 617b str r3, [r7, #20]
initial_TxXferCount = Size;
8002aec: 887b ldrh r3, [r7, #2]
8002aee: 827b strh r3, [r7, #18]
initial_RxXferCount = Size;
8002af0: 887b ldrh r3, [r7, #2]
8002af2: 823b strh r3, [r7, #16]
#if (USE_SPI_CRC != 0U)
spi_cr1 = READ_REG(hspi->Instance->CR1);
spi_cr2 = READ_REG(hspi->Instance->CR2);
#endif /* USE_SPI_CRC */
if (!((tmp_state == HAL_SPI_STATE_READY) || \
8002af4: 7efb ldrb r3, [r7, #27]
8002af6: 2b01 cmp r3, #1
8002af8: d00e beq.n 8002b18 <HAL_SPI_TransmitReceive+0x6e>
8002afa: 697b ldr r3, [r7, #20]
8002afc: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002b00: d106 bne.n 8002b10 <HAL_SPI_TransmitReceive+0x66>
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
8002b02: 68fb ldr r3, [r7, #12]
8002b04: 689b ldr r3, [r3, #8]
8002b06: 2b00 cmp r3, #0
8002b08: d102 bne.n 8002b10 <HAL_SPI_TransmitReceive+0x66>
8002b0a: 7efb ldrb r3, [r7, #27]
8002b0c: 2b04 cmp r3, #4
8002b0e: d003 beq.n 8002b18 <HAL_SPI_TransmitReceive+0x6e>
{
errorcode = HAL_BUSY;
8002b10: 2302 movs r3, #2
8002b12: f887 3023 strb.w r3, [r7, #35] @ 0x23
goto error;
8002b16: e1e0 b.n 8002eda <HAL_SPI_TransmitReceive+0x430>
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
8002b18: 68bb ldr r3, [r7, #8]
8002b1a: 2b00 cmp r3, #0
8002b1c: d005 beq.n 8002b2a <HAL_SPI_TransmitReceive+0x80>
8002b1e: 687b ldr r3, [r7, #4]
8002b20: 2b00 cmp r3, #0
8002b22: d002 beq.n 8002b2a <HAL_SPI_TransmitReceive+0x80>
8002b24: 887b ldrh r3, [r7, #2]
8002b26: 2b00 cmp r3, #0
8002b28: d103 bne.n 8002b32 <HAL_SPI_TransmitReceive+0x88>
{
errorcode = HAL_ERROR;
8002b2a: 2301 movs r3, #1
8002b2c: f887 3023 strb.w r3, [r7, #35] @ 0x23
goto error;
8002b30: e1d3 b.n 8002eda <HAL_SPI_TransmitReceive+0x430>
}
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
8002b32: 68fb ldr r3, [r7, #12]
8002b34: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
8002b38: b2db uxtb r3, r3
8002b3a: 2b04 cmp r3, #4
8002b3c: d003 beq.n 8002b46 <HAL_SPI_TransmitReceive+0x9c>
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
8002b3e: 68fb ldr r3, [r7, #12]
8002b40: 2205 movs r2, #5
8002b42: f883 205d strb.w r2, [r3, #93] @ 0x5d
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8002b46: 68fb ldr r3, [r7, #12]
8002b48: 2200 movs r2, #0
8002b4a: 661a str r2, [r3, #96] @ 0x60
hspi->pRxBuffPtr = (uint8_t *)pRxData;
8002b4c: 68fb ldr r3, [r7, #12]
8002b4e: 687a ldr r2, [r7, #4]
8002b50: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferCount = Size;
8002b52: 68fb ldr r3, [r7, #12]
8002b54: 887a ldrh r2, [r7, #2]
8002b56: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
hspi->RxXferSize = Size;
8002b5a: 68fb ldr r3, [r7, #12]
8002b5c: 887a ldrh r2, [r7, #2]
8002b5e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hspi->pTxBuffPtr = (uint8_t *)pTxData;
8002b62: 68fb ldr r3, [r7, #12]
8002b64: 68ba ldr r2, [r7, #8]
8002b66: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount = Size;
8002b68: 68fb ldr r3, [r7, #12]
8002b6a: 887a ldrh r2, [r7, #2]
8002b6c: 87da strh r2, [r3, #62] @ 0x3e
hspi->TxXferSize = Size;
8002b6e: 68fb ldr r3, [r7, #12]
8002b70: 887a ldrh r2, [r7, #2]
8002b72: 879a strh r2, [r3, #60] @ 0x3c
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
8002b74: 68fb ldr r3, [r7, #12]
8002b76: 2200 movs r2, #0
8002b78: 64da str r2, [r3, #76] @ 0x4c
hspi->TxISR = NULL;
8002b7a: 68fb ldr r3, [r7, #12]
8002b7c: 2200 movs r2, #0
8002b7e: 651a str r2, [r3, #80] @ 0x50
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Set the Rx Fifo threshold */
if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
8002b80: 68fb ldr r3, [r7, #12]
8002b82: 68db ldr r3, [r3, #12]
8002b84: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
8002b88: d802 bhi.n 8002b90 <HAL_SPI_TransmitReceive+0xe6>
8002b8a: 8a3b ldrh r3, [r7, #16]
8002b8c: 2b01 cmp r3, #1
8002b8e: d908 bls.n 8002ba2 <HAL_SPI_TransmitReceive+0xf8>
{
/* Set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
8002b90: 68fb ldr r3, [r7, #12]
8002b92: 681b ldr r3, [r3, #0]
8002b94: 685a ldr r2, [r3, #4]
8002b96: 68fb ldr r3, [r7, #12]
8002b98: 681b ldr r3, [r3, #0]
8002b9a: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8002b9e: 605a str r2, [r3, #4]
8002ba0: e007 b.n 8002bb2 <HAL_SPI_TransmitReceive+0x108>
}
else
{
/* Set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
8002ba2: 68fb ldr r3, [r7, #12]
8002ba4: 681b ldr r3, [r3, #0]
8002ba6: 685a ldr r2, [r3, #4]
8002ba8: 68fb ldr r3, [r7, #12]
8002baa: 681b ldr r3, [r3, #0]
8002bac: f442 5280 orr.w r2, r2, #4096 @ 0x1000
8002bb0: 605a str r2, [r3, #4]
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8002bb2: 68fb ldr r3, [r7, #12]
8002bb4: 681b ldr r3, [r3, #0]
8002bb6: 681b ldr r3, [r3, #0]
8002bb8: f003 0340 and.w r3, r3, #64 @ 0x40
8002bbc: 2b40 cmp r3, #64 @ 0x40
8002bbe: d007 beq.n 8002bd0 <HAL_SPI_TransmitReceive+0x126>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
8002bc0: 68fb ldr r3, [r7, #12]
8002bc2: 681b ldr r3, [r3, #0]
8002bc4: 681a ldr r2, [r3, #0]
8002bc6: 68fb ldr r3, [r7, #12]
8002bc8: 681b ldr r3, [r3, #0]
8002bca: f042 0240 orr.w r2, r2, #64 @ 0x40
8002bce: 601a str r2, [r3, #0]
}
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8002bd0: 68fb ldr r3, [r7, #12]
8002bd2: 68db ldr r3, [r3, #12]
8002bd4: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
8002bd8: f240 8081 bls.w 8002cde <HAL_SPI_TransmitReceive+0x234>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8002bdc: 68fb ldr r3, [r7, #12]
8002bde: 685b ldr r3, [r3, #4]
8002be0: 2b00 cmp r3, #0
8002be2: d002 beq.n 8002bea <HAL_SPI_TransmitReceive+0x140>
8002be4: 8a7b ldrh r3, [r7, #18]
8002be6: 2b01 cmp r3, #1
8002be8: d16d bne.n 8002cc6 <HAL_SPI_TransmitReceive+0x21c>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8002bea: 68fb ldr r3, [r7, #12]
8002bec: 6b9b ldr r3, [r3, #56] @ 0x38
8002bee: 881a ldrh r2, [r3, #0]
8002bf0: 68fb ldr r3, [r7, #12]
8002bf2: 681b ldr r3, [r3, #0]
8002bf4: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002bf6: 68fb ldr r3, [r7, #12]
8002bf8: 6b9b ldr r3, [r3, #56] @ 0x38
8002bfa: 1c9a adds r2, r3, #2
8002bfc: 68fb ldr r3, [r7, #12]
8002bfe: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
8002c00: 68fb ldr r3, [r7, #12]
8002c02: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002c04: b29b uxth r3, r3
8002c06: 3b01 subs r3, #1
8002c08: b29a uxth r2, r3
8002c0a: 68fb ldr r3, [r7, #12]
8002c0c: 87da strh r2, [r3, #62] @ 0x3e
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8002c0e: e05a b.n 8002cc6 <HAL_SPI_TransmitReceive+0x21c>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
8002c10: 68fb ldr r3, [r7, #12]
8002c12: 681b ldr r3, [r3, #0]
8002c14: 689b ldr r3, [r3, #8]
8002c16: f003 0302 and.w r3, r3, #2
8002c1a: 2b02 cmp r3, #2
8002c1c: d11b bne.n 8002c56 <HAL_SPI_TransmitReceive+0x1ac>
8002c1e: 68fb ldr r3, [r7, #12]
8002c20: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002c22: b29b uxth r3, r3
8002c24: 2b00 cmp r3, #0
8002c26: d016 beq.n 8002c56 <HAL_SPI_TransmitReceive+0x1ac>
8002c28: 6a7b ldr r3, [r7, #36] @ 0x24
8002c2a: 2b01 cmp r3, #1
8002c2c: d113 bne.n 8002c56 <HAL_SPI_TransmitReceive+0x1ac>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8002c2e: 68fb ldr r3, [r7, #12]
8002c30: 6b9b ldr r3, [r3, #56] @ 0x38
8002c32: 881a ldrh r2, [r3, #0]
8002c34: 68fb ldr r3, [r7, #12]
8002c36: 681b ldr r3, [r3, #0]
8002c38: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002c3a: 68fb ldr r3, [r7, #12]
8002c3c: 6b9b ldr r3, [r3, #56] @ 0x38
8002c3e: 1c9a adds r2, r3, #2
8002c40: 68fb ldr r3, [r7, #12]
8002c42: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
8002c44: 68fb ldr r3, [r7, #12]
8002c46: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002c48: b29b uxth r3, r3
8002c4a: 3b01 subs r3, #1
8002c4c: b29a uxth r2, r3
8002c4e: 68fb ldr r3, [r7, #12]
8002c50: 87da strh r2, [r3, #62] @ 0x3e
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
8002c52: 2300 movs r3, #0
8002c54: 627b str r3, [r7, #36] @ 0x24
}
#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
8002c56: 68fb ldr r3, [r7, #12]
8002c58: 681b ldr r3, [r3, #0]
8002c5a: 689b ldr r3, [r3, #8]
8002c5c: f003 0301 and.w r3, r3, #1
8002c60: 2b01 cmp r3, #1
8002c62: d11c bne.n 8002c9e <HAL_SPI_TransmitReceive+0x1f4>
8002c64: 68fb ldr r3, [r7, #12]
8002c66: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002c6a: b29b uxth r3, r3
8002c6c: 2b00 cmp r3, #0
8002c6e: d016 beq.n 8002c9e <HAL_SPI_TransmitReceive+0x1f4>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
8002c70: 68fb ldr r3, [r7, #12]
8002c72: 681b ldr r3, [r3, #0]
8002c74: 68da ldr r2, [r3, #12]
8002c76: 68fb ldr r3, [r7, #12]
8002c78: 6c1b ldr r3, [r3, #64] @ 0x40
8002c7a: b292 uxth r2, r2
8002c7c: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
8002c7e: 68fb ldr r3, [r7, #12]
8002c80: 6c1b ldr r3, [r3, #64] @ 0x40
8002c82: 1c9a adds r2, r3, #2
8002c84: 68fb ldr r3, [r7, #12]
8002c86: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferCount--;
8002c88: 68fb ldr r3, [r7, #12]
8002c8a: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002c8e: b29b uxth r3, r3
8002c90: 3b01 subs r3, #1
8002c92: b29a uxth r2, r3
8002c94: 68fb ldr r3, [r7, #12]
8002c96: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
8002c9a: 2301 movs r3, #1
8002c9c: 627b str r3, [r7, #36] @ 0x24
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
8002c9e: f7fd fe2b bl 80008f8 <HAL_GetTick>
8002ca2: 4602 mov r2, r0
8002ca4: 69fb ldr r3, [r7, #28]
8002ca6: 1ad3 subs r3, r2, r3
8002ca8: 6b3a ldr r2, [r7, #48] @ 0x30
8002caa: 429a cmp r2, r3
8002cac: d80b bhi.n 8002cc6 <HAL_SPI_TransmitReceive+0x21c>
8002cae: 6b3b ldr r3, [r7, #48] @ 0x30
8002cb0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8002cb4: d007 beq.n 8002cc6 <HAL_SPI_TransmitReceive+0x21c>
{
errorcode = HAL_TIMEOUT;
8002cb6: 2303 movs r3, #3
8002cb8: f887 3023 strb.w r3, [r7, #35] @ 0x23
hspi->State = HAL_SPI_STATE_READY;
8002cbc: 68fb ldr r3, [r7, #12]
8002cbe: 2201 movs r2, #1
8002cc0: f883 205d strb.w r2, [r3, #93] @ 0x5d
goto error;
8002cc4: e109 b.n 8002eda <HAL_SPI_TransmitReceive+0x430>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8002cc6: 68fb ldr r3, [r7, #12]
8002cc8: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002cca: b29b uxth r3, r3
8002ccc: 2b00 cmp r3, #0
8002cce: d19f bne.n 8002c10 <HAL_SPI_TransmitReceive+0x166>
8002cd0: 68fb ldr r3, [r7, #12]
8002cd2: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002cd6: b29b uxth r3, r3
8002cd8: 2b00 cmp r3, #0
8002cda: d199 bne.n 8002c10 <HAL_SPI_TransmitReceive+0x166>
8002cdc: e0e3 b.n 8002ea6 <HAL_SPI_TransmitReceive+0x3fc>
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8002cde: 68fb ldr r3, [r7, #12]
8002ce0: 685b ldr r3, [r3, #4]
8002ce2: 2b00 cmp r3, #0
8002ce4: d003 beq.n 8002cee <HAL_SPI_TransmitReceive+0x244>
8002ce6: 8a7b ldrh r3, [r7, #18]
8002ce8: 2b01 cmp r3, #1
8002cea: f040 80cf bne.w 8002e8c <HAL_SPI_TransmitReceive+0x3e2>
{
if (hspi->TxXferCount > 1U)
8002cee: 68fb ldr r3, [r7, #12]
8002cf0: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002cf2: b29b uxth r3, r3
8002cf4: 2b01 cmp r3, #1
8002cf6: d912 bls.n 8002d1e <HAL_SPI_TransmitReceive+0x274>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8002cf8: 68fb ldr r3, [r7, #12]
8002cfa: 6b9b ldr r3, [r3, #56] @ 0x38
8002cfc: 881a ldrh r2, [r3, #0]
8002cfe: 68fb ldr r3, [r7, #12]
8002d00: 681b ldr r3, [r3, #0]
8002d02: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002d04: 68fb ldr r3, [r7, #12]
8002d06: 6b9b ldr r3, [r3, #56] @ 0x38
8002d08: 1c9a adds r2, r3, #2
8002d0a: 68fb ldr r3, [r7, #12]
8002d0c: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount -= 2U;
8002d0e: 68fb ldr r3, [r7, #12]
8002d10: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002d12: b29b uxth r3, r3
8002d14: 3b02 subs r3, #2
8002d16: b29a uxth r2, r3
8002d18: 68fb ldr r3, [r7, #12]
8002d1a: 87da strh r2, [r3, #62] @ 0x3e
8002d1c: e0b6 b.n 8002e8c <HAL_SPI_TransmitReceive+0x3e2>
}
else
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
8002d1e: 68fb ldr r3, [r7, #12]
8002d20: 6b9a ldr r2, [r3, #56] @ 0x38
8002d22: 68fb ldr r3, [r7, #12]
8002d24: 681b ldr r3, [r3, #0]
8002d26: 330c adds r3, #12
8002d28: 7812 ldrb r2, [r2, #0]
8002d2a: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
8002d2c: 68fb ldr r3, [r7, #12]
8002d2e: 6b9b ldr r3, [r3, #56] @ 0x38
8002d30: 1c5a adds r2, r3, #1
8002d32: 68fb ldr r3, [r7, #12]
8002d34: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
8002d36: 68fb ldr r3, [r7, #12]
8002d38: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002d3a: b29b uxth r3, r3
8002d3c: 3b01 subs r3, #1
8002d3e: b29a uxth r2, r3
8002d40: 68fb ldr r3, [r7, #12]
8002d42: 87da strh r2, [r3, #62] @ 0x3e
}
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8002d44: e0a2 b.n 8002e8c <HAL_SPI_TransmitReceive+0x3e2>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
8002d46: 68fb ldr r3, [r7, #12]
8002d48: 681b ldr r3, [r3, #0]
8002d4a: 689b ldr r3, [r3, #8]
8002d4c: f003 0302 and.w r3, r3, #2
8002d50: 2b02 cmp r3, #2
8002d52: d134 bne.n 8002dbe <HAL_SPI_TransmitReceive+0x314>
8002d54: 68fb ldr r3, [r7, #12]
8002d56: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002d58: b29b uxth r3, r3
8002d5a: 2b00 cmp r3, #0
8002d5c: d02f beq.n 8002dbe <HAL_SPI_TransmitReceive+0x314>
8002d5e: 6a7b ldr r3, [r7, #36] @ 0x24
8002d60: 2b01 cmp r3, #1
8002d62: d12c bne.n 8002dbe <HAL_SPI_TransmitReceive+0x314>
{
if (hspi->TxXferCount > 1U)
8002d64: 68fb ldr r3, [r7, #12]
8002d66: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002d68: b29b uxth r3, r3
8002d6a: 2b01 cmp r3, #1
8002d6c: d912 bls.n 8002d94 <HAL_SPI_TransmitReceive+0x2ea>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8002d6e: 68fb ldr r3, [r7, #12]
8002d70: 6b9b ldr r3, [r3, #56] @ 0x38
8002d72: 881a ldrh r2, [r3, #0]
8002d74: 68fb ldr r3, [r7, #12]
8002d76: 681b ldr r3, [r3, #0]
8002d78: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002d7a: 68fb ldr r3, [r7, #12]
8002d7c: 6b9b ldr r3, [r3, #56] @ 0x38
8002d7e: 1c9a adds r2, r3, #2
8002d80: 68fb ldr r3, [r7, #12]
8002d82: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount -= 2U;
8002d84: 68fb ldr r3, [r7, #12]
8002d86: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002d88: b29b uxth r3, r3
8002d8a: 3b02 subs r3, #2
8002d8c: b29a uxth r2, r3
8002d8e: 68fb ldr r3, [r7, #12]
8002d90: 87da strh r2, [r3, #62] @ 0x3e
8002d92: e012 b.n 8002dba <HAL_SPI_TransmitReceive+0x310>
}
else
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
8002d94: 68fb ldr r3, [r7, #12]
8002d96: 6b9a ldr r2, [r3, #56] @ 0x38
8002d98: 68fb ldr r3, [r7, #12]
8002d9a: 681b ldr r3, [r3, #0]
8002d9c: 330c adds r3, #12
8002d9e: 7812 ldrb r2, [r2, #0]
8002da0: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
8002da2: 68fb ldr r3, [r7, #12]
8002da4: 6b9b ldr r3, [r3, #56] @ 0x38
8002da6: 1c5a adds r2, r3, #1
8002da8: 68fb ldr r3, [r7, #12]
8002daa: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
8002dac: 68fb ldr r3, [r7, #12]
8002dae: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002db0: b29b uxth r3, r3
8002db2: 3b01 subs r3, #1
8002db4: b29a uxth r2, r3
8002db6: 68fb ldr r3, [r7, #12]
8002db8: 87da strh r2, [r3, #62] @ 0x3e
}
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
8002dba: 2300 movs r3, #0
8002dbc: 627b str r3, [r7, #36] @ 0x24
}
#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
8002dbe: 68fb ldr r3, [r7, #12]
8002dc0: 681b ldr r3, [r3, #0]
8002dc2: 689b ldr r3, [r3, #8]
8002dc4: f003 0301 and.w r3, r3, #1
8002dc8: 2b01 cmp r3, #1
8002dca: d148 bne.n 8002e5e <HAL_SPI_TransmitReceive+0x3b4>
8002dcc: 68fb ldr r3, [r7, #12]
8002dce: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002dd2: b29b uxth r3, r3
8002dd4: 2b00 cmp r3, #0
8002dd6: d042 beq.n 8002e5e <HAL_SPI_TransmitReceive+0x3b4>
{
if (hspi->RxXferCount > 1U)
8002dd8: 68fb ldr r3, [r7, #12]
8002dda: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002dde: b29b uxth r3, r3
8002de0: 2b01 cmp r3, #1
8002de2: d923 bls.n 8002e2c <HAL_SPI_TransmitReceive+0x382>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
8002de4: 68fb ldr r3, [r7, #12]
8002de6: 681b ldr r3, [r3, #0]
8002de8: 68da ldr r2, [r3, #12]
8002dea: 68fb ldr r3, [r7, #12]
8002dec: 6c1b ldr r3, [r3, #64] @ 0x40
8002dee: b292 uxth r2, r2
8002df0: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
8002df2: 68fb ldr r3, [r7, #12]
8002df4: 6c1b ldr r3, [r3, #64] @ 0x40
8002df6: 1c9a adds r2, r3, #2
8002df8: 68fb ldr r3, [r7, #12]
8002dfa: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferCount -= 2U;
8002dfc: 68fb ldr r3, [r7, #12]
8002dfe: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002e02: b29b uxth r3, r3
8002e04: 3b02 subs r3, #2
8002e06: b29a uxth r2, r3
8002e08: 68fb ldr r3, [r7, #12]
8002e0a: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
if (hspi->RxXferCount <= 1U)
8002e0e: 68fb ldr r3, [r7, #12]
8002e10: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002e14: b29b uxth r3, r3
8002e16: 2b01 cmp r3, #1
8002e18: d81f bhi.n 8002e5a <HAL_SPI_TransmitReceive+0x3b0>
{
/* Set RX Fifo threshold before to switch on 8 bit data size */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
8002e1a: 68fb ldr r3, [r7, #12]
8002e1c: 681b ldr r3, [r3, #0]
8002e1e: 685a ldr r2, [r3, #4]
8002e20: 68fb ldr r3, [r7, #12]
8002e22: 681b ldr r3, [r3, #0]
8002e24: f442 5280 orr.w r2, r2, #4096 @ 0x1000
8002e28: 605a str r2, [r3, #4]
8002e2a: e016 b.n 8002e5a <HAL_SPI_TransmitReceive+0x3b0>
}
}
else
{
(*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
8002e2c: 68fb ldr r3, [r7, #12]
8002e2e: 681b ldr r3, [r3, #0]
8002e30: f103 020c add.w r2, r3, #12
8002e34: 68fb ldr r3, [r7, #12]
8002e36: 6c1b ldr r3, [r3, #64] @ 0x40
8002e38: 7812 ldrb r2, [r2, #0]
8002e3a: b2d2 uxtb r2, r2
8002e3c: 701a strb r2, [r3, #0]
hspi->pRxBuffPtr++;
8002e3e: 68fb ldr r3, [r7, #12]
8002e40: 6c1b ldr r3, [r3, #64] @ 0x40
8002e42: 1c5a adds r2, r3, #1
8002e44: 68fb ldr r3, [r7, #12]
8002e46: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferCount--;
8002e48: 68fb ldr r3, [r7, #12]
8002e4a: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002e4e: b29b uxth r3, r3
8002e50: 3b01 subs r3, #1
8002e52: b29a uxth r2, r3
8002e54: 68fb ldr r3, [r7, #12]
8002e56: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
}
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
8002e5a: 2301 movs r3, #1
8002e5c: 627b str r3, [r7, #36] @ 0x24
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
8002e5e: f7fd fd4b bl 80008f8 <HAL_GetTick>
8002e62: 4602 mov r2, r0
8002e64: 69fb ldr r3, [r7, #28]
8002e66: 1ad3 subs r3, r2, r3
8002e68: 6b3a ldr r2, [r7, #48] @ 0x30
8002e6a: 429a cmp r2, r3
8002e6c: d803 bhi.n 8002e76 <HAL_SPI_TransmitReceive+0x3cc>
8002e6e: 6b3b ldr r3, [r7, #48] @ 0x30
8002e70: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8002e74: d102 bne.n 8002e7c <HAL_SPI_TransmitReceive+0x3d2>
8002e76: 6b3b ldr r3, [r7, #48] @ 0x30
8002e78: 2b00 cmp r3, #0
8002e7a: d107 bne.n 8002e8c <HAL_SPI_TransmitReceive+0x3e2>
{
errorcode = HAL_TIMEOUT;
8002e7c: 2303 movs r3, #3
8002e7e: f887 3023 strb.w r3, [r7, #35] @ 0x23
hspi->State = HAL_SPI_STATE_READY;
8002e82: 68fb ldr r3, [r7, #12]
8002e84: 2201 movs r2, #1
8002e86: f883 205d strb.w r2, [r3, #93] @ 0x5d
goto error;
8002e8a: e026 b.n 8002eda <HAL_SPI_TransmitReceive+0x430>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8002e8c: 68fb ldr r3, [r7, #12]
8002e8e: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002e90: b29b uxth r3, r3
8002e92: 2b00 cmp r3, #0
8002e94: f47f af57 bne.w 8002d46 <HAL_SPI_TransmitReceive+0x29c>
8002e98: 68fb ldr r3, [r7, #12]
8002e9a: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
8002e9e: b29b uxth r3, r3
8002ea0: 2b00 cmp r3, #0
8002ea2: f47f af50 bne.w 8002d46 <HAL_SPI_TransmitReceive+0x29c>
errorcode = HAL_ERROR;
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
8002ea6: 69fa ldr r2, [r7, #28]
8002ea8: 6b39 ldr r1, [r7, #48] @ 0x30
8002eaa: 68f8 ldr r0, [r7, #12]
8002eac: f000 f93e bl 800312c <SPI_EndRxTxTransaction>
8002eb0: 4603 mov r3, r0
8002eb2: 2b00 cmp r3, #0
8002eb4: d005 beq.n 8002ec2 <HAL_SPI_TransmitReceive+0x418>
{
errorcode = HAL_ERROR;
8002eb6: 2301 movs r3, #1
8002eb8: f887 3023 strb.w r3, [r7, #35] @ 0x23
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
8002ebc: 68fb ldr r3, [r7, #12]
8002ebe: 2220 movs r2, #32
8002ec0: 661a str r2, [r3, #96] @ 0x60
}
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
8002ec2: 68fb ldr r3, [r7, #12]
8002ec4: 6e1b ldr r3, [r3, #96] @ 0x60
8002ec6: 2b00 cmp r3, #0
8002ec8: d003 beq.n 8002ed2 <HAL_SPI_TransmitReceive+0x428>
{
errorcode = HAL_ERROR;
8002eca: 2301 movs r3, #1
8002ecc: f887 3023 strb.w r3, [r7, #35] @ 0x23
8002ed0: e003 b.n 8002eda <HAL_SPI_TransmitReceive+0x430>
}
else
{
hspi->State = HAL_SPI_STATE_READY;
8002ed2: 68fb ldr r3, [r7, #12]
8002ed4: 2201 movs r2, #1
8002ed6: f883 205d strb.w r2, [r3, #93] @ 0x5d
}
error :
__HAL_UNLOCK(hspi);
8002eda: 68fb ldr r3, [r7, #12]
8002edc: 2200 movs r2, #0
8002ede: f883 205c strb.w r2, [r3, #92] @ 0x5c
return errorcode;
8002ee2: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
}
8002ee6: 4618 mov r0, r3
8002ee8: 3728 adds r7, #40 @ 0x28
8002eea: 46bd mov sp, r7
8002eec: bd80 pop {r7, pc}
...
08002ef0 <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
8002ef0: b580 push {r7, lr}
8002ef2: b088 sub sp, #32
8002ef4: af00 add r7, sp, #0
8002ef6: 60f8 str r0, [r7, #12]
8002ef8: 60b9 str r1, [r7, #8]
8002efa: 603b str r3, [r7, #0]
8002efc: 4613 mov r3, r2
8002efe: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8002f00: f7fd fcfa bl 80008f8 <HAL_GetTick>
8002f04: 4602 mov r2, r0
8002f06: 6abb ldr r3, [r7, #40] @ 0x28
8002f08: 1a9b subs r3, r3, r2
8002f0a: 683a ldr r2, [r7, #0]
8002f0c: 4413 add r3, r2
8002f0e: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
8002f10: f7fd fcf2 bl 80008f8 <HAL_GetTick>
8002f14: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
8002f16: 4b39 ldr r3, [pc, #228] @ (8002ffc <SPI_WaitFlagStateUntilTimeout+0x10c>)
8002f18: 681b ldr r3, [r3, #0]
8002f1a: 015b lsls r3, r3, #5
8002f1c: 0d1b lsrs r3, r3, #20
8002f1e: 69fa ldr r2, [r7, #28]
8002f20: fb02 f303 mul.w r3, r2, r3
8002f24: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8002f26: e054 b.n 8002fd2 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (Timeout != HAL_MAX_DELAY)
8002f28: 683b ldr r3, [r7, #0]
8002f2a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8002f2e: d050 beq.n 8002fd2 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
8002f30: f7fd fce2 bl 80008f8 <HAL_GetTick>
8002f34: 4602 mov r2, r0
8002f36: 69bb ldr r3, [r7, #24]
8002f38: 1ad3 subs r3, r2, r3
8002f3a: 69fa ldr r2, [r7, #28]
8002f3c: 429a cmp r2, r3
8002f3e: d902 bls.n 8002f46 <SPI_WaitFlagStateUntilTimeout+0x56>
8002f40: 69fb ldr r3, [r7, #28]
8002f42: 2b00 cmp r3, #0
8002f44: d13d bne.n 8002fc2 <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8002f46: 68fb ldr r3, [r7, #12]
8002f48: 681b ldr r3, [r3, #0]
8002f4a: 685a ldr r2, [r3, #4]
8002f4c: 68fb ldr r3, [r7, #12]
8002f4e: 681b ldr r3, [r3, #0]
8002f50: f022 02e0 bic.w r2, r2, #224 @ 0xe0
8002f54: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8002f56: 68fb ldr r3, [r7, #12]
8002f58: 685b ldr r3, [r3, #4]
8002f5a: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002f5e: d111 bne.n 8002f84 <SPI_WaitFlagStateUntilTimeout+0x94>
8002f60: 68fb ldr r3, [r7, #12]
8002f62: 689b ldr r3, [r3, #8]
8002f64: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8002f68: d004 beq.n 8002f74 <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
8002f6a: 68fb ldr r3, [r7, #12]
8002f6c: 689b ldr r3, [r3, #8]
8002f6e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002f72: d107 bne.n 8002f84 <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8002f74: 68fb ldr r3, [r7, #12]
8002f76: 681b ldr r3, [r3, #0]
8002f78: 681a ldr r2, [r3, #0]
8002f7a: 68fb ldr r3, [r7, #12]
8002f7c: 681b ldr r3, [r3, #0]
8002f7e: f022 0240 bic.w r2, r2, #64 @ 0x40
8002f82: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8002f84: 68fb ldr r3, [r7, #12]
8002f86: 6a9b ldr r3, [r3, #40] @ 0x28
8002f88: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8002f8c: d10f bne.n 8002fae <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
8002f8e: 68fb ldr r3, [r7, #12]
8002f90: 681b ldr r3, [r3, #0]
8002f92: 681a ldr r2, [r3, #0]
8002f94: 68fb ldr r3, [r7, #12]
8002f96: 681b ldr r3, [r3, #0]
8002f98: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8002f9c: 601a str r2, [r3, #0]
8002f9e: 68fb ldr r3, [r7, #12]
8002fa0: 681b ldr r3, [r3, #0]
8002fa2: 681a ldr r2, [r3, #0]
8002fa4: 68fb ldr r3, [r7, #12]
8002fa6: 681b ldr r3, [r3, #0]
8002fa8: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8002fac: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
8002fae: 68fb ldr r3, [r7, #12]
8002fb0: 2201 movs r2, #1
8002fb2: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8002fb6: 68fb ldr r3, [r7, #12]
8002fb8: 2200 movs r2, #0
8002fba: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
8002fbe: 2303 movs r3, #3
8002fc0: e017 b.n 8002ff2 <SPI_WaitFlagStateUntilTimeout+0x102>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
8002fc2: 697b ldr r3, [r7, #20]
8002fc4: 2b00 cmp r3, #0
8002fc6: d101 bne.n 8002fcc <SPI_WaitFlagStateUntilTimeout+0xdc>
{
tmp_timeout = 0U;
8002fc8: 2300 movs r3, #0
8002fca: 61fb str r3, [r7, #28]
}
count--;
8002fcc: 697b ldr r3, [r7, #20]
8002fce: 3b01 subs r3, #1
8002fd0: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8002fd2: 68fb ldr r3, [r7, #12]
8002fd4: 681b ldr r3, [r3, #0]
8002fd6: 689a ldr r2, [r3, #8]
8002fd8: 68bb ldr r3, [r7, #8]
8002fda: 4013 ands r3, r2
8002fdc: 68ba ldr r2, [r7, #8]
8002fde: 429a cmp r2, r3
8002fe0: bf0c ite eq
8002fe2: 2301 moveq r3, #1
8002fe4: 2300 movne r3, #0
8002fe6: b2db uxtb r3, r3
8002fe8: 461a mov r2, r3
8002fea: 79fb ldrb r3, [r7, #7]
8002fec: 429a cmp r2, r3
8002fee: d19b bne.n 8002f28 <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
return HAL_OK;
8002ff0: 2300 movs r3, #0
}
8002ff2: 4618 mov r0, r3
8002ff4: 3720 adds r7, #32
8002ff6: 46bd mov sp, r7
8002ff8: bd80 pop {r7, pc}
8002ffa: bf00 nop
8002ffc: 20000000 .word 0x20000000
08003000 <SPI_WaitFifoStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
8003000: b580 push {r7, lr}
8003002: b08a sub sp, #40 @ 0x28
8003004: af00 add r7, sp, #0
8003006: 60f8 str r0, [r7, #12]
8003008: 60b9 str r1, [r7, #8]
800300a: 607a str r2, [r7, #4]
800300c: 603b str r3, [r7, #0]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
800300e: 2300 movs r3, #0
8003010: 75fb strb r3, [r7, #23]
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8003012: f7fd fc71 bl 80008f8 <HAL_GetTick>
8003016: 4602 mov r2, r0
8003018: 6b3b ldr r3, [r7, #48] @ 0x30
800301a: 1a9b subs r3, r3, r2
800301c: 683a ldr r2, [r7, #0]
800301e: 4413 add r3, r2
8003020: 627b str r3, [r7, #36] @ 0x24
tmp_tickstart = HAL_GetTick();
8003022: f7fd fc69 bl 80008f8 <HAL_GetTick>
8003026: 6238 str r0, [r7, #32]
/* Initialize the 8bit temporary pointer */
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
8003028: 68fb ldr r3, [r7, #12]
800302a: 681b ldr r3, [r3, #0]
800302c: 330c adds r3, #12
800302e: 61fb str r3, [r7, #28]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
8003030: 4b3d ldr r3, [pc, #244] @ (8003128 <SPI_WaitFifoStateUntilTimeout+0x128>)
8003032: 681a ldr r2, [r3, #0]
8003034: 4613 mov r3, r2
8003036: 009b lsls r3, r3, #2
8003038: 4413 add r3, r2
800303a: 00da lsls r2, r3, #3
800303c: 1ad3 subs r3, r2, r3
800303e: 0d1b lsrs r3, r3, #20
8003040: 6a7a ldr r2, [r7, #36] @ 0x24
8003042: fb02 f303 mul.w r3, r2, r3
8003046: 61bb str r3, [r7, #24]
while ((hspi->Instance->SR & Fifo) != State)
8003048: e060 b.n 800310c <SPI_WaitFifoStateUntilTimeout+0x10c>
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
800304a: 68bb ldr r3, [r7, #8]
800304c: f5b3 6fc0 cmp.w r3, #1536 @ 0x600
8003050: d107 bne.n 8003062 <SPI_WaitFifoStateUntilTimeout+0x62>
8003052: 687b ldr r3, [r7, #4]
8003054: 2b00 cmp r3, #0
8003056: d104 bne.n 8003062 <SPI_WaitFifoStateUntilTimeout+0x62>
{
/* Flush Data Register by a blank read */
tmpreg8 = *ptmpreg8;
8003058: 69fb ldr r3, [r7, #28]
800305a: 781b ldrb r3, [r3, #0]
800305c: b2db uxtb r3, r3
800305e: 75fb strb r3, [r7, #23]
/* To avoid GCC warning */
UNUSED(tmpreg8);
8003060: 7dfb ldrb r3, [r7, #23]
}
if (Timeout != HAL_MAX_DELAY)
8003062: 683b ldr r3, [r7, #0]
8003064: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8003068: d050 beq.n 800310c <SPI_WaitFifoStateUntilTimeout+0x10c>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
800306a: f7fd fc45 bl 80008f8 <HAL_GetTick>
800306e: 4602 mov r2, r0
8003070: 6a3b ldr r3, [r7, #32]
8003072: 1ad3 subs r3, r2, r3
8003074: 6a7a ldr r2, [r7, #36] @ 0x24
8003076: 429a cmp r2, r3
8003078: d902 bls.n 8003080 <SPI_WaitFifoStateUntilTimeout+0x80>
800307a: 6a7b ldr r3, [r7, #36] @ 0x24
800307c: 2b00 cmp r3, #0
800307e: d13d bne.n 80030fc <SPI_WaitFifoStateUntilTimeout+0xfc>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8003080: 68fb ldr r3, [r7, #12]
8003082: 681b ldr r3, [r3, #0]
8003084: 685a ldr r2, [r3, #4]
8003086: 68fb ldr r3, [r7, #12]
8003088: 681b ldr r3, [r3, #0]
800308a: f022 02e0 bic.w r2, r2, #224 @ 0xe0
800308e: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8003090: 68fb ldr r3, [r7, #12]
8003092: 685b ldr r3, [r3, #4]
8003094: f5b3 7f82 cmp.w r3, #260 @ 0x104
8003098: d111 bne.n 80030be <SPI_WaitFifoStateUntilTimeout+0xbe>
800309a: 68fb ldr r3, [r7, #12]
800309c: 689b ldr r3, [r3, #8]
800309e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80030a2: d004 beq.n 80030ae <SPI_WaitFifoStateUntilTimeout+0xae>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
80030a4: 68fb ldr r3, [r7, #12]
80030a6: 689b ldr r3, [r3, #8]
80030a8: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80030ac: d107 bne.n 80030be <SPI_WaitFifoStateUntilTimeout+0xbe>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80030ae: 68fb ldr r3, [r7, #12]
80030b0: 681b ldr r3, [r3, #0]
80030b2: 681a ldr r2, [r3, #0]
80030b4: 68fb ldr r3, [r7, #12]
80030b6: 681b ldr r3, [r3, #0]
80030b8: f022 0240 bic.w r2, r2, #64 @ 0x40
80030bc: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
80030be: 68fb ldr r3, [r7, #12]
80030c0: 6a9b ldr r3, [r3, #40] @ 0x28
80030c2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80030c6: d10f bne.n 80030e8 <SPI_WaitFifoStateUntilTimeout+0xe8>
{
SPI_RESET_CRC(hspi);
80030c8: 68fb ldr r3, [r7, #12]
80030ca: 681b ldr r3, [r3, #0]
80030cc: 681a ldr r2, [r3, #0]
80030ce: 68fb ldr r3, [r7, #12]
80030d0: 681b ldr r3, [r3, #0]
80030d2: f422 5200 bic.w r2, r2, #8192 @ 0x2000
80030d6: 601a str r2, [r3, #0]
80030d8: 68fb ldr r3, [r7, #12]
80030da: 681b ldr r3, [r3, #0]
80030dc: 681a ldr r2, [r3, #0]
80030de: 68fb ldr r3, [r7, #12]
80030e0: 681b ldr r3, [r3, #0]
80030e2: f442 5200 orr.w r2, r2, #8192 @ 0x2000
80030e6: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
80030e8: 68fb ldr r3, [r7, #12]
80030ea: 2201 movs r2, #1
80030ec: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
80030f0: 68fb ldr r3, [r7, #12]
80030f2: 2200 movs r2, #0
80030f4: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
80030f8: 2303 movs r3, #3
80030fa: e010 b.n 800311e <SPI_WaitFifoStateUntilTimeout+0x11e>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
80030fc: 69bb ldr r3, [r7, #24]
80030fe: 2b00 cmp r3, #0
8003100: d101 bne.n 8003106 <SPI_WaitFifoStateUntilTimeout+0x106>
{
tmp_timeout = 0U;
8003102: 2300 movs r3, #0
8003104: 627b str r3, [r7, #36] @ 0x24
}
count--;
8003106: 69bb ldr r3, [r7, #24]
8003108: 3b01 subs r3, #1
800310a: 61bb str r3, [r7, #24]
while ((hspi->Instance->SR & Fifo) != State)
800310c: 68fb ldr r3, [r7, #12]
800310e: 681b ldr r3, [r3, #0]
8003110: 689a ldr r2, [r3, #8]
8003112: 68bb ldr r3, [r7, #8]
8003114: 4013 ands r3, r2
8003116: 687a ldr r2, [r7, #4]
8003118: 429a cmp r2, r3
800311a: d196 bne.n 800304a <SPI_WaitFifoStateUntilTimeout+0x4a>
}
}
return HAL_OK;
800311c: 2300 movs r3, #0
}
800311e: 4618 mov r0, r3
8003120: 3728 adds r7, #40 @ 0x28
8003122: 46bd mov sp, r7
8003124: bd80 pop {r7, pc}
8003126: bf00 nop
8003128: 20000000 .word 0x20000000
0800312c <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
800312c: b580 push {r7, lr}
800312e: b086 sub sp, #24
8003130: af02 add r7, sp, #8
8003132: 60f8 str r0, [r7, #12]
8003134: 60b9 str r1, [r7, #8]
8003136: 607a str r2, [r7, #4]
/* Control if the TX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
8003138: 687b ldr r3, [r7, #4]
800313a: 9300 str r3, [sp, #0]
800313c: 68bb ldr r3, [r7, #8]
800313e: 2200 movs r2, #0
8003140: f44f 51c0 mov.w r1, #6144 @ 0x1800
8003144: 68f8 ldr r0, [r7, #12]
8003146: f7ff ff5b bl 8003000 <SPI_WaitFifoStateUntilTimeout>
800314a: 4603 mov r3, r0
800314c: 2b00 cmp r3, #0
800314e: d007 beq.n 8003160 <SPI_EndRxTxTransaction+0x34>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8003150: 68fb ldr r3, [r7, #12]
8003152: 6e1b ldr r3, [r3, #96] @ 0x60
8003154: f043 0220 orr.w r2, r3, #32
8003158: 68fb ldr r3, [r7, #12]
800315a: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
800315c: 2303 movs r3, #3
800315e: e027 b.n 80031b0 <SPI_EndRxTxTransaction+0x84>
}
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8003160: 687b ldr r3, [r7, #4]
8003162: 9300 str r3, [sp, #0]
8003164: 68bb ldr r3, [r7, #8]
8003166: 2200 movs r2, #0
8003168: 2180 movs r1, #128 @ 0x80
800316a: 68f8 ldr r0, [r7, #12]
800316c: f7ff fec0 bl 8002ef0 <SPI_WaitFlagStateUntilTimeout>
8003170: 4603 mov r3, r0
8003172: 2b00 cmp r3, #0
8003174: d007 beq.n 8003186 <SPI_EndRxTxTransaction+0x5a>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8003176: 68fb ldr r3, [r7, #12]
8003178: 6e1b ldr r3, [r3, #96] @ 0x60
800317a: f043 0220 orr.w r2, r3, #32
800317e: 68fb ldr r3, [r7, #12]
8003180: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
8003182: 2303 movs r3, #3
8003184: e014 b.n 80031b0 <SPI_EndRxTxTransaction+0x84>
}
/* Control if the RX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
8003186: 687b ldr r3, [r7, #4]
8003188: 9300 str r3, [sp, #0]
800318a: 68bb ldr r3, [r7, #8]
800318c: 2200 movs r2, #0
800318e: f44f 61c0 mov.w r1, #1536 @ 0x600
8003192: 68f8 ldr r0, [r7, #12]
8003194: f7ff ff34 bl 8003000 <SPI_WaitFifoStateUntilTimeout>
8003198: 4603 mov r3, r0
800319a: 2b00 cmp r3, #0
800319c: d007 beq.n 80031ae <SPI_EndRxTxTransaction+0x82>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800319e: 68fb ldr r3, [r7, #12]
80031a0: 6e1b ldr r3, [r3, #96] @ 0x60
80031a2: f043 0220 orr.w r2, r3, #32
80031a6: 68fb ldr r3, [r7, #12]
80031a8: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
80031aa: 2303 movs r3, #3
80031ac: e000 b.n 80031b0 <SPI_EndRxTxTransaction+0x84>
}
return HAL_OK;
80031ae: 2300 movs r3, #0
}
80031b0: 4618 mov r0, r3
80031b2: 3710 adds r7, #16
80031b4: 46bd mov sp, r7
80031b6: bd80 pop {r7, pc}
080031b8 <memset>:
80031b8: 4402 add r2, r0
80031ba: 4603 mov r3, r0
80031bc: 4293 cmp r3, r2
80031be: d100 bne.n 80031c2 <memset+0xa>
80031c0: 4770 bx lr
80031c2: f803 1b01 strb.w r1, [r3], #1
80031c6: e7f9 b.n 80031bc <memset+0x4>
080031c8 <__libc_init_array>:
80031c8: b570 push {r4, r5, r6, lr}
80031ca: 4d0d ldr r5, [pc, #52] @ (8003200 <__libc_init_array+0x38>)
80031cc: 4c0d ldr r4, [pc, #52] @ (8003204 <__libc_init_array+0x3c>)
80031ce: 1b64 subs r4, r4, r5
80031d0: 10a4 asrs r4, r4, #2
80031d2: 2600 movs r6, #0
80031d4: 42a6 cmp r6, r4
80031d6: d109 bne.n 80031ec <__libc_init_array+0x24>
80031d8: 4d0b ldr r5, [pc, #44] @ (8003208 <__libc_init_array+0x40>)
80031da: 4c0c ldr r4, [pc, #48] @ (800320c <__libc_init_array+0x44>)
80031dc: f000 f818 bl 8003210 <_init>
80031e0: 1b64 subs r4, r4, r5
80031e2: 10a4 asrs r4, r4, #2
80031e4: 2600 movs r6, #0
80031e6: 42a6 cmp r6, r4
80031e8: d105 bne.n 80031f6 <__libc_init_array+0x2e>
80031ea: bd70 pop {r4, r5, r6, pc}
80031ec: f855 3b04 ldr.w r3, [r5], #4
80031f0: 4798 blx r3
80031f2: 3601 adds r6, #1
80031f4: e7ee b.n 80031d4 <__libc_init_array+0xc>
80031f6: f855 3b04 ldr.w r3, [r5], #4
80031fa: 4798 blx r3
80031fc: 3601 adds r6, #1
80031fe: e7f2 b.n 80031e6 <__libc_init_array+0x1e>
8003200: 08003258 .word 0x08003258
8003204: 08003258 .word 0x08003258
8003208: 08003258 .word 0x08003258
800320c: 0800325c .word 0x0800325c
08003210 <_init>:
8003210: b5f8 push {r3, r4, r5, r6, r7, lr}
8003212: bf00 nop
8003214: bcf8 pop {r3, r4, r5, r6, r7}
8003216: bc08 pop {r3}
8003218: 469e mov lr, r3
800321a: 4770 bx lr
0800321c <_fini>:
800321c: b5f8 push {r3, r4, r5, r6, r7, lr}
800321e: bf00 nop
8003220: bcf8 pop {r3, r4, r5, r6, r7}
8003222: bc08 pop {r3}
8003224: 469e mov lr, r3
8003226: 4770 bx lr
Reference in New Issue View Git Blame Copy Permalink