37 lines
1.7 KiB
Plaintext
37 lines
1.7 KiB
Plaintext
(version 1)
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(rule "0.15mm by default"
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(constraint track_width (min 0.15mm))
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(constraint clearance (min 0.15mm)))
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(rule "Via distance"
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(constraint hole_to_hole (min 0.3mm))
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(condition "A.Via_Type == 'Through' && B.Via_Type == 'Through'"))
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(rule "BGA neckdown"
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(constraint track_width (min 0.1mm) (opt 0.1mm))
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(constraint clearance (min 0.1mm) (opt 0.15mm))
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(constraint annular_width (min 0.05mm))
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(condition "A.intersectsArea('BGA_fanout')"))
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(rule "STM fanout"
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(constraint track_width (min 0.1mm) (opt 0.15mm))
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(constraint clearance (min 0.1mm) (opt 0.15mm))
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(condition "A.intersectsArea('STM_fanout')"))
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(rule "RAM via distance"
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(constraint hole_to_hole (min 0.2mm))
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(condition "A.NetClass == 'RAM' && (B.NetClass == 'RAM') && A.Via_Type == 'Through' && B.Via_Type == 'Through'"))
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(rule "RAM via size"
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(constraint annular_width (min 0.05mm))
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(constraint via_diameter (min 0.4mm))
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(condition "A.NetClass == 'RAM' || A.NetName == 'GND'"))
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(rule "RAM via clearance"
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(constraint hole_clearance (min 0.2mm))
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(condition "(A.NetClass == 'RAM' || A.NetName == 'GND') && B.NetClass == 'RAM' && A.Via_Type == 'Through'"))
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(rule "RAM GND coupling via distance"
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(constraint hole_to_hole (min 0.2mm))
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(condition "A.NetName == 'GND' && B.NetClass == 'RAM' && A.Via_Type == 'Through' && B.Via_Type == 'Through'"))
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(rule "RAM traces"
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(constraint track_width (min 0.1mm) (opt 0.1mm))
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(condition "A.NetClass == 'RAM'"))
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# Keep 50mil clearance to high-speed signals
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(rule "USB clearance"
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(constraint clearance (min 1.27mm))
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(condition "A.NetClass == 'USB' && !A.intersectsArea('USB_fanout') && (B.NetClass == 'CAN' || B.NetClass == 'Flash' || B.NetClass == 'RAM' || B.NetClass == 'SD' || B.NetClass == 'HS')"))
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