(version 1)
(rule "0.15mm by default"
	(constraint track_width (min 0.15mm))
	(constraint clearance (min 0.15mm)))
(rule "Via distance"
	(constraint hole_to_hole (min 0.3mm))
	(condition "A.Via_Type == 'Through' && B.Via_Type == 'Through'"))
(rule "BGA neckdown"
	(constraint track_width (min 0.1mm) (opt 0.1mm))
	(constraint clearance (min 0.1mm) (opt 0.15mm))
	(constraint annular_width (min 0.05mm))
	(condition "A.intersectsArea('BGA_fanout')"))
(rule "STM fanout"
	(constraint track_width (min 0.1mm) (opt 0.15mm))
	(constraint clearance (min 0.1mm) (opt 0.15mm))
	(condition "A.intersectsArea('STM_fanout')"))
(rule "RAM via distance"
	(constraint hole_to_hole (min 0.2mm))
	(condition "A.NetClass == 'RAM' && (B.NetClass == 'RAM') && A.Via_Type == 'Through' && B.Via_Type == 'Through'"))
(rule "RAM via size"
	(constraint annular_width (min 0.05mm))
	(constraint via_diameter (min 0.4mm))
	(condition "A.NetClass == 'RAM' || A.NetName == 'GND'"))
(rule "RAM via clearance"
	(constraint hole_clearance (min 0.2mm))
	(condition "(A.NetClass == 'RAM' || A.NetName == 'GND') && B.NetClass == 'RAM' && A.Via_Type == 'Through'"))
(rule "RAM GND coupling via distance"
	(constraint hole_to_hole (min 0.2mm))
	(condition "A.NetName == 'GND' && B.NetClass == 'RAM' && A.Via_Type == 'Through' && B.Via_Type == 'Through'"))
(rule "RAM traces"
	(constraint track_width (min 0.1mm) (opt 0.1mm))
	(condition "A.NetClass == 'RAM'"))
# Keep 50mil clearance to high-speed signals
(rule "USB clearance"
	(constraint clearance (min 1.27mm))
	(condition "A.NetClass == 'USB' && !A.intersectsArea('USB_fanout') && (B.NetClass == 'CAN' || B.NetClass == 'Flash' || B.NetClass == 'RAM' || B.NetClass == 'SD' || B.NetClass == 'HS')"))