 Jasper Blanckenburg
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3dac8e881f
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Redo RAM layout
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2024-10-11 17:35:47 +02:00 |
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Jasper Blanckenburg
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42e1fc35de
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Avoid Pxy_C pins
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2024-10-10 23:35:42 +02:00 |
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Jasper Blanckenburg
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f3914402ff
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More TODOs done
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2024-10-06 20:42:58 +02:00 |
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Jasper Blanckenburg
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4984542e45
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Fix a couple of TODOs
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2024-10-06 01:03:19 +02:00 |
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Jasper Blanckenburg
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b45f6bbb8b
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TODOs from PCB Review
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2024-10-05 21:30:36 +02:00 |
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Jasper Blanckenburg
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954281d81b
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Bigger copper pours for the LDOs
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2024-10-05 15:03:16 +02:00 |
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Jasper Blanckenburg
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c30b9e7df7
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Top/bottom GND plane, via stitching
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2024-10-03 17:37:15 +02:00 |
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Jasper Blanckenburg
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8a4c822450
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Finish routing
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2024-10-02 12:19:19 +02:00 |
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Jasper Blanckenburg
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8f40aceeb9
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Route power nets
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2024-10-02 02:35:39 +02:00 |
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Jasper Blanckenburg
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4bb89f776c
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Connect SWD
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2024-10-01 23:10:45 +02:00 |
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Jasper Blanckenburg
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f072a5ce1a
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Connect USB
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2024-10-01 22:35:02 +02:00 |
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Jasper Blanckenburg
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33024ed50b
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Layout flash/EEPROM/SD
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2024-10-01 21:08:55 +02:00 |
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Jasper Blanckenburg
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c6a802c991
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Layout HSE crystal
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2024-10-01 17:53:07 +02:00 |
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Jasper Blanckenburg
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bf0553f646
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Layout LSE crystal
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2024-09-29 19:57:36 +02:00 |
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Jasper Blanckenburg
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3bae23375c
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Fix DRC errors
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2024-09-29 13:53:12 +02:00 |
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Jasper Blanckenburg
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0cbbcca9d2
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Optimize RAM connections
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2024-09-29 13:37:31 +02:00 |
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Jasper Blanckenburg
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b26d0e5564
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Connect STM power pins
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2024-09-29 13:20:16 +02:00 |
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Jasper Blanckenburg
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b4764a8f11
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Connect RAM
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2024-09-29 04:14:08 +02:00 |
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Jasper Blanckenburg
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5911cd2b7c
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Start layouting RAM
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2024-09-29 01:15:12 +02:00 |
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Jasper Blanckenburg
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1362670b27
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Start layout
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2024-09-28 13:38:55 +02:00 |
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Jasper Blanckenburg
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8389ad5569
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Begin schematic
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2024-09-24 18:47:31 +02:00 |