690 lines
24 KiB
C++
690 lines
24 KiB
C++
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/**
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******************************************************************************
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* File Name : STM32DMA.cpp
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******************************************************************************
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* This file is generated by TouchGFX Generator 4.21.2. Please, do not edit!
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#include "stm32h7xx_hal.h"
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#include "stm32h7xx_hal_dma2d.h"
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#include <STM32DMA.hpp>
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#include <cassert>
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#include <touchgfx/Color.hpp>
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#include <touchgfx/hal/HAL.hpp>
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#include <touchgfx/hal/OSWrappers.hpp>
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#include <touchgfx/lcd/LCD.hpp>
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/* Makes touchgfx specific types and variables visible to this file */
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using namespace touchgfx;
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typedef struct
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{
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const uint16_t format;
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const uint16_t size;
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const uint32_t* const data;
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} clutData_t;
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extern "C" void DMA2D_IRQHandler()
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{
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/* Transfer Complete Interrupt management ************************************/
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if ((READ_REG(DMA2D->ISR) & DMA2D_FLAG_TC) != RESET)
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{
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/* Verify Transfer Complete Interrupt */
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if ((READ_REG(DMA2D->CR) & DMA2D_IT_TC) != RESET)
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{
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/* Disable the transfer complete interrupt */
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DMA2D->CR &= ~(DMA2D_IT_TC);
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/* Clear the transfer complete flag */
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DMA2D->IFCR = (DMA2D_FLAG_TC);
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/* Signal DMA queue of execution complete */
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touchgfx::HAL::getInstance()->signalDMAInterrupt();
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}
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}
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}
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STM32DMA::STM32DMA()
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: DMA_Interface(dma_queue), dma_queue(queue_storage, sizeof(queue_storage) / sizeof(queue_storage[0]))
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{
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}
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STM32DMA::~STM32DMA()
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{
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/* Disable DMA2D global Interrupt */
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NVIC_DisableIRQ(DMA2D_IRQn);
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}
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void STM32DMA::initialize()
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{
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/* Ensure DMA2D Clock is enabled */
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__HAL_RCC_DMA2D_CLK_ENABLE();
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__HAL_RCC_DMA2D_FORCE_RESET();
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__HAL_RCC_DMA2D_RELEASE_RESET();
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/* Enable DMA2D global Interrupt */
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HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2D_IRQn);
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}
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inline uint32_t STM32DMA::getChromARTInputFormat(Bitmap::BitmapFormat format)
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{
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// Default color mode set to ARGB8888
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uint32_t dma2dColorMode = DMA2D_INPUT_ARGB8888;
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switch (format)
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{
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case Bitmap::ARGB8888: /* DMA2D input mode set to 32bit ARGB */
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dma2dColorMode = DMA2D_INPUT_ARGB8888;
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break;
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case Bitmap::RGB888: /* DMA2D input mode set to 24bit RGB */
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dma2dColorMode = DMA2D_INPUT_RGB888;
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break;
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case Bitmap::RGB565: /* DMA2D input mode set to 16bit RGB */
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dma2dColorMode = DMA2D_INPUT_RGB565;
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break;
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case Bitmap::ARGB2222: /* Fall through */
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case Bitmap::ABGR2222: /* Fall through */
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case Bitmap::RGBA2222: /* Fall through */
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case Bitmap::BGRA2222: /* Fall through */
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case Bitmap::L8: /* DMA2D input mode set to 8bit Color Look up table*/
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dma2dColorMode = DMA2D_INPUT_L8;
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break;
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case Bitmap::BW: /* Fall through */
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case Bitmap::BW_RLE: /* Fall through */
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case Bitmap::GRAY4: /* Fall through */
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case Bitmap::GRAY2: /* Fall through */
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default: /* Unsupported input format for DMA2D */
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assert(0 && "Unsupported Format!");
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break;
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}
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return dma2dColorMode;
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}
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inline uint32_t STM32DMA::getChromARTOutputFormat(Bitmap::BitmapFormat format)
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{
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// Default color mode set to ARGB8888
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uint32_t dma2dColorMode = DMA2D_OUTPUT_ARGB8888;
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switch (format)
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{
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case Bitmap::ARGB8888: /* DMA2D output mode set to 32bit ARGB */
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dma2dColorMode = DMA2D_OUTPUT_ARGB8888;
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break;
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case Bitmap::RGB888: /* Fall through */
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case Bitmap::ARGB2222: /* Fall through */
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case Bitmap::ABGR2222: /* Fall through */
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case Bitmap::RGBA2222: /* Fall through */
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case Bitmap::BGRA2222: /* DMA2D output mode set to 24bit RGB */
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dma2dColorMode = DMA2D_OUTPUT_RGB888;
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break;
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case Bitmap::RGB565: /* DMA2D output mode set to 16bit RGB */
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dma2dColorMode = DMA2D_OUTPUT_RGB565;
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break;
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case Bitmap::L8: /* Fall through */
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case Bitmap::BW: /* Fall through */
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case Bitmap::BW_RLE: /* Fall through */
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case Bitmap::GRAY4: /* Fall through */
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case Bitmap::GRAY2: /* Fall through */
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default: /* Unsupported output format for DMA2D */
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assert(0 && "Unsupported Format!");
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break;
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}
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return dma2dColorMode;
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}
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BlitOperations STM32DMA::getBlitCaps()
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{
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return static_cast<BlitOperations>(BLIT_OP_FILL
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| BLIT_OP_FILL_WITH_ALPHA
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| BLIT_OP_COPY
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| BLIT_OP_COPY_L8
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| BLIT_OP_COPY_WITH_ALPHA
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| BLIT_OP_COPY_ARGB8888
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| BLIT_OP_COPY_ARGB8888_WITH_ALPHA
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| BLIT_OP_COPY_A4
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| BLIT_OP_COPY_A8);
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}
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/*
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* void STM32DMA::setupDataCopy(const BlitOp& blitOp) handles blit operation of
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* BLIT_OP_COPY
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* BLIT_OP_COPY_L8
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* BLIT_OP_COPY_WITH_ALPHA
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* BLIT_OP_COPY_ARGB8888
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* BLIT_OP_COPY_ARGB8888_WITH_ALPHA
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* BLIT_OP_COPY_A4
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* BLIT_OP_COPY_A8
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*/
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void STM32DMA::setupDataCopy(const BlitOp& blitOp)
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{
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uint32_t dma2dForegroundColorMode = getChromARTInputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.srcFormat));
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uint32_t dma2dBackgroundColorMode = getChromARTInputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
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uint32_t dma2dOutputColorMode = getChromARTOutputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
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/* DMA2D OOR register configuration */
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WRITE_REG(DMA2D->OOR, blitOp.dstLoopStride - blitOp.nSteps);
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/* DMA2D BGOR register configuration */
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WRITE_REG(DMA2D->BGOR, blitOp.dstLoopStride - blitOp.nSteps);
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/* DMA2D FGOR register configuration */
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WRITE_REG(DMA2D->FGOR, blitOp.srcLoopStride - blitOp.nSteps);
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/* DMA2D OPFCCR register configuration */
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WRITE_REG(DMA2D->OPFCCR, dma2dOutputColorMode);
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/* Configure DMA2D data size */
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WRITE_REG(DMA2D->NLR, (blitOp.nLoops | (blitOp.nSteps << DMA2D_NLR_PL_Pos)));
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/* Configure DMA2D destination address */
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WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Configure DMA2D source address */
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WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(blitOp.pSrc));
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switch (blitOp.operation)
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{
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case BLIT_OP_COPY_A4:
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A4 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* set DMA2D foreground color */
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WRITE_REG(DMA2D->FGCOLR, blitOp.color);
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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break;
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case BLIT_OP_COPY_A8:
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* set DMA2D foreground color */
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WRITE_REG(DMA2D->FGCOLR, blitOp.color);
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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break;
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case BLIT_OP_COPY_WITH_ALPHA:
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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break;
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case BLIT_OP_COPY_L8:
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{
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bool blend = true;
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const clutData_t* const palette = reinterpret_cast<const clutData_t*>(blitOp.pClut);
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/* Write foreground CLUT memory address */
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WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&palette->data));
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Configure CLUT */
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switch ((Bitmap::ClutFormat)palette->format)
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{
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case Bitmap::CLUT_FORMAT_L8_ARGB8888:
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/* Write foreground CLUT size and CLUT color mode */
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MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_ARGB8888 << DMA2D_FGPFCCR_CCM_Pos)));
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break;
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case Bitmap::CLUT_FORMAT_L8_RGB888:
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if(blitOp.alpha == 255)
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{
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blend = false;
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}
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MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_RGB888 << DMA2D_FGPFCCR_CCM_Pos)));
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break;
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case Bitmap::CLUT_FORMAT_L8_RGB565:
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default:
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assert(0 && "Unsupported format");
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break;
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}
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/* Enable the CLUT loading for the foreground */
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SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
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while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U)
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{
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}
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DMA2D->IFCR = (DMA2D_FLAG_CTC);
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/* Set DMA2D mode */
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if(blend)
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{
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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}
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else
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{
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WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_IT_TC | DMA2D_CR_START);
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}
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}
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break;
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case BLIT_OP_COPY_ARGB8888:
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case BLIT_OP_COPY_ARGB8888_WITH_ALPHA:
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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break;
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default: /* BLIT_OP_COPY */
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* Perform pixel-format-conversion (PFC) If Bitmap format is not same format as framebuffer format */
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if (blitOp.srcFormat != blitOp.dstFormat)
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{
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/* Start DMA2D : PFC Mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_IT_TC | DMA2D_CR_START);
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}
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else
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{
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/* Start DMA2D : M2M Mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M | DMA2D_IT_TC | DMA2D_CR_START);
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}
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break;
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}
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}
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/*
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* void STM32DMA::setupDataFill(const BlitOp& blitOp) handles blit operation of
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* BLIT_OP_FILL
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* BLIT_OP_FILL_WITH_ALPHA
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*/
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void STM32DMA::setupDataFill(const BlitOp& blitOp)
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{
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uint32_t dma2dOutputColorMode = getChromARTOutputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
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/* DMA2D OPFCCR register configuration */
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WRITE_REG(DMA2D->OPFCCR, dma2dOutputColorMode);
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/* Configure DMA2D data size */
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WRITE_REG(DMA2D->NLR, (blitOp.nLoops | (blitOp.nSteps << DMA2D_NLR_PL_Pos)));
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/* Configure DMA2D destination address */
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WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* DMA2D OOR register configuration */
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WRITE_REG(DMA2D->OOR, blitOp.dstLoopStride - blitOp.nSteps);
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if (blitOp.operation == BLIT_OP_FILL_WITH_ALPHA)
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{
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/* DMA2D BGOR register configuration */
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WRITE_REG(DMA2D->BGOR, blitOp.dstLoopStride - blitOp.nSteps);
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/* DMA2D FGOR register configuration */
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WRITE_REG(DMA2D->FGOR, blitOp.dstLoopStride - blitOp.nSteps);
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dOutputColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Write DMA2D FGPFCCR register */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_REPLACE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | ((blitOp.alpha << 24) & DMA2D_FGPFCCR_ALPHA));
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/* DMA2D FGCOLR register configuration */
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WRITE_REG(DMA2D->FGCOLR, blitOp.color);
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Configure DMA2D source address */
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WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Enable the Peripheral and Enable the transfer complete interrupt */
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WRITE_REG(DMA2D->CR, (DMA2D_IT_TC | DMA2D_CR_START | DMA2D_M2M_BLEND));
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}
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else
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{
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/* Write DMA2D FGPFCCR register */
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WRITE_REG(DMA2D->FGPFCCR, dma2dOutputColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_FGPFCCR_AM_Pos));
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/* DMA2D FGOR register configuration */
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WRITE_REG(DMA2D->FGOR, 0);
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/* Set color */
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WRITE_REG(DMA2D->OCOLR, ((blitOp.color >> 8) & 0xF800) | ((blitOp.color >> 5) & 0x07E0) | ((blitOp.color >> 3) & 0x001F));
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/* Enable the Peripheral and Enable the transfer complete interrupt */
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WRITE_REG(DMA2D->CR, (DMA2D_IT_TC | DMA2D_CR_START | DMA2D_R2M));
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}
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}
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namespace touchgfx
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{
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namespace paint
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{
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namespace
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{
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const clutData_t* L8CLUT = 0;
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uint32_t L8ClutLoaded = 0;
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} // namespace
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void setL8Pallette(const uint8_t* const data)
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{
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L8CLUT = reinterpret_cast<const clutData_t*>(data - offsetof(clutData_t, data));
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L8ClutLoaded = 0;
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}
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/**
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* @fn void tearDown();
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*
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* @brief Waits until previous DMA drawing operation has finished
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*/
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void tearDown()
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{
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/* Wait for DMA2D to finish last run */
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while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
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/* Clear transfer flags */
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WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
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}
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namespace rgb565
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{
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/**
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* @fn void lineFromColor();
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*
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* @brief Renders Canvas Widget chunks using DMA.
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* This functions will not generate an interrupt, and will not affect the DMA queue.
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*/
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void lineFromColor(uint16_t* const ptr, const unsigned count, const uint32_t color, const uint8_t alpha, const uint32_t color565)
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{
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/* Wait for DMA2D to finish last run */
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while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
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/* Clear transfer flags */
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WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
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/* DMA2D OPFCCR register configuration */
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WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
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/* Configure DMA2D data size */
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WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
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/* Configure DMA2D destination address */
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WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
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if (alpha < 0xFF)
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{
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, DMA2D_OUTPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Write DMA2D FGPFCCR register */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_REPLACE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | ((alpha << 24) & DMA2D_FGPFCCR_ALPHA));
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/* DMA2D FGCOLR register configuration */
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WRITE_REG(DMA2D->FGCOLR, color);
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, (uint32_t)ptr);
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/* Configure DMA2D source address */
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WRITE_REG(DMA2D->FGMAR, (uint32_t)ptr);
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/* Enable the Peripheral and Enable the transfer complete interrupt */
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WRITE_REG(DMA2D->CR, (DMA2D_CR_START | DMA2D_M2M_BLEND));
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}
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else
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{
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/* Write DMA2D FGPFCCR register */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_OUTPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_FGPFCCR_AM_Pos));
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/* Set color */
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WRITE_REG(DMA2D->OCOLR, color565);
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/* Enable the Peripheral and Enable the transfer complete interrupt */
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WRITE_REG(DMA2D->CR, (DMA2D_CR_START | DMA2D_R2M));
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}
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}
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void lineFromRGB565(uint16_t* const ptr, const uint16_t* const data, const unsigned count, const uint8_t alpha)
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{
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/* Wait for DMA2D to finish last run */
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while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
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/* Clear transfer flags */
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WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
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/* DMA2D OPFCCR register configuration */
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WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
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/* Configure DMA2D data size */
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WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
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/* Configure DMA2D destination address */
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WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
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/* Configure DMA2D source address */
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WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
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if (alpha < 0xFF)
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{
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (alpha << 24));
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
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}
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else
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{
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (alpha << 24));
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/* Start DMA2D : M2M Mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M | DMA2D_CR_START);
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}
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}
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void lineFromARGB8888(uint16_t* const ptr, const uint32_t* const data, const unsigned count, const uint8_t alpha)
|
|
{
|
|
/* Wait for DMA2D to finish last run */
|
|
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
|
|
|
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/* Clear transfer flags */
|
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WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
|
|
|
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/* DMA2D OPFCCR register configuration */
|
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WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
|
|
|
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/* Configure DMA2D data size */
|
|
WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
|
|
|
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/* Configure DMA2D destination address */
|
|
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
|
|
|
|
/* Configure DMA2D source address */
|
|
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
|
|
|
|
/* Set DMA2D color mode and alpha mode */
|
|
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_ARGB8888 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << 24));
|
|
|
|
/* Write DMA2D BGPFCCR register */
|
|
WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
|
|
|
|
/* Configure DMA2D Stream source2 address */
|
|
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
|
|
|
|
/* Set DMA2D mode */
|
|
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
|
|
}
|
|
|
|
void lineFromL8RGB888(uint16_t* const ptr, const uint8_t* const data, const unsigned count, const uint8_t alpha)
|
|
{
|
|
/* wait for DMA2D to finish last run */
|
|
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
|
|
|
|
/* DMA2D OPFCCR register configuration */
|
|
WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
|
|
|
|
/* Configure DMA2D data size */
|
|
WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
|
|
|
|
/* Configure DMA2D destination address */
|
|
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
|
|
|
|
/* Configure DMA2D source address */
|
|
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
|
|
|
|
/* Configure DMA2D Stream source2 address */
|
|
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
|
|
|
|
/* Load CLUT if not already loaded */
|
|
if (L8ClutLoaded == 0)
|
|
{
|
|
/* Write foreground CLUT memory address */
|
|
WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&L8CLUT->data));
|
|
|
|
/* Set DMA2D color mode and alpha mode */
|
|
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_L8 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << 24));
|
|
|
|
MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((L8CLUT->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_RGB888 << DMA2D_FGPFCCR_CCM_Pos)));
|
|
|
|
/* Enable the CLUT loading for the foreground */
|
|
SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
|
|
|
|
/* Write DMA2D BGPFCCR register */
|
|
WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
|
|
|
|
/* Mark CLUT loaded */
|
|
L8ClutLoaded = 1;
|
|
|
|
/* Wait for load to finish */
|
|
while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U);
|
|
|
|
/* Clear CLUT Transfer Complete flag */
|
|
DMA2D->IFCR = (DMA2D_FLAG_CTC);
|
|
}
|
|
else
|
|
{
|
|
/* Set correct alpha for these pixels */
|
|
MODIFY_REG(DMA2D->FGPFCCR, DMA2D_BGPFCCR_ALPHA_Msk, alpha << 24);
|
|
}
|
|
|
|
/* Start pixel transfer in correct mode */
|
|
if (alpha < 0xFF)
|
|
{
|
|
/* Set DMA2D mode */
|
|
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
|
|
}
|
|
else
|
|
{
|
|
/* Set DMA2D mode */
|
|
WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_CR_START);
|
|
}
|
|
}
|
|
|
|
void lineFromL8ARGB8888(uint16_t* const ptr, const uint8_t* const data, const unsigned count, const uint8_t alpha)
|
|
{
|
|
/* wait for DMA2D to finish last run */
|
|
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
|
|
|
|
/* DMA2D OPFCCR register configuration */
|
|
WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
|
|
|
|
/* Configure DMA2D data size */
|
|
WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
|
|
|
|
/* Configure DMA2D destination address */
|
|
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
|
|
|
|
/* Configure DMA2D source address */
|
|
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
|
|
|
|
/* Configure DMA2D Stream source2 address */
|
|
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
|
|
|
|
/* Load CLUT if not already loaded */
|
|
if (L8ClutLoaded == 0)
|
|
{
|
|
/* Write foreground CLUT memory address */
|
|
WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&L8CLUT->data));
|
|
|
|
/* Set DMA2D color mode and alpha mode */
|
|
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_L8 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << 24));
|
|
|
|
MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((L8CLUT->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_ARGB8888 << DMA2D_FGPFCCR_CCM_Pos)));
|
|
|
|
/* Enable the CLUT loading for the foreground */
|
|
SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
|
|
|
|
/* Write DMA2D BGPFCCR register */
|
|
WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
|
|
|
|
/* Mark CLUT loaded */
|
|
L8ClutLoaded = 1;
|
|
|
|
/* Wait for load to finish */
|
|
while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U);
|
|
|
|
/* Clear CLUT Transfer Complete flag */
|
|
DMA2D->IFCR = (DMA2D_FLAG_CTC);
|
|
}
|
|
else
|
|
{
|
|
/* Set correct alpha for these pixels */
|
|
MODIFY_REG(DMA2D->FGPFCCR, DMA2D_BGPFCCR_ALPHA_Msk, alpha << 24);
|
|
}
|
|
|
|
/* Start pixel transfer in blending mode */
|
|
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
|
|
}
|
|
|
|
} // namespace rgb565
|
|
} // namespace paint
|
|
} // namespace touchgfx
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|