Add DRS paddle switch as PF14
This commit is contained in:
@ -37,16 +37,12 @@ extern "C" {
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
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#if defined(STM32H7) || defined(STM32MP1)
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#define CRYP_DATATYPE_32B CRYP_NO_SWAP
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#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
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#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
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#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
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#if defined(STM32U5)
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#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
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#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
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#endif /* STM32U5 */
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#endif /* STM32U5 || STM32H7 || STM32MP1 */
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#endif /* STM32H7 || STM32MP1 */
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/**
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* @}
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*/
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@ -113,6 +109,9 @@ extern "C" {
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#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
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#endif /* STM32U5 */
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#if defined(STM32H5)
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#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
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#endif /* STM32H5 */
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/**
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* @}
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*/
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@ -140,7 +139,8 @@ extern "C" {
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#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
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#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
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#if defined(STM32L0)
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#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
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#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
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input 1 for COMP1, LPTIM input 2 for COMP2 */
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#endif
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#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
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#if defined(STM32F373xC) || defined(STM32F378xx)
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@ -239,10 +239,12 @@ extern "C" {
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/** @defgroup CRC_Aliases CRC API aliases
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* @{
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*/
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#if defined(STM32C0)
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#if defined(STM32H5) || defined(STM32C0)
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#else
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#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
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#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
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#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
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inter STM32 series compatibility */
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#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
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inter STM32 series compatibility */
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#endif
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/**
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* @}
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@ -273,7 +275,7 @@ extern "C" {
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
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#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
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#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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@ -285,7 +287,13 @@ extern "C" {
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#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
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#if defined(STM32H5)
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#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
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#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
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defined(STM32F4) || defined(STM32G4)
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#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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#endif
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@ -350,7 +358,8 @@ extern "C" {
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#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
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#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
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#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
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#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
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defined(STM32L4S7xx) || defined(STM32L4S9xx)
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#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
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#endif
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@ -539,6 +548,16 @@ extern "C" {
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#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
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#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
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#endif /* STM32U5 */
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#if defined(STM32U0)
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#define OB_USER_nRST_STOP OB_USER_NRST_STOP
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#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
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#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
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#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
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#define OB_USER_nBOOT0 OB_USER_NBOOT0
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#define OB_USER_nBOOT1 OB_USER_NBOOT1
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#define OB_nBOOT0_RESET OB_NBOOT0_RESET
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#define OB_nBOOT0_SET OB_NBOOT0_SET
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#endif /* STM32U0 */
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/**
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* @}
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@ -582,6 +601,106 @@ extern "C" {
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#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
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#endif /* STM32G4 */
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#if defined(STM32H5)
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#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
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#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
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#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
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#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
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#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
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#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
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#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
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#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
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#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
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#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
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#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
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#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
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#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
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#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
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#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
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#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
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#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
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#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
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#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
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#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
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#define SYSCFG_ETH_MII SBS_ETH_MII
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#define SYSCFG_ETH_RMII SBS_ETH_RMII
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#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
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#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
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#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
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#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
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#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
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#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
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#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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#define SYSCFG_SAU SBS_SAU
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#define SYSCFG_MPU_SEC SBS_MPU_SEC
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#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
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#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
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#else
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#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
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#endif /* __ARM_FEATURE_CMSE */
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#define SYSCFG_CLK SBS_CLK
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#define SYSCFG_CLASSB SBS_CLASSB
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#define SYSCFG_FPU SBS_FPU
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#define SYSCFG_ALL SBS_ALL
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#define SYSCFG_SEC SBS_SEC
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#define SYSCFG_NSEC SBS_NSEC
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#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
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#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
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#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
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#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
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#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
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#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
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#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
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#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
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#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
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#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
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#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
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#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
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#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
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#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
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#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
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#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
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#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
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#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
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#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
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#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
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#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
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#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
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#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
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#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
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#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
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#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
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#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
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#define HAL_SYSCFG_Lock HAL_SBS_Lock
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#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
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#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
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#endif /* __ARM_FEATURE_CMSE */
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#endif /* STM32H5 */
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/**
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* @}
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*/
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@ -649,14 +768,16 @@ extern "C" {
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#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
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#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
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#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
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#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
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#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
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STM32H757xx */
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#endif /* STM32H7 */
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#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
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#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
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#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
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#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
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#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
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defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
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@ -678,8 +799,10 @@ extern "C" {
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#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
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#if defined(STM32U5)
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#if defined(STM32U5) || defined(STM32H5)
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#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
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#endif /* STM32U5 || STM32H5 */
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#if defined(STM32U5)
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#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
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#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
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#endif /* STM32U5 */
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@ -694,7 +817,23 @@ extern "C" {
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#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
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#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
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#endif /* STM32U5 */
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#if defined(STM32H5)
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#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
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#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
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#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
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#endif /* STM32H5 */
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#if defined(STM32H5) || defined(STM32U5)
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#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
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#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
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#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
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#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
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#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
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#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
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#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
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#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
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#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
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#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
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#endif /* STM32H5 || STM32U5 */
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/**
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* @}
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*/
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@ -875,7 +1014,8 @@ extern "C" {
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#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
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#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
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#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
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#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
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#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
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defined(STM32L1) || defined(STM32F7)
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#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
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#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
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#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
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@ -1109,6 +1249,26 @@ extern "C" {
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#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
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#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
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#if defined(STM32H5) || defined(STM32H7RS)
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#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
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#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
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#endif /* STM32H5 || STM32H7RS */
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#if defined(STM32WBA)
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#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
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#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
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#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
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#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
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#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
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#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
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#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
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#endif /* STM32WBA */
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#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
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#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
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#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
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#endif /* STM32H5 || STM32WBA || STM32H7RS */
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#if defined(STM32F7)
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#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
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#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
|
||||
@ -1119,12 +1279,12 @@ extern "C" {
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32F7) || defined(STM32H7)
|
||||
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
|
||||
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
|
||||
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
|
||||
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
|
||||
#endif /* STM32F7 || STM32H7 */
|
||||
#endif /* STM32F7 || STM32H7 || STM32L0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -1291,7 +1451,7 @@ extern "C" {
|
||||
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
|
||||
#endif
|
||||
|
||||
#if defined(STM32U5) || defined(STM32MP2)
|
||||
#if defined(STM32U5)
|
||||
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
|
||||
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
|
||||
#endif
|
||||
@ -1404,30 +1564,40 @@ extern "C" {
|
||||
#define ETH_MMCRFAECR 0x00000198U
|
||||
#define ETH_MMCRGUFCR 0x000001C4U
|
||||
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
|
||||
the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
|
||||
MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
|
||||
or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
|
||||
of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
|
||||
transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
|
||||
frame for transmission */
|
||||
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
|
||||
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
|
||||
de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
|
||||
activate threshold */
|
||||
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
|
||||
#if defined(STM32F1)
|
||||
#else
|
||||
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
|
||||
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
|
||||
(or time-stamp) */
|
||||
#endif
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
|
||||
status */
|
||||
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
|
||||
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
|
||||
@ -1435,6 +1605,8 @@ extern "C" {
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1598,7 +1770,8 @@ extern "C" {
|
||||
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
|
||||
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
|
||||
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
|
||||
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
|
||||
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
|
||||
#if defined(STM32L0)
|
||||
@ -1607,8 +1780,10 @@ extern "C" {
|
||||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
|
||||
HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
|
||||
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||
@ -1642,16 +1817,21 @@ extern "C" {
|
||||
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
|
||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
|
||||
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
|
||||
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
|
||||
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
|
||||
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
|
||||
STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
|
||||
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
@ -1776,6 +1956,17 @@ extern "C" {
|
||||
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
|
||||
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
|
||||
|
||||
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
|
||||
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
|
||||
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
|
||||
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
|
||||
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
|
||||
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
|
||||
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
|
||||
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
|
||||
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
|
||||
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
|
||||
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
|
||||
@ -1784,6 +1975,8 @@ extern "C" {
|
||||
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
|
||||
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
|
||||
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
|
||||
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
|
||||
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
|
||||
@ -1794,6 +1987,7 @@ extern "C" {
|
||||
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
|
||||
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
|
||||
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
|
||||
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
|
||||
|
||||
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
|
||||
#endif
|
||||
@ -1802,6 +1996,20 @@ extern "C" {
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
|
||||
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
|
||||
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
|
||||
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
@ -1827,7 +2035,8 @@ extern "C" {
|
||||
#define HAL_TIM_DMAError TIM_DMAError
|
||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
|
||||
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||
@ -2084,7 +2293,8 @@ extern "C" {
|
||||
#define COMP_STOP __HAL_COMP_DISABLE
|
||||
#define COMP_LOCK __HAL_COMP_LOCK
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
|
||||
defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
|
||||
@ -2109,8 +2319,8 @@ extern "C" {
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#endif
|
||||
#if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
@ -2143,8 +2353,8 @@ extern "C" {
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#endif
|
||||
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
|
||||
@ -2201,8 +2411,8 @@ extern "C" {
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#endif
|
||||
#if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
@ -2219,7 +2429,7 @@ extern "C" {
|
||||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
#endif
|
||||
#else
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
@ -2256,8 +2466,10 @@ extern "C" {
|
||||
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -2416,7 +2628,9 @@ extern "C" {
|
||||
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
|
||||
@ -2425,8 +2639,12 @@ extern "C" {
|
||||
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
|
||||
HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
|
||||
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
|
||||
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
|
||||
@ -2462,8 +2680,8 @@ extern "C" {
|
||||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
|
||||
HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
@ -3436,7 +3654,12 @@ extern "C" {
|
||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
|
||||
#if defined(STM32U0)
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
|
||||
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
@ -3538,8 +3761,10 @@ extern "C" {
|
||||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#if !defined(STM32U0)
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
#endif
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
@ -3581,6 +3806,92 @@ extern "C" {
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
|
||||
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
|
||||
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
|
||||
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
|
||||
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
|
||||
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
|
||||
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
|
||||
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
|
||||
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
|
||||
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
|
||||
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
|
||||
|
||||
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
|
||||
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
|
||||
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
|
||||
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
|
||||
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
|
||||
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
|
||||
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
|
||||
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
|
||||
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
|
||||
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
|
||||
|
||||
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
|
||||
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
|
||||
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
|
||||
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
|
||||
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
|
||||
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
|
||||
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
|
||||
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
|
||||
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
|
||||
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
|
||||
|
||||
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
|
||||
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
|
||||
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
|
||||
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
|
||||
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
|
||||
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
|
||||
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
|
||||
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
|
||||
|
||||
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
|
||||
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
|
||||
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
|
||||
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
|
||||
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
|
||||
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
|
||||
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
|
||||
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
|
||||
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -3597,9 +3908,9 @@ extern "C" {
|
||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
|
||||
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32C0)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
|
||||
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
@ -3634,6 +3945,13 @@ extern "C" {
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
|
||||
defined (STM32H7) || \
|
||||
defined (STM32L0) || defined (STM32L1) || \
|
||||
defined (STM32WB)
|
||||
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
|
||||
#endif
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
|
||||
#define IS_TAMPER IS_RTC_TAMPER
|
||||
@ -3652,6 +3970,11 @@ extern "C" {
|
||||
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
|
||||
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
|
||||
|
||||
#if defined (STM32H5)
|
||||
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
|
||||
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -3910,6 +4233,9 @@ extern "C" {
|
||||
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
|
||||
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -137,7 +137,7 @@ typedef struct
|
||||
FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
|
||||
This parameter is applied only for 16-bit or 8-bit resolution.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
@ -918,12 +918,20 @@ typedef struct
|
||||
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
|
||||
|
||||
/**
|
||||
* @brief Calibration factor size verification (7 bits maximum).
|
||||
* @brief Calibration factor size verification (11 bits maximum).
|
||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
||||
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
|
||||
*/
|
||||
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
|
||||
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FFU))
|
||||
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
/**
|
||||
* @brief Calibration factor size verification (7 bits maximum on ADC3).
|
||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
||||
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
|
||||
*/
|
||||
#define IS_ADC_CALFACT_ADC3(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting.
|
||||
|
||||
@ -49,6 +49,7 @@
|
||||
#define HAL_DTS_MODULE_ENABLED
|
||||
#define HAL_DSI_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_FDCAN_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
@ -165,8 +166,9 @@
|
||||
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY (0x0FUL) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
|
||||
#define USE_SPI_CRC 1U /*!< use CRC in SPI */
|
||||
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
|
||||
#define USE_SPI_CRC 1U /*!< use CRC in SPI */
|
||||
#define USE_FLASH_ECC 0U /*!< use ECC error management in FLASH */
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
@ -285,6 +287,10 @@
|
||||
#include "stm32h7xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_eth_legacy.h"
|
||||
#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
@ -307,6 +307,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
|
||||
@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -78,19 +78,19 @@ typedef struct
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
} DAC_HandleTypeDef;
|
||||
@ -127,7 +127,7 @@ typedef struct
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
|
||||
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
|
||||
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
|
||||
|
||||
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
|
||||
@ -209,19 +209,19 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
||||
#if defined(HRTIM1)
|
||||
#define DAC_TRIGGER_HR1_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_HR1_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
|
||||
#endif
|
||||
#endif /* HRTIM12 */
|
||||
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#if defined(TIM23)
|
||||
#define DAC_TRIGGER_T23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */
|
||||
#endif
|
||||
#endif /* TIM23 */
|
||||
#if defined(TIM24)
|
||||
#define DAC_TRIGGER_T24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */
|
||||
#endif
|
||||
#endif /* TIM24 */
|
||||
#if defined(DAC2)
|
||||
#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
|
||||
#endif
|
||||
#endif /* DAC2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -478,7 +478,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
@ -504,8 +504,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
|
||||
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -514,8 +515,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -551,4 +552,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
|
||||
|
||||
#endif /* STM32H7xx_HAL_DAC_H */
|
||||
|
||||
|
||||
@ -81,6 +81,7 @@ extern "C" {
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -140,7 +141,7 @@ extern "C" {
|
||||
((TRIGGER) == DAC_TRIGGER_T23_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T24_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
|
||||
|
||||
@ -205,11 +206,11 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
|
||||
const uint32_t *pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
@ -229,7 +230,7 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
|
||||
uint32_t NewTrimmingValue);
|
||||
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -268,4 +269,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_DAC_EX_H */
|
||||
|
||||
|
||||
@ -66,7 +66,9 @@ typedef enum
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#define UNUSED(x) ((void)(x))
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(x) ((void)(x)) /* To avoid gcc/g++ warnings */
|
||||
#endif /* UNUSED */
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
|
||||
@ -976,7 +976,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
||||
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
/* Delay after an DSI warpper enabling */ \
|
||||
/* Delay after an DSI wrapper enabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
@ -989,7 +989,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
||||
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
/* Delay after an DSI warpper disabling*/ \
|
||||
/* Delay after an DSI wrapper disabling*/ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
@ -1184,7 +1184,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
|
||||
uint32_t Mode,
|
||||
uint32_t NbParams,
|
||||
uint32_t Param1,
|
||||
uint8_t *ParametersTable);
|
||||
const uint8_t *ParametersTable);
|
||||
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
|
||||
uint32_t ChannelNbr,
|
||||
uint8_t *Array,
|
||||
@ -1222,8 +1222,8 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
|
||||
* @brief Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
|
||||
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
||||
uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi);
|
||||
HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -1271,10 +1271,10 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
||||
|| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
|
||||
#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
|
||||
|| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
|
||||
#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\
|
||||
|| ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\
|
||||
|| ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\
|
||||
|| ((Vsync) == DSI_VSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\
|
||||
|| ((Hsync) == DSI_HSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
|
||||
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
|
||||
((VideoModeType) == DSI_VID_MODE_BURST))
|
||||
|
||||
@ -24,7 +24,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
@ -160,7 +159,7 @@ typedef struct
|
||||
|
||||
void *pData; /*!< Specifies Application packet pointer to save */
|
||||
|
||||
} ETH_TxPacketConfig;
|
||||
} ETH_TxPacketConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
@ -359,7 +358,6 @@ typedef struct
|
||||
|
||||
uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
|
||||
This parameter can be a value of @ref ETH_Burst_Mode */
|
||||
|
||||
FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats
|
||||
of any initiated burst transfer with INCRx and SINGLE transfers. */
|
||||
|
||||
@ -385,6 +383,7 @@ typedef struct
|
||||
uint32_t
|
||||
MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet
|
||||
This parameter can be a value from 0x40 to 0x3FFF */
|
||||
|
||||
} ETH_DMAConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
@ -421,7 +420,6 @@ typedef enum
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint8_t
|
||||
*MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
|
||||
|
||||
@ -540,7 +538,7 @@ typedef struct
|
||||
|
||||
__IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
|
||||
and also related to Tx operations. This parameter can
|
||||
be a value of @ref HAL_ETH_StateTypeDef */
|
||||
be a value of @ref ETH_State_Codes */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
|
||||
This parameter can be a value of @ref ETH_Error_Code.*/
|
||||
@ -598,7 +596,6 @@ typedef enum
|
||||
{
|
||||
HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
|
||||
HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
|
||||
|
||||
HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
|
||||
HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
|
||||
HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */
|
||||
@ -606,7 +603,6 @@ typedef enum
|
||||
HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */
|
||||
HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */
|
||||
|
||||
|
||||
} HAL_ETH_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
@ -738,11 +734,11 @@ typedef struct
|
||||
#define ETH_DMATXNDESCRF_CIC_DISABLE 0x00000000U /*!< Do Nothing: Checksum Engine is disabled */
|
||||
#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 0x00010000U /*!< Only IP header checksum calculation and insertion are enabled. */
|
||||
#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 0x00020000U /*!< IP header checksum and payload checksum calculation and insertion are
|
||||
enabled, but pseudo header
|
||||
enabled, but pseudo header
|
||||
checksum is not
|
||||
calculated in hardware */
|
||||
#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 0x00030000U /*!< IP Header checksum and payload checksum calculation and insertion are
|
||||
enabled, and pseudo header
|
||||
enabled, and pseudo header
|
||||
checksum is
|
||||
calculated in hardware. */
|
||||
#define ETH_DMATXNDESCRF_TPL 0x0003FFFFU /*!< TCP Payload Length */
|
||||
@ -795,7 +791,6 @@ typedef struct
|
||||
#define ETH_DMATXNDESCWBF_DB 0x00000002U /*!< Deferred Bit */
|
||||
#define ETH_DMATXNDESCWBF_IHE 0x00000004U /*!< IP Header Error */
|
||||
|
||||
|
||||
/*
|
||||
DMA Tx Context Descriptor
|
||||
-----------------------------------------------------------------------------------------------
|
||||
@ -846,7 +841,6 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
|
||||
* @{
|
||||
*/
|
||||
@ -945,7 +939,6 @@ typedef struct
|
||||
#define ETH_DMARXNDESCWBF_VF 0x00008000U /*!< VLAN Filter Status */
|
||||
#define ETH_DMARXNDESCWBF_ARPNR 0x00000400U /*!< ARP Reply Not Generated */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Bit definition of Rx normal descriptor register 3 write back format
|
||||
*/
|
||||
@ -1475,7 +1468,7 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_ETH_StateTypeDef ETH States
|
||||
/** @defgroup ETH_State_Codes ETH States
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */
|
||||
@ -1490,11 +1483,12 @@ typedef struct
|
||||
/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */
|
||||
#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */
|
||||
#define HAL_ETH_PTP_NOT_CONFIGURED 0x00000000U /*!< ETH PTP Configuration not done */
|
||||
#define HAL_ETH_PTP_CONFIGURED 0x00000001U /*!< ETH PTP Configuration done */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1587,6 +1581,7 @@ typedef struct
|
||||
* enabled @ref ETH_MAC_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
@ -1604,8 +1599,8 @@ typedef struct
|
||||
* @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
|
||||
* @retval The state of ETH MAC IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
|
||||
#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &\
|
||||
( __INTERRUPT__)) == ( __INTERRUPT__))
|
||||
|
||||
/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
|
||||
#define ETH_WAKEUP_EXTI_LINE 0x00400000U /* !< 86 - 64 = 22 */
|
||||
@ -1694,11 +1689,10 @@ typedef struct
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
|
||||
|
||||
#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1747,7 +1741,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
|
||||
HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
|
||||
HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
|
||||
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
|
||||
HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
|
||||
HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
|
||||
@ -1766,10 +1760,10 @@ HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_tx
|
||||
HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
|
||||
#endif /* HAL_ETH_USE_PTP */
|
||||
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
|
||||
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
|
||||
uint32_t RegValue);
|
||||
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
|
||||
uint32_t *pRegValue);
|
||||
@ -1794,8 +1788,8 @@ void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *ti
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/* MAC & DMA Configuration APIs **********************************************/
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
|
||||
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
|
||||
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
|
||||
HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
|
||||
HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
|
||||
void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
|
||||
@ -1805,13 +1799,15 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t
|
||||
uint32_t VLANIdentifier);
|
||||
|
||||
/* MAC L2 Packet Filtering APIs **********************************************/
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
|
||||
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
|
||||
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
|
||||
const uint8_t *pMACAddr);
|
||||
|
||||
/* MAC Power Down APIs *****************************************************/
|
||||
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
|
||||
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
|
||||
const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
|
||||
void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
|
||||
|
||||
@ -1823,11 +1819,11 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
|
||||
HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1851,5 +1847,3 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_ETH_H */
|
||||
|
||||
|
||||
|
||||
@ -314,32 +314,32 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t
|
||||
/* MAC L3 L4 Filtering APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
const ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
const ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
|
||||
/* MAC VLAN Processing APIs ************************************************/
|
||||
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
const ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
|
||||
|
||||
/* Energy Efficient Ethernet APIs *********************************************/
|
||||
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
|
||||
FunctionalState TxClockStop);
|
||||
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -364,5 +364,3 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_ETH_EX_H */
|
||||
|
||||
|
||||
|
||||
@ -391,52 +391,55 @@ typedef struct
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
|
||||
uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
|
||||
frame with its BRS flag set.
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
|
||||
of a CAN FD format frame with its BRS flag set.
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
|
||||
uint32_t Activity; /*!< Specifies the FDCAN module communication state.
|
||||
This parameter can be a value of @ref FDCAN_communication_state */
|
||||
This parameter can be a value of @ref FDCAN_communication_state */
|
||||
|
||||
uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
|
||||
This parameter can be:
|
||||
- 0 : The FDCAN is in Error_Active state
|
||||
- 1 : The FDCAN is in Error_Passive state */
|
||||
- 1 : The FDCAN is in Error_Passive state */
|
||||
|
||||
uint32_t Warning; /*!< Specifies the FDCAN module warning status.
|
||||
This parameter can be:
|
||||
- 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
|
||||
- 1 : at least one of error counters has reached the Error_Warning limit of 96 */
|
||||
- 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
|
||||
Error_Warning limit of 96
|
||||
- 1 : at least one of error counters has reached the Error_Warning
|
||||
limit of 96 */
|
||||
|
||||
uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
|
||||
This parameter can be:
|
||||
- 0 : The FDCAN is not in Bus_Off state
|
||||
- 1 : The FDCAN is in Bus_Off state */
|
||||
- 1 : The FDCAN is in Bus_Off state */
|
||||
|
||||
uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
|
||||
This parameter can be:
|
||||
- 0 : Last received CAN FD message did not have its ESI flag set
|
||||
- 1 : Last received CAN FD message had its ESI flag set */
|
||||
- 1 : Last received CAN FD message had its ESI flag set */
|
||||
|
||||
uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
|
||||
This parameter can be:
|
||||
- 0 : Last received CAN FD message did not have its BRS flag set
|
||||
- 1 : Last received CAN FD message had its BRS flag set */
|
||||
- 1 : Last received CAN FD message had its BRS flag set */
|
||||
|
||||
uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
|
||||
uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received
|
||||
since last protocol status.
|
||||
This parameter can be:
|
||||
- 0 : no CAN FD message received
|
||||
- 1 : CAN FD message received */
|
||||
- 0 : No CAN FD message received
|
||||
- 1 : CAN FD message received */
|
||||
|
||||
uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
|
||||
This parameter can be:
|
||||
- 0 : No protocol exception event occurred since last read access
|
||||
- 1 : Protocol exception event occurred */
|
||||
- 1 : Protocol exception event occurred */
|
||||
|
||||
uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
|
||||
This parameter can be a number between 0 and 127 */
|
||||
This parameter can be a number between 0 and 127 */
|
||||
|
||||
} FDCAN_ProtocolStatusTypeDef;
|
||||
|
||||
@ -446,21 +449,24 @@ typedef struct
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
|
||||
This parameter can be a number between 0 and 127 */
|
||||
This parameter can be a number between 0 and 127 */
|
||||
|
||||
uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
|
||||
This parameter can be:
|
||||
- 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
|
||||
- 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
|
||||
- 0 : The Receive Error Counter (RxErrorCnt) is below the error
|
||||
passive level of 128
|
||||
- 1 : The Receive Error Counter (RxErrorCnt) has reached the error
|
||||
passive level of 128 */
|
||||
|
||||
uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
|
||||
This parameter can be a number between 0 and 255.
|
||||
This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
|
||||
or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
|
||||
TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
|
||||
This counter is incremented each time when a FDCAN protocol error causes
|
||||
the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
|
||||
the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
|
||||
FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
|
||||
|
||||
} FDCAN_ErrorCountersTypeDef;
|
||||
|
||||
@ -759,15 +765,15 @@ typedef struct
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
|
||||
HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
|
||||
HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */
|
||||
HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */
|
||||
HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */
|
||||
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */
|
||||
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
|
||||
HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
|
||||
HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */
|
||||
HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */
|
||||
HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */
|
||||
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */
|
||||
|
||||
HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */
|
||||
HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */
|
||||
HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */
|
||||
HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */
|
||||
|
||||
} HAL_FDCAN_CallbackIDTypeDef;
|
||||
|
||||
@ -868,21 +874,21 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
|
||||
#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */
|
||||
#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */
|
||||
#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */
|
||||
#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */
|
||||
#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
|
||||
#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
|
||||
#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
|
||||
#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
|
||||
#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
|
||||
#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
|
||||
#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
|
||||
#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
|
||||
#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
|
||||
#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
|
||||
#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
|
||||
#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */
|
||||
#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */
|
||||
#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */
|
||||
#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */
|
||||
#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
|
||||
#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
|
||||
#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
|
||||
#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
|
||||
#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
|
||||
#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
|
||||
#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
|
||||
#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
|
||||
#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
|
||||
#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
|
||||
#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -962,21 +968,21 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1215,7 +1221,7 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
|
||||
#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
|
||||
#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1660,9 +1666,9 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
||||
/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
|
||||
#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
|
||||
#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
|
||||
#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
|
||||
#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
|
||||
#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1780,10 +1786,10 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
|
||||
@ -1823,7 +1829,9 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
||||
* This parameter can be one of @arg FDCAN_Interrupts
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
|
||||
#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
|
||||
((__HANDLE__)->Instance->IR &\
|
||||
(__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FDCAN interrupts.
|
||||
@ -1832,11 +1840,11 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
||||
* This parameter can be any combination of @arg FDCAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
|
||||
do{ \
|
||||
#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
|
||||
do { \
|
||||
((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
|
||||
FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
|
||||
}while(0)
|
||||
} while(0);
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FDCAN flag is set or not.
|
||||
@ -1845,7 +1853,9 @@ do{ \
|
||||
* This parameter can be one of @arg FDCAN_flags
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
|
||||
#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? \
|
||||
((__HANDLE__)->Instance->IR &\
|
||||
(__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FDCAN flags.
|
||||
@ -1854,11 +1864,11 @@ do{ \
|
||||
* This parameter can be any combination of @arg FDCAN_flags
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
do{ \
|
||||
#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
do { \
|
||||
((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
|
||||
FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \
|
||||
}while(0)
|
||||
} while(0);
|
||||
|
||||
/** @brief Check if the specified FDCAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
@ -1866,7 +1876,10 @@ do{ \
|
||||
* This parameter can be a value of @arg FDCAN_Interrupts
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
|
||||
#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
|
||||
((__HANDLE__)->Instance->IE &\
|
||||
(__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & \
|
||||
(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FDCAN TT interrupts.
|
||||
@ -1952,29 +1965,41 @@ HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
|
||||
pFDCAN_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxEventFifoCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_RxFifo0CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_RxFifo1CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_ErrorStatusCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
|
||||
/**
|
||||
@ -1985,12 +2010,15 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
|
||||
uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
|
||||
const FDCAN_ClkCalUnitTypeDef *sCcuConfig);
|
||||
uint32_t HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
|
||||
uint32_t HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
|
||||
uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
|
||||
uint32_t RejectRemoteExt);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
|
||||
@ -1998,14 +2026,16 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint3
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
|
||||
uint32_t TimeoutPeriod);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
|
||||
uint32_t TdcFilter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
@ -2022,21 +2052,27 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
|
||||
/* Control functions **********************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
const uint8_t *pTxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
const uint8_t *pTxData, uint32_t BufferIndex);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
|
||||
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
|
||||
FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_ErrorCountersTypeDef *ErrorCounters);
|
||||
uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
|
||||
uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
|
||||
uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
|
||||
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
|
||||
uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
|
||||
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
/**
|
||||
* @}
|
||||
@ -2046,13 +2082,16 @@ HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfd
|
||||
* @{
|
||||
*/
|
||||
/* TT Configuration and control functions**************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier,
|
||||
uint32_t Payload);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource,
|
||||
uint32_t TimeMarkValue, uint32_t RepeatFactor,
|
||||
uint32_t StartCycle);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
|
||||
@ -2066,7 +2105,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_TTOperationStatusTypeDef *TTOpStatus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -2076,8 +2116,10 @@ HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, F
|
||||
*/
|
||||
/* Interrupts management ******************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList,
|
||||
uint32_t InterruptLine);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
|
||||
uint32_t BufferIndexes);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
|
||||
@ -2115,8 +2157,8 @@ void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlo
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -2192,8 +2234,8 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
|
||||
#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
|
||||
#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
|
||||
#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
|
||||
#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
|
||||
#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
|
||||
#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
|
||||
#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
|
||||
#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
|
||||
((SIZE) == FDCAN_DATA_BYTES_12) || \
|
||||
((SIZE) == FDCAN_DATA_BYTES_16) || \
|
||||
|
||||
@ -176,6 +176,20 @@ typedef struct
|
||||
|
||||
} FLASH_CRCInitTypeDef;
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/**
|
||||
* @brief ECC Info Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Area; /*!< Area from which an ECC was detected.
|
||||
This parameter can be a value of @ref FLASHEx_ECC_Area */
|
||||
|
||||
uint32_t Address; /*!< ECC error address */
|
||||
|
||||
} FLASH_EccInfoTypeDef;
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -216,6 +230,18 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/** @defgroup FLASH_ECC_Area FLASH ECC Area
|
||||
* @brief FLASH ECC Area
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */
|
||||
#define FLASH_ECC_AREA_USER_BANK2 0x00000001U /*!< FLASH bank 2 area */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/** @defgroup FLASHEx_Option_Type FLASH Option Type
|
||||
* @{
|
||||
*/
|
||||
@ -837,6 +863,38 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void);
|
||||
#if defined (DUAL_BANK)
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void);
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt(void);
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void);
|
||||
#if defined (DUAL_BANK)
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void);
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
|
||||
void HAL_FLASHEx_BusFault_IRQHandler(void);
|
||||
|
||||
__weak void HAL_FLASHEx_EccDetectionCallback(void);
|
||||
__weak void HAL_FLASHEx_EccCorrectionCallback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -479,6 +479,22 @@ typedef struct
|
||||
#define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMAC_PARAM_P_MAX_IIR 64U /*!< Maximum value of P parameter with IIR */
|
||||
#define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */
|
||||
#define FMAC_PARAM_P_MIN 2U /*!< Minimum value of P parameter */
|
||||
#define FMAC_PARAM_Q_MAX 63U /*!< Maximum value of Q parameter */
|
||||
#define FMAC_PARAM_Q_MIN 1U /*!< Minimum value of Q parameter */
|
||||
#define FMAC_PARAM_R_MAX 7U /*!< Maximum value of R parameter */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -549,10 +565,12 @@ typedef struct
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
|
||||
(((__P__) >= 2U) && ((__P__) <= 127U))) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__P__) >= 2U) && ((__P__) <= 64U))) )
|
||||
#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
|
||||
(((__P__) >= FMAC_PARAM_P_MIN) && \
|
||||
((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__P__) >= FMAC_PARAM_P_MIN) && \
|
||||
((__P__) <= FMAC_PARAM_P_MAX_IIR))))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter Q.
|
||||
@ -562,7 +580,7 @@ typedef struct
|
||||
*/
|
||||
#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__Q__) >= 1U) && ((__Q__) <= 63U))) )
|
||||
(((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter R.
|
||||
@ -572,7 +590,7 @@ typedef struct
|
||||
*/
|
||||
#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
|
||||
((__R__) <= 7U))
|
||||
((__R__) <= FMAC_PARAM_R_MAX))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC buffer access.
|
||||
@ -682,8 +700,8 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac);
|
||||
uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
|
||||
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac);
|
||||
uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -54,7 +54,12 @@ extern "C" {
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
|
||||
#if defined(PWR_CPUCR_RETDS_CD) /* CPU domain power down Deepsleep */
|
||||
#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
|
||||
#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
|
||||
#define GPIO_AF0_NDSTOP2 ((uint8_t)0x00) /* NDSTOP2 Alternate Function mapping */
|
||||
#endif /* PWR_CPUCR_RETDS_CD */
|
||||
#if defined(PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
|
||||
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
|
||||
@ -171,6 +171,9 @@ typedef struct
|
||||
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT)
|
||||
#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT)
|
||||
#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -252,6 +255,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n
|
||||
uint8_t token, uint8_t *pbuff,
|
||||
uint16_t length, uint8_t do_ping);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t addr, uint8_t PortNbr);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
@ -280,10 +288,10 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
|
||||
@ -118,8 +118,6 @@ typedef enum
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
@ -709,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -804,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
||||
(~I2C_CR2_RD_WRN)))
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
|
||||
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
@ -289,7 +289,7 @@ typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8
|
||||
* @brief JPEG Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */
|
||||
#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */
|
||||
#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */
|
||||
@ -357,7 +357,7 @@ typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8
|
||||
* @param __HANDLE__ specifies the JPEG handle.
|
||||
* @param __FLAG__ specifies the flag to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag
|
||||
* @arg JPEG_FLAG_IFTF : The input FIFO is not full and is below its threshold flag
|
||||
* @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
|
||||
* @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
|
||||
* @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
|
||||
|
||||
@ -436,6 +436,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
||||
* @brief Write the passed parameter in the Autoreload register.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Autoreload value
|
||||
* This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
|
||||
* @retval None
|
||||
* @note The ARR register can only be modified when the LPTIM instance is enabled.
|
||||
*/
|
||||
@ -657,7 +658,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -750,9 +751,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
|
||||
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
|
||||
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\
|
||||
((__AUTORELOAD__) <= 0x0000FFFFUL))
|
||||
|
||||
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
|
||||
|
||||
@ -338,14 +338,14 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer
|
||||
/** @defgroup LTDC_Pixelformat LTDC Pixel format
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -104,9 +104,8 @@ typedef struct
|
||||
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
|
||||
parameter is mandatory for some NAND parts after the read
|
||||
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
|
||||
Example: Toshiba THTH58BYG3S0HBAI6.
|
||||
This parameter could be ENABLE or DISABLE
|
||||
Please check the Read Mode sequnece in the NAND device datasheet */
|
||||
Please check the Read Mode sequence in the NAND device datasheet */
|
||||
} NAND_DeviceConfigTypeDef;
|
||||
|
||||
/**
|
||||
@ -126,7 +125,7 @@ typedef struct
|
||||
|
||||
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
|
||||
|
||||
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
|
||||
NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
|
||||
@ -214,27 +213,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
||||
/* IO operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
|
||||
uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
|
||||
uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
|
||||
uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
|
||||
uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
|
||||
|
||||
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
/* NAND callback registering/unregistering */
|
||||
@ -264,8 +263,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
|
||||
* @{
|
||||
*/
|
||||
/* NAND State functions *******************************************************/
|
||||
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
||||
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
|
||||
*/
|
||||
|
||||
/* NOR State functions ********************************************************/
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
|
||||
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
#define STM32H7xx_HAL_OSPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
@ -90,7 +90,7 @@ typedef struct
|
||||
uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every
|
||||
Refresh+1 clock cycles.
|
||||
This parameter can be a value between 0 and 0xFFFFFFFF */
|
||||
}OSPI_InitTypeDef;
|
||||
} OSPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OSPI Handle Structure definition
|
||||
@ -111,21 +111,21 @@ typedef struct
|
||||
__IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */
|
||||
uint32_t Timeout; /*!< Timeout used for the OSPI external device access */
|
||||
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
|
||||
void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
|
||||
void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi);
|
||||
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
|
||||
}OSPI_HandleTypeDef;
|
||||
} OSPI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OSPI Regular Command Structure definition
|
||||
@ -176,7 +176,7 @@ typedef struct
|
||||
This parameter can be a value of @ref OSPI_DQSMode */
|
||||
uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
|
||||
This parameter can be a value of @ref OSPI_SIOOMode */
|
||||
}OSPI_RegularCmdTypeDef;
|
||||
} OSPI_RegularCmdTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OSPI Hyperbus Configuration Structure definition
|
||||
@ -191,7 +191,7 @@ typedef struct
|
||||
This parameter can be a value of @ref OSPI_WriteZeroLatency */
|
||||
uint32_t LatencyMode; /*!< It configures the latency mode.
|
||||
This parameter can be a value of @ref OSPI_LatencyMode */
|
||||
}OSPI_HyperbusCfgTypeDef;
|
||||
} OSPI_HyperbusCfgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OSPI Hyperbus Command Structure definition
|
||||
@ -210,7 +210,7 @@ typedef struct
|
||||
In case of autopolling mode, this parameter can be any value between 1 and 4 */
|
||||
uint32_t DQSMode; /*!< It enables or not the data strobe management.
|
||||
This parameter can be a value of @ref OSPI_DQSMode */
|
||||
}OSPI_HyperbusCmdTypeDef;
|
||||
} OSPI_HyperbusCmdTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OSPI Auto Polling mode configuration structure definition
|
||||
@ -227,7 +227,7 @@ typedef struct
|
||||
This parameter can be a value of @ref OSPI_AutomaticStop */
|
||||
uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
}OSPI_AutoPollingTypeDef;
|
||||
} OSPI_AutoPollingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OSPI Memory Mapped mode configuration structure definition
|
||||
@ -238,7 +238,7 @@ typedef struct
|
||||
This parameter can be a value of @ref OSPI_TimeOutActivation */
|
||||
uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
}OSPI_MemoryMappedTypeDef;
|
||||
} OSPI_MemoryMappedTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OSPI IO Manager Configuration structure definition
|
||||
@ -258,7 +258,7 @@ typedef struct
|
||||
uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
|
||||
if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
|
||||
This parameter can be a value between 1 and 256 */
|
||||
}OSPIM_CfgTypeDef;
|
||||
} OSPIM_CfgTypeDef;
|
||||
|
||||
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
@ -279,7 +279,7 @@ typedef enum
|
||||
|
||||
HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */
|
||||
HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */
|
||||
}HAL_OSPI_CallbackIDTypeDef;
|
||||
} HAL_OSPI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OSPI Callback pointer definition
|
||||
@ -790,10 +790,10 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
|
||||
/** @addtogroup OSPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -804,7 +804,7 @@ void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi);
|
||||
* @{
|
||||
*/
|
||||
/* OSPI IRQ handler function */
|
||||
void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi);
|
||||
|
||||
/* OSPI command configuration functions */
|
||||
HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
|
||||
@ -825,25 +825,25 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoP
|
||||
HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
|
||||
|
||||
/* OSPI memory-mapped mode functions */
|
||||
HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
|
||||
HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
|
||||
|
||||
/* Callback functions in non-blocking modes ***********************************/
|
||||
void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
|
||||
|
||||
/* OSPI indirect mode functions */
|
||||
void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
|
||||
|
||||
/* OSPI status flag polling mode functions */
|
||||
void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi);
|
||||
|
||||
/* OSPI memory-mapped mode functions */
|
||||
void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi);
|
||||
void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi);
|
||||
|
||||
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
|
||||
/* OSPI callback registering/unregistering */
|
||||
@ -859,13 +859,13 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL
|
||||
/** @addtogroup OSPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold);
|
||||
uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout);
|
||||
uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi);
|
||||
uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold);
|
||||
uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi);
|
||||
HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout);
|
||||
uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi);
|
||||
uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -352,10 +352,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode);
|
||||
HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode);
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -364,7 +364,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
@ -31,6 +31,12 @@ extern "C" {
|
||||
* @{
|
||||
*/
|
||||
#if defined(PSSI)
|
||||
|
||||
#ifndef USE_HAL_PSSI_REGISTER_CALLBACKS
|
||||
/* For backward compatibility, if USE_HAL_PSSI_REGISTER_CALLBACKS not defined, define it to 1*/
|
||||
#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U
|
||||
#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
|
||||
|
||||
/** @addtogroup PSSI PSSI
|
||||
* @brief PSSI HAL module driver
|
||||
* @{
|
||||
@ -47,12 +53,18 @@ extern "C" {
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */
|
||||
uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */
|
||||
uint32_t ControlSignal; /* !< Configures Data enable and Data ready */
|
||||
uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */
|
||||
uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */
|
||||
uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */
|
||||
uint32_t DataWidth; /* !< Configures the data width.
|
||||
This parameter can be a value of @ref PSSI_DATA_WIDTH. */
|
||||
uint32_t BusWidth; /* !< Configures the parallel bus width.
|
||||
This parameter can be a value of @ref PSSI_BUS_WIDTH. */
|
||||
uint32_t ControlSignal; /* !< Configures Data enable and Data ready.
|
||||
This parameter can be a value of @ref ControlSignal_Configuration. */
|
||||
uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity.
|
||||
This parameter can be a value of @ref Clock_Polarity. */
|
||||
uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity.
|
||||
This parameter can be a value of @ref Data_Enable_Polarity. */
|
||||
uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity.
|
||||
This parameter can be a value of @ref Ready_Polarity. */
|
||||
|
||||
} PSSI_InitTypeDef;
|
||||
|
||||
@ -76,16 +88,23 @@ typedef enum
|
||||
/**
|
||||
* @brief PSSI handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __PSSI_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
|
||||
{
|
||||
PSSI_TypeDef *Instance; /*!< PSSI register base address. */
|
||||
PSSI_InitTypeDef Init; /*!< PSSI Initialization Structure. */
|
||||
uint32_t *pBuffPtr; /*!< PSSI Data buffer. */
|
||||
uint32_t XferCount; /*!< PSSI transfer count */
|
||||
uint32_t XferSize; /*!< PSSI transfer size */
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
DMA_HandleTypeDef *hdmatx; /*!< PSSI Tx DMA Handle parameters */
|
||||
DMA_HandleTypeDef *hdmarx; /*!< PSSI Rx DMA Handle parameters */
|
||||
#endif /*HAL_DMA_MODULE_ENABLED*/
|
||||
|
||||
#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
|
||||
void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
|
||||
void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
|
||||
void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
|
||||
@ -93,6 +112,7 @@ typedef struct __PSSI_HandleTypeDef
|
||||
|
||||
void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp Init callback. */
|
||||
void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback. */
|
||||
#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< PSSI lock. */
|
||||
__IO HAL_PSSI_StateTypeDef State; /*!< PSSI transfer state. */
|
||||
@ -100,7 +120,7 @@ typedef struct __PSSI_HandleTypeDef
|
||||
|
||||
} PSSI_HandleTypeDef;
|
||||
|
||||
|
||||
#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL PSSI Callback pointer definition
|
||||
*/
|
||||
@ -120,7 +140,7 @@ typedef enum
|
||||
HAL_PSSI_MSPDEINIT_CB_ID = 0x06U /*!< PSSI Msp DeInit callback ID */
|
||||
|
||||
} HAL_PSSI_CallbackIDTypeDef;
|
||||
|
||||
#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -140,8 +160,9 @@ typedef enum
|
||||
#define HAL_PSSI_ERROR_OVER_RUN 0x00000004U /*!< FIFO Over-run error */
|
||||
#define HAL_PSSI_ERROR_DMA 0x00000008U /*!< Dma error */
|
||||
#define HAL_PSSI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
||||
#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */
|
||||
|
||||
#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -201,7 +222,7 @@ typedef enum
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Reday_Polarity Reday Polarity
|
||||
/** @defgroup Ready_Polarity Ready Polarity
|
||||
* @{
|
||||
*/
|
||||
#define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */
|
||||
@ -215,8 +236,6 @@ typedef enum
|
||||
*/
|
||||
#define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */
|
||||
#define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -238,7 +257,7 @@ typedef enum
|
||||
#define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */
|
||||
#define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */
|
||||
|
||||
#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/
|
||||
#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag */
|
||||
#define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/
|
||||
|
||||
|
||||
@ -272,12 +291,15 @@ typedef enum
|
||||
* @param __HANDLE__ specifies the PSSI handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_PSSI_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
}while(0)
|
||||
#else
|
||||
#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PSSI_STATE_RESET)
|
||||
#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
@ -414,6 +436,7 @@ typedef enum
|
||||
|
||||
#define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \
|
||||
((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH ))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -434,11 +457,11 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);
|
||||
void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi);
|
||||
void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
|
||||
#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
|
||||
pPSSI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
|
||||
|
||||
#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -452,9 +475,11 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
|
||||
#endif /*HAL_DMA_MODULE_ENABLED*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -465,8 +490,8 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ***************************************************/
|
||||
HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);
|
||||
uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
|
||||
HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi);
|
||||
uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -482,7 +507,6 @@ void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);
|
||||
void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
|
||||
void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -617,13 +617,13 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi,
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
|
||||
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -57,13 +57,19 @@ typedef enum
|
||||
/**
|
||||
* @brief RAMECC handle Structure definition
|
||||
*/
|
||||
|
||||
#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __RAMECC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
|
||||
{
|
||||
RAMECC_MonitorTypeDef *Instance; /*!< Register base address */
|
||||
__IO HAL_RAMECC_StateTypeDef State; /*!< RAMECC state */
|
||||
__IO uint32_t ErrorCode; /*!< RAMECC Error Code */
|
||||
void (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc); /*!< RAMECC error detect callback */
|
||||
RAMECC_MonitorTypeDef *Instance; /*!< Register base address */
|
||||
__IO HAL_RAMECC_StateTypeDef State; /*!< RAMECC state */
|
||||
__IO uint32_t ErrorCode; /*!< RAMECC Error Code */
|
||||
__IO uint32_t RAMECCErrorCode; /*!< RAMECC Detected Error Code */
|
||||
#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
|
||||
void (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc); /*!< RAMECC Error Detect callback */
|
||||
#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
|
||||
}RAMECC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
@ -81,7 +87,20 @@ typedef struct __RAMECC_HandleTypeDef
|
||||
#define HAL_RAMECC_ERROR_NONE 0x00000000U /*!< RAMECC No Error */
|
||||
#define HAL_RAMECC_ERROR_TIMEOUT 0x00000001U /*!< RAMECC Timeout Error */
|
||||
#define HAL_RAMECC_ERROR_BUSY 0x00000002U /*!< RAMECC Busy Error */
|
||||
#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_RAMECC_ERROR_INVALID_CALLBACK 0x00000003U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RAMECC_Error_Codes RAMECC Error Detected Codes
|
||||
* @{
|
||||
*/
|
||||
#define HAL_RAMECC_NO_ERROR 0x00000000U /*!< RAMECC No Error Detected */
|
||||
#define HAL_RAMECC_SINGLEERROR_DETECTED 0x00000001U /*!< RAMECC Single Error Detected */
|
||||
#define HAL_RAMECC_DOUBLEERROR_DETECTED 0x00000002U /*!< RAMECC Double Error Detected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -135,15 +154,15 @@ typedef struct __RAMECC_HandleTypeDef
|
||||
* @param __HANDLE__ : RAMECC handle.
|
||||
* @param __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_ENABLE : Global interrupt enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RAMECC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( \
|
||||
@ -159,15 +178,15 @@ typedef struct __RAMECC_HandleTypeDef
|
||||
* @param __HANDLE__ : RAMECC handle.
|
||||
* @param __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_ENABLE : Global interrupt enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RAMECC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ( \
|
||||
@ -183,15 +202,15 @@ typedef struct __RAMECC_HandleTypeDef
|
||||
* @param __HANDLE__ : Specifies the RAMECC Handle.
|
||||
* @param __INTERRUPT__ : Specifies the RAMECC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_ENABLE : Global interrupt enable mask.
|
||||
* @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
|
||||
* @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt enable.
|
||||
* @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ( \
|
||||
@ -204,10 +223,10 @@ typedef struct __RAMECC_HandleTypeDef
|
||||
* @param __HANDLE__ : RAMECC handle.
|
||||
* @param __FLAG__ : specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RAMECC_FLAG_SEDCF : RAMECC instance ECC single error detected and corrected flag.
|
||||
* @arg RAMECC_FLAG_DEDF : RAMECC instance ECC double error detected flag.
|
||||
* @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
|
||||
* @arg RAMECC_FLAGS_ALL : RAMECC instance all flag.
|
||||
* @arg RAMECC_FLAG_SINGLEERR_R : RAMECC instance ECC single error detected and corrected flag.
|
||||
* @arg RAMECC_FLAG_DOUBLEERR_R : RAMECC instance ECC double error detected flag.
|
||||
* @arg RAMECC_FLAG_DOUBLEERR_W : RAMECC instance ECC double error on byte write (BW) detected flag.
|
||||
* @arg RAMECC_FLAGS_ALL : RAMECC instance all flag.
|
||||
* @retval The state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (__FLAG__))
|
||||
@ -218,10 +237,10 @@ typedef struct __RAMECC_HandleTypeDef
|
||||
* @param __HANDLE__ : RAMECC handle.
|
||||
* @param __FLAG__ : specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RAMECC_FLAG_SEDCF : RAMECC instance ECC single error detected and corrected flag.
|
||||
* @arg RAMECC_FLAG_DEDF : RAMECC instance ECC double error detected flag.
|
||||
* @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
|
||||
* @arg RAMECC_FLAGS_ALL : RAMECC instance all flag.
|
||||
* @arg RAMECC_FLAG_SINGLEERR_R : RAMECC instance ECC single error detected and corrected flag.
|
||||
* @arg RAMECC_FLAG_DOUBLEERR_R : RAMECC instance ECC double error detected flag.
|
||||
* @arg RAMECC_FLAG_DOUBLEERR_W : RAMECC instance ECC double error on byte write (BW) detected flag.
|
||||
* @arg RAMECC_FLAGS_ALL : RAMECC instance all flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
|
||||
@ -247,8 +266,8 @@ typedef struct __RAMECC_HandleTypeDef
|
||||
* @brief Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -257,37 +276,50 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc);
|
||||
* @brief monitoring operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
|
||||
HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
|
||||
void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
|
||||
HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
|
||||
HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions
|
||||
/** @defgroup RAMECC_Exported_Functions_Group3 handle Interrupt and Callbacks Functions
|
||||
* @brief handle Interrupt and Callbacks Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc);
|
||||
void HAL_RAMECC_DetectErrorCallback(RAMECC_HandleTypeDef *hramecc);
|
||||
#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_RAMECC_RegisterCallback(RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
|
||||
HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc);
|
||||
#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RAMECC_Exported_Functions_Group4 Error information functions
|
||||
* @brief Error information functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RAMECC_Exported_Functions_Group4 State and Error Functions
|
||||
/** @defgroup RAMECC_Exported_Functions_Group5 State and Error Functions
|
||||
* @brief State and Error Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
|
||||
HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc);
|
||||
uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -350,4 +382,3 @@ uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_RAMECC_H */
|
||||
|
||||
|
||||
@ -319,7 +319,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
|
||||
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
@ -332,8 +332,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
|
||||
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -196,14 +196,14 @@ typedef struct
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
|
||||
/** @addtogroup RNG_Ex_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG_Ex_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
|
||||
|
||||
|
||||
@ -935,22 +935,6 @@ typedef struct
|
||||
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
|
||||
#endif /* TAMP */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP1F: Tamper1 interrupt flag
|
||||
* @arg RTC_FLAG_TAMP2F: Tamper2 interrupt flag
|
||||
* @arg RTC_FLAG_TAMP3F: Tamper3 interrupt flag
|
||||
* @retval Flag status
|
||||
*/
|
||||
#if defined(TAMP)
|
||||
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
|
||||
#else
|
||||
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
|
||||
#endif /* TAMP */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
|
||||
@ -100,8 +100,6 @@ typedef struct
|
||||
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
|
||||
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
||||
/**
|
||||
* @}
|
||||
@ -751,8 +749,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -56,7 +56,8 @@ typedef struct
|
||||
uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
|
||||
This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
|
||||
|
||||
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
|
||||
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status
|
||||
from channel A or B.
|
||||
This parameter can be a value of @ref SPDIFRX_Channel_Selection */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
|
||||
@ -65,22 +66,25 @@ typedef struct
|
||||
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
|
||||
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
|
||||
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PT_Mask */
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PT_Mask */
|
||||
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
|
||||
|
||||
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_V_Mask */
|
||||
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PE_Mask */
|
||||
FunctionalState SymbolClockGen; /*!< Enable/Disable the SPDIFRX Symbol Clock generation.
|
||||
This parameter can be set to Enable or Disable */
|
||||
This parameter can be set to Enable or Disable */
|
||||
|
||||
FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation.
|
||||
This parameter can be set to Enable or Disable */
|
||||
This parameter can be set to Enable or Disable */
|
||||
} SPDIFRX_InitTypeDef;
|
||||
|
||||
/**
|
||||
@ -94,17 +98,20 @@ typedef struct
|
||||
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
|
||||
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
|
||||
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PT_Mask */
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PT_Mask */
|
||||
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
|
||||
|
||||
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_V_Mask */
|
||||
This parameter can be a value of @ref SPDIFRX_V_Mask */
|
||||
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PE_Mask */
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PE_Mask */
|
||||
|
||||
} SPDIFRX_SetDataFormatTypeDef;
|
||||
|
||||
@ -156,7 +163,8 @@ typedef struct
|
||||
decremented when a sample is received.
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
|
||||
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information
|
||||
DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
|
||||
|
||||
@ -167,9 +175,11 @@ typedef struct
|
||||
__IO uint32_t ErrorCode; /* SPDIFRX Error code */
|
||||
|
||||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
|
||||
void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */
|
||||
void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed
|
||||
callback */
|
||||
void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */
|
||||
void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */
|
||||
void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed
|
||||
callback */
|
||||
void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */
|
||||
void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */
|
||||
void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */
|
||||
@ -177,9 +187,6 @@ typedef struct
|
||||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
|
||||
|
||||
} SPDIFRX_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
@ -199,9 +206,12 @@ typedef enum
|
||||
/**
|
||||
* @brief HAL SPDIFRX Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */
|
||||
typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback
|
||||
function */
|
||||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
|
||||
* @{
|
||||
@ -265,8 +275,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!<
|
||||
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
|
||||
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
|
||||
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied
|
||||
into the SPDIF_DR */
|
||||
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied
|
||||
into the SPDIF_DR, zeros are written instead*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -1091,8 +1091,11 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
|
||||
((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
|
||||
((LENGTH) == SPI_CRC_LENGTH_4BIT))
|
||||
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL)
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL)
|
||||
|
||||
|
||||
#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
|
||||
((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
|
||||
|
||||
@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
||||
*/
|
||||
|
||||
/* SRAM State functions ******************************************************/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -406,29 +406,28 @@ typedef struct
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
@ -1037,8 +1036,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
|
||||
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
|
||||
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
|
||||
#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
|
||||
#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1864,6 +1863,10 @@ mode.
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV8))
|
||||
|
||||
#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
|
||||
((__CHANNEL__) != (TIM_CHANNEL_5)) && \
|
||||
((__CHANNEL__) != (TIM_CHANNEL_6)))
|
||||
|
||||
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
|
||||
((__MODE__) == TIM_OPMODE_REPETITIVE))
|
||||
|
||||
@ -1884,8 +1887,9 @@ mode.
|
||||
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
|
||||
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
|
||||
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
|
||||
((__PERIOD__) > 0U))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
@ -1938,7 +1942,6 @@ mode.
|
||||
|
||||
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
|
||||
|
||||
|
||||
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
|
||||
((__STATE__) == TIM_BREAK_DISABLE))
|
||||
|
||||
@ -2009,8 +2012,8 @@ mode.
|
||||
((__MODE__) == TIM_OCMODE_PWM2) || \
|
||||
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
|
||||
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
|
||||
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
|
||||
|
||||
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
|
||||
((__MODE__) == TIM_OCMODE_ACTIVE) || \
|
||||
@ -2304,7 +2307,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
|
||||
* @{
|
||||
*/
|
||||
/* Timer Encoder functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
@ -2353,7 +2356,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
|
||||
@ -471,7 +471,7 @@ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISel
|
||||
#if defined(TIM_BDTR_BKBID)
|
||||
|
||||
HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput);
|
||||
#endif /* TIM_BDTR_BKBID */
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -178,7 +178,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
|
||||
|
||||
|
||||
/**
|
||||
|
||||
@ -144,7 +144,7 @@ typedef struct __USART_HandleTypeDef
|
||||
|
||||
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
|
||||
|
||||
uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
|
||||
uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
|
||||
of @ref USARTEx_Slave_Mode */
|
||||
|
||||
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
|
||||
|
||||
@ -45,7 +45,7 @@ extern "C" {
|
||||
* @{
|
||||
*/
|
||||
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -386,7 +386,14 @@ extern "C" {
|
||||
#endif /* ADC_VER_V5_3 */
|
||||
|
||||
#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
|
||||
#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
|
||||
#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx)
|
||||
#define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor ,
|
||||
temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
|
||||
110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */
|
||||
#else
|
||||
#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been
|
||||
calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
|
||||
#endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */
|
||||
#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
|
||||
|
||||
/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
|
||||
@ -6025,8 +6032,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
AWDThresholdsHighLow,
|
||||
AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
|
||||
(ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)),
|
||||
AWDThresholdValue << (((AWDThresholdsHighLow * ADC3_TR1_HT1) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -6081,11 +6088,24 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
|
||||
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
|
||||
{
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
|
||||
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
|
||||
+ (AWDThresholdsHighLow));
|
||||
if (ADCx == ADC3)
|
||||
{
|
||||
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
|
||||
((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
|
||||
|
||||
return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
|
||||
return (uint32_t)(READ_BIT(*preg,
|
||||
(ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)))
|
||||
>> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
|
||||
& ~(AWDThresholdsHighLow & ADC3_TR1_LT1)));
|
||||
}
|
||||
else
|
||||
{
|
||||
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
|
||||
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
|
||||
+ (AWDThresholdsHighLow));
|
||||
|
||||
return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
|
||||
}
|
||||
#else
|
||||
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
|
||||
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
|
||||
@ -6150,7 +6170,8 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t
|
||||
/* containing other bits reserved for other purpose. */
|
||||
if (ADCx == ADC3)
|
||||
{
|
||||
uint32_t __IO *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
|
||||
((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
|
||||
|
||||
MODIFY_REG(*preg,
|
||||
ADC3_TR1_HT1 | ADC3_TR1_LT1,
|
||||
|
||||
@ -77,70 +77,79 @@ static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer
|
||||
or as Source base address in case of memory to memory transfer direction.
|
||||
uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer
|
||||
or as Source base address in case of memory to memory transfer direction.
|
||||
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
|
||||
uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
|
||||
or as Destination base address in case of memory to memory transfer direction.
|
||||
uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
|
||||
or as Destination base address in case of memory to memory transfer direction.
|
||||
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the normal or circular operation mode.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_MODE
|
||||
@note: The circular buffer mode cannot be used if the memory to memory
|
||||
data transfer direction is configured on the selected Channel
|
||||
uint32_t Mode; /*!< Specifies the normal or circular operation mode.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_MODE
|
||||
@note: The circular buffer mode cannot be used if the memory to memory
|
||||
data transfer direction is configured on the selected Channel
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
|
||||
|
||||
uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_PERIPH
|
||||
uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_PERIPH
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
|
||||
|
||||
uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_MEMORY
|
||||
uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_MEMORY
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
|
||||
|
||||
uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
|
||||
uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
|
||||
|
||||
uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
|
||||
uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
|
||||
|
||||
uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
|
||||
The data unit is equal to the source buffer configuration set in PeripheralSize
|
||||
or MemorySize parameters depending in the transfer direction.
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
|
||||
uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
|
||||
The data unit is equal to the source buffer configuration set in PeripheralSize
|
||||
or MemorySize parameters depending in the transfer direction.
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
|
||||
|
||||
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
|
||||
This parameter can be a value of @ref DMAMUX2_Request_selection
|
||||
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
|
||||
This parameter can be a value of @ref DMAMUX2_Request_selection
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the channel priority level.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
|
||||
uint32_t Priority; /*!< Specifies the channel priority level.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
|
||||
|
||||
uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_DOUBLEBUFFER_MODE
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_EnableDoubleBufferMode() & LL_BDMA_DisableDoubleBufferMode(). */
|
||||
|
||||
uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
|
||||
This parameter can be a value of @ref BDMA_LL_EC_CURRENTTARGETMEM
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetCurrentTargetMem(). */
|
||||
} LL_BDMA_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
@ -275,7 +284,7 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
|
||||
/** @defgroup BDMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
|
||||
* @{
|
||||
*/
|
||||
#define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
|
||||
@ -284,6 +293,15 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BDMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
|
||||
* @{
|
||||
*/
|
||||
#define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
|
||||
#define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode
|
||||
* @{
|
||||
*/
|
||||
@ -333,14 +351,6 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
|
||||
* @{
|
||||
*/
|
||||
#define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
|
||||
#define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -549,7 +559,9 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t
|
||||
* CCR MINC LL_BDMA_ConfigTransfer\n
|
||||
* CCR PSIZE LL_BDMA_ConfigTransfer\n
|
||||
* CCR MSIZE LL_BDMA_ConfigTransfer\n
|
||||
* CCR PL LL_BDMA_ConfigTransfer
|
||||
* CCR PL LL_BDMA_ConfigTransfer\n
|
||||
* CCR DBM LL_BDMA_ConfigTransfer\n
|
||||
* CCR CT LL_BDMA_ConfigTransfer
|
||||
* @param BDMAx BDMA Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref LL_BDMA_CHANNEL_0
|
||||
@ -568,6 +580,8 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t
|
||||
* @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD
|
||||
* @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD
|
||||
* @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH
|
||||
* @arg @ref LL_BDMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_BDMA_DOUBLEBUFFER_MODE_ENABLE
|
||||
* @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
|
||||
@ -575,8 +589,8 @@ __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channe
|
||||
uint32_t bdma_base_addr = (uint32_t)BDMAx;
|
||||
|
||||
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
|
||||
BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,
|
||||
Configuration);
|
||||
BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL | \
|
||||
BDMA_CCR_DBM | BDMA_CCR_CT, Configuration);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1094,6 +1108,28 @@ __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32
|
||||
CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if double buffer mode is enabled or not.
|
||||
* @rmtoll CCR DBM LL_BDMA_IsEnabledDoubleBufferMode
|
||||
* @param BDMAx BDMAx Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref LL_BDMA_CHANNEL_0
|
||||
* @arg @ref LL_BDMA_CHANNEL_1
|
||||
* @arg @ref LL_BDMA_CHANNEL_2
|
||||
* @arg @ref LL_BDMA_CHANNEL_3
|
||||
* @arg @ref LL_BDMA_CHANNEL_4
|
||||
* @arg @ref LL_BDMA_CHANNEL_5
|
||||
* @arg @ref LL_BDMA_CHANNEL_6
|
||||
* @arg @ref LL_BDMA_CHANNEL_7
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
|
||||
{
|
||||
register uint32_t bdma_base_addr = (uint32_t)BDMAx;
|
||||
|
||||
return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM) == (BDMA_CCR_DBM)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the Source and Destination addresses.
|
||||
* @note This API must not be called when the BDMA channel is enabled.
|
||||
|
||||
@ -819,6 +819,91 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EF_FLAG_Management Comparator flag Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get comparator output trigger flag (latched)
|
||||
* @rmtoll SR C1IF LL_COMP_IsActiveFlag_OutputTrig
|
||||
* @param COMPx Comparator instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx)
|
||||
{
|
||||
if (COMPx == COMP1)
|
||||
{
|
||||
return ((READ_BIT(COMP12->SR, COMP_SR_C1IF) == (COMP_SR_C1IF)) ? 1UL : 0UL);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ((READ_BIT(COMP12->SR, COMP_SR_C2IF) == (COMP_SR_C2IF)) ? 1UL : 0UL);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear comparator comparator output trigger flag (latched)
|
||||
* @rmtoll ICFR CC1IF LL_COMP_ClearFlag_OutputTrig
|
||||
* @param COMPx Comparator instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *COMPx)
|
||||
{
|
||||
if (COMPx == COMP1)
|
||||
{
|
||||
SET_BIT(COMP12->ICFR, COMP_ICFR_C1IF);
|
||||
}
|
||||
else
|
||||
{
|
||||
SET_BIT(COMP12->ICFR, COMP_ICFR_C2IF);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EF_IT_Management Comparartor IT management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable comparator output trigger interrupt
|
||||
* @rmtoll ICFR ITEN LL_COMP_EnableIT_OutputTrig
|
||||
* @param COMPx Comparator instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_EnableIT_OutputTrig(COMP_TypeDef *COMPx)
|
||||
{
|
||||
SET_BIT(COMPx->CFGR, COMP_CFGRx_ITEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable comparator output trigger interrupt
|
||||
* @rmtoll ICFR ITEN LL_COMP_DisableIT_OutputTrig
|
||||
* @param COMPx Comparator instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *COMPx)
|
||||
{
|
||||
CLEAR_BIT(COMPx->CFGR, COMP_CFGRx_ITEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator output trigger interrupt state
|
||||
* @rmtoll ICFR ITEN LL_COMP_IsEnabledIT_OutputTrig
|
||||
* @param COMPx Comparator instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_ITEN) == (COMP_CFGRx_ITEN)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
|
||||
@ -184,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
|
||||
}
|
||||
@ -215,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
|
||||
}
|
||||
@ -242,7 +242,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
|
||||
}
|
||||
@ -270,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable initial CRC value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->INIT));
|
||||
}
|
||||
@ -301,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable Polynomial value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->POL));
|
||||
}
|
||||
@ -359,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->DR));
|
||||
}
|
||||
@ -371,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint16_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
@ -383,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
@ -395,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
|
||||
}
|
||||
@ -407,7 +407,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->IDR));
|
||||
}
|
||||
@ -433,7 +433,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||
ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -282,19 +282,19 @@ typedef struct
|
||||
#if defined (HRTIM1)
|
||||
#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */
|
||||
#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */
|
||||
#endif
|
||||
#endif /* HRTIM1 */
|
||||
#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
|
||||
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
|
||||
#if defined(TIM23)
|
||||
#define LL_DAC_TRIG_EXT_TIM23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */
|
||||
#endif
|
||||
#endif /* TIM23 */
|
||||
#if defined(TIM24)
|
||||
#define LL_DAC_TRIG_EXT_TIM24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */
|
||||
#endif
|
||||
#endif /* TIM24 */
|
||||
#if defined (DAC2)
|
||||
#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
|
||||
#endif
|
||||
#endif /* DAC2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -557,12 +557,10 @@ typedef struct
|
||||
* @arg @ref LL_DAC_RESOLUTION_8B
|
||||
* @retval DAC conversion data (unit: digital value)
|
||||
*/
|
||||
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
|
||||
__DAC_VOLTAGE__,\
|
||||
__DAC_RESOLUTION__) \
|
||||
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
/ (__VREFANALOG_VOLTAGE__) \
|
||||
)
|
||||
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
|
||||
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
/ (__VREFANALOG_VOLTAGE__) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -577,6 +575,7 @@ typedef struct
|
||||
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
|
||||
* @{
|
||||
*/
|
||||
@ -615,7 +614,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin
|
||||
* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
|
||||
* @arg @ref LL_DAC_MODE_CALIBRATION
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -654,7 +653,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -749,7 +748,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
||||
* (4) On this STM32 series, parameter not available on all devices.
|
||||
* Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -792,7 +791,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA
|
||||
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
|
||||
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -858,7 +857,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
||||
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
|
||||
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -925,7 +924,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
|
||||
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
|
||||
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -1023,7 +1022,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
||||
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
|
||||
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -1066,7 +1065,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
|
||||
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
|
||||
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -1125,7 +1124,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_
|
||||
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
|
||||
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -1167,7 +1166,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
|
||||
@ -1205,7 +1204,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -1242,7 +1241,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@ -1304,7 +1303,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
@ -1343,7 +1342,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
|
||||
* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
|
||||
* @retval DAC register address
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
|
||||
__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
|
||||
{
|
||||
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
|
||||
/* DAC channel selected. */
|
||||
@ -1404,7 +1403,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
@ -1462,7 +1461,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
@ -1635,7 +1634,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
|
||||
@ -1657,7 +1656,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1669,7 +1668,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1681,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1692,7 +1691,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1704,7 +1703,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1716,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1808,7 +1807,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1820,7 +1819,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1835,8 +1834,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
|
||||
/**
|
||||
@ -1863,4 +1862,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_LL_DAC_H */
|
||||
|
||||
|
||||
@ -85,98 +85,107 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
|
||||
or as Source base address in case of memory to memory transfer direction.
|
||||
uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
|
||||
or as Source base address in case of memory to memory transfer direction.
|
||||
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
|
||||
uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
|
||||
or as Destination base address in case of memory to memory transfer direction.
|
||||
uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
|
||||
or as Destination base address in case of memory to memory transfer direction.
|
||||
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_LL_EC_DIRECTION
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_LL_EC_DIRECTION
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the normal or circular operation mode.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MODE
|
||||
@note The circular buffer mode cannot be used if the memory to memory
|
||||
data transfer direction is configured on the selected Stream
|
||||
uint32_t Mode; /*!< Specifies the normal or circular operation mode.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MODE
|
||||
@note The circular buffer mode cannot be used if the memory to memory
|
||||
data transfer direction is configured on the selected Stream
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
|
||||
|
||||
uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PERIPH
|
||||
uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PERIPH
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
|
||||
|
||||
uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MEMORY
|
||||
uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MEMORY
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
|
||||
|
||||
uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
|
||||
uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
|
||||
|
||||
uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
|
||||
uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
|
||||
|
||||
uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
|
||||
The data unit is equal to the source buffer configuration set in PeripheralSize
|
||||
or MemorySize parameters depending in the transfer direction.
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
|
||||
uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
|
||||
The data unit is equal to the source buffer configuration set in PeripheralSize
|
||||
or MemorySize parameters depending in the transfer direction.
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
|
||||
|
||||
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
|
||||
This parameter can be a value of @ref DMAMUX1_Request_selection
|
||||
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
|
||||
This parameter can be a value of @ref DMAMUX1_Request_selection
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the channel priority level.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PRIORITY
|
||||
uint32_t Priority; /*!< Specifies the channel priority level.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PRIORITY
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
|
||||
|
||||
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_LL_FIFOMODE
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected stream
|
||||
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_LL_FIFOMODE
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected stream
|
||||
|
||||
This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
|
||||
This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
|
||||
|
||||
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
|
||||
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
|
||||
|
||||
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MBURST
|
||||
@note The burst mode is possible only if the address Increment mode is enabled.
|
||||
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MBURST
|
||||
@note The burst mode is possible only if the address Increment mode is enabled.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
|
||||
|
||||
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PBURST
|
||||
@note The burst mode is possible only if the address Increment mode is enabled.
|
||||
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PBURST
|
||||
@note The burst mode is possible only if the address Increment mode is enabled.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
|
||||
|
||||
uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode.
|
||||
This parameter can be a value of @ref DMA_LL_EC_DOUBLEBUFFER_MODE
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_EnableDoubleBufferMode() & LL_DMA_DisableDoubleBufferMode(). */
|
||||
|
||||
uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
|
||||
This parameter can be a value of @ref DMA_LL_EC_CURRENTTARGETMEM
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetCurrentTargetMem(). */
|
||||
} LL_DMA_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
@ -233,6 +242,15 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
|
||||
* @{
|
||||
*/
|
||||
#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
|
||||
#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_LL_EC_PERIPH PERIPH
|
||||
* @{
|
||||
*/
|
||||
@ -347,15 +365,6 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
|
||||
* @{
|
||||
*/
|
||||
#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
|
||||
#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -537,7 +546,9 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre
|
||||
* CR PSIZE LL_DMA_ConfigTransfer\n
|
||||
* CR MSIZE LL_DMA_ConfigTransfer\n
|
||||
* CR PL LL_DMA_ConfigTransfer\n
|
||||
* CR PFCTRL LL_DMA_ConfigTransfer
|
||||
* CR PFCTRL LL_DMA_ConfigTransfer\n
|
||||
* CR DBM LL_DMA_ConfigTransfer\n
|
||||
* CR CT LL_DMA_ConfigTransfer
|
||||
* @param DMAx DMAx Instance
|
||||
* @param Stream This parameter can be one of the following values:
|
||||
* @arg @ref LL_DMA_STREAM_0
|
||||
@ -556,6 +567,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre
|
||||
* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
|
||||
* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
|
||||
* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
|
||||
* @arg @ref LL_DMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_DMA_DOUBLEBUFFER_MODE_ENABLE
|
||||
* @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1
|
||||
*@retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
|
||||
@ -563,8 +576,8 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
|
||||
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
|
||||
DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
|
||||
Configuration);
|
||||
DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | \
|
||||
DMA_SxCR_PFCTRL | DMA_SxCR_DBM | DMA_SxCR_CT, Configuration);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1587,6 +1600,28 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t
|
||||
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if double buffer mode is enabled or not.
|
||||
* @rmtoll CR DBM LL_DMA_IsEnabledDoubleBufferMode
|
||||
* @param DMAx DMAx Instance
|
||||
* @param Stream This parameter can be one of the following values:
|
||||
* @arg @ref LL_DMA_STREAM_0
|
||||
* @arg @ref LL_DMA_STREAM_1
|
||||
* @arg @ref LL_DMA_STREAM_2
|
||||
* @arg @ref LL_DMA_STREAM_3
|
||||
* @arg @ref LL_DMA_STREAM_4
|
||||
* @arg @ref LL_DMA_STREAM_5
|
||||
* @arg @ref LL_DMA_STREAM_6
|
||||
* @arg @ref LL_DMA_STREAM_7
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
|
||||
{
|
||||
register uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
|
||||
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get FIFO status.
|
||||
* @rmtoll FCR FS LL_DMA_GetFIFOStatus
|
||||
|
||||
@ -184,7 +184,7 @@ __STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Wa
|
||||
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
|
||||
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM));
|
||||
}
|
||||
@ -209,7 +209,7 @@ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer
|
||||
* @retval uint8_t Number of 16-bit words allocated to the input buffer
|
||||
* (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
|
||||
}
|
||||
@ -234,7 +234,7 @@ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
|
||||
* @retval uint8_t Base address of the input buffer (X1) within the internal memory
|
||||
* (value between Min_Data=0x00 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos);
|
||||
}
|
||||
@ -259,7 +259,7 @@ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer
|
||||
* @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
|
||||
* (value between Min_Data=0x01 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
|
||||
}
|
||||
@ -284,7 +284,7 @@ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
|
||||
* @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
|
||||
* (value between Min_Data=0x00 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos);
|
||||
}
|
||||
@ -315,7 +315,7 @@ __STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Wa
|
||||
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
|
||||
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM));
|
||||
}
|
||||
@ -340,7 +340,7 @@ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferS
|
||||
* @retval uint8_t Number of 16-bit words allocated to the output buffer
|
||||
* (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
|
||||
}
|
||||
@ -365,7 +365,7 @@ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
|
||||
* @retval uint8_t Base address of the output buffer (Y) within the internal memory
|
||||
* (value between Min_Data=0x00 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetYBase(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos);
|
||||
}
|
||||
@ -398,7 +398,7 @@ __STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -431,7 +431,7 @@ __STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function)
|
||||
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
|
||||
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_GetFunction(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC));
|
||||
}
|
||||
@ -455,7 +455,7 @@ __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetParamR(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos);
|
||||
}
|
||||
@ -479,7 +479,7 @@ __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos);
|
||||
}
|
||||
@ -504,7 +504,7 @@ __STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
|
||||
* @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
|
||||
* (value between Min_Data=0x00 and Max_Data=0xFF).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint8_t LL_FMAC_GetParamP(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
|
||||
}
|
||||
@ -534,7 +534,7 @@ __STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -575,7 +575,7 @@ __STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -616,7 +616,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -649,7 +649,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -690,7 +690,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -723,7 +723,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -756,7 +756,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -789,7 +789,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -822,7 +822,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -841,7 +841,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -863,7 +863,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -874,7 +874,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -885,7 +885,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint32_t State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -917,7 +917,7 @@ __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
|
||||
* @param FMACx FMAC instance
|
||||
* @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
|
||||
__STATIC_INLINE uint16_t LL_FMAC_ReadData(const FMAC_TypeDef *FMACx)
|
||||
{
|
||||
return (uint16_t)(READ_REG(FMACx->RDATA));
|
||||
}
|
||||
@ -1040,7 +1040,7 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint
|
||||
* @{
|
||||
*/
|
||||
ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
|
||||
ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx);
|
||||
ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx);
|
||||
|
||||
|
||||
/**
|
||||
|
||||
@ -1135,7 +1135,7 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
|
||||
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
|
||||
HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
|
||||
uint32_t AutoRefreshNumber);
|
||||
uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
|
||||
}
|
||||
@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
|
||||
* @retval Address of data register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
{
|
||||
uint32_t data_reg_addr;
|
||||
|
||||
@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t
|
||||
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
|
||||
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
|
||||
}
|
||||
@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
|
||||
}
|
||||
@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
|
||||
}
|
||||
@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
|
||||
}
|
||||
@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
|
||||
}
|
||||
@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
|
||||
}
|
||||
@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
|
||||
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
|
||||
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
|
||||
}
|
||||
@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
|
||||
}
|
||||
@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
|
||||
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
|
||||
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
|
||||
}
|
||||
@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
|
||||
}
|
||||
@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
|
||||
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
|
||||
(ClockTimeout)) ? 1UL : 0UL);
|
||||
@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
|
||||
}
|
||||
@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans
|
||||
* @arg @ref LL_I2C_REQUEST_WRITE
|
||||
* @arg @ref LL_I2C_REQUEST_READ
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
|
||||
}
|
||||
@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
|
||||
}
|
||||
@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
|
||||
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
|
||||
{
|
||||
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
||||
uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
|
||||
((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
|
||||
(((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
||||
(uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
|
||||
|
||||
/* update CR2 register */
|
||||
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
|
||||
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
|
||||
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
|
||||
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
|
||||
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
|
||||
tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2150,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
|
||||
* @arg @ref LL_I2C_DIRECTION_WRITE
|
||||
* @arg @ref LL_I2C_DIRECTION_READ
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
|
||||
}
|
||||
@ -2161,7 +2168,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
|
||||
}
|
||||
@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2204,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
|
||||
}
|
||||
@ -2215,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
|
||||
}
|
||||
@ -2241,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
|
||||
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
|
||||
|
||||
|
||||
@ -357,7 +357,7 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
|
||||
ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
|
||||
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
|
||||
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
|
||||
void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
|
||||
|
||||
@ -219,7 +219,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -232,7 +232,12 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
|
||||
{
|
||||
#if defined(RNG_CR_CONDRST)
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
||||
#else
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CED);
|
||||
#endif /* RNG_CR_CONDRST*/
|
||||
}
|
||||
|
||||
/**
|
||||
@ -243,7 +248,12 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
|
||||
{
|
||||
#if defined(RNG_CR_CONDRST)
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
||||
#else
|
||||
SET_BIT(RNGx->CR, RNG_CR_CED);
|
||||
#endif /* RNG_CR_CONDRST*/
|
||||
}
|
||||
|
||||
/**
|
||||
@ -252,7 +262,7 @@ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -286,7 +296,7 @@ __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -308,7 +318,7 @@ __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -321,7 +331,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -332,7 +343,8 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CR, RNG_CR_NISTC);
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -341,7 +353,7 @@ __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -355,7 +367,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
|
||||
{
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -364,7 +377,7 @@ __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
|
||||
}
|
||||
@ -378,7 +391,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
|
||||
{
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -387,7 +401,7 @@ __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
|
||||
}
|
||||
@ -401,7 +415,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
|
||||
{
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -410,7 +425,7 @@ __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
|
||||
}
|
||||
@ -440,7 +455,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
|
||||
{
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
|
||||
MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -465,7 +481,7 @@ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
|
||||
* @arg @ref LL_RNG_CLKDIV_BY_16384
|
||||
* @arg @ref LL_RNG_CLKDIV_BY_32768
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
|
||||
}
|
||||
@ -484,7 +500,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -495,7 +511,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -506,7 +522,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -517,7 +533,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -528,7 +544,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -594,7 +610,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -613,7 +629,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval Generated 32-bit random value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(RNGx->DR));
|
||||
}
|
||||
@ -666,7 +682,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
|
||||
*/
|
||||
ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
|
||||
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
|
||||
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
|
||||
ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -1366,7 +1366,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma
|
||||
|
||||
/**
|
||||
* @brief Get time format (AM or PM notation)
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@ -1400,7 +1400,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
|
||||
|
||||
/**
|
||||
* @brief Get Hours in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@ -1435,7 +1435,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
|
||||
|
||||
/**
|
||||
* @brief Get Minutes in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@ -1470,7 +1470,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
|
||||
|
||||
/**
|
||||
* @brief Get Seconds in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@ -1520,7 +1520,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
|
||||
|
||||
/**
|
||||
* @brief Get time (hour, minute and second) in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@ -1666,7 +1666,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
|
||||
|
||||
/**
|
||||
* @brief Get Year in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
|
||||
* @rmtoll RTC_DR YT LL_RTC_DATE_GetYear
|
||||
@ -1700,7 +1700,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
|
||||
|
||||
/**
|
||||
* @brief Get Week day
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay
|
||||
* @param RTCx RTC Instance
|
||||
@ -1747,7 +1747,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
|
||||
|
||||
/**
|
||||
* @brief Get Month in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
|
||||
* @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth
|
||||
@ -1789,7 +1789,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
|
||||
|
||||
/**
|
||||
* @brief Get Day in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
|
||||
* @rmtoll RTC_DR DT LL_RTC_DATE_GetDay
|
||||
@ -1851,7 +1851,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
|
||||
|
||||
/**
|
||||
* @brief Get date (WeekDay, Day, Month and Year) in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
|
||||
* and __LL_RTC_GET_DAY are available to get independently each parameter.
|
||||
|
||||
@ -575,7 +575,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -610,7 +610,7 @@ __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -645,7 +645,7 @@ __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -673,7 +673,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
|
||||
* @arg @ref LL_SPI_MODE_MASTER
|
||||
* @arg @ref LL_SPI_MODE_SLAVE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
|
||||
}
|
||||
@ -728,7 +728,7 @@ __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t Mast
|
||||
* @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
|
||||
* @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
|
||||
}
|
||||
@ -783,7 +783,7 @@ __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t Mas
|
||||
* @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
|
||||
* @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
|
||||
}
|
||||
@ -808,7 +808,7 @@ __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
|
||||
}
|
||||
@ -833,7 +833,7 @@ __STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
|
||||
}
|
||||
@ -857,7 +857,7 @@ __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -873,7 +873,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
|
||||
{
|
||||
MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
|
||||
MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -884,7 +884,7 @@ __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCR
|
||||
* @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
|
||||
* @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
|
||||
}
|
||||
@ -911,7 +911,7 @@ __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCR
|
||||
* @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
|
||||
* @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
|
||||
}
|
||||
@ -939,7 +939,7 @@ __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLev
|
||||
* @arg @ref LL_SPI_SS_LEVEL_HIGH
|
||||
* @arg @ref LL_SPI_SS_LEVEL_LOW
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
|
||||
}
|
||||
@ -972,7 +972,7 @@ __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1005,7 +1005,7 @@ __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1038,7 +1038,7 @@ __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1068,7 +1068,7 @@ __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRC
|
||||
* @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
|
||||
* @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
|
||||
}
|
||||
@ -1098,7 +1098,7 @@ __STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetec
|
||||
* @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
|
||||
* @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
|
||||
}
|
||||
@ -1126,7 +1126,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
|
||||
* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
|
||||
* @arg @ref LL_SPI_PROTOCOL_TI
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
|
||||
}
|
||||
@ -1155,7 +1155,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase
|
||||
* @arg @ref LL_SPI_PHASE_1EDGE
|
||||
* @arg @ref LL_SPI_PHASE_2EDGE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
|
||||
}
|
||||
@ -1184,7 +1184,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
|
||||
* @arg @ref LL_SPI_POLARITY_LOW
|
||||
* @arg @ref LL_SPI_POLARITY_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
|
||||
}
|
||||
@ -1213,7 +1213,7 @@ __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolari
|
||||
* @arg @ref LL_SPI_NSS_POLARITY_LOW
|
||||
* @arg @ref LL_SPI_NSS_POLARITY_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
|
||||
}
|
||||
@ -1254,7 +1254,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau
|
||||
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
|
||||
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
|
||||
}
|
||||
@ -1283,7 +1283,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO
|
||||
* @arg @ref LL_SPI_LSB_FIRST
|
||||
* @arg @ref LL_SPI_MSB_FIRST
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
|
||||
}
|
||||
@ -1321,7 +1321,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra
|
||||
* @arg @ref LL_SPI_HALF_DUPLEX_RX
|
||||
* @arg @ref LL_SPI_HALF_DUPLEX_TX
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
|
||||
uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
|
||||
@ -1352,7 +1352,7 @@ __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t H
|
||||
* @arg @ref LL_SPI_HALF_DUPLEX_RX
|
||||
* @arg @ref LL_SPI_HALF_DUPLEX_TX
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
|
||||
}
|
||||
@ -1434,7 +1434,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
|
||||
* @arg @ref LL_SPI_DATAWIDTH_31BIT
|
||||
* @arg @ref LL_SPI_DATAWIDTH_32BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
|
||||
}
|
||||
@ -1490,7 +1490,7 @@ __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thresho
|
||||
* @arg @ref LL_SPI_FIFO_TH_15DATA
|
||||
* @arg @ref LL_SPI_FIFO_TH_16DATA
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
|
||||
}
|
||||
@ -1524,7 +1524,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1606,7 +1606,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
|
||||
* @arg @ref LL_SPI_CRC_31BIT
|
||||
* @arg @ref LL_SPI_CRC_32BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
|
||||
}
|
||||
@ -1639,7 +1639,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
|
||||
* @arg @ref LL_SPI_NSS_HARD_INPUT
|
||||
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
|
||||
}
|
||||
@ -1676,7 +1676,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1695,7 +1695,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1706,7 +1706,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1717,7 +1717,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1728,7 +1728,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1739,7 +1739,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1750,7 +1750,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1761,7 +1761,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1772,7 +1772,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1783,7 +1783,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1794,7 +1794,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1805,7 +1805,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1816,7 +1816,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1827,7 +1827,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1838,7 +1838,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1849,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
|
||||
}
|
||||
@ -1864,7 +1864,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
|
||||
* @arg @ref LL_SPI_RX_FIFO_2PACKET
|
||||
* @arg @ref LL_SPI_RX_FIFO_3PACKET
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
|
||||
}
|
||||
@ -2224,7 +2224,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2235,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2246,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2257,7 +2257,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2268,7 +2268,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2279,7 +2279,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2290,7 +2290,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2301,7 +2301,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2312,7 +2312,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2323,7 +2323,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2334,7 +2334,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2375,7 +2375,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2408,7 +2408,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2418,7 +2418,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval Address of data register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t) &(SPIx->TXDR);
|
||||
}
|
||||
@ -2429,7 +2429,7 @@ __STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval Address of data register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t) &(SPIx->RXDR);
|
||||
}
|
||||
@ -2447,7 +2447,7 @@ __STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
|
||||
{
|
||||
return (*((__IO uint8_t *)&SPIx->RXDR));
|
||||
}
|
||||
@ -2458,7 +2458,7 @@ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
|
||||
{
|
||||
#if defined (__GNUC__)
|
||||
__IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
|
||||
@ -2474,7 +2474,7 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
|
||||
{
|
||||
return (*((__IO uint32_t *)&SPIx->RXDR));
|
||||
}
|
||||
@ -2538,7 +2538,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(SPIx->CRCPOLY));
|
||||
}
|
||||
@ -2561,7 +2561,7 @@ __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(SPIx->UDRDR));
|
||||
}
|
||||
@ -2572,7 +2572,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(SPIx->RXCRC));
|
||||
}
|
||||
@ -2583,7 +2583,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(SPIx->TXCRC));
|
||||
}
|
||||
@ -2597,7 +2597,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
|
||||
ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
|
||||
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
|
||||
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
|
||||
|
||||
@ -2884,7 +2884,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength
|
||||
* @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
|
||||
* @arg @ref LL_I2S_DATAFORMAT_32B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
|
||||
}
|
||||
@ -2913,7 +2913,7 @@ __STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t Cha
|
||||
* @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
|
||||
* @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
|
||||
}
|
||||
@ -2946,7 +2946,7 @@ __STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Handle
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2973,7 +2973,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
|
||||
* @arg @ref LL_I2S_POLARITY_LOW
|
||||
* @arg @ref LL_I2S_POLARITY_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
|
||||
}
|
||||
@ -3008,7 +3008,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
|
||||
* @arg @ref LL_I2S_STANDARD_PCM_SHORT
|
||||
* @arg @ref LL_I2S_STANDARD_PCM_LONG
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
|
||||
}
|
||||
@ -3043,7 +3043,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard
|
||||
* @arg @ref LL_I2S_MODE_MASTER_RX
|
||||
* @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
|
||||
}
|
||||
@ -3104,7 +3104,7 @@ __STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledIOSwap(SPIx);
|
||||
}
|
||||
@ -3139,7 +3139,7 @@ __STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledGPIOControl(SPIx);
|
||||
}
|
||||
@ -3163,7 +3163,7 @@ __STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledIOLock(SPIx);
|
||||
}
|
||||
@ -3190,7 +3190,7 @@ __STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO
|
||||
* @arg @ref LL_I2S_LSB_FIRST
|
||||
* @arg @ref LL_I2S_MSB_FIRST
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_GetTransferBitOrder(SPIx);
|
||||
}
|
||||
@ -3208,11 +3208,11 @@ __STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
|
||||
|
||||
/**
|
||||
* @brief Check if there is an unfinished transfer
|
||||
* @rmtoll CR1 CSTART LL_I2S_IsTransferActive
|
||||
* @rmtoll CR1 CSTART LL_I2S_IsActiveTransfer
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsActiveMasterTransfer(SPIx);
|
||||
}
|
||||
@ -3252,7 +3252,7 @@ __STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thresho
|
||||
* @arg @ref LL_I2S_FIFO_TH_07DATA
|
||||
* @arg @ref LL_I2S_FIFO_TH_08DATA
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_GetFIFOThreshold(SPIx);
|
||||
}
|
||||
@ -3276,7 +3276,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t Presc
|
||||
* @param SPIx SPI Instance
|
||||
* @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
|
||||
}
|
||||
@ -3303,7 +3303,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc
|
||||
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
|
||||
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
|
||||
}
|
||||
@ -3336,7 +3336,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -3356,7 +3356,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsActiveFlag_RXP(SPIx);
|
||||
}
|
||||
@ -3367,7 +3367,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsActiveFlag_TXP(SPIx);
|
||||
}
|
||||
@ -3378,7 +3378,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsActiveFlag_UDR(SPIx);
|
||||
}
|
||||
@ -3389,7 +3389,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsActiveFlag_OVR(SPIx);
|
||||
}
|
||||
@ -3400,7 +3400,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsActiveFlag_FRE(SPIx);
|
||||
}
|
||||
@ -3562,7 +3562,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledIT_RXP(SPIx);
|
||||
}
|
||||
@ -3573,7 +3573,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledIT_TXP(SPIx);
|
||||
}
|
||||
@ -3584,7 +3584,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledIT_UDR(SPIx);
|
||||
}
|
||||
@ -3595,7 +3595,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledIT_OVR(SPIx);
|
||||
}
|
||||
@ -3606,7 +3606,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledIT_FRE(SPIx);
|
||||
}
|
||||
@ -3647,7 +3647,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledDMAReq_RX(SPIx);
|
||||
}
|
||||
@ -3680,7 +3680,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval State of bit (1 or 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_IsEnabledDMAReq_TX(SPIx);
|
||||
}
|
||||
@ -3699,7 +3699,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
|
||||
{
|
||||
return LL_SPI_ReceiveData16(SPIx);
|
||||
}
|
||||
@ -3710,7 +3710,7 @@ __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
|
||||
* @param SPIx SPI Instance
|
||||
* @retval 0..0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
|
||||
__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
|
||||
{
|
||||
return LL_SPI_ReceiveData32(SPIx);
|
||||
}
|
||||
@ -3750,8 +3750,8 @@ __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
|
||||
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
|
||||
ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
|
||||
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct);
|
||||
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
|
||||
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
|
||||
|
||||
|
||||
@ -653,10 +653,10 @@ typedef struct
|
||||
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
|
||||
/**
|
||||
* @}
|
||||
@ -737,6 +737,15 @@ typedef struct
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/** Legacy definitions for compatibility purpose
|
||||
@cond 0
|
||||
*/
|
||||
#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
@endcond
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
|
||||
* @{
|
||||
*/
|
||||
@ -752,8 +761,8 @@ typedef struct
|
||||
#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
|
||||
#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
|
||||
#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
|
||||
#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
|
||||
#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
|
||||
#define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
|
||||
#define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -967,11 +976,11 @@ typedef struct
|
||||
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
|
||||
@ -1157,6 +1166,15 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** Legacy definitions for compatibility purpose
|
||||
@cond 0
|
||||
*/
|
||||
#define LL_TIM_ReArmBRK(_PARAM_)
|
||||
#define LL_TIM_ReArmBRK2(_PARAM_)
|
||||
/**
|
||||
@endcond
|
||||
*/
|
||||
|
||||
#endif /*TIM_BDTR_BKBID */
|
||||
/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
|
||||
* @{
|
||||
@ -1340,6 +1358,9 @@ typedef struct
|
||||
#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24 input 1 is connected to CAN TMP */
|
||||
#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24 input 1 is connected to CAN RTP */
|
||||
#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
/** Legacy definitions for compatibility purpose
|
||||
@ -1350,6 +1371,7 @@ typedef struct
|
||||
@endcond
|
||||
*/
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1480,11 +1502,6 @@ typedef struct
|
||||
((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1941,6 +1958,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
|
||||
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
|
||||
* @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
|
||||
{
|
||||
return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
|
||||
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
|
||||
@ -2085,7 +2113,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe
|
||||
* @arg @ref LL_TIM_CHANNEL_CH6
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
|
||||
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
|
||||
{
|
||||
return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2171,8 +2199,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
|
||||
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
|
||||
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
|
||||
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
|
||||
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
|
||||
@ -2211,8 +2239,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
|
||||
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
|
||||
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
|
||||
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
|
||||
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
@ -2426,7 +2454,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
* @arg @ref LL_TIM_CHANNEL_CH6
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
@ -2502,7 +2530,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
|
||||
* @arg @ref LL_TIM_CHANNEL_CH6
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
@ -2587,7 +2615,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
* @arg @ref LL_TIM_CHANNEL_CH6
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
@ -3136,7 +3164,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
|
||||
{
|
||||
return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -3688,18 +3716,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
|
||||
SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Re-arm the break input (when it operates in bidirectional mode).
|
||||
* @note The Break input is automatically armed as soon as MOE bit is set.
|
||||
* @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
|
||||
* @param TIMx Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
|
||||
{
|
||||
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
|
||||
}
|
||||
|
||||
#endif /*TIM_BDTR_BKBID */
|
||||
/**
|
||||
* @brief Enable the break 2 function.
|
||||
@ -3828,18 +3844,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
|
||||
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Re-arm the break 2 input (when it operates in bidirectional mode).
|
||||
* @note The Break 2 input is automatically armed as soon as MOE bit is set.
|
||||
* @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
|
||||
* @param TIMx Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
|
||||
{
|
||||
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
|
||||
}
|
||||
|
||||
#endif /*TIM_BDTR_BKBID */
|
||||
/**
|
||||
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
|
||||
@ -5170,7 +5174,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
|
||||
ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
|
||||
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
|
||||
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
|
||||
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
|
||||
|
||||
@ -1567,7 +1567,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_
|
||||
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
|
||||
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
|
||||
__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
|
||||
}
|
||||
|
||||
@ -37,6 +37,13 @@ extern "C" {
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#ifndef HAL_USB_TIMEOUT
|
||||
#define HAL_USB_TIMEOUT 0xF000000U
|
||||
#endif /* define HAL_USB_TIMEOUT */
|
||||
|
||||
#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
|
||||
#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
|
||||
#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
|
||||
|
||||
/**
|
||||
* @brief USB Mode definition
|
||||
@ -85,38 +92,39 @@ typedef enum
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t dev_endpoints; /*!< Device Endpoints number.
|
||||
uint8_t dev_endpoints; /*!< Device Endpoints number.
|
||||
This parameter depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t Host_channels; /*!< Host Channels number.
|
||||
uint8_t Host_channels; /*!< Host Channels number.
|
||||
This parameter Depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */
|
||||
uint8_t dma_enable; /*!< USB DMA state.
|
||||
If DMA is not supported this parameter shall be set by default to zero */
|
||||
|
||||
uint32_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref PCD_Speed/HCD_Speed
|
||||
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
|
||||
uint8_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref PCD_Speed/HCD_Speed
|
||||
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
|
||||
|
||||
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
|
||||
uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
|
||||
|
||||
uint32_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
|
||||
uint8_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
|
||||
|
||||
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
|
||||
uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
|
||||
uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
|
||||
|
||||
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
||||
uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
||||
|
||||
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||
uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||
|
||||
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
||||
uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
||||
|
||||
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||
uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||
|
||||
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||
uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||
|
||||
} USB_CfgTypeDef;
|
||||
|
||||
@ -179,8 +187,13 @@ typedef struct
|
||||
(HCD_DEVICE_SPEED_xxx) */
|
||||
|
||||
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
|
||||
uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */
|
||||
uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */
|
||||
uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */
|
||||
uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */
|
||||
|
||||
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
|
||||
uint8_t hub_port_nbr; /*!< USB HUB port number */
|
||||
uint8_t hub_addr; /*!< USB HUB address */
|
||||
|
||||
uint8_t ep_type; /*!< Endpoint Type.
|
||||
This parameter can be any value of @ref USB_LL_EP_Type */
|
||||
@ -193,7 +206,7 @@ typedef struct
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
||||
|
||||
uint32_t XferSize; /*!< OTG Channel transfer size. */
|
||||
uint32_t XferSize; /*!< OTG Channel transfer size. */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length. */
|
||||
|
||||
@ -208,6 +221,7 @@ typedef struct
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
||||
|
||||
uint32_t ErrCnt; /*!< Host channel error count. */
|
||||
uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */
|
||||
|
||||
USB_URBStateTypeDef urb_state; /*!< URB state.
|
||||
This parameter can be any value of @ref USB_URBStateTypeDef */
|
||||
@ -425,6 +439,12 @@ typedef USB_HCTypeDef USB_OTG_HCTypeDef;
|
||||
#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU
|
||||
|
||||
#define HC_MAX_PKT_CNT 256U
|
||||
#define ISO_SPLT_MPS 188U
|
||||
|
||||
#define HCSPLT_BEGIN 1U
|
||||
#define HCSPLT_MIDDLE 2U
|
||||
#define HCSPLT_END 3U
|
||||
#define HCSPLT_FULL 4U
|
||||
|
||||
#define TEST_J 1U
|
||||
#define TEST_K 2U
|
||||
@ -482,55 +502,55 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
|
||||
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
||||
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
||||
uint8_t ch_ep_num, uint16_t len, uint8_t dma);
|
||||
|
||||
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
||||
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
|
||||
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
||||
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
|
||||
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
|
||||
uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup);
|
||||
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
|
||||
uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
|
||||
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
|
||||
|
||||
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
|
||||
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
|
||||
HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
|
||||
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address, uint8_t speed,
|
||||
uint8_t ep_type, uint16_t mps);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
|
||||
USB_OTG_HCTypeDef *hc, uint8_t dma);
|
||||
|
||||
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
|
||||
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
|
||||
uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
|
||||
HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
|
||||
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
/**
|
||||
|
||||
@ -345,7 +345,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @param Ticks Frequency of Ticks (Hz)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
|
||||
Reference in New Issue
Block a user