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@ -4131,7 +4131,7 @@ typedef struct
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#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
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#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
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#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
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#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
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#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
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#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
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#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
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@ -6149,10 +6149,10 @@ typedef struct
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#define DCMI_CR_VSPOL_Pos (7U)
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#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
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#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
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#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
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#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
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#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
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#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
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#define DCMI_CR_FCRC_0 (0x00000100U)
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#define DCMI_CR_FCRC_1 (0x00000200U)
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#define DCMI_CR_EDM_0 (0x00000400U)
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#define DCMI_CR_EDM_1 (0x00000800U)
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#define DCMI_CR_CRE_Pos (12U)
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#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
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#define DCMI_CR_CRE DCMI_CR_CRE_Msk
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@ -6907,7 +6907,7 @@ typedef struct
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#define ETH_MACCR_SARC_Pos (28U)
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#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
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#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
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#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
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#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
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#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
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#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
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#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
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@ -6926,14 +6926,14 @@ typedef struct
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#define ETH_MACCR_IPG_Pos (24U)
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#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
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#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
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#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
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#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
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#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
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#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
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#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
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#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
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#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
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#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
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#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
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#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
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#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
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#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
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#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
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#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
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#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
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#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
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#define ETH_MACCR_GPSLCE_Pos (23U)
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#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
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#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
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@ -7044,7 +7044,7 @@ typedef struct
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#define ETH_MACPFR_PCF_Pos (6U)
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#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
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#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
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#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
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#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
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#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
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#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
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#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
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@ -7080,21 +7080,21 @@ typedef struct
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#define ETH_MACWTR_WTO_Pos (0U)
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#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
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#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
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#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
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#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
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#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
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#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
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#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
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#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
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#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
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#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
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#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
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#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
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#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
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#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
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#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
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#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
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#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
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#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
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#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
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#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
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#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
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#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
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#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
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#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
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#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
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#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
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#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
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#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
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#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
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#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
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#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
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#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
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/* Bit definition for Ethernet MAC Hash Table High Register */
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#define ETH_MACHTHR_HTH_Pos (0U)
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@ -7113,7 +7113,7 @@ typedef struct
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#define ETH_MACVTR_EIVLS_Pos (28U)
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#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
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#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
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#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
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#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
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#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
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#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
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#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
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@ -7138,7 +7138,7 @@ typedef struct
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#define ETH_MACVTR_EVLS_Pos (21U)
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#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
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#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
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#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
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#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
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#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
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#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
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#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
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@ -7194,7 +7194,7 @@ typedef struct
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#define ETH_MACVIR_VLC_Pos (16U)
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#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
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#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
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#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
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#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
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#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
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#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
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#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
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@ -7230,7 +7230,7 @@ typedef struct
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#define ETH_MACIVIR_VLC_Pos (16U)
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#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
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#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
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#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
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#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
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#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
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#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
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#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
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@ -7263,7 +7263,7 @@ typedef struct
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#define ETH_MACTFCR_PLT_Pos (4U)
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#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
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#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
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#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
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#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
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#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
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#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
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#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
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@ -7465,7 +7465,7 @@ typedef struct
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#define ETH_MACDR_TFCSTS_Pos (17U)
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#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
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#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
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#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
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#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
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#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
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#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
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#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
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@ -7489,7 +7489,7 @@ typedef struct
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#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
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#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
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#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
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#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
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#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
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#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
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#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
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#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
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@ -7646,7 +7646,7 @@ typedef struct
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#define ETH_MACMDIOAR_CR_Pos (8U)
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#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
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#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
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#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
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#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
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#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
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#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
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#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
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@ -7801,12 +7801,12 @@ typedef struct
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#define ETH_MACAHR_MBC_Pos (24U)
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#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
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#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
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#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
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#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
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#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
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#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
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#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
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#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
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#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
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#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
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#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
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#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
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#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
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#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
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#define ETH_MACAHR_MACAH_Pos (0U)
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#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
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#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
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@ -8304,14 +8304,14 @@ typedef struct
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#define ETH_MTLTQOMR_TTC_Pos (4U)
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#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
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#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
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#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
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#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
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#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
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#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
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#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
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#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
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#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
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#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
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#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
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#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
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#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
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#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
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#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
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#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
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#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
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#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
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#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8346,10 +8346,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8396,10 +8396,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8422,7 +8422,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8435,7 +8435,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8467,14 +8467,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8514,7 +8514,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8536,7 +8536,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8560,11 +8560,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8573,12 +8573,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8596,12 +8596,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -14593,7 +14593,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -14627,7 +14627,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -14649,7 +14649,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -14684,7 +14684,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -14706,7 +14706,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -14729,7 +14729,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -14749,7 +14749,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18136,10 +18136,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -18636,57 +18636,57 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -18704,56 +18704,56 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -18772,58 +18772,58 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -18841,55 +18841,55 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21464,7 +21464,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4132,7 +4132,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6150,10 +6150,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6908,7 +6908,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6927,14 +6927,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7045,7 +7045,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7081,21 +7081,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7114,7 +7114,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7139,7 +7139,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7195,7 +7195,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7231,7 +7231,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7264,7 +7264,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7466,7 +7466,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7490,7 +7490,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7647,7 +7647,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7802,12 +7802,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8305,14 +8305,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8347,10 +8347,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8397,10 +8397,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8423,7 +8423,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8436,7 +8436,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8468,14 +8468,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8515,7 +8515,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8537,7 +8537,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8561,11 +8561,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8574,12 +8574,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8597,12 +8597,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -14605,7 +14605,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -14639,7 +14639,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -14661,7 +14661,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -14696,7 +14696,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -14718,7 +14718,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -14741,7 +14741,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -14761,7 +14761,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18148,10 +18148,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -18648,57 +18648,57 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -18716,56 +18716,56 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -18784,58 +18784,58 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -18853,55 +18853,55 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21476,7 +21476,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4266,7 +4266,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6044,7 +6044,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -6095,7 +6095,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6403,10 +6403,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -7161,7 +7161,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -7180,14 +7180,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7298,7 +7298,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7334,21 +7334,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7367,7 +7367,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7392,7 +7392,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7448,7 +7448,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7484,7 +7484,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7517,7 +7517,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7719,7 +7719,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7743,7 +7743,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7900,7 +7900,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -8055,12 +8055,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8558,14 +8558,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8600,10 +8600,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8650,10 +8650,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8676,7 +8676,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8689,7 +8689,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8721,14 +8721,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8768,7 +8768,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8790,7 +8790,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8814,11 +8814,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8827,12 +8827,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8850,12 +8850,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -15044,7 +15044,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -15078,7 +15078,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -15100,7 +15100,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -15135,7 +15135,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -15157,7 +15157,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -15180,7 +15180,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -15200,7 +15200,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18623,10 +18623,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -19123,57 +19123,57 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19191,56 +19191,56 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19259,58 +19259,58 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19328,55 +19328,55 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21951,7 +21951,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4267,7 +4267,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6045,7 +6045,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -6096,7 +6096,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6404,10 +6404,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -7162,7 +7162,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -7181,14 +7181,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7299,7 +7299,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7335,21 +7335,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7368,7 +7368,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7393,7 +7393,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7449,7 +7449,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7485,7 +7485,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7518,7 +7518,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7720,7 +7720,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7744,7 +7744,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7901,7 +7901,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -8056,12 +8056,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8559,14 +8559,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8601,10 +8601,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8651,10 +8651,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8677,7 +8677,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8690,7 +8690,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8722,14 +8722,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8769,7 +8769,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8791,7 +8791,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8815,11 +8815,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8828,12 +8828,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8851,12 +8851,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -15056,7 +15056,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -15090,7 +15090,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -15112,7 +15112,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -15147,7 +15147,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -15169,7 +15169,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -15192,7 +15192,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -15212,7 +15212,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18635,10 +18635,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -19135,57 +19135,57 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19203,56 +19203,56 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19271,58 +19271,58 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19340,55 +19340,55 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21963,7 +21963,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4266,7 +4266,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6044,7 +6044,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -6095,7 +6095,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6403,10 +6403,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -7161,7 +7161,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -7180,14 +7180,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7298,7 +7298,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7334,21 +7334,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7367,7 +7367,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7392,7 +7392,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7448,7 +7448,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7484,7 +7484,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7517,7 +7517,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7719,7 +7719,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7743,7 +7743,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7900,7 +7900,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -8055,12 +8055,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8558,14 +8558,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8600,10 +8600,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8650,10 +8650,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8676,7 +8676,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8689,7 +8689,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8721,14 +8721,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8768,7 +8768,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8790,7 +8790,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8814,11 +8814,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8827,12 +8827,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8850,12 +8850,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -15044,7 +15044,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -15078,7 +15078,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -15100,7 +15100,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -15135,7 +15135,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -15157,7 +15157,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -15180,7 +15180,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -15200,7 +15200,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18623,10 +18623,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -19123,57 +19123,57 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19191,56 +19191,56 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19259,58 +19259,58 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19328,55 +19328,55 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21951,7 +21951,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4267,7 +4267,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6045,7 +6045,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -6096,7 +6096,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6404,10 +6404,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -7162,7 +7162,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -7181,14 +7181,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7299,7 +7299,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7335,21 +7335,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7368,7 +7368,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7393,7 +7393,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7449,7 +7449,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7485,7 +7485,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7518,7 +7518,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7720,7 +7720,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7744,7 +7744,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7901,7 +7901,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -8056,12 +8056,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8559,14 +8559,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8601,10 +8601,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8651,10 +8651,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8677,7 +8677,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8690,7 +8690,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8722,14 +8722,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8769,7 +8769,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8791,7 +8791,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8815,11 +8815,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8828,12 +8828,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8851,12 +8851,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -15056,7 +15056,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -15090,7 +15090,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -15112,7 +15112,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -15147,7 +15147,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -15169,7 +15169,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -15192,7 +15192,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -15212,7 +15212,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18635,10 +18635,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -19135,57 +19135,57 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19203,56 +19203,56 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19271,58 +19271,58 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19340,55 +19340,55 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21963,7 +21963,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -3928,7 +3928,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5885,10 +5885,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6643,7 +6643,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6662,14 +6662,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -6780,7 +6780,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -6816,21 +6816,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -6849,7 +6849,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -6874,7 +6874,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -6930,7 +6930,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -6966,7 +6966,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -6999,7 +6999,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7201,7 +7201,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7225,7 +7225,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7382,7 +7382,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7537,12 +7537,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8040,14 +8040,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8082,10 +8082,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8132,10 +8132,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8158,7 +8158,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8171,7 +8171,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8203,14 +8203,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8250,7 +8250,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8272,7 +8272,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8296,11 +8296,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8309,12 +8309,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8332,12 +8332,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -13939,7 +13939,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -13973,7 +13973,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -13995,7 +13995,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -14030,7 +14030,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -14052,7 +14052,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -14075,7 +14075,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -14095,7 +14095,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -17426,10 +17426,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -17875,12 +17875,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -18155,61 +18156,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -18227,60 +18228,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -18299,62 +18300,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -18372,59 +18373,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -20392,7 +20393,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4023,7 +4023,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5980,10 +5980,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6738,7 +6738,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6757,14 +6757,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -6875,7 +6875,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -6911,21 +6911,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -6944,7 +6944,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -6969,7 +6969,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7025,7 +7025,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7061,7 +7061,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7094,7 +7094,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7296,7 +7296,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7320,7 +7320,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7477,7 +7477,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7632,12 +7632,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8135,14 +8135,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8177,10 +8177,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8227,10 +8227,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8253,7 +8253,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8266,7 +8266,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8298,14 +8298,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8345,7 +8345,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8367,7 +8367,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8391,11 +8391,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8404,12 +8404,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8427,12 +8427,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -14569,7 +14569,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -14603,7 +14603,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -14625,7 +14625,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -14660,7 +14660,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -14682,7 +14682,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -14705,7 +14705,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -14725,7 +14725,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18074,10 +18074,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -18523,12 +18523,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -18803,61 +18804,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -18875,60 +18876,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -18947,62 +18948,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19020,59 +19021,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21040,7 +21041,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4130,7 +4130,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6087,10 +6087,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6845,7 +6845,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6864,14 +6864,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -6982,7 +6982,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7018,21 +7018,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7051,7 +7051,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7076,7 +7076,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7132,7 +7132,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7168,7 +7168,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7201,7 +7201,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7403,7 +7403,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7427,7 +7427,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7584,7 +7584,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7739,12 +7739,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8242,14 +8242,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8284,10 +8284,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8334,10 +8334,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8360,7 +8360,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8373,7 +8373,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8405,14 +8405,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8452,7 +8452,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8474,7 +8474,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8498,11 +8498,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8511,12 +8511,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8534,12 +8534,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -15145,7 +15145,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -15179,7 +15179,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -15201,7 +15201,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -15236,7 +15236,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -15258,7 +15258,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -15281,7 +15281,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -15301,7 +15301,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18709,10 +18709,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -19158,12 +19158,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -19438,61 +19439,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19510,60 +19511,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19582,62 +19583,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19655,59 +19656,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_CM4L_Pos (0U)
|
||||
@ -21702,7 +21703,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4130,7 +4130,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6087,10 +6087,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6845,7 +6845,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6864,14 +6864,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -6982,7 +6982,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7018,21 +7018,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7051,7 +7051,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7076,7 +7076,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7132,7 +7132,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7168,7 +7168,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7201,7 +7201,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7403,7 +7403,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7427,7 +7427,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7584,7 +7584,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7739,12 +7739,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8242,14 +8242,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8284,10 +8284,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8334,10 +8334,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8360,7 +8360,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8373,7 +8373,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8405,14 +8405,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8452,7 +8452,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8474,7 +8474,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8498,11 +8498,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8511,12 +8511,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8534,12 +8534,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -15145,7 +15145,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -15179,7 +15179,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -15201,7 +15201,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -15236,7 +15236,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -15258,7 +15258,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -15281,7 +15281,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -15301,7 +15301,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18709,10 +18709,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -19158,12 +19158,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -19438,61 +19439,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19510,60 +19511,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19582,62 +19583,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19655,59 +19656,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_CM4L_Pos (0U)
|
||||
@ -21702,7 +21703,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4213,7 +4213,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6170,10 +6170,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6928,7 +6928,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6947,14 +6947,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7065,7 +7065,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7101,21 +7101,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7134,7 +7134,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7159,7 +7159,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7215,7 +7215,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7251,7 +7251,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7284,7 +7284,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7486,7 +7486,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7510,7 +7510,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7667,7 +7667,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7822,12 +7822,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8325,14 +8325,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8367,10 +8367,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8417,10 +8417,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8443,7 +8443,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8456,7 +8456,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8488,14 +8488,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8535,7 +8535,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8557,7 +8557,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8581,11 +8581,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8594,12 +8594,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8617,12 +8617,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -11024,13 +11024,13 @@ typedef struct
|
||||
#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
|
||||
|
||||
/******************* Bit definition for DSI_TDCR register ***************/
|
||||
#define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCR_3DM0 ((uint32_t)0x00000001U)
|
||||
#define DSI_TDCR_3DM1 ((uint32_t)0x00000002U)
|
||||
#define DSI_TDCR_3DM (0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCR_3DM0 (0x00000001U)
|
||||
#define DSI_TDCR_3DM1 (0x00000002U)
|
||||
|
||||
#define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCR_3DF0 ((uint32_t)0x00000004U)
|
||||
#define DSI_TDCR_3DF1 ((uint32_t)0x00000008U)
|
||||
#define DSI_TDCR_3DF (0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCR_3DF0 (0x00000004U)
|
||||
#define DSI_TDCR_3DF1 (0x00000008U)
|
||||
|
||||
#define DSI_TDCR_SVS_Pos (4U)
|
||||
#define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
|
||||
@ -12200,13 +12200,13 @@ typedef struct
|
||||
#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
|
||||
|
||||
/******************* Bit definition for DSI_TDCCR register **************/
|
||||
#define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U)
|
||||
#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U)
|
||||
#define DSI_TDCCR_3DM (0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCCR_3DM0 (0x00000001U)
|
||||
#define DSI_TDCCR_3DM1 (0x00000002U)
|
||||
|
||||
#define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U)
|
||||
#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U)
|
||||
#define DSI_TDCCR_3DF (0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCCR_3DF0 (0x00000004U)
|
||||
#define DSI_TDCCR_3DF1 (0x00000008U)
|
||||
|
||||
#define DSI_TDCCR_SVS_Pos (4U)
|
||||
#define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
|
||||
@ -18302,7 +18302,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -18336,7 +18336,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -18358,7 +18358,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -18393,7 +18393,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -18415,7 +18415,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -18438,7 +18438,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -18458,7 +18458,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -21882,10 +21882,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -22331,12 +22331,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -22611,61 +22612,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -22683,60 +22684,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -22755,62 +22756,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -22828,59 +22829,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_CM4L_Pos (0U)
|
||||
@ -24875,7 +24876,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4213,7 +4213,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6170,10 +6170,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6928,7 +6928,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6947,14 +6947,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7065,7 +7065,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7101,21 +7101,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7134,7 +7134,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7159,7 +7159,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7215,7 +7215,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7251,7 +7251,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7284,7 +7284,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7486,7 +7486,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7510,7 +7510,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7667,7 +7667,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7822,12 +7822,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8325,14 +8325,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8367,10 +8367,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8417,10 +8417,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8443,7 +8443,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8456,7 +8456,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8488,14 +8488,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8535,7 +8535,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8557,7 +8557,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8581,11 +8581,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8594,12 +8594,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8617,12 +8617,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -11024,13 +11024,13 @@ typedef struct
|
||||
#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
|
||||
|
||||
/******************* Bit definition for DSI_TDCR register ***************/
|
||||
#define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCR_3DM0 ((uint32_t)0x00000001U)
|
||||
#define DSI_TDCR_3DM1 ((uint32_t)0x00000002U)
|
||||
#define DSI_TDCR_3DM (0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCR_3DM0 (0x00000001U)
|
||||
#define DSI_TDCR_3DM1 (0x00000002U)
|
||||
|
||||
#define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCR_3DF0 ((uint32_t)0x00000004U)
|
||||
#define DSI_TDCR_3DF1 ((uint32_t)0x00000008U)
|
||||
#define DSI_TDCR_3DF (0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCR_3DF0 (0x00000004U)
|
||||
#define DSI_TDCR_3DF1 (0x00000008U)
|
||||
|
||||
#define DSI_TDCR_SVS_Pos (4U)
|
||||
#define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
|
||||
@ -12200,13 +12200,13 @@ typedef struct
|
||||
#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
|
||||
|
||||
/******************* Bit definition for DSI_TDCCR register **************/
|
||||
#define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U)
|
||||
#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U)
|
||||
#define DSI_TDCCR_3DM (0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCCR_3DM0 (0x00000001U)
|
||||
#define DSI_TDCCR_3DM1 (0x00000002U)
|
||||
|
||||
#define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U)
|
||||
#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U)
|
||||
#define DSI_TDCCR_3DF (0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCCR_3DF0 (0x00000004U)
|
||||
#define DSI_TDCCR_3DF1 (0x00000008U)
|
||||
|
||||
#define DSI_TDCCR_SVS_Pos (4U)
|
||||
#define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
|
||||
@ -18302,7 +18302,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -18336,7 +18336,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -18358,7 +18358,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -18393,7 +18393,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -18415,7 +18415,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -18438,7 +18438,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -18458,7 +18458,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -21882,10 +21882,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -22331,12 +22331,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -22611,61 +22612,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -22683,60 +22684,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -22755,62 +22756,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -22828,59 +22829,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_CM4L_Pos (0U)
|
||||
@ -24875,7 +24876,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4099,7 +4099,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5814,7 +5814,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -5865,7 +5865,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6173,10 +6173,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6931,7 +6931,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6950,14 +6950,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7068,7 +7068,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7104,21 +7104,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7137,7 +7137,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7162,7 +7162,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7218,7 +7218,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7254,7 +7254,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7287,7 +7287,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7489,7 +7489,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7513,7 +7513,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7670,7 +7670,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7825,12 +7825,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8328,14 +8328,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8370,10 +8370,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8420,10 +8420,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8446,7 +8446,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8459,7 +8459,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8491,14 +8491,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8538,7 +8538,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8560,7 +8560,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8584,11 +8584,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8597,12 +8597,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8620,12 +8620,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -14832,7 +14832,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -14866,7 +14866,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -14888,7 +14888,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -14923,7 +14923,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -14945,7 +14945,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -14968,7 +14968,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -14988,7 +14988,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18355,10 +18355,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -18804,12 +18804,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -19084,61 +19085,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19156,60 +19157,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19228,62 +19229,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19301,59 +19302,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21321,7 +21322,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4099,7 +4099,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5814,7 +5814,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -5865,7 +5865,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6173,10 +6173,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -6931,7 +6931,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -6950,14 +6950,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7068,7 +7068,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7104,21 +7104,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7137,7 +7137,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7162,7 +7162,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7218,7 +7218,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7254,7 +7254,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7287,7 +7287,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7489,7 +7489,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7513,7 +7513,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7670,7 +7670,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7825,12 +7825,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8328,14 +8328,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8370,10 +8370,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8420,10 +8420,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8446,7 +8446,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8459,7 +8459,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8491,14 +8491,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8538,7 +8538,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8560,7 +8560,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8584,11 +8584,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8597,12 +8597,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8620,12 +8620,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -14838,7 +14838,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -14872,7 +14872,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -14894,7 +14894,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -14929,7 +14929,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -14951,7 +14951,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -14974,7 +14974,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -14994,7 +14994,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18361,10 +18361,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -18810,12 +18810,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -19090,61 +19091,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19162,60 +19163,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19234,62 +19235,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19307,59 +19308,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -21327,7 +21328,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4206,7 +4206,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5921,7 +5921,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -5972,7 +5972,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6280,10 +6280,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -7038,7 +7038,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -7057,14 +7057,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7175,7 +7175,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7211,21 +7211,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7244,7 +7244,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7269,7 +7269,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7325,7 +7325,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7361,7 +7361,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7394,7 +7394,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7596,7 +7596,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7620,7 +7620,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7777,7 +7777,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -7932,12 +7932,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8435,14 +8435,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8477,10 +8477,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8527,10 +8527,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8553,7 +8553,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8566,7 +8566,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8598,14 +8598,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8645,7 +8645,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8667,7 +8667,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8691,11 +8691,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8704,12 +8704,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8727,12 +8727,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -15414,7 +15414,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -15448,7 +15448,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -15470,7 +15470,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -15505,7 +15505,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -15527,7 +15527,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -15550,7 +15550,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -15570,7 +15570,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -18996,10 +18996,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -19445,12 +19445,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -19725,61 +19726,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -19797,60 +19798,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -19869,62 +19870,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -19942,59 +19943,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_CM4L_Pos (0U)
|
||||
@ -21989,7 +21990,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4289,7 +4289,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -6004,7 +6004,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -6055,7 +6055,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6363,10 +6363,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -7121,7 +7121,7 @@ typedef struct
|
||||
#define ETH_MACCR_SARC_Pos (28U)
|
||||
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
|
||||
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
|
||||
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
|
||||
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
|
||||
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
|
||||
@ -7140,14 +7140,14 @@ typedef struct
|
||||
#define ETH_MACCR_IPG_Pos (24U)
|
||||
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
|
||||
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
|
||||
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
|
||||
#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
|
||||
#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
|
||||
#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
|
||||
#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
|
||||
#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
|
||||
#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
|
||||
#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
|
||||
#define ETH_MACCR_GPSLCE_Pos (23U)
|
||||
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
|
||||
@ -7258,7 +7258,7 @@ typedef struct
|
||||
#define ETH_MACPFR_PCF_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
|
||||
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
|
||||
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
|
||||
@ -7294,21 +7294,21 @@ typedef struct
|
||||
#define ETH_MACWTR_WTO_Pos (0U)
|
||||
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
|
||||
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
|
||||
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
|
||||
#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
|
||||
#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
|
||||
#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
|
||||
#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
|
||||
#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
|
||||
#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
|
||||
#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
|
||||
#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
|
||||
#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
|
||||
#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
|
||||
#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
|
||||
#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
|
||||
#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
|
||||
#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
|
||||
#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
|
||||
|
||||
/* Bit definition for Ethernet MAC Hash Table High Register */
|
||||
#define ETH_MACHTHR_HTH_Pos (0U)
|
||||
@ -7327,7 +7327,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EIVLS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
|
||||
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
|
||||
#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7352,7 +7352,7 @@ typedef struct
|
||||
#define ETH_MACVTR_EVLS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
|
||||
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
|
||||
#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
|
||||
@ -7408,7 +7408,7 @@ typedef struct
|
||||
#define ETH_MACVIR_VLC_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7444,7 +7444,7 @@ typedef struct
|
||||
#define ETH_MACIVIR_VLC_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
|
||||
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
|
||||
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
|
||||
@ -7477,7 +7477,7 @@ typedef struct
|
||||
#define ETH_MACTFCR_PLT_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
|
||||
#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
|
||||
@ -7679,7 +7679,7 @@ typedef struct
|
||||
#define ETH_MACDR_TFCSTS_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
|
||||
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
|
||||
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
|
||||
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
|
||||
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
|
||||
@ -7703,7 +7703,7 @@ typedef struct
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
|
||||
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
|
||||
@ -7860,7 +7860,7 @@ typedef struct
|
||||
#define ETH_MACMDIOAR_CR_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
|
||||
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
|
||||
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
|
||||
@ -8015,12 +8015,12 @@ typedef struct
|
||||
#define ETH_MACAHR_MBC_Pos (24U)
|
||||
#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
|
||||
#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
|
||||
#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
|
||||
#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
|
||||
#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
|
||||
#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
|
||||
#define ETH_MACAHR_MACAH_Pos (0U)
|
||||
#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
|
||||
#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
|
||||
@ -8518,14 +8518,14 @@ typedef struct
|
||||
#define ETH_MTLTQOMR_TTC_Pos (4U)
|
||||
#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
|
||||
#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
|
||||
#define ETH_MTLTQOMR_TSF_Pos (1U)
|
||||
#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
|
||||
@ -8560,10 +8560,10 @@ typedef struct
|
||||
#define ETH_MTLTQDR_TRCSTS_Pos (1U)
|
||||
#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
|
||||
#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
|
||||
#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
|
||||
#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
|
||||
#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
|
||||
@ -8610,10 +8610,10 @@ typedef struct
|
||||
#define ETH_MTLRQOMR_RTC_Pos (0U)
|
||||
#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
|
||||
#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
|
||||
#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
|
||||
|
||||
/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
|
||||
#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
|
||||
@ -8636,7 +8636,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RXQSTS_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
|
||||
#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
|
||||
#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
|
||||
@ -8649,7 +8649,7 @@ typedef struct
|
||||
#define ETH_MTLRQDR_RRCSTS_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
|
||||
#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
|
||||
#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
|
||||
@ -8681,14 +8681,14 @@ typedef struct
|
||||
#define ETH_DMAMR_PR_Pos (12U)
|
||||
#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
|
||||
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
|
||||
#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
|
||||
#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
|
||||
#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
|
||||
#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
|
||||
#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
|
||||
#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
|
||||
#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
|
||||
#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
|
||||
#define ETH_DMAMR_TXPR_Pos (11U)
|
||||
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
|
||||
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
|
||||
@ -8728,7 +8728,7 @@ typedef struct
|
||||
#define ETH_DMADSR_TPS_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
|
||||
#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
|
||||
#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
|
||||
#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
|
||||
@ -8750,7 +8750,7 @@ typedef struct
|
||||
#define ETH_DMADSR_RPS_Pos (8U)
|
||||
#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
|
||||
#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
|
||||
#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
|
||||
#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
|
||||
#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
|
||||
@ -8774,11 +8774,11 @@ typedef struct
|
||||
#define ETH_DMACCR_DSL_Pos (18U)
|
||||
#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
|
||||
#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
|
||||
#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
|
||||
#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
|
||||
#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
|
||||
#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
|
||||
#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_DSL_0BIT (0U)
|
||||
#define ETH_DMACCR_DSL_32BIT (0x00040000U)
|
||||
#define ETH_DMACCR_DSL_64BIT (0x00080000U)
|
||||
#define ETH_DMACCR_DSL_128BIT (0x00100000U)
|
||||
#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
|
||||
#define ETH_DMACCR_MSS_Pos (0U)
|
||||
#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
|
||||
#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
|
||||
@ -8787,12 +8787,12 @@ typedef struct
|
||||
#define ETH_DMACTCR_TPBL_Pos (16U)
|
||||
#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
|
||||
#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
|
||||
#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
|
||||
#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
|
||||
#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
|
||||
#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
|
||||
#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
|
||||
#define ETH_DMACTCR_TSE_Pos (12U)
|
||||
#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
|
||||
@ -8810,12 +8810,12 @@ typedef struct
|
||||
#define ETH_DMACRCR_RPBL_Pos (16U)
|
||||
#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
|
||||
#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
|
||||
#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
|
||||
#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
|
||||
#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
|
||||
#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
|
||||
#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
|
||||
#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
|
||||
#define ETH_DMACRCR_RBSZ_Pos (1U)
|
||||
#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
|
||||
#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
|
||||
@ -11217,13 +11217,13 @@ typedef struct
|
||||
#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
|
||||
|
||||
/******************* Bit definition for DSI_TDCR register ***************/
|
||||
#define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCR_3DM0 ((uint32_t)0x00000001U)
|
||||
#define DSI_TDCR_3DM1 ((uint32_t)0x00000002U)
|
||||
#define DSI_TDCR_3DM (0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCR_3DM0 (0x00000001U)
|
||||
#define DSI_TDCR_3DM1 (0x00000002U)
|
||||
|
||||
#define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCR_3DF0 ((uint32_t)0x00000004U)
|
||||
#define DSI_TDCR_3DF1 ((uint32_t)0x00000008U)
|
||||
#define DSI_TDCR_3DF (0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCR_3DF0 (0x00000004U)
|
||||
#define DSI_TDCR_3DF1 (0x00000008U)
|
||||
|
||||
#define DSI_TDCR_SVS_Pos (4U)
|
||||
#define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
|
||||
@ -12393,13 +12393,13 @@ typedef struct
|
||||
#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
|
||||
|
||||
/******************* Bit definition for DSI_TDCCR register **************/
|
||||
#define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U)
|
||||
#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U)
|
||||
#define DSI_TDCCR_3DM (0x00000003U) /*!< 3D Mode */
|
||||
#define DSI_TDCCR_3DM0 (0x00000001U)
|
||||
#define DSI_TDCCR_3DM1 (0x00000002U)
|
||||
|
||||
#define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U)
|
||||
#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U)
|
||||
#define DSI_TDCCR_3DF (0x0000000CU) /*!< 3D Format */
|
||||
#define DSI_TDCCR_3DF0 (0x00000004U)
|
||||
#define DSI_TDCCR_3DF1 (0x00000008U)
|
||||
|
||||
#define DSI_TDCCR_SVS_Pos (4U)
|
||||
#define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
|
||||
@ -18571,7 +18571,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -18605,7 +18605,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -18627,7 +18627,7 @@ typedef struct
|
||||
#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -18662,7 +18662,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -18684,7 +18684,7 @@ typedef struct
|
||||
#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -18707,7 +18707,7 @@ typedef struct
|
||||
#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -18727,7 +18727,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -22169,10 +22169,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -22618,12 +22618,13 @@ typedef struct
|
||||
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
|
||||
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
|
||||
#define QUADSPI_CR_FTHRES_Pos (8U)
|
||||
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
|
||||
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
|
||||
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
|
||||
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
|
||||
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
|
||||
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
|
||||
#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
|
||||
#define QUADSPI_CR_TEIE_Pos (16U)
|
||||
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
|
||||
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
||||
@ -22898,61 +22899,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -22970,60 +22971,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -23042,62 +23043,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -23115,59 +23116,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_CM4L_Pos (0U)
|
||||
@ -25162,7 +25163,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -3906,7 +3906,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5863,10 +5863,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -12753,7 +12753,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -12787,7 +12787,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -12809,7 +12809,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -12844,7 +12844,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -12866,7 +12866,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -12889,7 +12889,7 @@ typedef struct
|
||||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -12909,7 +12909,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -16578,10 +16578,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -17061,61 +17061,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -17133,60 +17133,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -17205,62 +17205,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -17278,59 +17278,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -19797,7 +19797,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -3907,7 +3907,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5864,10 +5864,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -12765,7 +12765,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -12799,7 +12799,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -12821,7 +12821,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -12856,7 +12856,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -12878,7 +12878,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -12901,7 +12901,7 @@ typedef struct
|
||||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -12921,7 +12921,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -16590,10 +16590,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -17073,61 +17073,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -17145,60 +17145,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -17217,62 +17217,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -17290,59 +17290,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -19809,7 +19809,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4041,7 +4041,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5758,7 +5758,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -5809,7 +5809,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6117,10 +6117,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -13197,7 +13197,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -13231,7 +13231,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -13253,7 +13253,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -13288,7 +13288,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -13310,7 +13310,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -13333,7 +13333,7 @@ typedef struct
|
||||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -13353,7 +13353,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -17058,10 +17058,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -17541,61 +17541,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -17613,60 +17613,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -17685,62 +17685,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -17758,59 +17758,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -20277,7 +20277,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4042,7 +4042,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5759,7 +5759,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -5810,7 +5810,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6118,10 +6118,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -13209,7 +13209,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -13243,7 +13243,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -13265,7 +13265,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -13300,7 +13300,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -13322,7 +13322,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -13345,7 +13345,7 @@ typedef struct
|
||||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -13365,7 +13365,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -17070,10 +17070,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -17553,61 +17553,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -17625,60 +17625,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -17697,62 +17697,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -17770,59 +17770,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -20289,7 +20289,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4041,7 +4041,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5758,7 +5758,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -5809,7 +5809,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6117,10 +6117,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -13204,7 +13204,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -13238,7 +13238,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -13260,7 +13260,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -13295,7 +13295,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -13317,7 +13317,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -13340,7 +13340,7 @@ typedef struct
|
||||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -13360,7 +13360,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -17065,10 +17065,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -17548,61 +17548,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -17620,60 +17620,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -17692,62 +17692,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -17765,59 +17765,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -20284,7 +20284,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -4042,7 +4042,7 @@ typedef struct
|
||||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
@ -5759,7 +5759,7 @@ typedef struct
|
||||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
@ -5810,7 +5810,7 @@ typedef struct
|
||||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
@ -6118,10 +6118,10 @@ typedef struct
|
||||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
@ -13216,7 +13216,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
@ -13250,7 +13250,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
@ -13272,7 +13272,7 @@ typedef struct
|
||||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
@ -13307,7 +13307,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
@ -13329,7 +13329,7 @@ typedef struct
|
||||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
@ -13352,7 +13352,7 @@ typedef struct
|
||||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
@ -13372,7 +13372,7 @@ typedef struct
|
||||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
@ -17077,10 +17077,10 @@ typedef struct
|
||||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@ -17560,61 +17560,61 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
@ -17632,60 +17632,60 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
@ -17704,62 +17704,62 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
@ -17777,59 +17777,59 @@ typedef struct
|
||||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
@ -20296,7 +20296,7 @@ typedef struct
|
||||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
||||
@ -102,11 +102,11 @@
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.10.2
|
||||
* @brief CMSIS Device version number V1.10.3
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
||||
@ -236,8 +236,8 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrup
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrup
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrupt
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
|
||||
@ -236,8 +236,8 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrup
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrup
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrupt
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
|
||||
@ -236,8 +236,8 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrup
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrup
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrupt
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
|
||||
@ -236,8 +236,8 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrup
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrup
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrupt
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
|
||||
@ -236,8 +236,8 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrup
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrup
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrupt
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
|
||||
@ -236,8 +236,8 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrup
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrup
|
||||
DCD TIM23_IRQHandler ; TIM23 global interrupt
|
||||
DCD TIM24_IRQHandler ; TIM24 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
||||
;/******************************************************************************
|
||||
; * @file startup_stm32h7a3xx.s
|
||||
; * @author MCD Application Team
|
||||
; * @brief STM32H7B3xx devices vector table for EWARM toolchain.
|
||||
;/******************************************************************************
|
||||
;* @file startup_stm32h7a3xx.s
|
||||
;* @author MCD Application Team
|
||||
;* @brief STM32H7B3xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;/******************************************************************************
|
||||
; * @file startup_stm32h7a3xxq.s
|
||||
; * @author MCD Application Team
|
||||
; * @brief STM32H7B3xx devices vector table for EWARM toolchain.
|
||||
;/******************************************************************************
|
||||
;* @file startup_stm32h7a3xxq.s
|
||||
;* @author MCD Application Team
|
||||
;* @brief STM32H7B3xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;/******************************************************************************
|
||||
; * @file startup_stm32h7b0xx.s
|
||||
; * @author MCD Application Team
|
||||
; * @brief STM32H7B0xx devices vector table for EWARM toolchain.
|
||||
;/******************************************************************************
|
||||
;* @file startup_stm32h7b0xx.s
|
||||
;* @author MCD Application Team
|
||||
;* @brief STM32H7B0xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;/******************************************************************************
|
||||
; * @file startup_stm32h7b0xxq.s
|
||||
; * @author MCD Application Team
|
||||
; * @brief STM32H7B0xx devices vector table for EWARM toolchain.
|
||||
;/******************************************************************************
|
||||
;* @file startup_stm32h7b0xxq.s
|
||||
;* @author MCD Application Team
|
||||
;* @brief STM32H7B0xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;/******************************************************************************
|
||||
; * @file startup_stm32h7b3xx.s
|
||||
; * @author MCD Application Team
|
||||
; * @brief STM32H7B3xx devices vector table for EWARM toolchain.
|
||||
;/******************************************************************************
|
||||
;* @file startup_stm32h7b3xx.s
|
||||
;* @author MCD Application Team
|
||||
;* @brief STM32H7B3xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;/******************************************************************************
|
||||
; * @file startup_stm32h7b3xxq.s
|
||||
; * @author MCD Application Team
|
||||
; * @brief STM32H7B3xx devices vector table for EWARM toolchain.
|
||||
;/******************************************************************************
|
||||
;* @file startup_stm32h7b3xxq.s
|
||||
;* @author MCD Application Team
|
||||
;* @brief STM32H7B3xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
|
||||
@ -94,14 +94,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#else
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
@ -109,14 +109,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#endif /* DUAL_CORE && CORE_CM4 */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
@ -94,14 +94,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#elif defined(CORE_CM7)
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
@ -109,14 +109,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#else
|
||||
#error Please #define CORE_CM4 or CORE_CM7
|
||||
|
||||
@ -97,14 +97,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#elif defined(CORE_CM7)
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
@ -112,14 +112,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#else
|
||||
#error Please #define CORE_CM4 or CORE_CM7
|
||||
|
||||
@ -97,14 +97,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#elif defined(CORE_CM7)
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
@ -112,14 +112,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x300. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#else
|
||||
#error Please #define CORE_CM4 or CORE_CM7
|
||||
|
||||
@ -95,14 +95,14 @@
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
/******************************************************************************/
|
||||
|
||||
Reference in New Issue
Block a user