874 lines
32 KiB
C
874 lines
32 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_hal_pwr.c
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* @author MCD Application Team
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* @brief PWR HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Power Controller (PWR) peripheral:
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* + Initialization and de-initialization functions.
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* + Peripheral Control functions.
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* + Interrupt Handling functions.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### PWR peripheral overview #####
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==============================================================================
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[..]
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(#) The Power control (PWR) provides an overview of the supply architecture
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for the different power domains and of the supply configuration
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controller.
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In the H7 family, the number of power domains is different between
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device lines. This difference is due to characteristics of each device.
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(#) Domain architecture overview for the different H7 lines:
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(+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
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These devices have 3 power domains (D1, D2 and D3).
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The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
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peripherals. The D2 domain contains peripherals and a CPU
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(Cortex-M4). The D3 domain contains the system control, I/O logic
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and low-power peripherals.
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(+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753
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devices have 3 power domains (D1, D2 and D3).
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The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
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peripherals. The D2 domain contains peripherals. The D3 domains
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contains the system control, I/O logic and low-power peripherals.
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(+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD).
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The core domain (CD) contains a CPU (Cortex-M7), a Flash
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memory and peripherals. The SmartRun domain contains the system
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control, I/O logic and low-power peripherals.
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(#) Every entity have low power mode as described below :
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(#) The CPU low power modes are :
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(+) CPU CRUN.
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(+) CPU CSLEEP.
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(+) CPU CSTOP.
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(#) The domain low power modes are :
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(+) DRUN.
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(+) DSTOP.
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(+) DSTANDBY.
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(#) The SYSTEM low power modes are :
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(+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
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Standby. In Run* mode, the performance is limited and the
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system supply configuration shall be programmed. The system
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enters Run mode only when the ACTVOSRDY bit in PWR control
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status register 1 (PWR_CSR1) is set to 1.
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(+) RUN.
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(+) STOP.
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(+) STANDBY.
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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(#) Power management peripheral is active by default at startup level in
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STM32h7xx lines.
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(#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
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to enable/disable access to the backup domain (RTC registers, RTC backup
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data registers and backup SRAM).
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(#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
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mode and voltage threshold) in order to set up the Power Voltage Detector,
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then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start
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and stop the PVD detection.
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(+) PVD level could be one of the following values :
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(++) 1V95
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(++) 2V1
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(++) 2V25
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(++) 2V4
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(++) 2V55
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(++) 2V7
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(++) 2V85
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(++) External voltage level
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(#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
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with the right parameter to configure the wake up pin polarity (Low or
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High) and to enable and disable it.
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(#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
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mode. Wake-up from SLEEP mode could be following to an event or an
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interrupt according to low power mode intrinsic request called (__WFI()
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or __WFE()).
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Please ensure to clear all CPU pending events by calling
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HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
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in SLEEP mode with __WFE() entry.
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(#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
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mode for single core devices. For dual core devices, this API will enter
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the domain (containing Cortex-Mx that executing this function) in DSTOP
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mode. According to the used parameter, user could select the regulator to
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be kept actif in low power mode and wake-up event type.
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Please ensure to clear all CPU pending events by calling
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HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
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in CSTOP mode with __WFE() entry.
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(#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
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STANDBY mode for single core devices. For dual core devices, this API
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will enter the domain (containing Cortex-Mx that executing this function)
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in DSTANDBY mode.
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(#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
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enable and disable the Cortex-Mx re-entring in SLEEP mode after an
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interruption handling is over.
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(#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
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to configure the Cortex-Mx to wake-up after any pending event / interrupt
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even if it's disabled or has insufficient priority to cause exception
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entry.
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(#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
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request.
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*** PWR HAL driver macros list ***
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=============================================
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[..]
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Below the list of most used macros in PWR HAL driver.
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(+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
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regulator output voltage.
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(+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
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(+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
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@endverbatim
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal.h"
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/** @addtogroup STM32H7xx_HAL_Driver
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* @{
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*/
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/** @defgroup PWR PWR
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* @brief PWR HAL module driver
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* @{
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*/
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#ifdef HAL_PWR_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @addtogroup PWR_Private_Constants PWR Private Constants
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* @{
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*/
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/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
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* @{
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*/
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#if !defined (DUAL_CORE)
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#define PVD_MODE_IT (0x00010000U)
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#define PVD_MODE_EVT (0x00020000U)
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#endif /* !defined (DUAL_CORE) */
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#define PVD_RISING_EDGE (0x00000001U)
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#define PVD_FALLING_EDGE (0x00000002U)
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#define PVD_RISING_FALLING_EDGE (0x00000003U)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup PWR_Exported_Functions PWR Exported Functions
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* @{
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*/
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/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
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* @brief Initialization and De-Initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and De-Initialization Functions #####
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===============================================================================
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[..]
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This section provides functions allowing to deinitialize power peripheral.
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[..]
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After system reset, the backup domain (RTC registers, RTC backup data
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registers and backup SRAM) is protected against possible unwanted write
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accesses.
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The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
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domain.
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The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
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domain.
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitialize the HAL PWR peripheral registers to their default reset
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* values.
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* @note This functionality is not available in this product.
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* The prototype is kept just to maintain compatibility with other
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* products.
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* @retval None.
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*/
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void HAL_PWR_DeInit (void)
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{
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}
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/**
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* @brief Enable access to the backup domain (RTC registers, RTC backup data
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* registers and backup SRAM).
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* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @retval None.
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*/
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void HAL_PWR_EnableBkUpAccess (void)
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{
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/* Enable access to RTC and backup registers */
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SET_BIT (PWR->CR1, PWR_CR1_DBP);
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}
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/**
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* @brief Disable access to the backup domain (RTC registers, RTC backup data
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* registers and backup SRAM).
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* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @retval None.
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*/
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void HAL_PWR_DisableBkUpAccess (void)
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{
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/* Disable access to RTC and backup registers */
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CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
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* @brief Power Control functions
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*
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@verbatim
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===============================================================================
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##### Peripheral Control Functions #####
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===============================================================================
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[..]
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This section provides functions allowing to control power peripheral.
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*** PVD configuration ***
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=========================
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[..]
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(+) The PVD is used to monitor the VDD power supply by comparing it to a
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threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
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register).
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(+) A PVDO flag is available to indicate if VDD is higher or lower
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than the PVD threshold. This event is internally connected to the EXTI
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line 16 to generate an interrupt if enabled.
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It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
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(+) The PVD is stopped in STANDBY mode.
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*** Wake-up pin configuration ***
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=================================
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[..]
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(+) Wake-up pin is used to wake up the system from STANDBY mode.
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The pin pull is configurable through the WKUPEPR register to be in
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No-pull, Pull-up and Pull-down.
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The pin polarity is configurable through the WKUPEPR register to be
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active on rising or falling edges.
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(+) There are up to six Wake-up pin in the STM32H7 devices family.
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*** Low Power modes configuration ***
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=====================================
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[..]
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The device present 3 principles low-power modes features:
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(+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining
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active (Powered and Clocked).
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(+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the
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regulator is running. The Main regulator or the LP
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regulator could be selected.
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(+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
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supply regulator is powered off.
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*** SLEEP mode ***
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==================
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[..]
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(+) Entry:
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The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
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SLEEPEntry) function.
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(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
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(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
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-@@- The Regulator parameter is not used for the STM32H7 family
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and is kept as parameter just to maintain compatibility with the
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lower power families (STM32L).
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(+) Exit:
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Any peripheral interrupt acknowledged by the nested vectored interrupt
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controller (NVIC) can wake up the device from SLEEP mode.
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*** STOP mode ***
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=================
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[..]
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In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
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the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
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register contents are preserved.
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The voltage regulator can be configured either in normal or low-power mode.
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To minimize the consumption in STOP mode, FLASH can be powered off before
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entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
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It can be switched on again by software after exiting the STOP mode using
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the HAL_PWREx_DisableFlashPowerDown() function.
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(+) Entry:
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The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
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STOPEntry) function with:
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(++) Regulator:
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(+++) PWR_MAINREGULATOR_ON: Main regulator ON.
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(+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
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(++) STOPEntry:
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(+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
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(+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
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(+) Exit:
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Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
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*** STANDBY mode ***
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====================
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[..]
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(+)
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The system STANDBY mode allows to achieve the lowest power consumption.
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It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
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disabled. The system is consequently powered off. The PLL, the HSI
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oscillator and the HSE oscillator are also switched off. SRAM and register
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contents are lost except for the RTC registers, RTC backup registers,
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backup SRAM and standby circuitry.
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[..]
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The voltage regulator is OFF.
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(++) Entry:
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(+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
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function.
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(++) Exit:
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(+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
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RTC wakeup, tamper event, time stamp event, external reset in NRST
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pin, IWDG reset.
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*** Auto-wakeup (AWU) from low-power mode ***
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=============================================
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[..]
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(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
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RTC Wakeup event, a tamper event or a time-stamp event, without
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depending on an external interrupt (Auto-wakeup mode).
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(+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
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(++) To wake up from the STOP mode with an RTC alarm event, it is
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necessary to configure the RTC to generate the RTC alarm using the
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HAL_RTC_SetAlarm_IT() function.
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(++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
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it is necessary to configure the RTC to detect the tamper or time
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stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
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HAL_RTCEx_SetTamper_IT() functions.
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(++) To wake up from the STOP mode with an RTC WakeUp event, it is
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necessary to configure the RTC to generate the RTC WakeUp event
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using the HAL_RTCEx_SetWakeUpTimer_IT() function.
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@endverbatim
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* @{
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*/
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/**
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* @brief Configure the event mode and the voltage threshold detected by the
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* Programmable Voltage Detector(PVD).
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* @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
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* the configuration information for the PVD.
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* @note Refer to the electrical characteristics of your device datasheet for
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* more details about the voltage threshold corresponding to each
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* detection level.
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* @note For dual core devices, please ensure to configure the EXTI lines for
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* the different Cortex-Mx through PWR_Exported_Macro provided by this
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* driver. All combination are allowed: wake up only Cortex-M7, wake up
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* only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
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* @retval None.
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*/
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void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
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{
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/* Check the PVD configuration parameter */
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if (sConfigPVD == NULL)
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{
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return;
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}
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/* Check the parameters */
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assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
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assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
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/* Set PLS[7:5] bits according to PVDLevel value */
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MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
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/* Clear previous config */
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#if !defined (DUAL_CORE)
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__HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
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__HAL_PWR_PVD_EXTI_DISABLE_IT ();
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#endif /* !defined (DUAL_CORE) */
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__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
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__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
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#if !defined (DUAL_CORE)
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/* Interrupt mode configuration */
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if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_IT ();
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}
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/* Event mode configuration */
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if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
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}
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#endif /* !defined (DUAL_CORE) */
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/* Rising edge configuration */
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if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
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}
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/* Falling edge configuration */
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if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
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}
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}
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/**
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* @brief Enable the Programmable Voltage Detector (PVD).
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* @retval None.
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*/
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void HAL_PWR_EnablePVD (void)
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{
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/* Enable the power voltage detector */
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SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
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}
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/**
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* @brief Disable the Programmable Voltage Detector (PVD).
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* @retval None.
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*/
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void HAL_PWR_DisablePVD (void)
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{
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/* Disable the power voltage detector */
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CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
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}
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/**
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* @brief Enable the WakeUp PINx functionality.
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* @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
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* This parameter can be one of the following legacy values, which
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* sets the default (rising edge):
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* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
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* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
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* or one of the following values where the user can explicitly states
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* the enabled pin and the chosen polarity:
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* @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
|
|
* PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
|
|
* PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
|
|
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
|
|
* PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
|
|
* PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
|
|
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
|
|
* @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
|
|
* and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
|
|
* GPIOI port.
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
|
|
|
|
/*
|
|
Enable and Specify the Wake-Up pin polarity and the pull configuration
|
|
for the event detection (rising or falling edge).
|
|
*/
|
|
MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable the WakeUp PINx functionality.
|
|
* @param WakeUpPinx : Specifies the Power Wake-Up pin to disable.
|
|
* This parameter can be one of the following values:
|
|
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
|
|
* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
|
|
* PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
|
|
* PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
|
|
* PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
|
|
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
|
|
* PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
|
|
* PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
|
|
* @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
|
|
* and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
|
|
* GPIOI port.
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
|
|
|
|
/* Disable the wake up pin selected */
|
|
CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
|
|
}
|
|
|
|
/**
|
|
* @brief Enter the current core in SLEEP mode (CSLEEP).
|
|
* @param Regulator : Specifies the regulator state in SLEEP mode.
|
|
* This parameter can be one of the following values:
|
|
* @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON.
|
|
* @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
|
|
* regulator ON.
|
|
* @note This parameter is not used for the STM32H7 family and is kept as
|
|
* parameter just to maintain compatibility with the lower power
|
|
* families.
|
|
* @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
|
|
* intrinsic instruction.
|
|
* This parameter can be one of the following values:
|
|
* @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
|
|
* @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
|
|
* @note Ensure to clear pending events before calling this API through
|
|
* HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param (IS_PWR_REGULATOR (Regulator));
|
|
assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
|
|
|
|
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
|
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
|
|
|
/* Select SLEEP mode entry */
|
|
if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
|
{
|
|
/* Request Wait For Interrupt */
|
|
__WFI ();
|
|
}
|
|
else
|
|
{
|
|
/* Request Wait For Event */
|
|
__WFE ();
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enter STOP mode.
|
|
* @note For single core devices, this API will enter the system in STOP mode
|
|
* with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR register is
|
|
* cleared.
|
|
* For dual core devices, this API will enter the domain (containing
|
|
* Cortex-Mx that executing this function) in DSTOP mode. If all
|
|
* Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
|
|
* cleared, all the system will enter in STOP mode.
|
|
* @param Regulator : Specifies the regulator state in STOP mode.
|
|
* This parameter can be one of the following values:
|
|
* @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
|
|
* @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
|
|
* regulator ON.
|
|
* @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
|
|
* intrinsic instruction.
|
|
* This parameter can be one of the following values:
|
|
* @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
|
|
* @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
|
|
* @note In System STOP mode, all I/O pins keep the same state as in Run mode.
|
|
* @note When exiting System STOP mode by issuing an interrupt or a wakeup
|
|
* event, the HSI RC oscillator is selected as default system wakeup
|
|
* clock.
|
|
* @note In System STOP mode, when the voltage regulator operates in low
|
|
* power mode, an additional startup delay is incurred when the system
|
|
* is waking up. By keeping the internal regulator ON during STOP mode,
|
|
* the consumption is higher although the startup time is reduced.
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param (IS_PWR_REGULATOR (Regulator));
|
|
assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
|
|
|
|
/* Select the regulator state in STOP mode */
|
|
MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
|
|
|
|
/* Configure the PWR mode for the different Domains */
|
|
#if defined (DUAL_CORE)
|
|
/* Check CPU ID */
|
|
if (HAL_GetCurrentCPUID () == CM7_CPUID)
|
|
{
|
|
/* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
|
|
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
|
|
}
|
|
else
|
|
{
|
|
/* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
|
|
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
|
|
}
|
|
#else /* Single core devices */
|
|
/* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
|
|
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
|
|
|
|
#if defined (PWR_CPUCR_PDDS_D2)
|
|
/* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
|
|
CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
|
|
#endif /* PWR_CPUCR_PDDS_D2 */
|
|
#endif /* defined (DUAL_CORE) */
|
|
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
|
|
|
/* Ensure that all instructions are done before entering STOP mode */
|
|
__DSB ();
|
|
__ISB ();
|
|
|
|
/* Select STOP mode entry */
|
|
if (STOPEntry == PWR_STOPENTRY_WFI)
|
|
{
|
|
/* Request Wait For Interrupt */
|
|
__WFI ();
|
|
}
|
|
else
|
|
{
|
|
/* Request Wait For Event */
|
|
__WFE ();
|
|
}
|
|
|
|
/* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
|
|
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
|
}
|
|
|
|
/**
|
|
* @brief Enter STANDBY mode.
|
|
* @note For single core devices, this API will enter the system in STANDBY
|
|
* mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
|
|
* register is cleared.
|
|
* For dual core devices, this API will enter the domain (containing
|
|
* Cortex-Mx that executing this function) in DSTANDBY mode. If all
|
|
* Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
|
|
* is cleared, all the system will enter in STANDBY mode.
|
|
* @note The system enters Standby mode only when all domains are in DSTANDBY.
|
|
* @note When the System exit STANDBY mode by issuing an interrupt or a
|
|
* wakeup event, the HSI RC oscillator is selected as system clock.
|
|
* @note It is recommended to disable all regulators before entring STANDBY
|
|
* mode for power consumption saving purpose.
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_EnterSTANDBYMode (void)
|
|
{
|
|
/* Configure the PWR mode for the different Domains */
|
|
#if defined (DUAL_CORE)
|
|
/* Check CPU ID */
|
|
if (HAL_GetCurrentCPUID () == CM7_CPUID)
|
|
{
|
|
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
|
|
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
|
|
SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
|
|
}
|
|
else
|
|
{
|
|
/* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
|
|
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
|
|
SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
|
|
}
|
|
#else /* Single core devices */
|
|
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
|
|
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
|
|
|
|
#if defined (PWR_CPUCR_PDDS_D2)
|
|
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
|
|
SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
|
|
#endif /* PWR_CPUCR_PDDS_D2 */
|
|
#endif /* defined (DUAL_CORE) */
|
|
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
|
|
|
/* Ensure that all instructions are done before entering STOP mode */
|
|
__DSB ();
|
|
__ISB ();
|
|
|
|
/* This option is used to ensure that store operations are completed */
|
|
#if defined (__CC_ARM)
|
|
__force_stores();
|
|
#endif /* defined (__CC_ARM) */
|
|
|
|
/* Request Wait For Interrupt */
|
|
__WFI ();
|
|
}
|
|
|
|
/**
|
|
* @brief Indicate Sleep-On-Exit feature when returning from Handler mode to
|
|
* Thread mode.
|
|
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
|
|
* processor re-enters SLEEP mode when an interruption handling is over.
|
|
* Setting this bit is useful when the processor is expected to run
|
|
* only on interruptions handling.
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_EnableSleepOnExit (void)
|
|
{
|
|
/* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
|
|
SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Sleep-On-Exit feature when returning from Handler mode to
|
|
* Thread mode.
|
|
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
|
|
* processor re-enters SLEEP mode when an interruption handling is over.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_DisableSleepOnExit (void)
|
|
{
|
|
/* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
|
|
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable CORTEX SEVONPEND feature.
|
|
* @note Sets SEVONPEND bit of SCR register. When this bit is set, any
|
|
* pending event / interrupt even if it's disabled or has insufficient
|
|
* priority to cause exception entry wakes up the Cortex-Mx.
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_EnableSEVOnPend (void)
|
|
{
|
|
/* Set SEVONPEND bit of Cortex-Mx System Control Register */
|
|
SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable CORTEX SEVONPEND feature.
|
|
* @note Resets SEVONPEND bit of SCR register. When this bit is reset, only
|
|
* enabled pending causes exception entry wakes up the Cortex-Mx.
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_DisableSEVOnPend (void)
|
|
{
|
|
/* Clear SEVONPEND bit of Cortex System Control Register */
|
|
CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
|
|
* @brief Interrupt Handling functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Interrupt Handling Functions #####
|
|
===============================================================================
|
|
[..]
|
|
This section provides functions allowing to handle the PVD pending
|
|
interrupts.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief This function handles the PWR PVD interrupt request.
|
|
* @note This API should be called under the PVD_AVD_IRQHandler().
|
|
* @retval None.
|
|
*/
|
|
void HAL_PWR_PVD_IRQHandler (void)
|
|
{
|
|
#if defined (DUAL_CORE)
|
|
/* Check Cortex-Mx ID */
|
|
if (HAL_GetCurrentCPUID () == CM7_CPUID)
|
|
{
|
|
/* Check PWR EXTI D1 flag */
|
|
if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
|
|
{
|
|
/* Clear PWR EXTI D1 pending bit */
|
|
__HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
|
|
|
|
/* PWR PVD interrupt user callback */
|
|
HAL_PWR_PVDCallback ();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PWR EXTI D2 flag */
|
|
if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
|
|
{
|
|
/* Clear PWR EXTI D2 pending bit */
|
|
__HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
|
|
|
|
/* PWR PVD interrupt user callback */
|
|
HAL_PWR_PVDCallback ();
|
|
}
|
|
}
|
|
#else /* Single core devices */
|
|
/* PVD EXTI line interrupt detected */
|
|
if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
|
|
{
|
|
/* Clear PWR EXTI pending bit */
|
|
__HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
|
|
|
|
/* PWR PVD interrupt user callback */
|
|
HAL_PWR_PVDCallback ();
|
|
}
|
|
#endif /* defined (DUAL_CORE) */
|
|
}
|
|
|
|
/**
|
|
* @brief PWR PVD interrupt callback.
|
|
* @retval None.
|
|
*/
|
|
__weak void HAL_PWR_PVDCallback (void)
|
|
{
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_PWR_PVDCallback can be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|