2619 lines
100 KiB
C
2619 lines
100 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_hal_adc_ex.c
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* @author MCD Application Team
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* @brief This file provides firmware functions to manage the following
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* functionalities of the Analog to Digital Converter (ADC)
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* peripheral:
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* + Peripheral Control functions
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* Other functions (generic functions) are available in file
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* "stm32h7xx_hal_adc.c".
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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[..]
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(@) Sections "ADC peripheral features" and "How to use this driver" are
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available in file of generic functions "stm32h7xx_hal_adc.c".
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[..]
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal.h"
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/** @addtogroup STM32H7xx_HAL_Driver
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* @{
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*/
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/** @defgroup ADCEx ADCEx
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* @brief ADC Extended HAL module driver
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* @{
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*/
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#ifdef HAL_ADC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
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* @{
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*/
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#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
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ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
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ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
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once the ADC is enabled */
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/* Fixed timeout value for ADC calibration. */
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/* Fixed timeout value for ADC calibration. */
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/* Values defined to be higher than worst cases: low clock frequency, */
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/* maximum prescalers. */
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/* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value */
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/* according to Data sheet), calibration_time MAX = 165010 / f_ADC */
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/* 165010 / 125000 = 1.32s */
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/* At maximum CPU speed (480 MHz), this means */
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/* 1.32 * 480 MHz = 633600000 CPU cycles */
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#define ADC_CALIBRATION_TIMEOUT (633600000U) /*!< ADC calibration time-out value */
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
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* @{
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*/
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/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
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* @brief Extended IO operation functions
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*
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@verbatim
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===============================================================================
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##### IO operation functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Perform the ADC self-calibration for single or differential ending.
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(+) Get calibration factors for single or differential ending.
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(+) Set calibration factors for single or differential ending.
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(+) Start conversion of ADC group injected.
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(+) Stop conversion of ADC group injected.
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(+) Poll for conversion complete on ADC group injected.
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(+) Get result of ADC group injected channel conversion.
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(+) Start conversion of ADC group injected and enable interruptions.
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(+) Stop conversion of ADC group injected and disable interruptions.
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(+) When multimode feature is available, start multimode and enable DMA transfer.
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(+) Stop multimode and disable ADC DMA transfer.
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(+) Get result of multimode conversion.
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@endverbatim
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* @{
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*/
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/**
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* @brief Perform an ADC automatic self-calibration
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* Calibration prerequisite: ADC must be disabled (execute this
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* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
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* @param hadc ADC handle
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* @param CalibrationMode Selection of calibration offset or
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* linear calibration offset.
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* @arg ADC_CALIB_OFFSET Channel in mode calibration offset
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* @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
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* @param SingleDiff Selection of single-ended or differential input
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* This parameter can be one of the following values:
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* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
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* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
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{
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HAL_StatusTypeDef tmp_hal_status;
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__IO uint32_t wait_loop_index = 0UL;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
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/* Process locked */
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__HAL_LOCK(hadc);
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/* Calibration prerequisite: ADC must be disabled. */
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/* Disable the ADC (if not already disabled) */
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tmp_hal_status = ADC_Disable(hadc);
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/* Check if ADC is effectively disabled */
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if (tmp_hal_status == HAL_OK)
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{
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/* Set ADC state */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
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HAL_ADC_STATE_BUSY_INTERNAL);
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/* Start ADC calibration in mode single-ended or differential */
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LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff);
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/* Wait for calibration completion */
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while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
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{
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wait_loop_index++;
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if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
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{
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/* Update ADC state machine to error */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_BUSY_INTERNAL,
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HAL_ADC_STATE_ERROR_INTERNAL);
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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return HAL_ERROR;
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}
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}
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/* Set ADC state */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_BUSY_INTERNAL,
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HAL_ADC_STATE_READY);
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}
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else
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{
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
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/* Note: No need to update variable "tmp_hal_status" here: already set */
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/* to state "HAL_ERROR" by function disabling the ADC. */
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}
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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/* Return function status */
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return tmp_hal_status;
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}
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/**
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* @brief Get the calibration factor.
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* @param hadc ADC handle.
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* @param SingleDiff This parameter can be only:
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* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
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* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
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* @retval Calibration value.
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*/
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uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
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{
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
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/* Return the selected ADC calibration value */
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return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
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}
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/**
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* @brief Get the calibration factor from automatic conversion result
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* @param hadc ADC handle
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* @param LinearCalib_Buffer: Linear calibration factor
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* @retval HAL state
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*/
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HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
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{
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uint32_t cnt;
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HAL_StatusTypeDef tmp_hal_status = HAL_OK;
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uint32_t temp_REG_IsConversionOngoing = 0UL;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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/* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
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if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
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{
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tmp_hal_status = ADC_Enable(hadc);
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}
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if (tmp_hal_status == HAL_OK)
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{
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if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
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{
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LL_ADC_REG_StopConversion(hadc->Instance);
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temp_REG_IsConversionOngoing = 1UL;
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}
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for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
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{
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LinearCalib_Buffer[cnt - 1U] = LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt));
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}
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if (temp_REG_IsConversionOngoing != 0UL)
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{
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LL_ADC_REG_StartConversion(hadc->Instance);
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}
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}
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return tmp_hal_status;
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}
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/**
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* @brief Set the calibration factor to overwrite automatic conversion result.
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* ADC must be enabled and no conversion is ongoing.
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* @param hadc ADC handle
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* @param SingleDiff This parameter can be only:
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* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
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* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
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* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
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* @retval HAL state
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*/
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HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
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{
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HAL_StatusTypeDef tmp_hal_status = HAL_OK;
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uint32_t tmp_adc_is_conversion_on_going_regular;
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uint32_t tmp_adc_is_conversion_on_going_injected;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
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assert_param(IS_ADC_CALFACT(CalibrationFactor));
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/* Process locked */
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__HAL_LOCK(hadc);
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/* Verification of hardware constraints before modifying the calibration */
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/* factors register: ADC must be enabled, no conversion on going. */
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tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
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tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
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if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
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&& (tmp_adc_is_conversion_on_going_regular == 0UL)
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&& (tmp_adc_is_conversion_on_going_injected == 0UL)
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)
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{
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/* Set the selected ADC calibration value */
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LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
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}
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else
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{
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/* Update ADC state machine */
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
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/* Update ADC error code */
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SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
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/* Update ADC state machine to error */
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tmp_hal_status = HAL_ERROR;
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}
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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/* Return function status */
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return tmp_hal_status;
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}
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/**
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* @brief Set the linear calibration factor
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* @param hadc ADC handle
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* @param LinearCalib_Buffer: Linear calibration factor
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* @retval HAL state
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*/
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HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
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{
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uint32_t cnt;
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__IO uint32_t wait_loop_index = 0;
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uint32_t temp_REG_IsConversionOngoing = 0UL;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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/* - Exit from deep-power-down mode and ADC voltage regulator enable */
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/* Exit deep power down mode if still in that state */
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if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
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{
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/* Exit deep power down mode */
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CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
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/* System was in deep power down mode, calibration must
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be relaunched or a previously saved calibration factor
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re-applied once the ADC voltage regulator is enabled */
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}
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if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
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{
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/* Enable ADC internal voltage regulator */
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SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
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/* Delay for ADC stabilization time */
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/* Wait loop initialization and execution */
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/* Note: Variable divided by 2 to compensate partially */
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/* CPU processing cycles. */
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wait_loop_index = ((ADC_STAB_DELAY_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
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while (wait_loop_index != 0UL)
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{
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wait_loop_index--;
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}
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}
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/* Verification that ADC voltage regulator is correctly enabled, whether */
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/* or not ADC is coming from state reset (if any potential problem of */
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/* clocking, voltage regulator would not be enabled). */
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if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
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{
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/* Update ADC state machine to error */
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
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/* Set ADC error code to ADC peripheral internal error */
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SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
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return HAL_ERROR;
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}
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/* Enable the ADC peripheral */
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if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) /* Enable the ADC if it is disabled */
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{
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if (ADC_Enable(hadc) != HAL_OK)
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{
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return HAL_ERROR;
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}
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else
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{
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for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
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{
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LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt), LinearCalib_Buffer[cnt - 1U]);
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}
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(void)ADC_Disable(hadc);
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}
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}
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else /* ADC is already enabled, so no need to enable it but need to stop conversion */
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{
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if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
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{
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LL_ADC_REG_StopConversion(hadc->Instance);
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temp_REG_IsConversionOngoing = 1UL;
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}
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for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
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{
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LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt), LinearCalib_Buffer[cnt - 1U]);
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}
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if (temp_REG_IsConversionOngoing != 0UL)
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{
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LL_ADC_REG_StartConversion(hadc->Instance);
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}
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}
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return HAL_OK;
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}
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/**
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* @brief Load the calibration factor from engi bytes
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* @param hadc ADC handle
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* @retval HAL state
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*/
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HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc)
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{
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HAL_StatusTypeDef tmp_hal_status = HAL_OK;
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uint32_t cnt, FactorOffset;
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uint32_t LinearCalib_Buffer[ADC_LINEAR_CALIB_REG_COUNT];
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/* Linearity calibration is retrieved from engi bytes
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read values from registers and put them to the CALFACT2 register */
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/* If needed linearity calibration can be done in runtime using
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LL_ADC_GetCalibrationLinearFactor() */
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if (hadc->Instance == ADC1)
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{
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FactorOffset = 0UL;
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}
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else if (hadc->Instance == ADC2)
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{
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FactorOffset = 8UL;
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}
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else /*Case ADC3*/
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{
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FactorOffset = 16UL;
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}
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for (cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++)
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{
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LinearCalib_Buffer[cnt] = *(uint32_t *)(ADC_LINEAR_CALIB_REG_1_ADDR + FactorOffset + cnt);
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}
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if (HAL_ADCEx_LinearCalibration_SetValue(hadc, (uint32_t *)LinearCalib_Buffer) != HAL_OK)
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{
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tmp_hal_status = HAL_ERROR;
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}
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return tmp_hal_status;
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}
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/**
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* @brief Enable ADC, start conversion of injected group.
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* @note Interruptions enabled in this function: None.
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* @note Case of multimode enabled when multimode feature is available:
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* HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
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* then for ADC master.
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* For ADC slave, ADC is enabled only (conversion is not started).
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* For ADC master, ADC is enabled and multimode conversion is started.
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* @param hadc ADC handle.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
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{
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HAL_StatusTypeDef tmp_hal_status;
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uint32_t tmp_config_injected_queue;
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uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
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{
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return HAL_BUSY;
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}
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else
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{
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/* In case of software trigger detection enabled, JQDIS must be set
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(which can be done only if ADSTART and JADSTART are both cleared).
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If JQDIS is not set at that point, returns an error
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- since software trigger detection is disabled. User needs to
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resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
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- or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
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the queue is empty */
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tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
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if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
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&& (tmp_config_injected_queue == 0UL)
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)
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{
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
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return HAL_ERROR;
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}
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/* Process locked */
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__HAL_LOCK(hadc);
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/* Enable the ADC peripheral */
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tmp_hal_status = ADC_Enable(hadc);
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/* Start conversion if ADC is effectively enabled */
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if (tmp_hal_status == HAL_OK)
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{
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/* Check if a regular conversion is ongoing */
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if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
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{
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/* Reset ADC error code field related to injected conversions only */
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CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
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}
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else
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{
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
}
|
|
|
|
/* Set ADC state */
|
|
/* - Clear state bitfield related to injected group conversion results */
|
|
/* - Set state bitfield related to injected operation */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
|
|
HAL_ADC_STATE_INJ_BUSY);
|
|
|
|
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
|
|
- if ADC instance is master or if multimode feature is not available
|
|
- if multimode setting is disabled (ADC instance slave in independent mode) */
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
)
|
|
{
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
}
|
|
|
|
/* Clear ADC group injected group conversion flag */
|
|
/* (To ensure of no unknown state from potential previous ADC operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Enable conversion of injected group, if automatic injected conversion */
|
|
/* is disabled. */
|
|
/* If software start has been selected, conversion starts immediately. */
|
|
/* If external trigger has been selected, conversion will start at next */
|
|
/* trigger event. */
|
|
/* Case of multimode enabled (when multimode feature is available): */
|
|
/* if ADC is slave, */
|
|
/* - ADC is enabled only (conversion is not started), */
|
|
/* - if multimode only concerns regular conversion, ADC is enabled */
|
|
/* and conversion is started. */
|
|
/* If ADC is master or independent, */
|
|
/* - ADC is enabled and conversion is started. */
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
|
|
)
|
|
{
|
|
/* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
|
|
if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
|
|
{
|
|
LL_ADC_INJ_StartConversion(hadc->Instance);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
}
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Stop conversion of injected channels. Disable ADC peripheral if
|
|
* no regular conversion is on going.
|
|
* @note If ADC must be disabled and if conversion is on going on
|
|
* regular group, function HAL_ADC_Stop must be used to stop both
|
|
* injected and regular groups, and disable the ADC.
|
|
* @note If injected group mode auto-injection is enabled,
|
|
* function HAL_ADC_Stop must be used.
|
|
* @note In case of multimode enabled (when multimode feature is available),
|
|
* HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
|
|
* For ADC master, conversion is stopped and ADC is disabled.
|
|
* For ADC slave, ADC is disabled only (conversion stop of ADC master
|
|
* has already stopped conversion of ADC slave).
|
|
* @param hadc ADC handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* 1. Stop potential conversion on going on injected group only. */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
|
|
|
|
/* Disable ADC peripheral if injected conversions are effectively stopped */
|
|
/* and if no conversion on regular group is on-going */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
{
|
|
/* 2. Disable the ADC peripheral */
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
/* Conversion on injected group is stopped, but ADC not disabled since */
|
|
/* conversion on regular group is still running. */
|
|
else
|
|
{
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Wait for injected group conversion to be completed.
|
|
* @param hadc ADC handle
|
|
* @param Timeout Timeout value in millisecond.
|
|
* @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
|
|
* checked and cleared depending on AUTDLY bit status.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
|
|
{
|
|
uint32_t tickstart;
|
|
uint32_t tmp_Flag_End;
|
|
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
|
|
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
|
|
uint32_t tmp_cfgr;
|
|
const ADC_TypeDef *tmpADC_Master;
|
|
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* If end of sequence selected */
|
|
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
|
|
{
|
|
tmp_Flag_End = ADC_FLAG_JEOS;
|
|
}
|
|
else /* end of conversion selected */
|
|
{
|
|
tmp_Flag_End = ADC_FLAG_JEOC;
|
|
}
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait until End of Conversion or Sequence flag is raised */
|
|
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
|
{
|
|
/* Check if timeout is disabled (set to infinite wait) */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
|
|
{
|
|
if((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
|
{
|
|
/* Update ADC state machine to timeout */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Retrieve ADC configuration */
|
|
tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
|
|
tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
|
|
/* Get relevant register CFGR in ADC instance of ADC master or slave */
|
|
/* in function of multimode state (for devices with multimode */
|
|
/* available). */
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
|
|
)
|
|
{
|
|
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
|
}
|
|
else
|
|
{
|
|
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
|
|
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
|
|
}
|
|
|
|
/* Update ADC state machine */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
|
|
|
|
/* Determine whether any further conversion upcoming on group injected */
|
|
/* by external trigger or by automatic injected conversion */
|
|
/* from group regular. */
|
|
if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
|
|
((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
|
|
((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
|
|
(READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
|
|
{
|
|
/* Check whether end of sequence is reached */
|
|
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
|
|
{
|
|
/* Particular case if injected contexts queue is enabled: */
|
|
/* when the last context has been fully processed, JSQR is reset */
|
|
/* by the hardware. Even if no injected conversion is planned to come */
|
|
/* (queue empty, triggers are ignored), it can start again */
|
|
/* immediately after setting a new context (JADSTART is still set). */
|
|
/* Therefore, state of HAL ADC injected group is kept to busy. */
|
|
if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
|
|
{
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
|
|
|
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Clear polled flag */
|
|
if (tmp_Flag_End == ADC_FLAG_JEOS)
|
|
{
|
|
/* Clear end of sequence JEOS flag of injected group if low power feature */
|
|
/* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
|
|
/* For injected groups, no new conversion will start before JEOS is */
|
|
/* cleared. */
|
|
if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
|
|
{
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
|
|
}
|
|
|
|
/* Return API HAL status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable ADC, start conversion of injected group with interruption.
|
|
* @note Interruptions enabled in this function according to initialization
|
|
* setting : JEOC (end of conversion) or JEOS (end of sequence)
|
|
* @note Case of multimode enabled (when multimode feature is enabled):
|
|
* HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
|
|
* then for ADC master.
|
|
* For ADC slave, ADC is enabled only (conversion is not started).
|
|
* For ADC master, ADC is enabled and multimode conversion is started.
|
|
* @param hadc ADC handle.
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
uint32_t tmp_config_injected_queue;
|
|
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else
|
|
{
|
|
/* In case of software trigger detection enabled, JQDIS must be set
|
|
(which can be done only if ADSTART and JADSTART are both cleared).
|
|
If JQDIS is not set at that point, returns an error
|
|
- since software trigger detection is disabled. User needs to
|
|
resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
|
|
- or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
|
|
the queue is empty */
|
|
tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
|
|
|
|
if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
|
|
&& (tmp_config_injected_queue == 0UL)
|
|
)
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* Enable the ADC peripheral */
|
|
tmp_hal_status = ADC_Enable(hadc);
|
|
|
|
/* Start conversion if ADC is effectively enabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Check if a regular conversion is ongoing */
|
|
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
|
|
{
|
|
/* Reset ADC error code field related to injected conversions only */
|
|
CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
|
|
}
|
|
else
|
|
{
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
}
|
|
|
|
/* Set ADC state */
|
|
/* - Clear state bitfield related to injected group conversion results */
|
|
/* - Set state bitfield related to injected operation */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
|
|
HAL_ADC_STATE_INJ_BUSY);
|
|
|
|
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
|
|
- if ADC instance is master or if multimode feature is not available
|
|
- if multimode setting is disabled (ADC instance slave in independent mode) */
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
)
|
|
{
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
}
|
|
|
|
/* Clear ADC group injected group conversion flag */
|
|
/* (To ensure of no unknown state from potential previous ADC operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Enable ADC Injected context queue overflow interrupt if this feature */
|
|
/* is enabled. */
|
|
if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
|
|
{
|
|
__HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
|
|
}
|
|
|
|
/* Enable ADC end of conversion interrupt */
|
|
switch (hadc->Init.EOCSelection)
|
|
{
|
|
case ADC_EOC_SEQ_CONV:
|
|
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
|
|
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
|
|
break;
|
|
/* case ADC_EOC_SINGLE_CONV */
|
|
default:
|
|
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
|
|
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
|
|
break;
|
|
}
|
|
|
|
/* Enable conversion of injected group, if automatic injected conversion */
|
|
/* is disabled. */
|
|
/* If software start has been selected, conversion starts immediately. */
|
|
/* If external trigger has been selected, conversion will start at next */
|
|
/* trigger event. */
|
|
/* Case of multimode enabled (when multimode feature is available): */
|
|
/* if ADC is slave, */
|
|
/* - ADC is enabled only (conversion is not started), */
|
|
/* - if multimode only concerns regular conversion, ADC is enabled */
|
|
/* and conversion is started. */
|
|
/* If ADC is master or independent, */
|
|
/* - ADC is enabled and conversion is started. */
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
|
|
)
|
|
{
|
|
/* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
|
|
if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
|
|
{
|
|
LL_ADC_INJ_StartConversion(hadc->Instance);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
}
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Stop conversion of injected channels, disable interruption of
|
|
* end-of-conversion. Disable ADC peripheral if no regular conversion
|
|
* is on going.
|
|
* @note If ADC must be disabled and if conversion is on going on
|
|
* regular group, function HAL_ADC_Stop must be used to stop both
|
|
* injected and regular groups, and disable the ADC.
|
|
* @note If injected group mode auto-injection is enabled,
|
|
* function HAL_ADC_Stop must be used.
|
|
* @note Case of multimode enabled (when multimode feature is available):
|
|
* HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
|
|
* then for ADC slave.
|
|
* For ADC master, conversion is stopped and ADC is disabled.
|
|
* For ADC slave, ADC is disabled only (conversion stop of ADC master
|
|
* has already stopped conversion of ADC slave).
|
|
* @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* 1. Stop potential conversion on going on injected group only. */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
|
|
|
|
/* Disable ADC peripheral if injected conversions are effectively stopped */
|
|
/* and if no conversion on the other group (regular group) is intended to */
|
|
/* continue. */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Disable ADC end of conversion interrupt for injected channels */
|
|
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
|
|
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
{
|
|
/* 2. Disable the ADC peripheral */
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
/* Conversion on injected group is stopped, but ADC not disabled since */
|
|
/* conversion on regular group is still running. */
|
|
else
|
|
{
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
|
|
* @note Multimode must have been previously configured using
|
|
* HAL_ADCEx_MultiModeConfigChannel() function.
|
|
* Interruptions enabled in this function:
|
|
* overrun, DMA half transfer, DMA transfer complete.
|
|
* Each of these interruptions has its dedicated callback function.
|
|
* @note State field of Slave ADC handle is not updated in this configuration:
|
|
* user should not rely on it for information related to Slave regular
|
|
* conversions.
|
|
* @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
|
|
* @param pData Destination Buffer address.
|
|
* @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
ADC_HandleTypeDef tmphadcSlave;
|
|
ADC_Common_TypeDef *tmpADC_Common;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
|
|
assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
|
|
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else
|
|
{
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
tmphadcSlave.State = HAL_ADC_STATE_RESET;
|
|
tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
|
|
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
|
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
|
|
|
if (tmphadcSlave.Instance == NULL)
|
|
{
|
|
/* Set ADC state */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Enable the ADC peripherals: master and slave (in case if not already */
|
|
/* enabled previously) */
|
|
tmp_hal_status = ADC_Enable(hadc);
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
tmp_hal_status = ADC_Enable(&tmphadcSlave);
|
|
}
|
|
|
|
/* Start multimode conversion of ADCs pair */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
(HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
|
|
HAL_ADC_STATE_REG_BUSY);
|
|
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
|
|
/* Set the DMA transfer complete callback */
|
|
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
|
|
|
|
/* Set the DMA half transfer complete callback */
|
|
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
|
|
|
|
/* Pointer to the common control register */
|
|
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
|
|
|
|
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
|
|
/* start (in case of SW start): */
|
|
|
|
/* Clear regular group conversion flag and overrun flag */
|
|
/* (To ensure of no unknown state from potential previous ADC operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Enable ADC overrun interrupt */
|
|
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
|
|
|
|
/* Start the DMA channel */
|
|
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
|
|
|
|
/* Enable conversion of regular group. */
|
|
/* If software start has been selected, conversion starts immediately. */
|
|
/* If external trigger has been selected, conversion will start at next */
|
|
/* trigger event. */
|
|
/* Start ADC group regular conversion */
|
|
LL_ADC_REG_StartConversion(hadc->Instance);
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
|
|
* @note Multimode is kept enabled after this function. MultiMode DMA bits
|
|
* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
|
|
* Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
|
|
* reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
|
|
* resort to HAL_ADCEx_DisableMultiMode() API.
|
|
* @note In case of DMA configured in circular mode, function
|
|
* HAL_ADC_Stop_DMA() must be called after this function with handle of
|
|
* ADC slave, to properly disable the DMA channel.
|
|
* @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
uint32_t tickstart;
|
|
ADC_HandleTypeDef tmphadcSlave;
|
|
uint32_t tmphadcSlave_conversion_on_going;
|
|
HAL_StatusTypeDef tmphadcSlave_disable_status;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
|
|
/* 1. Stop potential multimode conversion on going, on regular and injected groups */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
|
|
|
|
/* Disable ADC peripheral if conversions are effectively stopped */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
tmphadcSlave.State = HAL_ADC_STATE_RESET;
|
|
tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
|
|
|
|
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
|
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
|
|
|
if (tmphadcSlave.Instance == NULL)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Procedure to disable the ADC peripheral: wait for conversions */
|
|
/* effectively stopped (ADC master and ADC slave), then disable ADC */
|
|
|
|
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
|
|
tickstart = HAL_GetTick();
|
|
|
|
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
|
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|
|
|| (tmphadcSlave_conversion_on_going == 1UL)
|
|
)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
|
|
|
if((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|
|
|| (tmphadcSlave_conversion_on_going == 1UL)
|
|
)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
|
}
|
|
|
|
/* Disable the DMA channel (in case of DMA in circular mode or stop */
|
|
/* while DMA transfer is on going) */
|
|
/* Note: DMA channel of ADC slave should be stopped after this function */
|
|
/* with HAL_ADC_Stop_DMA() API. */
|
|
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
|
|
|
/* Check if DMA channel effectively disabled */
|
|
if (tmp_hal_status == HAL_ERROR)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
|
|
}
|
|
|
|
/* Disable ADC overrun interrupt */
|
|
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
|
|
|
|
/* 2. Disable the ADC peripherals: master and slave */
|
|
/* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
|
|
/* memory a potential failing status. */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
|
|
if ((ADC_Disable(hadc) == HAL_OK) &&
|
|
(tmphadcSlave_disable_status == HAL_OK))
|
|
{
|
|
tmp_hal_status = HAL_OK;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* In case of error, attempt to disable ADC master and slave without status assert */
|
|
(void) ADC_Disable(hadc);
|
|
(void) ADC_Disable(&tmphadcSlave);
|
|
}
|
|
|
|
/* Set ADC state (ADC master) */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
|
|
* @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
|
|
* @retval The converted data values.
|
|
*/
|
|
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
|
|
{
|
|
const ADC_Common_TypeDef *tmpADC_Common;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
|
|
|
/* Prevent unused argument(s) compilation warning if no assert_param check */
|
|
/* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
|
|
UNUSED(hadc);
|
|
|
|
/* Pointer to the common control register */
|
|
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
|
|
|
|
/* Return the multi mode conversion value */
|
|
return tmpADC_Common->CDR;
|
|
}
|
|
|
|
/**
|
|
* @brief Get ADC injected group conversion result.
|
|
* @note Reading register JDRx automatically clears ADC flag JEOC
|
|
* (ADC group injected end of unitary conversion).
|
|
* @note This function does not clear ADC flag JEOS
|
|
* (ADC group injected end of sequence conversion)
|
|
* Occurrence of flag JEOS rising:
|
|
* - If sequencer is composed of 1 rank, flag JEOS is equivalent
|
|
* to flag JEOC.
|
|
* - If sequencer is composed of several ranks, during the scan
|
|
* sequence flag JEOC only is raised, at the end of the scan sequence
|
|
* both flags JEOC and EOS are raised.
|
|
* Flag JEOS must not be cleared by this function because
|
|
* it would not be compliant with low power features
|
|
* (feature low power auto-wait, not available on all STM32 families).
|
|
* To clear this flag, either use function:
|
|
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
|
|
* model polling: @ref HAL_ADCEx_InjectedPollForConversion()
|
|
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
|
|
* @param hadc ADC handle
|
|
* @param InjectedRank the converted ADC injected rank.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
|
|
* @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
|
|
* @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
|
|
* @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
|
|
* @retval ADC group injected conversion data
|
|
*/
|
|
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
|
|
{
|
|
uint32_t tmp_jdr;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
|
|
|
|
/* Get ADC converted value */
|
|
switch (InjectedRank)
|
|
{
|
|
case ADC_INJECTED_RANK_4:
|
|
tmp_jdr = hadc->Instance->JDR4;
|
|
break;
|
|
case ADC_INJECTED_RANK_3:
|
|
tmp_jdr = hadc->Instance->JDR3;
|
|
break;
|
|
case ADC_INJECTED_RANK_2:
|
|
tmp_jdr = hadc->Instance->JDR2;
|
|
break;
|
|
case ADC_INJECTED_RANK_1:
|
|
default:
|
|
tmp_jdr = hadc->Instance->JDR1;
|
|
break;
|
|
}
|
|
|
|
/* Return ADC converted value */
|
|
return tmp_jdr;
|
|
}
|
|
|
|
/**
|
|
* @brief Injected conversion complete callback in non-blocking mode.
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Injected context queue overflow callback.
|
|
* @note This callback is called if injected context queue is enabled
|
|
(parameter "QueueInjectedContext" in injected channel configuration)
|
|
and if a new injected context is set when queue is full (maximum 2
|
|
contexts).
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Analog watchdog 2 callback in non-blocking mode.
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Analog watchdog 3 callback in non-blocking mode.
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
|
|
*/
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief End Of Sampling callback in non-blocking mode.
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Stop ADC conversion of regular group (and injected channels in
|
|
* case of auto_injection mode), disable ADC peripheral if no
|
|
* conversion is on going on injected group.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* 1. Stop potential regular conversion on going */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
|
|
|
|
/* Disable ADC peripheral if regular conversions are effectively stopped
|
|
and if no injected conversions are on-going */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Clear HAL_ADC_STATE_REG_BUSY bit */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
|
|
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
{
|
|
/* 2. Disable the ADC peripheral */
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
/* Conversion on injected group is stopped, but ADC not disabled since */
|
|
/* conversion on regular group is still running. */
|
|
else
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Stop ADC conversion of ADC groups regular and injected,
|
|
* disable interrution of end-of-conversion,
|
|
* disable ADC peripheral if no conversion is on going
|
|
* on injected group.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* 1. Stop potential regular conversion on going */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
|
|
|
|
/* Disable ADC peripheral if conversions are effectively stopped
|
|
and if no injected conversion is on-going */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Clear HAL_ADC_STATE_REG_BUSY bit */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
|
|
/* Disable all regular-related interrupts */
|
|
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
|
|
|
|
/* 2. Disable ADC peripheral if no injected conversions are on-going */
|
|
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
{
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
/* if no issue reported */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Stop ADC conversion of regular group (and injected group in
|
|
* case of auto_injection mode), disable ADC DMA transfer, disable
|
|
* ADC peripheral if no conversion is on going
|
|
* on injected group.
|
|
* @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
|
|
* For multimode (when multimode feature is available),
|
|
* HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* 1. Stop potential regular conversion on going */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
|
|
|
|
/* Disable ADC peripheral if conversions are effectively stopped
|
|
and if no injected conversion is on-going */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Clear HAL_ADC_STATE_REG_BUSY bit */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
|
|
/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
|
|
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1, 0UL);
|
|
|
|
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
|
|
/* while DMA transfer is on going) */
|
|
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
|
|
|
/* Check if DMA channel effectively disabled */
|
|
if (tmp_hal_status != HAL_OK)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
|
|
}
|
|
|
|
/* Disable ADC overrun interrupt */
|
|
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
|
|
|
|
/* 2. Disable the ADC peripheral */
|
|
/* Update "tmp_hal_status" only if DMA channel disabling passed, */
|
|
/* to keep in memory a potential failing status. */
|
|
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
{
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
}
|
|
else
|
|
{
|
|
(void)ADC_Disable(hadc);
|
|
}
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
|
|
* @note Multimode is kept enabled after this function. Multimode DMA bits
|
|
* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
|
|
* multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
|
|
* reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
|
|
* resort to HAL_ADCEx_DisableMultiMode() API.
|
|
* @note In case of DMA configured in circular mode, function
|
|
* HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
|
|
* ADC slave, to properly disable the DMA channel.
|
|
* @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
uint32_t tickstart;
|
|
ADC_HandleTypeDef tmphadcSlave;
|
|
uint32_t tmphadcSlave_conversion_on_going;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
|
|
/* 1. Stop potential multimode conversion on going, on regular groups */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
|
|
|
|
/* Disable ADC peripheral if conversions are effectively stopped */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Clear HAL_ADC_STATE_REG_BUSY bit */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
|
|
tmphadcSlave.State = HAL_ADC_STATE_RESET;
|
|
tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
|
|
|
|
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
|
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
|
|
|
if (tmphadcSlave.Instance == NULL)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Procedure to disable the ADC peripheral: wait for conversions */
|
|
/* effectively stopped (ADC master and ADC slave), then disable ADC */
|
|
|
|
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
|
|
tickstart = HAL_GetTick();
|
|
|
|
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
|
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|
|
|| (tmphadcSlave_conversion_on_going == 1UL)
|
|
)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
|
|
|
if((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|
|
|| (tmphadcSlave_conversion_on_going == 1UL)
|
|
)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
|
}
|
|
|
|
/* Disable the DMA channel (in case of DMA in circular mode or stop */
|
|
/* while DMA transfer is on going) */
|
|
/* Note: DMA channel of ADC slave should be stopped after this function */
|
|
/* with HAL_ADCEx_RegularStop_DMA() API. */
|
|
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
|
|
|
/* Check if DMA channel effectively disabled */
|
|
if (tmp_hal_status != HAL_OK)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
|
|
}
|
|
|
|
/* Disable ADC overrun interrupt */
|
|
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
|
|
|
|
/* 2. Disable the ADC peripherals: master and slave if no injected */
|
|
/* conversion is on-going. */
|
|
/* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
|
|
/* memory a potential failing status. */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
{
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
|
|
{
|
|
tmp_hal_status = ADC_Disable(&tmphadcSlave);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Both Master and Slave ADC's could be disabled. Update Master State */
|
|
/* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
|
|
}
|
|
else
|
|
{
|
|
/* injected (Master or Slave) conversions are still on-going,
|
|
no Master State change */
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
|
|
* @brief ADC Extended Peripheral Control functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Peripheral Control functions #####
|
|
===============================================================================
|
|
[..] This section provides functions allowing to:
|
|
(+) Configure channels on injected group
|
|
(+) Configure multimode when multimode feature is available
|
|
(+) Enable or Disable Injected Queue
|
|
(+) Disable ADC voltage regulator
|
|
(+) Enter ADC deep-power-down mode
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Configure a channel to be assigned to ADC group injected.
|
|
* @note Possibility to update parameters on the fly:
|
|
* This function initializes injected group, following calls to this
|
|
* function can be used to reconfigure some parameters of structure
|
|
* "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
|
|
* The setting of these parameters is conditioned to ADC state:
|
|
* Refer to comments of structure "ADC_InjectionConfTypeDef".
|
|
* @note In case of usage of internal measurement channels:
|
|
* Vbat/VrefInt/TempSensor.
|
|
* These internal paths can be disabled using function
|
|
* HAL_ADC_DeInit().
|
|
* @note Caution: For Injected Context Queue use, a context must be fully
|
|
* defined before start of injected conversion. All channels are configured
|
|
* consecutively for the same ADC instance. Therefore, the number of calls to
|
|
* HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
|
|
* InjectedNbrOfConversion for each context.
|
|
* - Example 1: If 1 context is intended to be used (or if there is no use of the
|
|
* Injected Queue Context feature) and if the context contains 3 injected ranks
|
|
* (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
|
|
* called once for each channel (i.e. 3 times) before starting a conversion.
|
|
* This function must not be called to configure a 4th injected channel:
|
|
* it would start a new context into context queue.
|
|
* - Example 2: If 2 contexts are intended to be used and each of them contains
|
|
* 3 injected ranks (InjectedNbrOfConversion = 3),
|
|
* HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
|
|
* for each context (3 channels x 2 contexts = 6 calls). Conversion can
|
|
* start once the 1st context is set, that is after the first three
|
|
* HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
|
|
* @param hadc ADC handle
|
|
* @param sConfigInjected Structure of ADC injected group and ADC channel for
|
|
* injected group.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
uint32_t tmpOffsetShifted;
|
|
uint32_t tmp_config_internal_channel;
|
|
uint32_t tmp_adc_is_conversion_on_going_regular;
|
|
uint32_t tmp_adc_is_conversion_on_going_injected;
|
|
__IO uint32_t wait_loop_index = 0;
|
|
|
|
uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
|
|
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
|
|
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
|
|
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
|
|
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
|
|
assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
|
|
assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
|
|
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
|
|
#if defined(ADC_VER_V5_V90)
|
|
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation));
|
|
if (hadc->Instance == ADC3)
|
|
{
|
|
assert_param(IS_ADC3_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign));
|
|
assert_param(IS_ADC3_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
|
|
}
|
|
else
|
|
#endif /* ADC_VER_V5_V90 */
|
|
{
|
|
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
|
|
}
|
|
|
|
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
|
|
{
|
|
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
|
|
assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
|
|
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
|
|
}
|
|
|
|
/* Check offset range according to oversampling setting */
|
|
if (hadc->Init.OversamplingMode == ENABLE)
|
|
{
|
|
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset / (hadc->Init.Oversampling.Ratio + 1U)));
|
|
}
|
|
else
|
|
{
|
|
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
|
|
}
|
|
#if defined(ADC_VER_V5_V90)
|
|
/* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
|
|
ignored (considered as reset) */
|
|
if (hadc->Instance == ADC3)
|
|
{
|
|
assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
|
|
}
|
|
#endif /* ADC_VER_V5_V90 */
|
|
/* JDISCEN and JAUTO bits can't be set at the same time */
|
|
assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
|
|
|
|
/* DISCEN and JAUTO bits can't be set at the same time */
|
|
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
|
|
|
|
/* Verification of channel number */
|
|
if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
|
|
{
|
|
assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
|
|
}
|
|
else
|
|
{
|
|
if (hadc->Instance == ADC1)
|
|
{
|
|
assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
|
|
}
|
|
if (hadc->Instance == ADC2)
|
|
{
|
|
assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
|
|
}
|
|
#if defined (ADC3)
|
|
if (hadc->Instance == ADC3)
|
|
{
|
|
assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* Configuration of injected group sequencer: */
|
|
/* Hardware constraint: Must fully define injected context register JSQR */
|
|
/* before make it entering into injected sequencer queue. */
|
|
/* */
|
|
/* - if scan mode is disabled: */
|
|
/* * Injected channels sequence length is set to 0x00: 1 channel */
|
|
/* converted (channel on injected rank 1) */
|
|
/* Parameter "InjectedNbrOfConversion" is discarded. */
|
|
/* * Injected context register JSQR setting is simple: register is fully */
|
|
/* defined on one call of this function (for injected rank 1) and can */
|
|
/* be entered into queue directly. */
|
|
/* - if scan mode is enabled: */
|
|
/* * Injected channels sequence length is set to parameter */
|
|
/* "InjectedNbrOfConversion". */
|
|
/* * Injected context register JSQR setting more complex: register is */
|
|
/* fully defined over successive calls of this function, for each */
|
|
/* injected channel rank. It is entered into queue only when all */
|
|
/* injected ranks have been set. */
|
|
/* Note: Scan mode is not present by hardware on this device, but used */
|
|
/* by software for alignment over all STM32 devices. */
|
|
|
|
if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
|
|
(sConfigInjected->InjectedNbrOfConversion == 1U))
|
|
{
|
|
/* Configuration of context register JSQR: */
|
|
/* - number of ranks in injected group sequencer: fixed to 1st rank */
|
|
/* (scan mode disabled, only rank 1 used) */
|
|
/* - external trigger to start conversion */
|
|
/* - external trigger polarity */
|
|
/* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
|
|
|
|
if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
|
|
{
|
|
/* Enable external trigger if trigger selection is different of */
|
|
/* software start. */
|
|
/* Note: This configuration keeps the hardware feature of parameter */
|
|
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
|
|
/* software start. */
|
|
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
|
|
{
|
|
tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
|
|
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
|
|
| sConfigInjected->ExternalTrigInjecConvEdge
|
|
);
|
|
}
|
|
else
|
|
{
|
|
tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
|
|
}
|
|
|
|
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
|
|
/* For debug and informative reasons, hadc handle saves JSQR setting */
|
|
hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
|
|
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Case of scan mode enabled, several channels to set into injected group */
|
|
/* sequencer. */
|
|
/* */
|
|
/* Procedure to define injected context register JSQR over successive */
|
|
/* calls of this function, for each injected channel rank: */
|
|
/* 1. Start new context and set parameters related to all injected */
|
|
/* channels: injected sequence length and trigger. */
|
|
|
|
/* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
|
|
/* call of the context under setting */
|
|
if (hadc->InjectionConfig.ChannelCount == 0U)
|
|
{
|
|
/* Initialize number of channels that will be configured on the context */
|
|
/* being built */
|
|
hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
|
|
/* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
|
|
call, this context will be written in JSQR register at the last call.
|
|
At this point, the context is merely reset */
|
|
hadc->InjectionConfig.ContextQueue = 0x00000000U;
|
|
|
|
/* Configuration of context register JSQR: */
|
|
/* - number of ranks in injected group sequencer */
|
|
/* - external trigger to start conversion */
|
|
/* - external trigger polarity */
|
|
|
|
/* Enable external trigger if trigger selection is different of */
|
|
/* software start. */
|
|
/* Note: This configuration keeps the hardware feature of parameter */
|
|
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
|
|
/* software start. */
|
|
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
|
|
{
|
|
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
|
|
| (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
|
|
| sConfigInjected->ExternalTrigInjecConvEdge
|
|
);
|
|
}
|
|
else
|
|
{
|
|
tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
|
|
}
|
|
|
|
}
|
|
|
|
/* 2. Continue setting of context under definition with parameter */
|
|
/* related to each channel: channel rank sequence */
|
|
/* Clear the old JSQx bits for the selected rank */
|
|
tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
|
|
|
|
/* Set the JSQx bits for the selected rank */
|
|
tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
|
|
|
|
/* Decrease channel count */
|
|
hadc->InjectionConfig.ChannelCount--;
|
|
|
|
/* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
|
|
call, aggregate the setting to those already built during the previous
|
|
HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
|
|
hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
|
|
|
|
/* 4. End of context setting: if this is the last channel set, then write context
|
|
into register JSQR and make it enter into queue */
|
|
if (hadc->InjectionConfig.ChannelCount == 0U)
|
|
{
|
|
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
|
|
}
|
|
}
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on injected group: */
|
|
/* - Injected context queue: Queue disable (active context is kept) or */
|
|
/* enable (context decremented, up to 2 contexts queued) */
|
|
/* - Injected discontinuous mode: can be enabled only if auto-injected */
|
|
/* mode is disabled. */
|
|
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
{
|
|
#if defined(ADC_VER_V5_V90)
|
|
if (hadc->Instance != ADC3)
|
|
{
|
|
/* ADC channels preselection */
|
|
hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
|
|
}
|
|
#else
|
|
/* ADC channels preselection */
|
|
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
|
|
#endif /* ADC_VER_V5_V90 */
|
|
|
|
/* If auto-injected mode is disabled: no constraint */
|
|
if (sConfigInjected->AutoInjectedConv == DISABLE)
|
|
{
|
|
MODIFY_REG(hadc->Instance->CFGR,
|
|
ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
|
|
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) |
|
|
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
|
|
}
|
|
/* If auto-injected mode is enabled: Injected discontinuous setting is */
|
|
/* discarded. */
|
|
else
|
|
{
|
|
MODIFY_REG(hadc->Instance->CFGR,
|
|
ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
|
|
ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
|
|
}
|
|
|
|
}
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular and injected groups: */
|
|
/* - Automatic injected conversion: can be enabled if injected group */
|
|
/* external triggers are disabled. */
|
|
/* - Channel sampling time */
|
|
/* - Channel offset */
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
|
|
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
|
|
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
|
|
)
|
|
{
|
|
/* If injected group external triggers are disabled (set to injected */
|
|
/* software start): no constraint */
|
|
if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
|
|
|| (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
|
|
{
|
|
if (sConfigInjected->AutoInjectedConv == ENABLE)
|
|
{
|
|
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
|
|
}
|
|
}
|
|
/* If Automatic injected conversion was intended to be set and could not */
|
|
/* due to injected group external triggers enabled, error is reported. */
|
|
else
|
|
{
|
|
if (sConfigInjected->AutoInjectedConv == ENABLE)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
|
|
}
|
|
}
|
|
|
|
if (sConfigInjected->InjecOversamplingMode == ENABLE)
|
|
{
|
|
#if defined(ADC_VER_V5_V90)
|
|
if (hadc->Instance == ADC3)
|
|
{
|
|
assert_param(IS_ADC_OVERSAMPLING_RATIO_ADC3(sConfigInjected->InjecOversampling.Ratio));
|
|
}
|
|
else
|
|
{
|
|
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
|
|
}
|
|
#else
|
|
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
|
|
#endif
|
|
assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
|
|
|
|
/* JOVSE must be reset in case of triggered regular mode */
|
|
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
|
|
|
|
/* Configuration of Injected Oversampler: */
|
|
/* - Oversampling Ratio */
|
|
/* - Right bit shift */
|
|
|
|
/* Enable OverSampling mode */
|
|
#if defined(ADC_VER_V5_V90)
|
|
if (hadc->Instance != ADC3)
|
|
{
|
|
MODIFY_REG(hadc->Instance->CFGR2,
|
|
ADC_CFGR2_JOVSE |
|
|
ADC_CFGR2_OVSR |
|
|
ADC_CFGR2_OVSS,
|
|
ADC_CFGR2_JOVSE |
|
|
((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
|
|
sConfigInjected->InjecOversampling.RightBitShift
|
|
);
|
|
}
|
|
else
|
|
{
|
|
MODIFY_REG(hadc->Instance->CFGR2,
|
|
ADC_CFGR2_JOVSE |
|
|
ADC3_CFGR2_OVSR |
|
|
ADC_CFGR2_OVSS,
|
|
ADC_CFGR2_JOVSE |
|
|
(sConfigInjected->InjecOversampling.Ratio) |
|
|
sConfigInjected->InjecOversampling.RightBitShift
|
|
);
|
|
}
|
|
#else
|
|
MODIFY_REG(hadc->Instance->CFGR2,
|
|
ADC_CFGR2_JOVSE |
|
|
ADC_CFGR2_OVSR |
|
|
ADC_CFGR2_OVSS,
|
|
ADC_CFGR2_JOVSE |
|
|
((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
|
|
sConfigInjected->InjecOversampling.RightBitShift
|
|
);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* Disable Regular OverSampling */
|
|
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
|
|
}
|
|
|
|
/* Set sampling time of the selected ADC channel */
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
|
|
|
|
/* Configure the offset: offset enable/disable, channel, offset value */
|
|
|
|
/* Shift the offset with respect to the selected ADC resolution. */
|
|
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
|
|
#if defined(ADC_VER_V5_V90)
|
|
if (hadc->Instance == ADC3)
|
|
{
|
|
tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
|
|
}
|
|
else
|
|
#endif /* ADC_VER_V5_V90 */
|
|
{
|
|
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
|
|
}
|
|
|
|
if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
|
|
{
|
|
/* Set ADC selected offset number */
|
|
LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted);
|
|
|
|
#if defined(ADC_VER_V5_V90)
|
|
if (hadc->Instance == ADC3)
|
|
{
|
|
/* Set ADC selected offset sign & saturation */
|
|
LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedOffsetSign);
|
|
LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
|
|
}
|
|
else
|
|
#endif /* ADC_VER_V5_V90 */
|
|
{
|
|
/* Set ADC selected offset signed saturation */
|
|
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
|
|
}
|
|
|
|
}
|
|
else
|
|
{
|
|
#if defined(ADC_VER_V5_V90)
|
|
if (hadc->Instance == ADC3)
|
|
{
|
|
/* Scan each offset register to check if the selected channel is targeted. */
|
|
/* If this is the case, the corresponding offset number is disabled. */
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
|
|
}
|
|
}
|
|
else
|
|
#endif /* ADC_VER_V5_V90 */
|
|
{
|
|
/* Scan each offset register to check if the selected channel is targeted. */
|
|
/* If this is the case, the corresponding offset number is disabled. */
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
|
{
|
|
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
|
{
|
|
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
|
{
|
|
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
|
|
{
|
|
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Single or differential mode */
|
|
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
{
|
|
/* Set mode single-ended or differential input of the selected ADC channel */
|
|
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
|
|
|
|
/* Configuration of differential mode */
|
|
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
|
|
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
|
|
{
|
|
/* Set sampling time of the selected ADC channel */
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
|
|
}
|
|
|
|
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
|
|
/* internal measurement paths enable: If internal channel selected, */
|
|
/* enable dedicated internal buffers and path. */
|
|
/* Note: these internal measurement paths can be disabled using */
|
|
/* HAL_ADC_DeInit(). */
|
|
|
|
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
|
|
{
|
|
/* Configuration of common ADC parameters (continuation) */
|
|
/* Software is allowed to change common parameters only when all ADCs */
|
|
/* of the common group are disabled. */
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
{
|
|
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
|
|
/* If the requested internal measurement path has already been enabled, */
|
|
/* bypass the configuration processing. */
|
|
if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
|
|
{
|
|
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
|
|
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Wait loop initialization and execution */
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles, scaling in us split to not */
|
|
/* exceed 32 bits register capacity and handle low frequency. */
|
|
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
|
while (wait_loop_index != 0UL)
|
|
{
|
|
wait_loop_index--;
|
|
}
|
|
}
|
|
}
|
|
else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
|
|
{
|
|
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
|
|
}
|
|
}
|
|
else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
|
|
{
|
|
if (ADC_VREFINT_INSTANCE(hadc))
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* nothing to do */
|
|
}
|
|
}
|
|
/* If the requested internal measurement path has already been enabled */
|
|
/* and other ADC of the common group are enabled, internal */
|
|
/* measurement paths cannot be enabled. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable ADC multimode and configure multimode parameters
|
|
* @note Possibility to update parameters on the fly:
|
|
* This function initializes multimode parameters, following
|
|
* calls to this function can be used to reconfigure some parameters
|
|
* of structure "ADC_MultiModeTypeDef" on the fly, without resetting
|
|
* the ADCs.
|
|
* The setting of these parameters is conditioned to ADC state.
|
|
* For parameters constraints, see comments of structure
|
|
* "ADC_MultiModeTypeDef".
|
|
* @note To move back configuration from multimode to single mode, ADC must
|
|
* be reset (using function HAL_ADC_Init() ).
|
|
* @param hadc Master ADC handle
|
|
* @param multimode Structure of ADC multimode configuration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
ADC_Common_TypeDef *tmpADC_Common;
|
|
ADC_HandleTypeDef tmphadcSlave;
|
|
uint32_t tmphadcSlave_conversion_on_going;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_MULTIMODE(multimode->Mode));
|
|
if (multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
{
|
|
assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
|
|
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
tmphadcSlave.State = HAL_ADC_STATE_RESET;
|
|
tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
|
|
|
|
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
|
|
|
if (tmphadcSlave.Instance == NULL)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Multimode DATA Format configuration */
|
|
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
|
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
&& (tmphadcSlave_conversion_on_going == 0UL))
|
|
{
|
|
/* Pointer to the common control register */
|
|
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
|
|
|
|
/* If multimode is selected, configure all multimode parameters. */
|
|
/* Otherwise, reset multimode parameters (can be used in case of */
|
|
/* transition from multimode to independent mode). */
|
|
if (multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
{
|
|
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
|
|
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Multimode mode selection */
|
|
/* - Multimode delay */
|
|
/* Note: Delay range depends on selected resolution: */
|
|
/* from 1 to 9 clock cycles for 16 bits */
|
|
/* from 1 to 9 clock cycles for 14 bits, */
|
|
/* from 1 to 8 clock cycles for 12 bits */
|
|
/* from 1 to 6 clock cycles for 10 and 8 bits */
|
|
/* If a higher delay is selected, it will be clipped to maximum delay */
|
|
/* range */
|
|
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
{
|
|
MODIFY_REG(tmpADC_Common->CCR,
|
|
ADC_CCR_DUAL |
|
|
ADC_CCR_DELAY,
|
|
multimode->Mode |
|
|
multimode->TwoSamplingDelay
|
|
);
|
|
}
|
|
}
|
|
else /* ADC_MODE_INDEPENDENT */
|
|
{
|
|
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
|
|
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Multimode mode selection */
|
|
/* - Multimode delay */
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
{
|
|
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
|
|
}
|
|
}
|
|
}
|
|
/* If one of the ADC sharing the same common group is enabled, no update */
|
|
/* could be done on neither of the multimode structure parameters. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable Injected Queue
|
|
* @note This function resets CFGR register JQDIS bit in order to enable the
|
|
* Injected Queue. JQDIS can be written only when ADSTART and JDSTART
|
|
* are both equal to 0 to ensure that no regular nor injected
|
|
* conversion is ongoing.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
uint32_t tmp_adc_is_conversion_on_going_regular;
|
|
uint32_t tmp_adc_is_conversion_on_going_injected;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
|
|
/* Parameter can be set only if no conversion is on-going */
|
|
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
|
|
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
|
|
)
|
|
{
|
|
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
|
|
|
|
/* Update state, clear previous result related to injected queue overflow */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
|
|
|
|
tmp_hal_status = HAL_OK;
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Injected Queue
|
|
* @note This function sets CFGR register JQDIS bit in order to disable the
|
|
* Injected Queue. JQDIS can be written only when ADSTART and JDSTART
|
|
* are both equal to 0 to ensure that no regular nor injected
|
|
* conversion is ongoing.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
uint32_t tmp_adc_is_conversion_on_going_regular;
|
|
uint32_t tmp_adc_is_conversion_on_going_injected;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
|
|
/* Parameter can be set only if no conversion is on-going */
|
|
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
|
|
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
|
|
)
|
|
{
|
|
LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
|
|
tmp_hal_status = HAL_OK;
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable ADC voltage regulator.
|
|
* @note Disabling voltage regulator allows to save power. This operation can
|
|
* be carried out only when ADC is disabled.
|
|
* @note To enable again the voltage regulator, the user is expected to
|
|
* resort to HAL_ADC_Init() API.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
{
|
|
LL_ADC_DisableInternalRegulator(hadc->Instance);
|
|
tmp_hal_status = HAL_OK;
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Enter ADC deep-power-down mode
|
|
* @note This mode is achieved in setting DEEPPWD bit and allows to save power
|
|
* in reducing leakage currents. It is particularly interesting before
|
|
* entering stop modes.
|
|
* @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
|
|
* ADC voltage regulator. This means that this API encompasses
|
|
* HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
|
|
* calibration is lost.
|
|
* @note To exit the ADC deep-power-down mode, the user is expected to
|
|
* resort to HAL_ADC_Init() API as well as to relaunch a calibration
|
|
* with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
|
|
* saved calibration factor.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
{
|
|
LL_ADC_EnableDeepPowerDown(hadc->Instance);
|
|
tmp_hal_status = HAL_OK;
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_ADC_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|