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<?xml version='1.0' encoding='utf-8'?>
<!--
Copyright (c) 2021 STMicroelectronics.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xsi:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32H7A3x</name>
<version>2.3</version>
<description>STM32H7A3x</description>
<cpu>
<name>CM7</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>AC</name>
<description>Access control</description>
<groupName>AC</groupName>
<baseAddress>0xE000EF90</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1D</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ITCMCR</name>
<displayName>ITCMCR</displayName>
<description>Instruction and Data Tightly-Coupled Memory
Control Registers</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMW</name>
<description>RMW</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETEN</name>
<description>RETEN</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SZ</name>
<description>SZ</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTCMCR</name>
<displayName>DTCMCR</displayName>
<description>Instruction and Data Tightly-Coupled Memory
Control Registers</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMW</name>
<description>RMW</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETEN</name>
<description>RETEN</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SZ</name>
<description>SZ</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBPCR</name>
<displayName>AHBPCR</displayName>
<description>AHBP Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>EN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SZ</name>
<description>SZ</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>CACR</name>
<displayName>CACR</displayName>
<description>Auxiliary Cache Control
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>SIWT</name>
<description>SIWT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCEN</name>
<description>ECCEN</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCEWT</name>
<description>FORCEWT</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBSCR</name>
<displayName>AHBSCR</displayName>
<description>AHB Slave Control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>CTL</name>
<description>CTL</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TPRI</name>
<description>TPRI</description>
<bitOffset>2</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>INITCOUNT</name>
<description>INITCOUNT</description>
<bitOffset>11</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>ABFSR</name>
<displayName>ABFSR</displayName>
<description>Auxiliary Bus Fault Status
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ITCM</name>
<description>ITCM</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTCM</name>
<description>DTCM</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBP</name>
<description>AHBP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AXIM</name>
<description>AXIM</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPPB</name>
<description>EPPB</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AXIMTYPE</name>
<description>AXIMTYPE</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC1</name>
<description>Analog to Digital Converter</description>
<groupName>ADC</groupName>
<baseAddress>0x40022000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x100</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC1_2</name>
<description>ADC1 and ADC2 global interrupt</description>
<value>18</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>ADC interrupt and status
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQOVF</name>
<description>ADC group injected contexts queue
overflow flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3</name>
<description>ADC analog watchdog 3 flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2</name>
<description>ADC analog watchdog 2 flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1</name>
<description>ADC analog watchdog 1 flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOS</name>
<description>ADC group injected end of sequence
conversions flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC</name>
<description>ADC group injected end of unitary
conversion flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>ADC group regular overrun
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOS</name>
<description>ADC group regular end of sequence
conversions flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC</name>
<description>ADC group regular end of unitary
conversion flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMP</name>
<description>ADC group regular end of sampling
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDY</name>
<description>ADC ready flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>ADC interrupt enable register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQOVFIE</name>
<description>ADC group injected contexts queue
overflow interrupt</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3IE</name>
<description>ADC analog watchdog 3
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2IE</name>
<description>ADC analog watchdog 2
interrupt</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1IE</name>
<description>ADC analog watchdog 1
interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOSIE</name>
<description>ADC group injected end of sequence
conversions interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOCIE</name>
<description>ADC group injected end of unitary
conversion interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRIE</name>
<description>ADC group regular overrun
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSIE</name>
<description>ADC group regular end of sequence
conversions interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOCIE</name>
<description>ADC group regular end of unitary
conversion interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMPIE</name>
<description>ADC group regular end of sampling
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDYIE</name>
<description>ADC ready interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>ADC control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>ADCAL</name>
<description>ADC calibration</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCALDIF</name>
<description>ADC differential mode for
calibration</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEEPPWD</name>
<description>ADC deep power down enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADVREGEN</name>
<description>ADC voltage regulator
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW6</name>
<description>Linearity calibration ready Word
6</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW5</name>
<description>Linearity calibration ready Word
5</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW4</name>
<description>Linearity calibration ready Word
4</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW3</name>
<description>Linearity calibration ready Word
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW2</name>
<description>Linearity calibration ready Word
2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW1</name>
<description>Linearity calibration ready Word
1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCALLIN</name>
<description>Linearity calibration</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOOST</name>
<description>Boost mode control</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JADSTP</name>
<description>ADC group injected conversion
stop</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSTP</name>
<description>ADC group regular conversion
stop</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JADSTART</name>
<description>ADC group injected conversion
start</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSTART</name>
<description>ADC group regular conversion
start</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDIS</name>
<description>ADC disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADEN</name>
<description>ADC enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>ADC configuration register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<fields>
<field>
<name>JQDIS</name>
<description>ADC group injected contexts queue
disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWDCH1CH</name>
<description>ADC analog watchdog 1 monitored channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JAUTO</name>
<description>ADC group injected automatic trigger
mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JAWD1EN</name>
<description>ADC analog watchdog 1 enable on scope
ADC group injected</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1EN</name>
<description>ADC analog watchdog 1 enable on scope
ADC group regular</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1SGL</name>
<description>ADC analog watchdog 1 monitoring a
single channel or all channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JQM</name>
<description>ADC group injected contexts queue
mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JDISCEN</name>
<description>ADC group injected sequencer
discontinuous mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISCNUM</name>
<description>ADC group regular sequencer
discontinuous number of ranks</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DISCEN</name>
<description>ADC group regular sequencer
discontinuous mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTDLY</name>
<description>ADC low power auto wait</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>ADC group regular continuous conversion
mode</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRMOD</name>
<description>ADC group regular overrun
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEN</name>
<description>ADC group regular external trigger
polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EXTSEL</name>
<description>ADC group regular external trigger
source</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RES</name>
<description>ADC data resolution</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMNGT</name>
<description>ADC DMA transfer enable</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR2</name>
<displayName>CFGR2</displayName>
<description>ADC configuration register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ROVSE</name>
<description>ADC oversampler enable on scope ADC
group regular</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JOVSE</name>
<description>ADC oversampler enable on scope ADC
group injected</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVSS</name>
<description>ADC oversampling shift</description>
<bitOffset>5</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TROVS</name>
<description>ADC oversampling discontinuous mode
(triggered mode) for ADC group regular</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVSM</name>
<description>Regular Oversampling mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSHIFT1</name>
<description>Right-shift data after Offset 1
correction</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSHIFT2</name>
<description>Right-shift data after Offset 2
correction</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSHIFT3</name>
<description>Right-shift data after Offset 3
correction</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSHIFT4</name>
<description>Right-shift data after Offset 4
correction</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSR</name>
<description>Oversampling ratio</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>LSHIFT</name>
<description>Left shift factor</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR1</name>
<displayName>SMPR1</displayName>
<description>ADC sampling time register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP9</name>
<description>ADC channel 9 sampling time
selection</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP8</name>
<description>ADC channel 8 sampling time
selection</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP7</name>
<description>ADC channel 7 sampling time
selection</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP6</name>
<description>ADC channel 6 sampling time
selection</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP5</name>
<description>ADC channel 5 sampling time
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP4</name>
<description>ADC channel 4 sampling time
selection</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP3</name>
<description>ADC channel 3 sampling time
selection</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP2</name>
<description>ADC channel 2 sampling time
selection</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP1</name>
<description>ADC channel 1 sampling time
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR2</name>
<displayName>SMPR2</displayName>
<description>ADC sampling time register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP19</name>
<description>ADC channel 18 sampling time
selection</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP18</name>
<description>ADC channel 18 sampling time
selection</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP17</name>
<description>ADC channel 17 sampling time
selection</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP16</name>
<description>ADC channel 16 sampling time
selection</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP15</name>
<description>ADC channel 15 sampling time
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP14</name>
<description>ADC channel 14 sampling time
selection</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP13</name>
<description>ADC channel 13 sampling time
selection</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP12</name>
<description>ADC channel 12 sampling time
selection</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP11</name>
<description>ADC channel 11 sampling time
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP10</name>
<description>ADC channel 10 sampling time
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>LTR1</name>
<displayName>LTR1</displayName>
<description>ADC analog watchdog 1 threshold
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LTR1</name>
<description>ADC analog watchdog 1 threshold
low</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>LHTR1</name>
<displayName>LHTR1</displayName>
<description>ADC analog watchdog 2 threshold
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x03FFFFFF</resetValue>
<fields>
<field>
<name>LHTR1</name>
<description>ADC analog watchdog 2 threshold
low</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR1</name>
<displayName>SQR1</displayName>
<description>ADC group regular sequencer ranks register
1</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ4</name>
<description>ADC group regular sequencer rank
4</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ3</name>
<description>ADC group regular sequencer rank
3</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ2</name>
<description>ADC group regular sequencer rank
2</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ1</name>
<description>ADC group regular sequencer rank
1</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>L3</name>
<description>L3</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR2</name>
<displayName>SQR2</displayName>
<description>ADC group regular sequencer ranks register
2</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ9</name>
<description>ADC group regular sequencer rank
9</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ8</name>
<description>ADC group regular sequencer rank
8</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ7</name>
<description>ADC group regular sequencer rank
7</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ6</name>
<description>ADC group regular sequencer rank
6</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ5</name>
<description>ADC group regular sequencer rank
5</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR3</name>
<displayName>SQR3</displayName>
<description>ADC group regular sequencer ranks register
3</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ14</name>
<description>ADC group regular sequencer rank
14</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ13</name>
<description>ADC group regular sequencer rank
13</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ12</name>
<description>ADC group regular sequencer rank
12</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ11</name>
<description>ADC group regular sequencer rank
11</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ10</name>
<description>ADC group regular sequencer rank
10</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR4</name>
<displayName>SQR4</displayName>
<description>ADC group regular sequencer ranks register
4</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ16</name>
<description>ADC group regular sequencer rank
16</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ15</name>
<description>ADC group regular sequencer rank
15</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>ADC group regular conversion data
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDATA</name>
<description>ADC group regular conversion
data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JSQR</name>
<displayName>JSQR</displayName>
<description>ADC group injected sequencer
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JSQ4</name>
<description>ADC group injected sequencer rank
4</description>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ3</name>
<description>ADC group injected sequencer rank
3</description>
<bitOffset>21</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ2</name>
<description>ADC group injected sequencer rank
2</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ1</name>
<description>ADC group injected sequencer rank
1</description>
<bitOffset>9</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JEXTEN</name>
<description>ADC group injected external trigger
polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>JEXTSEL</name>
<description>ADC group injected external trigger
source</description>
<bitOffset>2</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JL</name>
<description>ADC group injected sequencer scan
length</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR1</name>
<displayName>OFR1</displayName>
<description>ADC offset number 1 register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSATE</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset
level</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR2</name>
<displayName>OFR2</displayName>
<description>ADC offset number 2 register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSATE</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset
level</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR3</name>
<displayName>OFR3</displayName>
<description>ADC offset number 3 register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSATE</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset
level</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR4</name>
<displayName>OFR4</displayName>
<description>ADC offset number 4 register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSATE</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset
level</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR1</name>
<displayName>JDR1</displayName>
<description>ADC group injected sequencer rank 1
register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA1</name>
<description>ADC group injected sequencer rank 1
conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR2</name>
<displayName>JDR2</displayName>
<description>ADC group injected sequencer rank 2
register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA2</name>
<description>ADC group injected sequencer rank 2
conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR3</name>
<displayName>JDR3</displayName>
<description>ADC group injected sequencer rank 3
register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA3</name>
<description>ADC group injected sequencer rank 3
conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR4</name>
<displayName>JDR4</displayName>
<description>ADC group injected sequencer rank 4
register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA4</name>
<description>ADC group injected sequencer rank 4
conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWD2CR</name>
<displayName>AWD2CR</displayName>
<description>ADC analog watchdog 2 configuration
register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AWD2CH</name>
<description>ADC analog watchdog 2 monitored channel
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWD3CR</name>
<displayName>AWD3CR</displayName>
<description>ADC analog watchdog 3 configuration
register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AWD3CH</name>
<description>ADC analog watchdog 3 monitored channel
selection</description>
<bitOffset>1</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIFSEL</name>
<displayName>DIFSEL</displayName>
<description>ADC channel differential or single-ended
mode selection register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIFSEL</name>
<description>ADC channel differential or single-ended
mode for channel</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALFACT</name>
<displayName>CALFACT</displayName>
<description>ADC calibration factors
register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALFACT_D</name>
<description>ADC calibration factor in differential
mode</description>
<bitOffset>16</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>CALFACT_S</name>
<description>ADC calibration factor in single-ended
mode</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCSEL</name>
<displayName>PCSEL</displayName>
<description>ADC pre channel selection
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCSEL</name>
<description>Channel x (VINP[i]) pre
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LTR2</name>
<displayName>LTR2</displayName>
<description>ADC watchdog lower threshold register
2</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LTR2</name>
<description>Analog watchdog 2 lower
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>HTR2</name>
<displayName>HTR2</displayName>
<description>ADC watchdog higher threshold register
2</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x03FFFFFF</resetValue>
<fields>
<field>
<name>HTR2</name>
<description>Analog watchdog 2 higher
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>LTR3</name>
<displayName>LTR3</displayName>
<description>ADC watchdog lower threshold register
3</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LTR3</name>
<description>Analog watchdog 3 lower
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>HTR3</name>
<displayName>HTR3</displayName>
<description>ADC watchdog higher threshold register
3</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x03FFFFFF</resetValue>
<fields>
<field>
<name>HTR3</name>
<description>Analog watchdog 3 higher
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALFACT2</name>
<displayName>CALFACT2</displayName>
<description>ADC Calibration Factor register
2</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LINCALFACT</name>
<description>Linearity Calibration
Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC2</name>
<description>Analog to Digital Converter</description>
<groupName>ADC</groupName>
<baseAddress>0x40022100</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x100</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>ADC interrupt and status
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQOVF</name>
<description>ADC group injected contexts queue
overflow flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3</name>
<description>ADC analog watchdog 3 flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2</name>
<description>ADC analog watchdog 2 flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1</name>
<description>ADC analog watchdog 1 flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOS</name>
<description>ADC group injected end of sequence
conversions flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC</name>
<description>ADC group injected end of unitary
conversion flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>ADC group regular overrun
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOS</name>
<description>ADC group regular end of sequence
conversions flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC</name>
<description>ADC group regular end of unitary
conversion flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMP</name>
<description>ADC group regular end of sampling
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDY</name>
<description>ADC ready flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>ADC interrupt enable register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQOVFIE</name>
<description>ADC group injected contexts queue
overflow interrupt</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3IE</name>
<description>ADC analog watchdog 3
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2IE</name>
<description>ADC analog watchdog 2
interrupt</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1IE</name>
<description>ADC analog watchdog 1
interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOSIE</name>
<description>ADC group injected end of sequence
conversions interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOCIE</name>
<description>ADC group injected end of unitary
conversion interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRIE</name>
<description>ADC group regular overrun
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSIE</name>
<description>ADC group regular end of sequence
conversions interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOCIE</name>
<description>ADC group regular end of unitary
conversion interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMPIE</name>
<description>ADC group regular end of sampling
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDYIE</name>
<description>ADC ready interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>ADC control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADCAL</name>
<description>ADC calibration</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCALDIF</name>
<description>ADC differential mode for
calibration</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEEPPWD</name>
<description>ADC deep power down enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADVREGEN</name>
<description>ADC voltage regulator
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW6</name>
<description>Linearity calibration ready Word
6</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW5</name>
<description>Linearity calibration ready Word
5</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW4</name>
<description>Linearity calibration ready Word
4</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW3</name>
<description>Linearity calibration ready Word
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW2</name>
<description>Linearity calibration ready Word
2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINCALRDYW1</name>
<description>Linearity calibration ready Word
1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCALLIN</name>
<description>Linearity calibration</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOOST</name>
<description>Boost mode control</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JADSTP</name>
<description>ADC group injected conversion
stop</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSTP</name>
<description>ADC group regular conversion
stop</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JADSTART</name>
<description>ADC group injected conversion
start</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSTART</name>
<description>ADC group regular conversion
start</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDIS</name>
<description>ADC disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADEN</name>
<description>ADC enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>ADC configuration register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQDIS</name>
<description>ADC group injected contexts queue
disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWDCH1CH</name>
<description>ADC analog watchdog 1 monitored channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JAUTO</name>
<description>ADC group injected automatic trigger
mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JAWD1EN</name>
<description>ADC analog watchdog 1 enable on scope
ADC group injected</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1EN</name>
<description>ADC analog watchdog 1 enable on scope
ADC group regular</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1SGL</name>
<description>ADC analog watchdog 1 monitoring a
single channel or all channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JQM</name>
<description>ADC group injected contexts queue
mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JDISCEN</name>
<description>ADC group injected sequencer
discontinuous mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISCNUM</name>
<description>ADC group regular sequencer
discontinuous number of ranks</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DISCEN</name>
<description>ADC group regular sequencer
discontinuous mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTDLY</name>
<description>ADC low power auto wait</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>ADC group regular continuous conversion
mode</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRMOD</name>
<description>ADC group regular overrun
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEN</name>
<description>ADC group regular external trigger
polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EXTSEL</name>
<description>ADC group regular external trigger
source</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RES</name>
<description>ADC data resolution</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMNGT</name>
<description>ADC DMA transfer enable</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR2</name>
<displayName>CFGR2</displayName>
<description>ADC configuration register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ROVSE</name>
<description>ADC oversampler enable on scope ADC
group regular</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JOVSE</name>
<description>ADC oversampler enable on scope ADC
group injected</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVSS</name>
<description>ADC oversampling shift</description>
<bitOffset>5</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TROVS</name>
<description>ADC oversampling discontinuous mode
(triggered mode) for ADC group regular</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVSM</name>
<description>Regular Oversampling mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSHIFT1</name>
<description>Right-shift data after Offset 1
correction</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSHIFT2</name>
<description>Right-shift data after Offset 2
correction</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSHIFT3</name>
<description>Right-shift data after Offset 3
correction</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSHIFT4</name>
<description>Right-shift data after Offset 4
correction</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSR</name>
<description>Oversampling ratio</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>LSHIFT</name>
<description>Left shift factor</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR1</name>
<displayName>SMPR1</displayName>
<description>ADC sampling time register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP9</name>
<description>ADC channel 9 sampling time
selection</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP8</name>
<description>ADC channel 8 sampling time
selection</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP7</name>
<description>ADC channel 7 sampling time
selection</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP6</name>
<description>ADC channel 6 sampling time
selection</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP5</name>
<description>ADC channel 5 sampling time
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP4</name>
<description>ADC channel 4 sampling time
selection</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP3</name>
<description>ADC channel 3 sampling time
selection</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP2</name>
<description>ADC channel 2 sampling time
selection</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP1</name>
<description>ADC channel 1 sampling time
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR2</name>
<displayName>SMPR2</displayName>
<description>ADC sampling time register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP19</name>
<description>ADC channel 18 sampling time
selection</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP18</name>
<description>ADC channel 18 sampling time
selection</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP17</name>
<description>ADC channel 17 sampling time
selection</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP16</name>
<description>ADC channel 16 sampling time
selection</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP15</name>
<description>ADC channel 15 sampling time
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP14</name>
<description>ADC channel 14 sampling time
selection</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP13</name>
<description>ADC channel 13 sampling time
selection</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP12</name>
<description>ADC channel 12 sampling time
selection</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP11</name>
<description>ADC channel 11 sampling time
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP10</name>
<description>ADC channel 10 sampling time
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>LTR1</name>
<displayName>LTR1</displayName>
<description>ADC analog watchdog 1 threshold
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFF0000</resetValue>
<fields>
<field>
<name>LTR1</name>
<description>ADC analog watchdog 1 threshold
low</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>LHTR1</name>
<displayName>LHTR1</displayName>
<description>ADC analog watchdog 2 threshold
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFF0000</resetValue>
<fields>
<field>
<name>LHTR1</name>
<description>ADC analog watchdog 2 threshold
low</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR1</name>
<displayName>SQR1</displayName>
<description>ADC group regular sequencer ranks register
1</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ4</name>
<description>ADC group regular sequencer rank
4</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ3</name>
<description>ADC group regular sequencer rank
3</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ2</name>
<description>ADC group regular sequencer rank
2</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ1</name>
<description>ADC group regular sequencer rank
1</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>L3</name>
<description>L3</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR2</name>
<displayName>SQR2</displayName>
<description>ADC group regular sequencer ranks register
2</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ9</name>
<description>ADC group regular sequencer rank
9</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ8</name>
<description>ADC group regular sequencer rank
8</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ7</name>
<description>ADC group regular sequencer rank
7</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ6</name>
<description>ADC group regular sequencer rank
6</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ5</name>
<description>ADC group regular sequencer rank
5</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR3</name>
<displayName>SQR3</displayName>
<description>ADC group regular sequencer ranks register
3</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ14</name>
<description>ADC group regular sequencer rank
14</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ13</name>
<description>ADC group regular sequencer rank
13</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ12</name>
<description>ADC group regular sequencer rank
12</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ11</name>
<description>ADC group regular sequencer rank
11</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ10</name>
<description>ADC group regular sequencer rank
10</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR4</name>
<displayName>SQR4</displayName>
<description>ADC group regular sequencer ranks register
4</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ16</name>
<description>ADC group regular sequencer rank
16</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ15</name>
<description>ADC group regular sequencer rank
15</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>ADC group regular conversion data
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDATA</name>
<description>ADC group regular conversion
data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JSQR</name>
<displayName>JSQR</displayName>
<description>ADC group injected sequencer
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JSQ4</name>
<description>ADC group injected sequencer rank
4</description>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ3</name>
<description>ADC group injected sequencer rank
3</description>
<bitOffset>21</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ2</name>
<description>ADC group injected sequencer rank
2</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ1</name>
<description>ADC group injected sequencer rank
1</description>
<bitOffset>9</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JEXTEN</name>
<description>ADC group injected external trigger
polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>JEXTSEL</name>
<description>ADC group injected external trigger
source</description>
<bitOffset>2</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JL</name>
<description>ADC group injected sequencer scan
length</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR1</name>
<displayName>OFR1</displayName>
<description>ADC offset number 1 register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSATE</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset
level</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR2</name>
<displayName>OFR2</displayName>
<description>ADC offset number 2 register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSATE</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset
level</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR3</name>
<displayName>OFR3</displayName>
<description>ADC offset number 3 register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSATE</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset
level</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR4</name>
<displayName>OFR4</displayName>
<description>ADC offset number 4 register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSATE</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel
selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset
level</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR1</name>
<displayName>JDR1</displayName>
<description>ADC group injected sequencer rank 1
register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA1</name>
<description>ADC group injected sequencer rank 1
conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR2</name>
<displayName>JDR2</displayName>
<description>ADC group injected sequencer rank 2
register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA2</name>
<description>ADC group injected sequencer rank 2
conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR3</name>
<displayName>JDR3</displayName>
<description>ADC group injected sequencer rank 3
register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA3</name>
<description>ADC group injected sequencer rank 3
conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR4</name>
<displayName>JDR4</displayName>
<description>ADC group injected sequencer rank 4
register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA4</name>
<description>ADC group injected sequencer rank 4
conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWD2CR</name>
<displayName>AWD2CR</displayName>
<description>ADC analog watchdog 2 configuration
register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AWD2CH</name>
<description>ADC analog watchdog 2 monitored channel
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWD3CR</name>
<displayName>AWD3CR</displayName>
<description>ADC analog watchdog 3 configuration
register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AWD3CH</name>
<description>ADC analog watchdog 3 monitored channel
selection</description>
<bitOffset>1</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIFSEL</name>
<displayName>DIFSEL</displayName>
<description>ADC channel differential or single-ended
mode selection register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIFSEL</name>
<description>ADC channel differential or single-ended
mode for channel</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALFACT</name>
<displayName>CALFACT</displayName>
<description>ADC calibration factors
register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALFACT_D</name>
<description>ADC calibration factor in differential
mode</description>
<bitOffset>16</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>CALFACT_S</name>
<description>ADC calibration factor in single-ended
mode</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCSEL</name>
<displayName>PCSEL</displayName>
<description>ADC pre channel selection
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCSEL</name>
<description>Channel x (VINP[i]) pre
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LTR2</name>
<displayName>LTR2</displayName>
<description>ADC watchdog lower threshold register
2</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LTR2</name>
<description>Analog watchdog 2 lower
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>HTR2</name>
<displayName>HTR2</displayName>
<description>ADC watchdog higher threshold register
2</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HTR2</name>
<description>Analog watchdog 2 higher
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>LTR3</name>
<displayName>LTR3</displayName>
<description>ADC watchdog lower threshold register
3</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LTR3</name>
<description>Analog watchdog 3 lower
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>HTR3</name>
<displayName>HTR3</displayName>
<description>ADC watchdog higher threshold register
3</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HTR3</name>
<description>Analog watchdog 3 higher
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALFACT2</name>
<displayName>CALFACT2</displayName>
<description>ADC Calibration Factor register
2</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LINCALFACT</name>
<description>Linearity Calibration
Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC12_Common</name>
<description>Analog-to-Digital Converter</description>
<groupName>ADC</groupName>
<baseAddress>0x40022300</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x100</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>ADC Common status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADRDY_MST</name>
<description>Master ADC ready</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMP_MST</name>
<description>End of Sampling phase flag of the master
ADC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC_MST</name>
<description>End of regular conversion of the master
ADC</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOS_MST</name>
<description>End of regular sequence flag of the
master ADC</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_MST</name>
<description>Overrun flag of the master
ADC</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC_MST</name>
<description>End of injected conversion flag of the
master ADC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOS_MST</name>
<description>End of injected sequence flag of the
master ADC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1_MST</name>
<description>Analog watchdog 1 flag of the master
ADC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2_MST</name>
<description>Analog watchdog 2 flag of the master
ADC</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3_MST</name>
<description>Analog watchdog 3 flag of the master
ADC</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JQOVF_MST</name>
<description>Injected Context Queue Overflow flag of
the master ADC</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDY_SLV</name>
<description>Slave ADC ready</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMP_SLV</name>
<description>End of Sampling phase flag of the slave
ADC</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC_SLV</name>
<description>End of regular conversion of the slave
ADC</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOS_SLV</name>
<description>End of regular sequence flag of the
slave ADC</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_SLV</name>
<description>Overrun flag of the slave
ADC</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC_SLV</name>
<description>End of injected conversion flag of the
slave ADC</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOS_SLV</name>
<description>End of injected sequence flag of the
slave ADC</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1_SLV</name>
<description>Analog watchdog 1 flag of the slave
ADC</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2_SLV</name>
<description>Analog watchdog 2 flag of the slave
ADC</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3_SLV</name>
<description>Analog watchdog 3 flag of the slave
ADC</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JQOVF_SLV</name>
<description>Injected Context Queue Overflow flag of
the slave ADC</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>ADC common control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUAL</name>
<description>Dual ADC mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DELAY</name>
<description>Delay between 2 sampling
phases</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DAMDF</name>
<description>Dual ADC Mode Data Format</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKMODE</name>
<description>ADC clock mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>ADC prescaler</description>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VREFEN</name>
<description>VREFINT enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSENSEEN</name>
<description>Temperature sensor enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBATEN</name>
<description>VBAT enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDR</name>
<displayName>CDR</displayName>
<description>ADC common regular data register for dual
and triple modes</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDATA_SLV</name>
<description>Regular data of the slave
ADC</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>RDATA_MST</name>
<description>Regular data of the master
ADC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AXI</name>
<description>AXI interconnect registers</description>
<groupName>AXI</groupName>
<baseAddress>0x51000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x100000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>AXI_PERIPH_ID_4</name>
<displayName>AXI_PERIPH_ID_4</displayName>
<description>AXI interconnect - peripheral ID4
register</description>
<addressOffset>0x1FD0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>JEP106CON</name>
<description>JEP106 continuation code</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>KCOUNT4</name>
<description>Register file size</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_PERIPH_ID_0</name>
<displayName>AXI_PERIPH_ID_0</displayName>
<description>AXI interconnect - peripheral ID0
register</description>
<addressOffset>0x1FE0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>PARTNUM</name>
<description>Peripheral part number bits 0 to
7</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_PERIPH_ID_1</name>
<displayName>AXI_PERIPH_ID_1</displayName>
<description>AXI interconnect - peripheral ID1
register</description>
<addressOffset>0x1FE4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>PARTNUM</name>
<description>Peripheral part number bits 8 to
11</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>JEP106I</name>
<description>JEP106 identity bits 0 to
3</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_PERIPH_ID_2</name>
<displayName>AXI_PERIPH_ID_2</displayName>
<description>AXI interconnect - peripheral ID2
register</description>
<addressOffset>0x1FE8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>JEP106ID</name>
<description>JEP106 Identity bits 4 to
6</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>JEDEC</name>
<description>JEP106 code flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REVISION</name>
<description>Peripheral revision number</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_PERIPH_ID_3</name>
<displayName>AXI_PERIPH_ID_3</displayName>
<description>AXI interconnect - peripheral ID3
register</description>
<addressOffset>0x1FEC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>CUST_MOD_NUM</name>
<description>Customer modification</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>REV_AND</name>
<description>Customer version</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_COMP_ID_0</name>
<displayName>AXI_COMP_ID_0</displayName>
<description>AXI interconnect - component ID0
register</description>
<addressOffset>0x1FF0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>PREAMBLE</name>
<description>Preamble bits 0 to 7</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_COMP_ID_1</name>
<displayName>AXI_COMP_ID_1</displayName>
<description>AXI interconnect - component ID1
register</description>
<addressOffset>0x1FF4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>PREAMBLE</name>
<description>Preamble bits 8 to 11</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLASS</name>
<description>Component class</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_COMP_ID_2</name>
<displayName>AXI_COMP_ID_2</displayName>
<description>AXI interconnect - component ID2
register</description>
<addressOffset>0x1FF8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>PREAMBLE</name>
<description>Preamble bits 12 to 19</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_COMP_ID_3</name>
<displayName>AXI_COMP_ID_3</displayName>
<description>AXI interconnect - component ID3
register</description>
<addressOffset>0x1FFC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>PREAMBLE</name>
<description>Preamble bits 20 to 27</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG1_FN_MOD_ISS_BM</name>
<displayName>AXI_TARG1_FN_MOD_ISS_BM</displayName>
<description>AXI interconnect - TARG x bus matrix issuing
functionality register</description>
<addressOffset>0x2008</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>READ_ISS_OVERRIDE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Switch matrix write issuing override for
target</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG2_FN_MOD_ISS_BM</name>
<displayName>AXI_TARG2_FN_MOD_ISS_BM</displayName>
<description>AXI interconnect - TARG x bus matrix issuing
functionality register</description>
<addressOffset>0x3008</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>READ_ISS_OVERRIDE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Switch matrix write issuing override for
target</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG3_FN_MOD_ISS_BM</name>
<displayName>AXI_TARG3_FN_MOD_ISS_BM</displayName>
<description>AXI interconnect - TARG x bus matrix issuing
functionality register</description>
<addressOffset>0x4008</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>READ_ISS_OVERRIDE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Switch matrix write issuing override for
target</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG4_FN_MOD_ISS_BM</name>
<displayName>AXI_TARG4_FN_MOD_ISS_BM</displayName>
<description>AXI interconnect - TARG x bus matrix issuing
functionality register</description>
<addressOffset>0x5008</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>READ_ISS_OVERRIDE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Switch matrix write issuing override for
target</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG5_FN_MOD_ISS_BM</name>
<displayName>AXI_TARG5_FN_MOD_ISS_BM</displayName>
<description>AXI interconnect - TARG x bus matrix issuing
functionality register</description>
<addressOffset>0x6008</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>READ_ISS_OVERRIDE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Switch matrix write issuing override for
target</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG6_FN_MOD_ISS_BM</name>
<displayName>AXI_TARG6_FN_MOD_ISS_BM</displayName>
<description>AXI interconnect - TARG x bus matrix issuing
functionality register</description>
<addressOffset>0x7008</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>READ_ISS_OVERRIDE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Switch matrix write issuing override for
target</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG7_FN_MOD_ISS_BM</name>
<displayName>AXI_TARG7_FN_MOD_ISS_BM</displayName>
<description>AXI interconnect - TARG x bus matrix issuing
functionality register</description>
<addressOffset>0x800C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>READ_ISS_OVERRIDE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Switch matrix write issuing override for
target</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG1_FN_MOD2</name>
<displayName>AXI_TARG1_FN_MOD2</displayName>
<description>AXI interconnect - TARG x bus matrix
functionality 2 register</description>
<addressOffset>0x2024</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>BYPASS_MERGE</name>
<description>Disable packing of beats to match the
output data width</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG2_FN_MOD2</name>
<displayName>AXI_TARG2_FN_MOD2</displayName>
<description>AXI interconnect - TARG x bus matrix
functionality 2 register</description>
<addressOffset>0x3024</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>BYPASS_MERGE</name>
<description>Disable packing of beats to match the
output data width</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG7_FN_MOD2</name>
<displayName>AXI_TARG7_FN_MOD2</displayName>
<description>AXI interconnect - TARG x bus matrix
functionality 2 register</description>
<addressOffset>0x8024</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>BYPASS_MERGE</name>
<description>Disable packing of beats to match the
output data width</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG1_FN_MOD_LB</name>
<displayName>AXI_TARG1_FN_MOD_LB</displayName>
<description>AXI interconnect - TARG x long burst
functionality modification</description>
<addressOffset>0x202C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>FN_MOD_LB</name>
<description>Controls burst breaking of long
bursts</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG2_FN_MOD_LB</name>
<displayName>AXI_TARG2_FN_MOD_LB</displayName>
<description>AXI interconnect - TARG x long burst
functionality modification</description>
<addressOffset>0x302C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>FN_MOD_LB</name>
<description>Controls burst breaking of long
bursts</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG1_FN_MOD</name>
<displayName>AXI_TARG1_FN_MOD</displayName>
<description>AXI interconnect - TARG x long burst
functionality modification</description>
<addressOffset>0x2108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override AMIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override AMIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG2_FN_MOD</name>
<displayName>AXI_TARG2_FN_MOD</displayName>
<description>AXI interconnect - TARG x long burst
functionality modification</description>
<addressOffset>0x3108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override AMIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override AMIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_TARG7_FN_MOD</name>
<displayName>AXI_TARG7_FN_MOD</displayName>
<description>AXI interconnect - TARG x long burst
functionality modification</description>
<addressOffset>0x8108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override AMIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override AMIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI1_FN_MOD2</name>
<displayName>AXI_INI1_FN_MOD2</displayName>
<description>AXI interconnect - INI x functionality
modification 2 register</description>
<addressOffset>0x42024</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>BYPASS_MERGE</name>
<description>Disables alteration of transactions by
the up-sizer unless required by the
protocol</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI3_FN_MOD2</name>
<displayName>AXI_INI3_FN_MOD2</displayName>
<description>AXI interconnect - INI x functionality
modification 2 register</description>
<addressOffset>0x44024</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>BYPASS_MERGE</name>
<description>Disables alteration of transactions by
the up-sizer unless required by the
protocol</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI1_FN_MOD_AHB</name>
<displayName>AXI_INI1_FN_MOD_AHB</displayName>
<description>AXI interconnect - INI x AHB functionality
modification register</description>
<addressOffset>0x42028</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>RD_INC_OVERRIDE</name>
<description>Converts all AHB-Lite write transactions
to a series of single beat AXI</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WR_INC_OVERRIDE</name>
<description>Converts all AHB-Lite read transactions
to a series of single beat AXI</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI3_FN_MOD_AHB</name>
<displayName>AXI_INI3_FN_MOD_AHB</displayName>
<description>AXI interconnect - INI x AHB functionality
modification register</description>
<addressOffset>0x44028</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>RD_INC_OVERRIDE</name>
<description>Converts all AHB-Lite write transactions
to a series of single beat AXI</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WR_INC_OVERRIDE</name>
<description>Converts all AHB-Lite read transactions
to a series of single beat AXI</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI1_READ_QOS</name>
<displayName>AXI_INI1_READ_QOS</displayName>
<description>AXI interconnect - INI x read QoS
register</description>
<addressOffset>0x42100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AR_QOS</name>
<description>Read channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI2_READ_QOS</name>
<displayName>AXI_INI2_READ_QOS</displayName>
<description>AXI interconnect - INI x read QoS
register</description>
<addressOffset>0x43100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AR_QOS</name>
<description>Read channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI3_READ_QOS</name>
<displayName>AXI_INI3_READ_QOS</displayName>
<description>AXI interconnect - INI x read QoS
register</description>
<addressOffset>0x44100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AR_QOS</name>
<description>Read channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI4_READ_QOS</name>
<displayName>AXI_INI4_READ_QOS</displayName>
<description>AXI interconnect - INI x read QoS
register</description>
<addressOffset>0x45100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AR_QOS</name>
<description>Read channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI5_READ_QOS</name>
<displayName>AXI_INI5_READ_QOS</displayName>
<description>AXI interconnect - INI x read QoS
register</description>
<addressOffset>0x46100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AR_QOS</name>
<description>Read channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI6_READ_QOS</name>
<displayName>AXI_INI6_READ_QOS</displayName>
<description>AXI interconnect - INI x read QoS
register</description>
<addressOffset>0x47100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AR_QOS</name>
<description>Read channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI1_WRITE_QOS</name>
<displayName>AXI_INI1_WRITE_QOS</displayName>
<description>AXI interconnect - INI x write QoS
register</description>
<addressOffset>0x42104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AW_QOS</name>
<description>Write channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI2_WRITE_QOS</name>
<displayName>AXI_INI2_WRITE_QOS</displayName>
<description>AXI interconnect - INI x write QoS
register</description>
<addressOffset>0x43104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AW_QOS</name>
<description>Write channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI3_WRITE_QOS</name>
<displayName>AXI_INI3_WRITE_QOS</displayName>
<description>AXI interconnect - INI x write QoS
register</description>
<addressOffset>0x44104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AW_QOS</name>
<description>Write channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI4_WRITE_QOS</name>
<displayName>AXI_INI4_WRITE_QOS</displayName>
<description>AXI interconnect - INI x write QoS
register</description>
<addressOffset>0x45104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AW_QOS</name>
<description>Write channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI5_WRITE_QOS</name>
<displayName>AXI_INI5_WRITE_QOS</displayName>
<description>AXI interconnect - INI x write QoS
register</description>
<addressOffset>0x46104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AW_QOS</name>
<description>Write channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI6_WRITE_QOS</name>
<displayName>AXI_INI6_WRITE_QOS</displayName>
<description>AXI interconnect - INI x write QoS
register</description>
<addressOffset>0x47104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>AW_QOS</name>
<description>Write channel QoS setting</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI1_FN_MOD</name>
<displayName>AXI_INI1_FN_MOD</displayName>
<description>AXI interconnect - INI x issuing
functionality modification register</description>
<addressOffset>0x42108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override ASIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override ASIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI2_FN_MOD</name>
<displayName>AXI_INI2_FN_MOD</displayName>
<description>AXI interconnect - INI x issuing
functionality modification register</description>
<addressOffset>0x43108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override ASIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override ASIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI3_FN_MOD</name>
<displayName>AXI_INI3_FN_MOD</displayName>
<description>AXI interconnect - INI x issuing
functionality modification register</description>
<addressOffset>0x44108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override ASIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override ASIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI4_FN_MOD</name>
<displayName>AXI_INI4_FN_MOD</displayName>
<description>AXI interconnect - INI x issuing
functionality modification register</description>
<addressOffset>0x45108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override ASIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override ASIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI5_FN_MOD</name>
<displayName>AXI_INI5_FN_MOD</displayName>
<description>AXI interconnect - INI x issuing
functionality modification register</description>
<addressOffset>0x46108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override ASIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override ASIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AXI_INI6_FN_MOD</name>
<displayName>AXI_INI6_FN_MOD</displayName>
<description>AXI interconnect - INI x issuing
functionality modification register</description>
<addressOffset>0x47108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000004</resetValue>
<fields>
<field>
<name>READ_ISS_OVERRIDE</name>
<description>Override ASIB read issuing
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRITE_ISS_OVERRIDE</name>
<description>Override ASIB write issuing
capability</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>BDMA1</name>
<description>BDMA1</description>
<groupName>BDMA</groupName>
<baseAddress>0x48022C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>DMA interrupt status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GIF1</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF1</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF1</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF1</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF2</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF2</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF2</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF2</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF3</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF3</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF3</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF3</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF4</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF4</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF4</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF4</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF5</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF5</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF5</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF5</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF6</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF6</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF6</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF6</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF7</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF7</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF7</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF7</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF8</name>
<description>Channel x global interrupt flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF8</name>
<description>Channel x transfer complete flag (x =
1..8) This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF8</name>
<description>Channel x half transfer flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF8</name>
<description>Channel x transfer error flag (x = 1..8)
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCR register.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>DMA interrupt flag clear
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CGIF1</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF1</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF1</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF1</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF2</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF2</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF2</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF2</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF3</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF3</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF3</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF3</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF4</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF4</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF4</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF4</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF5</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF5</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF5</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF5</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF6</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF6</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF6</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF6</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF7</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF7</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF7</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF7</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF8</name>
<description>Channel x global interrupt clear This
bit is set and cleared by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF8</name>
<description>Channel x transfer complete clear This
bit is set and cleared by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF8</name>
<description>Channel x half transfer clear This bit
is set and cleared by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF8</name>
<description>Channel x transfer error clear This bit
is set and cleared by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR0</name>
<displayName>CCR0</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR0</name>
<displayName>CNDTR0</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR0</name>
<displayName>CPAR0</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM0AR0</name>
<displayName>CM0AR0</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR1</name>
<displayName>CNDTR1</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR1</name>
<displayName>CPAR1</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM0AR1</name>
<displayName>CM0AR1</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR2</name>
<displayName>CNDTR2</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR2</name>
<displayName>CPAR2</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM0AR2</name>
<displayName>CM0AR2</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR3</name>
<displayName>CNDTR3</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR3</name>
<displayName>CPAR3</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM0AR3</name>
<displayName>CM0AR3</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR4</name>
<displayName>CNDTR4</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR4</name>
<displayName>CPAR4</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM0AR4</name>
<displayName>CM0AR4</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR5</name>
<displayName>CNDTR5</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR5</name>
<displayName>CPAR5</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM0AR5</name>
<displayName>CM0AR5</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR6</name>
<displayName>CCR6</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR6</name>
<displayName>CNDTR6</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR6</name>
<displayName>CPAR6</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM0AR6</name>
<displayName>CM0AR6</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR7</name>
<displayName>CCR7</displayName>
<description>DMA channel x configuration
register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Channel enable This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction This bit is set
and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode This bit is set and
cleared by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode This bit is
set and cleared by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode This bit is set
and cleared by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size These bits are set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size These bits are set and
cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level These bits are
set and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode This bit is set
and cleared by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR7</name>
<displayName>CNDTR7</displayName>
<description>DMA channel x number of data
register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer Number of
data to be transferred (0 up to 65535). This register
can only be written when the channel is disabled.
Once the channel is enabled, this register is
read-only, indicating the remaining bytes to be
transmitted. This register decrements after each DMA
transfer. Once the transfer is completed, this
register can either stay at zero or be reloaded
automatically by the value previously programmed if
the channel is configured in auto-reload mode. If
this register is zero, no transaction can be served
whether the channel is enabled or not.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR7</name>
<displayName>CPAR7</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address Base address of the
peripheral data register from/to which the data will
be read/written. When PSIZE is 01 (16-bit), the PA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When PSIZE is 10 (32-bit), PA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM0AR7</name>
<displayName>CM0AR7</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Base address of the
memory area from/to which the data will be
read/written. When MSIZE is 01 (16-bit), the MA[0]
bit is ignored. Access is automatically aligned to a
half-word address. When MSIZE is 10 (32-bit), MA[1:0]
are ignored. Access is automatically aligned to a
word address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CM1AR0</name>
<displayName>CM1AR0</displayName>
<description>This register must not be written when the
channel is enabled</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>CM1AR1</name>
<displayName>CM1AR1</displayName>
<description>BDMA_CMAR1</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>CM1AR2</name>
<displayName>CM1AR2</displayName>
<description>BDMA_CM1AR2</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>CM1AR3</name>
<displayName>CM1AR3</displayName>
<description>BDMA_CMAR3</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>CM1AR4</name>
<displayName>CM1AR4</displayName>
<description>BDMA_CM1AR4</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>CM1AR5</name>
<displayName>CM1AR5</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>CM1AR6</name>
<displayName>CM1AR6</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>CM1AR7</name>
<displayName>CM1AR7</displayName>
<description>This register must not be written when the
channel is enabled.</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="BDMA1">
<name>BDMA2</name>
<baseAddress>0x58025400</baseAddress>
<interrupt>
<name>BDMA_CH1</name>
<description>BDMA channel 1 interrupt</description>
<value>129</value>
</interrupt>
<interrupt>
<name>BDMA_CH2</name>
<description>BDMA channel 2 interrupt</description>
<value>130</value>
</interrupt>
<interrupt>
<name>BDMA_CH3</name>
<description>BDMA channel 3 interrupt</description>
<value>131</value>
</interrupt>
<interrupt>
<name>BDMA_CH4</name>
<description>BDMA channel 4 interrupt</description>
<value>132</value>
</interrupt>
<interrupt>
<name>BDMA_CH5</name>
<description>BDMA channel 5 interrupt</description>
<value>133</value>
</interrupt>
<interrupt>
<name>BDMA_CH6</name>
<description>BDMA channel 6 interrupt</description>
<value>134</value>
</interrupt>
<interrupt>
<name>BDMA_CH7</name>
<description>BDMA channel 7 interrupt</description>
<value>135</value>
</interrupt>
<interrupt>
<name>BDMA_CH8</name>
<description>BDMA channel 8 interrupt</description>
<value>136</value>
</interrupt>
<interrupt>
<name>BDMA1</name>
<description>BDMA1</description>
<value>154</value>
</interrupt>
</peripheral>
<peripheral>
<name>CAN_CCU</name>
<description>FDCAN1</description>
<groupName>FDCAN</groupName>
<baseAddress>0x4000A800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>FDCAN_CREL</name>
<displayName>FDCAN_CREL</displayName>
<description>FDCAN Core Release Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x32141218</resetValue>
<fields>
<field>
<name>REL</name>
<description>Core release</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STEP</name>
<description>Step of Core release</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SUBSTEP</name>
<description>Sub-step of Core release</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>YEAR</name>
<description>Timestamp Year</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MON</name>
<description>Timestamp Month</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DAY</name>
<description>Timestamp Day</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ENDN</name>
<displayName>FDCAN_ENDN</displayName>
<description>FDCAN Core Release Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x87654321</resetValue>
<fields>
<field>
<name>ETV</name>
<description>Endiannes Test Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_DBTP</name>
<displayName>FDCAN_DBTP</displayName>
<description>FDCAN Data Bit Timing and Prescaler
Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000A33</resetValue>
<fields>
<field>
<name>DSJW</name>
<description>Synchronization Jump Width</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTSEG2</name>
<description>Data time segment after sample
point</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTSEG1</name>
<description>Data time segment after sample
point</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBRP</name>
<description>Data BIt Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TDC</name>
<description>Transceiver Delay
Compensation</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TEST</name>
<displayName>FDCAN_TEST</displayName>
<description>FDCAN Test Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LBCK</name>
<description>Loop Back mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX</name>
<description>Loop Back mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX</name>
<description>Control of Transmit Pin</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RWD</name>
<displayName>FDCAN_RWD</displayName>
<description>FDCAN RAM Watchdog Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDV</name>
<description>Watchdog value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WDC</name>
<description>Watchdog configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_CCCR</name>
<displayName>FDCAN_CCCR</displayName>
<description>FDCAN CC Control Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>INIT</name>
<description>Initialization</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCE</name>
<description>Configuration Change
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASM</name>
<description>ASM Restricted Operation
Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSA</name>
<description>Clock Stop Acknowledge</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSR</name>
<description>Clock Stop Request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MON</name>
<description>Bus Monitoring Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAR</name>
<description>Disable Automatic
Retransmission</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEST</name>
<description>Test Mode Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDOE</name>
<description>FD Operation Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>FDCAN Bit Rate Switching</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXHD</name>
<description>Protocol Exception Handling
Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EFBI</name>
<description>Edge Filtering during Bus
Integration</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXP</name>
<description>TXP</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NISO</name>
<description>Non ISO Operation</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NBTP</name>
<displayName>FDCAN_NBTP</displayName>
<description>FDCAN Nominal Bit Timing and Prescaler
Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000A33</resetValue>
<fields>
<field>
<name>NSJW</name>
<description>NSJW: Nominal (Re)Synchronization Jump
Width</description>
<bitOffset>25</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>NBRP</name>
<description>Bit Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>NTSEG1</name>
<description>Nominal Time segment before sample
point</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TSEG2</name>
<description>Nominal Time segment after sample
point</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TSCC</name>
<displayName>FDCAN_TSCC</displayName>
<description>FDCAN Timestamp Counter Configuration
Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TCP</name>
<description>Timestamp Counter
Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TSS</name>
<description>Timestamp Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TSCV</name>
<displayName>FDCAN_TSCV</displayName>
<description>FDCAN Timestamp Counter Value
Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSC</name>
<description>Timestamp Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TOCC</name>
<displayName>FDCAN_TOCC</displayName>
<description>FDCAN Timeout Counter Configuration
Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFF0000</resetValue>
<fields>
<field>
<name>ETOC</name>
<description>Enable Timeout Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOS</name>
<description>Timeout Select</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TOP</name>
<description>Timeout Period</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TOCV</name>
<displayName>FDCAN_TOCV</displayName>
<description>FDCAN Timeout Counter Value
Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>TOC</name>
<description>Timeout Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ECR</name>
<displayName>FDCAN_ECR</displayName>
<description>FDCAN Error Counter Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEL</name>
<description>AN Error Logging</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RP</name>
<description>Receive Error Passive</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TREC</name>
<description>Receive Error Counter</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TEC</name>
<description>Transmit Error Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_PSR</name>
<displayName>FDCAN_PSR</displayName>
<description>FDCAN Protocol Status Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000707</resetValue>
<fields>
<field>
<name>LEC</name>
<description>Last Error Code</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ACT</name>
<description>Activity</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EP</name>
<description>Error Passive</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>Warning Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>Bus_Off Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLEC</name>
<description>Data Last Error Code</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RESI</name>
<description>ESI flag of last received FDCAN
Message</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBRS</name>
<description>BRS flag of last received FDCAN
Message</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REDL</name>
<description>Received FDCAN Message</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXE</name>
<description>Protocol Exception Event</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCV</name>
<description>Transmitter Delay Compensation
Value</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TDCR</name>
<displayName>FDCAN_TDCR</displayName>
<description>FDCAN Transmitter Delay Compensation
Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDCF</name>
<description>Transmitter Delay Compensation Filter
Window Length</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TDCO</name>
<description>Transmitter Delay Compensation
Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_IR</name>
<displayName>FDCAN_IR</displayName>
<description>FDCAN Interrupt Register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0N</name>
<description>Rx FIFO 0 New Message</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0W</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0F</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>Rx FIFO 0 Message Lost</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1N</name>
<description>Rx FIFO 1 New Message</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1W</name>
<description>Rx FIFO 1 Watermark
Reached</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1F</name>
<description>Rx FIFO 1 Watermark
Reached</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>Rx FIFO 1 Message Lost</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPM</name>
<description>High Priority Message</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>Transmission Completed</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCF</name>
<description>Transmission Cancellation
Finished</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEF</name>
<description>Tx FIFO Empty</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFN</name>
<description>Tx Event FIFO New Entry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFW</name>
<description>Tx Event FIFO Watermark
Reached</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFF</name>
<description>Tx Event FIFO Full</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx Event FIFO Element Lost</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSW</name>
<description>Timestamp Wraparound</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAF</name>
<description>Message RAM Access Failure</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOO</name>
<description>Timeout Occurred</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRX</name>
<description>Message stored to Dedicated Rx
Buffer</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELO</name>
<description>Error Logging Overflow</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP</name>
<description>Error Passive</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>Warning Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>Bus_Off Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDI</name>
<description>Watchdog Interrupt</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEA</name>
<description>Protocol Error in Arbitration Phase
(Nominal Bit Time is used)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PED</name>
<description>Protocol Error in Data Phase (Data Bit
Time is used)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARA</name>
<description>Access to Reserved Address</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_IE</name>
<displayName>FDCAN_IE</displayName>
<description>FDCAN Interrupt Enable
Register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0NE</name>
<description>Rx FIFO 0 New Message
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0WE</name>
<description>Rx FIFO 0 Full Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FE</name>
<description>Rx FIFO 0 Full Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LE</name>
<description>Rx FIFO 0 Message Lost
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NE</name>
<description>Rx FIFO 1 New Message
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1WE</name>
<description>Rx FIFO 1 Watermark Reached
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FE</name>
<description>Rx FIFO 1 Watermark Reached
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LE</name>
<description>Rx FIFO 1 Message Lost
Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPME</name>
<description>High Priority Message
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCE</name>
<description>Transmission Completed
Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFE</name>
<description>Transmission Cancellation Finished
Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFE</name>
<description>Tx FIFO Empty Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNE</name>
<description>Tx Event FIFO New Entry
Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFWE</name>
<description>Tx Event FIFO Watermark Reached
Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFE</name>
<description>Tx Event FIFO Full Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLE</name>
<description>Tx Event FIFO Element Lost
Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWE</name>
<description>Timestamp Wraparound
Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFE</name>
<description>Message RAM Access Failure
Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOE</name>
<description>Timeout Occurred Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRXE</name>
<description>Message stored to Dedicated Rx Buffer
Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BECE</name>
<description>Bit Error Corrected Interrupt
Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BEUE</name>
<description>Bit Error Uncorrected Interrupt
Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOE</name>
<description>Error Logging Overflow
Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPE</name>
<description>Error Passive Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWE</name>
<description>Warning Status Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOE</name>
<description>Bus_Off Status Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIE</name>
<description>Watchdog Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAE</name>
<description>Protocol Error in Arbitration Phase
Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDE</name>
<description>Protocol Error in Data Phase
Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAE</name>
<description>Access to Reserved Address
Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ILS</name>
<displayName>FDCAN_ILS</displayName>
<description>FDCAN Interrupt Line Select
Register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0NL</name>
<description>Rx FIFO 0 New Message Interrupt
Line</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0WL</name>
<description>Rx FIFO 0 Watermark Reached Interrupt
Line</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FL</name>
<description>Rx FIFO 0 Full Interrupt
Line</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LL</name>
<description>Rx FIFO 0 Message Lost Interrupt
Line</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NL</name>
<description>Rx FIFO 1 New Message Interrupt
Line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1WL</name>
<description>Rx FIFO 1 Watermark Reached Interrupt
Line</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FL</name>
<description>Rx FIFO 1 Full Interrupt
Line</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LL</name>
<description>Rx FIFO 1 Message Lost Interrupt
Line</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPML</name>
<description>High Priority Message Interrupt
Line</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCL</name>
<description>Transmission Completed Interrupt
Line</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFL</name>
<description>Transmission Cancellation Finished
Interrupt Line</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx FIFO Empty Interrupt
Line</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNL</name>
<description>Tx Event FIFO New Entry Interrupt
Line</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFWL</name>
<description>Tx Event FIFO Watermark Reached
Interrupt Line</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFL</name>
<description>Tx Event FIFO Full Interrupt
Line</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLL</name>
<description>Tx Event FIFO Element Lost Interrupt
Line</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWL</name>
<description>Timestamp Wraparound Interrupt
Line</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFL</name>
<description>Message RAM Access Failure Interrupt
Line</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOL</name>
<description>Timeout Occurred Interrupt
Line</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRXL</name>
<description>Message stored to Dedicated Rx Buffer
Interrupt Line</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BECL</name>
<description>Bit Error Corrected Interrupt
Line</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BEUL</name>
<description>Bit Error Uncorrected Interrupt
Line</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOL</name>
<description>Error Logging Overflow Interrupt
Line</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPL</name>
<description>Error Passive Interrupt
Line</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWL</name>
<description>Warning Status Interrupt
Line</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOL</name>
<description>Bus_Off Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIL</name>
<description>Watchdog Interrupt Line</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAL</name>
<description>Protocol Error in Arbitration Phase
Line</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDL</name>
<description>Protocol Error in Data Phase
Line</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAL</name>
<description>Access to Reserved Address
Line</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ILE</name>
<displayName>FDCAN_ILE</displayName>
<description>FDCAN Interrupt Line Enable
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EINT0</name>
<description>Enable Interrupt Line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EINT1</name>
<description>Enable Interrupt Line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_GFC</name>
<displayName>FDCAN_GFC</displayName>
<description>FDCAN Global Filter Configuration
Register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RRFE</name>
<description>Reject Remote Frames
Extended</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RRFS</name>
<description>Reject Remote Frames
Standard</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ANFE</name>
<description>Accept Non-matching Frames
Extended</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ANFS</name>
<description>Accept Non-matching Frames
Standard</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_SIDFC</name>
<displayName>FDCAN_SIDFC</displayName>
<description>FDCAN Standard ID Filter Configuration
Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLSSA</name>
<description>Filter List Standard Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>LSS</name>
<description>List Size Standard</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_XIDFC</name>
<displayName>FDCAN_XIDFC</displayName>
<description>FDCAN Extended ID Filter Configuration
Register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLESA</name>
<description>Filter List Standard Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>LSE</name>
<description>List Size Extended</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_XIDAM</name>
<displayName>FDCAN_XIDAM</displayName>
<description>FDCAN Extended ID and Mask
Register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EIDM</name>
<description>Extended ID Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_HPMS</name>
<displayName>FDCAN_HPMS</displayName>
<description>FDCAN High Priority Message Status
Register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BIDX</name>
<description>Buffer Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MSI</name>
<description>Message Storage Indicator</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FIDX</name>
<description>Filter Index</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FLST</name>
<description>Filter List</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NDAT1</name>
<displayName>FDCAN_NDAT1</displayName>
<description>FDCAN New Data 1 Register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ND0</name>
<description>New data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND1</name>
<description>New data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND2</name>
<description>New data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND3</name>
<description>New data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND4</name>
<description>New data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND5</name>
<description>New data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND6</name>
<description>New data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND7</name>
<description>New data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND8</name>
<description>New data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND9</name>
<description>New data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND10</name>
<description>New data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND11</name>
<description>New data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND12</name>
<description>New data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND13</name>
<description>New data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND14</name>
<description>New data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND15</name>
<description>New data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND16</name>
<description>New data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND17</name>
<description>New data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND18</name>
<description>New data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND19</name>
<description>New data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND20</name>
<description>New data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND21</name>
<description>New data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND22</name>
<description>New data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND23</name>
<description>New data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND24</name>
<description>New data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND25</name>
<description>New data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND26</name>
<description>New data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND27</name>
<description>New data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND28</name>
<description>New data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND29</name>
<description>New data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND30</name>
<description>New data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND31</name>
<description>New data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NDAT2</name>
<displayName>FDCAN_NDAT2</displayName>
<description>FDCAN New Data 2 Register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ND32</name>
<description>New data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND33</name>
<description>New data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND34</name>
<description>New data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND35</name>
<description>New data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND36</name>
<description>New data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND37</name>
<description>New data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND38</name>
<description>New data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND39</name>
<description>New data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND40</name>
<description>New data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND41</name>
<description>New data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND42</name>
<description>New data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND43</name>
<description>New data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND44</name>
<description>New data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND45</name>
<description>New data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND46</name>
<description>New data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND47</name>
<description>New data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND48</name>
<description>New data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND49</name>
<description>New data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND50</name>
<description>New data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND51</name>
<description>New data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND52</name>
<description>New data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND53</name>
<description>New data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND54</name>
<description>New data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND55</name>
<description>New data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND56</name>
<description>New data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND57</name>
<description>New data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND58</name>
<description>New data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND59</name>
<description>New data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND60</name>
<description>New data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND61</name>
<description>New data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND62</name>
<description>New data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND63</name>
<description>New data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0C</name>
<displayName>FDCAN_RXF0C</displayName>
<description>FDCAN Rx FIFO 0 Configuration
Register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0SA</name>
<description>Rx FIFO 0 Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>F0S</name>
<description>Rx FIFO 0 Size</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>F0WM</name>
<description>FIFO 0 Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0S</name>
<displayName>FDCAN_RXF0S</displayName>
<description>FDCAN Rx FIFO 0 Status
Register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0FL</name>
<description>Rx FIFO 0 Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F0G</name>
<description>Rx FIFO 0 Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F0P</name>
<description>Rx FIFO 0 Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F0F</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>Rx FIFO 0 Message Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0A</name>
<displayName>FDCAN_RXF0A</displayName>
<description>CAN Rx FIFO 0 Acknowledge
Register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FA01</name>
<description>Rx FIFO 0 Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXBC</name>
<displayName>FDCAN_RXBC</displayName>
<description>FDCAN Rx Buffer Configuration
Register</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RBSA</name>
<description>Rx Buffer Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1C</name>
<displayName>FDCAN_RXF1C</displayName>
<description>FDCAN Rx FIFO 1 Configuration
Register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1SA</name>
<description>Rx FIFO 1 Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>F1S</name>
<description>Rx FIFO 1 Size</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1WM</name>
<description>Rx FIFO 1 Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1S</name>
<displayName>FDCAN_RXF1S</displayName>
<description>FDCAN Rx FIFO 1 Status
Register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1FL</name>
<description>Rx FIFO 1 Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1GI</name>
<description>Rx FIFO 1 Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1PI</name>
<description>Rx FIFO 1 Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1F</name>
<description>Rx FIFO 1 Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>Rx FIFO 1 Message Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMS</name>
<description>Debug Message Status</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1A</name>
<displayName>FDCAN_RXF1A</displayName>
<description>FDCAN Rx FIFO 1 Acknowledge
Register</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1AI</name>
<description>Rx FIFO 1 Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXESC</name>
<displayName>FDCAN_RXESC</displayName>
<description>FDCAN Rx Buffer Element Size Configuration
Register</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0DS</name>
<description>Rx FIFO 1 Data Field Size:</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>F1DS</name>
<description>Rx FIFO 0 Data Field Size:</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RBDS</name>
<description>Rx Buffer Data Field Size:</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBC</name>
<displayName>FDCAN_TXBC</displayName>
<description>FDCAN Tx Buffer Configuration
Register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBSA</name>
<description>Tx Buffers Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>NDTB</name>
<description>Number of Dedicated Transmit
Buffers</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFQS</name>
<description>Transmit FIFO/Queue Size</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFQM</name>
<description>Tx FIFO/Queue Mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXFQS</name>
<displayName>FDCAN_TXFQS</displayName>
<description>FDCAN Tx FIFO/Queue Status
Register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TFFL</name>
<description>Tx FIFO Free Level</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFGI</name>
<description>TFGI</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TFQPI</name>
<description>Tx FIFO/Queue Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TFQF</name>
<description>Tx FIFO/Queue Full</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXESC</name>
<displayName>FDCAN_TXESC</displayName>
<description>FDCAN Tx Buffer Element Size Configuration
Register</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBDS</name>
<description>Tx Buffer Data Field Size:</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBRP</name>
<displayName>FDCAN_TXBRP</displayName>
<description>FDCAN Tx Buffer Request Pending
Register</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRP</name>
<description>Transmission Request
Pending</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBAR</name>
<displayName>FDCAN_TXBAR</displayName>
<description>FDCAN Tx Buffer Add Request
Register</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AR</name>
<description>Add Request</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCR</name>
<displayName>FDCAN_TXBCR</displayName>
<description>FDCAN Tx Buffer Cancellation Request
Register</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CR</name>
<description>Cancellation Request</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBTO</name>
<displayName>FDCAN_TXBTO</displayName>
<description>FDCAN Tx Buffer Transmission Occurred
Register</description>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TO</name>
<description>Transmission Occurred.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCF</name>
<displayName>FDCAN_TXBCF</displayName>
<description>FDCAN Tx Buffer Cancellation Finished
Register</description>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CF</name>
<description>Cancellation Finished</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBTIE</name>
<displayName>FDCAN_TXBTIE</displayName>
<description>FDCAN Tx Buffer Transmission Interrupt
Enable Register</description>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIE</name>
<description>Transmission Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCIE</name>
<displayName>FDCAN_TXBCIE</displayName>
<description>FDCAN Tx Buffer Cancellation Finished
Interrupt Enable Register</description>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CF</name>
<description>Cancellation Finished Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFC</name>
<displayName>FDCAN_TXEFC</displayName>
<description>FDCAN Tx Event FIFO Configuration
Register</description>
<addressOffset>0xF0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFSA</name>
<description>Event FIFO Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>EFS</name>
<description>Event FIFO Size</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>EFWM</name>
<description>Event FIFO Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFS</name>
<displayName>FDCAN_TXEFS</displayName>
<description>FDCAN Tx Event FIFO Status
Register</description>
<addressOffset>0xF4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFFL</name>
<description>Event FIFO Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>EFGI</name>
<description>Event FIFO Get Index.</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>EFF</name>
<description>Event FIFO Full.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx Event FIFO Element
Lost.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFA</name>
<displayName>FDCAN_TXEFA</displayName>
<description>FDCAN Tx Event FIFO Acknowledge
Register</description>
<addressOffset>0xF8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFAI</name>
<description>Event FIFO Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTMC</name>
<displayName>FDCAN_TTTMC</displayName>
<description>FDCAN TT Trigger Memory Configuration
Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TMSA</name>
<description>Trigger Memory Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>TME</name>
<description>Trigger Memory Elements</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTRMC</name>
<displayName>FDCAN_TTRMC</displayName>
<description>FDCAN TT Reference Message Configuration
Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RID</name>
<description>Reference Identifier.</description>
<bitOffset>0</bitOffset>
<bitWidth>29</bitWidth>
</field>
<field>
<name>XTD</name>
<description>Extended Identifier</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMPS</name>
<description>Reference Message Payload
Select</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOCF</name>
<displayName>FDCAN_TTOCF</displayName>
<description>FDCAN TT Operation Configuration
Register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010000</resetValue>
<fields>
<field>
<name>OM</name>
<description>Operation Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN</name>
<description>Gap Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TM</name>
<description>Time Master</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDSDL</name>
<description>LD of Synchronization Deviation
Limit</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IRTO</name>
<description>Initial Reference Trigger
Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>EECS</name>
<description>Enable External Clock
Synchronization</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWL</name>
<description>Application Watchdog Limit</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>EGTF</name>
<description>Enable Global Time
Filtering</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECC</name>
<description>Enable Clock Calibration</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTP</name>
<description>Event Trigger Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTMLM</name>
<displayName>FDCAN_TTMLM</displayName>
<description>FDCAN TT Matrix Limits
Register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCM</name>
<description>Cycle Count Max</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Cycle Start
Synchronization</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TXEW</name>
<description>Tx Enable Window</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ENTT</name>
<description>Expected Number of Tx
Triggers</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TURCF</name>
<displayName>FDCAN_TURCF</displayName>
<description>FDCAN TUR Configuration
Register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NCL</name>
<description>Numerator Configuration
Low.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DC</name>
<description>Denominator Configuration.</description>
<bitOffset>16</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>ELT</name>
<description>Enable Local Time</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOCN</name>
<displayName>FDCAN_TTOCN</displayName>
<description>FDCAN TT Operation Control
Register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SGT</name>
<description>Set Global time</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECS</name>
<description>External Clock
Synchronization</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWP</name>
<description>Stop Watch Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWS</name>
<description>Stop Watch Source.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RTIE</name>
<description>Register Time Mark Interrupt Pulse
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMC</name>
<description>Register Time Mark Compare</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TTIE</name>
<description>Trigger Time Mark Interrupt Pulse
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCS</name>
<description>Gap Control Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FGP</name>
<description>Finish Gap.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMG</name>
<description>Time Mark Gap</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NIG</name>
<description>Next is Gap</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESCN</name>
<description>External Synchronization
Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCKC</name>
<description>TT Operation Control Register
Locked</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAN_TTGTP</name>
<displayName>CAN_TTGTP</displayName>
<description>FDCAN TT Global Time Preset
Register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NCL</name>
<description>Time Preset</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CTP</name>
<description>Cycle Time Target Phase</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTMK</name>
<displayName>FDCAN_TTTMK</displayName>
<description>FDCAN TT Time Mark Register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TM</name>
<description>Time Mark</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TICC</name>
<description>Time Mark Cycle Code</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>LCKM</name>
<description>TT Time Mark Register
Locked</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTIR</name>
<displayName>FDCAN_TTIR</displayName>
<description>FDCAN TT Interrupt Register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBC</name>
<description>Start of Basic Cycle</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMC</name>
<description>Start of Matrix Cycle</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSM</name>
<description>Change of Synchronization
Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOG</name>
<description>Start of Gap</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMI</name>
<description>Register Time Mark
Interrupt.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMI</name>
<description>Trigger Time Mark Event
Internal</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWE</name>
<description>Stop Watch Event</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTW</name>
<description>Global Time Wrap</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTD</name>
<description>Global Time Discontinuity</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTE</name>
<description>Global Time Error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXU</name>
<description>Tx Count Underflow</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXO</name>
<description>Tx Count Overflow</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1</name>
<description>Scheduling Error 1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2</name>
<description>Scheduling Error 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELC</name>
<description>Error Level Changed.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTG</name>
<description>Initialization Watch
Trigger</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WT</name>
<description>Watch Trigger</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AW</name>
<description>Application Watchdog</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CER</name>
<description>Configuration Error</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTIE</name>
<displayName>FDCAN_TTIE</displayName>
<description>FDCAN TT Interrupt Enable
Register</description>
<addressOffset>0x124</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBCE</name>
<description>Start of Basic Cycle Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMCE</name>
<description>Start of Matrix Cycle Interrupt
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSME</name>
<description>Change of Synchronization Mode Interrupt
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOGE</name>
<description>Start of Gap Interrupt
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMIE</name>
<description>Register Time Mark Interrupt
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMIE</name>
<description>Trigger Time Mark Event Internal
Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWEE</name>
<description>Stop Watch Event Interrupt
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTWE</name>
<description>Global Time Wrap Interrupt
Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTDE</name>
<description>Global Time Discontinuity Interrupt
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTEE</name>
<description>Global Time Error Interrupt
Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUE</name>
<description>Tx Count Underflow Interrupt
Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOE</name>
<description>Tx Count Overflow Interrupt
Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1E</name>
<description>Scheduling Error 1 Interrupt
Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2E</name>
<description>Scheduling Error 2 Interrupt
Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELCE</name>
<description>Change Error Level Interrupt
Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTGE</name>
<description>Initialization Watch Trigger Interrupt
Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WTE</name>
<description>Watch Trigger Interrupt
Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWE</name>
<description>Application Watchdog Interrupt
Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CERE</name>
<description>Configuration Error Interrupt
Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTILS</name>
<displayName>FDCAN_TTILS</displayName>
<description>FDCAN TT Interrupt Line Select
Register</description>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBCL</name>
<description>Start of Basic Cycle Interrupt
Line</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMCL</name>
<description>Start of Matrix Cycle Interrupt
Line</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSML</name>
<description>Change of Synchronization Mode Interrupt
Line</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOGL</name>
<description>Start of Gap Interrupt
Line</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMIL</name>
<description>Register Time Mark Interrupt
Line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMIL</name>
<description>Trigger Time Mark Event Internal
Interrupt Line</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWEL</name>
<description>Stop Watch Event Interrupt
Line</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTWL</name>
<description>Global Time Wrap Interrupt
Line</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTDL</name>
<description>Global Time Discontinuity Interrupt
Line</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTEL</name>
<description>Global Time Error Interrupt
Line</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUL</name>
<description>Tx Count Underflow Interrupt
Line</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOL</name>
<description>Tx Count Overflow Interrupt
Line</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1L</name>
<description>Scheduling Error 1 Interrupt
Line</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2L</name>
<description>Scheduling Error 2 Interrupt
Line</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELCL</name>
<description>Change Error Level Interrupt
Line</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTGL</name>
<description>Initialization Watch Trigger Interrupt
Line</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WTL</name>
<description>Watch Trigger Interrupt
Line</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWL</name>
<description>Application Watchdog Interrupt
Line</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CERL</name>
<description>Configuration Error Interrupt
Line</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOST</name>
<displayName>FDCAN_TTOST</displayName>
<description>FDCAN TT Operation Status
Register</description>
<addressOffset>0x12C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EL</name>
<description>Error Level</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MS</name>
<description>Master State.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYS</name>
<description>Synchronization State</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GTP</name>
<description>Quality of Global Time
Phase</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QCS</name>
<description>Quality of Clock Speed</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Reference Trigger Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WGTD</name>
<description>Wait for Global Time
Discontinuity</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GFI</name>
<description>Gap Finished Indicator.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMP</name>
<description>Time Master Priority</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GSI</name>
<description>Gap Started Indicator.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WFE</name>
<description>Wait for Event</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWE</name>
<description>Application Watchdog Event</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WECS</name>
<description>Wait for External Clock
Synchronization</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPL</name>
<description>Schedule Phase Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TURNA</name>
<displayName>FDCAN_TURNA</displayName>
<description>FDCAN TUR Numerator Actual
Register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NAV</name>
<description>Numerator Actual Value</description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTLGT</name>
<displayName>FDCAN_TTLGT</displayName>
<description>FDCAN TT Local and Global Time
Register</description>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LT</name>
<description>Local Time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GT</name>
<description>Global Time</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCTC</name>
<displayName>FDCAN_TTCTC</displayName>
<description>FDCAN TT Cycle Time and Count
Register</description>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CT</name>
<description>Cycle Time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CC</name>
<description>Cycle Count</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCPT</name>
<displayName>FDCAN_TTCPT</displayName>
<description>FDCAN TT Capture Time Register</description>
<addressOffset>0x13C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CT</name>
<description>Cycle Count Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SWV</name>
<description>Stop Watch Value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCSM</name>
<displayName>FDCAN_TTCSM</displayName>
<description>FDCAN TT Cycle Sync Mark
Register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSM</name>
<description>Cycle Sync Mark</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTS</name>
<displayName>FDCAN_TTTS</displayName>
<description>FDCAN TT Trigger Select
Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWTDEL</name>
<description>Stop watch trigger input
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EVTSEL</name>
<description>Event trigger input
selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CEC</name>
<description>CEC</description>
<groupName>CEC</groupName>
<baseAddress>0x40006C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CEC</name>
<description>HDMI-CEC global interrupt</description>
<value>94</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>CEC control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CECEN</name>
<description>CEC Enable The CECEN bit is set and
cleared by software. CECEN=1 starts message reception
and enables the TXSOM control. CECEN=0 disables the
CEC peripheral, clears all bits of CEC_CR register
and aborts any on-going reception or
transmission.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXSOM</name>
<description>Tx Start Of Message TXSOM is set by
software to command transmission of the first byte of
a CEC message. If the CEC message consists of only
one byte, TXEOM must be set before of TXSOM.
Start-Bit is effectively started on the CEC line
after SFT is counted. If TXSOM is set while a message
reception is ongoing, transmission will start after
the end of reception. TXSOM is cleared by hardware
after the last byte of the message is sent with a
positive acknowledge (TXEND=1), in case of
transmission underrun (TXUDR=1), negative acknowledge
(TXACKE=1), and transmission error (TXERR=1). It is
also cleared by CECEN=0. It is not cleared and
transmission is automatically retried in case of
arbitration lost (ARBLST=1). TXSOM can be also used
as a status bit informing application whether any
transmission request is pending or under execution.
The application can abort a transmission request at
any time by clearing the CECEN bit. Note: TXSOM must
be set when CECEN=1 TXSOM must be set when
transmission data is available into TXDR HEADERs
first four bits containing own peripheral address are
taken from TXDR[7:4], not from CEC_CFGR.OAR which is
used only for reception</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEOM</name>
<description>Tx End Of Message The TXEOM bit is set
by software to command transmission of the last byte
of a CEC message. TXEOM is cleared by hardware at the
same time and under the same conditions as for TXSOM.
Note: TXEOM must be set when CECEN=1 TXEOM must be
set before writing transmission data to TXDR If TXEOM
is set when TXSOM=0, transmitted message will consist
of 1 byte (HEADER) only (PING message)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>This register is used to configure the
HDMI-CEC controller. It is mandatory to write CEC_CFGR
only when CECEN=0.</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SFT</name>
<description>Signal Free Time SFT bits are set by
software. In the SFT=0x0 configuration the number of
nominal data bit periods waited before transmission
is ruled by hardware according to the transmission
history. In all the other configurations the SFT
number is determined by software. * 0x0 ** 2.5
Data-Bit periods if CEC is the last bus initiator
with unsuccessful transmission (ARBLST=1, TXERR=1,
TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is
the new bus initiator ** 6 Data-Bit periods if CEC is
the last bus initiator with successful transmission
(TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2:
1.5 nominal data bit periods * 0x3: 2.5 nominal data
bit periods * 0x4: 3.5 nominal data bit periods *
0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal
data bit periods * 0x7: 6.5 nominal data bit
periods</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXTOL</name>
<description>Rx-Tolerance The RXTOL bit is set and
cleared by software. ** Start-Bit, +/- 200 s rise,
+/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350
s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall
** Data-Bit: +/-300 s rise, +/- 500 s
fall</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRESTP</name>
<description>Rx-Stop on Bit Rising Error The BRESTP
bit is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BREGEN</name>
<description>Generate Error-Bit on Bit Rising Error
The BREGEN bit is set and cleared by software. Note:
If BRDNOGEN=0, an Error-bit is generated upon BRE
detection with BRESTP=1 in broadcast even if
BREGEN=0</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBPEGEN</name>
<description>Generate Error-Bit on Long Bit Period
Error The LBPEGEN bit is set and cleared by software.
Note: If BRDNOGEN=0, an Error-bit is generated upon
LBPE detection in broadcast even if
LBPEGEN=0</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDNOGEN</name>
<description>Avoid Error-Bit Generation in Broadcast
The BRDNOGEN bit is set and cleared by
software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SFTOPT</name>
<description>SFT Option Bit The SFTOPT bit is set and
cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OAR</name>
<description>Own addresses configuration The OAR bits
are set by software to select which destination
logical addresses has to be considered in receive
mode. Each bit, when set, enables the CEC logical
address identified by the given bit position. At the
end of HEADER reception, the received destination
address is compared with the enabled addresses. In
case of matching address, the incoming message is
acknowledged and received. In case of non-matching
address, the incoming message is received only in
listen mode (LSTN=1), but without acknowledge sent.
Broadcast messages are always received. Example: OAR
= 0b000 0000 0010 0001 means that CEC acknowledges
addresses 0x0 and 0x5. Consequently, each message
directed to one of these addresses is
received.</description>
<bitOffset>16</bitOffset>
<bitWidth>15</bitWidth>
</field>
<field>
<name>LSTN</name>
<description>Listen mode LSTN bit is set and cleared
by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXDR</name>
<displayName>TXDR</displayName>
<description>CEC Tx data register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXD</name>
<description>Tx Data register. TXD is a write-only
register containing the data byte to be transmitted.
Note: TXD must be written when
TXSTART=1</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXDR</name>
<displayName>RXDR</displayName>
<description>CEC Rx Data Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXD</name>
<description>Rx Data register. RXD is read-only and
contains the last data byte which has been received
from the CEC line.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>CEC Interrupt and Status
Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXBR</name>
<description>Rx-Byte Received The RXBR bit is set by
hardware to inform application that a new byte has
been received from the CEC line and stored into the
RXD buffer. RXBR is cleared by software write at
1.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXEND</name>
<description>End Of Reception RXEND is set by
hardware to inform application that the last byte of
a CEC message is received from the CEC line and
stored into the RXD buffer. RXEND is set at the same
time of RXBR. RXEND is cleared by software write at
1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVR</name>
<description>Rx-Overrun RXOVR is set by hardware if
RXBR is not yet cleared at the time a new byte is
received on the CEC line and stored into RXD. RXOVR
assertion stops message reception so that no
acknowledge is sent. In case of broadcast, a negative
acknowledge is sent. RXOVR is cleared by software
write at 1.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRE</name>
<description>Rx-Bit Rising Error BRE is set by
hardware in case a Data-Bit waveform is detected with
Bit Rising Error. BRE is set either at the time the
misplaced rising edge occurs, or at the end of the
maximum BRE tolerance allowed by RXTOL, in case
rising edge is still longing. BRE stops message
reception if BRESTP=1. BRE generates an Error-Bit on
the CEC line if BREGEN=1. BRE is cleared by software
write at 1.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBPE</name>
<description>Rx-Short Bit Period Error SBPE is set by
hardware in case a Data-Bit waveform is detected with
Short Bit Period Error. SBPE is set at the time the
anticipated falling edge occurs. SBPE generates an
Error-Bit on the CEC line. SBPE is cleared by
software write at 1.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBPE</name>
<description>Rx-Long Bit Period Error LBPE is set by
hardware in case a Data-Bit waveform is detected with
Long Bit Period Error. LBPE is set at the end of the
maximum bit-extension tolerance allowed by RXTOL, in
case falling edge is still longing. LBPE always stops
reception of the CEC message. LBPE generates an
Error-Bit on the CEC line if LBPEGEN=1. In case of
broadcast, Error-Bit is generated even in case of
LBPEGEN=0. LBPE is cleared by software write at
1.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXACKE</name>
<description>Rx-Missing Acknowledge In receive mode,
RXACKE is set by hardware to inform application that
no acknowledge was seen on the CEC line. RXACKE
applies only for broadcast messages and in listen
mode also for not directly addressed messages
(destination address not enabled in OAR). RXACKE
aborts message reception. RXACKE is cleared by
software write at 1.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBLST</name>
<description>Arbitration Lost ARBLST is set by
hardware to inform application that CEC device is
switching to reception due to arbitration lost event
following the TXSOM command. ARBLST can be due either
to a contending CEC device starting earlier or
starting at the same time but with higher HEADER
priority. After ARBLST assertion TXSOM bit keeps
pending for next transmission attempt. ARBLST is
cleared by software write at 1.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXBR</name>
<description>Tx-Byte Request TXBR is set by hardware
to inform application that the next transmission data
has to be written to TXDR. TXBR is set when the 4th
bit of currently transmitted byte is sent.
Application must write the next byte to TXDR within 6
nominal data-bit periods before transmission underrun
error occurs (TXUDR). TXBR is cleared by software
write at 1.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEND</name>
<description>End of Transmission TXEND is set by
hardware to inform application that the last byte of
the CEC message has been successfully transmitted.
TXEND clears the TXSOM and TXEOM control bits. TXEND
is cleared by software write at 1.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUDR</name>
<description>Tx-Buffer Underrun In transmission mode,
TXUDR is set by hardware if application was not in
time to load TXDR before of next byte transmission.
TXUDR aborts message transmission and clears TXSOM
and TXEOM control bits. TXUDR is cleared by software
write at 1</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Tx-Error In transmission mode, TXERR is
set by hardware if the CEC initiator detects low
impedance on the CEC line while it is released. TXERR
aborts message transmission and clears TXSOM and
TXEOM controls. TXERR is cleared by software write at
1.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXACKE</name>
<description>Tx-Missing Acknowledge Error In
transmission mode, TXACKE is set by hardware to
inform application that no acknowledge was received.
In case of broadcast transmission, TXACKE informs
application that a negative acknowledge was received.
TXACKE aborts message transmission and clears TXSOM
and TXEOM controls. TXACKE is cleared by software
write at 1.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>CEC interrupt enable register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXBRIE</name>
<description>Rx-Byte Received Interrupt Enable The
RXBRIE bit is set and cleared by
software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXENDIE</name>
<description>End Of Reception Interrupt Enable The
RXENDIE bit is set and cleared by
software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVRIE</name>
<description>Rx-Buffer Overrun Interrupt Enable The
RXOVRIE bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BREIE</name>
<description>Bit Rising Error Interrupt Enable The
BREIE bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBPEIE</name>
<description>Short Bit Period Error Interrupt Enable
The SBPEIE bit is set and cleared by
software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBPEIE</name>
<description>Long Bit Period Error Interrupt Enable
The LBPEIE bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXACKIE</name>
<description>Rx-Missing Acknowledge Error Interrupt
Enable The RXACKIE bit is set and cleared by
software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBLSTIE</name>
<description>Arbitration Lost Interrupt Enable The
ARBLSTIE bit is set and cleared by
software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXBRIE</name>
<description>Tx-Byte Request Interrupt Enable The
TXBRIE bit is set and cleared by
software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXENDIE</name>
<description>Tx-End Of Message Interrupt Enable The
TXENDIE bit is set and cleared by
software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUDRIE</name>
<description>Tx-Underrun Interrupt Enable The TXUDRIE
bit is set and cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRIE</name>
<description>Tx-Error Interrupt Enable The TXERRIE
bit is set and cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXACKIE</name>
<description>Tx-Missing Acknowledge Error Interrupt
Enable The TXACKEIE bit is set and cleared by
software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>COMP1</name>
<description>COMP1</description>
<groupName>COMP1</groupName>
<baseAddress>0x58003800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>COMP</name>
<description>COMP1 and COMP2</description>
<value>137</value>
</interrupt>
<registers>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Comparator status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C1VAL</name>
<description>COMP channel 1 output status
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2VAL</name>
<description>COMP channel 2 output status
bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C1IF</name>
<description>COMP channel 1 Interrupt
Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2IF</name>
<description>COMP channel 2 Interrupt
Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICFR</name>
<displayName>ICFR</displayName>
<description>Comparator interrupt clear flag
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1IF</name>
<description>Clear COMP channel 1 Interrupt
Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Clear COMP channel 2 Interrupt
Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>Comparator option register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFOP</name>
<description>Selection of source for alternate
function of output ports</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>OR</name>
<description>Option Register</description>
<bitOffset>11</bitOffset>
<bitWidth>21</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR1</name>
<displayName>CFGR1</displayName>
<description>Comparator configuration register
1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>COMP channel 1 enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRGEN</name>
<description>Scaler bridge enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCALEN</name>
<description>Voltage scaler enable bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POLARITY</name>
<description>COMP channel 1 polarity selection
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITEN</name>
<description>COMP channel 1 interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HYST</name>
<description>COMP channel 1 hysteresis selection
bits</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PWRMODE</name>
<description>Power Mode of the COMP channel
1</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INMSEL</name>
<description>COMP channel 1 inverting input selection
field</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>INPSEL</name>
<description>COMP channel 1 non-inverting input
selection bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLANKING</name>
<description>COMP channel 1 blanking source selection
bits</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR2</name>
<displayName>CFGR2</displayName>
<description>Comparator configuration register
2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>COMP channel 1 enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRGEN</name>
<description>Scaler bridge enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCALEN</name>
<description>Voltage scaler enable bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POLARITY</name>
<description>COMP channel 1 polarity selection
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WINMODE</name>
<description>Window comparator mode selection
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITEN</name>
<description>COMP channel 1 interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HYST</name>
<description>COMP channel 1 hysteresis selection
bits</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PWRMODE</name>
<description>Power Mode of the COMP channel
1</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INMSEL</name>
<description>COMP channel 1 inverting input selection
field</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>INPSEL</name>
<description>COMP channel 1 non-inverting input
selection bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLANKING</name>
<description>COMP channel 1 blanking source selection
bits</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>Cryptographic processor</description>
<groupName>CRC</groupName>
<baseAddress>0x40023000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMAMUX1_OV</name>
<description>DMAMUX1 overrun interrupt</description>
<value>102</value>
</interrupt>
<registers>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>Data register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>Independent Data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR</name>
<description>Independent Data register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RESET</name>
<description>RESET bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>POLYSIZE</name>
<description>Polynomial size</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>REV_IN</name>
<description>Reverse input data</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>REV_OUT</name>
<description>Reverse output data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT</name>
<displayName>INIT</displayName>
<description>Initial CRC value</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_INIT</name>
<description>Programmable initial CRC
value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>POL</name>
<displayName>POL</displayName>
<description>CRC polynomial</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>POL</name>
<description>Programmable polynomial</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRS</name>
<description>CRS</description>
<groupName>CRS</groupName>
<baseAddress>0x40008400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CRS</name>
<description>Clock Recovery System globa</description>
<value>144</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>CRS control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00002000</resetValue>
<fields>
<field>
<name>SYNCOKIE</name>
<description>SYNC event OK interrupt
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SYNCWARNIE</name>
<description>SYNC warning interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERRIE</name>
<description>Synchronization or trimming error
interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ESYNCIE</name>
<description>Expected SYNC interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CEN</name>
<description>Frequency error counter enable This bit
enables the oscillator clock for the frequency error
counter. When this bit is set, the CRS_CFGR register
is write-protected and cannot be
modified.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AUTOTRIMEN</name>
<description>Automatic trimming enable This bit
enables the automatic hardware adjustment of TRIM
bits according to the measured frequency error
between two SYNC events. If this bit is set, the TRIM
bits are read-only. The TRIM value can be adjusted by
hardware by one or two steps at a time, depending on
the measured frequency error value. Refer to
Section7.3.4: Frequency error evaluation and
automatic trimming for more details.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWSYNC</name>
<description>Generate software SYNC event This bit is
set by software in order to generate a software SYNC
event. It is automatically cleared by
hardware.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TRIM</name>
<description>HSI48 oscillator smooth trimming These
bits provide a user-programmable trimming value to
the HSI48 oscillator. They can be programmed to
adjust to variations in voltage and temperature that
influence the frequency of the HSI48. The default
value is 32, which corresponds to the middle of the
trimming interval. The trimming step is around 67 kHz
between two consecutive TRIM steps. A higher TRIM
value corresponds to a higher output frequency. When
the AUTOTRIMEN bit is set, this field is controlled
by hardware and is read-only.</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>This register can be written only when the
frequency error counter is disabled (CEN bit is cleared
in CRS_CR). When the counter is enabled, this register is
write-protected.</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x2022BB7F</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>Counter reload value RELOAD is the value
to be loaded in the frequency error counter with each
SYNC event. Refer to Section7.3.3: Frequency error
measurement for more details about counter
behavior.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FELIM</name>
<description>Frequency error limit FELIM contains the
value to be used to evaluate the captured frequency
error value latched in the FECAP[15:0] bits of the
CRS_ISR register. Refer to Section7.3.4: Frequency
error evaluation and automatic trimming for more
details about FECAP evaluation.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SYNCDIV</name>
<description>SYNC divider These bits are set and
cleared by software to control the division factor of
the SYNC signal.</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SYNCSRC</name>
<description>SYNC signal source selection These bits
are set and cleared by software to select the SYNC
signal source. Note: When using USB LPM (Link Power
Management) and the device is in Sleep mode, the
periodic USB SOF will not be generated by the host.
No SYNC signal will therefore be provided to the CRS
to calibrate the HSI48 on the run. To guarantee the
required clock precision after waking up from Sleep
mode, the LSE or reference clock on the GPIOs should
be used as SYNC signal.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCPOL</name>
<description>SYNC polarity selection This bit is set
and cleared by software to select the input polarity
for the SYNC signal source.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>CRS interrupt and status
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOKF</name>
<description>SYNC event OK flag This flag is set by
hardware when the measured frequency error is smaller
than FELIM * 3. This means that either no adjustment
of the TRIM value is needed or that an adjustment by
one trimming step is enough to compensate the
frequency error. An interrupt is generated if the
SYNCOKIE bit is set in the CRS_CR register. It is
cleared by software by setting the SYNCOKC bit in the
CRS_ICR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNF</name>
<description>SYNC warning flag This flag is set by
hardware when the measured frequency error is greater
than or equal to FELIM * 3, but smaller than FELIM *
128. This means that to compensate the frequency
error, the TRIM value must be adjusted by two steps
or more. An interrupt is generated if the SYNCWARNIE
bit is set in the CRS_CR register. It is cleared by
software by setting the SYNCWARNC bit in the CRS_ICR
register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRF</name>
<description>Error flag This flag is set by hardware
in case of any synchronization or trimming error. It
is the logical OR of the TRIMOVF, SYNCMISS and
SYNCERR bits. An interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by
software in reaction to setting the ERRC bit in the
CRS_ICR register, which clears the TRIMOVF, SYNCMISS
and SYNCERR bits.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCF</name>
<description>Expected SYNC flag This flag is set by
hardware when the frequency error counter reached a
zero value. An interrupt is generated if the ESYNCIE
bit is set in the CRS_CR register. It is cleared by
software by setting the ESYNCC bit in the CRS_ICR
register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCERR</name>
<description>SYNC error This flag is set by hardware
when the SYNC pulse arrives before the ESYNC event
and the measured frequency error is greater than or
equal to FELIM * 128. This means that the frequency
error is too big (internal frequency too low) to be
compensated by adjusting the TRIM value, and that
some other action should be taken. An interrupt is
generated if the ERRIE bit is set in the CRS_CR
register. It is cleared by software by setting the
ERRC bit in the CRS_ICR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCMISS</name>
<description>SYNC missed This flag is set by hardware
when the frequency error counter reached value FELIM
* 128 and no SYNC was detected, meaning either that a
SYNC pulse was missed or that the frequency error is
too big (internal frequency too high) to be
compensated by adjusting the TRIM value, and that
some other action should be taken. At this point, the
frequency error counter is stopped (waiting for a
next SYNC) and an interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by
software by setting the ERRC bit in the CRS_ICR
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIMOVF</name>
<description>Trimming overflow or underflow This flag
is set by hardware when the automatic trimming tries
to over- or under-flow the TRIM value. An interrupt
is generated if the ERRIE bit is set in the CRS_CR
register. It is cleared by software by setting the
ERRC bit in the CRS_ICR register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEDIR</name>
<description>Frequency error direction FEDIR is the
counting direction of the frequency error counter
latched in the time of the last SYNC event. It shows
whether the actual frequency is below or above the
target.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECAP</name>
<description>Frequency error capture FECAP is the
frequency error counter value latched in the time of
the last SYNC event. Refer to Section7.3.4: Frequency
error evaluation and automatic trimming for more
details about FECAP usage.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>CRS interrupt flag clear
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOKC</name>
<description>SYNC event OK clear flag Writing 1 to
this bit clears the SYNCOKF flag in the CRS_ISR
register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNC</name>
<description>SYNC warning clear flag Writing 1 to
this bit clears the SYNCWARNF flag in the CRS_ISR
register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRC</name>
<description>Error clear flag Writing 1 to this bit
clears TRIMOVF, SYNCMISS and SYNCERR bits and
consequently also the ERRF flag in the CRS_ISR
register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCC</name>
<description>Expected SYNC clear flag Writing 1 to
this bit clears the ESYNCF flag in the CRS_ISR
register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DAC</name>
<description>DAC</description>
<groupName>DAC</groupName>
<baseAddress>0x40007400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>DAC control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN1</name>
<description>DAC channel1 enable This bit is set and
cleared by software to enable/disable DAC
channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEN1</name>
<description>DAC channel1 trigger
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEL1</name>
<description>DAC channel1 trigger selection These
bits select the external event used to trigger DAC
channel1. Note: Only used if bit TEN1 = 1 (DAC
channel1 trigger enabled).</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>WAVE1</name>
<description>DAC channel1 noise/triangle wave
generation enable These bits are set and cleared by
software. Note: Only used if bit TEN1 = 1 (DAC
channel1 trigger enabled).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MAMP1</name>
<description>DAC channel1 mask/amplitude selector
These bits are written by software to select mask in
wave generation mode or amplitude in triangle
generation mode. = 1011: Unmask bits[11:0] of LFSR/
triangle amplitude equal to 4095</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN1</name>
<description>DAC channel1 DMA enable This bit is set
and cleared by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAUDRIE1</name>
<description>DAC channel1 DMA Underrun Interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN1</name>
<description>DAC Channel 1 calibration enable This
bit is set and cleared by software to enable/disable
DAC channel 1 calibration, it can be written only if
bit EN1=0 into DAC_CR (the calibration mode can be
entered/exit only when the DAC channel is disabled)
Otherwise, the write operation is
ignored.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN2</name>
<description>DAC channel2 enable This bit is set and
cleared by software to enable/disable DAC
channel2.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEN2</name>
<description>DAC channel2 trigger
enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEL2</name>
<description>DAC channel2 trigger selection These
bits select the external event used to trigger DAC
channel2 Note: Only used if bit TEN2 = 1 (DAC
channel2 trigger enabled).</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>WAVE2</name>
<description>DAC channel2 noise/triangle wave
generation enable These bits are set/reset by
software. 1x: Triangle wave generation enabled Note:
Only used if bit TEN2 = 1 (DAC channel2 trigger
enabled)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MAMP2</name>
<description>DAC channel2 mask/amplitude selector
These bits are written by software to select mask in
wave generation mode or amplitude in triangle
generation mode. = 1011: Unmask bits[11:0] of LFSR/
triangle amplitude equal to 4095</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN2</name>
<description>DAC channel2 DMA enable This bit is set
and cleared by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAUDRIE2</name>
<description>DAC channel2 DMA underrun interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN2</name>
<description>DAC Channel 2 calibration enable This
bit is set and cleared by software to enable/disable
DAC channel 2 calibration, it can be written only if
bit EN2=0 into DAC_CR (the calibration mode can be
entered/exit only when the DAC channel is disabled)
Otherwise, the write operation is
ignored.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWTRGR</name>
<displayName>SWTRGR</displayName>
<description>DAC software trigger register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWTRIG1</name>
<description>DAC channel1 software trigger This bit
is set by software to trigger the DAC in software
trigger mode. Note: This bit is cleared by hardware
(one APB1 clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1
register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWTRIG2</name>
<description>DAC channel2 software trigger This bit
is set by software to trigger the DAC in software
trigger mode. Note: This bit is cleared by hardware
(one APB1 clock cycle later) once the DAC_DHR2
register value has been loaded into the DAC_DOR2
register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12R1</name>
<displayName>DHR12R1</displayName>
<description>DAC channel1 12-bit right-aligned data
holding register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit right-aligned data
These bits are written by software which specifies
12-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12L1</name>
<displayName>DHR12L1</displayName>
<description>DAC channel1 12-bit left aligned data
holding register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit left-aligned data
These bits are written by software which specifies
12-bit data for DAC channel1.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR8R1</name>
<displayName>DHR8R1</displayName>
<description>DAC channel1 8-bit right aligned data
holding register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 8-bit right-aligned data
These bits are written by software which specifies
8-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12R2</name>
<displayName>DHR12R2</displayName>
<description>DAC channel2 12-bit right aligned data
holding register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit right-aligned data
These bits are written by software which specifies
12-bit data for DAC channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12L2</name>
<displayName>DHR12L2</displayName>
<description>DAC channel2 12-bit left aligned data
holding register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit left-aligned data
These bits are written by software which specify
12-bit data for DAC channel2.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR8R2</name>
<displayName>DHR8R2</displayName>
<description>DAC channel2 8-bit right-aligned data
holding register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 8-bit right-aligned data
These bits are written by software which specifies
8-bit data for DAC channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12RD</name>
<displayName>DHR12RD</displayName>
<description>Dual DAC 12-bit right-aligned data holding
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit right-aligned data
These bits are written by software which specifies
12-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit right-aligned data
These bits are written by software which specifies
12-bit data for DAC channel2.</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR12LD</name>
<displayName>DHR12LD</displayName>
<description>DUAL DAC 12-bit left aligned data holding
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit left-aligned data
These bits are written by software which specifies
12-bit data for DAC channel1.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit left-aligned data
These bits are written by software which specifies
12-bit data for DAC channel2.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DHR8RD</name>
<displayName>DHR8RD</displayName>
<description>DUAL DAC 8-bit right aligned data holding
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 8-bit right-aligned data
These bits are written by software which specifies
8-bit data for DAC channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 8-bit right-aligned data
These bits are written by software which specifies
8-bit data for DAC channel2.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOR1</name>
<displayName>DOR1</displayName>
<description>DAC channel1 data output
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DOR</name>
<description>DAC channel1 data output These bits are
read-only, they contain data output for DAC
channel1.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOR2</name>
<displayName>DOR2</displayName>
<description>DAC channel2 data output
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DOR</name>
<description>DAC channel2 data output These bits are
read-only, they contain data output for DAC
channel2.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>DAC status register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAUDR1</name>
<description>DAC channel1 DMA underrun flag This bit
is set by hardware and cleared by software (by
writing it to 1).</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAL_FLAG1</name>
<description>DAC Channel 1 calibration offset status
This bit is set and cleared by hardware</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BWST1</name>
<description>DAC Channel 1 busy writing sample time
flag This bit is systematically set just after Sample
&amp; Hold mode enable and is set each time the
software writes the register DAC_SHSR1, It is cleared
by hardware when the write operation of DAC_SHSR1 is
complete. (It takes about 3LSI periods of
synchronization).</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMAUDR2</name>
<description>DAC channel2 DMA underrun flag This bit
is set by hardware and cleared by software (by
writing it to 1).</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CAL_FLAG2</name>
<description>DAC Channel 2 calibration offset status
This bit is set and cleared by hardware</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BWST2</name>
<description>DAC Channel 2 busy writing sample time
flag This bit is systematically set just after Sample
&amp; Hold mode enable and is set each time the
software writes the register DAC_SHSR2, It is cleared
by hardware when the write operation of DAC_SHSR2 is
complete. (It takes about 3 LSI periods of
synchronization).</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>DAC calibration control
register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OTRIM1</name>
<description>DAC Channel 1 offset trimming
value</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OTRIM2</name>
<description>DAC Channel 2 offset trimming
value</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCR</name>
<displayName>MCR</displayName>
<description>DAC mode control register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE1</name>
<description>DAC Channel 1 mode These bits can be
written only when the DAC is disabled and not in the
calibration mode (when bit EN1=0 and bit CEN1 =0 in
the DAC_CR register). If EN1=1 or CEN1 =1 the write
operation is ignored. They can be set and cleared by
software to select the DAC Channel 1 mode: DAC
Channel 1 in normal Mode DAC Channel 1 in sample
&amp;amp; hold mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MODE2</name>
<description>DAC Channel 2 mode These bits can be
written only when the DAC is disabled and not in the
calibration mode (when bit EN2=0 and bit CEN2 =0 in
the DAC_CR register). If EN2=1 or CEN2 =1 the write
operation is ignored. They can be set and cleared by
software to select the DAC Channel 2 mode: DAC
Channel 2 in normal Mode DAC Channel 2 in sample
&amp;amp; hold mode</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHSR1</name>
<displayName>SHSR1</displayName>
<description>DAC Sample and Hold sample time register
1</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSAMPLE1</name>
<description>DAC Channel 1 sample Time (only valid in
sample &amp;amp; hold mode) These bits can be written
when the DAC channel1 is disabled or also during
normal operation. in the latter case, the write can
be done only when BWSTx of DAC_SR register is low, If
BWSTx=1, the write operation is
ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHSR2</name>
<displayName>SHSR2</displayName>
<description>DAC Sample and Hold sample time register
2</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSAMPLE2</name>
<description>DAC Channel 2 sample Time (only valid in
sample &amp;amp; hold mode) These bits can be written
when the DAC channel2 is disabled or also during
normal operation. in the latter case, the write can
be done only when BWSTx of DAC_SR register is low, if
BWSTx=1, the write operation is
ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHHR</name>
<displayName>SHHR</displayName>
<description>DAC Sample and Hold hold time
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010001</resetValue>
<fields>
<field>
<name>THOLD1</name>
<description>DAC Channel 1 hold Time (only valid in
sample &amp;amp; hold mode) Hold time= (THOLD[9:0]) x
T LSI</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>THOLD2</name>
<description>DAC Channel 2 hold time (only valid in
sample &amp;amp; hold mode). Hold time= (THOLD[9:0])
x T LSI</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHRR</name>
<displayName>SHRR</displayName>
<description>DAC Sample and Hold refresh time
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010001</resetValue>
<fields>
<field>
<name>TREFRESH1</name>
<description>DAC Channel 1 refresh Time (only valid
in sample &amp;amp; hold mode) Refresh time=
(TREFRESH[7:0]) x T LSI</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TREFRESH2</name>
<description>DAC Channel 2 refresh Time (only valid
in sample &amp;amp; hold mode) Refresh time=
(TREFRESH[7:0]) x T LSI</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DBGMCU</name>
<description>Microcontroller Debug Unit</description>
<groupName>DBGMCU</groupName>
<baseAddress>0x5C001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IDC</name>
<displayName>IDC</displayName>
<description>DBGMCU Identity Code Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x10006480</resetValue>
<fields>
<field>
<name>DEV_ID</name>
<description>Device ID</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>REV_ID</name>
<description>Revision</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>DBGMCU Configuration Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBGSLEEP_CD</name>
<description> Allow D1 domain debug in Sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBGSTOP_CD</name>
<description>Allow D1 domain debug in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBGSTBY_CD</name>
<description>Allow D1 domain debug in Standby mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBGSTOP_SRD</name>
<description>debug in SmartRun domain Stop mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBGSTBY_SRD</name>
<description>debug in SmartRun domain Standby mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRACECLKEN</name>
<description>Trace port clock enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDDBGCKEN</name>
<description> CPU domain debug clock enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRDDBGCKEN</name>
<description>SmartRun domain debug clock enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGOEN</name>
<description>External trigger output enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB3FZ1</name>
<displayName>APB3FZ1</displayName>
<description>DBGMCU APB3 peripheral freeze register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WWDG</name>
<description>WWDG stop in debug</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1LFZ1</name>
<displayName>APB1LFZ1</displayName>
<description>DBGMCU APB1L peripheral freeze register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIM2</name>
<description>TIM2 stop in debug</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM3</name>
<description>TIM3 stop in debug</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM4</name>
<description>TIM4 stop in debug</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM5</name>
<description>TIM5 stop in debug</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM6</name>
<description>TIM6 stop in debug</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM7</name>
<description>TIM7 stop in debug</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM12</name>
<description>TIM12 stop in debug</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM13</name>
<description>TIM13 stop in debug</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM14</name>
<description>TIM14 stop in debug</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPTIM1</name>
<description> LPTIM1 stop in debug</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1</name>
<description> I2C1 SMBUS timeout stop in debug </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C2</name>
<description> I2C2 SMBUS timeout stop in debug</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C3</name>
<description> I2C3 SMBUS timeout stop in debug</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB2FZ1</name>
<displayName>APB2FZ1</displayName>
<description>DBGMCU APB2 peripheral freeze register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIM1</name>
<description> TIM1 stop in debug</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM8</name>
<description> TIM8 stop in debug</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM15</name>
<description>TIM15 stop in debug</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM16</name>
<description>TIM16 stop in debug</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM17</name>
<description> TIM17 stop in debug</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB4FZ1</name>
<displayName>APB4FZ1</displayName>
<description>DBGMCU APB4 peripheral freeze register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2C4</name>
<description>I2C4 SMBUS timeout stop in debug</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPTIM2</name>
<description> LPTIM2 stop in debug</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPTIM3</name>
<description> LPTIM3 stop in debug</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTC</name>
<description>RTC stop in debug</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDGLSCD</name>
<description>LS watchdog for CPU domain stop in debug</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DCMI</name>
<description>Digital camera interface</description>
<groupName>DCMI</groupName>
<baseAddress>0x48020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DCMI_PSSI</name>
<description>DCMI/PSSI global interrupt</description>
<value>78</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OELS</name>
<description>Odd/Even Line Select (Line Select
Start)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSM</name>
<description>Line Select mode</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OEBS</name>
<description>Odd/Even Byte Select (Byte Select
Start)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSM</name>
<description>Byte Select mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ENABLE</name>
<description>DCMI enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EDM</name>
<description>Extended data mode</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FCRC</name>
<description>Frame capture rate control</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>VSPOL</name>
<description>Vertical synchronization
polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSPOL</name>
<description>Horizontal synchronization
polarity</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKPOL</name>
<description>Pixel clock polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESS</name>
<description>Embedded synchronization
select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JPEG</name>
<description>JPEG format</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CROP</name>
<description>Crop feature</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CM</name>
<description>Capture mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAPTURE</name>
<description>Capture enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>FNE</name>
<description>FIFO not empty</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC</name>
<description>VSYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSYNC</name>
<description>HSYNC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RIS</name>
<displayName>RIS</displayName>
<description>raw interrupt status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINE_RIS</name>
<description>Line raw interrupt status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_RIS</name>
<description>VSYNC raw interrupt status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_RIS</name>
<description>Synchronization error raw interrupt
status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_RIS</name>
<description>Overrun raw interrupt
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME_RIS</name>
<description>Capture complete raw interrupt
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINE_IE</name>
<description>Line interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_IE</name>
<description>VSYNC interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_IE</name>
<description>Synchronization error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_IE</name>
<description>Overrun interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME_IE</name>
<description>Capture complete interrupt
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MIS</name>
<displayName>MIS</displayName>
<description>masked interrupt status
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINE_MIS</name>
<description>Line masked interrupt
status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_MIS</name>
<description>VSYNC masked interrupt
status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_MIS</name>
<description>Synchronization error masked interrupt
status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_MIS</name>
<description>Overrun masked interrupt
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME_MIS</name>
<description>Capture complete masked interrupt
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>interrupt clear register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINE_ISC</name>
<description>line interrupt status
clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_ISC</name>
<description>Vertical synch interrupt status
clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_ISC</name>
<description>Synchronization error interrupt status
clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_ISC</name>
<description>Overrun interrupt status
clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME_ISC</name>
<description>Capture complete interrupt status
clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESCR</name>
<displayName>ESCR</displayName>
<description>embedded synchronization code
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>FEC</name>
<description>Frame end delimiter code</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LEC</name>
<description>Line end delimiter code</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LSC</name>
<description>Line start delimiter code</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FSC</name>
<description>Frame start delimiter code</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESUR</name>
<displayName>ESUR</displayName>
<description>embedded synchronization unmask
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>FEU</name>
<description>Frame end delimiter unmask</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LEU</name>
<description>Line end delimiter unmask</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LSU</name>
<description>Line start delimiter
unmask</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FSU</name>
<description>Frame start delimiter
unmask</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CWSTRT</name>
<displayName>CWSTRT</displayName>
<description>crop window start</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>VST</name>
<description>Vertical start line count</description>
<bitOffset>16</bitOffset>
<bitWidth>13</bitWidth>
</field>
<field>
<name>HOFFCNT</name>
<description>Horizontal offset count</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>CWSIZE</name>
<displayName>CWSIZE</displayName>
<description>crop window size</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>VLINE</name>
<description>Vertical line count</description>
<bitOffset>16</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>CAPCNT</name>
<description>Capture count</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>Byte3</name>
<description>Data byte 3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>Byte2</name>
<description>Data byte 2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>Byte1</name>
<description>Data byte 1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>Byte0</name>
<description>Data byte 0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DELAY_Block_SDMMC1</name>
<description>DELAY_Block_SDMMC1</description>
<groupName>DLYB</groupName>
<baseAddress>0x52008000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PVD_PVM</name>
<description>PVD through EXTI line</description>
<value>1</value>
</interrupt>
<interrupt>
<name>WKUP</name>
<description>WKUP1 to WKUP6 pins</description>
<value>149</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>DLYB control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DEN</name>
<description>Delay block enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEN</name>
<description>Sampler length enable bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>DLYB configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEL</name>
<description>Select the phase for the Output
clock</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>UNIT</name>
<description>Delay Defines the delay of a Unit delay
cell</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>LNG</name>
<description>Delay line length value</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>LNGF</name>
<description>Length valid flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="DELAY_Block_SDMMC1">
<name>DELAY_Block_SDMMC2</name>
<baseAddress>0x48022800</baseAddress>
</peripheral>
<peripheral>
<name>DFSDM1</name>
<description>Digital filter for sigma delta
modulators</description>
<groupName>DFSDM</groupName>
<baseAddress>0x40017800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x4bc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DFSDM_CH0CFGR1</name>
<displayName>DFSDM_CH0CFGR1</displayName>
<description>DFSDM channel 0 configuration register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SITP</name>
<description>Serial interface type for channel y
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI with rising edge to strobe data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI with falling edge to strobe data</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPICKSEL</name>
<description>SPI clock select for channel y
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>clock coming from external CKINy input - sampling point according SITP[1:0]</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock coming from internal CKOUT output - sampling point according SITP[1:0]</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDEN</name>
<description>Short-circuit detector enable on channel y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Input channel y will not be guarded by the short-circuit detector</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Input channel y will be continuously guarded by the short-circuit detector </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABEN</name>
<description>Clock absence detector enable on channel y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock absence detector disabled on channel y</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock absence detector enabled on channel y</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHEN</name>
<description>Channel y enable
If channel y is enabled, then serial data receiving is started according to the given channel setting.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel y disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel y enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHINSEL</name>
<description>Channel inputs selection
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel inputs are taken from pins of the same channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATMPX</name>
<description>Input data multiplexer for channel y
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATPACK</name>
<description>Data packing mode in DFSDM_CHyDATINR register.
first sample in INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
first sample INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTDIV</name>
<description>Output serial clock divider
 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output clock generation is disabled (CKOUT signal is set to low state)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTSRC</name>
<description>Output serial clock source selection
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Source for output clock is from system clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Source for output clock is from audio clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMEN</name>
<description>Global enable for DFSDM interface
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0:
all registers DFSDM_FLTxISR are set to reset state (x = 0..7)
all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM interface disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM interface enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH0CFGR2</name>
<displayName>DFSDM_CH0CFGR2</displayName>
<description>DFSDM channel 0 configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRBS</name>
<description>Data right bit-shift for channel y
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFFSET</name>
<description>24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH0AWSCDR</name>
<displayName>DFSDM_CH0AWSCDR</displayName>
<description>DFSDM channel 0 analog watchdog and short-circuit detector register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCDT</name>
<description>short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BKSCD</name>
<description>Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFOSR</name>
<description>Analog watchdog filter oversampling ratio (decimation rate) on channel y
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFORD</name>
<description>Analog watchdog Sinc filter order on channel y
2: Sinc2 filter type
3: Sinc3 filter type
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH0WDATR</name>
<displayName>DFSDM_CH0WDATR</displayName>
<description>DFSDM channel 0 watchdog filter data register</description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDATA</name>
<description>Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH0DATINR</name>
<displayName>DFSDM_CH0DATINR</displayName>
<description>DFSDM channel 0 data input register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INDAT0</name>
<description>Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See for more details.
INDAT0[15:0] is in the16-bit signed format.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INDAT1</name>
<description>Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See for more details.
INDAT0[15:1] is in the16-bit signed format.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH0DLYR</name>
<displayName>DFSDM_CH0DLYR</displayName>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLSSKP</name>
<description>Pulses to skip for input data skipping function
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH1CFGR1</name>
<displayName>DFSDM_CH1CFGR1</displayName>
<description>DFSDM channel 1 configuration register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SITP</name>
<description>Serial interface type for channel y
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI with rising edge to strobe data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI with falling edge to strobe data</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPICKSEL</name>
<description>SPI clock select for channel y
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>clock coming from external CKINy input - sampling point according SITP[1:0]</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock coming from internal CKOUT output - sampling point according SITP[1:0]</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDEN</name>
<description>Short-circuit detector enable on channel y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Input channel y will not be guarded by the short-circuit detector</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Input channel y will be continuously guarded by the short-circuit detector </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABEN</name>
<description>Clock absence detector enable on channel y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock absence detector disabled on channel y</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock absence detector enabled on channel y</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHEN</name>
<description>Channel y enable
If channel y is enabled, then serial data receiving is started according to the given channel setting.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel y disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel y enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHINSEL</name>
<description>Channel inputs selection
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel inputs are taken from pins of the same channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATMPX</name>
<description>Input data multiplexer for channel y
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATPACK</name>
<description>Data packing mode in DFSDM_CHyDATINR register.
first sample in INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
first sample INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTDIV</name>
<description>Output serial clock divider
 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output clock generation is disabled (CKOUT signal is set to low state)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTSRC</name>
<description>Output serial clock source selection
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Source for output clock is from system clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Source for output clock is from audio clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMEN</name>
<description>Global enable for DFSDM interface
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0:
all registers DFSDM_FLTxISR are set to reset state (x = 0..7)
all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM interface disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM interface enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH1CFGR2</name>
<displayName>DFSDM_CH1CFGR2</displayName>
<description>DFSDM channel 1 configuration register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRBS</name>
<description>Data right bit-shift for channel y
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFFSET</name>
<description>24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH1AWSCDR</name>
<displayName>DFSDM_CH1AWSCDR</displayName>
<description>DFSDM channel 1 analog watchdog and short-circuit detector register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCDT</name>
<description>short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BKSCD</name>
<description>Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFOSR</name>
<description>Analog watchdog filter oversampling ratio (decimation rate) on channel y
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFORD</name>
<description>Analog watchdog Sinc filter order on channel y
2: Sinc2 filter type
3: Sinc3 filter type
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH1WDATR</name>
<displayName>DFSDM_CH1WDATR</displayName>
<description>DFSDM channel 1 watchdog filter data register</description>
<addressOffset>0x2c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDATA</name>
<description>Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH1DATINR</name>
<displayName>DFSDM_CH1DATINR</displayName>
<description>DFSDM channel 1 data input register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INDAT0</name>
<description>Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See for more details.
INDAT0[15:0] is in the16-bit signed format.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INDAT1</name>
<description>Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See for more details.
INDAT0[15:1] is in the16-bit signed format.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH1DLYR</name>
<displayName>DFSDM_CH1DLYR</displayName>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLSSKP</name>
<description>Pulses to skip for input data skipping function
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH2CFGR1</name>
<displayName>DFSDM_CH2CFGR1</displayName>
<description>DFSDM channel 2 configuration register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SITP</name>
<description>Serial interface type for channel y
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI with rising edge to strobe data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI with falling edge to strobe data</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPICKSEL</name>
<description>SPI clock select for channel y
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>clock coming from external CKINy input - sampling point according SITP[1:0]</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock coming from internal CKOUT output - sampling point according SITP[1:0]</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDEN</name>
<description>Short-circuit detector enable on channel y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Input channel y will not be guarded by the short-circuit detector</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Input channel y will be continuously guarded by the short-circuit detector </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABEN</name>
<description>Clock absence detector enable on channel y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock absence detector disabled on channel y</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock absence detector enabled on channel y</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHEN</name>
<description>Channel y enable
If channel y is enabled, then serial data receiving is started according to the given channel setting.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel y disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel y enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHINSEL</name>
<description>Channel inputs selection
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel inputs are taken from pins of the same channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATMPX</name>
<description>Input data multiplexer for channel y
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATPACK</name>
<description>Data packing mode in DFSDM_CHyDATINR register.
first sample in INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
first sample INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTDIV</name>
<description>Output serial clock divider
 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output clock generation is disabled (CKOUT signal is set to low state)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTSRC</name>
<description>Output serial clock source selection
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Source for output clock is from system clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Source for output clock is from audio clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMEN</name>
<description>Global enable for DFSDM interface
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0:
all registers DFSDM_FLTxISR are set to reset state (x = 0..7)
all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM interface disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM interface enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH2CFGR2</name>
<displayName>DFSDM_CH2CFGR2</displayName>
<description>DFSDM channel 2 configuration register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRBS</name>
<description>Data right bit-shift for channel y
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFFSET</name>
<description>24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH2AWSCDR</name>
<displayName>DFSDM_CH2AWSCDR</displayName>
<description>DFSDM channel 2 analog watchdog and short-circuit detector register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCDT</name>
<description>short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BKSCD</name>
<description>Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFOSR</name>
<description>Analog watchdog filter oversampling ratio (decimation rate) on channel y
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFORD</name>
<description>Analog watchdog Sinc filter order on channel y
2: Sinc2 filter type
3: Sinc3 filter type
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH2WDATR</name>
<displayName>DFSDM_CH2WDATR</displayName>
<description>DFSDM channel 2 watchdog filter data register</description>
<addressOffset>0x4c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDATA</name>
<description>Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH2DATINR</name>
<displayName>DFSDM_CH2DATINR</displayName>
<description>DFSDM channel 2 data input register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INDAT0</name>
<description>Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See for more details.
INDAT0[15:0] is in the16-bit signed format.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INDAT1</name>
<description>Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See for more details.
INDAT0[15:1] is in the16-bit signed format.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH2DLYR</name>
<displayName>DFSDM_CH2DLYR</displayName>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLSSKP</name>
<description>Pulses to skip for input data skipping function
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH3CFGR1</name>
<displayName>DFSDM_CH3CFGR1</displayName>
<description>DFSDM channel 3 configuration register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SITP</name>
<description>Serial interface type for channel y
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI with rising edge to strobe data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI with falling edge to strobe data</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPICKSEL</name>
<description>SPI clock select for channel y
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>clock coming from external CKINy input - sampling point according SITP[1:0]</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock coming from internal CKOUT output - sampling point according SITP[1:0]</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDEN</name>
<description>Short-circuit detector enable on channel y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Input channel y will not be guarded by the short-circuit detector</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Input channel y will be continuously guarded by the short-circuit detector </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABEN</name>
<description>Clock absence detector enable on channel y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock absence detector disabled on channel y</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock absence detector enabled on channel y</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHEN</name>
<description>Channel y enable
If channel y is enabled, then serial data receiving is started according to the given channel setting.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel y disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel y enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHINSEL</name>
<description>Channel inputs selection
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel inputs are taken from pins of the same channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATMPX</name>
<description>Input data multiplexer for channel y
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATPACK</name>
<description>Data packing mode in DFSDM_CHyDATINR register.
first sample in INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
first sample INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTDIV</name>
<description>Output serial clock divider
 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output clock generation is disabled (CKOUT signal is set to low state)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTSRC</name>
<description>Output serial clock source selection
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Source for output clock is from system clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Source for output clock is from audio clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMEN</name>
<description>Global enable for DFSDM interface
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0:
all registers DFSDM_FLTxISR are set to reset state (x = 0..7)
all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM interface disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM interface enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH3CFGR2</name>
<displayName>DFSDM_CH3CFGR2</displayName>
<description>DFSDM channel 3 configuration register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRBS</name>
<description>Data right bit-shift for channel y
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFFSET</name>
<description>24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH3AWSCDR</name>
<displayName>DFSDM_CH3AWSCDR</displayName>
<description>DFSDM channel 3 analog watchdog and short-circuit detector register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCDT</name>
<description>short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BKSCD</name>
<description>Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFOSR</name>
<description>Analog watchdog filter oversampling ratio (decimation rate) on channel y
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFORD</name>
<description>Analog watchdog Sinc filter order on channel y
2: Sinc2 filter type
3: Sinc3 filter type
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH3WDATR</name>
<displayName>DFSDM_CH3WDATR</displayName>
<description>DFSDM channel 3 watchdog filter data register</description>
<addressOffset>0x6c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDATA</name>
<description>Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH3DATINR</name>
<displayName>DFSDM_CH3DATINR</displayName>
<description>DFSDM channel 3 data input register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INDAT0</name>
<description>Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See for more details.
INDAT0[15:0] is in the16-bit signed format.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INDAT1</name>
<description>Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See for more details.
INDAT0[15:1] is in the16-bit signed format.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH3DLYR</name>
<displayName>DFSDM_CH3DLYR</displayName>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLSSKP</name>
<description>Pulses to skip for input data skipping function
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH4CFGR1</name>
<displayName>DFSDM_CH4CFGR1</displayName>
<description>DFSDM channel 4 configuration register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SITP</name>
<description>Serial interface type for channel y
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI with rising edge to strobe data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI with falling edge to strobe data</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPICKSEL</name>
<description>SPI clock select for channel y
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>clock coming from external CKINy input - sampling point according SITP[1:0]</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock coming from internal CKOUT output - sampling point according SITP[1:0]</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDEN</name>
<description>Short-circuit detector enable on channel y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Input channel y will not be guarded by the short-circuit detector</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Input channel y will be continuously guarded by the short-circuit detector </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABEN</name>
<description>Clock absence detector enable on channel y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock absence detector disabled on channel y</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock absence detector enabled on channel y</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHEN</name>
<description>Channel y enable
If channel y is enabled, then serial data receiving is started according to the given channel setting.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel y disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel y enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHINSEL</name>
<description>Channel inputs selection
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel inputs are taken from pins of the same channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATMPX</name>
<description>Input data multiplexer for channel y
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATPACK</name>
<description>Data packing mode in DFSDM_CHyDATINR register.
first sample in INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
first sample INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTDIV</name>
<description>Output serial clock divider
 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output clock generation is disabled (CKOUT signal is set to low state)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTSRC</name>
<description>Output serial clock source selection
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Source for output clock is from system clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Source for output clock is from audio clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMEN</name>
<description>Global enable for DFSDM interface
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0:
all registers DFSDM_FLTxISR are set to reset state (x = 0..7)
all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM interface disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM interface enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH4CFGR2</name>
<displayName>DFSDM_CH4CFGR2</displayName>
<description>DFSDM channel 4 configuration register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRBS</name>
<description>Data right bit-shift for channel y
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFFSET</name>
<description>24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH4AWSCDR</name>
<displayName>DFSDM_CH4AWSCDR</displayName>
<description>DFSDM channel 4 analog watchdog and short-circuit detector register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCDT</name>
<description>short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BKSCD</name>
<description>Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFOSR</name>
<description>Analog watchdog filter oversampling ratio (decimation rate) on channel y
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFORD</name>
<description>Analog watchdog Sinc filter order on channel y
2: Sinc2 filter type
3: Sinc3 filter type
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH4WDATR</name>
<displayName>DFSDM_CH4WDATR</displayName>
<description>DFSDM channel 4 watchdog filter data register</description>
<addressOffset>0x8c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDATA</name>
<description>Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH4DATINR</name>
<displayName>DFSDM_CH4DATINR</displayName>
<description>DFSDM channel 4 data input register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INDAT0</name>
<description>Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See for more details.
INDAT0[15:0] is in the16-bit signed format.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INDAT1</name>
<description>Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See for more details.
INDAT0[15:1] is in the16-bit signed format.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH4DLYR</name>
<displayName>DFSDM_CH4DLYR</displayName>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLSSKP</name>
<description>Pulses to skip for input data skipping function
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH5CFGR1</name>
<displayName>DFSDM_CH5CFGR1</displayName>
<description>DFSDM channel 5 configuration register</description>
<addressOffset>0xa0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SITP</name>
<description>Serial interface type for channel y
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI with rising edge to strobe data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI with falling edge to strobe data</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPICKSEL</name>
<description>SPI clock select for channel y
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>clock coming from external CKINy input - sampling point according SITP[1:0]</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock coming from internal CKOUT output - sampling point according SITP[1:0]</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDEN</name>
<description>Short-circuit detector enable on channel y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Input channel y will not be guarded by the short-circuit detector</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Input channel y will be continuously guarded by the short-circuit detector </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABEN</name>
<description>Clock absence detector enable on channel y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock absence detector disabled on channel y</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock absence detector enabled on channel y</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHEN</name>
<description>Channel y enable
If channel y is enabled, then serial data receiving is started according to the given channel setting.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel y disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel y enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHINSEL</name>
<description>Channel inputs selection
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel inputs are taken from pins of the same channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATMPX</name>
<description>Input data multiplexer for channel y
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATPACK</name>
<description>Data packing mode in DFSDM_CHyDATINR register.
first sample in INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
first sample INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTDIV</name>
<description>Output serial clock divider
 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output clock generation is disabled (CKOUT signal is set to low state)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTSRC</name>
<description>Output serial clock source selection
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Source for output clock is from system clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Source for output clock is from audio clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMEN</name>
<description>Global enable for DFSDM interface
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0:
all registers DFSDM_FLTxISR are set to reset state (x = 0..7)
all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM interface disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM interface enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH5CFGR2</name>
<displayName>DFSDM_CH5CFGR2</displayName>
<description>DFSDM channel 5 configuration register</description>
<addressOffset>0xa4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRBS</name>
<description>Data right bit-shift for channel y
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFFSET</name>
<description>24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH5AWSCDR</name>
<displayName>DFSDM_CH5AWSCDR</displayName>
<description>DFSDM channel 5 analog watchdog and short-circuit detector register</description>
<addressOffset>0xa8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCDT</name>
<description>short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BKSCD</name>
<description>Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFOSR</name>
<description>Analog watchdog filter oversampling ratio (decimation rate) on channel y
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFORD</name>
<description>Analog watchdog Sinc filter order on channel y
2: Sinc2 filter type
3: Sinc3 filter type
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH5WDATR</name>
<displayName>DFSDM_CH5WDATR</displayName>
<description>DFSDM channel 5 watchdog filter data register</description>
<addressOffset>0xac</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDATA</name>
<description>Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH5DATINR</name>
<displayName>DFSDM_CH5DATINR</displayName>
<description>DFSDM channel 5 data input register</description>
<addressOffset>0xb0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INDAT0</name>
<description>Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See for more details.
INDAT0[15:0] is in the16-bit signed format.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INDAT1</name>
<description>Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See for more details.
INDAT0[15:1] is in the16-bit signed format.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH5DLYR</name>
<displayName>DFSDM_CH5DLYR</displayName>
<addressOffset>0xb4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLSSKP</name>
<description>Pulses to skip for input data skipping function
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH6CFGR1</name>
<displayName>DFSDM_CH6CFGR1</displayName>
<description>DFSDM channel 6 configuration register</description>
<addressOffset>0xc0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SITP</name>
<description>Serial interface type for channel y
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI with rising edge to strobe data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI with falling edge to strobe data</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPICKSEL</name>
<description>SPI clock select for channel y
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>clock coming from external CKINy input - sampling point according SITP[1:0]</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock coming from internal CKOUT output - sampling point according SITP[1:0]</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDEN</name>
<description>Short-circuit detector enable on channel y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Input channel y will not be guarded by the short-circuit detector</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Input channel y will be continuously guarded by the short-circuit detector </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABEN</name>
<description>Clock absence detector enable on channel y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock absence detector disabled on channel y</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock absence detector enabled on channel y</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHEN</name>
<description>Channel y enable
If channel y is enabled, then serial data receiving is started according to the given channel setting.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel y disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel y enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHINSEL</name>
<description>Channel inputs selection
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel inputs are taken from pins of the same channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATMPX</name>
<description>Input data multiplexer for channel y
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATPACK</name>
<description>Data packing mode in DFSDM_CHyDATINR register.
first sample in INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
first sample INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTDIV</name>
<description>Output serial clock divider
 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output clock generation is disabled (CKOUT signal is set to low state)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTSRC</name>
<description>Output serial clock source selection
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Source for output clock is from system clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Source for output clock is from audio clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMEN</name>
<description>Global enable for DFSDM interface
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0:
all registers DFSDM_FLTxISR are set to reset state (x = 0..7)
all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM interface disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM interface enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH6CFGR2</name>
<displayName>DFSDM_CH6CFGR2</displayName>
<description>DFSDM channel 6 configuration register</description>
<addressOffset>0xc4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRBS</name>
<description>Data right bit-shift for channel y
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFFSET</name>
<description>24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH6AWSCDR</name>
<displayName>DFSDM_CH6AWSCDR</displayName>
<description>DFSDM channel 6 analog watchdog and short-circuit detector register</description>
<addressOffset>0xc8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCDT</name>
<description>short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BKSCD</name>
<description>Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFOSR</name>
<description>Analog watchdog filter oversampling ratio (decimation rate) on channel y
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFORD</name>
<description>Analog watchdog Sinc filter order on channel y
2: Sinc2 filter type
3: Sinc3 filter type
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH6WDATR</name>
<displayName>DFSDM_CH6WDATR</displayName>
<description>DFSDM channel 6 watchdog filter data register</description>
<addressOffset>0xcc</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDATA</name>
<description>Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH6DATINR</name>
<displayName>DFSDM_CH6DATINR</displayName>
<description>DFSDM channel 6 data input register</description>
<addressOffset>0xd0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INDAT0</name>
<description>Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See for more details.
INDAT0[15:0] is in the16-bit signed format.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INDAT1</name>
<description>Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See for more details.
INDAT0[15:1] is in the16-bit signed format.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH6DLYR</name>
<displayName>DFSDM_CH6DLYR</displayName>
<addressOffset>0xd4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLSSKP</name>
<description>Pulses to skip for input data skipping function
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH7CFGR1</name>
<displayName>DFSDM_CH7CFGR1</displayName>
<description>DFSDM channel 7 configuration register</description>
<addressOffset>0xe0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SITP</name>
<description>Serial interface type for channel y
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI with rising edge to strobe data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI with falling edge to strobe data</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPICKSEL</name>
<description>SPI clock select for channel y
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>clock coming from external CKINy input - sampling point according SITP[1:0]</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock coming from internal CKOUT output - sampling point according SITP[1:0]</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDEN</name>
<description>Short-circuit detector enable on channel y</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Input channel y will not be guarded by the short-circuit detector</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Input channel y will be continuously guarded by the short-circuit detector </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABEN</name>
<description>Clock absence detector enable on channel y</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Clock absence detector disabled on channel y</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Clock absence detector enabled on channel y</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHEN</name>
<description>Channel y enable
If channel y is enabled, then serial data receiving is started according to the given channel setting.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel y disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel y enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHINSEL</name>
<description>Channel inputs selection
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel inputs are taken from pins of the same channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATMPX</name>
<description>Input data multiplexer for channel y
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATPACK</name>
<description>Data packing mode in DFSDM_CHyDATINR register.
first sample in INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
first sample INDAT0[15:0] (assigned to channel y)
second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTDIV</name>
<description>Output serial clock divider
 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output clock generation is disabled (CKOUT signal is set to low state)</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKOUTSRC</name>
<description>Output serial clock source selection
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Source for output clock is from system clock</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Source for output clock is from audio clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMEN</name>
<description>Global enable for DFSDM interface
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0:
all registers DFSDM_FLTxISR are set to reset state (x = 0..7)
all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM interface disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM interface enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH7CFGR2</name>
<displayName>DFSDM_CH7CFGR2</displayName>
<description>DFSDM channel 7 configuration register</description>
<addressOffset>0xe4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTRBS</name>
<description>Data right bit-shift for channel y
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OFFSET</name>
<description>24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH7AWSCDR</name>
<displayName>DFSDM_CH7AWSCDR</displayName>
<description>DFSDM channel 7 analog watchdog and short-circuit detector register</description>
<addressOffset>0xe8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCDT</name>
<description>short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BKSCD</name>
<description>Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFOSR</name>
<description>Analog watchdog filter oversampling ratio (decimation rate) on channel y
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWFORD</name>
<description>Analog watchdog Sinc filter order on channel y
2: Sinc2 filter type
3: Sinc3 filter type
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH7WDATR</name>
<displayName>DFSDM_CH7WDATR</displayName>
<description>DFSDM channel 7 watchdog filter data register</description>
<addressOffset>0xec</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDATA</name>
<description>Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH7DATINR</name>
<displayName>DFSDM_CH7DATINR</displayName>
<description>DFSDM channel 7 data input register</description>
<addressOffset>0xf0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INDAT0</name>
<description>Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See for more details.
INDAT0[15:0] is in the16-bit signed format.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INDAT1</name>
<description>Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See for more details.
INDAT0[15:1] is in the16-bit signed format.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_CH7DLYR</name>
<displayName>DFSDM_CH7DLYR</displayName>
<addressOffset>0xf4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLSSKP</name>
<description>Pulses to skip for input data skipping function
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0CR1</name>
<displayName>DFSDM_FLT0CR1</displayName>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFEN</name>
<description>DFSDM_FLTx enable
Data which are cleared by setting DFEN=0:
register DFSDM_FLTxISR is set to the reset state
register DFSDM_FLTxAWSR is set to the reset state</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start a conversion of the injected group of channels
This bit is always read as '0’.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSYNC</name>
<description>Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch an injected conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSCAN</name>
<description>Scanning conversion mode for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JDMAEN</name>
<description>DMA channel enabled to read data for the injected channel group
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read injected data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read injected data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>Trigger signal selection for launching injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).
DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to .
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JEXTEN</name>
<description>Trigger enable and trigger edge selection for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Trigger detection is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Each rising edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Each falling edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Both rising edges and falling edges on the selected trigger make requests to launch injected conversions</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSWSTART</name>
<description>Software start of a conversion on the regular channel
This bit is always read as '0’.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCONT</name>
<description>Continuous mode selection for regular conversions
Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regular channel is converted just once for each conversion request</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regular channel is converted repeatedly after each conversion request</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNC</name>
<description>Launch regular conversion synchronously with DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch a regular conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>DMA channel enabled to read data for the regular conversion
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read regular data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read regular data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCH</name>
<description>Regular channel selection
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel 0 is selected as the regular channel</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel 1 is selected as the regular channel</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST</name>
<description>Fast conversion mode selection for regular conversions
When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Fast conversion mode disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Fast conversion mode enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWFSEL</name>
<description>Analog watchdog fast mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog on channel transceivers value (after watchdog filter)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0CR2</name>
<displayName>DFSDM_FLT0CR2</displayName>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCIE</name>
<description>Injected end of conversion interrupt enable
Please see the explanation of JEOCF in DFSDM_FLTxISR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCIE</name>
<description>Regular end of conversion interrupt enable
Please see the explanation of REOCF in DFSDM_FLTxISR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRIE</name>
<description>Injected data overrun interrupt enable
Please see the explanation of JOVRF in DFSDM_FLTxISR.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRIE</name>
<description>Regular data overrun interrupt enable
Please see the explanation of ROVRF in DFSDM_FLTxISR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt enable
Please see the explanation of AWDF in DFSDM_FLTxISR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDIE</name>
<description>Short-circuit detector interrupt enable
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>short-circuit detector interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>short-circuit detector interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABIE</name>
<description>Clock absence interrupt enable
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection of channel input clock absence interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection of channel input clock absence interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXCH</name>
<description>Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0ISR</name>
<displayName>DFSDM_FLT0ISR</displayName>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<resetValue>0x00FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCF</name>
<description>End of injected conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCF</name>
<description>End of regular conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRF</name>
<description>Injected conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRF</name>
<description>Regular conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDF</name>
<description>Analog watchdog
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No Analog watchdog event occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JCIP</name>
<description>Injected conversion in progress status
A request to start an injected conversion is ignored when JCIP=1.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the injected channel group (neither by software nor by trigger) has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCIP</name>
<description>Regular conversion in progress status
A request to start a regular conversion is ignored when RCIP=1.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the regular channel has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the regular channel is in progress or a request for a regular conversion is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABF</name>
<description>Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCDF</name>
<description>short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0ICR</name>
<displayName>DFSDM_FLT0ICR</displayName>
<addressOffset>0x10c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRJOVRF</name>
<description>Clear the injected conversion overrun flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRROVRF</name>
<description>Clear the regular conversion overrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCKABF</name>
<description>Clear the clock absence flag
CLRCKABF[y]=0: Writing '0’ has no effect
CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRSCDF</name>
<description>Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing '0’ has no effect
CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0JCHGR</name>
<displayName>DFSDM_FLT0JCHGR</displayName>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JCHG</name>
<description>Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0FCR</name>
<displayName>DFSDM_FLT0FCR</displayName>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IOSR</name>
<description>Integrator oversampling ratio (averaging length)
from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FOSR</name>
<description>Sinc filter oversampling ratio (decimation rate)
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FORD</name>
<description>Sinc filter order
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0JDATAR</name>
<displayName>DFSDM_FLT0JDATAR</displayName>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JDATACH</name>
<description>Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>JDATA</name>
<description>Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0RDATAR</name>
<displayName>DFSDM_FLT0RDATAR</displayName>
<addressOffset>0x11c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATACH</name>
<description>Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RPEND</name>
<description>Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDATA</name>
<description>Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0AWHTR</name>
<displayName>DFSDM_FLT0AWHTR</displayName>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWH</name>
<description>Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWHT</name>
<description>Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0AWLTR</name>
<displayName>DFSDM_FLT0AWLTR</displayName>
<addressOffset>0x124</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWL</name>
<description>Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWLT</name>
<description>Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0AWSR</name>
<displayName>DFSDM_FLT0AWSR</displayName>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AWLTF</name>
<description>Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AWHTF</name>
<description>Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0AWCFR</name>
<displayName>DFSDM_FLT0AWCFR</displayName>
<addressOffset>0x12c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRAWLTF</name>
<description>Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0’ has no effect
CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRAWHTF</name>
<description>Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0’ has no effect
CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0EXMAX</name>
<displayName>DFSDM_FLT0EXMAX</displayName>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMAXCH</name>
<description>Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMAX</name>
<description>Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
<readAction>set</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0EXMIN</name>
<displayName>DFSDM_FLT0EXMIN</displayName>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<resetValue>0x7FFFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMINCH</name>
<description>Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMIN</name>
<description>Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
<readAction>clear</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT0CNVTIMR</name>
<displayName>DFSDM_FLT0CNVTIMR</displayName>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNVCNT</name>
<description>28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.</description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1CR1</name>
<displayName>DFSDM_FLT1CR1</displayName>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFEN</name>
<description>DFSDM_FLTx enable
Data which are cleared by setting DFEN=0:
register DFSDM_FLTxISR is set to the reset state
register DFSDM_FLTxAWSR is set to the reset state</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start a conversion of the injected group of channels
This bit is always read as '0’.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSYNC</name>
<description>Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch an injected conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSCAN</name>
<description>Scanning conversion mode for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JDMAEN</name>
<description>DMA channel enabled to read data for the injected channel group
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read injected data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read injected data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>Trigger signal selection for launching injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).
DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to .
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JEXTEN</name>
<description>Trigger enable and trigger edge selection for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Trigger detection is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Each rising edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Each falling edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Both rising edges and falling edges on the selected trigger make requests to launch injected conversions</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSWSTART</name>
<description>Software start of a conversion on the regular channel
This bit is always read as '0’.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCONT</name>
<description>Continuous mode selection for regular conversions
Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regular channel is converted just once for each conversion request</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regular channel is converted repeatedly after each conversion request</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNC</name>
<description>Launch regular conversion synchronously with DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch a regular conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>DMA channel enabled to read data for the regular conversion
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read regular data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read regular data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCH</name>
<description>Regular channel selection
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel 0 is selected as the regular channel</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel 1 is selected as the regular channel</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST</name>
<description>Fast conversion mode selection for regular conversions
When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Fast conversion mode disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Fast conversion mode enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWFSEL</name>
<description>Analog watchdog fast mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog on channel transceivers value (after watchdog filter)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1CR2</name>
<displayName>DFSDM_FLT1CR2</displayName>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCIE</name>
<description>Injected end of conversion interrupt enable
Please see the explanation of JEOCF in DFSDM_FLTxISR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCIE</name>
<description>Regular end of conversion interrupt enable
Please see the explanation of REOCF in DFSDM_FLTxISR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRIE</name>
<description>Injected data overrun interrupt enable
Please see the explanation of JOVRF in DFSDM_FLTxISR.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRIE</name>
<description>Regular data overrun interrupt enable
Please see the explanation of ROVRF in DFSDM_FLTxISR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt enable
Please see the explanation of AWDF in DFSDM_FLTxISR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDIE</name>
<description>Short-circuit detector interrupt enable
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>short-circuit detector interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>short-circuit detector interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABIE</name>
<description>Clock absence interrupt enable
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection of channel input clock absence interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection of channel input clock absence interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXCH</name>
<description>Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1ISR</name>
<displayName>DFSDM_FLT1ISR</displayName>
<addressOffset>0x188</addressOffset>
<size>0x20</size>
<resetValue>0x00FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCF</name>
<description>End of injected conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCF</name>
<description>End of regular conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRF</name>
<description>Injected conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRF</name>
<description>Regular conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDF</name>
<description>Analog watchdog
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No Analog watchdog event occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JCIP</name>
<description>Injected conversion in progress status
A request to start an injected conversion is ignored when JCIP=1.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the injected channel group (neither by software nor by trigger) has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCIP</name>
<description>Regular conversion in progress status
A request to start a regular conversion is ignored when RCIP=1.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the regular channel has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the regular channel is in progress or a request for a regular conversion is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABF</name>
<description>Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCDF</name>
<description>short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1ICR</name>
<displayName>DFSDM_FLT1ICR</displayName>
<addressOffset>0x18c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRJOVRF</name>
<description>Clear the injected conversion overrun flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRROVRF</name>
<description>Clear the regular conversion overrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCKABF</name>
<description>Clear the clock absence flag
CLRCKABF[y]=0: Writing '0’ has no effect
CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRSCDF</name>
<description>Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing '0’ has no effect
CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1JCHGR</name>
<displayName>DFSDM_FLT1JCHGR</displayName>
<addressOffset>0x190</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JCHG</name>
<description>Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1FCR</name>
<displayName>DFSDM_FLT1FCR</displayName>
<addressOffset>0x194</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IOSR</name>
<description>Integrator oversampling ratio (averaging length)
from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FOSR</name>
<description>Sinc filter oversampling ratio (decimation rate)
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FORD</name>
<description>Sinc filter order
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1JDATAR</name>
<displayName>DFSDM_FLT1JDATAR</displayName>
<addressOffset>0x198</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JDATACH</name>
<description>Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>JDATA</name>
<description>Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1RDATAR</name>
<displayName>DFSDM_FLT1RDATAR</displayName>
<addressOffset>0x19c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATACH</name>
<description>Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RPEND</name>
<description>Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDATA</name>
<description>Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1AWHTR</name>
<displayName>DFSDM_FLT1AWHTR</displayName>
<addressOffset>0x1a0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWH</name>
<description>Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWHT</name>
<description>Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1AWLTR</name>
<displayName>DFSDM_FLT1AWLTR</displayName>
<addressOffset>0x1a4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWL</name>
<description>Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWLT</name>
<description>Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1AWSR</name>
<displayName>DFSDM_FLT1AWSR</displayName>
<addressOffset>0x1a8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AWLTF</name>
<description>Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AWHTF</name>
<description>Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1AWCFR</name>
<displayName>DFSDM_FLT1AWCFR</displayName>
<addressOffset>0x1ac</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRAWLTF</name>
<description>Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0’ has no effect
CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRAWHTF</name>
<description>Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0’ has no effect
CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1EXMAX</name>
<displayName>DFSDM_FLT1EXMAX</displayName>
<addressOffset>0x1b0</addressOffset>
<size>0x20</size>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMAXCH</name>
<description>Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMAX</name>
<description>Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
<readAction>set</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1EXMIN</name>
<displayName>DFSDM_FLT1EXMIN</displayName>
<addressOffset>0x1b4</addressOffset>
<size>0x20</size>
<resetValue>0x7FFFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMINCH</name>
<description>Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMIN</name>
<description>Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
<readAction>clear</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT1CNVTIMR</name>
<displayName>DFSDM_FLT1CNVTIMR</displayName>
<addressOffset>0x1b8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNVCNT</name>
<description>28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.</description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2CR1</name>
<displayName>DFSDM_FLT2CR1</displayName>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFEN</name>
<description>DFSDM_FLTx enable
Data which are cleared by setting DFEN=0:
register DFSDM_FLTxISR is set to the reset state
register DFSDM_FLTxAWSR is set to the reset state</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start a conversion of the injected group of channels
This bit is always read as '0’.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSYNC</name>
<description>Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch an injected conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSCAN</name>
<description>Scanning conversion mode for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JDMAEN</name>
<description>DMA channel enabled to read data for the injected channel group
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read injected data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read injected data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>Trigger signal selection for launching injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).
DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to .
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JEXTEN</name>
<description>Trigger enable and trigger edge selection for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Trigger detection is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Each rising edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Each falling edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Both rising edges and falling edges on the selected trigger make requests to launch injected conversions</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSWSTART</name>
<description>Software start of a conversion on the regular channel
This bit is always read as '0’.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCONT</name>
<description>Continuous mode selection for regular conversions
Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regular channel is converted just once for each conversion request</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regular channel is converted repeatedly after each conversion request</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNC</name>
<description>Launch regular conversion synchronously with DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch a regular conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>DMA channel enabled to read data for the regular conversion
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read regular data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read regular data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCH</name>
<description>Regular channel selection
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel 0 is selected as the regular channel</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel 1 is selected as the regular channel</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST</name>
<description>Fast conversion mode selection for regular conversions
When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Fast conversion mode disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Fast conversion mode enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWFSEL</name>
<description>Analog watchdog fast mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog on channel transceivers value (after watchdog filter)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2CR2</name>
<displayName>DFSDM_FLT2CR2</displayName>
<addressOffset>0x204</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCIE</name>
<description>Injected end of conversion interrupt enable
Please see the explanation of JEOCF in DFSDM_FLTxISR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCIE</name>
<description>Regular end of conversion interrupt enable
Please see the explanation of REOCF in DFSDM_FLTxISR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRIE</name>
<description>Injected data overrun interrupt enable
Please see the explanation of JOVRF in DFSDM_FLTxISR.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRIE</name>
<description>Regular data overrun interrupt enable
Please see the explanation of ROVRF in DFSDM_FLTxISR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt enable
Please see the explanation of AWDF in DFSDM_FLTxISR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDIE</name>
<description>Short-circuit detector interrupt enable
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>short-circuit detector interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>short-circuit detector interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABIE</name>
<description>Clock absence interrupt enable
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection of channel input clock absence interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection of channel input clock absence interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXCH</name>
<description>Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2ISR</name>
<displayName>DFSDM_FLT2ISR</displayName>
<addressOffset>0x208</addressOffset>
<size>0x20</size>
<resetValue>0x00FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCF</name>
<description>End of injected conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCF</name>
<description>End of regular conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRF</name>
<description>Injected conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRF</name>
<description>Regular conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDF</name>
<description>Analog watchdog
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No Analog watchdog event occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JCIP</name>
<description>Injected conversion in progress status
A request to start an injected conversion is ignored when JCIP=1.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the injected channel group (neither by software nor by trigger) has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCIP</name>
<description>Regular conversion in progress status
A request to start a regular conversion is ignored when RCIP=1.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the regular channel has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the regular channel is in progress or a request for a regular conversion is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABF</name>
<description>Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCDF</name>
<description>short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2ICR</name>
<displayName>DFSDM_FLT2ICR</displayName>
<addressOffset>0x20c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRJOVRF</name>
<description>Clear the injected conversion overrun flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRROVRF</name>
<description>Clear the regular conversion overrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCKABF</name>
<description>Clear the clock absence flag
CLRCKABF[y]=0: Writing '0’ has no effect
CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRSCDF</name>
<description>Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing '0’ has no effect
CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2JCHGR</name>
<displayName>DFSDM_FLT2JCHGR</displayName>
<addressOffset>0x210</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JCHG</name>
<description>Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2FCR</name>
<displayName>DFSDM_FLT2FCR</displayName>
<addressOffset>0x214</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IOSR</name>
<description>Integrator oversampling ratio (averaging length)
from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FOSR</name>
<description>Sinc filter oversampling ratio (decimation rate)
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FORD</name>
<description>Sinc filter order
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2JDATAR</name>
<displayName>DFSDM_FLT2JDATAR</displayName>
<addressOffset>0x218</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JDATACH</name>
<description>Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>JDATA</name>
<description>Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2RDATAR</name>
<displayName>DFSDM_FLT2RDATAR</displayName>
<addressOffset>0x21c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATACH</name>
<description>Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RPEND</name>
<description>Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDATA</name>
<description>Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2AWHTR</name>
<displayName>DFSDM_FLT2AWHTR</displayName>
<addressOffset>0x220</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWH</name>
<description>Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWHT</name>
<description>Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2AWLTR</name>
<displayName>DFSDM_FLT2AWLTR</displayName>
<addressOffset>0x224</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWL</name>
<description>Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWLT</name>
<description>Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2AWSR</name>
<displayName>DFSDM_FLT2AWSR</displayName>
<addressOffset>0x228</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AWLTF</name>
<description>Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AWHTF</name>
<description>Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2AWCFR</name>
<displayName>DFSDM_FLT2AWCFR</displayName>
<addressOffset>0x22c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRAWLTF</name>
<description>Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0’ has no effect
CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRAWHTF</name>
<description>Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0’ has no effect
CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2EXMAX</name>
<displayName>DFSDM_FLT2EXMAX</displayName>
<addressOffset>0x230</addressOffset>
<size>0x20</size>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMAXCH</name>
<description>Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMAX</name>
<description>Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
<readAction>set</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2EXMIN</name>
<displayName>DFSDM_FLT2EXMIN</displayName>
<addressOffset>0x234</addressOffset>
<size>0x20</size>
<resetValue>0x7FFFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMINCH</name>
<description>Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMIN</name>
<description>Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
<readAction>clear</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT2CNVTIMR</name>
<displayName>DFSDM_FLT2CNVTIMR</displayName>
<addressOffset>0x238</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNVCNT</name>
<description>28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.</description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3CR1</name>
<displayName>DFSDM_FLT3CR1</displayName>
<addressOffset>0x280</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFEN</name>
<description>DFSDM_FLTx enable
Data which are cleared by setting DFEN=0:
register DFSDM_FLTxISR is set to the reset state
register DFSDM_FLTxAWSR is set to the reset state</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start a conversion of the injected group of channels
This bit is always read as '0’.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSYNC</name>
<description>Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch an injected conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSCAN</name>
<description>Scanning conversion mode for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JDMAEN</name>
<description>DMA channel enabled to read data for the injected channel group
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read injected data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read injected data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>Trigger signal selection for launching injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).
DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to .
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JEXTEN</name>
<description>Trigger enable and trigger edge selection for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Trigger detection is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Each rising edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Each falling edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Both rising edges and falling edges on the selected trigger make requests to launch injected conversions</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSWSTART</name>
<description>Software start of a conversion on the regular channel
This bit is always read as '0’.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCONT</name>
<description>Continuous mode selection for regular conversions
Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regular channel is converted just once for each conversion request</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regular channel is converted repeatedly after each conversion request</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNC</name>
<description>Launch regular conversion synchronously with DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch a regular conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>DMA channel enabled to read data for the regular conversion
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read regular data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read regular data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCH</name>
<description>Regular channel selection
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel 0 is selected as the regular channel</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel 1 is selected as the regular channel</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST</name>
<description>Fast conversion mode selection for regular conversions
When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Fast conversion mode disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Fast conversion mode enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWFSEL</name>
<description>Analog watchdog fast mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog on channel transceivers value (after watchdog filter)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3CR2</name>
<displayName>DFSDM_FLT3CR2</displayName>
<addressOffset>0x284</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCIE</name>
<description>Injected end of conversion interrupt enable
Please see the explanation of JEOCF in DFSDM_FLTxISR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCIE</name>
<description>Regular end of conversion interrupt enable
Please see the explanation of REOCF in DFSDM_FLTxISR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRIE</name>
<description>Injected data overrun interrupt enable
Please see the explanation of JOVRF in DFSDM_FLTxISR.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRIE</name>
<description>Regular data overrun interrupt enable
Please see the explanation of ROVRF in DFSDM_FLTxISR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt enable
Please see the explanation of AWDF in DFSDM_FLTxISR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDIE</name>
<description>Short-circuit detector interrupt enable
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>short-circuit detector interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>short-circuit detector interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABIE</name>
<description>Clock absence interrupt enable
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection of channel input clock absence interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection of channel input clock absence interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXCH</name>
<description>Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3ISR</name>
<displayName>DFSDM_FLT3ISR</displayName>
<addressOffset>0x288</addressOffset>
<size>0x20</size>
<resetValue>0x00FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCF</name>
<description>End of injected conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCF</name>
<description>End of regular conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRF</name>
<description>Injected conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRF</name>
<description>Regular conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDF</name>
<description>Analog watchdog
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No Analog watchdog event occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JCIP</name>
<description>Injected conversion in progress status
A request to start an injected conversion is ignored when JCIP=1.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the injected channel group (neither by software nor by trigger) has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCIP</name>
<description>Regular conversion in progress status
A request to start a regular conversion is ignored when RCIP=1.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the regular channel has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the regular channel is in progress or a request for a regular conversion is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABF</name>
<description>Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCDF</name>
<description>short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3ICR</name>
<displayName>DFSDM_FLT3ICR</displayName>
<addressOffset>0x28c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRJOVRF</name>
<description>Clear the injected conversion overrun flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRROVRF</name>
<description>Clear the regular conversion overrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCKABF</name>
<description>Clear the clock absence flag
CLRCKABF[y]=0: Writing '0’ has no effect
CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRSCDF</name>
<description>Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing '0’ has no effect
CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3JCHGR</name>
<displayName>DFSDM_FLT3JCHGR</displayName>
<addressOffset>0x290</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JCHG</name>
<description>Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3FCR</name>
<displayName>DFSDM_FLT3FCR</displayName>
<addressOffset>0x294</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IOSR</name>
<description>Integrator oversampling ratio (averaging length)
from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FOSR</name>
<description>Sinc filter oversampling ratio (decimation rate)
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FORD</name>
<description>Sinc filter order
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3JDATAR</name>
<displayName>DFSDM_FLT3JDATAR</displayName>
<addressOffset>0x298</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JDATACH</name>
<description>Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>JDATA</name>
<description>Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3RDATAR</name>
<displayName>DFSDM_FLT3RDATAR</displayName>
<addressOffset>0x29c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATACH</name>
<description>Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RPEND</name>
<description>Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDATA</name>
<description>Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3AWHTR</name>
<displayName>DFSDM_FLT3AWHTR</displayName>
<addressOffset>0x2a0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWH</name>
<description>Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWHT</name>
<description>Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3AWLTR</name>
<displayName>DFSDM_FLT3AWLTR</displayName>
<addressOffset>0x2a4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWL</name>
<description>Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWLT</name>
<description>Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3AWSR</name>
<displayName>DFSDM_FLT3AWSR</displayName>
<addressOffset>0x2a8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AWLTF</name>
<description>Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AWHTF</name>
<description>Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3AWCFR</name>
<displayName>DFSDM_FLT3AWCFR</displayName>
<addressOffset>0x2ac</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRAWLTF</name>
<description>Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0’ has no effect
CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRAWHTF</name>
<description>Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0’ has no effect
CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3EXMAX</name>
<displayName>DFSDM_FLT3EXMAX</displayName>
<addressOffset>0x2b0</addressOffset>
<size>0x20</size>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMAXCH</name>
<description>Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMAX</name>
<description>Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
<readAction>set</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3EXMIN</name>
<displayName>DFSDM_FLT3EXMIN</displayName>
<addressOffset>0x2b4</addressOffset>
<size>0x20</size>
<resetValue>0x7FFFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMINCH</name>
<description>Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMIN</name>
<description>Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
<readAction>clear</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT3CNVTIMR</name>
<displayName>DFSDM_FLT3CNVTIMR</displayName>
<addressOffset>0x2b8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNVCNT</name>
<description>28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.</description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4CR1</name>
<displayName>DFSDM_FLT4CR1</displayName>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFEN</name>
<description>DFSDM_FLTx enable
Data which are cleared by setting DFEN=0:
register DFSDM_FLTxISR is set to the reset state
register DFSDM_FLTxAWSR is set to the reset state</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start a conversion of the injected group of channels
This bit is always read as '0’.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSYNC</name>
<description>Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch an injected conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSCAN</name>
<description>Scanning conversion mode for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JDMAEN</name>
<description>DMA channel enabled to read data for the injected channel group
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read injected data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read injected data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>Trigger signal selection for launching injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).
DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to .
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JEXTEN</name>
<description>Trigger enable and trigger edge selection for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Trigger detection is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Each rising edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Each falling edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Both rising edges and falling edges on the selected trigger make requests to launch injected conversions</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSWSTART</name>
<description>Software start of a conversion on the regular channel
This bit is always read as '0’.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCONT</name>
<description>Continuous mode selection for regular conversions
Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regular channel is converted just once for each conversion request</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regular channel is converted repeatedly after each conversion request</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNC</name>
<description>Launch regular conversion synchronously with DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch a regular conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>DMA channel enabled to read data for the regular conversion
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read regular data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read regular data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCH</name>
<description>Regular channel selection
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel 0 is selected as the regular channel</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel 1 is selected as the regular channel</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST</name>
<description>Fast conversion mode selection for regular conversions
When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Fast conversion mode disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Fast conversion mode enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWFSEL</name>
<description>Analog watchdog fast mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog on channel transceivers value (after watchdog filter)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4CR2</name>
<displayName>DFSDM_FLT4CR2</displayName>
<addressOffset>0x304</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCIE</name>
<description>Injected end of conversion interrupt enable
Please see the explanation of JEOCF in DFSDM_FLTxISR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCIE</name>
<description>Regular end of conversion interrupt enable
Please see the explanation of REOCF in DFSDM_FLTxISR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRIE</name>
<description>Injected data overrun interrupt enable
Please see the explanation of JOVRF in DFSDM_FLTxISR.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRIE</name>
<description>Regular data overrun interrupt enable
Please see the explanation of ROVRF in DFSDM_FLTxISR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt enable
Please see the explanation of AWDF in DFSDM_FLTxISR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDIE</name>
<description>Short-circuit detector interrupt enable
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>short-circuit detector interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>short-circuit detector interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABIE</name>
<description>Clock absence interrupt enable
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection of channel input clock absence interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection of channel input clock absence interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXCH</name>
<description>Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4ISR</name>
<displayName>DFSDM_FLT4ISR</displayName>
<addressOffset>0x308</addressOffset>
<size>0x20</size>
<resetValue>0x00FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCF</name>
<description>End of injected conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCF</name>
<description>End of regular conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRF</name>
<description>Injected conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRF</name>
<description>Regular conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDF</name>
<description>Analog watchdog
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No Analog watchdog event occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JCIP</name>
<description>Injected conversion in progress status
A request to start an injected conversion is ignored when JCIP=1.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the injected channel group (neither by software nor by trigger) has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCIP</name>
<description>Regular conversion in progress status
A request to start a regular conversion is ignored when RCIP=1.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the regular channel has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the regular channel is in progress or a request for a regular conversion is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABF</name>
<description>Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCDF</name>
<description>short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4ICR</name>
<displayName>DFSDM_FLT4ICR</displayName>
<addressOffset>0x30c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRJOVRF</name>
<description>Clear the injected conversion overrun flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRROVRF</name>
<description>Clear the regular conversion overrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCKABF</name>
<description>Clear the clock absence flag
CLRCKABF[y]=0: Writing '0’ has no effect
CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRSCDF</name>
<description>Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing '0’ has no effect
CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4JCHGR</name>
<displayName>DFSDM_FLT4JCHGR</displayName>
<addressOffset>0x310</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JCHG</name>
<description>Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4FCR</name>
<displayName>DFSDM_FLT4FCR</displayName>
<addressOffset>0x314</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IOSR</name>
<description>Integrator oversampling ratio (averaging length)
from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FOSR</name>
<description>Sinc filter oversampling ratio (decimation rate)
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FORD</name>
<description>Sinc filter order
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4JDATAR</name>
<displayName>DFSDM_FLT4JDATAR</displayName>
<addressOffset>0x318</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JDATACH</name>
<description>Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>JDATA</name>
<description>Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4RDATAR</name>
<displayName>DFSDM_FLT4RDATAR</displayName>
<addressOffset>0x31c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATACH</name>
<description>Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RPEND</name>
<description>Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDATA</name>
<description>Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4AWHTR</name>
<displayName>DFSDM_FLT4AWHTR</displayName>
<addressOffset>0x320</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWH</name>
<description>Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWHT</name>
<description>Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4AWLTR</name>
<displayName>DFSDM_FLT4AWLTR</displayName>
<addressOffset>0x324</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWL</name>
<description>Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWLT</name>
<description>Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4AWSR</name>
<displayName>DFSDM_FLT4AWSR</displayName>
<addressOffset>0x328</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AWLTF</name>
<description>Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AWHTF</name>
<description>Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4AWCFR</name>
<displayName>DFSDM_FLT4AWCFR</displayName>
<addressOffset>0x32c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRAWLTF</name>
<description>Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0’ has no effect
CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRAWHTF</name>
<description>Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0’ has no effect
CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4EXMAX</name>
<displayName>DFSDM_FLT4EXMAX</displayName>
<addressOffset>0x330</addressOffset>
<size>0x20</size>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMAXCH</name>
<description>Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMAX</name>
<description>Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
<readAction>set</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4EXMIN</name>
<displayName>DFSDM_FLT4EXMIN</displayName>
<addressOffset>0x334</addressOffset>
<size>0x20</size>
<resetValue>0x7FFFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMINCH</name>
<description>Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMIN</name>
<description>Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
<readAction>clear</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT4CNVTIMR</name>
<displayName>DFSDM_FLT4CNVTIMR</displayName>
<addressOffset>0x338</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNVCNT</name>
<description>28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.</description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5CR1</name>
<displayName>DFSDM_FLT5CR1</displayName>
<addressOffset>0x380</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFEN</name>
<description>DFSDM_FLTx enable
Data which are cleared by setting DFEN=0:
register DFSDM_FLTxISR is set to the reset state
register DFSDM_FLTxAWSR is set to the reset state</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start a conversion of the injected group of channels
This bit is always read as '0’.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSYNC</name>
<description>Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch an injected conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSCAN</name>
<description>Scanning conversion mode for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JDMAEN</name>
<description>DMA channel enabled to read data for the injected channel group
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read injected data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read injected data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>Trigger signal selection for launching injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).
DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to .
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JEXTEN</name>
<description>Trigger enable and trigger edge selection for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Trigger detection is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Each rising edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Each falling edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Both rising edges and falling edges on the selected trigger make requests to launch injected conversions</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSWSTART</name>
<description>Software start of a conversion on the regular channel
This bit is always read as '0’.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCONT</name>
<description>Continuous mode selection for regular conversions
Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regular channel is converted just once for each conversion request</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regular channel is converted repeatedly after each conversion request</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNC</name>
<description>Launch regular conversion synchronously with DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch a regular conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>DMA channel enabled to read data for the regular conversion
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read regular data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read regular data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCH</name>
<description>Regular channel selection
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel 0 is selected as the regular channel</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel 1 is selected as the regular channel</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST</name>
<description>Fast conversion mode selection for regular conversions
When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Fast conversion mode disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Fast conversion mode enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWFSEL</name>
<description>Analog watchdog fast mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog on channel transceivers value (after watchdog filter)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5CR2</name>
<displayName>DFSDM_FLT5CR2</displayName>
<addressOffset>0x384</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCIE</name>
<description>Injected end of conversion interrupt enable
Please see the explanation of JEOCF in DFSDM_FLTxISR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCIE</name>
<description>Regular end of conversion interrupt enable
Please see the explanation of REOCF in DFSDM_FLTxISR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRIE</name>
<description>Injected data overrun interrupt enable
Please see the explanation of JOVRF in DFSDM_FLTxISR.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRIE</name>
<description>Regular data overrun interrupt enable
Please see the explanation of ROVRF in DFSDM_FLTxISR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt enable
Please see the explanation of AWDF in DFSDM_FLTxISR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDIE</name>
<description>Short-circuit detector interrupt enable
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>short-circuit detector interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>short-circuit detector interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABIE</name>
<description>Clock absence interrupt enable
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection of channel input clock absence interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection of channel input clock absence interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXCH</name>
<description>Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5ISR</name>
<displayName>DFSDM_FLT5ISR</displayName>
<addressOffset>0x388</addressOffset>
<size>0x20</size>
<resetValue>0x00FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCF</name>
<description>End of injected conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCF</name>
<description>End of regular conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRF</name>
<description>Injected conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRF</name>
<description>Regular conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDF</name>
<description>Analog watchdog
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No Analog watchdog event occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JCIP</name>
<description>Injected conversion in progress status
A request to start an injected conversion is ignored when JCIP=1.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the injected channel group (neither by software nor by trigger) has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCIP</name>
<description>Regular conversion in progress status
A request to start a regular conversion is ignored when RCIP=1.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the regular channel has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the regular channel is in progress or a request for a regular conversion is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABF</name>
<description>Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCDF</name>
<description>short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5ICR</name>
<displayName>DFSDM_FLT5ICR</displayName>
<addressOffset>0x38c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRJOVRF</name>
<description>Clear the injected conversion overrun flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRROVRF</name>
<description>Clear the regular conversion overrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCKABF</name>
<description>Clear the clock absence flag
CLRCKABF[y]=0: Writing '0’ has no effect
CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRSCDF</name>
<description>Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing '0’ has no effect
CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5JCHGR</name>
<displayName>DFSDM_FLT5JCHGR</displayName>
<addressOffset>0x390</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JCHG</name>
<description>Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5FCR</name>
<displayName>DFSDM_FLT5FCR</displayName>
<addressOffset>0x394</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IOSR</name>
<description>Integrator oversampling ratio (averaging length)
from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FOSR</name>
<description>Sinc filter oversampling ratio (decimation rate)
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FORD</name>
<description>Sinc filter order
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5JDATAR</name>
<displayName>DFSDM_FLT5JDATAR</displayName>
<addressOffset>0x398</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JDATACH</name>
<description>Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>JDATA</name>
<description>Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5RDATAR</name>
<displayName>DFSDM_FLT5RDATAR</displayName>
<addressOffset>0x39c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATACH</name>
<description>Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RPEND</name>
<description>Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDATA</name>
<description>Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5AWHTR</name>
<displayName>DFSDM_FLT5AWHTR</displayName>
<addressOffset>0x3a0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWH</name>
<description>Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWHT</name>
<description>Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5AWLTR</name>
<displayName>DFSDM_FLT5AWLTR</displayName>
<addressOffset>0x3a4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWL</name>
<description>Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWLT</name>
<description>Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5AWSR</name>
<displayName>DFSDM_FLT5AWSR</displayName>
<addressOffset>0x3a8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AWLTF</name>
<description>Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AWHTF</name>
<description>Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5AWCFR</name>
<displayName>DFSDM_FLT5AWCFR</displayName>
<addressOffset>0x3ac</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRAWLTF</name>
<description>Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0’ has no effect
CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRAWHTF</name>
<description>Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0’ has no effect
CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5EXMAX</name>
<displayName>DFSDM_FLT5EXMAX</displayName>
<addressOffset>0x3b0</addressOffset>
<size>0x20</size>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMAXCH</name>
<description>Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMAX</name>
<description>Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
<readAction>set</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5EXMIN</name>
<displayName>DFSDM_FLT5EXMIN</displayName>
<addressOffset>0x3b4</addressOffset>
<size>0x20</size>
<resetValue>0x7FFFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMINCH</name>
<description>Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMIN</name>
<description>Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
<readAction>clear</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT5CNVTIMR</name>
<displayName>DFSDM_FLT5CNVTIMR</displayName>
<addressOffset>0x3b8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNVCNT</name>
<description>28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.</description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6CR1</name>
<displayName>DFSDM_FLT6CR1</displayName>
<addressOffset>0x400</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFEN</name>
<description>DFSDM_FLTx enable
Data which are cleared by setting DFEN=0:
register DFSDM_FLTxISR is set to the reset state
register DFSDM_FLTxAWSR is set to the reset state</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start a conversion of the injected group of channels
This bit is always read as '0’.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSYNC</name>
<description>Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch an injected conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSCAN</name>
<description>Scanning conversion mode for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JDMAEN</name>
<description>DMA channel enabled to read data for the injected channel group
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read injected data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read injected data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>Trigger signal selection for launching injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).
DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to .
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JEXTEN</name>
<description>Trigger enable and trigger edge selection for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Trigger detection is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Each rising edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Each falling edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Both rising edges and falling edges on the selected trigger make requests to launch injected conversions</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSWSTART</name>
<description>Software start of a conversion on the regular channel
This bit is always read as '0’.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCONT</name>
<description>Continuous mode selection for regular conversions
Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regular channel is converted just once for each conversion request</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regular channel is converted repeatedly after each conversion request</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNC</name>
<description>Launch regular conversion synchronously with DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch a regular conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>DMA channel enabled to read data for the regular conversion
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read regular data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read regular data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCH</name>
<description>Regular channel selection
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel 0 is selected as the regular channel</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel 1 is selected as the regular channel</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST</name>
<description>Fast conversion mode selection for regular conversions
When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Fast conversion mode disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Fast conversion mode enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWFSEL</name>
<description>Analog watchdog fast mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog on channel transceivers value (after watchdog filter)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6CR2</name>
<displayName>DFSDM_FLT6CR2</displayName>
<addressOffset>0x404</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCIE</name>
<description>Injected end of conversion interrupt enable
Please see the explanation of JEOCF in DFSDM_FLTxISR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCIE</name>
<description>Regular end of conversion interrupt enable
Please see the explanation of REOCF in DFSDM_FLTxISR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRIE</name>
<description>Injected data overrun interrupt enable
Please see the explanation of JOVRF in DFSDM_FLTxISR.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRIE</name>
<description>Regular data overrun interrupt enable
Please see the explanation of ROVRF in DFSDM_FLTxISR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt enable
Please see the explanation of AWDF in DFSDM_FLTxISR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDIE</name>
<description>Short-circuit detector interrupt enable
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>short-circuit detector interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>short-circuit detector interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABIE</name>
<description>Clock absence interrupt enable
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection of channel input clock absence interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection of channel input clock absence interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXCH</name>
<description>Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6ISR</name>
<displayName>DFSDM_FLT6ISR</displayName>
<addressOffset>0x408</addressOffset>
<size>0x20</size>
<resetValue>0x00FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCF</name>
<description>End of injected conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCF</name>
<description>End of regular conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRF</name>
<description>Injected conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRF</name>
<description>Regular conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDF</name>
<description>Analog watchdog
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No Analog watchdog event occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JCIP</name>
<description>Injected conversion in progress status
A request to start an injected conversion is ignored when JCIP=1.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the injected channel group (neither by software nor by trigger) has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCIP</name>
<description>Regular conversion in progress status
A request to start a regular conversion is ignored when RCIP=1.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the regular channel has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the regular channel is in progress or a request for a regular conversion is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABF</name>
<description>Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCDF</name>
<description>short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6ICR</name>
<displayName>DFSDM_FLT6ICR</displayName>
<addressOffset>0x40c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRJOVRF</name>
<description>Clear the injected conversion overrun flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRROVRF</name>
<description>Clear the regular conversion overrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCKABF</name>
<description>Clear the clock absence flag
CLRCKABF[y]=0: Writing '0’ has no effect
CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRSCDF</name>
<description>Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing '0’ has no effect
CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6JCHGR</name>
<displayName>DFSDM_FLT6JCHGR</displayName>
<addressOffset>0x410</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JCHG</name>
<description>Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6FCR</name>
<displayName>DFSDM_FLT6FCR</displayName>
<addressOffset>0x414</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IOSR</name>
<description>Integrator oversampling ratio (averaging length)
from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FOSR</name>
<description>Sinc filter oversampling ratio (decimation rate)
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FORD</name>
<description>Sinc filter order
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6JDATAR</name>
<displayName>DFSDM_FLT6JDATAR</displayName>
<addressOffset>0x418</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JDATACH</name>
<description>Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>JDATA</name>
<description>Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6RDATAR</name>
<displayName>DFSDM_FLT6RDATAR</displayName>
<addressOffset>0x41c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATACH</name>
<description>Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RPEND</name>
<description>Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDATA</name>
<description>Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6AWHTR</name>
<displayName>DFSDM_FLT6AWHTR</displayName>
<addressOffset>0x420</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWH</name>
<description>Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWHT</name>
<description>Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6AWLTR</name>
<displayName>DFSDM_FLT6AWLTR</displayName>
<addressOffset>0x424</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWL</name>
<description>Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWLT</name>
<description>Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6AWSR</name>
<displayName>DFSDM_FLT6AWSR</displayName>
<addressOffset>0x428</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AWLTF</name>
<description>Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AWHTF</name>
<description>Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6AWCFR</name>
<displayName>DFSDM_FLT6AWCFR</displayName>
<addressOffset>0x42c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRAWLTF</name>
<description>Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0’ has no effect
CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRAWHTF</name>
<description>Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0’ has no effect
CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6EXMAX</name>
<displayName>DFSDM_FLT6EXMAX</displayName>
<addressOffset>0x430</addressOffset>
<size>0x20</size>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMAXCH</name>
<description>Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMAX</name>
<description>Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
<readAction>set</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6EXMIN</name>
<displayName>DFSDM_FLT6EXMIN</displayName>
<addressOffset>0x434</addressOffset>
<size>0x20</size>
<resetValue>0x7FFFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMINCH</name>
<description>Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMIN</name>
<description>Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
<readAction>clear</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT6CNVTIMR</name>
<displayName>DFSDM_FLT6CNVTIMR</displayName>
<addressOffset>0x438</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNVCNT</name>
<description>28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.</description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7CR1</name>
<displayName>DFSDM_FLT7CR1</displayName>
<addressOffset>0x480</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFEN</name>
<description>DFSDM_FLTx enable
Data which are cleared by setting DFEN=0:
register DFSDM_FLTxISR is set to the reset state
register DFSDM_FLTxAWSR is set to the reset state</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start a conversion of the injected group of channels
This bit is always read as '0’.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become '1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1’ has no effect if JSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSYNC</name>
<description>Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch an injected conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSCAN</name>
<description>Scanning conversion mode for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>One channel conversion is performed from the injected channel group and next the selected channel from this group is selected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The series of conversions for the injected group channels is executed, starting over with the lowest selected channel.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JDMAEN</name>
<description>DMA channel enabled to read data for the injected channel group
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read injected data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read injected data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>Trigger signal selection for launching injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).
DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to .
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>JEXTEN</name>
<description>Trigger enable and trigger edge selection for injected conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Trigger detection is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Each rising edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Each falling edge on the selected trigger makes a request to launch an injected conversion</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Both rising edges and falling edges on the selected trigger make requests to launch injected conversions</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSWSTART</name>
<description>Software start of a conversion on the regular channel
This bit is always read as '0’.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ makes a request to start a conversion on the regular channel and causes RCIP to become '1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1’ has no effect if RSYNC=1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCONT</name>
<description>Continuous mode selection for regular conversions
Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The regular channel is converted just once for each conversion request</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The regular channel is converted repeatedly after each conversion request</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNC</name>
<description>Launch regular conversion synchronously with DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Do not launch a regular conversion synchronously with DFSDM_FLT0</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>DMA channel enabled to read data for the regular conversion
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The DMA channel is not enabled to read regular data</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The DMA channel is enabled to read regular data</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCH</name>
<description>Regular channel selection
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Channel 0 is selected as the regular channel</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Channel 1 is selected as the regular channel</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST</name>
<description>Fast conversion mode selection for regular conversions
When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Fast conversion mode disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Fast conversion mode enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWFSEL</name>
<description>Analog watchdog fast mode select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog on channel transceivers value (after watchdog filter)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7CR2</name>
<displayName>DFSDM_FLT7CR2</displayName>
<addressOffset>0x484</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCIE</name>
<description>Injected end of conversion interrupt enable
Please see the explanation of JEOCF in DFSDM_FLTxISR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCIE</name>
<description>Regular end of conversion interrupt enable
Please see the explanation of REOCF in DFSDM_FLTxISR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular end of conversion interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular end of conversion interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRIE</name>
<description>Injected data overrun interrupt enable
Please see the explanation of JOVRF in DFSDM_FLTxISR.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Injected data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Injected data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRIE</name>
<description>Regular data overrun interrupt enable
Please see the explanation of ROVRF in DFSDM_FLTxISR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Regular data overrun interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Regular data overrun interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt enable
Please see the explanation of AWDF in DFSDM_FLTxISR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Analog watchdog interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Analog watchdog interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCDIE</name>
<description>Short-circuit detector interrupt enable
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>short-circuit detector interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>short-circuit detector interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABIE</name>
<description>Clock absence interrupt enable
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Detection of channel input clock absence interrupt is disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Detection of channel input clock absence interrupt is enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXCH</name>
<description>Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7ISR</name>
<displayName>DFSDM_FLT7ISR</displayName>
<addressOffset>0x488</addressOffset>
<size>0x20</size>
<resetValue>0x00FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JEOCF</name>
<description>End of injected conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REOCF</name>
<description>End of regular conversion flag
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion has completed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion has completed and its data may be read</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JOVRF</name>
<description>Injected conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No injected conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1’. JDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROVRF</name>
<description>Regular conversion overrun flag
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No regular conversion overrun has occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1’. RDATAR is not affected by overruns</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AWDF</name>
<description>Analog watchdog
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No Analog watchdog event occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JCIP</name>
<description>Injected conversion in progress status
A request to start an injected conversion is ignored when JCIP=1.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the injected channel group (neither by software nor by trigger) has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1’ being written to JSWSTART or to a trigger detection</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RCIP</name>
<description>Regular conversion in progress status
A request to start a regular conversion is ignored when RCIP=1.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No request to convert the regular channel has been issued</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The conversion of the regular channel is in progress or a request for a regular conversion is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKABF</name>
<description>Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SCDF</name>
<description>short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7ICR</name>
<displayName>DFSDM_FLT7ICR</displayName>
<addressOffset>0x48c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRJOVRF</name>
<description>Clear the injected conversion overrun flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the JOVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRROVRF</name>
<description>Clear the regular conversion overrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Writing '0’ has no effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Writing '1’ clears the ROVRF bit in the DFSDM_FLTxISR register</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLRCKABF</name>
<description>Clear the clock absence flag
CLRCKABF[y]=0: Writing '0’ has no effect
CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRSCDF</name>
<description>Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing '0’ has no effect
CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7JCHGR</name>
<displayName>DFSDM_FLT7JCHGR</displayName>
<addressOffset>0x490</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JCHG</name>
<description>Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7FCR</name>
<displayName>DFSDM_FLT7FCR</displayName>
<addressOffset>0x494</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IOSR</name>
<description>Integrator oversampling ratio (averaging length)
from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FOSR</name>
<description>Sinc filter oversampling ratio (decimation rate)
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FORD</name>
<description>Sinc filter order
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FastSinc filter type</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Sinc1 filter type</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7JDATAR</name>
<displayName>DFSDM_FLT7JDATAR</displayName>
<addressOffset>0x498</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JDATACH</name>
<description>Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>JDATA</name>
<description>Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7RDATAR</name>
<displayName>DFSDM_FLT7RDATAR</displayName>
<addressOffset>0x49c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATACH</name>
<description>Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RPEND</name>
<description>Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDATA</name>
<description>Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7AWHTR</name>
<displayName>DFSDM_FLT7AWHTR</displayName>
<addressOffset>0x4a0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWH</name>
<description>Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWHT</name>
<description>Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7AWLTR</name>
<displayName>DFSDM_FLT7AWLTR</displayName>
<addressOffset>0x4a4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BKAWL</name>
<description>Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AWLT</name>
<description>Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7AWSR</name>
<displayName>DFSDM_FLT7AWSR</displayName>
<addressOffset>0x4a8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AWLTF</name>
<description>Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AWHTF</name>
<description>Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7AWCFR</name>
<displayName>DFSDM_FLT7AWCFR</displayName>
<addressOffset>0x4ac</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRAWLTF</name>
<description>Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0’ has no effect
CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLRAWHTF</name>
<description>Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0’ has no effect
CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7EXMAX</name>
<displayName>DFSDM_FLT7EXMAX</displayName>
<addressOffset>0x4b0</addressOffset>
<size>0x20</size>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMAXCH</name>
<description>Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMAX</name>
<description>Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
<readAction>set</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7EXMIN</name>
<displayName>DFSDM_FLT7EXMIN</displayName>
<addressOffset>0x4b4</addressOffset>
<size>0x20</size>
<resetValue>0x7FFFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EXMINCH</name>
<description>Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EXMIN</name>
<description>Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
<readAction>clear</readAction>
</field>
</fields>
</register>
<register>
<name>DFSDM_FLT7CNVTIMR</name>
<displayName>DFSDM_FLT7CNVTIMR</displayName>
<addressOffset>0x4b8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNVCNT</name>
<description>28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.</description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="DFSDM1">
<name>DFSDM2</name>
<baseAddress>0x58006C00</baseAddress>
</peripheral>
<peripheral>
<name>DMA1</name>
<description>DMA controller</description>
<groupName>DMA</groupName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA_STR0</name>
<description>DMA1 Stream0 global interrupt</description>
<value>11</value>
</interrupt>
<interrupt>
<name>DMA_STR1</name>
<description>DMA1 Stream1 global interrupt</description>
<value>12</value>
</interrupt>
<interrupt>
<name>DMA_STR2</name>
<description>DMA1 Stream2 global interrupt</description>
<value>13</value>
</interrupt>
<interrupt>
<name>DMA_STR3</name>
<description>DMA1 Stream3 global interrupt</description>
<value>14</value>
</interrupt>
<interrupt>
<name>DMA_STR4</name>
<description>DMA1 Stream4 global interrupt</description>
<value>15</value>
</interrupt>
<interrupt>
<name>DMA_STR5</name>
<description>DMA1 Stream5 global interrupt</description>
<value>16</value>
</interrupt>
<interrupt>
<name>DMA_STR6</name>
<description>DMA1 Stream6 global interrupt</description>
<value>17</value>
</interrupt>
<interrupt>
<name>DMA1_STR7</name>
<description>DMA1 Stream7 global interrupt</description>
<value>47</value>
</interrupt>
<registers>
<register>
<name>LISR</name>
<displayName>LISR</displayName>
<description>low interrupt status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TCIF3</name>
<description>Stream x transfer complete interrupt
flag (x = 3..0)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF3</name>
<description>Stream x half transfer interrupt flag
(x=3..0)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF3</name>
<description>Stream x transfer error interrupt flag
(x=3..0)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIF3</name>
<description>Stream x direct mode error interrupt
flag (x=3..0)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIF3</name>
<description>Stream x FIFO error interrupt flag
(x=3..0)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF2</name>
<description>Stream x transfer complete interrupt
flag (x = 3..0)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF2</name>
<description>Stream x half transfer interrupt flag
(x=3..0)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF2</name>
<description>Stream x transfer error interrupt flag
(x=3..0)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIF2</name>
<description>Stream x direct mode error interrupt
flag (x=3..0)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIF2</name>
<description>Stream x FIFO error interrupt flag
(x=3..0)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF1</name>
<description>Stream x transfer complete interrupt
flag (x = 3..0)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF1</name>
<description>Stream x half transfer interrupt flag
(x=3..0)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF1</name>
<description>Stream x transfer error interrupt flag
(x=3..0)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIF1</name>
<description>Stream x direct mode error interrupt
flag (x=3..0)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIF1</name>
<description>Stream x FIFO error interrupt flag
(x=3..0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF0</name>
<description>Stream x transfer complete interrupt
flag (x = 3..0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF0</name>
<description>Stream x half transfer interrupt flag
(x=3..0)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF0</name>
<description>Stream x transfer error interrupt flag
(x=3..0)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIF0</name>
<description>Stream x direct mode error interrupt
flag (x=3..0)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIF0</name>
<description>Stream x FIFO error interrupt flag
(x=3..0)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HISR</name>
<displayName>HISR</displayName>
<description>high interrupt status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TCIF7</name>
<description>Stream x transfer complete interrupt
flag (x=7..4)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF7</name>
<description>Stream x half transfer interrupt flag
(x=7..4)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF7</name>
<description>Stream x transfer error interrupt flag
(x=7..4)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIF7</name>
<description>Stream x direct mode error interrupt
flag (x=7..4)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIF7</name>
<description>Stream x FIFO error interrupt flag
(x=7..4)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF6</name>
<description>Stream x transfer complete interrupt
flag (x=7..4)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF6</name>
<description>Stream x half transfer interrupt flag
(x=7..4)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF6</name>
<description>Stream x transfer error interrupt flag
(x=7..4)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIF6</name>
<description>Stream x direct mode error interrupt
flag (x=7..4)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIF6</name>
<description>Stream x FIFO error interrupt flag
(x=7..4)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF5</name>
<description>Stream x transfer complete interrupt
flag (x=7..4)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF5</name>
<description>Stream x half transfer interrupt flag
(x=7..4)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF5</name>
<description>Stream x transfer error interrupt flag
(x=7..4)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIF5</name>
<description>Stream x direct mode error interrupt
flag (x=7..4)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIF5</name>
<description>Stream x FIFO error interrupt flag
(x=7..4)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF4</name>
<description>Stream x transfer complete interrupt
flag (x=7..4)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF4</name>
<description>Stream x half transfer interrupt flag
(x=7..4)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF4</name>
<description>Stream x transfer error interrupt flag
(x=7..4)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIF4</name>
<description>Stream x direct mode error interrupt
flag (x=7..4)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEIF4</name>
<description>Stream x FIFO error interrupt flag
(x=7..4)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LIFCR</name>
<displayName>LIFCR</displayName>
<description>low interrupt flag clear
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTCIF3</name>
<description>Stream x clear transfer complete
interrupt flag (x = 3..0)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF3</name>
<description>Stream x clear half transfer interrupt
flag (x = 3..0)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF3</name>
<description>Stream x clear transfer error interrupt
flag (x = 3..0)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDMEIF3</name>
<description>Stream x clear direct mode error
interrupt flag (x = 3..0)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFEIF3</name>
<description>Stream x clear FIFO error interrupt flag
(x = 3..0)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF2</name>
<description>Stream x clear transfer complete
interrupt flag (x = 3..0)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF2</name>
<description>Stream x clear half transfer interrupt
flag (x = 3..0)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF2</name>
<description>Stream x clear transfer error interrupt
flag (x = 3..0)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDMEIF2</name>
<description>Stream x clear direct mode error
interrupt flag (x = 3..0)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFEIF2</name>
<description>Stream x clear FIFO error interrupt flag
(x = 3..0)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF1</name>
<description>Stream x clear transfer complete
interrupt flag (x = 3..0)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF1</name>
<description>Stream x clear half transfer interrupt
flag (x = 3..0)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF1</name>
<description>Stream x clear transfer error interrupt
flag (x = 3..0)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDMEIF1</name>
<description>Stream x clear direct mode error
interrupt flag (x = 3..0)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFEIF1</name>
<description>Stream x clear FIFO error interrupt flag
(x = 3..0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF0</name>
<description>Stream x clear transfer complete
interrupt flag (x = 3..0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF0</name>
<description>Stream x clear half transfer interrupt
flag (x = 3..0)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF0</name>
<description>Stream x clear transfer error interrupt
flag (x = 3..0)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDMEIF0</name>
<description>Stream x clear direct mode error
interrupt flag (x = 3..0)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFEIF0</name>
<description>Stream x clear FIFO error interrupt flag
(x = 3..0)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HIFCR</name>
<displayName>HIFCR</displayName>
<description>high interrupt flag clear
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTCIF7</name>
<description>Stream x clear transfer complete
interrupt flag (x = 7..4)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF7</name>
<description>Stream x clear half transfer interrupt
flag (x = 7..4)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF7</name>
<description>Stream x clear transfer error interrupt
flag (x = 7..4)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDMEIF7</name>
<description>Stream x clear direct mode error
interrupt flag (x = 7..4)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFEIF7</name>
<description>Stream x clear FIFO error interrupt flag
(x = 7..4)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF6</name>
<description>Stream x clear transfer complete
interrupt flag (x = 7..4)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF6</name>
<description>Stream x clear half transfer interrupt
flag (x = 7..4)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF6</name>
<description>Stream x clear transfer error interrupt
flag (x = 7..4)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDMEIF6</name>
<description>Stream x clear direct mode error
interrupt flag (x = 7..4)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFEIF6</name>
<description>Stream x clear FIFO error interrupt flag
(x = 7..4)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF5</name>
<description>Stream x clear transfer complete
interrupt flag (x = 7..4)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF5</name>
<description>Stream x clear half transfer interrupt
flag (x = 7..4)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF5</name>
<description>Stream x clear transfer error interrupt
flag (x = 7..4)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDMEIF5</name>
<description>Stream x clear direct mode error
interrupt flag (x = 7..4)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFEIF5</name>
<description>Stream x clear FIFO error interrupt flag
(x = 7..4)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF4</name>
<description>Stream x clear transfer complete
interrupt flag (x = 7..4)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF4</name>
<description>Stream x clear half transfer interrupt
flag (x = 7..4)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF4</name>
<description>Stream x clear transfer error interrupt
flag (x = 7..4)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CDMEIF4</name>
<description>Stream x clear direct mode error
interrupt flag (x = 7..4)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFEIF4</name>
<description>Stream x clear FIFO error interrupt flag
(x = 7..4)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S0CR</name>
<displayName>S0CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S0NDTR</name>
<displayName>S0NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>S0PAR</name>
<displayName>S0PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S0M0AR</name>
<displayName>S0M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S0M1AR</name>
<displayName>S0M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S0FCR</name>
<displayName>S0FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>S1CR</name>
<displayName>S1CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S1NDTR</name>
<displayName>S1NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>S1PAR</name>
<displayName>S1PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S1M0AR</name>
<displayName>S1M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S1M1AR</name>
<displayName>S1M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S1FCR</name>
<displayName>S1FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>S2CR</name>
<displayName>S2CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S2NDTR</name>
<displayName>S2NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>S2PAR</name>
<displayName>S2PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S2M0AR</name>
<displayName>S2M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S2M1AR</name>
<displayName>S2M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S2FCR</name>
<displayName>S2FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>S3CR</name>
<displayName>S3CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S3NDTR</name>
<displayName>S3NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>S3PAR</name>
<displayName>S3PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S3M0AR</name>
<displayName>S3M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S3M1AR</name>
<displayName>S3M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S3FCR</name>
<displayName>S3FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>S4CR</name>
<displayName>S4CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S4NDTR</name>
<displayName>S4NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>S4PAR</name>
<displayName>S4PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S4M0AR</name>
<displayName>S4M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S4M1AR</name>
<displayName>S4M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S4FCR</name>
<displayName>S4FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>S5CR</name>
<displayName>S5CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S5NDTR</name>
<displayName>S5NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>S5PAR</name>
<displayName>S5PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S5M0AR</name>
<displayName>S5M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S5M1AR</name>
<displayName>S5M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S5FCR</name>
<displayName>S5FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>S6CR</name>
<displayName>S6CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S6NDTR</name>
<displayName>S6NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>S6PAR</name>
<displayName>S6PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S6M0AR</name>
<displayName>S6M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S6M1AR</name>
<displayName>S6M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S6FCR</name>
<displayName>S6FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>S7CR</name>
<displayName>S7CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>S7NDTR</name>
<displayName>S7NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>S7PAR</name>
<displayName>S7PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S7M0AR</name>
<displayName>S7M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S7M1AR</name>
<displayName>S7M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>S7FCR</name>
<displayName>S7FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="DMA1">
<name>DMA2</name>
<baseAddress>0x40020400</baseAddress>
<interrupt>
<name>ETH</name>
<description>Ethernet global interrupt</description>
<value>61</value>
</interrupt>
<interrupt>
<name>ETH_WKUP</name>
<description>Ethernet wakeup through EXTI</description>
<value>62</value>
</interrupt>
</peripheral>
<peripheral>
<name>DMA2D</name>
<description>DMA2D</description>
<groupName>DMA2D</groupName>
<baseAddress>0x52001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA2D</name>
<description>DMA2D global interrupt</description>
<value>90</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>DMA2D control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>START</name>
<description>Start This bit can be used to launch the
DMA2D according to the parameters loaded in the
various configuration registers</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUSP</name>
<description>Suspend This bit can be used to suspend
the current transfer. This bit is set and reset by
software. It is automatically reset by hardware when
the START bit is reset.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABORT</name>
<description>Abort This bit can be used to abort the
current transfer. This bit is set by software and is
automatically reset by hardware when the START bit is
reset.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TWIE</name>
<description>Transfer watermark interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAEIE</name>
<description>CLUT access error interrupt enable This
bit is set and cleared by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIE</name>
<description>CLUT transfer complete interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEIE</name>
<description>Configuration Error Interrupt Enable
This bit is set and cleared by
software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODE</name>
<description>DMA2D mode This bit is set and cleared
by software. It cannot be modified while a transfer
is ongoing.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>DMA2D Interrupt Status
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF</name>
<description>Transfer error interrupt flag This bit
is set when an error occurs during a DMA transfer
(data transfer or automatic CLUT
loading).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF</name>
<description>Transfer complete interrupt flag This
bit is set when a DMA2D transfer operation is
complete (data transfer only).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TWIF</name>
<description>Transfer watermark interrupt flag This
bit is set when the last pixel of the watermarked
line has been transferred.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAEIF</name>
<description>CLUT access error interrupt flag This
bit is set when the CPU accesses the CLUT while the
CLUT is being automatically copied from a system
memory to the internal DMA2D.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF</name>
<description>CLUT transfer complete interrupt flag
This bit is set when the CLUT copy from a system
memory area to the internal DMA2D memory is
complete.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEIF</name>
<description>Configuration error interrupt flag This
bit is set when the START bit of DMA2D_CR,
DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong
configuration has been programmed.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>DMA2D interrupt flag clear
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF</name>
<description>Clear Transfer error interrupt flag
Programming this bit to 1 clears the TEIF flag in the
DMA2D_ISR register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF</name>
<description>Clear transfer complete interrupt flag
Programming this bit to 1 clears the TCIF flag in the
DMA2D_ISR register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTWIF</name>
<description>Clear transfer watermark interrupt flag
Programming this bit to 1 clears the TWIF flag in the
DMA2D_ISR register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAECIF</name>
<description>Clear CLUT access error interrupt flag
Programming this bit to 1 clears the CAEIF flag in
the DMA2D_ISR register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF</name>
<description>Clear CLUT transfer complete interrupt
flag Programming this bit to 1 clears the CTCIF flag
in the DMA2D_ISR register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCEIF</name>
<description>Clear configuration error interrupt flag
Programming this bit to 1 clears the CEIF flag in the
DMA2D_ISR register</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGMAR</name>
<displayName>FGMAR</displayName>
<description>DMA2D foreground memory address
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Address of the data used
for the foreground image. This register can only be
written when data transfers are disabled. Once the
data transfer has started, this register is
read-only. The address alignment must match the image
format selected e.g. a 32-bit per pixel format must
be 32-bit aligned, a 16-bit per pixel format must be
16-bit aligned and a 4-bit per pixel format must be
8-bit aligned.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGOR</name>
<displayName>FGOR</displayName>
<description>DMA2D foreground offset
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LO</name>
<description>Line offset Line offset used for the
foreground expressed in pixel. This value is used to
generate the address. It is added at the end of each
line to determine the starting address of the next
line. These bits can only be written when data
transfers are disabled. Once a data transfer has
started, they become read-only. If the image format
is 4-bit per pixel, the line offset must be
even.</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGMAR</name>
<displayName>BGMAR</displayName>
<description>DMA2D background memory address
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Address of the data used
for the background image. This register can only be
written when data transfers are disabled. Once a data
transfer has started, this register is read-only. The
address alignment must match the image format
selected e.g. a 32-bit per pixel format must be
32-bit aligned, a 16-bit per pixel format must be
16-bit aligned and a 4-bit per pixel format must be
8-bit aligned.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGOR</name>
<displayName>BGOR</displayName>
<description>DMA2D background offset
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LO</name>
<description>Line offset Line offset used for the
background image (expressed in pixel). This value is
used for the address generation. It is added at the
end of each line to determine the starting address of
the next line. These bits can only be written when
data transfers are disabled. Once data transfer has
started, they become read-only. If the image format
is 4-bit per pixel, the line offset must be
even.</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGPFCCR</name>
<displayName>FGPFCCR</displayName>
<description>DMA2D foreground PFC control
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CM</name>
<description>Color mode These bits defines the color
format of the foreground image. They can only be
written when data transfers are disabled. Once the
transfer has started, they are read-only. others:
meaningless</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CCM</name>
<description>CLUT color mode This bit defines the
color format of the CLUT. It can only be written when
the transfer is disabled. Once the CLUT transfer has
started, this bit is read-only.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start This bit can be set to start the
automatic loading of the CLUT. It is automatically
reset: ** at the end of the transfer ** when the
transfer is aborted by the user application by
setting the ABORT bit in DMA2D_CR ** when a transfer
error occurs ** when the transfer has not started due
to a configuration error or another transfer
operation already ongoing (data transfer or automatic
background CLUT transfer).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS</name>
<description>CLUT size These bits define the size of
the CLUT used for the foreground image. Once the CLUT
transfer has started, this field is read-only. The
number of CLUT entries is equal to CS[7:0] +
1.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>AM</name>
<description>Alpha mode These bits select the alpha
channel value to be used for the foreground image.
They can only be written data the transfer are
disabled. Once the transfer has started, they become
read-only. other configurations are
meaningless</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Chroma Sub-Sampling These bits define
the chroma sub-sampling mode for YCbCr color mode.
Once the transfer has started, these bits are
read-only. others: meaningless</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AI</name>
<description>Alpha Inverted This bit inverts the
alpha value. Once the transfer has started, this bit
is read-only.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBS</name>
<description>Red Blue Swap This bit allows to swap
the R &amp;amp; B to support BGR or ABGR color
formats. Once the transfer has started, this bit is
read-only.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALPHA</name>
<description>Alpha value These bits define a fixed
alpha channel value which can replace the original
alpha value or be multiplied by the original alpha
value according to the alpha mode selected through
the AM[1:0] bits. These bits can only be written when
data transfers are disabled. Once a transfer has
started, they become read-only.</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGCOLR</name>
<displayName>FGCOLR</displayName>
<description>DMA2D foreground color
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLUE</name>
<description>Blue Value These bits defines the blue
value for the A4 or A8 mode of the foreground image.
They can only be written when data transfers are
disabled. Once the transfer has started, They are
read-only.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>Green Value These bits defines the green
value for the A4 or A8 mode of the foreground image.
They can only be written when data transfers are
disabled. Once the transfer has started, They are
read-only.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RED</name>
<description>Red Value These bits defines the red
value for the A4 or A8 mode of the foreground image.
They can only be written when data transfers are
disabled. Once the transfer has started, they are
read-only.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGPFCCR</name>
<displayName>BGPFCCR</displayName>
<description>DMA2D background PFC control
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CM</name>
<description>Color mode These bits define the color
format of the foreground image. These bits can only
be written when data transfers are disabled. Once the
transfer has started, they are read-only. others:
meaningless</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CCM</name>
<description>CLUT Color mode These bits define the
color format of the CLUT. This register can only be
written when the transfer is disabled. Once the CLUT
transfer has started, this bit is
read-only.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start This bit is set to start the
automatic loading of the CLUT. This bit is
automatically reset: ** at the end of the transfer **
when the transfer is aborted by the user application
by setting the ABORT bit in the DMA2D_CR ** when a
transfer error occurs ** when the transfer has not
started due to a configuration error or another
transfer operation already on going (data transfer or
automatic BackGround CLUT transfer).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS</name>
<description>CLUT size These bits define the size of
the CLUT used for the BG. Once the CLUT transfer has
started, this field is read-only. The number of CLUT
entries is equal to CS[7:0] + 1.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>AM</name>
<description>Alpha mode These bits define which alpha
channel value to be used for the background image.
These bits can only be written when data transfers
are disabled. Once the transfer has started, they are
read-only. others: meaningless</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AI</name>
<description>Alpha Inverted This bit inverts the
alpha value. Once the transfer has started, this bit
is read-only.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBS</name>
<description>Red Blue Swap This bit allows to swap
the R &amp;amp; B to support BGR or ABGR color
formats. Once the transfer has started, this bit is
read-only.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALPHA</name>
<description>Alpha value These bits define a fixed
alpha channel value which can replace the original
alpha value or be multiplied with the original alpha
value according to the alpha mode selected with bits
AM[1: 0]. These bits can only be written when data
transfers are disabled. Once the transfer has
started, they are read-only.</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGCOLR</name>
<displayName>BGCOLR</displayName>
<description>DMA2D background color
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLUE</name>
<description>Blue Value These bits define the blue
value for the A4 or A8 mode of the background. These
bits can only be written when data transfers are
disabled. Once the transfer has started, they are
read-only.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>Green Value These bits define the green
value for the A4 or A8 mode of the background. These
bits can only be written when data transfers are
disabled. Once the transfer has started, they are
read-only.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RED</name>
<description>Red Value These bits define the red
value for the A4 or A8 mode of the background. These
bits can only be written when data transfers are
disabled. Once the transfer has started, they are
read-only.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DFGCMAR</name>
<displayName>DFGCMAR</displayName>
<description>DMA2D foreground CLUT memory address
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory Address Address of the data used
for the CLUT address dedicated to the foreground
image. This register can only be written when no
transfer is ongoing. Once the CLUT transfer has
started, this register is read-only. If the
foreground CLUT format is 32-bit, the address must be
32-bit aligned.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGCMAR</name>
<displayName>BGCMAR</displayName>
<description>DMA2D background CLUT memory address
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address Address of the data used
for the CLUT address dedicated to the background
image. This register can only be written when no
transfer is on going. Once the CLUT transfer has
started, this register is read-only. If the
background CLUT format is 32-bit, the address must be
32-bit aligned.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPFCCR</name>
<displayName>OPFCCR</displayName>
<description>DMA2D output PFC control
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CM</name>
<description>Color mode These bits define the color
format of the output image. These bits can only be
written when data transfers are disabled. Once the
transfer has started, they are read-only. others:
meaningless</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AI</name>
<description>Alpha Inverted This bit inverts the
alpha value. Once the transfer has started, this bit
is read-only.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBS</name>
<description>Red Blue Swap This bit allows to swap
the R &amp;amp; B to support BGR or ABGR color
formats. Once the transfer has started, this bit is
read-only.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OCOLR</name>
<displayName>OCOLR</displayName>
<description>DMA2D output color register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLUE</name>
<description>Blue Value These bits define the blue
value of the output image. These bits can only be
written when data transfers are disabled. Once the
transfer has started, they are
read-only.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>Green Value These bits define the green
value of the output image. These bits can only be
written when data transfers are disabled. Once the
transfer has started, they are
read-only.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RED</name>
<description>Red Value These bits define the red
value of the output image. These bits can only be
written when data transfers are disabled. Once the
transfer has started, they are
read-only.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ALPHA</name>
<description>Alpha Channel Value These bits define
the alpha channel of the output color. These bits can
only be written when data transfers are disabled.
Once the transfer has started, they are
read-only.</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>OMAR</name>
<displayName>OMAR</displayName>
<description>DMA2D output memory address
register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory Address Address of the data used
for the output FIFO. These bits can only be written
when data transfers are disabled. Once the transfer
has started, they are read-only. The address
alignment must match the image format selected e.g. a
32-bit per pixel format must be 32-bit aligned and a
16-bit per pixel format must be 16-bit
aligned.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OOR</name>
<displayName>OOR</displayName>
<description>DMA2D output offset register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LO</name>
<description>Line Offset Line offset used for the
output (expressed in pixels). This value is used for
the address generation. It is added at the end of
each line to determine the starting address of the
next line. These bits can only be written when data
transfers are disabled. Once the transfer has
started, they are read-only.</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>NLR</name>
<displayName>NLR</displayName>
<description>DMA2D number of line register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NL</name>
<description>Number of lines Number of lines of the
area to be transferred. These bits can only be
written when data transfers are disabled. Once the
transfer has started, they are
read-only.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PL</name>
<description>Pixel per lines Number of pixels per
lines of the area to be transferred. These bits can
only be written when data transfers are disabled.
Once the transfer has started, they are read-only. If
any of the input image format is 4-bit per pixel,
pixel per lines must be even.</description>
<bitOffset>16</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>LWR</name>
<displayName>LWR</displayName>
<description>DMA2D line watermark register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LW</name>
<description>Line watermark These bits allow to
configure the line watermark for interrupt
generation. An interrupt is raised when the last
pixel of the watermarked line has been transferred.
These bits can only be written when data transfers
are disabled. Once the transfer has started, they are
read-only.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AMTCR</name>
<displayName>AMTCR</displayName>
<description>DMA2D AXI master timer configuration
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Enable Enables the dead time
functionality.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT</name>
<description>Dead Time Dead time value in the AXI
clock cycle inserted between two consecutive accesses
on the AXI master port. These bits represent the
minimum guaranteed number of cycles between two
consecutive AXI accesses.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX1</name>
<description>DMAMUX</description>
<groupName>DMAMUX</groupName>
<baseAddress>0x40020800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DMAMUX1_C0CR</name>
<displayName>DMAMUX1_C0CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C1CR</name>
<displayName>DMAMUX1_C1CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C2CR</name>
<displayName>DMAMUX1_C2CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C3CR</name>
<displayName>DMAMUX1_C3CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C4CR</name>
<displayName>DMAMUX1_C4CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C5CR</name>
<displayName>DMAMUX1_C5CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C6CR</name>
<displayName>DMAMUX1_C6CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C7CR</name>
<displayName>DMAMUX1_C7CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C8CR</name>
<displayName>DMAMUX1_C8CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C9CR</name>
<displayName>DMAMUX1_C9CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C10CR</name>
<displayName>DMAMUX1_C10CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C11CR</name>
<displayName>DMAMUX1_C11CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C12CR</name>
<displayName>DMAMUX1_C12CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C13CR</name>
<displayName>DMAMUX1_C13CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C14CR</name>
<displayName>DMAMUX1_C14CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_C15CR</name>
<displayName>DMAMUX1_C15CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RG0CR</name>
<displayName>DMAMUX1_RG0CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RG1CR</name>
<displayName>DMAMUX1_RG1CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RG2CR</name>
<displayName>DMAMUX1_RG2CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RG3CR</name>
<displayName>DMAMUX1_RG3CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RG4CR</name>
<displayName>DMAMUX1_RG4CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RG5CR</name>
<displayName>DMAMUX1_RG5CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RG6CR</name>
<displayName>DMAMUX1_RG6CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RG7CR</name>
<displayName>DMAMUX1_RG7CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RGSR</name>
<displayName>DMAMUX1_RGSR</displayName>
<description>DMAMux - DMA request generator status
register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OF</name>
<description>Trigger event overrun flag The flag is
set when a trigger event occurs on DMA request
generator channel x, while the DMA request generator
counter value is lower than GNBREQ. The flag is
cleared by writing 1 to the corresponding COFx bit in
DMAMUX_RGCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_RGCFR</name>
<displayName>DMAMUX1_RGCFR</displayName>
<description>DMAMux - DMA request generator clear flag
register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COF</name>
<description>Clear trigger event overrun flag Upon
setting, this bit clears the corresponding overrun
flag OFx in the DMAMUX_RGCSR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_CSR</name>
<displayName>DMAMUX1_CSR</displayName>
<description>DMAMUX request line multiplexer interrupt
channel status register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SOF</name>
<description>Synchronization overrun event
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMUX1_CFR</name>
<displayName>DMAMUX1_CFR</displayName>
<description>DMAMUX request line multiplexer interrupt
clear flag register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSOF</name>
<description>Clear synchronization overrun event
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX2</name>
<description>DMAMUX</description>
<groupName>DMAMUX</groupName>
<baseAddress>0x58025800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMAMUX2_OVR</name>
<description>DMAMUX2 overrun interrupt</description>
<value>128</value>
</interrupt>
<registers>
<register>
<name>C0CR</name>
<displayName>C0CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1CR</name>
<displayName>C1CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CR</name>
<displayName>C2CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3CR</name>
<displayName>C3CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4CR</name>
<displayName>C4CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5CR</name>
<displayName>C5CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6CR</name>
<displayName>C6CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7CR</name>
<displayName>C7CR</displayName>
<description>DMAMux - DMA request line multiplexer
channel x control register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>Input DMA request line
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Interrupt enable at synchronization
event overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event generation
enable/disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronous operating mode
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Synchronization event type selector
Defines the synchronization event on the selected
synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests to forward
Defines the number of DMA requests forwarded before
output event is generated. In synchronous mode, it
also defines the number of DMA requests to forward
after a synchronization event, then stop forwarding.
The actual number of DMA requests forwarded is
NBREQ+1. Note: This field can only be written when
both SE and EGE bits are reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization input
selected</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG0CR</name>
<displayName>RG0CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG1CR</name>
<displayName>RG1CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG2CR</name>
<displayName>RG2CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG3CR</name>
<displayName>RG3CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG4CR</name>
<displayName>RG4CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG5CR</name>
<displayName>RG5CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG6CR</name>
<displayName>RG6CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG7CR</name>
<displayName>RG7CR</displayName>
<description>DMAMux - DMA request generator channel x
control register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_ID</name>
<description>DMA request trigger input
selected</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Interrupt enable at trigger event
overrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GE</name>
<description>DMA request generator channel
enable/disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>DMA request generator trigger event type
selection Defines the trigger event on the selected
DMA request trigger input</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GNBREQ</name>
<description>Number of DMA requests to generate
Defines the number of DMA requests generated after a
trigger event, then stop generating. The actual
number of generated DMA requests is GNBREQ+1. Note:
This field can only be written when GE bit is
reset.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RGSR</name>
<displayName>RGSR</displayName>
<description>DMAMux - DMA request generator status
register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OF</name>
<description>Trigger event overrun flag The flag is
set when a trigger event occurs on DMA request
generator channel x, while the DMA request generator
counter value is lower than GNBREQ. The flag is
cleared by writing 1 to the corresponding COFx bit in
DMAMUX_RGCFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RGCFR</name>
<displayName>RGCFR</displayName>
<description>DMAMux - DMA request generator clear flag
register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COF</name>
<description>Clear trigger event overrun flag Upon
setting, this bit clears the corresponding overrun
flag OFx in the DMAMUX_RGCSR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>DMAMUX request line multiplexer interrupt
channel status register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SOF</name>
<description>Synchronization overrun event
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFR</name>
<displayName>CFR</displayName>
<description>DMAMUX request line multiplexer interrupt
clear flag register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSOF</name>
<description>Clear synchronization overrun event
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="DELAY_Block_SDMMC1">
<name>Delay_Block_OCTOSPI1</name>
<baseAddress>0x52006000</baseAddress>
</peripheral>
<peripheral derivedFrom="DELAY_Block_SDMMC1">
<name>Delay_Block_OCTOSPI2</name>
<baseAddress>0x5200B000</baseAddress>
</peripheral>
<peripheral>
<name>EXTI</name>
<description>External interrupt/event
controller</description>
<groupName>EXTI</groupName>
<baseAddress>0x58000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>EXTI0</name>
<description>EXTI Line 0 interrupt</description>
<value>6</value>
</interrupt>
<interrupt>
<name>EXTI1</name>
<description>EXTI Line 1 interrupt</description>
<value>7</value>
</interrupt>
<interrupt>
<name>EXTI2</name>
<description>EXTI Line 2 interrupt</description>
<value>8</value>
</interrupt>
<interrupt>
<name>EXTI3</name>
<description>EXTI Line 3interrupt</description>
<value>9</value>
</interrupt>
<interrupt>
<name>EXTI4</name>
<description>EXTI Line 4interrupt</description>
<value>10</value>
</interrupt>
<interrupt>
<name>EXTI9_5</name>
<description>EXTI Line[9:5] interrupts</description>
<value>23</value>
</interrupt>
<interrupt>
<name>EXTI15_10</name>
<description>EXTI Line[15:10] interrupts</description>
<value>40</value>
</interrupt>
<registers>
<register>
<name>RTSR1</name>
<displayName>RTSR1</displayName>
<description>EXTI rising trigger selection
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TR0</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR1</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR2</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR3</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR4</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR5</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR6</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR7</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR8</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR9</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR10</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR11</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR12</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR13</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR14</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR15</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR16</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR17</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR18</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR19</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR20</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR21</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FTSR1</name>
<displayName>FTSR1</displayName>
<description>EXTI falling trigger selection
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TR0</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR1</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR2</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR3</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR4</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR5</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR6</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR7</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR8</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR9</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR10</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR11</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR12</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR13</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR14</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR15</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR16</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR17</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR18</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR19</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR20</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR21</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWIER1</name>
<displayName>SWIER1</displayName>
<description>EXTI software interrupt event
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWIER0</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER1</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER2</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER3</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER4</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER5</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER6</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER7</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER8</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER9</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER10</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER11</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER12</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER13</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER14</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER15</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER16</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER17</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER18</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER19</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER20</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER21</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>D3PMR1</name>
<displayName>D3PMR1</displayName>
<description>EXTI D3 pending mask register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR0</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR1</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR2</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR3</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR4</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR5</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR6</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR7</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR8</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR9</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR10</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR11</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR12</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR13</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR14</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR15</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR19</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR20</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR21</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR25</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>D3PCR1L</name>
<displayName>D3PCR1L</displayName>
<description>EXTI D3 pending clear selection register
low</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCS0</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS1</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS2</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS3</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS4</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS5</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS6</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS7</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS8</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS9</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS10</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS11</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS12</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS13</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS14</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS15</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
(n/2)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>D3PCR1H</name>
<displayName>D3PCR1H</displayName>
<description>EXTI D3 pending clear selection register
high</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCS19</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
((n+32)/2)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS20</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
((n+32)/2)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS21</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
((n+32)/2)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS25</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
((n+32)/2)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTSR2</name>
<displayName>RTSR2</displayName>
<description>EXTI rising trigger selection
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TR49</name>
<description>Rising trigger event configuration bit
of Configurable Event input x+32</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR51</name>
<description>Rising trigger event configuration bit
of Configurable Event input x+32</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FTSR2</name>
<displayName>FTSR2</displayName>
<description>EXTI falling trigger selection
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TR49</name>
<description>Falling trigger event configuration bit
of Configurable Event input x+32</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR51</name>
<description>Falling trigger event configuration bit
of Configurable Event input x+32</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWIER2</name>
<displayName>SWIER2</displayName>
<description>EXTI software interrupt event
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWIER49</name>
<description>Software interrupt on line
x+32</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER51</name>
<description>Software interrupt on line
x+32</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>D3PMR2</name>
<displayName>D3PMR2</displayName>
<description>EXTI D3 pending mask register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR34</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR35</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR41</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR48</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR49</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR50</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR51</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR52</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR53</name>
<description>D3 Pending Mask on Event input
x+32</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>D3PCR2L</name>
<displayName>D3PCR2L</displayName>
<description>EXTI D3 pending clear selection register
low</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCS35</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
((n+64)/2)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS34</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
((n+64)/2)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS41</name>
<description>D3 Pending request clear input signal
selection on Event input x = truncate
((n+64)/2)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>D3PCR2H</name>
<displayName>D3PCR2H</displayName>
<description>EXTI D3 pending clear selection register
high</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCS48</name>
<description>Pending request clear input signal
selection on Event input x= truncate
((n+96)/2)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS49</name>
<description>Pending request clear input signal
selection on Event input x= truncate
((n+96)/2)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS50</name>
<description>Pending request clear input signal
selection on Event input x= truncate
((n+96)/2)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS51</name>
<description>Pending request clear input signal
selection on Event input x= truncate
((n+96)/2)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS52</name>
<description>Pending request clear input signal
selection on Event input x= truncate
((n+96)/2)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCS53</name>
<description>Pending request clear input signal
selection on Event input x= truncate
((n+96)/2)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTSR3</name>
<displayName>RTSR3</displayName>
<description>EXTI rising trigger selection
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TR82</name>
<description>Rising trigger event configuration bit
of Configurable Event input x+64</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR84</name>
<description>Rising trigger event configuration bit
of Configurable Event input x+64</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR85</name>
<description>Rising trigger event configuration bit
of Configurable Event input x+64</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR86</name>
<description>Rising trigger event configuration bit
of Configurable Event input x+64</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FTSR3</name>
<displayName>FTSR3</displayName>
<description>EXTI falling trigger selection
register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TR82</name>
<description>Falling trigger event configuration bit
of Configurable Event input x+64</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR84</name>
<description>Falling trigger event configuration bit
of Configurable Event input x+64</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR85</name>
<description>Falling trigger event configuration bit
of Configurable Event input x+64</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TR86</name>
<description>Falling trigger event configuration bit
of Configurable Event input x+64</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWIER3</name>
<displayName>SWIER3</displayName>
<description>EXTI software interrupt event
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWIER82</name>
<description>Software interrupt on line
x+64</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER84</name>
<description>Software interrupt on line
x+64</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER85</name>
<description>Software interrupt on line
x+64</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWIER86</name>
<description>Software interrupt on line
x+64</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>D3PMR3</name>
<displayName>D3PMR3</displayName>
<description>EXTI D3 pending mask register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR88</name>
<description>D3 Pending Mask on Event input
x+64</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>D3PCR3H</name>
<displayName>D3PCR3H</displayName>
<description>EXTI D3 pending clear selection register
high</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCS88</name>
<description>D3 Pending request clear input signal
selection on Event input x= truncate
N+160/2</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUIMR1</name>
<displayName>CPUIMR1</displayName>
<description>EXTI interrupt mask register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFC00000</resetValue>
<fields>
<field>
<name>MR0</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR1</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR2</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR3</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR4</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR5</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR6</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR7</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR8</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR9</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR10</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR11</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR12</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR13</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR14</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR15</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR16</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR17</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR18</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR19</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR20</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR21</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR22</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR23</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR24</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR25</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR26</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR27</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR28</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR29</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR30</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR31</name>
<description>Rising trigger event configuration bit
of Configurable Event input</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUEMR1</name>
<displayName>CPUEMR1</displayName>
<description>EXTI event mask register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR0</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR1</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR2</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR3</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR4</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR5</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR6</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR7</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR8</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR9</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR10</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR11</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR12</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR13</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR14</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR15</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR16</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR17</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR18</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR19</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR20</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR21</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR22</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR23</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR24</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR25</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR26</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR27</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR28</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR29</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR30</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR31</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUPR1</name>
<displayName>CPUPR1</displayName>
<description>EXTI pending register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR0</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR1</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR2</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR3</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR4</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR5</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR6</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR7</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR8</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR9</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR10</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR11</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR12</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR13</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR14</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR15</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR16</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR17</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR18</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR19</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR20</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR21</name>
<description>CPU Event mask on Event input
x</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUIMR2</name>
<displayName>CPUIMR2</displayName>
<description>EXTI interrupt mask register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR0</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR1</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR2</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR3</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR4</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR5</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR6</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR7</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR8</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR9</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR10</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR11</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR12</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR14</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR15</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR16</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR17</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR18</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR19</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR20</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR21</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR22</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR23</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR24</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR25</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR26</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR27</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR28</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR29</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR30</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR31</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUEMR2</name>
<displayName>CPUEMR2</displayName>
<description>EXTI event mask register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR32</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR33</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR34</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR35</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR36</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR37</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR38</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR39</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR40</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR41</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR42</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR43</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR44</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR46</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR47</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR48</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR49</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR50</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR51</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR52</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR53</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR54</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR55</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR56</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR57</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR58</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR59</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR60</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR61</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR62</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR63</name>
<description>CPU Interrupt Mask on Direct Event input
x+32</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUPR2</name>
<displayName>CPUPR2</displayName>
<description>EXTI pending register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR49</name>
<description>Configurable event inputs x+32 Pending
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR51</name>
<description>Configurable event inputs x+32 Pending
bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUIMR3</name>
<displayName>CPUIMR3</displayName>
<description>EXTI interrupt mask register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR64</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR65</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR66</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR67</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR68</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR69</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR70</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR71</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR72</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR73</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR74</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR75</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR76</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR77</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR78</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR79</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR80</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR82</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR84</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR85</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR86</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR87</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR88</name>
<description>CPU Interrupt Mask on Direct Event input
x+64</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUEMR3</name>
<displayName>CPUEMR3</displayName>
<description>EXTI event mask register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR64</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR65</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR66</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR67</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR68</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR69</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR70</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR71</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR72</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR73</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR74</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR75</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR76</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR77</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR78</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR79</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR80</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR82</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR84</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR85</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR86</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR87</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MR88</name>
<description>CPU Event mask on Event input
x+64</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUPR3</name>
<displayName>CPUPR3</displayName>
<description>EXTI pending register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR82</name>
<description>Configurable event inputs x+64 Pending
bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR84</name>
<description>Configurable event inputs x+64 Pending
bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR85</name>
<description>Configurable event inputs x+64 Pending
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PR86</name>
<description>Configurable event inputs x+64 Pending
bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FDCAN</name>
<description>FDCAN1</description>
<groupName>FDCAN</groupName>
<baseAddress>0x4000A400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FDCAN1_IT0</name>
<description>TTCAN Interrupt 0</description>
<value>19</value>
</interrupt>
<interrupt>
<name>FDCAN2_IT0</name>
<description>FDCAN Interrupt 0</description>
<value>20</value>
</interrupt>
<interrupt>
<name>FDCAN1_IT1</name>
<description>TTCAN Interrupt 1</description>
<value>21</value>
</interrupt>
<interrupt>
<name>FDCAN2_IT1</name>
<description>FDCAN Interrupt 1</description>
<value>22</value>
</interrupt>
<registers>
<register>
<name>FDCAN_CREL</name>
<displayName>FDCAN_CREL</displayName>
<description>FDCAN Core Release Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x32141218</resetValue>
<fields>
<field>
<name>REL</name>
<description>Core release</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STEP</name>
<description>Step of Core release</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SUBSTEP</name>
<description>Sub-step of Core release</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>YEAR</name>
<description>Timestamp Year</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MON</name>
<description>Timestamp Month</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DAY</name>
<description>Timestamp Day</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ENDN</name>
<displayName>FDCAN_ENDN</displayName>
<description>FDCAN Core Release Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x87654321</resetValue>
<fields>
<field>
<name>ETV</name>
<description>Endiannes Test Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_DBTP</name>
<displayName>FDCAN_DBTP</displayName>
<description>FDCAN Data Bit Timing and Prescaler
Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000A33</resetValue>
<fields>
<field>
<name>DSJW</name>
<description>Synchronization Jump Width</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTSEG2</name>
<description>Data time segment after sample
point</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTSEG1</name>
<description>Data time segment after sample
point</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBRP</name>
<description>Data BIt Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TDC</name>
<description>Transceiver Delay
Compensation</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TEST</name>
<displayName>FDCAN_TEST</displayName>
<description>FDCAN Test Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LBCK</name>
<description>Loop Back mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX</name>
<description>Loop Back mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX</name>
<description>Control of Transmit Pin</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RWD</name>
<displayName>FDCAN_RWD</displayName>
<description>FDCAN RAM Watchdog Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDV</name>
<description>Watchdog value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WDC</name>
<description>Watchdog configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_CCCR</name>
<displayName>FDCAN_CCCR</displayName>
<description>FDCAN CC Control Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>INIT</name>
<description>Initialization</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCE</name>
<description>Configuration Change
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASM</name>
<description>ASM Restricted Operation
Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSA</name>
<description>Clock Stop Acknowledge</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSR</name>
<description>Clock Stop Request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MON</name>
<description>Bus Monitoring Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAR</name>
<description>Disable Automatic
Retransmission</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEST</name>
<description>Test Mode Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDOE</name>
<description>FD Operation Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>FDCAN Bit Rate Switching</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXHD</name>
<description>Protocol Exception Handling
Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EFBI</name>
<description>Edge Filtering during Bus
Integration</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXP</name>
<description>TXP</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NISO</name>
<description>Non ISO Operation</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NBTP</name>
<displayName>FDCAN_NBTP</displayName>
<description>FDCAN Nominal Bit Timing and Prescaler
Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000A33</resetValue>
<fields>
<field>
<name>NSJW</name>
<description>NSJW: Nominal (Re)Synchronization Jump
Width</description>
<bitOffset>25</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>NBRP</name>
<description>Bit Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>NTSEG1</name>
<description>Nominal Time segment before sample
point</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TSEG2</name>
<description>Nominal Time segment after sample
point</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TSCC</name>
<displayName>FDCAN_TSCC</displayName>
<description>FDCAN Timestamp Counter Configuration
Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TCP</name>
<description>Timestamp Counter
Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TSS</name>
<description>Timestamp Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TSCV</name>
<displayName>FDCAN_TSCV</displayName>
<description>FDCAN Timestamp Counter Value
Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSC</name>
<description>Timestamp Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TOCC</name>
<displayName>FDCAN_TOCC</displayName>
<description>FDCAN Timeout Counter Configuration
Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFF0000</resetValue>
<fields>
<field>
<name>ETOC</name>
<description>Enable Timeout Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOS</name>
<description>Timeout Select</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TOP</name>
<description>Timeout Period</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TOCV</name>
<displayName>FDCAN_TOCV</displayName>
<description>FDCAN Timeout Counter Value
Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>TOC</name>
<description>Timeout Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ECR</name>
<displayName>FDCAN_ECR</displayName>
<description>FDCAN Error Counter Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEL</name>
<description>AN Error Logging</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RP</name>
<description>Receive Error Passive</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TREC</name>
<description>Receive Error Counter</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TEC</name>
<description>Transmit Error Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_PSR</name>
<displayName>FDCAN_PSR</displayName>
<description>FDCAN Protocol Status Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000707</resetValue>
<fields>
<field>
<name>LEC</name>
<description>Last Error Code</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ACT</name>
<description>Activity</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EP</name>
<description>Error Passive</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>Warning Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>Bus_Off Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLEC</name>
<description>Data Last Error Code</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RESI</name>
<description>ESI flag of last received FDCAN
Message</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBRS</name>
<description>BRS flag of last received FDCAN
Message</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REDL</name>
<description>Received FDCAN Message</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXE</name>
<description>Protocol Exception Event</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCV</name>
<description>Transmitter Delay Compensation
Value</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TDCR</name>
<displayName>FDCAN_TDCR</displayName>
<description>FDCAN Transmitter Delay Compensation
Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDCF</name>
<description>Transmitter Delay Compensation Filter
Window Length</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TDCO</name>
<description>Transmitter Delay Compensation
Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_IR</name>
<displayName>FDCAN_IR</displayName>
<description>FDCAN Interrupt Register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0N</name>
<description>Rx FIFO 0 New Message</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0W</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0F</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>Rx FIFO 0 Message Lost</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1N</name>
<description>Rx FIFO 1 New Message</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1W</name>
<description>Rx FIFO 1 Watermark
Reached</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1F</name>
<description>Rx FIFO 1 Watermark
Reached</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>Rx FIFO 1 Message Lost</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPM</name>
<description>High Priority Message</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>Transmission Completed</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCF</name>
<description>Transmission Cancellation
Finished</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEF</name>
<description>Tx FIFO Empty</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFN</name>
<description>Tx Event FIFO New Entry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFW</name>
<description>Tx Event FIFO Watermark
Reached</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFF</name>
<description>Tx Event FIFO Full</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx Event FIFO Element Lost</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSW</name>
<description>Timestamp Wraparound</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAF</name>
<description>Message RAM Access Failure</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOO</name>
<description>Timeout Occurred</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRX</name>
<description>Message stored to Dedicated Rx
Buffer</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELO</name>
<description>Error Logging Overflow</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP</name>
<description>Error Passive</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>Warning Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>Bus_Off Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDI</name>
<description>Watchdog Interrupt</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEA</name>
<description>Protocol Error in Arbitration Phase
(Nominal Bit Time is used)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PED</name>
<description>Protocol Error in Data Phase (Data Bit
Time is used)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARA</name>
<description>Access to Reserved Address</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_IE</name>
<displayName>FDCAN_IE</displayName>
<description>FDCAN Interrupt Enable
Register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0NE</name>
<description>Rx FIFO 0 New Message
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0WE</name>
<description>Rx FIFO 0 Full Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FE</name>
<description>Rx FIFO 0 Full Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LE</name>
<description>Rx FIFO 0 Message Lost
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NE</name>
<description>Rx FIFO 1 New Message
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1WE</name>
<description>Rx FIFO 1 Watermark Reached
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FE</name>
<description>Rx FIFO 1 Watermark Reached
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LE</name>
<description>Rx FIFO 1 Message Lost
Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPME</name>
<description>High Priority Message
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCE</name>
<description>Transmission Completed
Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFE</name>
<description>Transmission Cancellation Finished
Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFE</name>
<description>Tx FIFO Empty Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNE</name>
<description>Tx Event FIFO New Entry
Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFWE</name>
<description>Tx Event FIFO Watermark Reached
Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFE</name>
<description>Tx Event FIFO Full Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLE</name>
<description>Tx Event FIFO Element Lost
Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWE</name>
<description>Timestamp Wraparound
Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFE</name>
<description>Message RAM Access Failure
Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOE</name>
<description>Timeout Occurred Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRXE</name>
<description>Message stored to Dedicated Rx Buffer
Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BECE</name>
<description>Bit Error Corrected Interrupt
Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BEUE</name>
<description>Bit Error Uncorrected Interrupt
Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOE</name>
<description>Error Logging Overflow
Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPE</name>
<description>Error Passive Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWE</name>
<description>Warning Status Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOE</name>
<description>Bus_Off Status Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIE</name>
<description>Watchdog Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAE</name>
<description>Protocol Error in Arbitration Phase
Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDE</name>
<description>Protocol Error in Data Phase
Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAE</name>
<description>Access to Reserved Address
Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ILS</name>
<displayName>FDCAN_ILS</displayName>
<description>FDCAN Interrupt Line Select
Register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0NL</name>
<description>Rx FIFO 0 New Message Interrupt
Line</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0WL</name>
<description>Rx FIFO 0 Watermark Reached Interrupt
Line</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FL</name>
<description>Rx FIFO 0 Full Interrupt
Line</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LL</name>
<description>Rx FIFO 0 Message Lost Interrupt
Line</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NL</name>
<description>Rx FIFO 1 New Message Interrupt
Line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1WL</name>
<description>Rx FIFO 1 Watermark Reached Interrupt
Line</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FL</name>
<description>Rx FIFO 1 Full Interrupt
Line</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LL</name>
<description>Rx FIFO 1 Message Lost Interrupt
Line</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPML</name>
<description>High Priority Message Interrupt
Line</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCL</name>
<description>Transmission Completed Interrupt
Line</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFL</name>
<description>Transmission Cancellation Finished
Interrupt Line</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx FIFO Empty Interrupt
Line</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNL</name>
<description>Tx Event FIFO New Entry Interrupt
Line</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFWL</name>
<description>Tx Event FIFO Watermark Reached
Interrupt Line</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFL</name>
<description>Tx Event FIFO Full Interrupt
Line</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLL</name>
<description>Tx Event FIFO Element Lost Interrupt
Line</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWL</name>
<description>Timestamp Wraparound Interrupt
Line</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFL</name>
<description>Message RAM Access Failure Interrupt
Line</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOL</name>
<description>Timeout Occurred Interrupt
Line</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRXL</name>
<description>Message stored to Dedicated Rx Buffer
Interrupt Line</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BECL</name>
<description>Bit Error Corrected Interrupt
Line</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BEUL</name>
<description>Bit Error Uncorrected Interrupt
Line</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOL</name>
<description>Error Logging Overflow Interrupt
Line</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPL</name>
<description>Error Passive Interrupt
Line</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWL</name>
<description>Warning Status Interrupt
Line</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOL</name>
<description>Bus_Off Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIL</name>
<description>Watchdog Interrupt Line</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAL</name>
<description>Protocol Error in Arbitration Phase
Line</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDL</name>
<description>Protocol Error in Data Phase
Line</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAL</name>
<description>Access to Reserved Address
Line</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ILE</name>
<displayName>FDCAN_ILE</displayName>
<description>FDCAN Interrupt Line Enable
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EINT0</name>
<description>Enable Interrupt Line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EINT1</name>
<description>Enable Interrupt Line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_GFC</name>
<displayName>FDCAN_GFC</displayName>
<description>FDCAN Global Filter Configuration
Register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RRFE</name>
<description>Reject Remote Frames
Extended</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RRFS</name>
<description>Reject Remote Frames
Standard</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ANFE</name>
<description>Accept Non-matching Frames
Extended</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ANFS</name>
<description>Accept Non-matching Frames
Standard</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_SIDFC</name>
<displayName>FDCAN_SIDFC</displayName>
<description>FDCAN Standard ID Filter Configuration
Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLSSA</name>
<description>Filter List Standard Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>LSS</name>
<description>List Size Standard</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_XIDFC</name>
<displayName>FDCAN_XIDFC</displayName>
<description>FDCAN Extended ID Filter Configuration
Register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLESA</name>
<description>Filter List Standard Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>LSE</name>
<description>List Size Extended</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_XIDAM</name>
<displayName>FDCAN_XIDAM</displayName>
<description>FDCAN Extended ID and Mask
Register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EIDM</name>
<description>Extended ID Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_HPMS</name>
<displayName>FDCAN_HPMS</displayName>
<description>FDCAN High Priority Message Status
Register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BIDX</name>
<description>Buffer Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MSI</name>
<description>Message Storage Indicator</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FIDX</name>
<description>Filter Index</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FLST</name>
<description>Filter List</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NDAT1</name>
<displayName>FDCAN_NDAT1</displayName>
<description>FDCAN New Data 1 Register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ND0</name>
<description>New data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND1</name>
<description>New data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND2</name>
<description>New data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND3</name>
<description>New data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND4</name>
<description>New data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND5</name>
<description>New data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND6</name>
<description>New data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND7</name>
<description>New data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND8</name>
<description>New data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND9</name>
<description>New data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND10</name>
<description>New data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND11</name>
<description>New data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND12</name>
<description>New data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND13</name>
<description>New data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND14</name>
<description>New data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND15</name>
<description>New data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND16</name>
<description>New data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND17</name>
<description>New data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND18</name>
<description>New data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND19</name>
<description>New data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND20</name>
<description>New data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND21</name>
<description>New data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND22</name>
<description>New data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND23</name>
<description>New data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND24</name>
<description>New data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND25</name>
<description>New data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND26</name>
<description>New data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND27</name>
<description>New data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND28</name>
<description>New data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND29</name>
<description>New data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND30</name>
<description>New data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND31</name>
<description>New data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NDAT2</name>
<displayName>FDCAN_NDAT2</displayName>
<description>FDCAN New Data 2 Register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ND32</name>
<description>New data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND33</name>
<description>New data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND34</name>
<description>New data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND35</name>
<description>New data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND36</name>
<description>New data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND37</name>
<description>New data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND38</name>
<description>New data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND39</name>
<description>New data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND40</name>
<description>New data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND41</name>
<description>New data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND42</name>
<description>New data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND43</name>
<description>New data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND44</name>
<description>New data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND45</name>
<description>New data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND46</name>
<description>New data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND47</name>
<description>New data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND48</name>
<description>New data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND49</name>
<description>New data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND50</name>
<description>New data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND51</name>
<description>New data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND52</name>
<description>New data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND53</name>
<description>New data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND54</name>
<description>New data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND55</name>
<description>New data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND56</name>
<description>New data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND57</name>
<description>New data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND58</name>
<description>New data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND59</name>
<description>New data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND60</name>
<description>New data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND61</name>
<description>New data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND62</name>
<description>New data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND63</name>
<description>New data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0C</name>
<displayName>FDCAN_RXF0C</displayName>
<description>FDCAN Rx FIFO 0 Configuration
Register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0SA</name>
<description>Rx FIFO 0 Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>F0S</name>
<description>Rx FIFO 0 Size</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>F0WM</name>
<description>FIFO 0 Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0S</name>
<displayName>FDCAN_RXF0S</displayName>
<description>FDCAN Rx FIFO 0 Status
Register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0FL</name>
<description>Rx FIFO 0 Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F0G</name>
<description>Rx FIFO 0 Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F0P</name>
<description>Rx FIFO 0 Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F0F</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>Rx FIFO 0 Message Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0A</name>
<displayName>FDCAN_RXF0A</displayName>
<description>CAN Rx FIFO 0 Acknowledge
Register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FA01</name>
<description>Rx FIFO 0 Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXBC</name>
<displayName>FDCAN_RXBC</displayName>
<description>FDCAN Rx Buffer Configuration
Register</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RBSA</name>
<description>Rx Buffer Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1C</name>
<displayName>FDCAN_RXF1C</displayName>
<description>FDCAN Rx FIFO 1 Configuration
Register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1SA</name>
<description>Rx FIFO 1 Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>F1S</name>
<description>Rx FIFO 1 Size</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1WM</name>
<description>Rx FIFO 1 Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1S</name>
<displayName>FDCAN_RXF1S</displayName>
<description>FDCAN Rx FIFO 1 Status
Register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1FL</name>
<description>Rx FIFO 1 Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1GI</name>
<description>Rx FIFO 1 Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1PI</name>
<description>Rx FIFO 1 Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1F</name>
<description>Rx FIFO 1 Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>Rx FIFO 1 Message Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMS</name>
<description>Debug Message Status</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1A</name>
<displayName>FDCAN_RXF1A</displayName>
<description>FDCAN Rx FIFO 1 Acknowledge
Register</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1AI</name>
<description>Rx FIFO 1 Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXESC</name>
<displayName>FDCAN_RXESC</displayName>
<description>FDCAN Rx Buffer Element Size Configuration
Register</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0DS</name>
<description>Rx FIFO 1 Data Field Size:</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>F1DS</name>
<description>Rx FIFO 0 Data Field Size:</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RBDS</name>
<description>Rx Buffer Data Field Size:</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBC</name>
<displayName>FDCAN_TXBC</displayName>
<description>FDCAN Tx Buffer Configuration
Register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBSA</name>
<description>Tx Buffers Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>NDTB</name>
<description>Number of Dedicated Transmit
Buffers</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFQS</name>
<description>Transmit FIFO/Queue Size</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFQM</name>
<description>Tx FIFO/Queue Mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXFQS</name>
<displayName>FDCAN_TXFQS</displayName>
<description>FDCAN Tx FIFO/Queue Status
Register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TFFL</name>
<description>Tx FIFO Free Level</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFGI</name>
<description>TFGI</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TFQPI</name>
<description>Tx FIFO/Queue Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TFQF</name>
<description>Tx FIFO/Queue Full</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXESC</name>
<displayName>FDCAN_TXESC</displayName>
<description>FDCAN Tx Buffer Element Size Configuration
Register</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBDS</name>
<description>Tx Buffer Data Field Size:</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBRP</name>
<displayName>FDCAN_TXBRP</displayName>
<description>FDCAN Tx Buffer Request Pending
Register</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRP</name>
<description>Transmission Request
Pending</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBAR</name>
<displayName>FDCAN_TXBAR</displayName>
<description>FDCAN Tx Buffer Add Request
Register</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AR</name>
<description>Add Request</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCR</name>
<displayName>FDCAN_TXBCR</displayName>
<description>FDCAN Tx Buffer Cancellation Request
Register</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CR</name>
<description>Cancellation Request</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBTO</name>
<displayName>FDCAN_TXBTO</displayName>
<description>FDCAN Tx Buffer Transmission Occurred
Register</description>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TO</name>
<description>Transmission Occurred.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCF</name>
<displayName>FDCAN_TXBCF</displayName>
<description>FDCAN Tx Buffer Cancellation Finished
Register</description>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CF</name>
<description>Cancellation Finished</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBTIE</name>
<displayName>FDCAN_TXBTIE</displayName>
<description>FDCAN Tx Buffer Transmission Interrupt
Enable Register</description>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIE</name>
<description>Transmission Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCIE</name>
<displayName>FDCAN_TXBCIE</displayName>
<description>FDCAN Tx Buffer Cancellation Finished
Interrupt Enable Register</description>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CF</name>
<description>Cancellation Finished Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFC</name>
<displayName>FDCAN_TXEFC</displayName>
<description>FDCAN Tx Event FIFO Configuration
Register</description>
<addressOffset>0xF0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFSA</name>
<description>Event FIFO Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>EFS</name>
<description>Event FIFO Size</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>EFWM</name>
<description>Event FIFO Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFS</name>
<displayName>FDCAN_TXEFS</displayName>
<description>FDCAN Tx Event FIFO Status
Register</description>
<addressOffset>0xF4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFFL</name>
<description>Event FIFO Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>EFGI</name>
<description>Event FIFO Get Index.</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>EFF</name>
<description>Event FIFO Full.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx Event FIFO Element
Lost.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFA</name>
<displayName>FDCAN_TXEFA</displayName>
<description>FDCAN Tx Event FIFO Acknowledge
Register</description>
<addressOffset>0xF8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFAI</name>
<description>Event FIFO Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTMC</name>
<displayName>FDCAN_TTTMC</displayName>
<description>FDCAN TT Trigger Memory Configuration
Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TMSA</name>
<description>Trigger Memory Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>TME</name>
<description>Trigger Memory Elements</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTRMC</name>
<displayName>FDCAN_TTRMC</displayName>
<description>FDCAN TT Reference Message Configuration
Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RID</name>
<description>Reference Identifier.</description>
<bitOffset>0</bitOffset>
<bitWidth>29</bitWidth>
</field>
<field>
<name>XTD</name>
<description>Extended Identifier</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMPS</name>
<description>Reference Message Payload
Select</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOCF</name>
<displayName>FDCAN_TTOCF</displayName>
<description>FDCAN TT Operation Configuration
Register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010000</resetValue>
<fields>
<field>
<name>OM</name>
<description>Operation Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN</name>
<description>Gap Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TM</name>
<description>Time Master</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDSDL</name>
<description>LD of Synchronization Deviation
Limit</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IRTO</name>
<description>Initial Reference Trigger
Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>EECS</name>
<description>Enable External Clock
Synchronization</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWL</name>
<description>Application Watchdog Limit</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>EGTF</name>
<description>Enable Global Time
Filtering</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECC</name>
<description>Enable Clock Calibration</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTP</name>
<description>Event Trigger Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTMLM</name>
<displayName>FDCAN_TTMLM</displayName>
<description>FDCAN TT Matrix Limits
Register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCM</name>
<description>Cycle Count Max</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Cycle Start
Synchronization</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TXEW</name>
<description>Tx Enable Window</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ENTT</name>
<description>Expected Number of Tx
Triggers</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TURCF</name>
<displayName>FDCAN_TURCF</displayName>
<description>FDCAN TUR Configuration
Register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NCL</name>
<description>Numerator Configuration
Low.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DC</name>
<description>Denominator Configuration.</description>
<bitOffset>16</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>ELT</name>
<description>Enable Local Time</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOCN</name>
<displayName>FDCAN_TTOCN</displayName>
<description>FDCAN TT Operation Control
Register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SGT</name>
<description>Set Global time</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECS</name>
<description>External Clock
Synchronization</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWP</name>
<description>Stop Watch Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWS</name>
<description>Stop Watch Source.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RTIE</name>
<description>Register Time Mark Interrupt Pulse
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMC</name>
<description>Register Time Mark Compare</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TTIE</name>
<description>Trigger Time Mark Interrupt Pulse
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCS</name>
<description>Gap Control Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FGP</name>
<description>Finish Gap.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMG</name>
<description>Time Mark Gap</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NIG</name>
<description>Next is Gap</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESCN</name>
<description>External Synchronization
Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCKC</name>
<description>TT Operation Control Register
Locked</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAN_TTGTP</name>
<displayName>CAN_TTGTP</displayName>
<description>FDCAN TT Global Time Preset
Register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NCL</name>
<description>Time Preset</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CTP</name>
<description>Cycle Time Target Phase</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTMK</name>
<displayName>FDCAN_TTTMK</displayName>
<description>FDCAN TT Time Mark Register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TM</name>
<description>Time Mark</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TICC</name>
<description>Time Mark Cycle Code</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>LCKM</name>
<description>TT Time Mark Register
Locked</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTIR</name>
<displayName>FDCAN_TTIR</displayName>
<description>FDCAN TT Interrupt Register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBC</name>
<description>Start of Basic Cycle</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMC</name>
<description>Start of Matrix Cycle</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSM</name>
<description>Change of Synchronization
Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOG</name>
<description>Start of Gap</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMI</name>
<description>Register Time Mark
Interrupt.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMI</name>
<description>Trigger Time Mark Event
Internal</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWE</name>
<description>Stop Watch Event</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTW</name>
<description>Global Time Wrap</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTD</name>
<description>Global Time Discontinuity</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTE</name>
<description>Global Time Error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXU</name>
<description>Tx Count Underflow</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXO</name>
<description>Tx Count Overflow</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1</name>
<description>Scheduling Error 1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2</name>
<description>Scheduling Error 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELC</name>
<description>Error Level Changed.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTG</name>
<description>Initialization Watch
Trigger</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WT</name>
<description>Watch Trigger</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AW</name>
<description>Application Watchdog</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CER</name>
<description>Configuration Error</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTIE</name>
<displayName>FDCAN_TTIE</displayName>
<description>FDCAN TT Interrupt Enable
Register</description>
<addressOffset>0x124</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBCE</name>
<description>Start of Basic Cycle Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMCE</name>
<description>Start of Matrix Cycle Interrupt
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSME</name>
<description>Change of Synchronization Mode Interrupt
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOGE</name>
<description>Start of Gap Interrupt
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMIE</name>
<description>Register Time Mark Interrupt
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMIE</name>
<description>Trigger Time Mark Event Internal
Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWEE</name>
<description>Stop Watch Event Interrupt
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTWE</name>
<description>Global Time Wrap Interrupt
Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTDE</name>
<description>Global Time Discontinuity Interrupt
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTEE</name>
<description>Global Time Error Interrupt
Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUE</name>
<description>Tx Count Underflow Interrupt
Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOE</name>
<description>Tx Count Overflow Interrupt
Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1E</name>
<description>Scheduling Error 1 Interrupt
Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2E</name>
<description>Scheduling Error 2 Interrupt
Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELCE</name>
<description>Change Error Level Interrupt
Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTGE</name>
<description>Initialization Watch Trigger Interrupt
Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WTE</name>
<description>Watch Trigger Interrupt
Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWE</name>
<description>Application Watchdog Interrupt
Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CERE</name>
<description>Configuration Error Interrupt
Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTILS</name>
<displayName>FDCAN_TTILS</displayName>
<description>FDCAN TT Interrupt Line Select
Register</description>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBCL</name>
<description>Start of Basic Cycle Interrupt
Line</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMCL</name>
<description>Start of Matrix Cycle Interrupt
Line</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSML</name>
<description>Change of Synchronization Mode Interrupt
Line</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOGL</name>
<description>Start of Gap Interrupt
Line</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMIL</name>
<description>Register Time Mark Interrupt
Line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMIL</name>
<description>Trigger Time Mark Event Internal
Interrupt Line</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWEL</name>
<description>Stop Watch Event Interrupt
Line</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTWL</name>
<description>Global Time Wrap Interrupt
Line</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTDL</name>
<description>Global Time Discontinuity Interrupt
Line</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTEL</name>
<description>Global Time Error Interrupt
Line</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUL</name>
<description>Tx Count Underflow Interrupt
Line</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOL</name>
<description>Tx Count Overflow Interrupt
Line</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1L</name>
<description>Scheduling Error 1 Interrupt
Line</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2L</name>
<description>Scheduling Error 2 Interrupt
Line</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELCL</name>
<description>Change Error Level Interrupt
Line</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTGL</name>
<description>Initialization Watch Trigger Interrupt
Line</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WTL</name>
<description>Watch Trigger Interrupt
Line</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWL</name>
<description>Application Watchdog Interrupt
Line</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CERL</name>
<description>Configuration Error Interrupt
Line</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOST</name>
<displayName>FDCAN_TTOST</displayName>
<description>FDCAN TT Operation Status
Register</description>
<addressOffset>0x12C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EL</name>
<description>Error Level</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MS</name>
<description>Master State.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYS</name>
<description>Synchronization State</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GTP</name>
<description>Quality of Global Time
Phase</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QCS</name>
<description>Quality of Clock Speed</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Reference Trigger Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WGTD</name>
<description>Wait for Global Time
Discontinuity</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GFI</name>
<description>Gap Finished Indicator.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMP</name>
<description>Time Master Priority</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GSI</name>
<description>Gap Started Indicator.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WFE</name>
<description>Wait for Event</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWE</name>
<description>Application Watchdog Event</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WECS</name>
<description>Wait for External Clock
Synchronization</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPL</name>
<description>Schedule Phase Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TURNA</name>
<displayName>FDCAN_TURNA</displayName>
<description>FDCAN TUR Numerator Actual
Register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NAV</name>
<description>Numerator Actual Value</description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTLGT</name>
<displayName>FDCAN_TTLGT</displayName>
<description>FDCAN TT Local and Global Time
Register</description>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LT</name>
<description>Local Time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GT</name>
<description>Global Time</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCTC</name>
<displayName>FDCAN_TTCTC</displayName>
<description>FDCAN TT Cycle Time and Count
Register</description>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CT</name>
<description>Cycle Time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CC</name>
<description>Cycle Count</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCPT</name>
<displayName>FDCAN_TTCPT</displayName>
<description>FDCAN TT Capture Time Register</description>
<addressOffset>0x13C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CT</name>
<description>Cycle Count Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SWV</name>
<description>Stop Watch Value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCSM</name>
<displayName>FDCAN_TTCSM</displayName>
<description>FDCAN TT Cycle Sync Mark
Register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSM</name>
<description>Cycle Sync Mark</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTS</name>
<displayName>FDCAN_TTTS</displayName>
<description>FDCAN TT Trigger Select
Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWTDEL</name>
<description>Stop watch trigger input
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EVTSEL</name>
<description>Event trigger input
selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FMC</name>
<description>FMC</description>
<groupName>FMC</groupName>
<baseAddress>0x52004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FMC</name>
<description>FMC global interrupt</description>
<value>48</value>
</interrupt>
<registers>
<register>
<name>BCR1</name>
<displayName>BCR1</displayName>
<description>This register contains the control
information of each memory bank, used for SRAMs, PSRAM
and NOR Flash memories.</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000030DB</resetValue>
<fields>
<field>
<name>MBKEN</name>
<description>Memory bank enable bit This bit enables
the memory bank. After reset Bank1 is enabled, all
others are disabled. Accessing a disabled bank causes
an ERROR on AXI bus.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUXEN</name>
<description>Address/data multiplexing enable bit
When this bit is set, the address and data values are
multiplexed on the data bus, valid only with NOR and
PSRAM memories:</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTYP</name>
<description>Memory type These bits define the type
of external memory attached to the corresponding
memory bank:</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWID</name>
<description>Memory data bus width Defines the
external memory device width, valid for all type of
memories.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FACCEN</name>
<description>Flash access enable This bit enables NOR
Flash memory access operations.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BURSTEN</name>
<description>Burst enable bit This bit
enables/disables synchronous accesses during read
operations. It is valid only for synchronous memories
operating in Burst mode:</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITPOL</name>
<description>Wait signal polarity bit This bit
defines the polarity of the wait signal from memory
used for either in synchronous or asynchronous
mode:</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITCFG</name>
<description>Wait timing configuration The NWAIT
signal indicates whether the data from the memory are
valid or if a wait state must be inserted when
accessing the memory in synchronous mode. This
configuration bit determines if NWAIT is asserted by
the memory one clock cycle before the wait state or
during the wait state:</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WREN</name>
<description>Write enable bit This bit indicates
whether write operations are enabled/disabled in the
bank by the FMC:</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITEN</name>
<description>Wait enable bit This bit
enables/disables wait-state insertion via the NWAIT
signal when accessing the memory in synchronous
mode.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTMOD</name>
<description>Extended mode enable. This bit enables
the FMC to program the write timings for asynchronous
accesses inside the FMC_BWTR register, thus resulting
in different timings for read and write operations.
Note: When the extended mode is disabled, the FMC can
operate in Mode1 or Mode2 as follows: ** Mode 1 is
the default mode when the SRAM/PSRAM memory type is
selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
mode when the NOR memory type is selected (MTYP =
0x10).</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNCWAIT</name>
<description>Wait signal during asynchronous
transfers This bit enables/disables the FMC to use
the wait signal even during an asynchronous
protocol.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPSIZE</name>
<description>CRAM Page Size These are used for
Cellular RAM 1.5 which does not allow burst access to
cross the address boundaries between pages. When
these bits are configured, the FMC controller splits
automatically the burst access when the memory page
size is reached (refer to memory datasheet for page
size). Other configuration: reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CBURSTRW</name>
<description>Write burst enable For PSRAM (CRAM)
operating in Burst mode, the bit enables synchronous
accesses during write operations. The enable bit for
synchronous read accesses is the BURSTEN bit in the
FMC_BCRx register.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCLKEN</name>
<description>Continuous Clock Enable This bit enables
the FMC_CLK clock output to external memory devices.
Note: The CCLKEN bit of the FMC_BCR2..4 registers is
dont care. It is only enabled through the FMC_BCR1
register. Bank 1 must be configured in synchronous
mode to generate the FMC_CLK continuous clock. If
CCLKEN bit is set, the FMC_CLK clock ratio is
specified by CLKDIV value in the FMC_BTR1 register.
CLKDIV in FMC_BWTR1 is dont care. If the synchronous
mode is used and CCLKEN bit is set, the synchronous
memories connected to other banks than Bank 1 are
clocked by the same clock (the CLKDIV value in the
FMC_BTR2..4 and FMC_BWTR2..4 registers for other
banks has no effect.)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WFDIS</name>
<description>Write FIFO Disable This bit disables the
Write FIFO used by the FMC controller. Note: The
WFDIS bit of the FMC_BCR2..4 registers is dont care.
It is only enabled through the FMC_BCR1
register.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BMAP</name>
<description>FMC bank mapping These bits allows
different to remap SDRAM bank2 or swap the FMC
NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
The BMAP bits of the FMC_BCR2..4 registers are dont
care. It is only enabled through the FMC_BCR1
register.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FMCEN</name>
<description>FMC controller Enable This bit
enables/disables the FMC controller. Note: The FMCEN
bit of the FMC_BCR2..4 registers is dont care. It is
only enabled through the FMC_BCR1
register.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BTR1</name>
<displayName>BTR1</displayName>
<description>This register contains the control
information of each memory bank, used for SRAMs, PSRAM
and NOR Flash memories.If the EXTMOD bit is set in the
FMC_BCRx register, then this register is partitioned for
write and read access, that is, 2 registers are
available: one to configure read accesses (this register)
and one to configure write accesses (FMC_BWTRx
registers).</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ADDSET</name>
<description>Address setup phase duration These bits
are written by software to define the duration of the
address setup phase (refer to Figure81 to Figure93),
used in SRAMs, ROMs and asynchronous NOR Flash: For
each access mode address setup phase duration, please
refer to the respective figure (refer to Figure81 to
Figure93). Note: In synchronous accesses, this value
is dont care. In Muxed mode or Mode D, the minimum
value for ADDSET is 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDHLD</name>
<description>Address-hold phase duration These bits
are written by software to define the duration of the
address hold phase (refer to Figure81 to Figure93),
used in mode D or multiplexed accesses: For each
access mode address-hold phase duration, please refer
to the respective figure (Figure81 to Figure93).
Note: In synchronous accesses, this value is not
used, the address hold phase is always 1 memory clock
period duration.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>Data-phase duration These bits are
written by software to define the duration of the
data phase (refer to Figure81 to Figure93), used in
asynchronous accesses: For each memory type and
access mode data-phase duration, please refer to the
respective figure (Figure81 to Figure93). Example:
Mode1, write access, DATAST=1: Data-phase duration=
DATAST+1 = 2 KCK_FMC clock cycles. Note: In
synchronous accesses, this value is dont
care.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSTURN</name>
<description>Bus turnaround phase duration These bits
are written by software to add a delay at the end of
a write-to-read or read-to write transaction. The
programmed bus turnaround delay is inserted between
an asynchronous read (in muxed or mode D) or write
transaction and any other asynchronous /synchronous
read/write from/to a static bank. If a read operation
is performed, the bank can be the same or a different
one, whereas it must be different in case of write
operation to the bank, except in muxed mode or mode
D. In some cases, whatever the programmed BUSTRUN
values, the bus turnaround delay is fixed as follows:
The bus turnaround delay is not inserted between two
consecutive asynchronous write transfers to the same
static memory bank except in muxed mode and mode D.
There is a bus turnaround delay of 1 FMC clock cycle
between: Two consecutive asynchronous read transfers
to the same static memory bank except for modes muxed
and D. An asynchronous read to an asynchronous or
synchronous write to any static bank or dynamic bank
except in modes muxed and D mode. There is a bus
turnaround delay of 2 FMC clock cycle between: Two
consecutive synchronous write operations (in Burst or
Single mode) to the same bank. A synchronous write
(burst or single) access and an asynchronous write or
read transfer to or from static memory bank (the bank
can be the same or a different one in case of a read
operation. Two consecutive synchronous read
operations (in Burst or Single mode) followed by any
synchronous/asynchronous read or write from/to
another static memory bank. There is a bus turnaround
delay of 3 FMC clock cycle between: Two consecutive
synchronous write operations (in Burst or Single
mode) to different static banks. A synchronous write
access (in Burst or Single mode) and a synchronous
read from the same or a different bank. The bus
turnaround delay allows to match the minimum time
between consecutive transactions (tEHEL from NEx high
to NEx low) and the maximum time required by the
memory to free the data bus after a read access
(tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805;
tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
&amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126.
...</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKDIV</name>
<description>Clock divide ratio (for FMC_CLK signal)
These bits define the period of FMC_CLK clock output
signal, expressed in number of KCK_FMC cycles: In
asynchronous NOR Flash, SRAM or PSRAM accesses, this
value is dont care. Note: Refer to Section20.6.5:
Synchronous transactions for FMC_CLK divider ratio
formula)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATLAT</name>
<description>Data latency for synchronous memory For
synchronous access with read write burst mode enabled
these bits define the number of memory clock
cycles</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ACCMOD</name>
<description>Access mode These bits specify the
asynchronous access modes as shown in the timing
diagrams. They are taken into account only when the
EXTMOD bit in the FMC_BCRx register is
1.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCR2</name>
<displayName>BCR2</displayName>
<description>This register contains the control
information of each memory bank, used for SRAMs, PSRAM
and NOR Flash memories.</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000030D2</resetValue>
<fields>
<field>
<name>MBKEN</name>
<description>Memory bank enable bit This bit enables
the memory bank. After reset Bank1 is enabled, all
others are disabled. Accessing a disabled bank causes
an ERROR on AXI bus.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUXEN</name>
<description>Address/data multiplexing enable bit
When this bit is set, the address and data values are
multiplexed on the data bus, valid only with NOR and
PSRAM memories:</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTYP</name>
<description>Memory type These bits define the type
of external memory attached to the corresponding
memory bank:</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWID</name>
<description>Memory data bus width Defines the
external memory device width, valid for all type of
memories.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FACCEN</name>
<description>Flash access enable This bit enables NOR
Flash memory access operations.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BURSTEN</name>
<description>Burst enable bit This bit
enables/disables synchronous accesses during read
operations. It is valid only for synchronous memories
operating in Burst mode:</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITPOL</name>
<description>Wait signal polarity bit This bit
defines the polarity of the wait signal from memory
used for either in synchronous or asynchronous
mode:</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITCFG</name>
<description>Wait timing configuration The NWAIT
signal indicates whether the data from the memory are
valid or if a wait state must be inserted when
accessing the memory in synchronous mode. This
configuration bit determines if NWAIT is asserted by
the memory one clock cycle before the wait state or
during the wait state:</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WREN</name>
<description>Write enable bit This bit indicates
whether write operations are enabled/disabled in the
bank by the FMC:</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITEN</name>
<description>Wait enable bit This bit
enables/disables wait-state insertion via the NWAIT
signal when accessing the memory in synchronous
mode.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTMOD</name>
<description>Extended mode enable. This bit enables
the FMC to program the write timings for asynchronous
accesses inside the FMC_BWTR register, thus resulting
in different timings for read and write operations.
Note: When the extended mode is disabled, the FMC can
operate in Mode1 or Mode2 as follows: ** Mode 1 is
the default mode when the SRAM/PSRAM memory type is
selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
mode when the NOR memory type is selected (MTYP =
0x10).</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNCWAIT</name>
<description>Wait signal during asynchronous
transfers This bit enables/disables the FMC to use
the wait signal even during an asynchronous
protocol.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPSIZE</name>
<description>CRAM Page Size These are used for
Cellular RAM 1.5 which does not allow burst access to
cross the address boundaries between pages. When
these bits are configured, the FMC controller splits
automatically the burst access when the memory page
size is reached (refer to memory datasheet for page
size). Other configuration: reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CBURSTRW</name>
<description>Write burst enable For PSRAM (CRAM)
operating in Burst mode, the bit enables synchronous
accesses during write operations. The enable bit for
synchronous read accesses is the BURSTEN bit in the
FMC_BCRx register.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCLKEN</name>
<description>Continuous Clock Enable This bit enables
the FMC_CLK clock output to external memory devices.
Note: The CCLKEN bit of the FMC_BCR2..4 registers is
dont care. It is only enabled through the FMC_BCR1
register. Bank 1 must be configured in synchronous
mode to generate the FMC_CLK continuous clock. If
CCLKEN bit is set, the FMC_CLK clock ratio is
specified by CLKDIV value in the FMC_BTR1 register.
CLKDIV in FMC_BWTR1 is dont care. If the synchronous
mode is used and CCLKEN bit is set, the synchronous
memories connected to other banks than Bank 1 are
clocked by the same clock (the CLKDIV value in the
FMC_BTR2..4 and FMC_BWTR2..4 registers for other
banks has no effect.)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WFDIS</name>
<description>Write FIFO Disable This bit disables the
Write FIFO used by the FMC controller. Note: The
WFDIS bit of the FMC_BCR2..4 registers is dont care.
It is only enabled through the FMC_BCR1
register.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BMAP</name>
<description>FMC bank mapping These bits allows
different to remap SDRAM bank2 or swap the FMC
NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
The BMAP bits of the FMC_BCR2..4 registers are dont
care. It is only enabled through the FMC_BCR1
register.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FMCEN</name>
<description>FMC controller Enable This bit
enables/disables the FMC controller. Note: The FMCEN
bit of the FMC_BCR2..4 registers is dont care. It is
only enabled through the FMC_BCR1
register.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BTR2</name>
<displayName>BTR2</displayName>
<description>This register contains the control
information of each memory bank, used for SRAMs, PSRAM
and NOR Flash memories.If the EXTMOD bit is set in the
FMC_BCRx register, then this register is partitioned for
write and read access, that is, 2 registers are
available: one to configure read accesses (this register)
and one to configure write accesses (FMC_BWTRx
registers).</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ADDSET</name>
<description>Address setup phase duration These bits
are written by software to define the duration of the
address setup phase (refer to Figure81 to Figure93),
used in SRAMs, ROMs and asynchronous NOR Flash: For
each access mode address setup phase duration, please
refer to the respective figure (refer to Figure81 to
Figure93). Note: In synchronous accesses, this value
is dont care. In Muxed mode or Mode D, the minimum
value for ADDSET is 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDHLD</name>
<description>Address-hold phase duration These bits
are written by software to define the duration of the
address hold phase (refer to Figure81 to Figure93),
used in mode D or multiplexed accesses: For each
access mode address-hold phase duration, please refer
to the respective figure (Figure81 to Figure93).
Note: In synchronous accesses, this value is not
used, the address hold phase is always 1 memory clock
period duration.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>Data-phase duration These bits are
written by software to define the duration of the
data phase (refer to Figure81 to Figure93), used in
asynchronous accesses: For each memory type and
access mode data-phase duration, please refer to the
respective figure (Figure81 to Figure93). Example:
Mode1, write access, DATAST=1: Data-phase duration=
DATAST+1 = 2 KCK_FMC clock cycles. Note: In
synchronous accesses, this value is dont
care.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSTURN</name>
<description>Bus turnaround phase duration These bits
are written by software to add a delay at the end of
a write-to-read or read-to write transaction. The
programmed bus turnaround delay is inserted between
an asynchronous read (in muxed or mode D) or write
transaction and any other asynchronous /synchronous
read/write from/to a static bank. If a read operation
is performed, the bank can be the same or a different
one, whereas it must be different in case of write
operation to the bank, except in muxed mode or mode
D. In some cases, whatever the programmed BUSTRUN
values, the bus turnaround delay is fixed as follows:
The bus turnaround delay is not inserted between two
consecutive asynchronous write transfers to the same
static memory bank except in muxed mode and mode D.
There is a bus turnaround delay of 1 FMC clock cycle
between: Two consecutive asynchronous read transfers
to the same static memory bank except for modes muxed
and D. An asynchronous read to an asynchronous or
synchronous write to any static bank or dynamic bank
except in modes muxed and D mode. There is a bus
turnaround delay of 2 FMC clock cycle between: Two
consecutive synchronous write operations (in Burst or
Single mode) to the same bank. A synchronous write
(burst or single) access and an asynchronous write or
read transfer to or from static memory bank (the bank
can be the same or a different one in case of a read
operation. Two consecutive synchronous read
operations (in Burst or Single mode) followed by any
synchronous/asynchronous read or write from/to
another static memory bank. There is a bus turnaround
delay of 3 FMC clock cycle between: Two consecutive
synchronous write operations (in Burst or Single
mode) to different static banks. A synchronous write
access (in Burst or Single mode) and a synchronous
read from the same or a different bank. The bus
turnaround delay allows to match the minimum time
between consecutive transactions (tEHEL from NEx high
to NEx low) and the maximum time required by the
memory to free the data bus after a read access
(tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805;
tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
&amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 1.
...</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKDIV</name>
<description>Clock divide ratio (for FMC_CLK signal)
These bits define the period of FMC_CLK clock output
signal, expressed in number of KCK_FMC cycles: In
asynchronous NOR Flash, SRAM or PSRAM accesses, this
value is dont care. Note: Refer to Section20.6.5:
Synchronous transactions for FMC_CLK divider ratio
formula)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATLAT</name>
<description>Data latency for synchronous memory For
synchronous access with read write burst mode enabled
these bits define the number of memory clock
cycles</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ACCMOD</name>
<description>Access mode These bits specify the
asynchronous access modes as shown in the timing
diagrams. They are taken into account only when the
EXTMOD bit in the FMC_BCRx register is
1.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCR3</name>
<displayName>BCR3</displayName>
<description>This register contains the control
information of each memory bank, used for SRAMs, PSRAM
and NOR Flash memories.</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000030D2</resetValue>
<fields>
<field>
<name>MBKEN</name>
<description>Memory bank enable bit This bit enables
the memory bank. After reset Bank1 is enabled, all
others are disabled. Accessing a disabled bank causes
an ERROR on AXI bus.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUXEN</name>
<description>Address/data multiplexing enable bit
When this bit is set, the address and data values are
multiplexed on the data bus, valid only with NOR and
PSRAM memories:</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTYP</name>
<description>Memory type These bits define the type
of external memory attached to the corresponding
memory bank:</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWID</name>
<description>Memory data bus width Defines the
external memory device width, valid for all type of
memories.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FACCEN</name>
<description>Flash access enable This bit enables NOR
Flash memory access operations.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BURSTEN</name>
<description>Burst enable bit This bit
enables/disables synchronous accesses during read
operations. It is valid only for synchronous memories
operating in Burst mode:</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITPOL</name>
<description>Wait signal polarity bit This bit
defines the polarity of the wait signal from memory
used for either in synchronous or asynchronous
mode:</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITCFG</name>
<description>Wait timing configuration The NWAIT
signal indicates whether the data from the memory are
valid or if a wait state must be inserted when
accessing the memory in synchronous mode. This
configuration bit determines if NWAIT is asserted by
the memory one clock cycle before the wait state or
during the wait state:</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WREN</name>
<description>Write enable bit This bit indicates
whether write operations are enabled/disabled in the
bank by the FMC:</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITEN</name>
<description>Wait enable bit This bit
enables/disables wait-state insertion via the NWAIT
signal when accessing the memory in synchronous
mode.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTMOD</name>
<description>Extended mode enable. This bit enables
the FMC to program the write timings for asynchronous
accesses inside the FMC_BWTR register, thus resulting
in different timings for read and write operations.
Note: When the extended mode is disabled, the FMC can
operate in Mode1 or Mode2 as follows: ** Mode 1 is
the default mode when the SRAM/PSRAM memory type is
selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
mode when the NOR memory type is selected (MTYP =
0x10).</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNCWAIT</name>
<description>Wait signal during asynchronous
transfers This bit enables/disables the FMC to use
the wait signal even during an asynchronous
protocol.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPSIZE</name>
<description>CRAM Page Size These are used for
Cellular RAM 1.5 which does not allow burst access to
cross the address boundaries between pages. When
these bits are configured, the FMC controller splits
automatically the burst access when the memory page
size is reached (refer to memory datasheet for page
size). Other configuration: reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CBURSTRW</name>
<description>Write burst enable For PSRAM (CRAM)
operating in Burst mode, the bit enables synchronous
accesses during write operations. The enable bit for
synchronous read accesses is the BURSTEN bit in the
FMC_BCRx register.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCLKEN</name>
<description>Continuous Clock Enable This bit enables
the FMC_CLK clock output to external memory devices.
Note: The CCLKEN bit of the FMC_BCR2..4 registers is
dont care. It is only enabled through the FMC_BCR1
register. Bank 1 must be configured in synchronous
mode to generate the FMC_CLK continuous clock. If
CCLKEN bit is set, the FMC_CLK clock ratio is
specified by CLKDIV value in the FMC_BTR1 register.
CLKDIV in FMC_BWTR1 is dont care. If the synchronous
mode is used and CCLKEN bit is set, the synchronous
memories connected to other banks than Bank 1 are
clocked by the same clock (the CLKDIV value in the
FMC_BTR2..4 and FMC_BWTR2..4 registers for other
banks has no effect.)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WFDIS</name>
<description>Write FIFO Disable This bit disables the
Write FIFO used by the FMC controller. Note: The
WFDIS bit of the FMC_BCR2..4 registers is dont care.
It is only enabled through the FMC_BCR1
register.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BMAP</name>
<description>FMC bank mapping These bits allows
different to remap SDRAM bank2 or swap the FMC
NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
The BMAP bits of the FMC_BCR2..4 registers are dont
care. It is only enabled through the FMC_BCR1
register.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FMCEN</name>
<description>FMC controller Enable This bit
enables/disables the FMC controller. Note: The FMCEN
bit of the FMC_BCR2..4 registers is dont care. It is
only enabled through the FMC_BCR1
register.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BTR3</name>
<displayName>BTR3</displayName>
<description>This register contains the control
information of each memory bank, used for SRAMs, PSRAM
and NOR Flash memories.If the EXTMOD bit is set in the
FMC_BCRx register, then this register is partitioned for
write and read access, that is, 2 registers are
available: one to configure read accesses (this register)
and one to configure write accesses (FMC_BWTRx
registers).</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ADDSET</name>
<description>Address setup phase duration These bits
are written by software to define the duration of the
address setup phase (refer to Figure81 to Figure93),
used in SRAMs, ROMs and asynchronous NOR Flash: For
each access mode address setup phase duration, please
refer to the respective figure (refer to Figure81 to
Figure93). Note: In synchronous accesses, this value
is dont care. In Muxed mode or Mode D, the minimum
value for ADDSET is 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDHLD</name>
<description>Address-hold phase duration These bits
are written by software to define the duration of the
address hold phase (refer to Figure81 to Figure93),
used in mode D or multiplexed accesses: For each
access mode address-hold phase duration, please refer
to the respective figure (Figure81 to Figure93).
Note: In synchronous accesses, this value is not
used, the address hold phase is always 1 memory clock
period duration.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>Data-phase duration These bits are
written by software to define the duration of the
data phase (refer to Figure81 to Figure93), used in
asynchronous accesses: For each memory type and
access mode data-phase duration, please refer to the
respective figure (Figure81 to Figure93). Example:
Mode1, write access, DATAST=1: Data-phase duration=
DATAST+1 = 2 KCK_FMC clock cycles. Note: In
synchronous accesses, this value is dont
care.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSTURN</name>
<description>Bus turnaround phase duration These bits
are written by software to add a delay at the end of
a write-to-read or read-to write transaction. The
programmed bus turnaround delay is inserted between
an asynchronous read (in muxed or mode D) or write
transaction and any other asynchronous /synchronous
read/write from/to a static bank. If a read operation
is performed, the bank can be the same or a different
one, whereas it must be different in case of write
operation to the bank, except in muxed mode or mode
D. In some cases, whatever the programmed BUSTRUN
values, the bus turnaround delay is fixed as follows:
The bus turnaround delay is not inserted between two
consecutive asynchronous write transfers to the same
static memory bank except in muxed mode and mode D.
There is a bus turnaround delay of 1 FMC clock cycle
between: Two consecutive asynchronous read transfers
to the same static memory bank except for modes muxed
and D. An asynchronous read to an asynchronous or
synchronous write to any static bank or dynamic bank
except in modes muxed and D mode. There is a bus
turnaround delay of 2 FMC clock cycle between: Two
consecutive synchronous write operations (in Burst or
Single mode) to the same bank. A synchronous write
(burst or single) access and an asynchronous write or
read transfer to or from static memory bank (the bank
can be the same or a different one in case of a read
operation. Two consecutive synchronous read
operations (in Burst or Single mode) followed by any
synchronous/asynchronous read or write from/to
another static memory bank. There is a bus turnaround
delay of 3 FMC clock cycle between: Two consecutive
synchronous write operations (in Burst or Single
mode) to different static banks. A synchronous write
access (in Burst or Single mode) and a synchronous
read from the same or a different bank. The bus
turnaround delay allows to match the minimum time
between consecutive transactions (tEHEL from NEx high
to NEx low) and the maximum time required by the
memory to free the data bus after a read access
(tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805;
tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
&amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1.
...</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKDIV</name>
<description>Clock divide ratio (for FMC_CLK signal)
These bits define the period of FMC_CLK clock output
signal, expressed in number of KCK_FMC cycles: In
asynchronous NOR Flash, SRAM or PSRAM accesses, this
value is dont care. Note: Refer to Section20.6.5:
Synchronous transactions for FMC_CLK divider ratio
formula)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATLAT</name>
<description>Data latency for synchronous memory For
synchronous access with read write burst mode enabled
these bits define the number of memory clock
cycles</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ACCMOD</name>
<description>Access mode These bits specify the
asynchronous access modes as shown in the timing
diagrams. They are taken into account only when the
EXTMOD bit in the FMC_BCRx register is
1.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCR4</name>
<displayName>BCR4</displayName>
<description>This register contains the control
information of each memory bank, used for SRAMs, PSRAM
and NOR Flash memories.</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000030D2</resetValue>
<fields>
<field>
<name>MBKEN</name>
<description>Memory bank enable bit This bit enables
the memory bank. After reset Bank1 is enabled, all
others are disabled. Accessing a disabled bank causes
an ERROR on AXI bus.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUXEN</name>
<description>Address/data multiplexing enable bit
When this bit is set, the address and data values are
multiplexed on the data bus, valid only with NOR and
PSRAM memories:</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTYP</name>
<description>Memory type These bits define the type
of external memory attached to the corresponding
memory bank:</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWID</name>
<description>Memory data bus width Defines the
external memory device width, valid for all type of
memories.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FACCEN</name>
<description>Flash access enable This bit enables NOR
Flash memory access operations.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BURSTEN</name>
<description>Burst enable bit This bit
enables/disables synchronous accesses during read
operations. It is valid only for synchronous memories
operating in Burst mode:</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITPOL</name>
<description>Wait signal polarity bit This bit
defines the polarity of the wait signal from memory
used for either in synchronous or asynchronous
mode:</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITCFG</name>
<description>Wait timing configuration The NWAIT
signal indicates whether the data from the memory are
valid or if a wait state must be inserted when
accessing the memory in synchronous mode. This
configuration bit determines if NWAIT is asserted by
the memory one clock cycle before the wait state or
during the wait state:</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WREN</name>
<description>Write enable bit This bit indicates
whether write operations are enabled/disabled in the
bank by the FMC:</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITEN</name>
<description>Wait enable bit This bit
enables/disables wait-state insertion via the NWAIT
signal when accessing the memory in synchronous
mode.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTMOD</name>
<description>Extended mode enable. This bit enables
the FMC to program the write timings for asynchronous
accesses inside the FMC_BWTR register, thus resulting
in different timings for read and write operations.
Note: When the extended mode is disabled, the FMC can
operate in Mode1 or Mode2 as follows: ** Mode 1 is
the default mode when the SRAM/PSRAM memory type is
selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
mode when the NOR memory type is selected (MTYP =
0x10).</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNCWAIT</name>
<description>Wait signal during asynchronous
transfers This bit enables/disables the FMC to use
the wait signal even during an asynchronous
protocol.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPSIZE</name>
<description>CRAM Page Size These are used for
Cellular RAM 1.5 which does not allow burst access to
cross the address boundaries between pages. When
these bits are configured, the FMC controller splits
automatically the burst access when the memory page
size is reached (refer to memory datasheet for page
size). Other configuration: reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CBURSTRW</name>
<description>Write burst enable For PSRAM (CRAM)
operating in Burst mode, the bit enables synchronous
accesses during write operations. The enable bit for
synchronous read accesses is the BURSTEN bit in the
FMC_BCRx register.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCLKEN</name>
<description>Continuous Clock Enable This bit enables
the FMC_CLK clock output to external memory devices.
Note: The CCLKEN bit of the FMC_BCR2..4 registers is
dont care. It is only enabled through the FMC_BCR1
register. Bank 1 must be configured in synchronous
mode to generate the FMC_CLK continuous clock. If
CCLKEN bit is set, the FMC_CLK clock ratio is
specified by CLKDIV value in the FMC_BTR1 register.
CLKDIV in FMC_BWTR1 is dont care. If the synchronous
mode is used and CCLKEN bit is set, the synchronous
memories connected to other banks than Bank 1 are
clocked by the same clock (the CLKDIV value in the
FMC_BTR2..4 and FMC_BWTR2..4 registers for other
banks has no effect.)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WFDIS</name>
<description>Write FIFO Disable This bit disables the
Write FIFO used by the FMC controller. Note: The
WFDIS bit of the FMC_BCR2..4 registers is dont care.
It is only enabled through the FMC_BCR1
register.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BMAP</name>
<description>FMC bank mapping These bits allows
different to remap SDRAM bank2 or swap the FMC
NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
The BMAP bits of the FMC_BCR2..4 registers are dont
care. It is only enabled through the FMC_BCR1
register.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FMCEN</name>
<description>FMC controller Enable This bit
enables/disables the FMC controller. Note: The FMCEN
bit of the FMC_BCR2..4 registers is dont care. It is
only enabled through the FMC_BCR1
register.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BTR4</name>
<displayName>BTR4</displayName>
<description>This register contains the control
information of each memory bank, used for SRAMs, PSRAM
and NOR Flash memories.If the EXTMOD bit is set in the
FMC_BCRx register, then this register is partitioned for
write and read access, that is, 2 registers are
available: one to configure read accesses (this register)
and one to configure write accesses (FMC_BWTRx
registers).</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ADDSET</name>
<description>Address setup phase duration These bits
are written by software to define the duration of the
address setup phase (refer to Figure81 to Figure93),
used in SRAMs, ROMs and asynchronous NOR Flash: For
each access mode address setup phase duration, please
refer to the respective figure (refer to Figure81 to
Figure93). Note: In synchronous accesses, this value
is dont care. In Muxed mode or Mode D, the minimum
value for ADDSET is 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDHLD</name>
<description>Address-hold phase duration These bits
are written by software to define the duration of the
address hold phase (refer to Figure81 to Figure93),
used in mode D or multiplexed accesses: For each
access mode address-hold phase duration, please refer
to the respective figure (Figure81 to Figure93).
Note: In synchronous accesses, this value is not
used, the address hold phase is always 1 memory clock
period duration.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>Data-phase duration These bits are
written by software to define the duration of the
data phase (refer to Figure81 to Figure93), used in
asynchronous accesses: For each memory type and
access mode data-phase duration, please refer to the
respective figure (Figure81 to Figure93). Example:
Mode1, write access, DATAST=1: Data-phase duration=
DATAST+1 = 2 KCK_FMC clock cycles. Note: In
synchronous accesses, this value is dont
care.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSTURN</name>
<description>Bus turnaround phase duration These bits
are written by software to add a delay at the end of
a write-to-read or read-to write transaction. The
programmed bus turnaround delay is inserted between
an asynchronous read (in muxed or mode D) or write
transaction and any other asynchronous /synchronous
read/write from/to a static bank. If a read operation
is performed, the bank can be the same or a different
one, whereas it must be different in case of write
operation to the bank, except in muxed mode or mode
D. In some cases, whatever the programmed BUSTRUN
values, the bus turnaround delay is fixed as follows:
The bus turnaround delay is not inserted between two
consecutive asynchronous write transfers to the same
static memory bank except in muxed mode and mode D.
There is a bus turnaround delay of 1 FMC clock cycle
between: Two consecutive asynchronous read transfers
to the same static memory bank except for modes muxed
and D. An asynchronous read to an asynchronous or
synchronous write to any static bank or dynamic bank
except in modes muxed and D mode. There is a bus
turnaround delay of 2 FMC clock cycle between: Two
consecutive synchronous write operations (in Burst or
Single mode) to the same bank. A synchronous write
(burst or single) access and an asynchronous write or
read transfer to or from static memory bank (the bank
can be the same or a different one in case of a read
operation. Two consecutive synchronous read
operations (in Burst or Single mode) followed by any
synchronous/asynchronous read or write from/to
another static memory bank. There is a bus turnaround
delay of 3 FMC clock cycle between: Two consecutive
synchronous write operations (in Burst or Single
mode) to different static banks. A synchronous write
access (in Burst or Single mode) and a synchronous
read from the same or a different bank. The bus
turnaround delay allows to match the minimum time
between consecutive transactions (tEHEL from NEx high
to NEx low) and the maximum time required by the
memory to free the data bus after a read access
(tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805;
tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
&amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1.
...</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKDIV</name>
<description>Clock divide ratio (for FMC_CLK signal)
These bits define the period of FMC_CLK clock output
signal, expressed in number of KCK_FMC cycles: In
asynchronous NOR Flash, SRAM or PSRAM accesses, this
value is dont care. Note: Refer to Section20.6.5:
Synchronous transactions for FMC_CLK divider ratio
formula)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATLAT</name>
<description>Data latency for synchronous memory For
synchronous access with read write burst mode enabled
these bits define the number of memory clock
cycles</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ACCMOD</name>
<description>Access mode These bits specify the
asynchronous access modes as shown in the timing
diagrams. They are taken into account only when the
EXTMOD bit in the FMC_BCRx register is
1.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCR</name>
<displayName>PCR</displayName>
<description>NAND Flash control registers</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000018</resetValue>
<fields>
<field>
<name>PWAITEN</name>
<description>Wait feature enable bit. This bit
enables the Wait feature for the NAND Flash memory
bank:</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PBKEN</name>
<description>NAND Flash memory bank enable bit. This
bit enables the memory bank. Accessing a disabled
memory bank causes an ERROR on AXI bus</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWID</name>
<description>Data bus width. These bits define the
external memory device width.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ECCEN</name>
<description>ECC computation logic enable
bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCLR</name>
<description>CLE to RE delay. These bits set time
from CLE low to RE low in number of KCK_FMC clock
cycles. The time is give by the following formula:
t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is
the KCK_FMC clock period Note: Set is MEMSET or
ATTSET according to the addressed
space.</description>
<bitOffset>9</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TAR</name>
<description>ALE to RE delay. These bits set time
from ALE low to RE low in number of KCK_FMC clock
cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC
where TKCK_FMC is the FMC clock period Note: Set is
MEMSET or ATTSET according to the addressed
space.</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ECCPS</name>
<description>ECC page size. These bits define the
page size for the extended ECC:</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>This register contains information about the
FIFO status and interrupt. The FMC features a FIFO that
is used when writing to memories to transfer up to 16
words of data.This is used to quickly write to the FIFO
and free the AXI bus for transactions to peripherals
other than the FMC, while the FMC is draining its FIFO
into the memory. One of these register bits indicates the
status of the FIFO, for ECC purposes.The ECC is
calculated while the data are written to the memory. To
read the correct ECC, the software must consequently wait
until the FIFO is empty.</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>IRS</name>
<description>Interrupt rising edge status The flag is
set by hardware and reset by software. Note: If this
bit is written by software to 1 it will be
set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ILS</name>
<description>Interrupt high-level status The flag is
set by hardware and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IFS</name>
<description>Interrupt falling edge status The flag
is set by hardware and reset by software. Note: If
this bit is written by software to 1 it will be
set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IREN</name>
<description>Interrupt rising edge detection enable
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ILEN</name>
<description>Interrupt high-level detection enable
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IFEN</name>
<description>Interrupt falling edge detection enable
bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FEMPT</name>
<description>FIFO empty. Read-only bit that provides
the status of the FIFO</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PMEM</name>
<displayName>PMEM</displayName>
<description>The FMC_PMEM read/write register contains
the timing information for NAND Flash memory bank. This
information is used to access either the common memory
space of the NAND Flash for command, address write access
and data read/write access.</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>MEMSET</name>
<description>Common memory x setup time These bits
define the number of KCK_FMC (+1) clock cycles to set
up the address before the command assertion (NWE,
NOE), for NAND Flash read or write access to common
memory space:</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MEMWAIT</name>
<description>Common memory wait time These bits
define the minimum number of KCK_FMC (+1) clock
cycles to assert the command (NWE, NOE), for NAND
Flash read or write access to common memory space.
The duration of command assertion is extended if the
wait signal (NWAIT) is active (low) at the end of the
programmed value of KCK_FMC:</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MEMHOLD</name>
<description>Common memory hold time These bits
define the number of KCK_FMC clock cycles for write
accesses and KCK_FMC+1 clock cycles for read accesses
during which the address is held (and data for write
accesses) after the command is de-asserted (NWE,
NOE), for NAND Flash read or write access to common
memory space:</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MEMHIZ</name>
<description>Common memory x data bus Hi-Z time These
bits define the number of KCK_FMC clock cycles during
which the data bus is kept Hi-Z after the start of a
NAND Flash write access to common memory space. This
is only valid for write transactions:</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PATT</name>
<displayName>PATT</displayName>
<description>The FMC_PATT read/write register contains
the timing information for NAND Flash memory bank. It is
used for 8-bit accesses to the attribute memory space of
the NAND Flash for the last address write access if the
timing must differ from that of previous accesses (for
Ready/Busy management, refer to Section20.8.5: NAND Flash
prewait feature).</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>ATTSET</name>
<description>Attribute memory setup time These bits
define the number of KCK_FMC (+1) clock cycles to set
up address before the command assertion (NWE, NOE),
for NAND Flash read or write access to attribute
memory space:</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ATTWAIT</name>
<description>Attribute memory wait time These bits
define the minimum number of x KCK_FMC (+1) clock
cycles to assert the command (NWE, NOE), for NAND
Flash read or write access to attribute memory space.
The duration for command assertion is extended if the
wait signal (NWAIT) is active (low) at the end of the
programmed value of KCK_FMC:</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ATTHOLD</name>
<description>Attribute memory hold time These bits
define the number of KCK_FMC clock cycles during
which the address is held (and data for write access)
after the command de-assertion (NWE, NOE), for NAND
Flash read or write access to attribute memory
space:</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ATTHIZ</name>
<description>Attribute memory data bus Hi-Z time
These bits define the number of KCK_FMC clock cycles
during which the data bus is kept in Hi-Z after the
start of a NAND Flash write access to attribute
memory space on socket. Only valid for writ
transaction:</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECCR</name>
<displayName>ECCR</displayName>
<description>This register contain the current error
correction code value computed by the ECC computation
modules of the FMC NAND controller. When the CPU
reads/writes the data from a NAND Flash memory page at
the correct address (refer to Section20.8.6: Computation
of the error correction code (ECC) in NAND Flash memory),
the data read/written from/to the NAND Flash memory are
processed automatically by the ECC computation module.
When X bytes have been read (according to the ECCPS field
in the FMC_PCR registers), the CPU must read the computed
ECC value from the FMC_ECC registers. It then verifies if
these computed parity data are the same as the parity
value recorded in the spare area, to determine whether a
page is valid, and, to correct it otherwise. The FMC_ECCR
register should be cleared after being read by setting
the ECCEN bit to 0. To compute a new data block, the
ECCEN bit must be set to 1.</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECC</name>
<description>ECC result This field contains the value
computed by the ECC computation logic. Table167
describes the contents of these bit
fields.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BWTR1</name>
<displayName>BWTR1</displayName>
<description>This register contains the control
information of each memory bank. It is used for SRAMs,
PSRAMs and NOR Flash memories. When the EXTMOD bit is set
in the FMC_BCRx register, then this register is active
for write access.</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ADDSET</name>
<description>Address setup phase duration. These bits
are written by software to define the duration of the
address setup phase in KCK_FMC cycles (refer to
Figure81 to Figure93), used in asynchronous accesses:
... Note: In synchronous accesses, this value is not
used, the address setup phase is always 1 Flash clock
period duration. In muxed mode, the minimum ADDSET
value is 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDHLD</name>
<description>Address-hold phase duration. These bits
are written by software to define the duration of the
address hold phase (refer to Figure81 to Figure93),
used in asynchronous multiplexed accesses: ... Note:
In synchronous NOR Flash accesses, this value is not
used, the address hold phase is always 1 Flash clock
period duration.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>Data-phase duration. These bits are
written by software to define the duration of the
data phase (refer to Figure81 to Figure93), used in
asynchronous SRAM, PSRAM and NOR Flash memory
accesses:</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSTURN</name>
<description>Bus turnaround phase duration These bits
are written by software to add a delay at the end of
a write transaction to match the minimum time between
consecutive transactions (tEHEL from ENx high to ENx
low): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
tEHELmin. The programmed bus turnaround delay is
inserted between a an asynchronous write transfer and
any other asynchronous /synchronous read or write
transfer to or from a static bank. If a read
operation is performed, the bank can be the same or a
different one, whereas it must be different in case
of write operation to the bank, except in muxed mode
or mode D. In some cases, whatever the programmed
BUSTRUN values, the bus turnaround delay is fixed as
follows: The bus turnaround delay is not inserted
between two consecutive asynchronous write transfers
to the same static memory bank except for muxed mode
and mode D. There is a bus turnaround delay of 2 FMC
clock cycle between: Two consecutive synchronous
write operations (in Burst or Single mode) to the
same bank A synchronous write transfer ((in Burst or
Single mode) and an asynchronous write or read
transfer to or from static memory bank. There is a
bus turnaround delay of 3 FMC clock cycle between:
Two consecutive synchronous write operations (in
Burst or Single mode) to different static banks. A
synchronous write transfer (in Burst or Single mode)
and a synchronous read from the same or a different
bank. ...</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ACCMOD</name>
<description>Access mode. These bits specify the
asynchronous access modes as shown in the next timing
diagrams.These bits are taken into account only when
the EXTMOD bit in the FMC_BCRx register is
1.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BWTR2</name>
<displayName>BWTR2</displayName>
<description>This register contains the control
information of each memory bank. It is used for SRAMs,
PSRAMs and NOR Flash memories. When the EXTMOD bit is set
in the FMC_BCRx register, then this register is active
for write access.</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ADDSET</name>
<description>Address setup phase duration. These bits
are written by software to define the duration of the
address setup phase in KCK_FMC cycles (refer to
Figure81 to Figure93), used in asynchronous accesses:
... Note: In synchronous accesses, this value is not
used, the address setup phase is always 1 Flash clock
period duration. In muxed mode, the minimum ADDSET
value is 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDHLD</name>
<description>Address-hold phase duration. These bits
are written by software to define the duration of the
address hold phase (refer to Figure81 to Figure93),
used in asynchronous multiplexed accesses: ... Note:
In synchronous NOR Flash accesses, this value is not
used, the address hold phase is always 1 Flash clock
period duration.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>Data-phase duration. These bits are
written by software to define the duration of the
data phase (refer to Figure81 to Figure93), used in
asynchronous SRAM, PSRAM and NOR Flash memory
accesses:</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSTURN</name>
<description>Bus turnaround phase duration These bits
are written by software to add a delay at the end of
a write transaction to match the minimum time between
consecutive transactions (tEHEL from ENx high to ENx
low): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
tEHELmin. The programmed bus turnaround delay is
inserted between a an asynchronous write transfer and
any other asynchronous /synchronous read or write
transfer to or from a static bank. If a read
operation is performed, the bank can be the same or a
different one, whereas it must be different in case
of write operation to the bank, except in muxed mode
or mode D. In some cases, whatever the programmed
BUSTRUN values, the bus turnaround delay is fixed as
follows: The bus turnaround delay is not inserted
between two consecutive asynchronous write transfers
to the same static memory bank except for muxed mode
and mode D. There is a bus turnaround delay of 2 FMC
clock cycle between: Two consecutive synchronous
write operations (in Burst or Single mode) to the
same bank A synchronous write transfer ((in Burst or
Single mode) and an asynchronous write or read
transfer to or from static memory bank. There is a
bus turnaround delay of 3 FMC clock cycle between:
Two consecutive synchronous write operations (in
Burst or Single mode) to different static banks. A
synchronous write transfer (in Burst or Single mode)
and a synchronous read from the same or a different
bank. ...</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ACCMOD</name>
<description>Access mode. These bits specify the
asynchronous access modes as shown in the next timing
diagrams.These bits are taken into account only when
the EXTMOD bit in the FMC_BCRx register is
1.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BWTR3</name>
<displayName>BWTR3</displayName>
<description>This register contains the control
information of each memory bank. It is used for SRAMs,
PSRAMs and NOR Flash memories. When the EXTMOD bit is set
in the FMC_BCRx register, then this register is active
for write access.</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ADDSET</name>
<description>Address setup phase duration. These bits
are written by software to define the duration of the
address setup phase in KCK_FMC cycles (refer to
Figure81 to Figure93), used in asynchronous accesses:
... Note: In synchronous accesses, this value is not
used, the address setup phase is always 1 Flash clock
period duration. In muxed mode, the minimum ADDSET
value is 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDHLD</name>
<description>Address-hold phase duration. These bits
are written by software to define the duration of the
address hold phase (refer to Figure81 to Figure93),
used in asynchronous multiplexed accesses: ... Note:
In synchronous NOR Flash accesses, this value is not
used, the address hold phase is always 1 Flash clock
period duration.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>Data-phase duration. These bits are
written by software to define the duration of the
data phase (refer to Figure81 to Figure93), used in
asynchronous SRAM, PSRAM and NOR Flash memory
accesses:</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSTURN</name>
<description>Bus turnaround phase duration These bits
are written by software to add a delay at the end of
a write transaction to match the minimum time between
consecutive transactions (tEHEL from ENx high to ENx
low): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
tEHELmin. The programmed bus turnaround delay is
inserted between a an asynchronous write transfer and
any other asynchronous /synchronous read or write
transfer to or from a static bank. If a read
operation is performed, the bank can be the same or a
different one, whereas it must be different in case
of write operation to the bank, except in muxed mode
or mode D. In some cases, whatever the programmed
BUSTRUN values, the bus turnaround delay is fixed as
follows: The bus turnaround delay is not inserted
between two consecutive asynchronous write transfers
to the same static memory bank except for muxed mode
and mode D. There is a bus turnaround delay of 2 FMC
clock cycle between: Two consecutive synchronous
write operations (in Burst or Single mode) to the
same bank A synchronous write transfer ((in Burst or
Single mode) and an asynchronous write or read
transfer to or from static memory bank. There is a
bus turnaround delay of 3 FMC clock cycle between:
Two consecutive synchronous write operations (in
Burst or Single mode) to different static banks. A
synchronous write transfer (in Burst or Single mode)
and a synchronous read from the same or a different
bank. ...</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ACCMOD</name>
<description>Access mode. These bits specify the
asynchronous access modes as shown in the next timing
diagrams.These bits are taken into account only when
the EXTMOD bit in the FMC_BCRx register is
1.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BWTR4</name>
<displayName>BWTR4</displayName>
<description>This register contains the control
information of each memory bank. It is used for SRAMs,
PSRAMs and NOR Flash memories. When the EXTMOD bit is set
in the FMC_BCRx register, then this register is active
for write access.</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ADDSET</name>
<description>Address setup phase duration. These bits
are written by software to define the duration of the
address setup phase in KCK_FMC cycles (refer to
Figure81 to Figure93), used in asynchronous accesses:
... Note: In synchronous accesses, this value is not
used, the address setup phase is always 1 Flash clock
period duration. In muxed mode, the minimum ADDSET
value is 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDHLD</name>
<description>Address-hold phase duration. These bits
are written by software to define the duration of the
address hold phase (refer to Figure81 to Figure93),
used in asynchronous multiplexed accesses: ... Note:
In synchronous NOR Flash accesses, this value is not
used, the address hold phase is always 1 Flash clock
period duration.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>Data-phase duration. These bits are
written by software to define the duration of the
data phase (refer to Figure81 to Figure93), used in
asynchronous SRAM, PSRAM and NOR Flash memory
accesses:</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSTURN</name>
<description>Bus turnaround phase duration These bits
are written by software to add a delay at the end of
a write transaction to match the minimum time between
consecutive transactions (tEHEL from ENx high to ENx
low): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
tEHELmin. The programmed bus turnaround delay is
inserted between a an asynchronous write transfer and
any other asynchronous /synchronous read or write
transfer to or from a static bank. If a read
operation is performed, the bank can be the same or a
different one, whereas it must be different in case
of write operation to the bank, except in muxed mode
or mode D. In some cases, whatever the programmed
BUSTRUN values, the bus turnaround delay is fixed as
follows: The bus turnaround delay is not inserted
between two consecutive asynchronous write transfers
to the same static memory bank except for muxed mode
and mode D. There is a bus turnaround delay of 2 FMC
clock cycle between: Two consecutive synchronous
write operations (in Burst or Single mode) to the
same bank A synchronous write transfer ((in Burst or
Single mode) and an asynchronous write or read
transfer to or from static memory bank. There is a
bus turnaround delay of 3 FMC clock cycle between:
Two consecutive synchronous write operations (in
Burst or Single mode) to different static banks. A
synchronous write transfer (in Burst or Single mode)
and a synchronous read from the same or a different
bank. ...</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ACCMOD</name>
<description>Access mode. These bits specify the
asynchronous access modes as shown in the next timing
diagrams.These bits are taken into account only when
the EXTMOD bit in the FMC_BCRx register is
1.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDCR1</name>
<displayName>SDCR1</displayName>
<description>This register contains the control
parameters for each SDRAM memory bank</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000002D0</resetValue>
<fields>
<field>
<name>NC</name>
<description>Number of column address bits These bits
define the number of bits of a column
address.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NR</name>
<description>Number of row address bits These bits
define the number of bits of a row
address.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWID</name>
<description>Memory data bus width. These bits define
the memory device width.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NB</name>
<description>Number of internal banks This bit sets
the number of internal banks.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAS</name>
<description>CAS Latency This bits sets the SDRAM CAS
latency in number of memory clock
cycles</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WP</name>
<description>Write protection This bit enables write
mode access to the SDRAM bank.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDCLK</name>
<description>SDRAM clock configuration These bits
define the SDRAM clock period for both SDRAM banks
and allow disabling the clock before changing the
frequency. In this case the SDRAM must be
re-initialized. Note: The corresponding bits in the
FMC_SDCR2 register is read only.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RBURST</name>
<description>Burst read This bit enables burst read
mode. The SDRAM controller anticipates the next read
commands during the CAS latency and stores data in
the Read FIFO. Note: The corresponding bit in the
FMC_SDCR2 register is read only.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RPIPE</name>
<description>Read pipe These bits define the delay,
in KCK_FMC clock cycles, for reading data after CAS
latency. Note: The corresponding bits in the
FMC_SDCR2 register is read only.</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDCR2</name>
<displayName>SDCR2</displayName>
<description>This register contains the control
parameters for each SDRAM memory bank</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000002D0</resetValue>
<fields>
<field>
<name>NC</name>
<description>Number of column address bits These bits
define the number of bits of a column
address.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NR</name>
<description>Number of row address bits These bits
define the number of bits of a row
address.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MWID</name>
<description>Memory data bus width. These bits define
the memory device width.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NB</name>
<description>Number of internal banks This bit sets
the number of internal banks.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAS</name>
<description>CAS Latency This bits sets the SDRAM CAS
latency in number of memory clock
cycles</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WP</name>
<description>Write protection This bit enables write
mode access to the SDRAM bank.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDCLK</name>
<description>SDRAM clock configuration These bits
define the SDRAM clock period for both SDRAM banks
and allow disabling the clock before changing the
frequency. In this case the SDRAM must be
re-initialized. Note: The corresponding bits in the
FMC_SDCR2 register is read only.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RBURST</name>
<description>Burst read This bit enables burst read
mode. The SDRAM controller anticipates the next read
commands during the CAS latency and stores data in
the Read FIFO. Note: The corresponding bit in the
FMC_SDCR2 register is read only.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RPIPE</name>
<description>Read pipe These bits define the delay,
in KCK_FMC clock cycles, for reading data after CAS
latency. Note: The corresponding bits in the
FMC_SDCR2 register is read only.</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDTR1</name>
<displayName>SDTR1</displayName>
<description>This register contains the timing parameters
of each SDRAM bank</description>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>TMRD</name>
<description>Load Mode Register to Active These bits
define the delay between a Load Mode Register command
and an Active or Refresh command in number of memory
clock cycles. ....</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TXSR</name>
<description>Exit Self-refresh delay These bits
define the delay from releasing the Self-refresh
command to issuing the Activate command in number of
memory clock cycles. .... Note: If two SDRAM devices
are used, the FMC_SDTR1 and FMC_SDTR2 must be
programmed with the same TXSR timing corresponding to
the slowest SDRAM device.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRAS</name>
<description>Self refresh time These bits define the
minimum Self-refresh period in number of memory clock
cycles. ....</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRC</name>
<description>Row cycle delay These bits define the
delay between the Refresh command and the Activate
command, as well as the delay between two consecutive
Refresh commands. It is expressed in number of memory
clock cycles. The TRC timing is only configured in
the FMC_SDTR1 register. If two SDRAM devices are
used, the TRC must be programmed with the timings of
the slowest device. .... Note: TRC must match the TRC
and TRFC (Auto Refresh period) timings defined in the
SDRAM device datasheet. Note: The corresponding bits
in the FMC_SDTR2 register are dont
care.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TWR</name>
<description>Recovery delay These bits define the
delay between a Write and a Precharge command in
number of memory clock cycles. .... Note: TWR must be
programmed to match the write recovery time (tWR)
defined in the SDRAM datasheet, and to guarantee
that: TWR &amp;#8805; TRAS - TRCD and TWR
&amp;#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles,
TRCD= 2 cycles. So, TWR &amp;gt;= 2 cycles. TWR must
be programmed to 0x1. If two SDRAM devices are used,
the FMC_SDTR1 and FMC_SDTR2 must be programmed with
the same TWR timing corresponding to the slowest
SDRAM device.</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRP</name>
<description>Row precharge delay These bits define
the delay between a Precharge command and another
command in number of memory clock cycles. The TRP
timing is only configured in the FMC_SDTR1 register.
If two SDRAM devices are used, the TRP must be
programmed with the timing of the slowest device.
.... Note: The corresponding bits in the FMC_SDTR2
register are dont care.</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRCD</name>
<description>Row to column delay These bits define
the delay between the Activate command and a
Read/Write command in number of memory clock cycles.
....</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDTR2</name>
<displayName>SDTR2</displayName>
<description>This register contains the timing parameters
of each SDRAM bank</description>
<addressOffset>0x14C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>TMRD</name>
<description>Load Mode Register to Active These bits
define the delay between a Load Mode Register command
and an Active or Refresh command in number of memory
clock cycles. ....</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TXSR</name>
<description>Exit Self-refresh delay These bits
define the delay from releasing the Self-refresh
command to issuing the Activate command in number of
memory clock cycles. .... Note: If two SDRAM devices
are used, the FMC_SDTR1 and FMC_SDTR2 must be
programmed with the same TXSR timing corresponding to
the slowest SDRAM device.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRAS</name>
<description>Self refresh time These bits define the
minimum Self-refresh period in number of memory clock
cycles. ....</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRC</name>
<description>Row cycle delay These bits define the
delay between the Refresh command and the Activate
command, as well as the delay between two consecutive
Refresh commands. It is expressed in number of memory
clock cycles. The TRC timing is only configured in
the FMC_SDTR1 register. If two SDRAM devices are
used, the TRC must be programmed with the timings of
the slowest device. .... Note: TRC must match the TRC
and TRFC (Auto Refresh period) timings defined in the
SDRAM device datasheet. Note: The corresponding bits
in the FMC_SDTR2 register are dont
care.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TWR</name>
<description>Recovery delay These bits define the
delay between a Write and a Precharge command in
number of memory clock cycles. .... Note: TWR must be
programmed to match the write recovery time (tWR)
defined in the SDRAM datasheet, and to guarantee
that: TWR &amp;#8805; TRAS - TRCD and TWR
&amp;#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles,
TRCD= 2 cycles. So, TWR &amp;gt;= 2 cycles. TWR must
be programmed to 0x1. If two SDRAM devices are used,
the FMC_SDTR1 and FMC_SDTR2 must be programmed with
the same TWR timing corresponding to the slowest
SDRAM device.</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRP</name>
<description>Row precharge delay These bits define
the delay between a Precharge command and another
command in number of memory clock cycles. The TRP
timing is only configured in the FMC_SDTR1 register.
If two SDRAM devices are used, the TRP must be
programmed with the timing of the slowest device.
.... Note: The corresponding bits in the FMC_SDTR2
register are dont care.</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TRCD</name>
<description>Row to column delay These bits define
the delay between the Activate command and a
Read/Write command in number of memory clock cycles.
....</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDCMR</name>
<displayName>SDCMR</displayName>
<description>This register contains the command issued
when the SDRAM device is accessed. This register is used
to initialize the SDRAM device, and to activate the
Self-refresh and the Power-down modes. As soon as the
MODE field is written, the command will be issued only to
one or to both SDRAM banks according to CTB1 and CTB2
command bits. This register is the same for both SDRAM
banks.</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE</name>
<description>Command mode These bits define the
command issued to the SDRAM device. Note: When a
command is issued, at least one Command Target Bank
bit ( CTB1 or CTB2) must be set otherwise the command
will be ignored. Note: If two SDRAM banks are used,
the Auto-refresh and PALL command must be issued
simultaneously to the two devices with CTB1 and CTB2
bits set otherwise the command will be ignored. Note:
If only one SDRAM bank is used and a command is
issued with its associated CTB bit set, the other CTB
bit of the unused bank must be kept to
0.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CTB2</name>
<description>Command Target Bank 2 This bit indicates
whether the command will be issued to SDRAM Bank 2 or
not.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTB1</name>
<description>Command Target Bank 1 This bit indicates
whether the command will be issued to SDRAM Bank 1 or
not.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NRFS</name>
<description>Number of Auto-refresh These bits define
the number of consecutive Auto-refresh commands
issued when MODE = 011. ....</description>
<bitOffset>5</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MRD</name>
<description>Mode Register definition This 14-bit
field defines the SDRAM Mode Register content. The
Mode Register is programmed using the Load Mode
Register command. The MRD[13:0] bits are also used to
program the extended mode register for mobile
SDRAM.</description>
<bitOffset>9</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDRTR</name>
<displayName>SDRTR</displayName>
<description>This register sets the refresh rate in
number of SDCLK clock cycles between the refresh cycles
by configuring the Refresh Timer Count value.Examplewhere
64 ms is the SDRAM refresh period.The refresh rate must
be increased by 20 SDRAM clock cycles (as in the above
example) to obtain a safe margin if an internal refresh
request occurs when a read request has been accepted. It
corresponds to a COUNT value of 0000111000000 (448). This
13-bit field is loaded into a timer which is decremented
using the SDRAM clock. This timer generates a refresh
pulse when zero is reached. The COUNT value must be set
at least to 41 SDRAM clock cycles.As soon as the
FMC_SDRTR register is programmed, the timer starts
counting. If the value programmed in the register is 0,
no refresh is carried out. This register must not be
reprogrammed after the initialization procedure to avoid
modifying the refresh rate.Each time a refresh pulse is
generated, this 13-bit COUNT field is reloaded into the
counter.If a memory access is in progress, the
Auto-refresh request is delayed. However, if the memory
access and Auto-refresh requests are generated
simultaneously, the Auto-refresh takes precedence. If the
memory access occurs during a refresh operation, the
request is buffered to be processed when the refresh is
complete.This register is common to SDRAM bank 1 and bank
2.</description>
<addressOffset>0x154</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRE</name>
<description>Clear Refresh error flag This bit is
used to clear the Refresh Error Flag (RE) in the
Status Register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>COUNT</name>
<description>Refresh Timer Count This 13-bit field
defines the refresh rate of the SDRAM device. It is
expressed in number of memory clock cycles. It must
be set at least to 41 SDRAM clock cycles (0x29).
Refresh rate = (COUNT + 1) x SDRAM frequency clock
COUNT = (SDRAM refresh period / Number of rows) -
20</description>
<bitOffset>1</bitOffset>
<bitWidth>13</bitWidth>
<access>read-write</access>
</field>
<field>
<name>REIE</name>
<description>RES Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SDSR</name>
<displayName>SDSR</displayName>
<description>SDRAM Status register</description>
<addressOffset>0x158</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RE</name>
<description>Refresh error flag An interrupt is
generated if REIE = 1 and RE = 1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODES1</name>
<description>Status Mode for Bank 1 These bits define
the Status Mode of SDRAM Bank 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODES2</name>
<description>Status Mode for Bank 2 These bits define
the Status Mode of SDRAM Bank 2.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU</name>
<description>Floting point unit</description>
<groupName>FPU</groupName>
<baseAddress>0xE000EF34</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>FPCCR</name>
<displayName>FPCCR</displayName>
<description>Floating-point context control
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSPACT</name>
<description>LSPACT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USER</name>
<description>USER</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THREAD</name>
<description>THREAD</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFRDY</name>
<description>HFRDY</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRDY</name>
<description>MMRDY</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFRDY</name>
<description>BFRDY</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONRDY</name>
<description>MONRDY</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPEN</name>
<description>LSPEN</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASPEN</name>
<description>ASPEN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPCAR</name>
<displayName>FPCAR</displayName>
<description>Floating-point context address
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Location of unpopulated
floating-point</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPSCR</name>
<displayName>FPSCR</displayName>
<description>Floating-point status control
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOC</name>
<description>Invalid operation cumulative exception
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DZC</name>
<description>Division by zero cumulative exception
bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFC</name>
<description>Overflow cumulative exception
bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UFC</name>
<description>Underflow cumulative exception
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IXC</name>
<description>Inexact cumulative exception
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDC</name>
<description>Input denormal cumulative exception
bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMode</name>
<description>Rounding Mode control
field</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FZ</name>
<description>Flush-to-zero mode control
bit:</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DN</name>
<description>Default NaN mode control
bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHP</name>
<description>Alternative half-precision control
bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>V</name>
<description>Overflow condition code
flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>Carry condition code flag</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Z</name>
<description>Zero condition code flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>N</name>
<description>Negative condition code
flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU_CPACR</name>
<description>Floating point unit CPACR</description>
<groupName>FPU</groupName>
<baseAddress>0xE000ED88</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CPACR</name>
<displayName>CPACR</displayName>
<description>Coprocessor access control
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000000</resetValue>
<fields>
<field>
<name>CP</name>
<description>CP</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>Flash</name>
<description>Flash</description>
<groupName>Flash</groupName>
<baseAddress>0x52002000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FLASH</name>
<description>Flash memory global interrupt</description>
<value>4</value>
</interrupt>
<registers>
<register>
<name>ACR</name>
<displayName>ACR</displayName>
<description>Access control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000600</resetValue>
<fields>
<field>
<name>LATENCY</name>
<description>Read latency</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>WRHIGHFREQ</name>
<description>Flash signal delay</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACR_</name>
<displayName>ACR_</displayName>
<description>Access control register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LATENCY</name>
<description>Read latency</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>WRHIGHFREQ</name>
<description>Flash signal delay</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR1</name>
<displayName>KEYR1</displayName>
<description>FLASH key register for bank 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEYR1</name>
<description>Bank 1 access configuration unlock
key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTKEYR</name>
<displayName>OPTKEYR</displayName>
<description>FLASH option key register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTKEYR</name>
<description>Unlock key option bytes</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTKEYR_</name>
<displayName>OPTKEYR_</displayName>
<description>FLASH option key register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTKEYR</name>
<description>Unlock key option bytes</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>FLASH control register for bank
1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK1</name>
<description>Bank 1 configuration lock
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PG1</name>
<description>Bank 1 program enable bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SER1</name>
<description>Bank 1 sector erase
request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BER1</name>
<description>Bank 1 erase request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE1</name>
<description>Bank 1 program size</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FW1</name>
<description>Bank 1 write forcing control
bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START1</name>
<description>Bank 1 bank or sector erase start
control bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNB1</name>
<description>Bank 1 sector erase selection
number</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CRC_EN</name>
<description>Bank 1 CRC control bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOPIE1</name>
<description>Bank 1 end-of-program interrupt control
bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRPERRIE1</name>
<description>Bank 1 write protection error interrupt
enable bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGSERRIE1</name>
<description>Bank 1 programming sequence error
interrupt enable bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRBERRIE1</name>
<description>Bank 1 strobe error interrupt enable
bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INCERRIE1</name>
<description>Bank 1 inconsistency error interrupt
enable bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPERRIE1</name>
<description>Bank 1 write/erase error interrupt
enable bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDPERRIE1</name>
<description>Bank 1 read protection error interrupt
enable bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDSERRIE1</name>
<description>Bank 1 secure error interrupt enable
bit</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNECCERRIE1</name>
<description>Bank 1 ECC single correction error
interrupt enable bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBECCERRIE1</name>
<description>Bank 1 ECC double detection error
interrupt enable bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCENDIE1</name>
<description>Bank 1 end of CRC calculation interrupt
enable bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR1</name>
<displayName>SR1</displayName>
<description>FLASH status register for bank
1</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BSY1</name>
<description>Bank 1 ongoing program
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WBNE1</name>
<description>Bank 1 write buffer not empty
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QW1</name>
<description>Bank 1 wait queue flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_BUSY1</name>
<description>Bank 1 CRC busy flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOP1</name>
<description>Bank 1 end-of-program flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRPERR1</name>
<description>Bank 1 write protection error
flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGSERR1</name>
<description>Bank 1 programming sequence error
flag</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRBERR1</name>
<description>Bank 1 strobe error flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INCERR1</name>
<description>Bank 1 inconsistency error
flag</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPERR1</name>
<description>Bank 1 write/erase error
flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDPERR1</name>
<description>Bank 1 read protection error
flag</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDSERR1</name>
<description>Bank 1 secure error flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNECCERR11</name>
<description>Bank 1 single correction error
flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBECCERR1</name>
<description>Bank 1 ECC double detection error
flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCEND1</name>
<description>Bank 1 CRC-complete flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>FLASH clear control register for bank
1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLR_EOP1</name>
<description>Bank 1 EOP1 flag clear bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_WRPERR1</name>
<description>Bank 1 WRPERR1 flag clear
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_PGSERR1</name>
<description>Bank 1 PGSERR1 flag clear
bi</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_STRBERR1</name>
<description>Bank 1 STRBERR1 flag clear
bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_INCERR1</name>
<description>Bank 1 INCERR1 flag clear
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_OPERR1</name>
<description>Bank 1 OPERR1 flag clear
bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_RDPERR1</name>
<description>Bank 1 RDPERR1 flag clear
bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_RDSERR1</name>
<description>Bank 1 RDSERR1 flag clear
bit</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_SNECCERR1</name>
<description>Bank 1 SNECCERR1 flag clear
bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_DBECCERR1</name>
<description>Bank 1 DBECCERR1 flag clear
bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_CRCEND1</name>
<description>Bank 1 CRCEND1 flag clear
bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTCR</name>
<displayName>OPTCR</displayName>
<description>FLASH option control register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTLOCK</name>
<description>FLASH_OPTCR lock option configuration
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTSTART</name>
<description>Option byte start change option
configuration bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MER</name>
<description>Flash mass erase enable
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTCHANGEERRIE</name>
<description>Option byte change error interrupt
enable bit</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP_BANK</name>
<description>Bank swapping configuration
bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTCR_</name>
<displayName>OPTCR_</displayName>
<description>FLASH option control register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTLOCK</name>
<description>FLASH_OPTCR lock option configuration
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTSTART</name>
<description>Option byte start change option
configuration bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MER</name>
<description>Flash mass erase enable
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTCHANGEERRIE</name>
<description>Option byte change error interrupt
enable bit</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP_BANK</name>
<description>Bank swapping configuration
bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTSR_CUR_</name>
<displayName>OPTSR_CUR_</displayName>
<description>FLASH option status register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPT_BUSY</name>
<description>Option byte change ongoing
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOR_LEV</name>
<description>Brownout level option status
bit</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IWDG1_HW</name>
<description>IWDG1 control option status
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STOP_D1</name>
<description>D1 DStop entry reset option status
bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STBY_D1</name>
<description>D1 DStandby entry reset option status
bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDP</name>
<description>Readout protection level option status
byte</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FZ_IWDG_STOP</name>
<description>IWDG Stop mode freeze option status
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FZ_IWDG_SDBY</name>
<description>IWDG Standby mode freeze option status
bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST_RAM_SIZE</name>
<description>DTCM RAM size option
status</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SECURITY</name>
<description>Security enable option status
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSS1</name>
<description>User option bit 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERSO_OK</name>
<description>Device personalization status
bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IO_HSLV</name>
<description>I/O high-speed at low-voltage status bit
(PRODUCT_BELOW_25V)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTCHANGEERR</name>
<description>Option byte change error
flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP_BANK_OPT</name>
<description>Bank swapping option status
bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTSR_CUR</name>
<displayName>OPTSR_CUR</displayName>
<description>FLASH option status register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPT_BUSY</name>
<description>Option byte change ongoing
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOR_LEV</name>
<description>Brownout level option status
bit</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IWDG1_HW</name>
<description>IWDG1 control option status
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STOP_D1</name>
<description>D1 DStop entry reset option status
bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STBY_D1</name>
<description>D1 DStandby entry reset option status
bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDP</name>
<description>Readout protection level option status
byte</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FZ_IWDG_STOP</name>
<description>IWDG Stop mode freeze option status
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FZ_IWDG_SDBY</name>
<description>IWDG Standby mode freeze option status
bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST_RAM_SIZE</name>
<description>DTCM RAM size option
status</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SECURITY</name>
<description>Security enable option status
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSS1</name>
<description>User option bit 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERSO_OK</name>
<description>Device personalization status
bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IO_HSLV</name>
<description>I/O high-speed at low-voltage status bit
(PRODUCT_BELOW_25V)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTCHANGEERR</name>
<description>Option byte change error
flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP_BANK_OPT</name>
<description>Bank swapping option status
bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTSR_PRG</name>
<displayName>OPTSR_PRG</displayName>
<description>FLASH option status register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BOR_LEV</name>
<description>BOR reset level option configuration
bits</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IWDG1_HW</name>
<description>IWDG1 option configuration
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STOP_D1</name>
<description>Option byte erase after D1 DStop option
configuration bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STBY_D1</name>
<description>Option byte erase after D1 DStandby
option configuration bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDP</name>
<description>Readout protection level option
configuration byte</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FZ_IWDG_STOP</name>
<description>IWDG Stop mode freeze option
configuration bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FZ_IWDG_SDBY</name>
<description>IWDG Standby mode freeze option
configuration bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST_RAM_SIZE</name>
<description>DTCM size select option configuration
bits</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SECURITY</name>
<description>Security option configuration
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSS1</name>
<description>User option configuration bit
1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSS2</name>
<description>User option configuration bit
2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IO_HSLV</name>
<description>I/O high-speed at low-voltage
(PRODUCT_BELOW_25V)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP_BANK_OPT</name>
<description>Bank swapping option configuration
bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTSR_PRG_</name>
<displayName>OPTSR_PRG_</displayName>
<description>FLASH option status register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BOR_LEV</name>
<description>BOR reset level option configuration
bits</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IWDG1_HW</name>
<description>IWDG1 option configuration
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STOP_D1</name>
<description>Option byte erase after D1 DStop option
configuration bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STBY_D1</name>
<description>Option byte erase after D1 DStandby
option configuration bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDP</name>
<description>Readout protection level option
configuration byte</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FZ_IWDG_STOP</name>
<description>IWDG Stop mode freeze option
configuration bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FZ_IWDG_SDBY</name>
<description>IWDG Standby mode freeze option
configuration bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST_RAM_SIZE</name>
<description>DTCM size select option configuration
bits</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SECURITY</name>
<description>Security option configuration
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSS1</name>
<description>User option configuration bit
1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSS2</name>
<description>User option configuration bit
2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IO_HSLV</name>
<description>I/O high-speed at low-voltage
(PRODUCT_BELOW_25V)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP_BANK_OPT</name>
<description>Bank swapping option configuration
bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTCCR_</name>
<displayName>OPTCCR_</displayName>
<description>FLASH option clear control
register</description>
<addressOffset>0x124</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLR_OPTCHANGEERR</name>
<description>OPTCHANGEERR reset bit</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTCCR</name>
<displayName>OPTCCR</displayName>
<description>FLASH option clear control
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLR_OPTCHANGEERR</name>
<description>OPTCHANGEERR reset bit</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRAR_CUR1</name>
<displayName>PRAR_CUR1</displayName>
<description>FLASH protection address for bank
1</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROT_AREA_START1</name>
<description>Bank 1 lowest PCROP protected
address</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>PROT_AREA_END1</name>
<description>Bank 1 highest PCROP protected
address</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DMEP1</name>
<description>Bank 1 PCROP protected erase enable
option status bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRAR_PRG1</name>
<displayName>PRAR_PRG1</displayName>
<description>FLASH protection address for bank
1</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROT_AREA_START1</name>
<description>Bank 1 lowest PCROP protected address
configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>PROT_AREA_END1</name>
<description>Bank 1 highest PCROP protected address
configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DMEP1</name>
<description>Bank 1 PCROP protected erase enable
option configuration bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPSN_CUR1R</name>
<displayName>WPSN_CUR1R</displayName>
<description>FLASH write sector protection for bank
1</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WRPSn1</name>
<description>Bank 1 sector write protection option
status byte</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPSN_PRG1R</name>
<displayName>WPSN_PRG1R</displayName>
<description>FLASH write sector protection for bank
1</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WRPSn1</name>
<description>Bank 1 sector write protection
configuration byte</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BOOT_CURR</name>
<displayName>BOOT_CURR</displayName>
<description>FLASH register with boot
address</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BOOT_ADD0</name>
<description>Boot address 0</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>BOOT_ADD1</name>
<description>Boot address 1</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BOOT_PRGR</name>
<displayName>BOOT_PRGR</displayName>
<description>FLASH register with boot
address</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BOOT_ADD0</name>
<description>Boot address 0</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>BOOT_ADD1</name>
<description>Boot address 1</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCCR1</name>
<displayName>CRCCR1</displayName>
<description>FLASH CRC control register for bank
1</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_SECT</name>
<description>Bank 1 CRC sector number</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ALL_BANK</name>
<description>Bank 1 CRC select bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_BY_SECT</name>
<description>Bank 1 CRC sector mode select
bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD_SECT</name>
<description>Bank 1 CRC sector select
bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLEAN_SECT</name>
<description>Bank 1 CRC sector list clear
bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START_CRC</name>
<description>Bank 1 CRC start bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLEAN_CRC</name>
<description>Bank 1 CRC clear bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_BURST</name>
<description>Bank 1 CRC burst size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCSADD1R</name>
<displayName>CRCSADD1R</displayName>
<description>FLASH CRC start address register for bank
1</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_START_ADDR</name>
<description>CRC start address on bank
1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCEADD1R</name>
<displayName>CRCEADD1R</displayName>
<description>FLASH CRC end address register for bank
1</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_END_ADDR</name>
<description>CRC end address on bank 1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCDATAR</name>
<displayName>CRCDATAR</displayName>
<description>FLASH CRC data register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_DATA</name>
<description>CRC result</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECC_FA1R</name>
<displayName>ECC_FA1R</displayName>
<description>FLASH ECC fail address for bank
1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FAIL_ECC_ADDR1</name>
<description>Bank 1 ECC error address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR2</name>
<displayName>KEYR2</displayName>
<description>FLASH key register for bank 2</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEYR2</name>
<description>Bank 2 access configuration unlock
key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>FLASH control register for bank
2</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK2</name>
<description>Bank 2 configuration lock
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PG2</name>
<description>Bank 2 program enable bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SER2</name>
<description>Bank 2 sector erase
request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BER2</name>
<description>Bank 2 erase request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSIZE2</name>
<description>Bank 2 program size</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FW2</name>
<description>Bank 2 write forcing control
bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START2</name>
<description>Bank 2 bank or sector erase start
control bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNB2</name>
<description>Bank 2 sector erase selection
number</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CRC_EN</name>
<description>Bank 2 CRC control bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOPIE2</name>
<description>Bank 2 end-of-program interrupt control
bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRPERRIE2</name>
<description>Bank 2 write protection error interrupt
enable bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGSERRIE2</name>
<description>Bank 2 programming sequence error
interrupt enable bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRBERRIE2</name>
<description>Bank 2 strobe error interrupt enable
bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INCERRIE2</name>
<description>Bank 2 inconsistency error interrupt
enable bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPERRIE2</name>
<description>Bank 2 write/erase error interrupt
enable bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDPERRIE2</name>
<description>Bank 2 read protection error interrupt
enable bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDSERRIE2</name>
<description>Bank 2 secure error interrupt enable
bit</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNECCERRIE2</name>
<description>Bank 2 ECC single correction error
interrupt enable bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBECCERRIE2</name>
<description>Bank 2 ECC double detection error
interrupt enable bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCENDIE2</name>
<description>Bank 2 end of CRC calculation interrupt
enable bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR2</name>
<displayName>SR2</displayName>
<description>FLASH status register for bank
2</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BSY2</name>
<description>Bank 2 ongoing program
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WBNE2</name>
<description>Bank 2 write buffer not empty
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QW2</name>
<description>Bank 2 wait queue flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_BUSY2</name>
<description>Bank 2 CRC busy flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOP2</name>
<description>Bank 2 end-of-program flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRPERR2</name>
<description>Bank 2 write protection error
flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGSERR2</name>
<description>Bank 2 programming sequence error
flag</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRBERR2</name>
<description>Bank 2 strobe error flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INCERR2</name>
<description>Bank 2 inconsistency error
flag</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPERR2</name>
<description>Bank 2 write/erase error
flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDPERR2</name>
<description>Bank 2 read protection error
flag</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDSERR2</name>
<description>Bank 2 secure error flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNECCERR2</name>
<description>Bank 2 single correction error
flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBECCERR2</name>
<description>Bank 2 ECC double detection error
flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCEND2</name>
<description>Bank 2 CRC-complete flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>FLASH clear control register for bank
2</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLR_EOP2</name>
<description>Bank 1 EOP1 flag clear bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_WRPERR2</name>
<description>Bank 2 WRPERR1 flag clear
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_PGSERR2</name>
<description>Bank 2 PGSERR1 flag clear
bi</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_STRBERR2</name>
<description>Bank 2 STRBERR1 flag clear
bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_INCERR2</name>
<description>Bank 2 INCERR1 flag clear
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_OPERR2</name>
<description>Bank 2 OPERR1 flag clear
bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_RDPERR2</name>
<description>Bank 2 RDPERR1 flag clear
bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_RDSERR1</name>
<description>Bank 1 RDSERR1 flag clear
bit</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_SNECCERR2</name>
<description>Bank 2 SNECCERR1 flag clear
bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_DBECCERR1</name>
<description>Bank 1 DBECCERR1 flag clear
bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_CRCEND2</name>
<description>Bank 2 CRCEND1 flag clear
bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRAR_CUR2</name>
<displayName>PRAR_CUR2</displayName>
<description>FLASH protection address for bank
1</description>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROT_AREA_START2</name>
<description>Bank 2 lowest PCROP protected
address</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>PROT_AREA_END2</name>
<description>Bank 2 highest PCROP protected
address</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DMEP2</name>
<description>Bank 2 PCROP protected erase enable
option status bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRAR_PRG2</name>
<displayName>PRAR_PRG2</displayName>
<description>FLASH protection address for bank
2</description>
<alternateRegister>PRAR_PRG1</alternateRegister>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROT_AREA_START2</name>
<description>Bank 2 lowest PCROP protected address
configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>PROT_AREA_END2</name>
<description>Bank 2 highest PCROP protected address
configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>DMEP2</name>
<description>Bank 2 PCROP protected erase enable
option configuration bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPSN_CUR2R</name>
<displayName>WPSN_CUR2R</displayName>
<description>FLASH write sector protection for bank
2</description>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WRPSn2</name>
<description>Bank 2 sector write protection option
status byte</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPSN_PRG2R</name>
<displayName>WPSN_PRG2R</displayName>
<description>FLASH write sector protection for bank
2</description>
<addressOffset>0x13C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WRPSn2</name>
<description>Bank 2 sector write protection
configuration byte</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCCR2</name>
<displayName>CRCCR2</displayName>
<description>FLASH CRC control register for bank
1</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_SECT</name>
<description>Bank 2 CRC sector number</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ALL_BANK</name>
<description>Bank 2 CRC select bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_BY_SECT</name>
<description>Bank 2 CRC sector mode select
bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD_SECT</name>
<description>Bank 2 CRC sector select
bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLEAN_SECT</name>
<description>Bank 2 CRC sector list clear
bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START_CRC</name>
<description>Bank 2 CRC start bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLEAN_CRC</name>
<description>Bank 2 CRC clear bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_BURST</name>
<description>Bank 2 CRC burst size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCSADD2R</name>
<displayName>CRCSADD2R</displayName>
<description>FLASH CRC start address register for bank
2</description>
<addressOffset>0x154</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_START_ADDR</name>
<description>CRC start address on bank
2</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCEADD2R</name>
<displayName>CRCEADD2R</displayName>
<description>FLASH CRC end address register for bank
2</description>
<addressOffset>0x158</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRC_END_ADDR</name>
<description>CRC end address on bank 2</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECC_FA2R</name>
<displayName>ECC_FA2R</displayName>
<description>FLASH ECC fail address for bank
2</description>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FAIL_ECC_ADDR2</name>
<description>Bank 2 ECC error address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<description>GPIO</description>
<groupName>GPIO</groupName>
<baseAddress>0x58020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xABFFFFFF</resetValue>
<fields>
<field>
<name>MODE0</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE1</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE2</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE3</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE4</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE5</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE6</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE7</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE8</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE9</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE10</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE11</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE12</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE13</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE14</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE15</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O mode.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT15</name>
<description>Port x configuration bits (y = 0..15)
These bits are written by software to configure the
I/O output type.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0C000000</resetValue>
<fields>
<field>
<name>OSPEED0</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED1</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED2</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED3</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED4</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED5</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED6</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED7</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED8</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED9</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED10</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED11</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED12</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED13</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED14</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEED15</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O output speed. Note: Refer to the
device datasheet for the frequency specifications and
the power supply and load conditions for each
speed.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x12100000</resetValue>
<fields>
<field>
<name>PUPD0</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD1</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD2</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD3</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD4</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD5</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD6</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD7</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD8</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD9</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD10</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD11</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD12</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD13</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD14</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPD15</name>
<description>[1:0]: Port x configuration bits (y =
0..15) These bits are written by software to
configure the I/O pull-up or pull-down</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ID0</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID1</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID2</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID3</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID4</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID5</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID6</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID7</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID8</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID9</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID10</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID11</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID12</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID13</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID14</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ID15</name>
<description>Port input data bit (y = 0..15) These
bits are read-only. They contain the input value of
the corresponding I/O port.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OD0</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD1</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD2</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD3</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD4</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD5</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD6</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD7</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD8</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD9</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD10</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD11</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD12</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD13</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD14</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OD15</name>
<description>Port output data bit These bits can be
read and written by software. Note: For atomic bit
set/reset, the OD bits can be individually set and/or
reset by writing to the GPIOx_BSRR or GPIOx_BRR
registers (x = A..F).</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y= 0..15) These bits
are write-only. A read to these bits returns the
value 0x0000.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR15</name>
<description>Port x reset bit y (y = 0..15) These
bits are write-only. A read to these bits returns the
value 0x0000. Note: If both BSx and BRx are set, BSx
has priority.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>This register is used to lock the
configuration of the port bits when a correct write
sequence is applied to bit 16 (LCKK). The value of bits
[15:0] is used to lock the configuration of the GPIO.
During the write sequence, the value of LCKR[15:0] must
not change. When the LOCK sequence has been applied on a
port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.A
specific write sequence is used to write to the
GPIOx_LCKR register. Only word access (32-bit long) is
allowed during this locking sequence.Each lock bit
freezes a specific configuration register (control and
alternate function registers).</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y= 0..15) These bits
are read/write but can only be written when the LCKK
bit is 0.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCKK</name>
<description>Lock key This bit can be read any time.
It can only be modified using the lock key write
sequence. LOCK key write sequence: WR LCKR[16] = 1 +
LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] =
1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read
operation is optional but it confirms that the lock
is active) Note: During the LOCK key write sequence,
the value of LCK[15:0] must not change. Any error in
the lock sequence aborts the lock. After the first
lock sequence on any bit of the port, any read access
on the LCKK bit will return 1 until the next MCU
reset or peripheral reset.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL0</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 0..7) These bits are written by
software to configure alternate function I/Os AFSELy
selection:</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL1</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 0..7) These bits are written by
software to configure alternate function I/Os AFSELy
selection:</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL2</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 0..7) These bits are written by
software to configure alternate function I/Os AFSELy
selection:</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL3</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 0..7) These bits are written by
software to configure alternate function I/Os AFSELy
selection:</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL4</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 0..7) These bits are written by
software to configure alternate function I/Os AFSELy
selection:</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL5</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 0..7) These bits are written by
software to configure alternate function I/Os AFSELy
selection:</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL6</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 0..7) These bits are written by
software to configure alternate function I/Os AFSELy
selection:</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL7</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 0..7) These bits are written by
software to configure alternate function I/Os AFSELy
selection:</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL8</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 8..15) These bits are written by
software to configure alternate function
I/Os</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL9</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 8..15) These bits are written by
software to configure alternate function
I/Os</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL10</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 8..15) These bits are written by
software to configure alternate function
I/Os</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL11</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 8..15) These bits are written by
software to configure alternate function
I/Os</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL12</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 8..15) These bits are written by
software to configure alternate function
I/Os</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL13</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 8..15) These bits are written by
software to configure alternate function
I/Os</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL14</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 8..15) These bits are written by
software to configure alternate function
I/Os</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL15</name>
<description>[3:0]: Alternate function selection for
port x pin y (y = 8..15) These bits are written by
software to configure alternate function
I/Os</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOB</name>
<baseAddress>0x58020400</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOC</name>
<baseAddress>0x58020800</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOD</name>
<baseAddress>0x58020C00</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOE</name>
<baseAddress>0x58021000</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOF</name>
<baseAddress>0x58021400</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOG</name>
<baseAddress>0x58021800</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOH</name>
<baseAddress>0x58021C00</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOI</name>
<baseAddress>0x58022000</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOJ</name>
<baseAddress>0x58022400</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOA">
<name>GPIOK</name>
<baseAddress>0x58022800</baseAddress>
</peripheral>
<peripheral>
<name>HRTIM_Common</name>
<description>High Resolution Timer: Common
functions</description>
<groupName>HRTIM</groupName>
<baseAddress>0x40017780</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x80</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control Register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AD4USRC</name>
<description>ADC Trigger 4 Update
Source</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AD3USRC</name>
<description>ADC Trigger 3 Update
Source</description>
<bitOffset>22</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AD2USRC</name>
<description>ADC Trigger 2 Update
Source</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AD1USRC</name>
<description>ADC Trigger 1 Update
Source</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TEUDIS</name>
<description>Timer E Update Disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDUDIS</name>
<description>Timer D Update Disable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCUDIS</name>
<description>Timer C Update Disable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBUDIS</name>
<description>Timer B Update Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAUDIS</name>
<description>Timer A Update Disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUDIS</name>
<description>Master Update Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control Register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TERST</name>
<description>Timer E counter software
reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRST</name>
<description>Timer D counter software
reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCRST</name>
<description>Timer C counter software
reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBRST</name>
<description>Timer B counter software
reset</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TARST</name>
<description>Timer A counter software
reset</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRST</name>
<description>Master Counter software
reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TESWU</name>
<description>Timer E Software Update</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDSWU</name>
<description>Timer D Software Update</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCSWU</name>
<description>Timer C Software Update</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBSWU</name>
<description>Timer B Software Update</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TASWU</name>
<description>Timer A Software update</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSWU</name>
<description>Master Timer Software
update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt Status Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BMPER</name>
<description>Burst mode Period Interrupt
Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DLLRDY</name>
<description>DLL Ready Interrupt Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SYSFLT</name>
<description>System Fault Interrupt
Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FLT5</name>
<description>Fault 5 Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FLT4</name>
<description>Fault 4 Interrupt Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FLT3</name>
<description>Fault 3 Interrupt Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FLT2</name>
<description>Fault 2 Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FLT1</name>
<description>Fault 1 Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt Clear Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BMPERC</name>
<description>Burst mode period flag
Clear</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>DLLRDYC</name>
<description>DLL Ready Interrupt flag
Clear</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SYSFLTC</name>
<description>System Fault Interrupt Flag
Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FLT5C</name>
<description>Fault 5 Interrupt Flag
Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>FLT4C</name>
<description>Fault 4 Interrupt Flag
Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>FLT3C</name>
<description>Fault 3 Interrupt Flag
Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>FLT2C</name>
<description>Fault 2 Interrupt Flag
Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>FLT1C</name>
<description>Fault 1 Interrupt Flag
Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>Interrupt Enable Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BMPERIE</name>
<description>Burst mode period Interrupt
Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLLRDYIE</name>
<description>DLL Ready Interrupt Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSFLTE</name>
<description>System Fault Interrupt
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5IE</name>
<description>Fault 5 Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4IE</name>
<description>Fault 4 Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3IE</name>
<description>Fault 3 Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2IE</name>
<description>Fault 2 Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1IE</name>
<description>Fault 1 Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OENR</name>
<displayName>OENR</displayName>
<description>Output Enable Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TE2OEN</name>
<description>Timer E Output 2 Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1OEN</name>
<description>Timer E Output 1 Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD2OEN</name>
<description>Timer D Output 2 Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1OEN</name>
<description>Timer D Output 1 Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC2OEN</name>
<description>Timer C Output 2 Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1OEN</name>
<description>Timer C Output 1 Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB2OEN</name>
<description>Timer B Output 2 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1OEN</name>
<description>Timer B Output 1 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA2OEN</name>
<description>Timer A Output 2 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1OEN</name>
<description>Timer A Output 1 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DISR</name>
<displayName>DISR</displayName>
<description>DISR</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TE2ODIS</name>
<description>TE2ODIS</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1ODIS</name>
<description>TE1ODIS</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD2ODIS</name>
<description>TD2ODIS</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1ODIS</name>
<description>TD1ODIS</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC2ODIS</name>
<description>TC2ODIS</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1ODIS</name>
<description>TC1ODIS</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB2ODIS</name>
<description>TB2ODIS</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1ODIS</name>
<description>TB1ODIS</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA2ODIS</name>
<description>TA2ODIS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1ODIS</name>
<description>TA1ODIS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODSR</name>
<displayName>ODSR</displayName>
<description>Output Disable Status Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TE2ODS</name>
<description>Timer E Output 2 disable
status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1ODS</name>
<description>Timer E Output 1 disable
status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD2ODS</name>
<description>Timer D Output 2 disable
status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1ODS</name>
<description>Timer D Output 1 disable
status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC2ODS</name>
<description>Timer C Output 2 disable
status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1ODS</name>
<description>Timer C Output 1 disable
status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB2ODS</name>
<description>Timer B Output 2 disable
status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1ODS</name>
<description>Timer B Output 1 disable
status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA2ODS</name>
<description>Timer A Output 2 disable
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1ODS</name>
<description>Timer A Output 1 disable
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BMCR</name>
<displayName>BMCR</displayName>
<description>Burst Mode Control Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BMSTAT</name>
<description>Burst Mode Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEBM</name>
<description>Timer E Burst Mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDBM</name>
<description>Timer D Burst Mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBM</name>
<description>Timer C Burst Mode</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBBM</name>
<description>Timer B Burst Mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TABM</name>
<description>Timer A Burst Mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MTBM</name>
<description>Master Timer Burst Mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BMPREN</name>
<description>Burst Mode Preload Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BMPRSC</name>
<description>Burst Mode Prescaler</description>
<bitOffset>6</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BMCLK</name>
<description>Burst Mode Clock source</description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BMOM</name>
<description>Burst Mode operating mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BME</name>
<description>Burst Mode enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BMTRG</name>
<displayName>BMTRG</displayName>
<description>BMTRG</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OCHPEV</name>
<description>OCHPEV</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP2</name>
<description>TECMP2</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>TECMP1</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEREP</name>
<description>TEREP</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TERST</name>
<description>TERST</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP2</name>
<description>TDCMP2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>TDCMP1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDREP</name>
<description>TDREP</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDRST</name>
<description>TDRST</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>TCCMP2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>TCCMP1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCREP</name>
<description>TCREP</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCRST</name>
<description>TCRST</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>TBCMP2</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>TBCMP1</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBREP</name>
<description>TBREP</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBRST</name>
<description>TBRST</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>TACMP2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>TACMP1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAREP</name>
<description>TAREP</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TARST</name>
<description>TARST</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTREP</name>
<description>MSTREP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTRST</name>
<description>MSTRST</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW</name>
<description>SW</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BMCMPR6</name>
<displayName>BMCMPR6</displayName>
<description>BMCMPR6</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BMCMP</name>
<description>BMCMP</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BMPER</name>
<displayName>BMPER</displayName>
<description>Burst Mode Period Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BMPER</name>
<description>Burst mode Period</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>EECR1</name>
<displayName>EECR1</displayName>
<description>Timer External Event Control Register
1</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE5FAST</name>
<description>External Event 5 Fast mode</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE5SNS</name>
<description>External Event 5
Sensitivity</description>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE5POL</name>
<description>External Event 5 Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE5SRC</name>
<description>External Event 5 Source</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE4FAST</name>
<description>External Event 4 Fast mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE4SNS</name>
<description>External Event 4
Sensitivity</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE4POL</name>
<description>External Event 4 Polarity</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE4SRC</name>
<description>External Event 4 Source</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE3FAST</name>
<description>External Event 3 Fast mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE3SNS</name>
<description>External Event 3
Sensitivity</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE3POL</name>
<description>External Event 3 Polarity</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE3SRC</name>
<description>External Event 3 Source</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE2FAST</name>
<description>External Event 2 Fast mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE2SNS</name>
<description>External Event 2
Sensitivity</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE2POL</name>
<description>External Event 2 Polarity</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE2SRC</name>
<description>External Event 2 Source</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE1FAST</name>
<description>External Event 1 Fast mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE1SNS</name>
<description>External Event 1
Sensitivity</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE1POL</name>
<description>External Event 1 Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE1SRC</name>
<description>External Event 1 Source</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>EECR2</name>
<displayName>EECR2</displayName>
<description>Timer External Event Control Register
2</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE10SNS</name>
<description>External Event 10
Sensitivity</description>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE10POL</name>
<description>External Event 10 Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE10SRC</name>
<description>External Event 10 Source</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE9SNS</name>
<description>External Event 9
Sensitivity</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE9POL</name>
<description>External Event 9 Polarity</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE9SRC</name>
<description>External Event 9 Source</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE8SNS</name>
<description>External Event 8
Sensitivity</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE8POL</name>
<description>External Event 8 Polarity</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE8SRC</name>
<description>External Event 8 Source</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE7SNS</name>
<description>External Event 7
Sensitivity</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE7POL</name>
<description>External Event 7 Polarity</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE7SRC</name>
<description>External Event 7 Source</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE6SNS</name>
<description>External Event 6
Sensitivity</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE6POL</name>
<description>External Event 6 Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE6SRC</name>
<description>External Event 6 Source</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>EECR3</name>
<displayName>EECR3</displayName>
<description>Timer External Event Control Register
3</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE10SNS</name>
<description>EE10SNS</description>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE10POL</name>
<description>EE10POL</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE10SRC</name>
<description>EE10SRC</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE9SNS</name>
<description>EE9SNS</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE9POL</name>
<description>EE9POL</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE9SRC</name>
<description>EE9SRC</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE8SNS</name>
<description>EE8SNS</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE8POL</name>
<description>EE8POL</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE8SRC</name>
<description>EE8SRC</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE7SNS</name>
<description>EE7SNS</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE7POL</name>
<description>EE7POL</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE7SRC</name>
<description>EE7SRC</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE6SNS</name>
<description>EE6SNS</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EE6POL</name>
<description>EE6POL</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE6SRC</name>
<description>EE6SRC</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC1R</name>
<displayName>ADC1R</displayName>
<description>ADC Trigger 1 Register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AD1TEPER</name>
<description>ADC trigger 1 on Timer E
Period</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TEC4</name>
<description>ADC trigger 1 on Timer E compare
4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TEC3</name>
<description>ADC trigger 1 on Timer E compare
3</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TEC2</name>
<description>ADC trigger 1 on Timer E compare
2</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TDPER</name>
<description>ADC trigger 1 on Timer D
Period</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TDC4</name>
<description>ADC trigger 1 on Timer D compare
4</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TDC3</name>
<description>ADC trigger 1 on Timer D compare
3</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TDC2</name>
<description>ADC trigger 1 on Timer D compare
2</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TCPER</name>
<description>ADC trigger 1 on Timer C
Period</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TCC4</name>
<description>ADC trigger 1 on Timer C compare
4</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TCC3</name>
<description>ADC trigger 1 on Timer C compare
3</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TCC2</name>
<description>ADC trigger 1 on Timer C compare
2</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBRST</name>
<description>ADC trigger 1 on Timer B
Reset</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBPER</name>
<description>ADC trigger 1 on Timer B
Period</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBC4</name>
<description>ADC trigger 1 on Timer B compare
4</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBC3</name>
<description>ADC trigger 1 on Timer B compare
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBC2</name>
<description>ADC trigger 1 on Timer B compare
2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TARST</name>
<description>ADC trigger 1 on Timer A
Reset</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TAPER</name>
<description>ADC trigger 1 on Timer A
Period</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TAC4</name>
<description>ADC trigger 1 on Timer A compare
4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TAC3</name>
<description>ADC trigger 1 on Timer A compare
3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TAC2</name>
<description>ADC trigger 1 on Timer A compare
2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV5</name>
<description>ADC trigger 1 on External Event
5</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV4</name>
<description>ADC trigger 1 on External Event
4</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV3</name>
<description>ADC trigger 1 on External Event
3</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV2</name>
<description>ADC trigger 1 on External Event
2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV1</name>
<description>ADC trigger 1 on External Event
1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MPER</name>
<description>ADC trigger 1 on Master
Period</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MC4</name>
<description>ADC trigger 1 on Master Compare
4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MC3</name>
<description>ADC trigger 1 on Master Compare
3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MC2</name>
<description>ADC trigger 1 on Master Compare
2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MC1</name>
<description>ADC trigger 1 on Master Compare
1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC2R</name>
<displayName>ADC2R</displayName>
<description>ADC Trigger 2 Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AD2TERST</name>
<description>ADC trigger 2 on Timer E
Reset</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TEC4</name>
<description>ADC trigger 2 on Timer E compare
4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TEC3</name>
<description>ADC trigger 2 on Timer E compare
3</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TEC2</name>
<description>ADC trigger 2 on Timer E compare
2</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDRST</name>
<description>ADC trigger 2 on Timer D
Reset</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDPER</name>
<description>ADC trigger 2 on Timer D
Period</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDC4</name>
<description>ADC trigger 2 on Timer D compare
4</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDC3</name>
<description>ADC trigger 2 on Timer D compare
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDC2</name>
<description>ADC trigger 2 on Timer D compare
2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCRST</name>
<description>ADC trigger 2 on Timer C
Reset</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCPER</name>
<description>ADC trigger 2 on Timer C
Period</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCC4</name>
<description>ADC trigger 2 on Timer C compare
4</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCC3</name>
<description>ADC trigger 2 on Timer C compare
3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCC2</name>
<description>ADC trigger 2 on Timer C compare
2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TBPER</name>
<description>ADC trigger 2 on Timer B
Period</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TBC4</name>
<description>ADC trigger 2 on Timer B compare
4</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TBC3</name>
<description>ADC trigger 2 on Timer B compare
3</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TBC2</name>
<description>ADC trigger 2 on Timer B compare
2</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TAPER</name>
<description>ADC trigger 2 on Timer A
Period</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TAC4</name>
<description>ADC trigger 2 on Timer A compare
4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TAC3</name>
<description>ADC trigger 2 on Timer A compare
3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TAC2</name>
<description>ADC trigger 2 on Timer A compare
2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV10</name>
<description>ADC trigger 2 on External Event
10</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV9</name>
<description>ADC trigger 2 on External Event
9</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV8</name>
<description>ADC trigger 2 on External Event
8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV7</name>
<description>ADC trigger 2 on External Event
7</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV6</name>
<description>ADC trigger 2 on External Event
6</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MPER</name>
<description>ADC trigger 2 on Master
Period</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MC4</name>
<description>ADC trigger 2 on Master Compare
4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MC3</name>
<description>ADC trigger 2 on Master Compare
3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MC2</name>
<description>ADC trigger 2 on Master Compare
2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MC1</name>
<description>ADC trigger 2 on Master Compare
1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC3R</name>
<displayName>ADC3R</displayName>
<description>ADC Trigger 3 Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AD1TEPER</name>
<description>AD1TEPER</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TEC4</name>
<description>AD1TEC4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TEC3</name>
<description>AD1TEC3</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TEC2</name>
<description>AD1TEC2</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TDPER</name>
<description>AD1TDPER</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TDC4</name>
<description>AD1TDC4</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TDC3</name>
<description>AD1TDC3</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TDC2</name>
<description>AD1TDC2</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TCPER</name>
<description>AD1TCPER</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TCC4</name>
<description>AD1TCC4</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TCC3</name>
<description>AD1TCC3</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TCC2</name>
<description>AD1TCC2</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBRST</name>
<description>AD1TBRST</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBPER</name>
<description>AD1TBPER</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBC4</name>
<description>AD1TBC4</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBC3</name>
<description>AD1TBC3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TBC2</name>
<description>AD1TBC2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TARST</name>
<description>AD1TARST</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TAPER</name>
<description>AD1TAPER</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TAC4</name>
<description>AD1TAC4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TAC3</name>
<description>AD1TAC3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1TAC2</name>
<description>AD1TAC2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV5</name>
<description>AD1EEV5</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV4</name>
<description>AD1EEV4</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV3</name>
<description>AD1EEV3</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV2</name>
<description>AD1EEV2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1EEV1</name>
<description>AD1EEV1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MPER</name>
<description>AD1MPER</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MC4</name>
<description>AD1MC4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MC3</name>
<description>AD1MC3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MC2</name>
<description>AD1MC2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD1MC1</name>
<description>AD1MC1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC4R</name>
<displayName>ADC4R</displayName>
<description>ADC Trigger 4 Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AD2TERST</name>
<description>AD2TERST</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TEC4</name>
<description>AD2TEC4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TEC3</name>
<description>AD2TEC3</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TEC2</name>
<description>AD2TEC2</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDRST</name>
<description>AD2TDRST</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDPER</name>
<description>AD2TDPER</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDC4</name>
<description>AD2TDC4</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDC3</name>
<description>AD2TDC3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TDC2</name>
<description>AD2TDC2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCRST</name>
<description>AD2TCRST</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCPER</name>
<description>AD2TCPER</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCC4</name>
<description>AD2TCC4</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCC3</name>
<description>AD2TCC3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TCC2</name>
<description>AD2TCC2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TBPER</name>
<description>AD2TBPER</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TBC4</name>
<description>AD2TBC4</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TBC3</name>
<description>AD2TBC3</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TBC2</name>
<description>AD2TBC2</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TAPER</name>
<description>AD2TAPER</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TAC4</name>
<description>AD2TAC4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TAC3</name>
<description>AD2TAC3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2TAC2</name>
<description>AD2TAC2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV10</name>
<description>AD2EEV10</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV9</name>
<description>AD2EEV9</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV8</name>
<description>AD2EEV8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV7</name>
<description>AD2EEV7</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2EEV6</name>
<description>AD2EEV6</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MPER</name>
<description>AD2MPER</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MC4</name>
<description>AD2MC4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MC3</name>
<description>AD2MC3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MC2</name>
<description>AD2MC2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AD2MC1</name>
<description>AD2MC1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DLLCR</name>
<displayName>DLLCR</displayName>
<description>DLL Control Register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALRTE</name>
<description>DLL Calibration rate</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CALEN</name>
<description>DLL Calibration Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAL</name>
<description>DLL Calibration Start</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLTINR1</name>
<displayName>FLTINR1</displayName>
<description>HRTIM Fault Input Register 1</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLT4LCK</name>
<description>FLT4LCK</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4F</name>
<description>FLT4F</description>
<bitOffset>27</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FLT4SRC</name>
<description>FLT4SRC</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4P</name>
<description>FLT4P</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4E</name>
<description>FLT4E</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3LCK</name>
<description>FLT3LCK</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3F</name>
<description>FLT3F</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FLT3SRC</name>
<description>FLT3SRC</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3P</name>
<description>FLT3P</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3E</name>
<description>FLT3E</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2LCK</name>
<description>FLT2LCK</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2F</name>
<description>FLT2F</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FLT2SRC</name>
<description>FLT2SRC</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2P</name>
<description>FLT2P</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2E</name>
<description>FLT2E</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1LCK</name>
<description>FLT1LCK</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1F</name>
<description>FLT1F</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FLT1SRC</name>
<description>FLT1SRC</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1P</name>
<description>FLT1P</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1E</name>
<description>FLT1E</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLTINR2</name>
<displayName>FLTINR2</displayName>
<description>HRTIM Fault Input Register 2</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLTSD</name>
<description>FLTSD</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FLT5LCK</name>
<description>FLT5LCK</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5F</name>
<description>FLT5F</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FLT5SRC</name>
<description>FLT5SRC</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5P</name>
<description>FLT5P</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5E</name>
<description>FLT5E</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDMUPDR</name>
<displayName>BDMUPDR</displayName>
<description>BDMUPDR</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCMP4</name>
<description>MCMP4</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP3</name>
<description>MCMP3</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP2</name>
<description>MCMP2</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP1</name>
<description>MCMP1</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MREP</name>
<description>MREP</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MPER</name>
<description>MPER</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>MCNT</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MDIER</name>
<description>MDIER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MICR</name>
<description>MICR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCR</name>
<description>MCR</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTxUPR</name>
<displayName>BDTxUPR</displayName>
<description>Burst DMA Timerx update
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMxFLTR</name>
<description>HRTIM_FLTxR register update
enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxOUTR</name>
<description>HRTIM_OUTxR register update
enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxCHPR</name>
<description>HRTIM_CHPxR register update
enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxRSTR</name>
<description>HRTIM_RSTxR register update
enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxEEFR2</name>
<description>HRTIM_EEFxR2 register update
enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxEEFR1</name>
<description>HRTIM_EEFxR1 register update
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxRST2R</name>
<description>HRTIM_RST2xR register update
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxSET2R</name>
<description>HRTIM_SET2xR register update
enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxRST1R</name>
<description>HRTIM_RST1xR register update
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxSET1R</name>
<description>HRTIM_SET1xR register update
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMx_DTxR</name>
<description>HRTIM_DTxR register update
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxCMP4</name>
<description>HRTIM_CMP4xR register update
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxCMP3</name>
<description>HRTIM_CMP3xR register update
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxCMP2</name>
<description>HRTIM_CMP2xR register update
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxCMP1</name>
<description>HRTIM_CMP1xR register update
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxREP</name>
<description>HRTIM_REPxR register update
enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxPER</name>
<description>HRTIM_PERxR register update
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxCNT</name>
<description>HRTIM_CNTxR register update
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxDIER</name>
<description>HRTIM_TIMxDIER register update
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxICR</name>
<description>HRTIM_TIMxICR register update
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMxCR</name>
<description>HRTIM_TIMxCR register update
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDMADR</name>
<displayName>BDMADR</displayName>
<description>Burst DMA Data Register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BDMADR</name>
<description>Burst DMA Data register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HRTIM_Master</name>
<description>High Resolution Timer: Master Timers</description>
<groupName>HRTIM</groupName>
<baseAddress>0x40017400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x80</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MCR</name>
<displayName>MCR</displayName>
<description>Master Timer Control Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BRSTDMA</name>
<description>Burst DMA Update</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MREPU</name>
<description>Master Timer Repetition
update</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PREEN</name>
<description>Preload enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACSYNC</name>
<description>AC Synchronization</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TECEN</name>
<description>Timer E counter enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCEN</name>
<description>Timer D counter enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCEN</name>
<description>Timer C counter enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCEN</name>
<description>Timer B counter enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACEN</name>
<description>Timer A counter enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCEN</name>
<description>Master Counter enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNC_SRC</name>
<description>Synchronization source</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNC_OUT</name>
<description>Synchronization output</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCSTRTM</name>
<description>Synchronization Starts
Master</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCRSTM</name>
<description>Synchronization Resets
Master</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNC_IN</name>
<description>ynchronization input</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HALF</name>
<description>Half mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETRIG</name>
<description>Master Re-triggerable mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>Master Continuous mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_PSC</name>
<description>HRTIM Master Clock
prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>MISR</name>
<displayName>MISR</displayName>
<description>Master Timer Interrupt Status
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MUPD</name>
<description>Master Update Interrupt
Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNC</name>
<description>Sync Input Interrupt Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MREP</name>
<description>Master Repetition Interrupt
Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP4</name>
<description>Master Compare 4 Interrupt
Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP3</name>
<description>Master Compare 3 Interrupt
Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP2</name>
<description>Master Compare 2 Interrupt
Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP1</name>
<description>Master Compare 1 Interrupt
Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MICR</name>
<displayName>MICR</displayName>
<description>Master Timer Interrupt Clear
Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MUPDC</name>
<description>Master update Interrupt flag
clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCC</name>
<description>Sync Input Interrupt flag
clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MREPC</name>
<description>Repetition Interrupt flag
clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP4C</name>
<description>Master Compare 4 Interrupt flag
clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP3C</name>
<description>Master Compare 3 Interrupt flag
clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP2C</name>
<description>Master Compare 2 Interrupt flag
clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP1C</name>
<description>Master Compare 1 Interrupt flag
clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIER4</name>
<displayName>MDIER4</displayName>
<description>MDIER4</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MUPDDE</name>
<description>MUPDDE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCDE</name>
<description>SYNCDE</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MREPDE</name>
<description>MREPDE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP4DE</name>
<description>MCMP4DE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP3DE</name>
<description>MCMP3DE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP2DE</name>
<description>MCMP2DE</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP1DE</name>
<description>MCMP1DE</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUPDIE</name>
<description>MUPDIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCIE</name>
<description>SYNCIE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MREPIE</name>
<description>MREPIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP4IE</name>
<description>MCMP4IE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP3IE</name>
<description>MCMP3IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP2IE</name>
<description>MCMP2IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCMP1IE</name>
<description>MCMP1IE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCNTR</name>
<displayName>MCNTR</displayName>
<description>Master Timer Counter Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPER</name>
<displayName>MPER</displayName>
<description>Master Timer Period Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>MPER</name>
<description>Master Timer Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MREP</name>
<displayName>MREP</displayName>
<description>Master Timer Repetition
Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MREP</name>
<description>Master Timer Repetition counter
value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCMP1R</name>
<displayName>MCMP1R</displayName>
<description>Master Timer Compare 1
Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCMP1</name>
<description>Master Timer Compare 1
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCMP2R</name>
<displayName>MCMP2R</displayName>
<description>Master Timer Compare 2
Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCMP2</name>
<description>Master Timer Compare 2
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCMP3R</name>
<displayName>MCMP3R</displayName>
<description>Master Timer Compare 3
Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCMP3</name>
<description>Master Timer Compare 3
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCMP4R</name>
<displayName>MCMP4R</displayName>
<description>Master Timer Compare 4
Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCMP4</name>
<description>Master Timer Compare 4
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HRTIM_TIMA</name>
<description>High Resolution Timer: TIMA</description>
<groupName>HRTIM</groupName>
<baseAddress>0x40017480</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x80</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA2_STR0</name>
<description>DMA2 Stream0 interrupt</description>
<value>56</value>
</interrupt>
<interrupt>
<name>DMA2_STR1</name>
<description>DMA2 Stream1 interrupt</description>
<value>57</value>
</interrupt>
<interrupt>
<name>DMA2_STR2</name>
<description>DMA2 Stream2 interrupt</description>
<value>58</value>
</interrupt>
<interrupt>
<name>DMA2_STR3</name>
<description>DMA2 Stream3 interrupt</description>
<value>59</value>
</interrupt>
<interrupt>
<name>DMA2_STR4</name>
<description>DMA2 Stream4 interrupt</description>
<value>60</value>
</interrupt>
<interrupt>
<name>DMA2_STR5</name>
<description>DMA2 Stream5 interrupt</description>
<value>68</value>
</interrupt>
<interrupt>
<name>DMA2_STR6</name>
<description>DMA2 Stream6 interrupt</description>
<value>69</value>
</interrupt>
<interrupt>
<name>DMA2_STR7</name>
<description>DMA2 Stream7 interrupt</description>
<value>70</value>
</interrupt>
<registers>
<register>
<name>TIMACR</name>
<displayName>TIMACR</displayName>
<description>Timerx Control Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDGAT</name>
<description>Update Gating</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PREEN</name>
<description>Preload enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACSYNC</name>
<description>AC Synchronization</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSTU</name>
<description>Master Timer update</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEU</name>
<description>TEU</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDU</name>
<description>TDU</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCU</name>
<description>TCU</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBU</name>
<description>TBU</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxRSTU</name>
<description>Timerx reset update</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxREPU</name>
<description>Timer x Repetition update</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DELCMP4</name>
<description>Delayed CMP4 mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DELCMP2</name>
<description>Delayed CMP2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCSTRTx</name>
<description>Synchronization Starts Timer
x</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCRSTx</name>
<description>Synchronization Resets Timer
x</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSHPLL</name>
<description>Push-Pull mode enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALF</name>
<description>Half mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETRIG</name>
<description>Re-triggerable mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>Continuous mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_PSCx</name>
<description>HRTIM Timer x Clock
prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMAISR</name>
<displayName>TIMAISR</displayName>
<description>Timerx Interrupt Status
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>O2STAT</name>
<description>Output 2 State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>O1STAT</name>
<description>Output 1 State</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPPSTAT</name>
<description>Idle Push Pull Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPPSTAT</name>
<description>Current Push Pull Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection Flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST</name>
<description>Reset Interrupt Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2</name>
<description>Output 2 Reset Interrupt
Flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2</name>
<description>Output 2 Set Interrupt
Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1</name>
<description>Output 1 Reset Interrupt
Flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx1</name>
<description>Output 1 Set Interrupt
Flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2</name>
<description>Capture2 Interrupt Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1</name>
<description>Capture1 Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPD</name>
<description>Update Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REP</name>
<description>Repetition Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Compare 4 Interrupt Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Compare 3 Interrupt Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Compare 2 Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Compare 1 Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMAICR</name>
<displayName>TIMAICR</displayName>
<description>Timerx Interrupt Clear
Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTC</name>
<description>Delayed Protection Flag
Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTC</name>
<description>Reset Interrupt flag Clear</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2C</name>
<description>Output 2 Reset flag Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET2xC</name>
<description>Output 2 Set flag Clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1C</name>
<description>Output 1 Reset flag Clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xC</name>
<description>Output 1 Set flag Clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2C</name>
<description>Capture2 Interrupt flag
Clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1C</name>
<description>Capture1 Interrupt flag
Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDC</name>
<description>Update Interrupt flag
Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPC</name>
<description>Repetition Interrupt flag
Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4C</name>
<description>Compare 4 Interrupt flag
Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3C</name>
<description>Compare 3 Interrupt flag
Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2C</name>
<description>Compare 2 Interrupt flag
Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1C</name>
<description>Compare 1 Interrupt flag
Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMADIER5</name>
<displayName>TIMADIER5</displayName>
<description>TIMxDIER5</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTDE</name>
<description>DLYPRTDE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDE</name>
<description>RSTDE</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2DE</name>
<description>RSTx2DE</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2DE</name>
<description>SETx2DE</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1DE</name>
<description>RSTx1DE</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xDE</name>
<description>SET1xDE</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2DE</name>
<description>CPT2DE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1DE</name>
<description>CPT1DE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDDE</name>
<description>UPDDE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPDE</name>
<description>REPDE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4DE</name>
<description>CMP4DE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3DE</name>
<description>CMP3DE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2DE</name>
<description>CMP2DE</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1DE</name>
<description>CMP1DE</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRTIE</name>
<description>DLYPRTIE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIE</name>
<description>RSTIE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2IE</name>
<description>RSTx2IE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2IE</name>
<description>SETx2IE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1IE</name>
<description>RSTx1IE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xIE</name>
<description>SET1xIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2IE</name>
<description>CPT2IE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1IE</name>
<description>CPT1IE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDIE</name>
<description>UPDIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPIE</name>
<description>REPIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4IE</name>
<description>CMP4IE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3IE</name>
<description>CMP3IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2IE</name>
<description>CMP2IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1IE</name>
<description>CMP1IE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNTAR</name>
<displayName>CNTAR</displayName>
<description>Timerx Counter Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNTx</name>
<description>Timerx Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERAR</name>
<displayName>PERAR</displayName>
<description>Timerx Period Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>PERx</name>
<description>Timerx Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>REPAR</name>
<displayName>REPAR</displayName>
<description>Timerx Repetition Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition counter
value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1AR</name>
<displayName>CMP1AR</displayName>
<description>Timerx Compare 1 Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1CAR</name>
<displayName>CMP1CAR</displayName>
<description>Timerx Compare 1 Compound
Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition value (aliased from
HRTIM_REPx register)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP2AR</name>
<displayName>CMP2AR</displayName>
<description>Timerx Compare 2 Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP2x</name>
<description>Timerx Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP3AR</name>
<displayName>CMP3AR</displayName>
<description>Timerx Compare 3 Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP3x</name>
<description>Timerx Compare 3 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP4AR</name>
<displayName>CMP4AR</displayName>
<description>Timerx Compare 4 Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP4x</name>
<description>Timerx Compare 4 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1AR</name>
<displayName>CPT1AR</displayName>
<description>Timerx Capture 1 Register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT1x</name>
<description>Timerx Capture 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2AR</name>
<displayName>CPT2AR</displayName>
<description>Timerx Capture 2 Register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT2x</name>
<description>Timerx Capture 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTAR</name>
<displayName>DTAR</displayName>
<description>Timerx Deadtime Register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTFLKx</name>
<description>Deadtime Falling Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFSLKx</name>
<description>Deadtime Falling Sign Lock</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDTFx</name>
<description>Sign Deadtime Falling
value</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFx</name>
<description>Deadtime Falling value</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>DTRLKx</name>
<description>Deadtime Rising Lock</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRSLKx</name>
<description>Deadtime Rising Sign Lock</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTPRSC</name>
<description>Deadtime Prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SDTRx</name>
<description>Sign Deadtime Rising value</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRx</name>
<description>Deadtime Rising value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETA1R</name>
<displayName>SETA1R</displayName>
<description>Timerx Output1 Set Register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>Registers update (transfer preload to
active)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>Timer Event 9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>Timer Event 8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>Timer Event 7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>Timer Event 6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>Timer Event 5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>Timer Event 4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>Timer Event 3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>Timer Event 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>Timer Event 1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master Compare 4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master Compare 3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master Compare 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master Compare 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master Period</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Timer A compare 3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Timer A compare 1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Timer A Period</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>Timer A resynchronizaton</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>Software Set trigger</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTA1R</name>
<displayName>RSTA1R</displayName>
<description>Timerx Output1 Reset Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETA2R</name>
<displayName>SETA2R</displayName>
<description>Timerx Output2 Set Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>SST</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTA2R</name>
<displayName>RSTA2R</displayName>
<description>Timerx Output2 Reset Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFAR1</name>
<displayName>EEFAR1</displayName>
<description>Timerx External Event Filtering Register
1</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE5FLTR</name>
<description>External Event 5 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE5LTCH</name>
<description>External Event 5 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE4FLTR</name>
<description>External Event 4 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE4LTCH</name>
<description>External Event 4 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE3FLTR</name>
<description>External Event 3 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE3LTCH</name>
<description>External Event 3 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE2FLTR</name>
<description>External Event 2 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE2LTCH</name>
<description>External Event 2 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE1FLTR</name>
<description>External Event 1 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE1LTCH</name>
<description>External Event 1 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFAR2</name>
<displayName>EEFAR2</displayName>
<description>Timerx External Event Filtering Register
2</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE10FLTR</name>
<description>External Event 10 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE10LTCH</name>
<description>External Event 10 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE9FLTR</name>
<description>External Event 9 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE9LTCH</name>
<description>External Event 9 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE8FLTR</name>
<description>External Event 8 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE8LTCH</name>
<description>External Event 8 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE7FLTR</name>
<description>External Event 7 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE7LTCH</name>
<description>External Event 7 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE6FLTR</name>
<description>External Event 6 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE6LTCH</name>
<description>External Event 6 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTAR</name>
<displayName>RSTAR</displayName>
<description>TimerA Reset Register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMECMP4</name>
<description>Timer E Compare 4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP4</name>
<description>Timer D Compare 4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP4</name>
<description>Timer C Compare 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP4</name>
<description>Timer B Compare 4</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master compare 4</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master compare 3</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master compare 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master compare 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master timer Period</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4 reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2 reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDT</name>
<description>Timer A Update reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHPAR</name>
<displayName>CHPAR</displayName>
<description>Timerx Chopper Register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRTPW</name>
<description>STRTPW</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CHPDTY</name>
<description>Timerx chopper duty cycle
value</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHPFRQ</name>
<description>Timerx carrier frequency
value</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1ACR</name>
<displayName>CPT1ACR</displayName>
<description>Timerx Capture 2 Control
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1RST</name>
<description>Timer E output 1 Reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1SET</name>
<description>Timer E output 1 Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1RST</name>
<description>Timer D output 1 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1SET</name>
<description>Timer D output 1 Set</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1RST</name>
<description>Timer C output 1 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1SET</name>
<description>Timer C output 1 Set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1RST</name>
<description>Timer B output 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1SET</name>
<description>Timer B output 1 Set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2ACR</name>
<displayName>CPT2ACR</displayName>
<description>CPT2xCR</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1RST</name>
<description>Timer E output 1 Reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1SET</name>
<description>Timer E output 1 Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1RST</name>
<description>Timer D output 1 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1SET</name>
<description>Timer D output 1 Set</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1RST</name>
<description>Timer C output 1 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1SET</name>
<description>Timer C output 1 Set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1RST</name>
<description>Timer B output 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1SET</name>
<description>Timer B output 1 Set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTAR</name>
<displayName>OUTAR</displayName>
<description>Timerx Output Register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIDL2</name>
<description>Output 2 Deadtime upon burst mode Idle
entry</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP2</name>
<description>Output 2 Chopper enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2</name>
<description>Output 2 Fault state</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES2</name>
<description>Output 2 Idle State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM2</name>
<description>Output 2 Idle mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL2</name>
<description>Output 2 polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYPRTEN</name>
<description>Delayed Protection Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTEN</name>
<description>Deadtime enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIDL1</name>
<description>Output 1 Deadtime upon burst mode Idle
entry</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP1</name>
<description>Output 1 Chopper enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1</name>
<description>Output 1 Fault state</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES1</name>
<description>Output 1 Idle State</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM1</name>
<description>Output 1 Idle mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL1</name>
<description>Output 1 polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLTAR</name>
<displayName>FLTAR</displayName>
<description>Timerx Fault Register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLTLCK</name>
<description>Fault sources Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5EN</name>
<description>Fault 5 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4EN</name>
<description>Fault 4 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3EN</name>
<description>Fault 3 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2EN</name>
<description>Fault 2 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1EN</name>
<description>Fault 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HRTIM_TIMB</name>
<description>High Resolution Timer: TIMB</description>
<groupName>HRTIM</groupName>
<baseAddress>0x40017500</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x80</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TIMBCR</name>
<displayName>TIMBCR</displayName>
<description>Timerx Control Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDGAT</name>
<description>Update Gating</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PREEN</name>
<description>Preload enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACSYNC</name>
<description>AC Synchronization</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSTU</name>
<description>Master Timer update</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEU</name>
<description>TEU</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDU</name>
<description>TDU</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCU</name>
<description>TCU</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBU</name>
<description>TBU</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxRSTU</name>
<description>Timerx reset update</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxREPU</name>
<description>Timer x Repetition update</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DELCMP4</name>
<description>Delayed CMP4 mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DELCMP2</name>
<description>Delayed CMP2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCSTRTx</name>
<description>Synchronization Starts Timer
x</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCRSTx</name>
<description>Synchronization Resets Timer
x</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSHPLL</name>
<description>Push-Pull mode enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALF</name>
<description>Half mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETRIG</name>
<description>Re-triggerable mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>Continuous mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_PSCx</name>
<description>HRTIM Timer x Clock
prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMBISR</name>
<displayName>TIMBISR</displayName>
<description>Timerx Interrupt Status
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>O2STAT</name>
<description>Output 2 State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>O1STAT</name>
<description>Output 1 State</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPPSTAT</name>
<description>Idle Push Pull Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPPSTAT</name>
<description>Current Push Pull Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection Flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST</name>
<description>Reset Interrupt Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2</name>
<description>Output 2 Reset Interrupt
Flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2</name>
<description>Output 2 Set Interrupt
Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1</name>
<description>Output 1 Reset Interrupt
Flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx1</name>
<description>Output 1 Set Interrupt
Flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2</name>
<description>Capture2 Interrupt Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1</name>
<description>Capture1 Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPD</name>
<description>Update Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REP</name>
<description>Repetition Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Compare 4 Interrupt Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Compare 3 Interrupt Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Compare 2 Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Compare 1 Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMBICR</name>
<displayName>TIMBICR</displayName>
<description>Timerx Interrupt Clear
Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTC</name>
<description>Delayed Protection Flag
Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTC</name>
<description>Reset Interrupt flag Clear</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2C</name>
<description>Output 2 Reset flag Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET2xC</name>
<description>Output 2 Set flag Clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1C</name>
<description>Output 1 Reset flag Clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xC</name>
<description>Output 1 Set flag Clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2C</name>
<description>Capture2 Interrupt flag
Clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1C</name>
<description>Capture1 Interrupt flag
Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDC</name>
<description>Update Interrupt flag
Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPC</name>
<description>Repetition Interrupt flag
Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4C</name>
<description>Compare 4 Interrupt flag
Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3C</name>
<description>Compare 3 Interrupt flag
Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2C</name>
<description>Compare 2 Interrupt flag
Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1C</name>
<description>Compare 1 Interrupt flag
Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMBDIER5</name>
<displayName>TIMBDIER5</displayName>
<description>TIMxDIER5</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTDE</name>
<description>DLYPRTDE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDE</name>
<description>RSTDE</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2DE</name>
<description>RSTx2DE</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2DE</name>
<description>SETx2DE</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1DE</name>
<description>RSTx1DE</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xDE</name>
<description>SET1xDE</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2DE</name>
<description>CPT2DE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1DE</name>
<description>CPT1DE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDDE</name>
<description>UPDDE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPDE</name>
<description>REPDE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4DE</name>
<description>CMP4DE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3DE</name>
<description>CMP3DE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2DE</name>
<description>CMP2DE</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1DE</name>
<description>CMP1DE</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRTIE</name>
<description>DLYPRTIE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIE</name>
<description>RSTIE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2IE</name>
<description>RSTx2IE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2IE</name>
<description>SETx2IE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1IE</name>
<description>RSTx1IE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xIE</name>
<description>SET1xIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2IE</name>
<description>CPT2IE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1IE</name>
<description>CPT1IE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDIE</name>
<description>UPDIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPIE</name>
<description>REPIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4IE</name>
<description>CMP4IE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3IE</name>
<description>CMP3IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2IE</name>
<description>CMP2IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1IE</name>
<description>CMP1IE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNTR</name>
<displayName>CNTR</displayName>
<description>Timerx Counter Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNTx</name>
<description>Timerx Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERBR</name>
<displayName>PERBR</displayName>
<description>Timerx Period Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>PERx</name>
<description>Timerx Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>REPBR</name>
<displayName>REPBR</displayName>
<description>Timerx Repetition Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition counter
value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1BR</name>
<displayName>CMP1BR</displayName>
<description>Timerx Compare 1 Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1CBR</name>
<displayName>CMP1CBR</displayName>
<description>Timerx Compare 1 Compound
Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition value (aliased from
HRTIM_REPx register)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP2BR</name>
<displayName>CMP2BR</displayName>
<description>Timerx Compare 2 Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP2x</name>
<description>Timerx Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP3BR</name>
<displayName>CMP3BR</displayName>
<description>Timerx Compare 3 Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP3x</name>
<description>Timerx Compare 3 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP4BR</name>
<displayName>CMP4BR</displayName>
<description>Timerx Compare 4 Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP4x</name>
<description>Timerx Compare 4 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1BR</name>
<displayName>CPT1BR</displayName>
<description>Timerx Capture 1 Register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT1x</name>
<description>Timerx Capture 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2BR</name>
<displayName>CPT2BR</displayName>
<description>Timerx Capture 2 Register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT2x</name>
<description>Timerx Capture 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTBR</name>
<displayName>DTBR</displayName>
<description>Timerx Deadtime Register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTFLKx</name>
<description>Deadtime Falling Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFSLKx</name>
<description>Deadtime Falling Sign Lock</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDTFx</name>
<description>Sign Deadtime Falling
value</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFx</name>
<description>Deadtime Falling value</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>DTRLKx</name>
<description>Deadtime Rising Lock</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRSLKx</name>
<description>Deadtime Rising Sign Lock</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTPRSC</name>
<description>Deadtime Prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SDTRx</name>
<description>Sign Deadtime Rising value</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRx</name>
<description>Deadtime Rising value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETB1R</name>
<displayName>SETB1R</displayName>
<description>Timerx Output1 Set Register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>Registers update (transfer preload to
active)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>Timer Event 9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>Timer Event 8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>Timer Event 7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>Timer Event 6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>Timer Event 5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>Timer Event 4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>Timer Event 3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>Timer Event 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>Timer Event 1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master Compare 4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master Compare 3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master Compare 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master Compare 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master Period</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Timer A compare 3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Timer A compare 1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Timer A Period</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>Timer A resynchronizaton</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>Software Set trigger</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTB1R</name>
<displayName>RSTB1R</displayName>
<description>Timerx Output1 Reset Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETB2R</name>
<displayName>SETB2R</displayName>
<description>Timerx Output2 Set Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>SST</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTB2R</name>
<displayName>RSTB2R</displayName>
<description>Timerx Output2 Reset Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFBR1</name>
<displayName>EEFBR1</displayName>
<description>Timerx External Event Filtering Register
1</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE5FLTR</name>
<description>External Event 5 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE5LTCH</name>
<description>External Event 5 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE4FLTR</name>
<description>External Event 4 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE4LTCH</name>
<description>External Event 4 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE3FLTR</name>
<description>External Event 3 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE3LTCH</name>
<description>External Event 3 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE2FLTR</name>
<description>External Event 2 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE2LTCH</name>
<description>External Event 2 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE1FLTR</name>
<description>External Event 1 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE1LTCH</name>
<description>External Event 1 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFBR2</name>
<displayName>EEFBR2</displayName>
<description>Timerx External Event Filtering Register
2</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE10FLTR</name>
<description>External Event 10 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE10LTCH</name>
<description>External Event 10 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE9FLTR</name>
<description>External Event 9 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE9LTCH</name>
<description>External Event 9 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE8FLTR</name>
<description>External Event 8 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE8LTCH</name>
<description>External Event 8 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE7FLTR</name>
<description>External Event 7 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE7LTCH</name>
<description>External Event 7 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE6FLTR</name>
<description>External Event 6 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE6LTCH</name>
<description>External Event 6 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTBR</name>
<displayName>RSTBR</displayName>
<description>TimerA Reset Register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMECMP4</name>
<description>Timer E Compare 4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP4</name>
<description>Timer D Compare 4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP4</name>
<description>Timer C Compare 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP4</name>
<description>Timer A Compare 4</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master compare 4</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master compare 3</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master compare 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master compare 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master timer Period</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4 reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2 reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDT</name>
<description>Timer A Update reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHPBR</name>
<displayName>CHPBR</displayName>
<description>Timerx Chopper Register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRTPW</name>
<description>STRTPW</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CHPDTY</name>
<description>Timerx chopper duty cycle
value</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHPFRQ</name>
<description>Timerx carrier frequency
value</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1BCR</name>
<displayName>CPT1BCR</displayName>
<description>Timerx Capture 2 Control
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1RST</name>
<description>Timer E output 1 Reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1SET</name>
<description>Timer E output 1 Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1RST</name>
<description>Timer D output 1 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1SET</name>
<description>Timer D output 1 Set</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1RST</name>
<description>Timer C output 1 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1SET</name>
<description>Timer C output 1 Set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1RST</name>
<description>Timer A output 1 Reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1SET</name>
<description>Timer A output 1 Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2BCR</name>
<displayName>CPT2BCR</displayName>
<description>CPT2xCR</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1RST</name>
<description>Timer E output 1 Reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1SET</name>
<description>Timer E output 1 Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1RST</name>
<description>Timer D output 1 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1SET</name>
<description>Timer D output 1 Set</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1RST</name>
<description>Timer C output 1 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1SET</name>
<description>Timer C output 1 Set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1RST</name>
<description>Timer A output 1 Reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1SET</name>
<description>Timer A output 1 Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTBR</name>
<displayName>OUTBR</displayName>
<description>Timerx Output Register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIDL2</name>
<description>Output 2 Deadtime upon burst mode Idle
entry</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP2</name>
<description>Output 2 Chopper enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2</name>
<description>Output 2 Fault state</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES2</name>
<description>Output 2 Idle State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM2</name>
<description>Output 2 Idle mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL2</name>
<description>Output 2 polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYPRTEN</name>
<description>Delayed Protection Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTEN</name>
<description>Deadtime enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIDL1</name>
<description>Output 1 Deadtime upon burst mode Idle
entry</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP1</name>
<description>Output 1 Chopper enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1</name>
<description>Output 1 Fault state</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES1</name>
<description>Output 1 Idle State</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM1</name>
<description>Output 1 Idle mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL1</name>
<description>Output 1 polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLTBR</name>
<displayName>FLTBR</displayName>
<description>Timerx Fault Register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLTLCK</name>
<description>Fault sources Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5EN</name>
<description>Fault 5 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4EN</name>
<description>Fault 4 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3EN</name>
<description>Fault 3 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2EN</name>
<description>Fault 2 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1EN</name>
<description>Fault 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HRTIM_TIMC</name>
<description>High Resolution Timer: TIMC</description>
<groupName>HRTIM</groupName>
<baseAddress>0x40017580</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x80</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TIMCCR</name>
<displayName>TIMCCR</displayName>
<description>Timerx Control Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDGAT</name>
<description>Update Gating</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PREEN</name>
<description>Preload enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACSYNC</name>
<description>AC Synchronization</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSTU</name>
<description>Master Timer update</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEU</name>
<description>TEU</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDU</name>
<description>TDU</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCU</name>
<description>TCU</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBU</name>
<description>TBU</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxRSTU</name>
<description>Timerx reset update</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxREPU</name>
<description>Timer x Repetition update</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DELCMP4</name>
<description>Delayed CMP4 mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DELCMP2</name>
<description>Delayed CMP2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCSTRTx</name>
<description>Synchronization Starts Timer
x</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCRSTx</name>
<description>Synchronization Resets Timer
x</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSHPLL</name>
<description>Push-Pull mode enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALF</name>
<description>Half mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETRIG</name>
<description>Re-triggerable mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>Continuous mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_PSCx</name>
<description>HRTIM Timer x Clock
prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMCISR</name>
<displayName>TIMCISR</displayName>
<description>Timerx Interrupt Status
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>O2STAT</name>
<description>Output 2 State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>O1STAT</name>
<description>Output 1 State</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPPSTAT</name>
<description>Idle Push Pull Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPPSTAT</name>
<description>Current Push Pull Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection Flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST</name>
<description>Reset Interrupt Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2</name>
<description>Output 2 Reset Interrupt
Flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2</name>
<description>Output 2 Set Interrupt
Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1</name>
<description>Output 1 Reset Interrupt
Flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx1</name>
<description>Output 1 Set Interrupt
Flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2</name>
<description>Capture2 Interrupt Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1</name>
<description>Capture1 Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPD</name>
<description>Update Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REP</name>
<description>Repetition Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Compare 4 Interrupt Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Compare 3 Interrupt Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Compare 2 Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Compare 1 Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMCICR</name>
<displayName>TIMCICR</displayName>
<description>Timerx Interrupt Clear
Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTC</name>
<description>Delayed Protection Flag
Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTC</name>
<description>Reset Interrupt flag Clear</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2C</name>
<description>Output 2 Reset flag Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET2xC</name>
<description>Output 2 Set flag Clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1C</name>
<description>Output 1 Reset flag Clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xC</name>
<description>Output 1 Set flag Clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2C</name>
<description>Capture2 Interrupt flag
Clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1C</name>
<description>Capture1 Interrupt flag
Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDC</name>
<description>Update Interrupt flag
Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPC</name>
<description>Repetition Interrupt flag
Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4C</name>
<description>Compare 4 Interrupt flag
Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3C</name>
<description>Compare 3 Interrupt flag
Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2C</name>
<description>Compare 2 Interrupt flag
Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1C</name>
<description>Compare 1 Interrupt flag
Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMCDIER5</name>
<displayName>TIMCDIER5</displayName>
<description>TIMxDIER5</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTDE</name>
<description>DLYPRTDE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDE</name>
<description>RSTDE</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2DE</name>
<description>RSTx2DE</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2DE</name>
<description>SETx2DE</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1DE</name>
<description>RSTx1DE</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xDE</name>
<description>SET1xDE</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2DE</name>
<description>CPT2DE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1DE</name>
<description>CPT1DE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDDE</name>
<description>UPDDE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPDE</name>
<description>REPDE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4DE</name>
<description>CMP4DE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3DE</name>
<description>CMP3DE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2DE</name>
<description>CMP2DE</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1DE</name>
<description>CMP1DE</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRTIE</name>
<description>DLYPRTIE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIE</name>
<description>RSTIE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2IE</name>
<description>RSTx2IE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2IE</name>
<description>SETx2IE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1IE</name>
<description>RSTx1IE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xIE</name>
<description>SET1xIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2IE</name>
<description>CPT2IE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1IE</name>
<description>CPT1IE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDIE</name>
<description>UPDIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPIE</name>
<description>REPIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4IE</name>
<description>CMP4IE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3IE</name>
<description>CMP3IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2IE</name>
<description>CMP2IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1IE</name>
<description>CMP1IE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNTCR</name>
<displayName>CNTCR</displayName>
<description>Timerx Counter Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNTx</name>
<description>Timerx Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERCR</name>
<displayName>PERCR</displayName>
<description>Timerx Period Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>PERx</name>
<description>Timerx Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>REPCR</name>
<displayName>REPCR</displayName>
<description>Timerx Repetition Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition counter
value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1CR</name>
<displayName>CMP1CR</displayName>
<description>Timerx Compare 1 Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1CCR</name>
<displayName>CMP1CCR</displayName>
<description>Timerx Compare 1 Compound
Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition value (aliased from
HRTIM_REPx register)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP2CR</name>
<displayName>CMP2CR</displayName>
<description>Timerx Compare 2 Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP2x</name>
<description>Timerx Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP3CR</name>
<displayName>CMP3CR</displayName>
<description>Timerx Compare 3 Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP3x</name>
<description>Timerx Compare 3 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP4CR</name>
<displayName>CMP4CR</displayName>
<description>Timerx Compare 4 Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP4x</name>
<description>Timerx Compare 4 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1CR</name>
<displayName>CPT1CR</displayName>
<description>Timerx Capture 1 Register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT1x</name>
<description>Timerx Capture 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2CR</name>
<displayName>CPT2CR</displayName>
<description>Timerx Capture 2 Register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT2x</name>
<description>Timerx Capture 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTCR</name>
<displayName>DTCR</displayName>
<description>Timerx Deadtime Register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTFLKx</name>
<description>Deadtime Falling Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFSLKx</name>
<description>Deadtime Falling Sign Lock</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDTFx</name>
<description>Sign Deadtime Falling
value</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFx</name>
<description>Deadtime Falling value</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>DTRLKx</name>
<description>Deadtime Rising Lock</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRSLKx</name>
<description>Deadtime Rising Sign Lock</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTPRSC</name>
<description>Deadtime Prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SDTRx</name>
<description>Sign Deadtime Rising value</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRx</name>
<description>Deadtime Rising value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETC1R</name>
<displayName>SETC1R</displayName>
<description>Timerx Output1 Set Register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>Registers update (transfer preload to
active)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>Timer Event 9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>Timer Event 8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>Timer Event 7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>Timer Event 6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>Timer Event 5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>Timer Event 4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>Timer Event 3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>Timer Event 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>Timer Event 1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master Compare 4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master Compare 3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master Compare 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master Compare 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master Period</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Timer A compare 3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Timer A compare 1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Timer A Period</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>Timer A resynchronizaton</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>Software Set trigger</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTC1R</name>
<displayName>RSTC1R</displayName>
<description>Timerx Output1 Reset Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETC2R</name>
<displayName>SETC2R</displayName>
<description>Timerx Output2 Set Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>SST</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTC2R</name>
<displayName>RSTC2R</displayName>
<description>Timerx Output2 Reset Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFCR1</name>
<displayName>EEFCR1</displayName>
<description>Timerx External Event Filtering Register
1</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE5FLTR</name>
<description>External Event 5 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE5LTCH</name>
<description>External Event 5 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE4FLTR</name>
<description>External Event 4 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE4LTCH</name>
<description>External Event 4 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE3FLTR</name>
<description>External Event 3 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE3LTCH</name>
<description>External Event 3 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE2FLTR</name>
<description>External Event 2 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE2LTCH</name>
<description>External Event 2 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE1FLTR</name>
<description>External Event 1 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE1LTCH</name>
<description>External Event 1 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFCR2</name>
<displayName>EEFCR2</displayName>
<description>Timerx External Event Filtering Register
2</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE10FLTR</name>
<description>External Event 10 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE10LTCH</name>
<description>External Event 10 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE9FLTR</name>
<description>External Event 9 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE9LTCH</name>
<description>External Event 9 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE8FLTR</name>
<description>External Event 8 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE8LTCH</name>
<description>External Event 8 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE7FLTR</name>
<description>External Event 7 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE7LTCH</name>
<description>External Event 7 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE6FLTR</name>
<description>External Event 6 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE6LTCH</name>
<description>External Event 6 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTCR</name>
<displayName>RSTCR</displayName>
<description>TimerA Reset Register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMECMP4</name>
<description>Timer E Compare 4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP4</name>
<description>Timer D Compare 4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP4</name>
<description>Timer B Compare 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP4</name>
<description>Timer A Compare 4</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master compare 4</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master compare 3</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master compare 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master compare 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master timer Period</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4 reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2 reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDT</name>
<description>Timer A Update reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHPCR</name>
<displayName>CHPCR</displayName>
<description>Timerx Chopper Register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRTPW</name>
<description>STRTPW</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CHPDTY</name>
<description>Timerx chopper duty cycle
value</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHPFRQ</name>
<description>Timerx carrier frequency
value</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1CCR</name>
<displayName>CPT1CCR</displayName>
<description>Timerx Capture 2 Control
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1RST</name>
<description>Timer E output 1 Reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1SET</name>
<description>Timer E output 1 Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1RST</name>
<description>Timer D output 1 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1SET</name>
<description>Timer D output 1 Set</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1RST</name>
<description>Timer B output 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1SET</name>
<description>Timer B output 1 Set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1RST</name>
<description>Timer A output 1 Reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1SET</name>
<description>Timer A output 1 Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2CCR</name>
<displayName>CPT2CCR</displayName>
<description>CPT2xCR</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1RST</name>
<description>Timer E output 1 Reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1SET</name>
<description>Timer E output 1 Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1RST</name>
<description>Timer D output 1 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1SET</name>
<description>Timer D output 1 Set</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1RST</name>
<description>Timer B output 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1SET</name>
<description>Timer B output 1 Set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1RST</name>
<description>Timer A output 1 Reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1SET</name>
<description>Timer A output 1 Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTCR</name>
<displayName>OUTCR</displayName>
<description>Timerx Output Register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIDL2</name>
<description>Output 2 Deadtime upon burst mode Idle
entry</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP2</name>
<description>Output 2 Chopper enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2</name>
<description>Output 2 Fault state</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES2</name>
<description>Output 2 Idle State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM2</name>
<description>Output 2 Idle mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL2</name>
<description>Output 2 polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYPRTEN</name>
<description>Delayed Protection Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTEN</name>
<description>Deadtime enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIDL1</name>
<description>Output 1 Deadtime upon burst mode Idle
entry</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP1</name>
<description>Output 1 Chopper enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1</name>
<description>Output 1 Fault state</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES1</name>
<description>Output 1 Idle State</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM1</name>
<description>Output 1 Idle mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL1</name>
<description>Output 1 polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLTCR</name>
<displayName>FLTCR</displayName>
<description>Timerx Fault Register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLTLCK</name>
<description>Fault sources Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5EN</name>
<description>Fault 5 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4EN</name>
<description>Fault 4 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3EN</name>
<description>Fault 3 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2EN</name>
<description>Fault 2 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1EN</name>
<description>Fault 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HRTIM_TIMD</name>
<description>High Resolution Timer: TIMD</description>
<groupName>HRTIM</groupName>
<baseAddress>0x40017600</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x80</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TIMDCR</name>
<displayName>TIMDCR</displayName>
<description>Timerx Control Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDGAT</name>
<description>Update Gating</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PREEN</name>
<description>Preload enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACSYNC</name>
<description>AC Synchronization</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSTU</name>
<description>Master Timer update</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEU</name>
<description>TEU</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDU</name>
<description>TDU</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCU</name>
<description>TCU</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBU</name>
<description>TBU</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxRSTU</name>
<description>Timerx reset update</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxREPU</name>
<description>Timer x Repetition update</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DELCMP4</name>
<description>Delayed CMP4 mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DELCMP2</name>
<description>Delayed CMP2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCSTRTx</name>
<description>Synchronization Starts Timer
x</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCRSTx</name>
<description>Synchronization Resets Timer
x</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSHPLL</name>
<description>Push-Pull mode enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALF</name>
<description>Half mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETRIG</name>
<description>Re-triggerable mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>Continuous mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_PSCx</name>
<description>HRTIM Timer x Clock
prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMDISR</name>
<displayName>TIMDISR</displayName>
<description>Timerx Interrupt Status
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>O2STAT</name>
<description>Output 2 State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>O1STAT</name>
<description>Output 1 State</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPPSTAT</name>
<description>Idle Push Pull Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPPSTAT</name>
<description>Current Push Pull Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection Flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST</name>
<description>Reset Interrupt Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2</name>
<description>Output 2 Reset Interrupt
Flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2</name>
<description>Output 2 Set Interrupt
Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1</name>
<description>Output 1 Reset Interrupt
Flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx1</name>
<description>Output 1 Set Interrupt
Flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2</name>
<description>Capture2 Interrupt Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1</name>
<description>Capture1 Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPD</name>
<description>Update Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REP</name>
<description>Repetition Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Compare 4 Interrupt Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Compare 3 Interrupt Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Compare 2 Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Compare 1 Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMDICR</name>
<displayName>TIMDICR</displayName>
<description>Timerx Interrupt Clear
Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTC</name>
<description>Delayed Protection Flag
Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTC</name>
<description>Reset Interrupt flag Clear</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2C</name>
<description>Output 2 Reset flag Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET2xC</name>
<description>Output 2 Set flag Clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1C</name>
<description>Output 1 Reset flag Clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xC</name>
<description>Output 1 Set flag Clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2C</name>
<description>Capture2 Interrupt flag
Clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1C</name>
<description>Capture1 Interrupt flag
Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDC</name>
<description>Update Interrupt flag
Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPC</name>
<description>Repetition Interrupt flag
Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4C</name>
<description>Compare 4 Interrupt flag
Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3C</name>
<description>Compare 3 Interrupt flag
Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2C</name>
<description>Compare 2 Interrupt flag
Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1C</name>
<description>Compare 1 Interrupt flag
Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMDDIER5</name>
<displayName>TIMDDIER5</displayName>
<description>TIMxDIER5</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTDE</name>
<description>DLYPRTDE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDE</name>
<description>RSTDE</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2DE</name>
<description>RSTx2DE</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2DE</name>
<description>SETx2DE</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1DE</name>
<description>RSTx1DE</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xDE</name>
<description>SET1xDE</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2DE</name>
<description>CPT2DE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1DE</name>
<description>CPT1DE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDDE</name>
<description>UPDDE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPDE</name>
<description>REPDE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4DE</name>
<description>CMP4DE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3DE</name>
<description>CMP3DE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2DE</name>
<description>CMP2DE</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1DE</name>
<description>CMP1DE</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRTIE</name>
<description>DLYPRTIE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIE</name>
<description>RSTIE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2IE</name>
<description>RSTx2IE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2IE</name>
<description>SETx2IE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1IE</name>
<description>RSTx1IE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xIE</name>
<description>SET1xIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2IE</name>
<description>CPT2IE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1IE</name>
<description>CPT1IE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDIE</name>
<description>UPDIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPIE</name>
<description>REPIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4IE</name>
<description>CMP4IE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3IE</name>
<description>CMP3IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2IE</name>
<description>CMP2IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1IE</name>
<description>CMP1IE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNTDR</name>
<displayName>CNTDR</displayName>
<description>Timerx Counter Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNTx</name>
<description>Timerx Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERDR</name>
<displayName>PERDR</displayName>
<description>Timerx Period Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>PERx</name>
<description>Timerx Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>REPDR</name>
<displayName>REPDR</displayName>
<description>Timerx Repetition Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition counter
value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1DR</name>
<displayName>CMP1DR</displayName>
<description>Timerx Compare 1 Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1CDR</name>
<displayName>CMP1CDR</displayName>
<description>Timerx Compare 1 Compound
Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition value (aliased from
HRTIM_REPx register)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP2DR</name>
<displayName>CMP2DR</displayName>
<description>Timerx Compare 2 Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP2x</name>
<description>Timerx Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP3DR</name>
<displayName>CMP3DR</displayName>
<description>Timerx Compare 3 Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP3x</name>
<description>Timerx Compare 3 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP4DR</name>
<displayName>CMP4DR</displayName>
<description>Timerx Compare 4 Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP4x</name>
<description>Timerx Compare 4 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1DR</name>
<displayName>CPT1DR</displayName>
<description>Timerx Capture 1 Register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT1x</name>
<description>Timerx Capture 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2DR</name>
<displayName>CPT2DR</displayName>
<description>Timerx Capture 2 Register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT2x</name>
<description>Timerx Capture 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTDR</name>
<displayName>DTDR</displayName>
<description>Timerx Deadtime Register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTFLKx</name>
<description>Deadtime Falling Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFSLKx</name>
<description>Deadtime Falling Sign Lock</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDTFx</name>
<description>Sign Deadtime Falling
value</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFx</name>
<description>Deadtime Falling value</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>DTRLKx</name>
<description>Deadtime Rising Lock</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRSLKx</name>
<description>Deadtime Rising Sign Lock</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTPRSC</name>
<description>Deadtime Prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SDTRx</name>
<description>Sign Deadtime Rising value</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRx</name>
<description>Deadtime Rising value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETD1R</name>
<displayName>SETD1R</displayName>
<description>Timerx Output1 Set Register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>Registers update (transfer preload to
active)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>Timer Event 9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>Timer Event 8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>Timer Event 7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>Timer Event 6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>Timer Event 5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>Timer Event 4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>Timer Event 3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>Timer Event 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>Timer Event 1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master Compare 4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master Compare 3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master Compare 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master Compare 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master Period</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Timer A compare 3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Timer A compare 1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Timer A Period</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>Timer A resynchronizaton</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>Software Set trigger</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTD1R</name>
<displayName>RSTD1R</displayName>
<description>Timerx Output1 Reset Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETD2R</name>
<displayName>SETD2R</displayName>
<description>Timerx Output2 Set Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>SST</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTD2R</name>
<displayName>RSTD2R</displayName>
<description>Timerx Output2 Reset Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFDR1</name>
<displayName>EEFDR1</displayName>
<description>Timerx External Event Filtering Register
1</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE5FLTR</name>
<description>External Event 5 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE5LTCH</name>
<description>External Event 5 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE4FLTR</name>
<description>External Event 4 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE4LTCH</name>
<description>External Event 4 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE3FLTR</name>
<description>External Event 3 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE3LTCH</name>
<description>External Event 3 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE2FLTR</name>
<description>External Event 2 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE2LTCH</name>
<description>External Event 2 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE1FLTR</name>
<description>External Event 1 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE1LTCH</name>
<description>External Event 1 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFDR2</name>
<displayName>EEFDR2</displayName>
<description>Timerx External Event Filtering Register
2</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE10FLTR</name>
<description>External Event 10 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE10LTCH</name>
<description>External Event 10 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE9FLTR</name>
<description>External Event 9 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE9LTCH</name>
<description>External Event 9 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE8FLTR</name>
<description>External Event 8 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE8LTCH</name>
<description>External Event 8 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE7FLTR</name>
<description>External Event 7 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE7LTCH</name>
<description>External Event 7 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE6FLTR</name>
<description>External Event 6 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE6LTCH</name>
<description>External Event 6 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTDR</name>
<displayName>RSTDR</displayName>
<description>TimerA Reset Register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMECMP4</name>
<description>Timer E Compare 4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP4</name>
<description>Timer C Compare 4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP4</name>
<description>Timer B Compare 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP4</name>
<description>Timer A Compare 4</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master compare 4</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master compare 3</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master compare 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master compare 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master timer Period</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4 reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2 reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDT</name>
<description>Timer A Update reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHPDR</name>
<displayName>CHPDR</displayName>
<description>Timerx Chopper Register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRTPW</name>
<description>STRTPW</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CHPDTY</name>
<description>Timerx chopper duty cycle
value</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHPFRQ</name>
<description>Timerx carrier frequency
value</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1DCR</name>
<displayName>CPT1DCR</displayName>
<description>Timerx Capture 2 Control
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1RST</name>
<description>Timer E output 1 Reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1SET</name>
<description>Timer E output 1 Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1RST</name>
<description>Timer C output 1 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1SET</name>
<description>Timer C output 1 Set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1RST</name>
<description>Timer B output 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1SET</name>
<description>Timer B output 1 Set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1RST</name>
<description>Timer A output 1 Reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1SET</name>
<description>Timer A output 1 Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2DCR</name>
<displayName>CPT2DCR</displayName>
<description>CPT2xCR</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TECMP2</name>
<description>Timer E Compare 2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TECMP1</name>
<description>Timer E Compare 1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1RST</name>
<description>Timer E output 1 Reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE1SET</name>
<description>Timer E output 1 Set</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1RST</name>
<description>Timer C output 1 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1SET</name>
<description>Timer C output 1 Set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1RST</name>
<description>Timer B output 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1SET</name>
<description>Timer B output 1 Set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1RST</name>
<description>Timer A output 1 Reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1SET</name>
<description>Timer A output 1 Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTDR</name>
<displayName>OUTDR</displayName>
<description>Timerx Output Register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIDL2</name>
<description>Output 2 Deadtime upon burst mode Idle
entry</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP2</name>
<description>Output 2 Chopper enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2</name>
<description>Output 2 Fault state</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES2</name>
<description>Output 2 Idle State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM2</name>
<description>Output 2 Idle mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL2</name>
<description>Output 2 polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYPRTEN</name>
<description>Delayed Protection Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTEN</name>
<description>Deadtime enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIDL1</name>
<description>Output 1 Deadtime upon burst mode Idle
entry</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP1</name>
<description>Output 1 Chopper enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1</name>
<description>Output 1 Fault state</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES1</name>
<description>Output 1 Idle State</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM1</name>
<description>Output 1 Idle mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL1</name>
<description>Output 1 polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLTDR</name>
<displayName>FLTDR</displayName>
<description>Timerx Fault Register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLTLCK</name>
<description>Fault sources Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5EN</name>
<description>Fault 5 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4EN</name>
<description>Fault 4 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3EN</name>
<description>Fault 3 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2EN</name>
<description>Fault 2 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1EN</name>
<description>Fault 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HRTIM_TIME</name>
<description>High Resolution Timer: TIME</description>
<groupName>HRTIM</groupName>
<baseAddress>0x40017680</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x80</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TIMECR</name>
<displayName>TIMECR</displayName>
<description>Timerx Control Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDGAT</name>
<description>Update Gating</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PREEN</name>
<description>Preload enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACSYNC</name>
<description>AC Synchronization</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSTU</name>
<description>Master Timer update</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEU</name>
<description>TEU</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDU</name>
<description>TDU</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCU</name>
<description>TCU</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBU</name>
<description>TBU</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxRSTU</name>
<description>Timerx reset update</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TxREPU</name>
<description>Timer x Repetition update</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DELCMP4</name>
<description>Delayed CMP4 mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DELCMP2</name>
<description>Delayed CMP2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCSTRTx</name>
<description>Synchronization Starts Timer
x</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCRSTx</name>
<description>Synchronization Resets Timer
x</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PSHPLL</name>
<description>Push-Pull mode enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALF</name>
<description>Half mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RETRIG</name>
<description>Re-triggerable mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>Continuous mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_PSCx</name>
<description>HRTIM Timer x Clock
prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMEISR</name>
<displayName>TIMEISR</displayName>
<description>Timerx Interrupt Status
Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>O2STAT</name>
<description>Output 2 State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>O1STAT</name>
<description>Output 1 State</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPPSTAT</name>
<description>Idle Push Pull Status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPPSTAT</name>
<description>Current Push Pull Status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection Flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST</name>
<description>Reset Interrupt Flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2</name>
<description>Output 2 Reset Interrupt
Flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2</name>
<description>Output 2 Set Interrupt
Flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1</name>
<description>Output 1 Reset Interrupt
Flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx1</name>
<description>Output 1 Set Interrupt
Flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2</name>
<description>Capture2 Interrupt Flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1</name>
<description>Capture1 Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPD</name>
<description>Update Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REP</name>
<description>Repetition Interrupt Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Compare 4 Interrupt Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Compare 3 Interrupt Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Compare 2 Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Compare 1 Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMEICR</name>
<displayName>TIMEICR</displayName>
<description>Timerx Interrupt Clear
Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTC</name>
<description>Delayed Protection Flag
Clear</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTC</name>
<description>Reset Interrupt flag Clear</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2C</name>
<description>Output 2 Reset flag Clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET2xC</name>
<description>Output 2 Set flag Clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1C</name>
<description>Output 1 Reset flag Clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xC</name>
<description>Output 1 Set flag Clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2C</name>
<description>Capture2 Interrupt flag
Clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1C</name>
<description>Capture1 Interrupt flag
Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDC</name>
<description>Update Interrupt flag
Clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPC</name>
<description>Repetition Interrupt flag
Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4C</name>
<description>Compare 4 Interrupt flag
Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3C</name>
<description>Compare 3 Interrupt flag
Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2C</name>
<description>Compare 2 Interrupt flag
Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1C</name>
<description>Compare 1 Interrupt flag
Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMEDIER5</name>
<displayName>TIMEDIER5</displayName>
<description>TIMxDIER5</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYPRTDE</name>
<description>DLYPRTDE</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTDE</name>
<description>RSTDE</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2DE</name>
<description>RSTx2DE</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2DE</name>
<description>SETx2DE</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1DE</name>
<description>RSTx1DE</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xDE</name>
<description>SET1xDE</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2DE</name>
<description>CPT2DE</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1DE</name>
<description>CPT1DE</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDDE</name>
<description>UPDDE</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPDE</name>
<description>REPDE</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4DE</name>
<description>CMP4DE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3DE</name>
<description>CMP3DE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2DE</name>
<description>CMP2DE</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1DE</name>
<description>CMP1DE</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRTIE</name>
<description>DLYPRTIE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTIE</name>
<description>RSTIE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx2IE</name>
<description>RSTx2IE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SETx2IE</name>
<description>SETx2IE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTx1IE</name>
<description>RSTx1IE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SET1xIE</name>
<description>SET1xIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT2IE</name>
<description>CPT2IE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPT1IE</name>
<description>CPT1IE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDIE</name>
<description>UPDIE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REPIE</name>
<description>REPIE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4IE</name>
<description>CMP4IE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3IE</name>
<description>CMP3IE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2IE</name>
<description>CMP2IE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1IE</name>
<description>CMP1IE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNTER</name>
<displayName>CNTER</displayName>
<description>Timerx Counter Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNTx</name>
<description>Timerx Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERER</name>
<displayName>PERER</displayName>
<description>Timerx Period Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>PERx</name>
<description>Timerx Period value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>REPER</name>
<displayName>REPER</displayName>
<description>Timerx Repetition Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition counter
value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1ER</name>
<displayName>CMP1ER</displayName>
<description>Timerx Compare 1 Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP1CER</name>
<displayName>CMP1CER</displayName>
<description>Timerx Compare 1 Compound
Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REPx</name>
<description>Timerx Repetition value (aliased from
HRTIM_REPx register)</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CMP1x</name>
<description>Timerx Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP2ER</name>
<displayName>CMP2ER</displayName>
<description>Timerx Compare 2 Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP2x</name>
<description>Timerx Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP3ER</name>
<displayName>CMP3ER</displayName>
<description>Timerx Compare 3 Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP3x</name>
<description>Timerx Compare 3 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP4ER</name>
<displayName>CMP4ER</displayName>
<description>Timerx Compare 4 Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP4x</name>
<description>Timerx Compare 4 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1ER</name>
<displayName>CPT1ER</displayName>
<description>Timerx Capture 1 Register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT1x</name>
<description>Timerx Capture 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2ER</name>
<displayName>CPT2ER</displayName>
<description>Timerx Capture 2 Register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPT2x</name>
<description>Timerx Capture 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTER</name>
<displayName>DTER</displayName>
<description>Timerx Deadtime Register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTFLKx</name>
<description>Deadtime Falling Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFSLKx</name>
<description>Deadtime Falling Sign Lock</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDTFx</name>
<description>Sign Deadtime Falling
value</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTFx</name>
<description>Deadtime Falling value</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>DTRLKx</name>
<description>Deadtime Rising Lock</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRSLKx</name>
<description>Deadtime Rising Sign Lock</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTPRSC</name>
<description>Deadtime Prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SDTRx</name>
<description>Sign Deadtime Rising value</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRx</name>
<description>Deadtime Rising value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETE1R</name>
<displayName>SETE1R</displayName>
<description>Timerx Output1 Set Register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>Registers update (transfer preload to
active)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>Timer Event 9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>Timer Event 8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>Timer Event 7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>Timer Event 6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>Timer Event 5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>Timer Event 4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>Timer Event 3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>Timer Event 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>Timer Event 1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master Compare 4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master Compare 3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master Compare 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master Compare 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master Period</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>Timer A compare 3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>Timer A compare 1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Timer A Period</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>Timer A resynchronizaton</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>Software Set trigger</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTE1R</name>
<displayName>RSTE1R</displayName>
<description>Timerx Output1 Reset Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETE2R</name>
<displayName>SETE2R</displayName>
<description>Timerx Output2 Set Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SST</name>
<description>SST</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTE2R</name>
<displayName>RSTE2R</displayName>
<description>Timerx Output2 Reset Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UPDATE</name>
<description>UPDATE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>EXTEVNT10</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>EXTEVNT9</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>EXTEVNT8</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>EXTEVNT7</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>EXTEVNT6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>EXTEVNT5</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>EXTEVNT4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>EXTEVNT3</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>EXTEVNT2</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>EXTEVNT1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT9</name>
<description>TIMEVNT9</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT8</name>
<description>TIMEVNT8</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT7</name>
<description>TIMEVNT7</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT6</name>
<description>TIMEVNT6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT5</name>
<description>TIMEVNT5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT4</name>
<description>TIMEVNT4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT3</name>
<description>TIMEVNT3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT2</name>
<description>TIMEVNT2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEVNT1</name>
<description>TIMEVNT1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>MSTCMP4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>MSTCMP3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>MSTCMP2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>MSTCMP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>MSTPER</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>CMP4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP3</name>
<description>CMP3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>CMP2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP1</name>
<description>CMP1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>PER</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESYNC</name>
<description>RESYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRT</name>
<description>SRT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFER1</name>
<displayName>EEFER1</displayName>
<description>Timerx External Event Filtering Register
1</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE5FLTR</name>
<description>External Event 5 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE5LTCH</name>
<description>External Event 5 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE4FLTR</name>
<description>External Event 4 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE4LTCH</name>
<description>External Event 4 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE3FLTR</name>
<description>External Event 3 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE3LTCH</name>
<description>External Event 3 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE2FLTR</name>
<description>External Event 2 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE2LTCH</name>
<description>External Event 2 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE1FLTR</name>
<description>External Event 1 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE1LTCH</name>
<description>External Event 1 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EEFER2</name>
<displayName>EEFER2</displayName>
<description>Timerx External Event Filtering Register
2</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EE10FLTR</name>
<description>External Event 10 filter</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE10LTCH</name>
<description>External Event 10 latch</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE9FLTR</name>
<description>External Event 9 filter</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE9LTCH</name>
<description>External Event 9 latch</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE8FLTR</name>
<description>External Event 8 filter</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE8LTCH</name>
<description>External Event 8 latch</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE7FLTR</name>
<description>External Event 7 filter</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE7LTCH</name>
<description>External Event 7 latch</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EE6FLTR</name>
<description>External Event 6 filter</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EE6LTCH</name>
<description>External Event 6 latch</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSTER</name>
<displayName>RSTER</displayName>
<description>TimerA Reset Register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMDCMP4</name>
<description>Timer D Compare 4</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP4</name>
<description>Timer C Compare 4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP4</name>
<description>Timer B Compare 4</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP4</name>
<description>Timer A Compare 4</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT10</name>
<description>External Event 10</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT9</name>
<description>External Event 9</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT8</name>
<description>External Event 8</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT7</name>
<description>External Event 7</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT6</name>
<description>External Event 6</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT5</name>
<description>External Event 5</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT4</name>
<description>External Event 4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT3</name>
<description>External Event 3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT2</name>
<description>External Event 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEVNT1</name>
<description>External Event 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP4</name>
<description>Master compare 4</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP3</name>
<description>Master compare 3</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP2</name>
<description>Master compare 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTCMP1</name>
<description>Master compare 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTPER</name>
<description>Master timer Period</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP4</name>
<description>Timer A compare 4 reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP2</name>
<description>Timer A compare 2 reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPDT</name>
<description>Timer A Update reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CHPER</name>
<displayName>CHPER</displayName>
<description>Timerx Chopper Register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRTPW</name>
<description>STRTPW</description>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CHPDTY</name>
<description>Timerx chopper duty cycle
value</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHPFRQ</name>
<description>Timerx carrier frequency
value</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT1ECR</name>
<displayName>CPT1ECR</displayName>
<description>Timerx Capture 2 Control
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1RST</name>
<description>Timer D output 1 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1SET</name>
<description>Timer D output 1 Set</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1RST</name>
<description>Timer C output 1 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1SET</name>
<description>Timer C output 1 Set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1RST</name>
<description>Timer B output 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1SET</name>
<description>Timer B output 1 Set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1RST</name>
<description>Timer A output 1 Reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1SET</name>
<description>Timer A output 1 Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPT2ECR</name>
<displayName>CPT2ECR</displayName>
<description>CPT2xCR</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDCMP2</name>
<description>Timer D Compare 2</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCMP1</name>
<description>Timer D Compare 1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1RST</name>
<description>Timer D output 1 Reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TD1SET</name>
<description>Timer D output 1 Set</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP2</name>
<description>Timer C Compare 2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCMP1</name>
<description>Timer C Compare 1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1RST</name>
<description>Timer C output 1 Reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC1SET</name>
<description>Timer C output 1 Set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP2</name>
<description>Timer B Compare 2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBCMP1</name>
<description>Timer B Compare 1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1RST</name>
<description>Timer B output 1 Reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TB1SET</name>
<description>Timer B output 1 Set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP2</name>
<description>Timer A Compare 2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACMP1</name>
<description>Timer A Compare 1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1RST</name>
<description>Timer A output 1 Reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TA1SET</name>
<description>Timer A output 1 Set</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV10CPT</name>
<description>External Event 10 Capture</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV9CPT</name>
<description>External Event 9 Capture</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV8CPT</name>
<description>External Event 8 Capture</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV7CPT</name>
<description>External Event 7 Capture</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV6CPT</name>
<description>External Event 6 Capture</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV5CPT</name>
<description>External Event 5 Capture</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV4CPT</name>
<description>External Event 4 Capture</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV3CPT</name>
<description>External Event 3 Capture</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV2CPT</name>
<description>External Event 2 Capture</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXEV1CPT</name>
<description>External Event 1 Capture</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDPCPT</name>
<description>Update Capture</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWCPT</name>
<description>Software Capture</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTER</name>
<displayName>OUTER</displayName>
<description>Timerx Output Register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIDL2</name>
<description>Output 2 Deadtime upon burst mode Idle
entry</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP2</name>
<description>Output 2 Chopper enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2</name>
<description>Output 2 Fault state</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES2</name>
<description>Output 2 Idle State</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM2</name>
<description>Output 2 Idle mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL2</name>
<description>Output 2 polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLYPRT</name>
<description>Delayed Protection</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYPRTEN</name>
<description>Delayed Protection Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTEN</name>
<description>Deadtime enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIDL1</name>
<description>Output 1 Deadtime upon burst mode Idle
entry</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHP1</name>
<description>Output 1 Chopper enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1</name>
<description>Output 1 Fault state</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDLES1</name>
<description>Output 1 Idle State</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEM1</name>
<description>Output 1 Idle mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL1</name>
<description>Output 1 polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLTER</name>
<displayName>FLTER</displayName>
<description>Timerx Fault Register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLTLCK</name>
<description>Fault sources Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT5EN</name>
<description>Fault 5 enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT4EN</name>
<description>Fault 4 enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT3EN</name>
<description>Fault 3 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT2EN</name>
<description>Fault 2 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLT1EN</name>
<description>Fault 1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HSEM</name>
<description>HSEM</description>
<groupName>HSEM</groupName>
<baseAddress>0x48020800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>HSEM0</name>
<description>HSEM global interrupt 1</description>
<value>125</value>
</interrupt>
<registers>
<register>
<name>R0</name>
<displayName>R0</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R1</name>
<displayName>R1</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R2</name>
<displayName>R2</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R3</name>
<displayName>R3</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R4</name>
<displayName>R4</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R5</name>
<displayName>R5</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R6</name>
<displayName>R6</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R7</name>
<displayName>R7</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R8</name>
<displayName>R8</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R9</name>
<displayName>R9</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R10</name>
<displayName>R10</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R11</name>
<displayName>R11</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R12</name>
<displayName>R12</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R13</name>
<displayName>R13</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R14</name>
<displayName>R14</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R15</name>
<displayName>R15</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R16</name>
<displayName>R16</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R17</name>
<displayName>R17</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R18</name>
<displayName>R18</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R19</name>
<displayName>R19</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R20</name>
<displayName>R20</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R21</name>
<displayName>R21</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R22</name>
<displayName>R22</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R23</name>
<displayName>R23</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R24</name>
<displayName>R24</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R25</name>
<displayName>R25</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R26</name>
<displayName>R26</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R27</name>
<displayName>R27</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R28</name>
<displayName>R28</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R29</name>
<displayName>R29</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R30</name>
<displayName>R30</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>R31</name>
<displayName>R31</displayName>
<description>HSEM register HSEM_R0 HSEM_R31</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR0</name>
<displayName>RLR0</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR1</name>
<displayName>RLR1</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR2</name>
<displayName>RLR2</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR3</name>
<displayName>RLR3</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR4</name>
<displayName>RLR4</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR5</name>
<displayName>RLR5</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR6</name>
<displayName>RLR6</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR7</name>
<displayName>RLR7</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR8</name>
<displayName>RLR8</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR9</name>
<displayName>RLR9</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR10</name>
<displayName>RLR10</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR11</name>
<displayName>RLR11</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR12</name>
<displayName>RLR12</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR13</name>
<displayName>RLR13</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR14</name>
<displayName>RLR14</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR15</name>
<displayName>RLR15</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR16</name>
<displayName>RLR16</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR17</name>
<displayName>RLR17</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR18</name>
<displayName>RLR18</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR19</name>
<displayName>RLR19</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR20</name>
<displayName>RLR20</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR21</name>
<displayName>RLR21</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR22</name>
<displayName>RLR22</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR23</name>
<displayName>RLR23</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR24</name>
<displayName>RLR24</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR25</name>
<displayName>RLR25</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR26</name>
<displayName>RLR26</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xE8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR27</name>
<displayName>RLR27</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xEC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR28</name>
<displayName>RLR28</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xF0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR29</name>
<displayName>RLR29</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xF4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR30</name>
<displayName>RLR30</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xF8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR31</name>
<displayName>RLR31</displayName>
<description>HSEM Read lock register</description>
<addressOffset>0xFC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MASTERID</name>
<description>Semaphore MasterID</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>HSEM Interrupt enable register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISEM0</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM1</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM2</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM3</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM4</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM5</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM6</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM7</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM8</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM9</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM10</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM11</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM12</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM13</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM14</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM15</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM16</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM17</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM18</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM19</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM20</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM21</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM22</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM23</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM24</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM25</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM26</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM27</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM28</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM29</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM30</name>
<description>Interrupt semaphore n enable
bit</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM31</name>
<description>Interrupt(N) semaphore n enable
bit.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>HSEM Interrupt clear register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISEM0</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM1</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM2</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM3</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM4</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM5</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM6</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM7</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM8</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM9</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM10</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM11</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM12</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM13</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM14</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM15</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM16</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM17</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM18</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM19</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM20</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM21</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM22</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM23</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM24</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM25</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM26</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM27</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM28</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM29</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM30</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM31</name>
<description>Interrupt(N) semaphore n clear
bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>HSEM Interrupt status register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISEM0</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM1</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM2</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM3</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM4</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM5</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM6</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM7</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM8</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM9</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM10</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM11</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM12</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM13</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM14</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM15</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM16</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM17</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM18</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM19</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM20</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM21</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM22</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM23</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM24</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM25</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM26</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM27</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM28</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM29</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM30</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM31</name>
<description>Interrupt(N) semaphore n status bit
before enable (mask)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MISR</name>
<displayName>MISR</displayName>
<description>HSEM Masked interrupt status
register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISEM0</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM1</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM2</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM3</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM4</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM5</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM6</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM7</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM8</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM9</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM10</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM11</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM12</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM13</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM14</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM15</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM16</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM17</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM18</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM19</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM20</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM21</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM22</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM23</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM24</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM25</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM26</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM27</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM28</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM29</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM30</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISEM31</name>
<description>masked interrupt(N) semaphore n status
bit after enable (mask)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>HSEM Clear register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASTERID</name>
<description>MasterID of semaphores to be
cleared</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>KEY</name>
<description>Semaphore clear Key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR</name>
<displayName>KEYR</displayName>
<description>HSEM Interrupt clear register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Semaphore Clear Key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>I2C</description>
<groupName>I2C</groupName>
<baseAddress>0x40005400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1_EV</name>
<description>I2C1 event interrupt</description>
<value>31</value>
</interrupt>
<interrupt>
<name>I2C1_ER</name>
<description>I2C1 error interrupt</description>
<value>32</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PE</name>
<description>Peripheral enable Note: When PE=0, the
I2C SCL and SDA lines are released. Internal state
machines and status bits are put back to their reset
value. When cleared, PE must be kept low for at least
3 APB clock cycles.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXIE</name>
<description>TX Interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXIE</name>
<description>RX Interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDRIE</name>
<description>Address match Interrupt enable (slave
only)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKIE</name>
<description>Not acknowledge received Interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPIE</name>
<description>STOP detection Interrupt
enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer Complete interrupt enable Note:
Any of these events will generate an interrupt:
Transfer Complete (TC) Transfer Complete Reload
(TCR)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupts enable Note: Any of
these errors generate an interrupt: Arbitration Loss
(ARLO) Bus Error detection (BERR) Overrun/Underrun
(OVR) Timeout detection (TIMEOUT) PEC error detection
(PECERR) Alert pin event detection
(ALERT)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DNF</name>
<description>Digital noise filter These bits are used
to configure the digital noise filter on SDA and SCL
input. The digital filter will filter spikes with a
length of up to DNF[3:0] * tI2CCLK ... Note: If the
analog filter is also enabled, the digital filter is
added to the analog filter. This filter can only be
programmed when the I2C is disabled (PE =
0).</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ANFOFF</name>
<description>Analog noise filter OFF Note: This bit
can only be programmed when the I2C is disabled (PE =
0).</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDMAEN</name>
<description>DMA transmission requests
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDMAEN</name>
<description>DMA reception requests
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBC</name>
<description>Slave byte control This bit is used to
enable hardware byte control in slave
mode.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOSTRETCH</name>
<description>Clock stretching disable This bit is
used to disable clock stretching in slave mode. It
must be kept cleared in master mode. Note: This bit
can only be programmed when the I2C is disabled (PE =
0).</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUPEN</name>
<description>Wakeup from Stop mode enable Note: If
the Wakeup from Stop mode feature is not supported,
this bit is reserved and forced by hardware to 0.
Please refer to Section25.3: I2C implementation.
Note: WUPEN can be set only when DNF =
0000</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCEN</name>
<description>General call enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHEN</name>
<description>SMBus Host address enable Note: If the
SMBus feature is not supported, this bit is reserved
and forced by hardware to 0. Please refer to
Section25.3: I2C implementation.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDEN</name>
<description>SMBus Device Default address enable
Note: If the SMBus feature is not supported, this bit
is reserved and forced by hardware to 0. Please refer
to Section25.3: I2C implementation.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALERTEN</name>
<description>SMBus alert enable Device mode
(SMBHEN=0): Host mode (SMBHEN=1): Note: When
ALERTEN=0, the SMBA pin can be used as a standard
GPIO. If the SMBus feature is not supported, this bit
is reserved and forced by hardware to 0. Please refer
to Section25.3: I2C implementation.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECEN</name>
<description>PEC enable Note: If the SMBus feature is
not supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SADD0</name>
<description>Slave address bit 0 (master mode) In
7-bit addressing mode (ADD10 = 0): This bit is dont
care In 10-bit addressing mode (ADD10 = 1): This bit
should be written with bit 0 of the slave address to
be sent Note: Changing these bits when the START bit
is set is not allowed.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD1</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD2</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD3</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD4</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD5</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD6</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD7</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD8</name>
<description>Slave address bit 9:8 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits are
dont care In 10-bit addressing mode (ADD10 = 1):
These bits should be written with bits 9:8 of the
slave address to be sent Note: Changing these bits
when the START bit is set is not
allowed.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD9</name>
<description>Slave address bit 9:8 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits are
dont care In 10-bit addressing mode (ADD10 = 1):
These bits should be written with bits 9:8 of the
slave address to be sent Note: Changing these bits
when the START bit is set is not
allowed.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_WRN</name>
<description>Transfer direction (master mode) Note:
Changing this bit when the START bit is set is not
allowed.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD10</name>
<description>10-bit addressing mode (master mode)
Note: Changing this bit when the START bit is set is
not allowed.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HEAD10R</name>
<description>10-bit address header only read
direction (master receiver mode) Note: Changing this
bit when the START bit is set is not
allowed.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start generation This bit is set by
software, and cleared by hardware after the Start
followed by the address sequence is sent, by an
arbitration loss, by a timeout error detection, or
when PE = 0. It can also be cleared by software by
writing 1 to the ADDRCF bit in the I2C_ICR register.
If the I2C is already in master mode with AUTOEND =
0, setting this bit generates a Repeated Start
condition when RELOAD=0, after the end of the NBYTES
transfer. Otherwise setting this bit will generate a
START condition once the bus is free. Note: Writing 0
to this bit has no effect. The START bit can be set
even if the bus is BUSY or I2C is in slave mode. This
bit has no effect when RELOAD is set.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>Stop generation (master mode) The bit is
set by software, cleared by hardware when a Stop
condition is detected, or when PE = 0. In Master
Mode: Note: Writing 0 to this bit has no
effect.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>NACK generation (slave mode) The bit is
set by software, cleared by hardware when the NACK is
sent, or when a STOP condition or an Address matched
is received, or when PE=0. Note: Writing 0 to this
bit has no effect. This bit is used in slave mode
only: in master receiver mode, NACK is automatically
generated after last byte preceding STOP or RESTART
condition, whatever the NACK bit value. When an
overrun occurs in slave receiver NOSTRETCH mode, a
NACK is automatically generated whatever the NACK bit
value. When hardware PEC checking is enabled
(PECBYTE=1), the PEC acknowledge value does not
depend on the NACK value.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBYTES</name>
<description>Number of bytes The number of bytes to
be transmitted/received is programmed there. This
field is dont care in slave mode with SBC=0. Note:
Changing these bits when the START bit is set is not
allowed.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RELOAD</name>
<description>NBYTES reload mode This bit is set and
cleared by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTOEND</name>
<description>Automatic end mode (master mode) This
bit is set and cleared by software. Note: This bit
has no effect in slave mode or when the RELOAD bit is
set.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECBYTE</name>
<description>Packet error checking byte This bit is
set by software, and cleared by hardware when the PEC
is transferred, or when a STOP condition or an
Address matched is received, also when PE=0. Note:
Writing 0 to this bit has no effect. This bit has no
effect when RELOAD is set. This bit has no effect is
slave mode when SBC=0. If the SMBus feature is not
supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OAR1</name>
<displayName>OAR1</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OA1</name>
<description>Interface address 7-bit addressing mode:
dont care 10-bit addressing mode: bits 9:8 of address
Note: These bits can be written only when OA1EN=0.
OA1[7:1]: Interface address Bits 7:1 of address Note:
These bits can be written only when OA1EN=0. OA1[0]:
Interface address 7-bit addressing mode: dont care
10-bit addressing mode: bit 0 of address Note: This
bit can be written only when OA1EN=0.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>OA1MODE</name>
<description>Own Address 1 10-bit mode Note: This bit
can be written only when OA1EN=0.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OA1EN</name>
<description>Own Address 1 enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OAR2</name>
<displayName>OAR2</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OA2</name>
<description>Interface address bits 7:1 of address
Note: These bits can be written only when
OA2EN=0.</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>OA2MSK</name>
<description>Own Address 2 masks Note: These bits can
be written only when OA2EN=0. As soon as OA2MSK is
not equal to 0, the reserved I2C addresses (0b0000xxx
and 0b1111xxx) are not acknowledged even if the
comparison matches.</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OA2EN</name>
<description>Own Address 2 enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMINGR</name>
<displayName>TIMINGR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCLL</name>
<description>SCL low period (master mode) This field
is used to generate the SCL low period in master
mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also
used to generate tBUF and tSU:STA
timings.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SCLH</name>
<description>SCL high period (master mode) This field
is used to generate the SCL high period in master
mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also
used to generate tSU:STO and tHD:STA
timing.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SDADEL</name>
<description>Data hold time This field is used to
generate the delay tSDADEL between SCL falling edge
and SDA edge. In master mode and in slave mode with
NOSTRETCH = 0, the SCL line is stretched low during
tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is
used to generate tHD:DAT timing.</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SCLDEL</name>
<description>Data setup time This field is used to
generate a delay tSCLDEL between SDA edge and SCL
rising edge. In master mode and in slave mode with
NOSTRETCH = 0, the SCL line is stretched low during
tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL
is used to generate tSU:DAT timing.</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>Timing prescaler This field is used to
prescale I2CCLK in order to generate the clock period
tPRESC used for data setup and hold counters (refer
to I2C timings on page9) and for SCL high and low
level counters (refer to I2C master initialization on
page24). tPRESC = (PRESC+1) x tI2CCLK</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMEOUTR</name>
<displayName>TIMEOUTR</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMEOUTA</name>
<description>Bus Timeout A This field is used to
configure: The SCL low timeout condition tTIMEOUT
when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK
The bus idle condition (both SCL and SDA high) when
TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These
bits can be written only when
TIMOUTEN=0.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TIDLE</name>
<description>Idle clock timeout detection Note: This
bit can be written only when
TIMOUTEN=0.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUTEN</name>
<description>Clock timeout enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUTB</name>
<description>Bus timeout B This field is used to
configure the cumulative clock extension timeout: In
master mode, the master cumulative clock low extend
time (tLOW:MEXT) is detected In slave mode, the slave
cumulative clock low extend time (tLOW:SEXT) is
detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK
Note: These bits can be written only when
TEXTEN=0.</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TEXTEN</name>
<description>Extended clock timeout
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>TXE</name>
<description>Transmit data register empty
(transmitters) This bit is set by hardware when the
I2C_TXDR register is empty. It is cleared when the
next data to be sent is written in the I2C_TXDR
register. This bit can be written to 1 by software in
order to flush the transmit data register I2C_TXDR.
Note: This bit is set by hardware when
PE=0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXIS</name>
<description>Transmit interrupt status (transmitters)
This bit is set by hardware when the I2C_TXDR
register is empty and the data to be transmitted must
be written in the I2C_TXDR register. It is cleared
when the next data to be sent is written in the
I2C_TXDR register. This bit can be written to 1 by
software when NOSTRETCH=1 only, in order to generate
a TXIS event (interrupt if TXIE=1 or DMA request if
TXDMAEN=1). Note: This bit is cleared by hardware
when PE=0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXNE</name>
<description>Receive data register not empty
(receivers) This bit is set by hardware when the
received data is copied into the I2C_RXDR register,
and is ready to be read. It is cleared when I2C_RXDR
is read. Note: This bit is cleared by hardware when
PE=0.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ADDR</name>
<description>Address matched (slave mode) This bit is
set by hardware as soon as the received slave address
matched with one of the enabled slave addresses. It
is cleared by software by setting ADDRCF bit. Note:
This bit is cleared by hardware when
PE=0.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NACKF</name>
<description>Not Acknowledge received flag This flag
is set by hardware when a NACK is received after a
byte transmission. It is cleared by software by
setting the NACKCF bit. Note: This bit is cleared by
hardware when PE=0.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>STOPF</name>
<description>Stop detection flag This flag is set by
hardware when a Stop condition is detected on the bus
and the peripheral is involved in this transfer:
either as a master, provided that the STOP condition
is generated by the peripheral. or as a slave,
provided that the peripheral has been addressed
previously during this transfer. It is cleared by
software by setting the STOPCF bit. Note: This bit is
cleared by hardware when PE=0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TC</name>
<description>Transfer Complete (master mode) This
flag is set by hardware when RELOAD=0, AUTOEND=0 and
NBYTES data have been transferred. It is cleared by
software when START bit or STOP bit is set. Note:
This bit is cleared by hardware when
PE=0.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TCR</name>
<description>Transfer Complete Reload This flag is
set by hardware when RELOAD=1 and NBYTES data have
been transferred. It is cleared by software when
NBYTES is written to a non-zero value. Note: This bit
is cleared by hardware when PE=0. This flag is only
for master mode, or for slave mode when the SBC bit
is set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BERR</name>
<description>Bus error This flag is set by hardware
when a misplaced Start or Stop condition is detected
whereas the peripheral is involved in the transfer.
The flag is not set during the address phase in slave
mode. It is cleared by software by setting BERRCF
bit. Note: This bit is cleared by hardware when
PE=0.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ARLO</name>
<description>Arbitration lost This flag is set by
hardware in case of arbitration loss. It is cleared
by software by setting the ARLOCF bit. Note: This bit
is cleared by hardware when PE=0.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR</name>
<description>Overrun/Underrun (slave mode) This flag
is set by hardware in slave mode with NOSTRETCH=1,
when an overrun/underrun error occurs. It is cleared
by software by setting the OVRCF bit. Note: This bit
is cleared by hardware when PE=0.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PECERR</name>
<description>PEC Error in reception This flag is set
by hardware when the received PEC does not match with
the PEC register content. A NACK is automatically
sent after the wrong PEC reception. It is cleared by
software by setting the PECCF bit. Note: This bit is
cleared by hardware when PE=0. If the SMBus feature
is not supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout or tLOW detection flag This flag
is set by hardware when a timeout or extended clock
timeout occurred. It is cleared by software by
setting the TIMEOUTCF bit. Note: This bit is cleared
by hardware when PE=0. If the SMBus feature is not
supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ALERT</name>
<description>SMBus alert This flag is set by hardware
when SMBHEN=1 (SMBus host configuration), ALERTEN=1
and a SMBALERT event (falling edge) is detected on
SMBA pin. It is cleared by software by setting the
ALERTCF bit. Note: This bit is cleared by hardware
when PE=0. If the SMBus feature is not supported,
this bit is reserved and forced by hardware to 0.
Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BUSY</name>
<description>Bus busy This flag indicates that a
communication is in progress on the bus. It is set by
hardware when a START condition is detected. It is
cleared by hardware when a Stop condition is
detected, or when PE=0.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DIR</name>
<description>Transfer direction (Slave mode) This
flag is updated when an address match event occurs
(ADDR=1).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ADDCODE</name>
<description>Address match code (Slave mode) These
bits are updated with the received address when an
address match event occurs (ADDR = 1). In the case of
a 10-bit address, ADDCODE provides the 10-bit header
followed by the 2 MSBs of the address.</description>
<bitOffset>17</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRCF</name>
<description>Address matched flag clear Writing 1 to
this bit clears the ADDR flag in the I2C_ISR
register. Writing 1 to this bit also clears the START
bit in the I2C_CR2 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKCF</name>
<description>Not Acknowledge flag clear Writing 1 to
this bit clears the ACKF flag in I2C_ISR
register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPCF</name>
<description>Stop detection flag clear Writing 1 to
this bit clears the STOPF flag in the I2C_ISR
register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BERRCF</name>
<description>Bus error flag clear Writing 1 to this
bit clears the BERRF flag in the I2C_ISR
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARLOCF</name>
<description>Arbitration Lost flag clear Writing 1 to
this bit clears the ARLO flag in the I2C_ISR
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRCF</name>
<description>Overrun/Underrun flag clear Writing 1 to
this bit clears the OVR flag in the I2C_ISR
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECCF</name>
<description>PEC Error flag clear Writing 1 to this
bit clears the PECERR flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit
is reserved and forced by hardware to 0. Please refer
to Section25.3: I2C implementation.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUTCF</name>
<description>Timeout detection flag clear Writing 1
to this bit clears the TIMEOUT flag in the I2C_ISR
register. Note: If the SMBus feature is not
supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALERTCF</name>
<description>Alert flag clear Writing 1 to this bit
clears the ALERT flag in the I2C_ISR register. Note:
If the SMBus feature is not supported, this bit is
reserved and forced by hardware to 0. Please refer to
Section25.3: I2C implementation.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PECR</name>
<displayName>PECR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PEC</name>
<description>Packet error checking register This
field contains the internal PEC when PECEN=1. The PEC
is cleared by hardware when PE=0.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXDR</name>
<displayName>RXDR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDATA</name>
<description>8-bit receive data Data byte received
from the I2C bus.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXDR</name>
<displayName>TXDR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXDATA</name>
<description>8-bit transmit data Data byte to be
transmitted to the I2C bus. Note: These bits can be
written only when TXE=1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C1">
<name>I2C2</name>
<baseAddress>0x40005800</baseAddress>
<interrupt>
<name>I2C2_EV</name>
<description>I2C2 event interrupt</description>
<value>33</value>
</interrupt>
<interrupt>
<name>I2C2_ER</name>
<description>I2C2 error interrupt</description>
<value>34</value>
</interrupt>
</peripheral>
<peripheral>
<name>I2C3</name>
<description>I2C</description>
<groupName>I2C</groupName>
<baseAddress>0x40005C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C3_EV</name>
<description>I2C3 event interrupt</description>
<value>72</value>
</interrupt>
<interrupt>
<name>I2C3_ER</name>
<description>I2C3 error interrupt</description>
<value>73</value>
</interrupt>
<registers>
<register>
<name>I2C_CR1</name>
<displayName>I2C_CR1</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PE</name>
<description>Peripheral enable Note: When PE=0, the
I2C SCL and SDA lines are released. Internal state
machines and status bits are put back to their reset
value. When cleared, PE must be kept low for at least
3 APB clock cycles.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXIE</name>
<description>TX Interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXIE</name>
<description>RX Interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDRIE</name>
<description>Address match Interrupt enable (slave
only)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKIE</name>
<description>Not acknowledge received Interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPIE</name>
<description>STOP detection Interrupt
enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer Complete interrupt enable Note:
Any of these events will generate an interrupt:
Transfer Complete (TC) Transfer Complete Reload
(TCR)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupts enable Note: Any of
these errors generate an interrupt: Arbitration Loss
(ARLO) Bus Error detection (BERR) Overrun/Underrun
(OVR) Timeout detection (TIMEOUT) PEC error detection
(PECERR) Alert pin event detection
(ALERT)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DNF</name>
<description>Digital noise filter These bits are used
to configure the digital noise filter on SDA and SCL
input. The digital filter will filter spikes with a
length of up to DNF[3:0] * tI2CCLK ... Note: If the
analog filter is also enabled, the digital filter is
added to the analog filter. This filter can only be
programmed when the I2C is disabled (PE =
0).</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ANFOFF</name>
<description>Analog noise filter OFF Note: This bit
can only be programmed when the I2C is disabled (PE =
0).</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDMAEN</name>
<description>DMA transmission requests
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDMAEN</name>
<description>DMA reception requests
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBC</name>
<description>Slave byte control This bit is used to
enable hardware byte control in slave
mode.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOSTRETCH</name>
<description>Clock stretching disable This bit is
used to disable clock stretching in slave mode. It
must be kept cleared in master mode. Note: This bit
can only be programmed when the I2C is disabled (PE =
0).</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUPEN</name>
<description>Wakeup from Stop mode enable Note: If
the Wakeup from Stop mode feature is not supported,
this bit is reserved and forced by hardware to 0.
Please refer to Section25.3: I2C implementation.
Note: WUPEN can be set only when DNF =
0000</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCEN</name>
<description>General call enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHEN</name>
<description>SMBus Host address enable Note: If the
SMBus feature is not supported, this bit is reserved
and forced by hardware to 0. Please refer to
Section25.3: I2C implementation.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDEN</name>
<description>SMBus Device Default address enable
Note: If the SMBus feature is not supported, this bit
is reserved and forced by hardware to 0. Please refer
to Section25.3: I2C implementation.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALERTEN</name>
<description>SMBus alert enable Device mode
(SMBHEN=0): Host mode (SMBHEN=1): Note: When
ALERTEN=0, the SMBA pin can be used as a standard
GPIO. If the SMBus feature is not supported, this bit
is reserved and forced by hardware to 0. Please refer
to Section25.3: I2C implementation.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECEN</name>
<description>PEC enable Note: If the SMBus feature is
not supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_CR2</name>
<displayName>I2C_CR2</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SADD0</name>
<description>Slave address bit 0 (master mode) In
7-bit addressing mode (ADD10 = 0): This bit is dont
care In 10-bit addressing mode (ADD10 = 1): This bit
should be written with bit 0 of the slave address to
be sent Note: Changing these bits when the START bit
is set is not allowed.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD1</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD2</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD3</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD4</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD5</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD6</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD7</name>
<description>Slave address bit 7:1 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits should
be written with the 7-bit slave address to be sent In
10-bit addressing mode (ADD10 = 1): These bits should
be written with bits 7:1 of the slave address to be
sent. Note: Changing these bits when the START bit is
set is not allowed.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD8</name>
<description>Slave address bit 9:8 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits are
dont care In 10-bit addressing mode (ADD10 = 1):
These bits should be written with bits 9:8 of the
slave address to be sent Note: Changing these bits
when the START bit is set is not
allowed.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD9</name>
<description>Slave address bit 9:8 (master mode) In
7-bit addressing mode (ADD10 = 0): These bits are
dont care In 10-bit addressing mode (ADD10 = 1):
These bits should be written with bits 9:8 of the
slave address to be sent Note: Changing these bits
when the START bit is set is not
allowed.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_WRN</name>
<description>Transfer direction (master mode) Note:
Changing this bit when the START bit is set is not
allowed.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD10</name>
<description>10-bit addressing mode (master mode)
Note: Changing this bit when the START bit is set is
not allowed.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HEAD10R</name>
<description>10-bit address header only read
direction (master receiver mode) Note: Changing this
bit when the START bit is set is not
allowed.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start generation This bit is set by
software, and cleared by hardware after the Start
followed by the address sequence is sent, by an
arbitration loss, by a timeout error detection, or
when PE = 0. It can also be cleared by software by
writing 1 to the ADDRCF bit in the I2C_ICR register.
If the I2C is already in master mode with AUTOEND =
0, setting this bit generates a Repeated Start
condition when RELOAD=0, after the end of the NBYTES
transfer. Otherwise setting this bit will generate a
START condition once the bus is free. Note: Writing 0
to this bit has no effect. The START bit can be set
even if the bus is BUSY or I2C is in slave mode. This
bit has no effect when RELOAD is set.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>Stop generation (master mode) The bit is
set by software, cleared by hardware when a Stop
condition is detected, or when PE = 0. In Master
Mode: Note: Writing 0 to this bit has no
effect.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>NACK generation (slave mode) The bit is
set by software, cleared by hardware when the NACK is
sent, or when a STOP condition or an Address matched
is received, or when PE=0. Note: Writing 0 to this
bit has no effect. This bit is used in slave mode
only: in master receiver mode, NACK is automatically
generated after last byte preceding STOP or RESTART
condition, whatever the NACK bit value. When an
overrun occurs in slave receiver NOSTRETCH mode, a
NACK is automatically generated whatever the NACK bit
value. When hardware PEC checking is enabled
(PECBYTE=1), the PEC acknowledge value does not
depend on the NACK value.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBYTES</name>
<description>Number of bytes The number of bytes to
be transmitted/received is programmed there. This
field is dont care in slave mode with SBC=0. Note:
Changing these bits when the START bit is set is not
allowed.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RELOAD</name>
<description>NBYTES reload mode This bit is set and
cleared by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTOEND</name>
<description>Automatic end mode (master mode) This
bit is set and cleared by software. Note: This bit
has no effect in slave mode or when the RELOAD bit is
set.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECBYTE</name>
<description>Packet error checking byte This bit is
set by software, and cleared by hardware when the PEC
is transferred, or when a STOP condition or an
Address matched is received, also when PE=0. Note:
Writing 0 to this bit has no effect. This bit has no
effect when RELOAD is set. This bit has no effect is
slave mode when SBC=0. If the SMBus feature is not
supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_OAR1</name>
<displayName>I2C_OAR1</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OA1</name>
<description>Interface address 7-bit addressing mode:
dont care 10-bit addressing mode: bits 9:8 of address
Note: These bits can be written only when OA1EN=0.
OA1[7:1]: Interface address Bits 7:1 of address Note:
These bits can be written only when OA1EN=0. OA1[0]:
Interface address 7-bit addressing mode: dont care
10-bit addressing mode: bit 0 of address Note: This
bit can be written only when OA1EN=0.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>OA1MODE</name>
<description>Own Address 1 10-bit mode Note: This bit
can be written only when OA1EN=0.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OA1EN</name>
<description>Own Address 1 enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_OAR2</name>
<displayName>I2C_OAR2</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OA2</name>
<description>Interface address bits 7:1 of address
Note: These bits can be written only when
OA2EN=0.</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>OA2MSK</name>
<description>Own Address 2 masks Note: These bits can
be written only when OA2EN=0. As soon as OA2MSK is
not equal to 0, the reserved I2C addresses (0b0000xxx
and 0b1111xxx) are not acknowledged even if the
comparison matches.</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OA2EN</name>
<description>Own Address 2 enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_TIMINGR</name>
<displayName>I2C_TIMINGR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCLL</name>
<description>SCL low period (master mode) This field
is used to generate the SCL low period in master
mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also
used to generate tBUF and tSU:STA
timings.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SCLH</name>
<description>SCL high period (master mode) This field
is used to generate the SCL high period in master
mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also
used to generate tSU:STO and tHD:STA
timing.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SDADEL</name>
<description>Data hold time This field is used to
generate the delay tSDADEL between SCL falling edge
and SDA edge. In master mode and in slave mode with
NOSTRETCH = 0, the SCL line is stretched low during
tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is
used to generate tHD:DAT timing.</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SCLDEL</name>
<description>Data setup time This field is used to
generate a delay tSCLDEL between SDA edge and SCL
rising edge. In master mode and in slave mode with
NOSTRETCH = 0, the SCL line is stretched low during
tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL
is used to generate tSU:DAT timing.</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>Timing prescaler This field is used to
prescale I2CCLK in order to generate the clock period
tPRESC used for data setup and hold counters (refer
to I2C timings on page9) and for SCL high and low
level counters (refer to I2C master initialization on
page24). tPRESC = (PRESC+1) x tI2CCLK</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_TIMEOUTR</name>
<displayName>I2C_TIMEOUTR</displayName>
<description>Access: No wait states, except if a write
access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the
second write access until the previous one is completed.
The latency of the second write access can be up to 2 x
PCLK1 + 6 x I2CCLK.</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMEOUTA</name>
<description>Bus Timeout A This field is used to
configure: The SCL low timeout condition tTIMEOUT
when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK
The bus idle condition (both SCL and SDA high) when
TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These
bits can be written only when
TIMOUTEN=0.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TIDLE</name>
<description>Idle clock timeout detection Note: This
bit can be written only when
TIMOUTEN=0.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUTEN</name>
<description>Clock timeout enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUTB</name>
<description>Bus timeout B This field is used to
configure the cumulative clock extension timeout: In
master mode, the master cumulative clock low extend
time (tLOW:MEXT) is detected In slave mode, the slave
cumulative clock low extend time (tLOW:SEXT) is
detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK
Note: These bits can be written only when
TEXTEN=0.</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TEXTEN</name>
<description>Extended clock timeout
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_ISR</name>
<displayName>I2C_ISR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>TXE</name>
<description>Transmit data register empty
(transmitters) This bit is set by hardware when the
I2C_TXDR register is empty. It is cleared when the
next data to be sent is written in the I2C_TXDR
register. This bit can be written to 1 by software in
order to flush the transmit data register I2C_TXDR.
Note: This bit is set by hardware when
PE=0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXIS</name>
<description>Transmit interrupt status (transmitters)
This bit is set by hardware when the I2C_TXDR
register is empty and the data to be transmitted must
be written in the I2C_TXDR register. It is cleared
when the next data to be sent is written in the
I2C_TXDR register. This bit can be written to 1 by
software when NOSTRETCH=1 only, in order to generate
a TXIS event (interrupt if TXIE=1 or DMA request if
TXDMAEN=1). Note: This bit is cleared by hardware
when PE=0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXNE</name>
<description>Receive data register not empty
(receivers) This bit is set by hardware when the
received data is copied into the I2C_RXDR register,
and is ready to be read. It is cleared when I2C_RXDR
is read. Note: This bit is cleared by hardware when
PE=0.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ADDR</name>
<description>Address matched (slave mode) This bit is
set by hardware as soon as the received slave address
matched with one of the enabled slave addresses. It
is cleared by software by setting ADDRCF bit. Note:
This bit is cleared by hardware when
PE=0.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NACKF</name>
<description>Not Acknowledge received flag This flag
is set by hardware when a NACK is received after a
byte transmission. It is cleared by software by
setting the NACKCF bit. Note: This bit is cleared by
hardware when PE=0.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>STOPF</name>
<description>Stop detection flag This flag is set by
hardware when a Stop condition is detected on the bus
and the peripheral is involved in this transfer:
either as a master, provided that the STOP condition
is generated by the peripheral. or as a slave,
provided that the peripheral has been addressed
previously during this transfer. It is cleared by
software by setting the STOPCF bit. Note: This bit is
cleared by hardware when PE=0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TC</name>
<description>Transfer Complete (master mode) This
flag is set by hardware when RELOAD=0, AUTOEND=0 and
NBYTES data have been transferred. It is cleared by
software when START bit or STOP bit is set. Note:
This bit is cleared by hardware when
PE=0.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TCR</name>
<description>Transfer Complete Reload This flag is
set by hardware when RELOAD=1 and NBYTES data have
been transferred. It is cleared by software when
NBYTES is written to a non-zero value. Note: This bit
is cleared by hardware when PE=0. This flag is only
for master mode, or for slave mode when the SBC bit
is set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BERR</name>
<description>Bus error This flag is set by hardware
when a misplaced Start or Stop condition is detected
whereas the peripheral is involved in the transfer.
The flag is not set during the address phase in slave
mode. It is cleared by software by setting BERRCF
bit. Note: This bit is cleared by hardware when
PE=0.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ARLO</name>
<description>Arbitration lost This flag is set by
hardware in case of arbitration loss. It is cleared
by software by setting the ARLOCF bit. Note: This bit
is cleared by hardware when PE=0.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR</name>
<description>Overrun/Underrun (slave mode) This flag
is set by hardware in slave mode with NOSTRETCH=1,
when an overrun/underrun error occurs. It is cleared
by software by setting the OVRCF bit. Note: This bit
is cleared by hardware when PE=0.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PECERR</name>
<description>PEC Error in reception This flag is set
by hardware when the received PEC does not match with
the PEC register content. A NACK is automatically
sent after the wrong PEC reception. It is cleared by
software by setting the PECCF bit. Note: This bit is
cleared by hardware when PE=0. If the SMBus feature
is not supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout or tLOW detection flag This flag
is set by hardware when a timeout or extended clock
timeout occurred. It is cleared by software by
setting the TIMEOUTCF bit. Note: This bit is cleared
by hardware when PE=0. If the SMBus feature is not
supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ALERT</name>
<description>SMBus alert This flag is set by hardware
when SMBHEN=1 (SMBus host configuration), ALERTEN=1
and a SMBALERT event (falling edge) is detected on
SMBA pin. It is cleared by software by setting the
ALERTCF bit. Note: This bit is cleared by hardware
when PE=0. If the SMBus feature is not supported,
this bit is reserved and forced by hardware to 0.
Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BUSY</name>
<description>Bus busy This flag indicates that a
communication is in progress on the bus. It is set by
hardware when a START condition is detected. It is
cleared by hardware when a Stop condition is
detected, or when PE=0.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DIR</name>
<description>Transfer direction (Slave mode) This
flag is updated when an address match event occurs
(ADDR=1).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ADDCODE</name>
<description>Address match code (Slave mode) These
bits are updated with the received address when an
address match event occurs (ADDR = 1). In the case of
a 10-bit address, ADDCODE provides the 10-bit header
followed by the 2 MSBs of the address.</description>
<bitOffset>17</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>I2C_ICR</name>
<displayName>I2C_ICR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRCF</name>
<description>Address matched flag clear Writing 1 to
this bit clears the ADDR flag in the I2C_ISR
register. Writing 1 to this bit also clears the START
bit in the I2C_CR2 register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKCF</name>
<description>Not Acknowledge flag clear Writing 1 to
this bit clears the ACKF flag in I2C_ISR
register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPCF</name>
<description>Stop detection flag clear Writing 1 to
this bit clears the STOPF flag in the I2C_ISR
register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BERRCF</name>
<description>Bus error flag clear Writing 1 to this
bit clears the BERRF flag in the I2C_ISR
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARLOCF</name>
<description>Arbitration Lost flag clear Writing 1 to
this bit clears the ARLO flag in the I2C_ISR
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRCF</name>
<description>Overrun/Underrun flag clear Writing 1 to
this bit clears the OVR flag in the I2C_ISR
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECCF</name>
<description>PEC Error flag clear Writing 1 to this
bit clears the PECERR flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit
is reserved and forced by hardware to 0. Please refer
to Section25.3: I2C implementation.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUTCF</name>
<description>Timeout detection flag clear Writing 1
to this bit clears the TIMEOUT flag in the I2C_ISR
register. Note: If the SMBus feature is not
supported, this bit is reserved and forced by
hardware to 0. Please refer to Section25.3: I2C
implementation.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALERTCF</name>
<description>Alert flag clear Writing 1 to this bit
clears the ALERT flag in the I2C_ISR register. Note:
If the SMBus feature is not supported, this bit is
reserved and forced by hardware to 0. Please refer to
Section25.3: I2C implementation.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_PECR</name>
<displayName>I2C_PECR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PEC</name>
<description>Packet error checking register This
field contains the internal PEC when PECEN=1. The PEC
is cleared by hardware when PE=0.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_RXDR</name>
<displayName>I2C_RXDR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDATA</name>
<description>8-bit receive data Data byte received
from the I2C bus.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>I2C_TXDR</name>
<displayName>I2C_TXDR</displayName>
<description>Access: No wait states</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXDATA</name>
<description>8-bit transmit data Data byte to be
transmitted to the I2C bus. Note: These bits can be
written only when TXE=1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C3">
<name>I2C4</name>
<baseAddress>0x58001C00</baseAddress>
<interrupt>
<name>I2C4_EV</name>
<description>I2C4 event interrupt</description>
<value>95</value>
</interrupt>
<interrupt>
<name>I2C4_ER</name>
<description>I2C4 error interrupt</description>
<value>96</value>
</interrupt>
</peripheral>
<peripheral>
<name>IWDG</name>
<description>IWDG</description>
<groupName>IWDG</groupName>
<baseAddress>0x58004800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IWDG_KR</name>
<displayName>IWDG_KR</displayName>
<description>Key register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Key value (write only, read 0x0000)
These bits must be written by software at regular
intervals with the key value 0xAAAA, otherwise the
watchdog generates a reset when the counter reaches
0. Writing the key value 0x5555 to enable access to
the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see
Section23.3.6: Register access protection) Writing
the key value CCCCh starts the watchdog (except if
the hardware watchdog option is
selected)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>IWDG_PR</name>
<displayName>IWDG_PR</displayName>
<description>Prescaler register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Prescaler divider These bits are write
access protected see Section23.3.6: Register access
protection. They are written by software to select
the prescaler divider feeding the counter clock. PVU
bit of IWDG_SR must be reset in order to be able to
change the prescaler divider. Note: Reading this
register returns the prescaler value from the VDD
voltage domain. This value may not be up to
date/valid if a write operation to this register is
ongoing. For this reason the value read from this
register is valid only when the PVU bit in the
IWDG_SR register is reset.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>IWDG_RLR</name>
<displayName>IWDG_RLR</displayName>
<description>Reload register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>RL</name>
<description>Watchdog counter reload value These bits
are write access protected see Section23.3.6. They
are written by software to define the value to be
loaded in the watchdog counter each time the value
0xAAAA is written in the IWDG_KR register. The
watchdog counter counts down from this value. The
timeout period is a function of this value and the
clock prescaler. Refer to the datasheet for the
timeout information. The RVU bit in the IWDG_SR
register must be reset in order to be able to change
the reload value. Note: Reading this register returns
the reload value from the VDD voltage domain. This
value may not be up to date/valid if a write
operation to this register is ongoing on this
register. For this reason the value read from this
register is valid only when the RVU bit in the
IWDG_SR register is reset.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>IWDG_SR</name>
<displayName>IWDG_SR</displayName>
<description>Status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PVU</name>
<description>Watchdog prescaler value update This bit
is set by hardware to indicate that an update of the
prescaler value is ongoing. It is reset by hardware
when the prescaler update operation is completed in
the VDD voltage domain (takes up to 5 RC 40 kHz
cycles). Prescaler value can be updated only when PVU
bit is reset.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RVU</name>
<description>Watchdog counter reload value update
This bit is set by hardware to indicate that an
update of the reload value is ongoing. It is reset by
hardware when the reload value update operation is
completed in the VDD voltage domain (takes up to 5 RC
40 kHz cycles). Reload value can be updated only when
RVU bit is reset.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WVU</name>
<description>Watchdog counter window value update
This bit is set by hardware to indicate that an
update of the window value is ongoing. It is reset by
hardware when the reload value update operation is
completed in the VDD voltage domain (takes up to 5 RC
40 kHz cycles). Window value can be updated only when
WVU bit is reset. This bit is generated only if
generic window = 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IWDG_WINR</name>
<displayName>IWDG_WINR</displayName>
<description>Window register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>WIN</name>
<description>Watchdog counter window value These bits
are write access protected see Section23.3.6. These
bits contain the high limit of the window value to be
compared to the downcounter. To prevent a reset, the
downcounter must be reloaded when its value is lower
than the window register value and greater than 0x0
The WVU bit in the IWDG_SR register must be reset in
order to be able to change the reload value. Note:
Reading this register returns the reload value from
the VDD voltage domain. This value may not be valid
if a write operation to this register is ongoing. For
this reason the value read from this register is
valid only when the WVU bit in the IWDG_SR register
is reset.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>JPEG</name>
<description>JPEG</description>
<groupName>JPEG</groupName>
<baseAddress>0x52003000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>JPEG</name>
<description>JPEG global interrupt</description>
<value>121</value>
</interrupt>
<registers>
<register>
<name>CONFR0</name>
<displayName>CONFR0</displayName>
<description>JPEG codec control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>START</name>
<description>Start This bit start or stop the
encoding or decoding process. Read this register
always return 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONFR1</name>
<displayName>CONFR1</displayName>
<description>JPEG codec configuration register
1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NF</name>
<description>Number of color components This field
defines the number of color components minus
1.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DE</name>
<description>Decoding Enable This bit selects the
coding or decoding process</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COLORSPACE</name>
<description>Color Space This filed defines the
number of quantization tables minus 1 to insert in
the output stream.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NS</name>
<description>Number of components for Scan This field
defines the number of components minus 1 for scan
header marker segment.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HDR</name>
<description>Header Processing This bit enable the
header processing (generation/parsing).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>YSIZE</name>
<description>Y Size This field defines the number of
lines in source image.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONFR2</name>
<displayName>CONFR2</displayName>
<description>JPEG codec configuration register
2</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NMCU</name>
<description>Number of MCU For encoding: this field
defines the number of MCU units minus 1 to encode.
For decoding: this field indicates the number of
complete MCU units minus 1 to be decoded (this field
is updated after the JPEG header parsing). If the
decoded image size has not a X or Y size multiple of
8 or 16 (depending on the sub-sampling process), the
resulting incomplete or empty MCU must be added to
this value to get the total number of MCU
generated.</description>
<bitOffset>0</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONFR3</name>
<displayName>CONFR3</displayName>
<description>JPEG codec configuration register
3</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XSIZE</name>
<description>X size This field defines the number of
pixels per line.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONFRN1</name>
<displayName>CONFRN1</displayName>
<description>JPEG codec configuration register
4-7</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HD</name>
<description>Huffman DC Selects the Huffman table for
encoding the DC coefficients.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HA</name>
<description>Huffman AC Selects the Huffman table for
encoding the AC coefficients.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QT</name>
<description>Quantization Table Selects quantization
table associated with a color
component.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NB</name>
<description>Number of Block Number of data units
minus 1 that belong to a particular color in the
MCU.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VSF</name>
<description>Vertical Sampling Factor Vertical
sampling factor for component i.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HSF</name>
<description>Horizontal Sampling Factor Horizontal
sampling factor for component i.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONFRN2</name>
<displayName>CONFRN2</displayName>
<description>JPEG codec configuration register
4-7</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HD</name>
<description>Huffman DC Selects the Huffman table for
encoding the DC coefficients.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HA</name>
<description>Huffman AC Selects the Huffman table for
encoding the AC coefficients.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QT</name>
<description>Quantization Table Selects quantization
table associated with a color
component.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NB</name>
<description>Number of Block Number of data units
minus 1 that belong to a particular color in the
MCU.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VSF</name>
<description>Vertical Sampling Factor Vertical
sampling factor for component i.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HSF</name>
<description>Horizontal Sampling Factor Horizontal
sampling factor for component i.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONFRN3</name>
<displayName>CONFRN3</displayName>
<description>JPEG codec configuration register
4-7</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HD</name>
<description>Huffman DC Selects the Huffman table for
encoding the DC coefficients.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HA</name>
<description>Huffman AC Selects the Huffman table for
encoding the AC coefficients.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QT</name>
<description>Quantization Table Selects quantization
table associated with a color
component.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NB</name>
<description>Number of Block Number of data units
minus 1 that belong to a particular color in the
MCU.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VSF</name>
<description>Vertical Sampling Factor Vertical
sampling factor for component i.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HSF</name>
<description>Horizontal Sampling Factor Horizontal
sampling factor for component i.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONFRN4</name>
<displayName>CONFRN4</displayName>
<description>JPEG codec configuration register
4-7</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HD</name>
<description>Huffman DC Selects the Huffman table for
encoding the DC coefficients.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HA</name>
<description>Huffman AC Selects the Huffman table for
encoding the AC coefficients.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QT</name>
<description>Quantization Table Selects quantization
table associated with a color
component.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NB</name>
<description>Number of Block Number of data units
minus 1 that belong to a particular color in the
MCU.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VSF</name>
<description>Vertical Sampling Factor Vertical
sampling factor for component i.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HSF</name>
<description>Horizontal Sampling Factor Horizontal
sampling factor for component i.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>JPEG control register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JCEN</name>
<description>JPEG Core Enable Enable the JPEG codec
Core.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IFTIE</name>
<description>Input FIFO Threshold Interrupt Enable
This bit enables the interrupt generation when input
FIFO reach the threshold.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IFNFIE</name>
<description>Input FIFO Not Full Interrupt Enable
This bit enables the interrupt generation when input
FIFO is not empty.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFTIE</name>
<description>Output FIFO Threshold Interrupt Enable
This bit enables the interrupt generation when output
FIFO reach the threshold.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFNEIE</name>
<description>Output FIFO Not Empty Interrupt Enable
This bit enables the interrupt generation when output
FIFO is not empty.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOCIE</name>
<description>End of Conversion Interrupt Enable This
bit enables the interrupt generation on the end of
conversion.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPDIE</name>
<description>Header Parsing Done Interrupt Enable
This bit enables the interrupt generation on the
Header Parsing Operation.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDMAEN</name>
<description>Input DMA Enable Enable the DMA request
generation for the input FIFO.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODMAEN</name>
<description>Output DMA Enable Enable the DMA request
generation for the output FIFO.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IFF</name>
<description>Input FIFO Flush This bit flush the
input FIFO. This bit is always read as
0.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFF</name>
<description>Output FIFO Flush This bit flush the
output FIFO. This bit is always read as
0.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>JPEG status register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000006</resetValue>
<fields>
<field>
<name>IFTF</name>
<description>Input FIFO Threshold Flag This bit is
set when the input FIFO is not full and is bellow its
threshold.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IFNFF</name>
<description>Input FIFO Not Full Flag This bit is set
when the input FIFO is not full (a data can be
written).</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFTF</name>
<description>Output FIFO Threshold Flag This bit is
set when the output FIFO is not empty and has reach
its threshold.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFNEF</name>
<description>Output FIFO Not Empty Flag This bit is
set when the output FIFO is not empty (a data is
available).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOCF</name>
<description>End of Conversion Flag This bit is set
when the JPEG codec core has finished the encoding or
the decoding process and than last data has been sent
to the output FIFO.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPDF</name>
<description>Header Parsing Done Flag This bit is set
in decode mode when the JPEG codec has finished the
parsing of the headers and the internal registers
have been updated.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COF</name>
<description>Codec Operation Flag This bit is set
when when a JPEG codec operation is on going
(encoding or decoding).</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFR</name>
<displayName>CFR</displayName>
<description>JPEG clear flag register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEOCF</name>
<description>Clear End of Conversion Flag Writing 1
clears the End of Conversion Flag of the JPEG Status
Register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHPDF</name>
<description>Clear Header Parsing Done Flag Writing 1
clears the Header Parsing Done Flag of the JPEG
Status Register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIR</name>
<displayName>DIR</displayName>
<description>JPEG data input register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATAIN</name>
<description>Data Input FIFO Input FIFO data
register.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOR</name>
<displayName>DOR</displayName>
<description>JPEG data output register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATAOUT</name>
<description>Data Output FIFO Output FIFO data
register.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPTIM1</name>
<description>Low power timer</description>
<groupName>LPTIM</groupName>
<baseAddress>0x40002400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTIM1</name>
<description>LPTIM1 global interrupt</description>
<value>93</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt and Status Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWN</name>
<description>Counter direction change up to
down</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UP</name>
<description>Counter direction change down to
up</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROK</name>
<description>Autoreload register update
OK</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOK</name>
<description>Compare register update OK</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIG</name>
<description>External trigger edge
event</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRM</name>
<description>Autoreload match</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM</name>
<description>Compare match</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt Clear Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWNCF</name>
<description>Direction change to down Clear
Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPCF</name>
<description>Direction change to UP Clear
Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROKCF</name>
<description>Autoreload register update OK Clear
Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOKCF</name>
<description>Compare register update OK Clear
Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIGCF</name>
<description>External trigger valid edge Clear
Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRMCF</name>
<description>Autoreload match Clear
Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPMCF</name>
<description>compare match Clear Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>Interrupt Enable Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWNIE</name>
<description>Direction change to down Interrupt
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPIE</name>
<description>Direction change to UP Interrupt
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROKIE</name>
<description>Autoreload register update OK Interrupt
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOKIE</name>
<description>Compare register update OK Interrupt
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIGIE</name>
<description>External trigger valid edge Interrupt
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRMIE</name>
<description>Autoreload match Interrupt
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPMIE</name>
<description>Compare match Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>Configuration Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENC</name>
<description>Encoder mode enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTMODE</name>
<description>counter mode enabled</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRELOAD</name>
<description>Registers update mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVPOL</name>
<description>Waveform shape polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVE</name>
<description>Waveform shape</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUT</name>
<description>Timeout enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIGEN</name>
<description>Trigger enable and
polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRIGSEL</name>
<description>Trigger selector</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>Clock prescaler</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TRGFLT</name>
<description>Configurable digital filter for
trigger</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKFLT</name>
<description>Configurable digital filter for external
clock</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKPOL</name>
<description>Clock Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKSEL</name>
<description>Clock selector</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>LPTIM Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNGSTRT</name>
<description>LPTIM start in single mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNTSTRT</name>
<description>Timer start in continuous
mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTRST</name>
<description>Counter reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTARE</name>
<description>Reset after read enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP</name>
<displayName>CMP</displayName>
<description>Compare Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP</name>
<description>Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>Autoreload Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>Counter Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>LPTIM_CFGR2</name>
<displayName>LPTIM_CFGR2</displayName>
<description>LPTIM configuration register 2</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN1SEL</name>
<description>LPTIM Input 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IN2SEL</name>
<description>LPTIM Input 2 selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="LPTIM1">
<name>LPTIM2</name>
<baseAddress>0x58002400</baseAddress>
</peripheral>
<peripheral>
<name>LPTIM3</name>
<description>Low power timer</description>
<groupName>LPTIM</groupName>
<baseAddress>0x58002800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTIM2</name>
<description>LPTIM2 timer interrupt</description>
<value>138</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt and Status Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWN</name>
<description>Counter direction change up to
down</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UP</name>
<description>Counter direction change down to
up</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROK</name>
<description>Autoreload register update
OK</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOK</name>
<description>Compare register update OK</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIG</name>
<description>External trigger edge
event</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRM</name>
<description>Autoreload match</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM</name>
<description>Compare match</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt Clear Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWNCF</name>
<description>Direction change to down Clear
Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPCF</name>
<description>Direction change to UP Clear
Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROKCF</name>
<description>Autoreload register update OK Clear
Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOKCF</name>
<description>Compare register update OK Clear
Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIGCF</name>
<description>External trigger valid edge Clear
Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRMCF</name>
<description>Autoreload match Clear
Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPMCF</name>
<description>compare match Clear Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>Interrupt Enable Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWNIE</name>
<description>Direction change to down Interrupt
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPIE</name>
<description>Direction change to UP Interrupt
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROKIE</name>
<description>Autoreload register update OK Interrupt
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOKIE</name>
<description>Compare register update OK Interrupt
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIGIE</name>
<description>External trigger valid edge Interrupt
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRMIE</name>
<description>Autoreload match Interrupt
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPMIE</name>
<description>Compare match Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>Configuration Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENC</name>
<description>Encoder mode enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTMODE</name>
<description>counter mode enabled</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRELOAD</name>
<description>Registers update mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVPOL</name>
<description>Waveform shape polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVE</name>
<description>Waveform shape</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUT</name>
<description>Timeout enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIGEN</name>
<description>Trigger enable and
polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRIGSEL</name>
<description>Trigger selector</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>Clock prescaler</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TRGFLT</name>
<description>Configurable digital filter for
trigger</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKFLT</name>
<description>Configurable digital filter for external
clock</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKPOL</name>
<description>Clock Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKSEL</name>
<description>Clock selector</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>LPTIM Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNGSTRT</name>
<description>LPTIM start in single mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNTSTRT</name>
<description>Timer start in continuous
mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTRST</name>
<description>Counter reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSTARE</name>
<description>Reset after read enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP</name>
<displayName>CMP</displayName>
<description>Compare Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP</name>
<description>Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>Autoreload Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>Counter Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>LPTIM_CFGR2</name>
<displayName>LPTIM_CFGR2</displayName>
<description>LPTIM configuration register 2</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN1SEL</name>
<description>LPTIM Input 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPUART1</name>
<description>LPUART1</description>
<groupName>LPUART</groupName>
<baseAddress>0x58000C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTIM3</name>
<description>LPTIM2 timer interrupt</description>
<value>139</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFIFO Full interrupt
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFIFO empty interrupt
enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFO mode enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>Word length</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT</name>
<description>Driver Enable assertion
time</description>
<bitOffset>21</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DEDT</name>
<description>Driver Enable deassertion
time</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level
inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level
inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address
Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFIFO threshold
configuration</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFIFO threshold interrupt
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>Receive FIFO threshold
configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFIFO threshold interrupt
enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt
enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag
selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception
Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BRR</name>
<description>BRR</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush
request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00C0</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFIFO threshold flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFIFO threshold flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFIFO Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFIFO Empty</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NE</name>
<description>NE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear
flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear
flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>Prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LTDC</name>
<description>LCD-TFT Controller</description>
<groupName>LTDC</groupName>
<baseAddress>0x50001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SSCR</name>
<displayName>SSCR</displayName>
<description>Synchronization Size Configuration
Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HSW</name>
<description>Horizontal Synchronization Width (in
units of pixel clock period)</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>VSH</name>
<description>Vertical Synchronization Height (in
units of horizontal scan line)</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>BPCR</name>
<displayName>BPCR</displayName>
<description>Back Porch Configuration
Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHBP</name>
<description>Accumulated Horizontal back porch (in
units of pixel clock period)</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>AVBP</name>
<description>Accumulated Vertical back porch (in
units of horizontal scan line)</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWCR</name>
<displayName>AWCR</displayName>
<description>Active Width Configuration
Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AAV</name>
<description>AAV</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>AAH</name>
<description>Accumulated Active Height (in units of
horizontal scan line)</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>TWCR</name>
<displayName>TWCR</displayName>
<description>Total Width Configuration
Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOTALW</name>
<description>Total Width (in units of pixel clock
period)</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TOTALH</name>
<description>Total Height (in units of horizontal
scan line)</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>GCR</name>
<displayName>GCR</displayName>
<description>Global Control Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00002220</resetValue>
<fields>
<field>
<name>HSPOL</name>
<description>Horizontal Synchronization
Polarity</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VSPOL</name>
<description>Vertical Synchronization
Polarity</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DEPOL</name>
<description>Data Enable Polarity</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PCPOL</name>
<description>Pixel Clock Polarity</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DEN</name>
<description>Dither Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DRW</name>
<description>Dither Red Width</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DGW</name>
<description>Dither Green Width</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DBW</name>
<description>Dither Blue Width</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LTDCEN</name>
<description>LCD-TFT controller enable
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRCR</name>
<displayName>SRCR</displayName>
<description>Shadow Reload Configuration
Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VBR</name>
<description>Vertical Blanking Reload</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IMR</name>
<description>Immediate Reload</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCCR</name>
<displayName>BCCR</displayName>
<description>Background Color Configuration
Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BCBLUE</name>
<description>Background Color Blue
value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BCGREEN</name>
<description>Background Color Green
value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BCRED</name>
<description>Background Color Red value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>Interrupt Enable Register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RRIE</name>
<description>Register Reload interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TERRIE</name>
<description>Transfer Error Interrupt
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUIE</name>
<description>FIFO Underrun Interrupt
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LIE</name>
<description>Line Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt Status Register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RRIF</name>
<description>Register Reload Interrupt
Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TERRIF</name>
<description>Transfer Error interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUIF</name>
<description>FIFO Underrun Interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LIF</name>
<description>Line Interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt Clear Register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRRIF</name>
<description>Clears Register Reload Interrupt
Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTERRIF</name>
<description>Clears the Transfer Error Interrupt
Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFUIF</name>
<description>Clears the FIFO Underrun Interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLIF</name>
<description>Clears the Line Interrupt
Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LIPCR</name>
<displayName>LIPCR</displayName>
<description>Line Interrupt Position Configuration
Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LIPOS</name>
<description>Line Interrupt Position</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPSR</name>
<displayName>CPSR</displayName>
<description>Current Position Status
Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CXPOS</name>
<description>Current X Position</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CYPOS</name>
<description>Current Y Position</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDSR</name>
<displayName>CDSR</displayName>
<description>Current Display Status
Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000000F</resetValue>
<fields>
<field>
<name>HSYNCS</name>
<description>Horizontal Synchronization display
Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNCS</name>
<description>Vertical Synchronization display
Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDES</name>
<description>Horizontal Data Enable display
Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VDES</name>
<description>Vertical Data Enable display
Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1CR</name>
<displayName>L1CR</displayName>
<description>Layerx Control Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLUTEN</name>
<description>Color Look-Up Table Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COLKEN</name>
<description>Color Keying Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LEN</name>
<description>Layer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1WHPCR</name>
<displayName>L1WHPCR</displayName>
<description>Layerx Window Horizontal Position
Configuration Register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WHSPPOS</name>
<description>Window Horizontal Stop
Position</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>WHSTPOS</name>
<description>Window Horizontal Start
Position</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1WVPCR</name>
<displayName>L1WVPCR</displayName>
<description>Layerx Window Vertical Position
Configuration Register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WVSPPOS</name>
<description>Window Vertical Stop
Position</description>
<bitOffset>16</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>WVSTPOS</name>
<description>Window Vertical Start
Position</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1CKCR</name>
<displayName>L1CKCR</displayName>
<description>Layerx Color Keying Configuration
Register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CKRED</name>
<description>Color Key Red value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CKGREEN</name>
<description>Color Key Green value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CKBLUE</name>
<description>Color Key Blue value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1PFCR</name>
<displayName>L1PFCR</displayName>
<description>Layerx Pixel Format Configuration
Register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PF</name>
<description>Pixel Format</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1CACR</name>
<displayName>L1CACR</displayName>
<description>Layerx Constant Alpha Configuration
Register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CONSTA</name>
<description>Constant Alpha</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1DCCR</name>
<displayName>L1DCCR</displayName>
<description>Layerx Default Color Configuration
Register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCALPHA</name>
<description>Default Color Alpha</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DCRED</name>
<description>Default Color Red</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DCGREEN</name>
<description>Default Color Green</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DCBLUE</name>
<description>Default Color Blue</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1BFCR</name>
<displayName>L1BFCR</displayName>
<description>Layerx Blending Factors Configuration
Register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000607</resetValue>
<fields>
<field>
<name>BF1</name>
<description>Blending Factor 1</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>BF2</name>
<description>Blending Factor 2</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1CFBAR</name>
<displayName>L1CFBAR</displayName>
<description>Layerx Color Frame Buffer Address
Register</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBADD</name>
<description>Color Frame Buffer Start
Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1CFBLR</name>
<displayName>L1CFBLR</displayName>
<description>Layerx Color Frame Buffer Length
Register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBP</name>
<description>Color Frame Buffer Pitch in
bytes</description>
<bitOffset>16</bitOffset>
<bitWidth>13</bitWidth>
</field>
<field>
<name>CFBLL</name>
<description>Color Frame Buffer Line
Length</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1CFBLNR</name>
<displayName>L1CFBLNR</displayName>
<description>Layerx ColorFrame Buffer Line Number
Register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBLNBR</name>
<description>Frame Buffer Line Number</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>L1CLUTWR</name>
<displayName>L1CLUTWR</displayName>
<description>Layerx CLUT Write Register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLUTADD</name>
<description>CLUT Address</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RED</name>
<description>Red value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>Green value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BLUE</name>
<description>Blue value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2CR</name>
<displayName>L2CR</displayName>
<description>Layerx Control Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLUTEN</name>
<description>Color Look-Up Table Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COLKEN</name>
<description>Color Keying Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LEN</name>
<description>Layer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2WHPCR</name>
<displayName>L2WHPCR</displayName>
<description>Layerx Window Horizontal Position
Configuration Register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WHSPPOS</name>
<description>Window Horizontal Stop
Position</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>WHSTPOS</name>
<description>Window Horizontal Start
Position</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2WVPCR</name>
<displayName>L2WVPCR</displayName>
<description>Layerx Window Vertical Position
Configuration Register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WVSPPOS</name>
<description>Window Vertical Stop
Position</description>
<bitOffset>16</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>WVSTPOS</name>
<description>Window Vertical Start
Position</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2CKCR</name>
<displayName>L2CKCR</displayName>
<description>Layerx Color Keying Configuration
Register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CKRED</name>
<description>Color Key Red value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CKGREEN</name>
<description>Color Key Green value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CKBLUE</name>
<description>Color Key Blue value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2PFCR</name>
<displayName>L2PFCR</displayName>
<description>Layerx Pixel Format Configuration
Register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PF</name>
<description>Pixel Format</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2CACR</name>
<displayName>L2CACR</displayName>
<description>Layerx Constant Alpha Configuration
Register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CONSTA</name>
<description>Constant Alpha</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2DCCR</name>
<displayName>L2DCCR</displayName>
<description>Layerx Default Color Configuration
Register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCALPHA</name>
<description>Default Color Alpha</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DCRED</name>
<description>Default Color Red</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DCGREEN</name>
<description>Default Color Green</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DCBLUE</name>
<description>Default Color Blue</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2BFCR</name>
<displayName>L2BFCR</displayName>
<description>Layerx Blending Factors Configuration
Register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000607</resetValue>
<fields>
<field>
<name>BF1</name>
<description>Blending Factor 1</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>BF2</name>
<description>Blending Factor 2</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2CFBAR</name>
<displayName>L2CFBAR</displayName>
<description>Layerx Color Frame Buffer Address
Register</description>
<addressOffset>0x12C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBADD</name>
<description>Color Frame Buffer Start
Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2CFBLR</name>
<displayName>L2CFBLR</displayName>
<description>Layerx Color Frame Buffer Length
Register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBP</name>
<description>Color Frame Buffer Pitch in
bytes</description>
<bitOffset>16</bitOffset>
<bitWidth>13</bitWidth>
</field>
<field>
<name>CFBLL</name>
<description>Color Frame Buffer Line
Length</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2CFBLNR</name>
<displayName>L2CFBLNR</displayName>
<description>Layerx ColorFrame Buffer Line Number
Register</description>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBLNBR</name>
<description>Frame Buffer Line Number</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>L2CLUTWR</name>
<displayName>L2CLUTWR</displayName>
<description>Layerx CLUT Write Register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLUTADD</name>
<description>CLUT Address</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RED</name>
<description>Red value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>Green value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BLUE</name>
<description>Blue value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MDIOS</name>
<description>Management data input/output slave</description>
<groupName>MDIOS</groupName>
<baseAddress>0x40009400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MDIOS_CR</name>
<displayName>MDIOS_CR</displayName>
<description>MDIOS configuration register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>Peripheral enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRIE</name>
<description>Register write interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDIE</name>
<description>Register Read Interrupt
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DPC</name>
<description>Disable Preamble Check</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PORT_ADDRESS</name>
<description>Slaves's address</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_WRFR</name>
<displayName>MDIOS_WRFR</displayName>
<description>MDIOS write flag register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WRF</name>
<description>Write flags for MDIO registers 0 to
31</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_CWRFR</name>
<displayName>MDIOS_CWRFR</displayName>
<description>MDIOS clear write flag
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CWRF</name>
<description>Clear the write flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_RDFR</name>
<displayName>MDIOS_RDFR</displayName>
<description>MDIOS read flag register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDF</name>
<description>Read flags for MDIO registers 0 to
31</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_CRDFR</name>
<displayName>MDIOS_CRDFR</displayName>
<description>MDIOS clear read flag register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRDF</name>
<description>Clear the read flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_SR</name>
<displayName>MDIOS_SR</displayName>
<description>MDIOS status register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERF</name>
<description>Preamble error flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SERF</name>
<description>Start error flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TERF</name>
<description>Turnaround error flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_CLRFR</name>
<displayName>MDIOS_CLRFR</displayName>
<description>MDIOS clear flag register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPERF</name>
<description>Clear the preamble error
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSERF</name>
<description>Clear the start error flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTERF</name>
<description>Clear the turnaround error
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR0</name>
<displayName>MDIOS_DINR0</displayName>
<description>MDIOS input data register 0</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN0</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR1</name>
<displayName>MDIOS_DINR1</displayName>
<description>MDIOS input data register 1</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN1</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR2</name>
<displayName>MDIOS_DINR2</displayName>
<description>MDIOS input data register 2</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN2</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR3</name>
<displayName>MDIOS_DINR3</displayName>
<description>MDIOS input data register 3</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN3</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR4</name>
<displayName>MDIOS_DINR4</displayName>
<description>MDIOS input data register 4</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN4</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR5</name>
<displayName>MDIOS_DINR5</displayName>
<description>MDIOS input data register 5</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN5</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR6</name>
<displayName>MDIOS_DINR6</displayName>
<description>MDIOS input data register 6</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN6</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR7</name>
<displayName>MDIOS_DINR7</displayName>
<description>MDIOS input data register 7</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN7</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR8</name>
<displayName>MDIOS_DINR8</displayName>
<description>MDIOS input data register 8</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN8</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR9</name>
<displayName>MDIOS_DINR9</displayName>
<description>MDIOS input data register 9</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN9</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR10</name>
<displayName>MDIOS_DINR10</displayName>
<description>MDIOS input data register 10</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN10</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR11</name>
<displayName>MDIOS_DINR11</displayName>
<description>MDIOS input data register 11</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN11</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR12</name>
<displayName>MDIOS_DINR12</displayName>
<description>MDIOS input data register 12</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN12</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR13</name>
<displayName>MDIOS_DINR13</displayName>
<description>MDIOS input data register 13</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN13</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR14</name>
<displayName>MDIOS_DINR14</displayName>
<description>MDIOS input data register 14</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN14</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR15</name>
<displayName>MDIOS_DINR15</displayName>
<description>MDIOS input data register 15</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN15</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR16</name>
<displayName>MDIOS_DINR16</displayName>
<description>MDIOS input data register 16</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN16</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR17</name>
<displayName>MDIOS_DINR17</displayName>
<description>MDIOS input data register 17</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN17</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR18</name>
<displayName>MDIOS_DINR18</displayName>
<description>MDIOS input data register 18</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN18</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR19</name>
<displayName>MDIOS_DINR19</displayName>
<description>MDIOS input data register 19</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN19</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR20</name>
<displayName>MDIOS_DINR20</displayName>
<description>MDIOS input data register 20</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN20</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR21</name>
<displayName>MDIOS_DINR21</displayName>
<description>MDIOS input data register 21</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN21</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR22</name>
<displayName>MDIOS_DINR22</displayName>
<description>MDIOS input data register 22</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN22</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR23</name>
<displayName>MDIOS_DINR23</displayName>
<description>MDIOS input data register 23</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN23</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR24</name>
<displayName>MDIOS_DINR24</displayName>
<description>MDIOS input data register 24</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN24</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR25</name>
<displayName>MDIOS_DINR25</displayName>
<description>MDIOS input data register 25</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN25</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR26</name>
<displayName>MDIOS_DINR26</displayName>
<description>MDIOS input data register 26</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN26</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR27</name>
<displayName>MDIOS_DINR27</displayName>
<description>MDIOS input data register 27</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN27</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR28</name>
<displayName>MDIOS_DINR28</displayName>
<description>MDIOS input data register 28</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN28</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR29</name>
<displayName>MDIOS_DINR29</displayName>
<description>MDIOS input data register 29</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN29</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR30</name>
<displayName>MDIOS_DINR30</displayName>
<description>MDIOS input data register 30</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN30</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DINR31</name>
<displayName>MDIOS_DINR31</displayName>
<description>MDIOS input data register 31</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIN31</name>
<description>Input data received from MDIO Master
during write frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR0</name>
<displayName>MDIOS_DOUTR0</displayName>
<description>MDIOS output data register 0</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT0</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR1</name>
<displayName>MDIOS_DOUTR1</displayName>
<description>MDIOS output data register 1</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT1</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR2</name>
<displayName>MDIOS_DOUTR2</displayName>
<description>MDIOS output data register 2</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT2</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR3</name>
<displayName>MDIOS_DOUTR3</displayName>
<description>MDIOS output data register 3</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT3</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR4</name>
<displayName>MDIOS_DOUTR4</displayName>
<description>MDIOS output data register 4</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT4</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR5</name>
<displayName>MDIOS_DOUTR5</displayName>
<description>MDIOS output data register 5</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT5</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR6</name>
<displayName>MDIOS_DOUTR6</displayName>
<description>MDIOS output data register 6</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT6</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR7</name>
<displayName>MDIOS_DOUTR7</displayName>
<description>MDIOS output data register 7</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT7</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR8</name>
<displayName>MDIOS_DOUTR8</displayName>
<description>MDIOS output data register 8</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT8</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR9</name>
<displayName>MDIOS_DOUTR9</displayName>
<description>MDIOS output data register 9</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT9</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR10</name>
<displayName>MDIOS_DOUTR10</displayName>
<description>MDIOS output data register 10</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT10</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR11</name>
<displayName>MDIOS_DOUTR11</displayName>
<description>MDIOS output data register 11</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT11</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR12</name>
<displayName>MDIOS_DOUTR12</displayName>
<description>MDIOS output data register 12</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT12</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR13</name>
<displayName>MDIOS_DOUTR13</displayName>
<description>MDIOS output data register 13</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT13</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR14</name>
<displayName>MDIOS_DOUTR14</displayName>
<description>MDIOS output data register 14</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT14</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR15</name>
<displayName>MDIOS_DOUTR15</displayName>
<description>MDIOS output data register 15</description>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT15</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR16</name>
<displayName>MDIOS_DOUTR16</displayName>
<description>MDIOS output data register 16</description>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT16</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR17</name>
<displayName>MDIOS_DOUTR17</displayName>
<description>MDIOS output data register 17</description>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT17</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR18</name>
<displayName>MDIOS_DOUTR18</displayName>
<description>MDIOS output data register 18</description>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT18</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR19</name>
<displayName>MDIOS_DOUTR19</displayName>
<description>MDIOS output data register 19</description>
<addressOffset>0xE8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT19</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR20</name>
<displayName>MDIOS_DOUTR20</displayName>
<description>MDIOS output data register 20</description>
<addressOffset>0xEC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT20</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR21</name>
<displayName>MDIOS_DOUTR21</displayName>
<description>MDIOS output data register 21</description>
<addressOffset>0xF0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT21</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR22</name>
<displayName>MDIOS_DOUTR22</displayName>
<description>MDIOS output data register 22</description>
<addressOffset>0xF4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT22</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR23</name>
<displayName>MDIOS_DOUTR23</displayName>
<description>MDIOS output data register 23</description>
<addressOffset>0xF8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT23</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR24</name>
<displayName>MDIOS_DOUTR24</displayName>
<description>MDIOS output data register 24</description>
<addressOffset>0xFC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT24</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR25</name>
<displayName>MDIOS_DOUTR25</displayName>
<description>MDIOS output data register 25</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT25</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR26</name>
<displayName>MDIOS_DOUTR26</displayName>
<description>MDIOS output data register 26</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT26</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR27</name>
<displayName>MDIOS_DOUTR27</displayName>
<description>MDIOS output data register 27</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT27</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR28</name>
<displayName>MDIOS_DOUTR28</displayName>
<description>MDIOS output data register 28</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT28</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR29</name>
<displayName>MDIOS_DOUTR29</displayName>
<description>MDIOS output data register 29</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT29</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR30</name>
<displayName>MDIOS_DOUTR30</displayName>
<description>MDIOS output data register 30</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT30</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MDIOS_DOUTR31</name>
<displayName>MDIOS_DOUTR31</displayName>
<description>MDIOS output data register 31</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOUT31</name>
<description>Output data sent to MDIO Master during
read frames</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MDMA</name>
<description>MDMA</description>
<groupName>MDMA</groupName>
<baseAddress>0x52000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MDMA</name>
<description>MDMA</description>
<value>122</value>
</interrupt>
<registers>
<register>
<name>GISR0</name>
<displayName>GISR0</displayName>
<description>MDMA Global Interrupt/Status
Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GIF0</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF1</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF2</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF3</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF4</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF5</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF6</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF7</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF8</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF9</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF10</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF11</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF12</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF13</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF14</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF15</name>
<description>Channel x global interrupt flag (x=...)
This bit is set and reset by hardware. It is a
logical OR of all the Channel x interrupt flags
(CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in
the interrupt mask register (CTCIEx, BTIEx, BRTIEx,
TEIEx)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0ISR</name>
<displayName>C0ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF0</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF0</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF0</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF0</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF0</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA0</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0IFCR</name>
<displayName>C0IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF0</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF0</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF0</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF0</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF0</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0ESR</name>
<displayName>C0ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0CR</name>
<displayName>C0CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C0TCR</name>
<displayName>C0TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0BNDTR</name>
<displayName>C0BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0SAR</name>
<displayName>C0SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0DAR</name>
<displayName>C0DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0BRUR</name>
<displayName>C0BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0LAR</name>
<displayName>C0LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0TBR</name>
<displayName>C0TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0MAR</name>
<displayName>C0MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C0MDR</name>
<displayName>C0MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1ISR</name>
<displayName>C1ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF1</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF1</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF1</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF1</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF1</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA1</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1IFCR</name>
<displayName>C1IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF1</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF1</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF1</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF1</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF1</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1ESR</name>
<displayName>C1ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1CR</name>
<displayName>C1CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C1TCR</name>
<displayName>C1TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1BNDTR</name>
<displayName>C1BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1SAR</name>
<displayName>C1SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1DAR</name>
<displayName>C1DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1BRUR</name>
<displayName>C1BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1LAR</name>
<displayName>C1LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1TBR</name>
<displayName>C1TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1MAR</name>
<displayName>C1MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1MDR</name>
<displayName>C1MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2ISR</name>
<displayName>C2ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF2</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF2</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF2</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF2</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF2</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA2</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2IFCR</name>
<displayName>C2IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF2</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF2</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF2</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF2</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF2</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2ESR</name>
<displayName>C2ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CR</name>
<displayName>C2CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C2TCR</name>
<displayName>C2TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2BNDTR</name>
<displayName>C2BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2SAR</name>
<displayName>C2SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2DAR</name>
<displayName>C2DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2BRUR</name>
<displayName>C2BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2LAR</name>
<displayName>C2LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2TBR</name>
<displayName>C2TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0xE8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2MAR</name>
<displayName>C2MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0xF0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2MDR</name>
<displayName>C2MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0xF4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3ISR</name>
<displayName>C3ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF3</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF3</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF3</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF3</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF3</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA3</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3IFCR</name>
<displayName>C3IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF3</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF3</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF3</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF3</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF3</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3ESR</name>
<displayName>C3ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3CR</name>
<displayName>C3CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C3TCR</name>
<displayName>C3TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3BNDTR</name>
<displayName>C3BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3SAR</name>
<displayName>C3SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3DAR</name>
<displayName>C3DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3BRUR</name>
<displayName>C3BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3LAR</name>
<displayName>C3LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x124</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3TBR</name>
<displayName>C3TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3MAR</name>
<displayName>C3MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3MDR</name>
<displayName>C3MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4ISR</name>
<displayName>C4ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF4</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF4</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF4</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF4</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF4</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA4</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4IFCR</name>
<displayName>C4IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF4</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF4</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF4</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF4</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF4</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4ESR</name>
<displayName>C4ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4CR</name>
<displayName>C4CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x14C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C4TCR</name>
<displayName>C4TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4BNDTR</name>
<displayName>C4BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x154</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4SAR</name>
<displayName>C4SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x158</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4DAR</name>
<displayName>C4DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x15C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4BRUR</name>
<displayName>C4BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4LAR</name>
<displayName>C4LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x164</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4TBR</name>
<displayName>C4TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x168</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4MAR</name>
<displayName>C4MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x170</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4MDR</name>
<displayName>C4MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x174</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5ISR</name>
<displayName>C5ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF5</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF5</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF5</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF5</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF5</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA5</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5IFCR</name>
<displayName>C5IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF5</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF5</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF5</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF5</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF5</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5ESR</name>
<displayName>C5ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x188</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5CR</name>
<displayName>C5CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x18C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C5TCR</name>
<displayName>C5TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x190</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5BNDTR</name>
<displayName>C5BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x194</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5SAR</name>
<displayName>C5SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x198</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5DAR</name>
<displayName>C5DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x19C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5BRUR</name>
<displayName>C5BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x1A0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5LAR</name>
<displayName>C5LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x1A4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5TBR</name>
<displayName>C5TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x1A8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5MAR</name>
<displayName>C5MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x1B0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5MDR</name>
<displayName>C5MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x1B4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6ISR</name>
<displayName>C6ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x1C0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF6</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF6</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF6</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF6</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF6</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA6</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6IFCR</name>
<displayName>C6IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x1C4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF6</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF6</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF6</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF6</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF6</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6ESR</name>
<displayName>C6ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x1C8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6CR</name>
<displayName>C6CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x1CC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C6TCR</name>
<displayName>C6TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x1D0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6BNDTR</name>
<displayName>C6BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x1D4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6SAR</name>
<displayName>C6SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x1D8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6DAR</name>
<displayName>C6DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x1DC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6BRUR</name>
<displayName>C6BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x1E0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6LAR</name>
<displayName>C6LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x1E4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6TBR</name>
<displayName>C6TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x1E8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6MAR</name>
<displayName>C6MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x1F0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6MDR</name>
<displayName>C6MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x1F4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7ISR</name>
<displayName>C7ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF7</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF7</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF7</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF7</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF7</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA7</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7IFCR</name>
<displayName>C7IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x204</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF7</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF7</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF7</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF7</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF7</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7ESR</name>
<displayName>C7ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x208</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7CR</name>
<displayName>C7CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x20C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C7TCR</name>
<displayName>C7TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x210</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7BNDTR</name>
<displayName>C7BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x214</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7SAR</name>
<displayName>C7SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x218</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7DAR</name>
<displayName>C7DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x21C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7BRUR</name>
<displayName>C7BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x220</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7LAR</name>
<displayName>C7LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x224</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7TBR</name>
<displayName>C7TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x228</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7MAR</name>
<displayName>C7MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x230</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7MDR</name>
<displayName>C7MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x234</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8ISR</name>
<displayName>C8ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x240</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF8</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF8</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF8</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF8</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF8</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA8</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8IFCR</name>
<displayName>C8IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x244</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF8</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF8</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF8</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF8</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF8</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8ESR</name>
<displayName>C8ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x248</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8CR</name>
<displayName>C8CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x24C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C8TCR</name>
<displayName>C8TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x250</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8BNDTR</name>
<displayName>C8BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x254</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8SAR</name>
<displayName>C8SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x258</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8DAR</name>
<displayName>C8DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x25C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8BRUR</name>
<displayName>C8BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x260</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8LAR</name>
<displayName>C8LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x264</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8TBR</name>
<displayName>C8TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x268</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8MAR</name>
<displayName>C8MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x270</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8MDR</name>
<displayName>C8MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x274</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9ISR</name>
<displayName>C9ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x280</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF9</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF9</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF9</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF9</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF9</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA9</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9IFCR</name>
<displayName>C9IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x284</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF9</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF9</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF9</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF9</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF9</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9ESR</name>
<displayName>C9ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x288</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9CR</name>
<displayName>C9CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x28C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C9TCR</name>
<displayName>C9TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x290</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9BNDTR</name>
<displayName>C9BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x294</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9SAR</name>
<displayName>C9SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x298</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9DAR</name>
<displayName>C9DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x29C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9BRUR</name>
<displayName>C9BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x2A0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9LAR</name>
<displayName>C9LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x2A4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9TBR</name>
<displayName>C9TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x2A8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9MAR</name>
<displayName>C9MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x2B0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9MDR</name>
<displayName>C9MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x2B4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10ISR</name>
<displayName>C10ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x2C0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF10</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF10</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF10</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF10</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF10</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA10</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10IFCR</name>
<displayName>C10IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x2C4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF10</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF10</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF10</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF10</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF10</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10ESR</name>
<displayName>C10ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x2C8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10CR</name>
<displayName>C10CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x2CC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C10TCR</name>
<displayName>C10TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x2D0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10BNDTR</name>
<displayName>C10BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x2D4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10SAR</name>
<displayName>C10SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x2D8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10DAR</name>
<displayName>C10DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x2DC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10BRUR</name>
<displayName>C10BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x2E0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10LAR</name>
<displayName>C10LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x2E4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10TBR</name>
<displayName>C10TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x2E8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10MAR</name>
<displayName>C10MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x2F0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10MDR</name>
<displayName>C10MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x2F4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11ISR</name>
<displayName>C11ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF11</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF11</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF11</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF11</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF11</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA11</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11IFCR</name>
<displayName>C11IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x304</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF11</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF11</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF11</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF11</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF11</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11ESR</name>
<displayName>C11ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x308</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11CR</name>
<displayName>C11CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x30C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C11TCR</name>
<displayName>C11TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x310</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11BNDTR</name>
<displayName>C11BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x314</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11SAR</name>
<displayName>C11SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x318</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11DAR</name>
<displayName>C11DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x31C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11BRUR</name>
<displayName>C11BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x320</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11LAR</name>
<displayName>C11LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x324</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11TBR</name>
<displayName>C11TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x328</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11MAR</name>
<displayName>C11MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x330</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11MDR</name>
<displayName>C11MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x334</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12ISR</name>
<displayName>C12ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x340</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF12</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF12</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF12</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF12</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF12</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA12</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12IFCR</name>
<displayName>C12IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x344</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF12</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF12</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF12</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF12</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF12</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12ESR</name>
<displayName>C12ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x348</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12CR</name>
<displayName>C12CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x34C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C12TCR</name>
<displayName>C12TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x350</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12BNDTR</name>
<displayName>C12BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x354</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12SAR</name>
<displayName>C12SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x358</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12DAR</name>
<displayName>C12DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x35C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12BRUR</name>
<displayName>C12BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x360</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12LAR</name>
<displayName>C12LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x364</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12TBR</name>
<displayName>C12TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x368</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12MAR</name>
<displayName>C12MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x370</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12MDR</name>
<displayName>C12MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x374</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13ISR</name>
<displayName>C13ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x380</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF13</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF13</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF13</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF13</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF13</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA13</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13IFCR</name>
<displayName>C13IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x384</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF13</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF13</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF13</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF13</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF13</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13ESR</name>
<displayName>C13ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x388</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13CR</name>
<displayName>C13CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x38C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C13TCR</name>
<displayName>C13TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x390</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13BNDTR</name>
<displayName>C13BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x394</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13SAR</name>
<displayName>C13SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x398</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13DAR</name>
<displayName>C13DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x39C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13BRUR</name>
<displayName>C13BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x3A0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13LAR</name>
<displayName>C13LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x3A4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13TBR</name>
<displayName>C13TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x3A8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13MAR</name>
<displayName>C13MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x3B0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13MDR</name>
<displayName>C13MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x3B4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14ISR</name>
<displayName>C14ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x3C0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF14</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF14</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF14</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF14</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF14</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA14</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14IFCR</name>
<displayName>C14IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x3C4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF14</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF14</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF14</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF14</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF14</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14ESR</name>
<displayName>C14ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x3C8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14CR</name>
<displayName>C14CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x3CC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C14TCR</name>
<displayName>C14TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x3D0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14BNDTR</name>
<displayName>C14BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x3D4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14SAR</name>
<displayName>C14SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x3D8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14DAR</name>
<displayName>C14DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x3DC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14BRUR</name>
<displayName>C14BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x3E0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14LAR</name>
<displayName>C14LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x3E4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14TBR</name>
<displayName>C14TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x3E8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14MAR</name>
<displayName>C14MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x3F0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C14MDR</name>
<displayName>C14MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x3F4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15ISR</name>
<displayName>C15ISR</displayName>
<description>MDMA channel x interrupt/status
register</description>
<addressOffset>0x400</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF15</name>
<description>Channel x transfer error interrupt flag
This bit is set by hardware. It is cleared by
software writing 1 to the corresponding bit in the
DMA_IFCRy register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF15</name>
<description>Channel x Channel Transfer Complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register. CTC is set when the
last block was transferred and the channel has been
automatically disabled. CTC is also set when the
channel is suspended, as a result of writing EN bit
to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRTIF15</name>
<description>Channel x block repeat transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BTIF15</name>
<description>Channel x block transfer complete
interrupt flag This bit is set by hardware. It is
cleared by software writing 1 to the corresponding
bit in the DMA_IFCRy register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF15</name>
<description>channel x buffer transfer
complete</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRQA15</name>
<description>channel x request active
flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15IFCR</name>
<displayName>C15IFCR</displayName>
<description>MDMA channel x interrupt flag clear
register</description>
<addressOffset>0x404</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF15</name>
<description>Channel x clear transfer error interrupt
flag Writing a 1 into this bit clears TEIFx in the
MDMA_ISRy register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF15</name>
<description>Clear Channel transfer complete
interrupt flag for channel x Writing a 1 into this
bit clears CTCIFx in the MDMA_ISRy
register</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBRTIF15</name>
<description>Channel x clear block repeat transfer
complete interrupt flag Writing a 1 into this bit
clears BRTIFx in the MDMA_ISRy register</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBTIF15</name>
<description>Channel x Clear block transfer complete
interrupt flag Writing a 1 into this bit clears BTIFx
in the MDMA_ISRy register</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLTCIF15</name>
<description>CLear buffer Transfer Complete Interrupt
Flag for channel x Writing a 1 into this bit clears
TCIFx in the MDMA_ISRy register</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15ESR</name>
<displayName>C15ESR</displayName>
<description>MDMA Channel x error status
register</description>
<addressOffset>0x408</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEA</name>
<description>Transfer Error Address These bits are
set and cleared by HW, in case of an MDMA data
transfer error. It is used in conjunction with TED.
This field indicates the 7 LSBits of the address
which generated a transfer/access error. It may be
used by SW to retrieve the failing address, by adding
this value (truncated to the buffer transfer length
size) to the current SAR/DAR value. Note: The SAR/DAR
current value doesnt reflect this last address due to
the FIFO management system. The SAR/DAR are only
updated at the end of a (buffer) transfer (of TLEN+1
bytes). Note: It is not set in case of a link data
error.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TED</name>
<description>Transfer Error Direction These bit is
set and cleared by HW, in case of an MDMA data
transfer error.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TELD</name>
<description>Transfer Error Link Data These bit is
set by HW, in case of a transfer error while reading
the block link data structure. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEMD</name>
<description>Transfer Error Mask Data These bit is
set by HW, in case of a transfer error while writing
the Mask Data. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASE</name>
<description>Address/Size Error These bit is set by
HW, when the programmed address is not aligned with
the data size. TED will indicate whether the problem
is on the source or destination. It is cleared by
software writing 1 to the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>Block Size Error These bit is set by HW,
when the block size is not an integer multiple of the
data size either for source or destination. TED will
indicate whether the problem is on the source or
destination. It is cleared by software writing 1 to
the CTEIFx bit in the DMA_IFCRy
register.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15CR</name>
<displayName>C15CR</displayName>
<description>This register is used to control the
concerned channel.</description>
<addressOffset>0x40C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTCIE</name>
<description>Channel Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRTIE</name>
<description>Block Repeat transfer interrupt enable
This bit is set and cleared by
software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTIE</name>
<description>Block Transfer interrupt enable This bit
is set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TCIE</name>
<description>buffer Transfer Complete interrupt
enable This bit is set and cleared by
software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PL</name>
<description>Priority level These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEX</name>
<description>byte Endianness exchange</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEX</name>
<description>Half word Endianes
exchange</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WEX</name>
<description>Word Endianness exchange</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWRQ</name>
<description>SW ReQuest Writing a 1 into this bit
sets the CRQAx in MDMA_ISRy register, activating the
request on Channel x Note: Either the whole CxCR
register or the 8-bit/16-bit register @ Address
offset: 0x4E + 0x40 chn may be used for SWRQ
activation. In case of a SW request, acknowledge is
not generated (neither HW signal, nor CxMAR write
access).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>C15TCR</name>
<displayName>C15TCR</displayName>
<description>This register is used to configure the
concerned channel.</description>
<addressOffset>0x410</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SINC</name>
<description>Source increment mode These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0 Note: When source is
AHB (SBUS=1), SINC = 00 is forbidden. In Linked List
Mode, at the end of a block (single or last block in
repeated block transfer mode), this register will be
loaded from memory (from address given by current
LAR[31:0] + 0x00).</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINC</name>
<description>Destination increment mode These bits
are set and cleared by software. These bits are
protected and can be written only if EN is 0 Note:
When destination is AHB (DBUS=1), DINC = 00 is
forbidden.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SSIZE</name>
<description>Source data size These bits are set and
cleared by software. These bits are protected and can
be written only if EN is 0 Note: If a value of 11 is
programmed for the TCM access/AHB port, a transfer
error will occur (TEIF bit set) If SINCOS &amp;lt;
SSIZE and SINC &amp;#8800; 00, the result will be
unpredictable. Note: SSIZE = 11 (double-word) is
forbidden when source is TCM/AHB bus
(SBUS=1).</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Destination data size These bits are set
and cleared by software. These bits are protected and
can be written only if EN is 0. Note: If a value of
11 is programmed for the TCM access/AHB port, a
transfer error will occur (TEIF bit set) If DINCOS
&amp;lt; DSIZE and DINC &amp;#8800; 00, the result
will be unpredictable. Note: DSIZE = 11 (double-word)
is forbidden when destination is TCM/AHB bus
(DBUS=1).</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SINCOS</name>
<description>source increment offset
size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DINCOS</name>
<description>Destination increment
offset</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SBURST</name>
<description>source burst transfer
configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBURST</name>
<description>Destination burst transfer
configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TLEN</name>
<description>buffer transfer lengh</description>
<bitOffset>18</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKE</name>
<description>PacK Enable These bit is set and cleared
by software. If the Source Size is smaller than the
destination, it will be padded according to the PAM
value. If the Source data size is larger than the
destination one, it will be truncated. The alignment
will be done according to the PAM[0] value. This bit
is protected and can be written only if EN is
0</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PAM</name>
<description>Padding/Alignement Mode These bits are
set and cleared by software. Case 1: Source data size
smaller than destination data size - 3 options are
valid. Case 2: Source data size larger than
destination data size. The remainder part is
discarded. When PKE = 1 or DSIZE=SSIZE, these bits
are ignored. These bits are protected and can be
written only if EN is 0</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRGM</name>
<description>Trigger Mode These bits are set and
cleared by software. Note: If TRGM is 11 for the
current block, all the values loaded at the end of
the current block through the linked list mechanism
must keep the same value (TRGM=11) and the same SWRM
value, otherwise the result is undefined. These bits
are protected and can be written only if EN is
0.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SWRM</name>
<description>SW Request Mode This bit is set and
cleared by software. If a HW or SW request is
currently active, the bit change will be delayed
until the current transfer is completed. If the CxMAR
contains a valid address, the CxMDR value will also
be written @ CxMAR address. This bit is protected and
can be written only if EN is 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BWM</name>
<description>Bufferable Write Mode This bit is set
and cleared by software. This bit is protected and
can be written only if EN is 0. Note: All MDMA
destination accesses are non-cacheable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15BNDTR</name>
<displayName>C15BNDTR</displayName>
<description>MDMA Channel x block number of data
register</description>
<addressOffset>0x414</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BNDT</name>
<description>block number of data to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>BRSUM</name>
<description>Block Repeat Source address Update Mode
These bits are protected and can be written only if
EN is 0.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRDUM</name>
<description>Block Repeat Destination address Update
Mode These bits are protected and can be written only
if EN is 0.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRC</name>
<description>Block Repeat Count This field contains
the number of repetitions of the current block (0 to
4095). When the channel is enabled, this register is
read-only, indicating the remaining number of blocks,
excluding the current one. This register decrements
after each complete block transfer. Once the last
block transfer has completed, this register can
either stay at zero or be reloaded automatically from
memory (in Linked List mode - i.e. Link Address
valid). These bits are protected and can be written
only if EN is 0.</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15SAR</name>
<displayName>C15SAR</displayName>
<description>MDMA channel x source address
register</description>
<addressOffset>0x418</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR</name>
<description>source adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15DAR</name>
<displayName>C15DAR</displayName>
<description>MDMA channel x destination address
register</description>
<addressOffset>0x41C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAR</name>
<description>Destination adr base</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15BRUR</name>
<displayName>C15BRUR</displayName>
<description>MDMA channel x Block Repeat address Update
register</description>
<addressOffset>0x420</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUV</name>
<description>source adresse update
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DUV</name>
<description>destination address update</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15LAR</name>
<displayName>C15LAR</displayName>
<description>MDMA channel x Link Address
register</description>
<addressOffset>0x424</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LAR</name>
<description>Link address register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15TBR</name>
<displayName>C15TBR</displayName>
<description>MDMA channel x Trigger and Bus selection
Register</description>
<addressOffset>0x428</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSEL</name>
<description>Trigger selection</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SBUS</name>
<description>Source BUS select This bit is protected
and can be written only if EN is 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBUS</name>
<description>Destination BUS slect This bit is
protected and can be written only if EN is
0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15MAR</name>
<displayName>C15MAR</displayName>
<description>MDMA channel x Mask address
register</description>
<addressOffset>0x430</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAR</name>
<description>Mask address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C15MDR</name>
<displayName>C15MDR</displayName>
<description>MDMA channel x Mask Data
register</description>
<addressOffset>0x434</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MDR</name>
<description>Mask data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MPU</name>
<description>Memory protection unit</description>
<groupName>MPU</groupName>
<baseAddress>0xE000ED90</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x15</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM7</name>
<description>TIM7 global interrupt</description>
<value>55</value>
</interrupt>
<registers>
<register>
<name>MPU_TYPER</name>
<displayName>MPU_TYPER</displayName>
<description>MPU type register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X00000800</resetValue>
<fields>
<field>
<name>SEPARATE</name>
<description>Separate flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DREGION</name>
<description>Number of MPU data regions</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IREGION</name>
<description>Number of MPU instruction
regions</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_CTRL</name>
<displayName>MPU_CTRL</displayName>
<description>MPU control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Enables the MPU</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFNMIENA</name>
<description>Enables the operation of MPU during hard
fault</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIVDEFENA</name>
<description>Enable priviliged software access to
default memory map</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_RNR</name>
<displayName>MPU_RNR</displayName>
<description>MPU region number register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>REGION</name>
<description>MPU region</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_RBAR</name>
<displayName>MPU_RBAR</displayName>
<description>MPU region base address
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>REGION</name>
<description>MPU region field</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VALID</name>
<description>MPU region number valid</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>Region base address field</description>
<bitOffset>5</bitOffset>
<bitWidth>27</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_RASR</name>
<displayName>MPU_RASR</displayName>
<description>MPU region attribute and size
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Region enable bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIZE</name>
<description>Size of the MPU protection
region</description>
<bitOffset>1</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SRD</name>
<description>Subregion disable bits</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>B</name>
<description>memory attribute</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>memory attribute</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S</name>
<description>Shareable memory attribute</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEX</name>
<description>memory attribute</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AP</name>
<description>Access permission</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>XN</name>
<description>Instruction access disable
bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC</name>
<description>Nested Vectored Interrupt
Controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000E100</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x3C5</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM6_DAC</name>
<description>TIM6 global interrupt</description>
<value>54</value>
</interrupt>
<registers>
<register>
<name>ISER0</name>
<displayName>ISER0</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER1</name>
<displayName>ISER1</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER2</name>
<displayName>ISER2</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER0</name>
<displayName>ICER0</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER1</name>
<displayName>ICER1</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER2</name>
<displayName>ICER2</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR0</name>
<displayName>ISPR0</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR1</name>
<displayName>ISPR1</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR2</name>
<displayName>ISPR2</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR0</name>
<displayName>ICPR0</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR1</name>
<displayName>ICPR1</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR2</name>
<displayName>ICPR2</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x188</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR0</name>
<displayName>IABR0</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR1</name>
<displayName>IABR1</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x204</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR2</name>
<displayName>IABR2</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x208</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR0</name>
<displayName>IPR0</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR1</name>
<displayName>IPR1</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x304</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR2</name>
<displayName>IPR2</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x308</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR3</name>
<displayName>IPR3</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x30C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR4</name>
<displayName>IPR4</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x310</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR5</name>
<displayName>IPR5</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x314</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR6</name>
<displayName>IPR6</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x318</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR7</name>
<displayName>IPR7</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x31C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR8</name>
<displayName>IPR8</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x320</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR9</name>
<displayName>IPR9</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x324</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR10</name>
<displayName>IPR10</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x328</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR11</name>
<displayName>IPR11</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x32C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR12</name>
<displayName>IPR12</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x330</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR13</name>
<displayName>IPR13</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x334</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR14</name>
<displayName>IPR14</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x338</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR15</name>
<displayName>IPR15</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x33C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR16</name>
<displayName>IPR16</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x340</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR17</name>
<displayName>IPR17</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x344</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR18</name>
<displayName>IPR18</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x348</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR19</name>
<displayName>IPR19</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x34C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR20</name>
<displayName>IPR20</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x350</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR21</name>
<displayName>IPR21</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x354</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR22</name>
<displayName>IPR22</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x358</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR23</name>
<displayName>IPR23</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x35C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR24</name>
<displayName>IPR24</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x360</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR25</name>
<displayName>IPR25</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x364</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR26</name>
<displayName>IPR26</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x368</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR27</name>
<displayName>IPR27</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x36C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR28</name>
<displayName>IPR28</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x370</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR29</name>
<displayName>IPR29</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x374</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR30</name>
<displayName>IPR30</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x378</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR31</name>
<displayName>IPR31</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x37C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR32</name>
<displayName>IPR32</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x380</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR33</name>
<displayName>IPR33</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x384</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR34</name>
<displayName>IPR34</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x388</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR35</name>
<displayName>IPR35</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x38C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR36</name>
<displayName>IPR36</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x390</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR37</name>
<displayName>IPR37</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x394</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR38</name>
<displayName>IPR38</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x398</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR39</name>
<displayName>IPR39</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x39C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER3</name>
<displayName>ISER3</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x3A0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER4</name>
<displayName>ISER4</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x3A4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER3</name>
<displayName>ICER3</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x3A8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER4</name>
<displayName>ICER4</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x3AC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR3</name>
<displayName>ISPR3</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x3B0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR4</name>
<displayName>ISPR4</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x3B4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR3</name>
<displayName>IABR3</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x3B8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR4</name>
<displayName>IABR4</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x3BC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR40</name>
<displayName>IPR40</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x3C0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC_STIR</name>
<description>Nested vectored interrupt
controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000EF00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>STIR</name>
<displayName>STIR</displayName>
<description>Software trigger interrupt
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTID</name>
<description>Software generated interrupt
ID</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OCTOSPI2</name>
<description>OctoSPI</description>
<groupName>OctoSPI</groupName>
<baseAddress>0x5200A000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>OCTOSPI2</name>
<description>OCTOSPI2 global interrupt</description>
<value>150</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FMODE</name>
<description>Functional mode</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PMM</name>
<description>Polling match mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APMS</name>
<description>Automatic poll mode stop</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOIE</name>
<description>TimeOut interrupt enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMIE</name>
<description>Status match interrupt
enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTIE</name>
<description>FIFO threshold interrupt
enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTHRES</name>
<description>IFO threshold level</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>FSEL</name>
<description>FLASH memory selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DQM</name>
<description>Dual-quad mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCEN</name>
<description>Timeout counter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABORT</name>
<description>Abort request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR1</name>
<displayName>DCR1</displayName>
<description>device configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CKMODE</name>
<description>Mode 0 / mode 3</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRCK</name>
<description>Free running clock</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSHT</name>
<description>Chip-select high time</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEVSIZE</name>
<description>Device size</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>MTYP</name>
<description>Memory type</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR2</name>
<displayName>DCR2</displayName>
<description>device configuration register
2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WRAPSIZE</name>
<description>Wrap size</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR3</name>
<displayName>DCR3</displayName>
<description>device configuration register
3</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAXTRAN</name>
<description>Maximum transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CSBOUND</name>
<description>CS boundary</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR4</name>
<displayName>DCR4</displayName>
<description>DCR4</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REFRESH</name>
<description>Refresh rate</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEF</name>
<description>Clear transfer error flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCF</name>
<description>Clear transfer complete
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSMF</name>
<description>Clear status match flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTOF</name>
<description>Clear timeout flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTF</name>
<description>FIFO threshold flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLEVEL</name>
<description>FIFO level</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FCR</name>
<displayName>FCR</displayName>
<description>flag clear register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEF</name>
<description>Clear transfer error flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCF</name>
<description>Clear transfer complete
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSMF</name>
<description>Clear status match flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTOF</name>
<description>Clear timeout flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DLR</name>
<displayName>DLR</displayName>
<description>data length register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DL</name>
<description>Data length</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AR</name>
<displayName>AR</displayName>
<description>address register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADRESS</name>
<description>Adress</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSMKR</name>
<displayName>PSMKR</displayName>
<description>polling status mask register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASK</name>
<description>Status mask</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSMAR</name>
<displayName>PSMAR</displayName>
<description>polling status match register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MATCH</name>
<description>Match</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>polling interval register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMODE</name>
<description>Instruction mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IDTR</name>
<description>Instruction double transfer
rate</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISIZE</name>
<description>Instruction size</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADMODE</name>
<description>Address mode</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ADDTR</name>
<description>Address double transfer
rate</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSIZE</name>
<description>Address size</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ABMODE</name>
<description>Alternate byte mode</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ABDTR</name>
<description>Alternate bytes double transfer
rate</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABSIZE</name>
<description>Alternate bytes size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMODE</name>
<description>Data mode</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DDTR</name>
<description>Alternate bytes double transfer
rate</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DQSE</name>
<description>DQS enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIOO</name>
<description>Send instruction only once
mode</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<displayName>TCR</displayName>
<description>communication configuration
register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCYC</name>
<description>Number of dummy cycles</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DHQC</name>
<description>Delay hold quarter cycle</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSHIFT</name>
<description>Sample shift</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IR</name>
<displayName>IR</displayName>
<description>timing configuration register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INSTRUCTION</name>
<description>INSTRUCTION</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ABR</name>
<displayName>ABR</displayName>
<description>instruction register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALTERNATE</name>
<description>Alternate bytes</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LPTR</name>
<displayName>LPTR</displayName>
<description>alternate bytes register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMEOUT</name>
<description>Timeout period</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPCCR</name>
<displayName>WPCCR</displayName>
<description>low-power timeout register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMODE</name>
<description>Instruction mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IDTR</name>
<description>Instruction double transfer
rate</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISIZE</name>
<description>Instruction size</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADMODE</name>
<description>Address mode</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ADDTR</name>
<description>Address double transfer
rate</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSIZE</name>
<description>Address size</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ABMODE</name>
<description>Alternate byte mode</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ABDTR</name>
<description>Alternate bytes double transfer
rate</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABSIZE</name>
<description>Alternate bytes size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMODE</name>
<description>Data mode</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DDTR</name>
<description>alternate bytes double transfer
rate</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DQSE</name>
<description>DQS enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPTCR</name>
<displayName>WPTCR</displayName>
<description>wrap timing configuration
register</description>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCYC</name>
<description>Number of dummy cycles</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DHQC</name>
<description>Delay hold quarter cycle</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSHIFT</name>
<description>Sample shift</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPIR</name>
<displayName>WPIR</displayName>
<description>wrap instruction register</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INSTRUCTION</name>
<description>INSTRUCTION</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPABR</name>
<displayName>WPABR</displayName>
<description>wrap alternate bytes register</description>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALTERNATE</name>
<description>Alternate bytes</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WCCR</name>
<displayName>WCCR</displayName>
<description>write communication configuration
register</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMODE</name>
<description>Instruction mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IDTR</name>
<description>Instruction double transfer
rate</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISIZE</name>
<description>Instruction size</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADMODE</name>
<description>Address mode</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ADDTR</name>
<description>Address double transfer
rate</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSIZE</name>
<description>Address size</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ABMODE</name>
<description>Alternate-byte mode</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ABDTR</name>
<description>Alternate bytes double transfer
rate</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABSIZE</name>
<description>Alternate bytes size</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMODE</name>
<description>Data mode</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DDTR</name>
<description>DDTR</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DQSE</name>
<description>DQSE</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WTCR</name>
<displayName>WTCR</displayName>
<description>write timing configuration
register</description>
<addressOffset>0x188</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCYC</name>
<description>DCYC</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>WABR</name>
<displayName>WABR</displayName>
<description>write alternate bytes register</description>
<addressOffset>0x1A0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALTERNATE</name>
<description>Alternate bytes</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HLCR</name>
<displayName>HLCR</displayName>
<description>HyperBusTM latency configuration
register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LM</name>
<description>Latency mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WZL</name>
<description>Write zero latency</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TACC</name>
<description>Access time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TRWR</name>
<description>Read write recovery time</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PIR</name>
<displayName>PIR</displayName>
<description>OCTOSPI polling interval
register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTERVAL</name>
<description>Polling interval</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>WIR</name>
<displayName>WIR</displayName>
<description>instruction register</description>
<addressOffset>0x190</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INSTRUCTION</name>
<description>INSTRUCTION</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="OCTOSPI2">
<name>OCTOSPI1_CONTROL_REGISTER</name>
<baseAddress>0x52005000</baseAddress>
</peripheral>
<peripheral>
<name>OPAMP</name>
<description>Operational amplifiers</description>
<groupName>OPAMP</groupName>
<baseAddress>0x40009000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>OPAMP1_CSR</name>
<displayName>OPAMP1_CSR</displayName>
<description>OPAMP1 control/status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPAEN</name>
<description>Operational amplifier
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_VP</name>
<description>Force internal reference on VP (reserved
for test</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VP_SEL</name>
<description>Operational amplifier PGA
mode</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>VM_SEL</name>
<description>Inverting input selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OPAHSM</name>
<description>Operational amplifier high-speed
mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALON</name>
<description>Calibration mode enabled</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALSEL</name>
<description>Calibration selection</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PGA_GAIN</name>
<description>allows to switch from AOP offset trimmed
values to AOP offset</description>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USERTRIM</name>
<description>User trimming enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSTREF</name>
<description>OPAMP calibration reference voltage
output control (reserved for test)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALOUT</name>
<description>Operational amplifier calibration
output</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP1_OTR</name>
<displayName>OPAMP1_OTR</displayName>
<description>OPAMP1 offset trimming register in normal
mode</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRIMOFFSETN</name>
<description>Trim for NMOS differential
pairs</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMOFFSETP</name>
<description>Trim for PMOS differential
pairs</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP1_HSOTR</name>
<displayName>OPAMP1_HSOTR</displayName>
<description>OPAMP1 offset trimming register in low-power
mode</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRIMLPOFFSETN</name>
<description>Trim for NMOS differential
pairs</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMLPOFFSETP</name>
<description>Trim for PMOS differential
pairs</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP2_CSR</name>
<displayName>OPAMP2_CSR</displayName>
<description>OPAMP2 control/status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPAEN</name>
<description>Operational amplifier
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_VP</name>
<description>Force internal reference on VP (reserved
for test)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VM_SEL</name>
<description>Inverting input selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OPAHSM</name>
<description>Operational amplifier high-speed
mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALON</name>
<description>Calibration mode enabled</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALSEL</name>
<description>Calibration selection</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PGA_GAIN</name>
<description>Operational amplifier Programmable
amplifier gain value</description>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USERTRIM</name>
<description>User trimming enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSTREF</name>
<description>OPAMP calibration reference voltage
output control (reserved for test)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALOUT</name>
<description>Operational amplifier calibration
output</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP2_OTR</name>
<displayName>OPAMP2_OTR</displayName>
<description>OPAMP2 offset trimming register in normal
mode</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRIMOFFSETN</name>
<description>Trim for NMOS differential
pairs</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMOFFSETP</name>
<description>Trim for PMOS differential
pairs</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPAMP2_HSOTR</name>
<displayName>OPAMP2_HSOTR</displayName>
<description>OPAMP2 offset trimming register in low-power
mode</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRIMLPOFFSETN</name>
<description>Trim for NMOS differential
pairs</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRIMLPOFFSETP</name>
<description>Trim for PMOS differential
pairs</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG1_HS_DEVICE</name>
<description>USB 1 on the go high speed</description>
<groupName>USB_OTG_HS</groupName>
<baseAddress>0x40040800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>OTG_HS_DCFG</name>
<displayName>OTG_HS_DCFG</displayName>
<description>OTG_HS device configuration
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02200000</resetValue>
<fields>
<field>
<name>DSPD</name>
<description>Device speed</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NZLSOHSK</name>
<description>Nonzero-length status OUT
handshake</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>4</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PFIVL</name>
<description>Periodic (micro)frame
interval</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PERSCHIVL</name>
<description>Periodic scheduling
interval</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DCTL</name>
<displayName>OTG_HS_DCTL</displayName>
<description>OTG_HS device control register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>RWUSIG</name>
<description>Remote wakeup signaling</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SDIS</name>
<description>Soft disconnect</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GINSTS</name>
<description>Global IN NAK status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>GONSTS</name>
<description>Global OUT NAK status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TCTL</name>
<description>Test control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SGINAK</name>
<description>Set global IN NAK</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CGINAK</name>
<description>Clear global IN NAK</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SGONAK</name>
<description>Set global OUT NAK</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CGONAK</name>
<description>Clear global OUT NAK</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>POPRGDNE</name>
<description>Power-on programming done</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DSTS</name>
<displayName>OTG_HS_DSTS</displayName>
<description>OTG_HS device status register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>SUSPSTS</name>
<description>Suspend status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENUMSPD</name>
<description>Enumerated speed</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EERR</name>
<description>Erratic error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FNSOF</name>
<description>Frame number of the received
SOF</description>
<bitOffset>8</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPMSK</name>
<displayName>OTG_HS_DIEPMSK</displayName>
<description>OTG_HS device IN endpoint common interrupt
mask register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDM</name>
<description>Endpoint disabled interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOM</name>
<description>Timeout condition mask (nonisochronous
endpoints)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITTXFEMSK</name>
<description>IN token received when TxFIFO empty
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNMM</name>
<description>IN token received with EP mismatch
mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNEM</name>
<description>IN endpoint NAK effective
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFURM</name>
<description>FIFO underrun mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIM</name>
<description>BNA interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPMSK</name>
<displayName>OTG_HS_DOEPMSK</displayName>
<description>OTG_HS device OUT endpoint common interrupt
mask register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDM</name>
<description>Endpoint disabled interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUPM</name>
<description>SETUP phase done mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDM</name>
<description>OUT token received when endpoint
disabled mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets received
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPEM</name>
<description>OUT packet error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOIM</name>
<description>BNA interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DAINT</name>
<displayName>OTG_HS_DAINT</displayName>
<description>OTG_HS device all endpoints interrupt
register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>IEPINT</name>
<description>IN endpoint interrupt bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoint interrupt
bits</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DAINTMSK</name>
<displayName>OTG_HS_DAINTMSK</displayName>
<description>OTG_HS all endpoints interrupt mask
register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>IEPM</name>
<description>IN EP interrupt mask bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>OEPM</name>
<description>OUT EP interrupt mask bits</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DVBUSDIS</name>
<displayName>OTG_HS_DVBUSDIS</displayName>
<description>OTG_HS device VBUS discharge time
register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x000017D7</resetValue>
<fields>
<field>
<name>VBUSDT</name>
<description>Device VBUS discharge time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DVBUSPULSE</name>
<displayName>OTG_HS_DVBUSPULSE</displayName>
<description>OTG_HS device VBUS pulsing time
register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x000005B8</resetValue>
<fields>
<field>
<name>DVBUSP</name>
<description>Device VBUS pulsing time</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTHRCTL</name>
<displayName>OTG_HS_DTHRCTL</displayName>
<description>OTG_HS Device threshold control
register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>NONISOTHREN</name>
<description>Nonisochronous IN endpoints threshold
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISOTHREN</name>
<description>ISO IN endpoint threshold
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXTHRLEN</name>
<description>Transmit threshold length</description>
<bitOffset>2</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RXTHREN</name>
<description>Receive threshold enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXTHRLEN</name>
<description>Receive threshold length</description>
<bitOffset>17</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>ARPEN</name>
<description>Arbiter parking enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPEMPMSK</name>
<displayName>OTG_HS_DIEPEMPMSK</displayName>
<description>OTG_HS device IN endpoint FIFO empty
interrupt mask register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTXFEM</name>
<description>IN EP Tx FIFO empty interrupt mask
bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DEACHINT</name>
<displayName>OTG_HS_DEACHINT</displayName>
<description>OTG_HS device each endpoint interrupt
register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>IEP1INT</name>
<description>IN endpoint 1interrupt bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OEP1INT</name>
<description>OUT endpoint 1 interrupt
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DEACHINTMSK</name>
<displayName>OTG_HS_DEACHINTMSK</displayName>
<description>OTG_HS device each endpoint interrupt
register mask</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>IEP1INTM</name>
<description>IN Endpoint 1 interrupt mask
bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OEP1INTM</name>
<description>OUT Endpoint 1 interrupt mask
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPCTL0</name>
<displayName>OTG_HS_DIEPCTL0</displayName>
<description>OTG device endpoint-0 control
register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPCTL1</name>
<displayName>OTG_HS_DIEPCTL1</displayName>
<description>OTG device endpoint-1 control
register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPCTL2</name>
<displayName>OTG_HS_DIEPCTL2</displayName>
<description>OTG device endpoint-2 control
register</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPCTL3</name>
<displayName>OTG_HS_DIEPCTL3</displayName>
<description>OTG device endpoint-3 control
register</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPCTL4</name>
<displayName>OTG_HS_DIEPCTL4</displayName>
<description>OTG device endpoint-4 control
register</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPCTL5</name>
<displayName>OTG_HS_DIEPCTL5</displayName>
<description>OTG device endpoint-5 control
register</description>
<addressOffset>0x1A0</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPCTL6</name>
<displayName>OTG_HS_DIEPCTL6</displayName>
<description>OTG device endpoint-6 control
register</description>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPCTL7</name>
<displayName>OTG_HS_DIEPCTL7</displayName>
<description>OTG device endpoint-7 control
register</description>
<addressOffset>0x1E0</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPINT0</name>
<displayName>OTG_HS_DIEPINT0</displayName>
<description>OTG device endpoint-0 interrupt
register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPINT1</name>
<displayName>OTG_HS_DIEPINT1</displayName>
<description>OTG device endpoint-1 interrupt
register</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPINT2</name>
<displayName>OTG_HS_DIEPINT2</displayName>
<description>OTG device endpoint-2 interrupt
register</description>
<addressOffset>0x148</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPINT3</name>
<displayName>OTG_HS_DIEPINT3</displayName>
<description>OTG device endpoint-3 interrupt
register</description>
<addressOffset>0x168</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPINT4</name>
<displayName>OTG_HS_DIEPINT4</displayName>
<description>OTG device endpoint-4 interrupt
register</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPINT5</name>
<displayName>OTG_HS_DIEPINT5</displayName>
<description>OTG device endpoint-5 interrupt
register</description>
<addressOffset>0x1A8</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPINT6</name>
<displayName>OTG_HS_DIEPINT6</displayName>
<description>OTG device endpoint-6 interrupt
register</description>
<addressOffset>0x1C8</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPINT7</name>
<displayName>OTG_HS_DIEPINT7</displayName>
<description>OTG device endpoint-7 interrupt
register</description>
<addressOffset>0x1E8</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTSIZ0</name>
<displayName>OTG_HS_DIEPTSIZ0</displayName>
<description>OTG_HS device IN endpoint 0 transfer size
register</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPDMA1</name>
<displayName>OTG_HS_DIEPDMA1</displayName>
<description>OTG_HS device endpoint-1 DMA address
register</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPDMA2</name>
<displayName>OTG_HS_DIEPDMA2</displayName>
<description>OTG_HS device endpoint-2 DMA address
register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPDMA3</name>
<displayName>OTG_HS_DIEPDMA3</displayName>
<description>OTG_HS device endpoint-3 DMA address
register</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPDMA4</name>
<displayName>OTG_HS_DIEPDMA4</displayName>
<description>OTG_HS device endpoint-4 DMA address
register</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPDMA5</name>
<displayName>OTG_HS_DIEPDMA5</displayName>
<description>OTG_HS device endpoint-5 DMA address
register</description>
<addressOffset>0x194</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTXFSTS0</name>
<displayName>OTG_HS_DTXFSTS0</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTXFSTS1</name>
<displayName>OTG_HS_DTXFSTS1</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTXFSTS2</name>
<displayName>OTG_HS_DTXFSTS2</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x158</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTXFSTS3</name>
<displayName>OTG_HS_DTXFSTS3</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x178</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTXFSTS4</name>
<displayName>OTG_HS_DTXFSTS4</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x198</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTXFSTS5</name>
<displayName>OTG_HS_DTXFSTS5</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x1B8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTSIZ1</name>
<displayName>OTG_HS_DIEPTSIZ1</displayName>
<description>OTG_HS device endpoint transfer size
register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTSIZ2</name>
<displayName>OTG_HS_DIEPTSIZ2</displayName>
<description>OTG_HS device endpoint transfer size
register</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTSIZ3</name>
<displayName>OTG_HS_DIEPTSIZ3</displayName>
<description>OTG_HS device endpoint transfer size
register</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTSIZ4</name>
<displayName>OTG_HS_DIEPTSIZ4</displayName>
<description>OTG_HS device endpoint transfer size
register</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTSIZ5</name>
<displayName>OTG_HS_DIEPTSIZ5</displayName>
<description>OTG_HS device endpoint transfer size
register</description>
<addressOffset>0x1B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPCTL0</name>
<displayName>OTG_HS_DOEPCTL0</displayName>
<description>OTG_HS device control OUT endpoint 0 control
register</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<resetValue>0x00008000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPCTL1</name>
<displayName>OTG_HS_DOEPCTL1</displayName>
<description>OTG device endpoint-1 control
register</description>
<addressOffset>0x320</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even odd frame/Endpoint data
PID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID/Set even
frame</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPCTL2</name>
<displayName>OTG_HS_DOEPCTL2</displayName>
<description>OTG device endpoint-2 control
register</description>
<addressOffset>0x340</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even odd frame/Endpoint data
PID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID/Set even
frame</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPCTL3</name>
<displayName>OTG_HS_DOEPCTL3</displayName>
<description>OTG device endpoint-3 control
register</description>
<addressOffset>0x360</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even odd frame/Endpoint data
PID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID/Set even
frame</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPINT0</name>
<displayName>OTG_HS_DOEPINT0</displayName>
<description>OTG_HS device endpoint-0 interrupt
register</description>
<addressOffset>0x308</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPINT1</name>
<displayName>OTG_HS_DOEPINT1</displayName>
<description>OTG_HS device endpoint-1 interrupt
register</description>
<addressOffset>0x328</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPINT2</name>
<displayName>OTG_HS_DOEPINT2</displayName>
<description>OTG_HS device endpoint-2 interrupt
register</description>
<addressOffset>0x348</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPINT3</name>
<displayName>OTG_HS_DOEPINT3</displayName>
<description>OTG_HS device endpoint-3 interrupt
register</description>
<addressOffset>0x368</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPINT4</name>
<displayName>OTG_HS_DOEPINT4</displayName>
<description>OTG_HS device endpoint-4 interrupt
register</description>
<addressOffset>0x388</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPINT5</name>
<displayName>OTG_HS_DOEPINT5</displayName>
<description>OTG_HS device endpoint-5 interrupt
register</description>
<addressOffset>0x3A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPINT6</name>
<displayName>OTG_HS_DOEPINT6</displayName>
<description>OTG_HS device endpoint-6 interrupt
register</description>
<addressOffset>0x3C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPINT7</name>
<displayName>OTG_HS_DOEPINT7</displayName>
<description>OTG_HS device endpoint-7 interrupt
register</description>
<addressOffset>0x3E8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPTSIZ0</name>
<displayName>OTG_HS_DOEPTSIZ0</displayName>
<description>OTG_HS device endpoint-0 transfer size
register</description>
<addressOffset>0x310</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUPCNT</name>
<description>SETUP packet count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPTSIZ1</name>
<displayName>OTG_HS_DOEPTSIZ1</displayName>
<description>OTG_HS device endpoint-1 transfer size
register</description>
<addressOffset>0x330</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPTSIZ2</name>
<displayName>OTG_HS_DOEPTSIZ2</displayName>
<description>OTG_HS device endpoint-2 transfer size
register</description>
<addressOffset>0x350</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPTSIZ3</name>
<displayName>OTG_HS_DOEPTSIZ3</displayName>
<description>OTG_HS device endpoint-3 transfer size
register</description>
<addressOffset>0x370</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPTSIZ4</name>
<displayName>OTG_HS_DOEPTSIZ4</displayName>
<description>OTG_HS device endpoint-4 transfer size
register</description>
<addressOffset>0x390</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTSIZ6</name>
<displayName>OTG_HS_DIEPTSIZ6</displayName>
<description>OTG_HS device endpoint transfer size
register</description>
<alternateRegister>OTG_HS_DIEPCTL5</alternateRegister>
<addressOffset>0x1A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTXFSTS6</name>
<displayName>OTG_HS_DTXFSTS6</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x1A4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTSIZ7</name>
<displayName>OTG_HS_DIEPTSIZ7</displayName>
<description>OTG_HS device endpoint transfer size
register</description>
<alternateRegister>OTG_HS_DIEPINT5</alternateRegister>
<addressOffset>0x1A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DTXFSTS7</name>
<displayName>OTG_HS_DTXFSTS7</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x1AC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPCTL4</name>
<displayName>OTG_HS_DOEPCTL4</displayName>
<description>OTG device endpoint-4 control
register</description>
<addressOffset>0x380</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even odd frame/Endpoint data
PID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID/Set even
frame</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPCTL5</name>
<displayName>OTG_HS_DOEPCTL5</displayName>
<description>OTG device endpoint-5 control
register</description>
<addressOffset>0x3A0</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even odd frame/Endpoint data
PID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID/Set even
frame</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPCTL6</name>
<displayName>OTG_HS_DOEPCTL6</displayName>
<description>OTG device endpoint-6 control
register</description>
<addressOffset>0x3C0</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even odd frame/Endpoint data
PID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID/Set even
frame</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPCTL7</name>
<displayName>OTG_HS_DOEPCTL7</displayName>
<description>OTG device endpoint-7 control
register</description>
<addressOffset>0x3E0</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even odd frame/Endpoint data
PID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>Stall</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID/Set even
frame</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPTSIZ5</name>
<displayName>OTG_HS_DOEPTSIZ5</displayName>
<description>OTG_HS device endpoint-5 transfer size
register</description>
<addressOffset>0x3B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPTSIZ6</name>
<displayName>OTG_HS_DOEPTSIZ6</displayName>
<description>OTG_HS device endpoint-6 transfer size
register</description>
<addressOffset>0x3D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DOEPTSIZ7</name>
<displayName>OTG_HS_DOEPTSIZ7</displayName>
<description>OTG_HS device endpoint-7 transfer size
register</description>
<addressOffset>0x3F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG1_HS_GLOBAL</name>
<description>USB 1 on the go high speed</description>
<groupName>USB_OTG_HS</groupName>
<baseAddress>0x40040000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CRYP</name>
<description>CRYP global interrupt</description>
<value>79</value>
</interrupt>
<registers>
<register>
<name>OTG_HS_GOTGCTL</name>
<displayName>OTG_HS_GOTGCTL</displayName>
<description>OTG_HS control and status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000800</resetValue>
<fields>
<field>
<name>SRQSCS</name>
<description>Session request success</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SRQ</name>
<description>Session request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HNGSCS</name>
<description>Host negotiation success</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HNPRQ</name>
<description>HNP request</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSHNPEN</name>
<description>Host set HNP enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DHNPEN</name>
<description>Device HNP enabled</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CIDSTS</name>
<description>Connector ID status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DBCT</name>
<description>Long/short debounce time</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ASVLD</name>
<description>A-session valid</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BSVLD</name>
<description>B-session valid</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EHEN</name>
<description>Embedded host enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GOTGINT</name>
<displayName>OTG_HS_GOTGINT</displayName>
<description>OTG_HS interrupt register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>SEDET</name>
<description>Session end detected</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRSSCHG</name>
<description>Session request success status
change</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HNSSCHG</name>
<description>Host negotiation success status
change</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HNGDET</name>
<description>Host negotiation detected</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADTOCHG</name>
<description>A-device timeout change</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBCDNE</name>
<description>Debounce done</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDCHNG</name>
<description>ID input pin changed</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GAHBCFG</name>
<displayName>OTG_HS_GAHBCFG</displayName>
<description>OTG_HS AHB configuration
register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>GINT</name>
<description>Global interrupt mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBSTLEN</name>
<description>Burst length/type</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFELVL</name>
<description>TxFIFO empty level</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTXFELVL</name>
<description>Periodic TxFIFO empty
level</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GUSBCFG</name>
<displayName>OTG_HS_GUSBCFG</displayName>
<description>OTG_HS USB configuration
register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<resetValue>0x00000A00</resetValue>
<fields>
<field>
<name>TOCAL</name>
<description>FS timeout calibration</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PHYSEL</name>
<description>USB 2.0 high-speed ULPI PHY or USB 1.1
full-speed serial transceiver select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SRPCAP</name>
<description>SRP-capable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HNPCAP</name>
<description>HNP-capable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRDT</name>
<description>USB turnaround time</description>
<bitOffset>10</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PHYLPCS</name>
<description>PHY Low-power clock select</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIFSLS</name>
<description>ULPI FS/LS select</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIAR</name>
<description>ULPI Auto-resume</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPICSM</name>
<description>ULPI Clock SuspendM</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIEVBUSD</name>
<description>ULPI External VBUS Drive</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIEVBUSI</name>
<description>ULPI external VBUS
indicator</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSDPS</name>
<description>TermSel DLine pulsing
selection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PCCI</name>
<description>Indicator complement</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTCI</name>
<description>Indicator pass through</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIIPD</name>
<description>ULPI interface protect
disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FHMOD</name>
<description>Forced host mode</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FDMOD</name>
<description>Forced peripheral mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GRSTCTL</name>
<displayName>OTG_HS_GRSTCTL</displayName>
<description>OTG_HS reset register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>CSRST</name>
<description>Core soft reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSRST</name>
<description>HCLK soft reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FCRST</name>
<description>Host frame counter reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFFLSH</name>
<description>RxFIFO flush</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFFLSH</name>
<description>TxFIFO flush</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AHBIDL</name>
<description>AHB master idle</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMAREQ</name>
<description>DMA request signal enabled for USB OTG
HS</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GINTSTS</name>
<displayName>OTG_HS_GINTSTS</displayName>
<description>OTG_HS core interrupt register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x04000020</resetValue>
<fields>
<field>
<name>CMOD</name>
<description>Current mode of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MMIS</name>
<description>Mode mismatch interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OTGINT</name>
<description>OTG interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SOF</name>
<description>Start of frame</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFLVL</name>
<description>RxFIFO nonempty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NPTXFE</name>
<description>Nonperiodic TxFIFO empty</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>GINAKEFF</name>
<description>Global IN nonperiodic NAK
effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BOUTNAKEFF</name>
<description>Global OUT NAK effective</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ESUSP</name>
<description>Early suspend</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBSUSP</name>
<description>USB suspend</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBRST</name>
<description>USB reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ENUMDNE</name>
<description>Enumeration done</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ISOODRP</name>
<description>Isochronous OUT packet dropped
interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOPF</name>
<description>End of periodic frame
interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEPINT</name>
<description>IN endpoint interrupt</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoint interrupt</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IISOIXFR</name>
<description>Incomplete isochronous IN
transfer</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PXFR_INCOMPISOOUT</name>
<description>Incomplete periodic
transfer</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATAFSUSP</name>
<description>Data fetch suspended</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HPRTINT</name>
<description>Host port interrupt</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HCINT</name>
<description>Host channels interrupt</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PTXFE</name>
<description>Periodic TxFIFO empty</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CIDSCHG</name>
<description>Connector ID status change</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DISCINT</name>
<description>Disconnect detected
interrupt</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SRQINT</name>
<description>Session request/new session detected
interrupt</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WKUINT</name>
<description>Resume/remote wakeup detected
interrupt</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GINTMSK</name>
<displayName>OTG_HS_GINTMSK</displayName>
<description>OTG_HS interrupt mask register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MMISM</name>
<description>Mode mismatch interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OTGINT</name>
<description>OTG interrupt mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOFM</name>
<description>Start of frame mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFLVLM</name>
<description>Receive FIFO nonempty mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NPTXFEM</name>
<description>Nonperiodic TxFIFO empty
mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GINAKEFFM</name>
<description>Global nonperiodic IN NAK effective
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GONAKEFFM</name>
<description>Global OUT NAK effective
mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ESUSPM</name>
<description>Early suspend mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBSUSPM</name>
<description>USB suspend mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBRST</name>
<description>USB reset mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ENUMDNEM</name>
<description>Enumeration done mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ISOODRPM</name>
<description>Isochronous OUT packet dropped interrupt
mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOPFM</name>
<description>End of periodic frame interrupt
mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEPINT</name>
<description>IN endpoints interrupt
mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoints interrupt
mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IISOIXFRM</name>
<description>Incomplete isochronous IN transfer
mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PXFRM_IISOOXFRM</name>
<description>Incomplete periodic transfer
mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSUSPM</name>
<description>Data fetch suspended mask</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRTIM</name>
<description>Host port interrupt mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HCIM</name>
<description>Host channels interrupt
mask</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTXFEM</name>
<description>Periodic TxFIFO empty mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CIDSCHGM</name>
<description>Connector ID status change
mask</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DISCINT</name>
<description>Disconnect detected interrupt
mask</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SRQIM</name>
<description>Session request/new session detected
interrupt mask</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WUIM</name>
<description>Resume/remote wakeup detected interrupt
mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RSTDE</name>
<description>Reset detected interrupt
mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPMINTM</name>
<description>LPM interrupt mask</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GRXSTSR_Host</name>
<displayName>OTG_HS_GRXSTSR_Host</displayName>
<description>OTG_HS Receive status debug read register
(host mode)</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>CHNUM</name>
<description>Channel number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GRXSTSP_Host</name>
<displayName>OTG_HS_GRXSTSP_Host</displayName>
<description>OTG_HS status read and pop register (host
mode)</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>CHNUM</name>
<description>Channel number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GRXFSIZ</name>
<displayName>OTG_HS_GRXFSIZ</displayName>
<description>OTG_HS Receive FIFO size
register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>RXFD</name>
<description>RxFIFO depth</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HNPTXFSIZ_Host</name>
<displayName>OTG_HS_HNPTXFSIZ_Host</displayName>
<description>OTG_HS nonperiodic transmit FIFO size
register (host mode)</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>NPTXFSA</name>
<description>Nonperiodic transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NPTXFD</name>
<description>Nonperiodic TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTXF0_Device</name>
<displayName>OTG_HS_DIEPTXF0_Device</displayName>
<description>Endpoint 0 transmit FIFO size (peripheral
mode)</description>
<alternateRegister>OTG_HS_HNPTXFSIZ_Host</alternateRegister>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>TX0FSA</name>
<description>Endpoint 0 transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TX0FD</name>
<description>Endpoint 0 TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GNPTXSTS</name>
<displayName>OTG_HS_GNPTXSTS</displayName>
<description>OTG_HS nonperiodic transmit FIFO/queue
status register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00080200</resetValue>
<fields>
<field>
<name>NPTXFSAV</name>
<description>Nonperiodic TxFIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NPTQXSAV</name>
<description>Nonperiodic transmit request queue space
available</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NPTXQTOP</name>
<description>Top of the nonperiodic transmit request
queue</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GCCFG</name>
<displayName>OTG_HS_GCCFG</displayName>
<description>OTG_HS general core configuration
register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PWRDWN</name>
<description>Power down</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BCDEN</name>
<description>Battery charging detector (BCD)
enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCDEN</name>
<description>Data contact detection (DCD) mode
enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDEN</name>
<description>Primary detection (PD) mode
enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDEN</name>
<description>Secondary detection (SD) mode
enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBDEN</name>
<description>USB VBUS detection enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCDET</name>
<description>Data contact detection (DCD)
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDET</name>
<description>Primary detection (PD)
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDET</name>
<description>Secondary detection (SD)
status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS2DET</name>
<description>DM pull-up detection
status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_CID</name>
<displayName>OTG_HS_CID</displayName>
<description>OTG_HS core ID register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00001200</resetValue>
<fields>
<field>
<name>PRODUCT_ID</name>
<description>Product ID field</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HPTXFSIZ</name>
<displayName>OTG_HS_HPTXFSIZ</displayName>
<description>OTG_HS Host periodic transmit FIFO size
register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000600</resetValue>
<fields>
<field>
<name>PTXSA</name>
<description>Host periodic TxFIFO start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PTXFD</name>
<description>Host periodic TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTXF1</name>
<displayName>OTG_HS_DIEPTXF1</displayName>
<description>OTG_HS device IN endpoint transmit FIFO size
register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFOx transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTXF2</name>
<displayName>OTG_HS_DIEPTXF2</displayName>
<description>OTG_HS device IN endpoint transmit FIFO size
register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFOx transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTXF3</name>
<displayName>OTG_HS_DIEPTXF3</displayName>
<description>OTG_HS device IN endpoint transmit FIFO size
register</description>
<addressOffset>0x11C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFOx transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTXF4</name>
<displayName>OTG_HS_DIEPTXF4</displayName>
<description>OTG_HS device IN endpoint transmit FIFO size
register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFOx transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTXF5</name>
<displayName>OTG_HS_DIEPTXF5</displayName>
<description>OTG_HS device IN endpoint transmit FIFO size
register</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFOx transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTXF6</name>
<displayName>OTG_HS_DIEPTXF6</displayName>
<description>OTG_HS device IN endpoint transmit FIFO size
register</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFOx transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_DIEPTXF7</name>
<displayName>OTG_HS_DIEPTXF7</displayName>
<description>OTG_HS device IN endpoint transmit FIFO size
register</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFOx transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GRXSTSR_Device</name>
<displayName>OTG_HS_GRXSTSR_Device</displayName>
<description>OTG_HS Receive status debug read register
(peripheral mode mode)</description>
<alternateRegister>OTG_HS_GRXSTSR_Host</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FRMNUM</name>
<description>Frame number</description>
<bitOffset>21</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GRXSTSP_Device</name>
<displayName>OTG_HS_GRXSTSP_Device</displayName>
<description>OTG_HS status read and pop register
(peripheral mode)</description>
<alternateRegister>OTG_HS_GRXSTSP_Host</alternateRegister>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FRMNUM</name>
<description>Frame number</description>
<bitOffset>21</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_GLPMCFG</name>
<displayName>OTG_HS_GLPMCFG</displayName>
<description>OTG core LPM configuration
register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>LPMEN</name>
<description>LPM support enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPMACK</name>
<description>LPM token acknowledge
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BESL</name>
<description>Best effort service
latency</description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>REMWAKE</name>
<description>bRemoteWake value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>L1SSEN</name>
<description>L1 Shallow Sleep enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BESLTHRS</name>
<description>BESL threshold</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>L1DSEN</name>
<description>L1 deep sleep enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPMRST</name>
<description>LPM response</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SLPSTS</name>
<description>Port sleep status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>L1RSMOK</name>
<description>Sleep State Resume OK</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LPMCHIDX</name>
<description>LPM Channel Index</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPMRCNT</name>
<description>LPM retry count</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNDLPM</name>
<description>Send LPM transaction</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPMRCNTSTS</name>
<description>LPM retry count status</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ENBESL</name>
<description>Enable best effort service
latency</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG1_HS_HOST</name>
<description>USB 1 on the go high speed</description>
<groupName>USB_OTG_HS</groupName>
<baseAddress>0x40040400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>OTG_HS_EP1_OUT</name>
<description>OTG_HS out global interrupt</description>
<value>74</value>
</interrupt>
<interrupt>
<name>OTG_HS_EP1_IN</name>
<description>OTG_HS in global interrupt</description>
<value>75</value>
</interrupt>
<interrupt>
<name>OTG_HS_WKUP</name>
<description>OTG_HS wakeup interrupt</description>
<value>76</value>
</interrupt>
<interrupt>
<name>OTG_HS</name>
<description>OTG_HS global interrupt</description>
<value>77</value>
</interrupt>
<registers>
<register>
<name>OTG_HS_HCFG</name>
<displayName>OTG_HS_HCFG</displayName>
<description>OTG_HS host configuration
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>FSLSPCS</name>
<description>FS/LS PHY clock select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSLSS</name>
<description>FS- and LS-only support</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HFIR</name>
<displayName>OTG_HS_HFIR</displayName>
<description>OTG_HS Host frame interval
register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0000EA60</resetValue>
<fields>
<field>
<name>FRIVL</name>
<description>Frame interval</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HFNUM</name>
<displayName>OTG_HS_HFNUM</displayName>
<description>OTG_HS host frame number/frame time
remaining register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00003FFF</resetValue>
<fields>
<field>
<name>FRNUM</name>
<description>Frame number</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FTREM</name>
<description>Frame time remaining</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HPTXSTS</name>
<displayName>OTG_HS_HPTXSTS</displayName>
<description>OTG_HS_Host periodic transmit FIFO/queue
status register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00080100</resetValue>
<fields>
<field>
<name>PTXFSAVL</name>
<description>Periodic transmit data FIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTXQSAV</name>
<description>Periodic transmit request queue space
available</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PTXQTOP</name>
<description>Top of the periodic transmit request
queue</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HAINT</name>
<displayName>OTG_HS_HAINT</displayName>
<description>OTG_HS Host all channels interrupt
register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>HAINT</name>
<description>Channel interrupts</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HAINTMSK</name>
<displayName>OTG_HS_HAINTMSK</displayName>
<description>OTG_HS host all channels interrupt mask
register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>HAINTM</name>
<description>Channel interrupt mask</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HPRT</name>
<displayName>OTG_HS_HPRT</displayName>
<description>OTG_HS host port control and status
register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PCSTS</name>
<description>Port connect status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PCDET</name>
<description>Port connect detected</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PENA</name>
<description>Port enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PENCHNG</name>
<description>Port enable/disable change</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POCA</name>
<description>Port overcurrent active</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>POCCHNG</name>
<description>Port overcurrent change</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRES</name>
<description>Port resume</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PSUSP</name>
<description>Port suspend</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRST</name>
<description>Port reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLSTS</name>
<description>Port line status</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PPWR</name>
<description>Port power</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTCTL</name>
<description>Port test control</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PSPD</name>
<description>Port speed</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR0</name>
<displayName>OTG_HS_HCCHAR0</displayName>
<description>OTG_HS host channel-0 characteristics
register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR1</name>
<displayName>OTG_HS_HCCHAR1</displayName>
<description>OTG_HS host channel-1 characteristics
register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR2</name>
<displayName>OTG_HS_HCCHAR2</displayName>
<description>OTG_HS host channel-2 characteristics
register</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR3</name>
<displayName>OTG_HS_HCCHAR3</displayName>
<description>OTG_HS host channel-3 characteristics
register</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR4</name>
<displayName>OTG_HS_HCCHAR4</displayName>
<description>OTG_HS host channel-4 characteristics
register</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR5</name>
<displayName>OTG_HS_HCCHAR5</displayName>
<description>OTG_HS host channel-5 characteristics
register</description>
<addressOffset>0x1A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR6</name>
<displayName>OTG_HS_HCCHAR6</displayName>
<description>OTG_HS host channel-6 characteristics
register</description>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR7</name>
<displayName>OTG_HS_HCCHAR7</displayName>
<description>OTG_HS host channel-7 characteristics
register</description>
<addressOffset>0x1E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR8</name>
<displayName>OTG_HS_HCCHAR8</displayName>
<description>OTG_HS host channel-8 characteristics
register</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR9</name>
<displayName>OTG_HS_HCCHAR9</displayName>
<description>OTG_HS host channel-9 characteristics
register</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR10</name>
<displayName>OTG_HS_HCCHAR10</displayName>
<description>OTG_HS host channel-10 characteristics
register</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR11</name>
<displayName>OTG_HS_HCCHAR11</displayName>
<description>OTG_HS host channel-11 characteristics
register</description>
<addressOffset>0x260</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT0</name>
<displayName>OTG_HS_HCSPLT0</displayName>
<description>OTG_HS host channel-0 split control
register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT1</name>
<displayName>OTG_HS_HCSPLT1</displayName>
<description>OTG_HS host channel-1 split control
register</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT2</name>
<displayName>OTG_HS_HCSPLT2</displayName>
<description>OTG_HS host channel-2 split control
register</description>
<addressOffset>0x144</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT3</name>
<displayName>OTG_HS_HCSPLT3</displayName>
<description>OTG_HS host channel-3 split control
register</description>
<addressOffset>0x164</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT4</name>
<displayName>OTG_HS_HCSPLT4</displayName>
<description>OTG_HS host channel-4 split control
register</description>
<addressOffset>0x184</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT5</name>
<displayName>OTG_HS_HCSPLT5</displayName>
<description>OTG_HS host channel-5 split control
register</description>
<addressOffset>0x1A4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT6</name>
<displayName>OTG_HS_HCSPLT6</displayName>
<description>OTG_HS host channel-6 split control
register</description>
<addressOffset>0x1C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT7</name>
<displayName>OTG_HS_HCSPLT7</displayName>
<description>OTG_HS host channel-7 split control
register</description>
<addressOffset>0x1E4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT8</name>
<displayName>OTG_HS_HCSPLT8</displayName>
<description>OTG_HS host channel-8 split control
register</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT9</name>
<displayName>OTG_HS_HCSPLT9</displayName>
<description>OTG_HS host channel-9 split control
register</description>
<addressOffset>0x224</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT10</name>
<displayName>OTG_HS_HCSPLT10</displayName>
<description>OTG_HS host channel-10 split control
register</description>
<addressOffset>0x244</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT11</name>
<displayName>OTG_HS_HCSPLT11</displayName>
<description>OTG_HS host channel-11 split control
register</description>
<addressOffset>0x264</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT0</name>
<displayName>OTG_HS_HCINT0</displayName>
<description>OTG_HS host channel-11 interrupt
register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT1</name>
<displayName>OTG_HS_HCINT1</displayName>
<description>OTG_HS host channel-1 interrupt
register</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT2</name>
<displayName>OTG_HS_HCINT2</displayName>
<description>OTG_HS host channel-2 interrupt
register</description>
<addressOffset>0x148</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT3</name>
<displayName>OTG_HS_HCINT3</displayName>
<description>OTG_HS host channel-3 interrupt
register</description>
<addressOffset>0x168</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT4</name>
<displayName>OTG_HS_HCINT4</displayName>
<description>OTG_HS host channel-4 interrupt
register</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT5</name>
<displayName>OTG_HS_HCINT5</displayName>
<description>OTG_HS host channel-5 interrupt
register</description>
<addressOffset>0x1A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT6</name>
<displayName>OTG_HS_HCINT6</displayName>
<description>OTG_HS host channel-6 interrupt
register</description>
<addressOffset>0x1C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT7</name>
<displayName>OTG_HS_HCINT7</displayName>
<description>OTG_HS host channel-7 interrupt
register</description>
<addressOffset>0x1E8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT8</name>
<displayName>OTG_HS_HCINT8</displayName>
<description>OTG_HS host channel-8 interrupt
register</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT9</name>
<displayName>OTG_HS_HCINT9</displayName>
<description>OTG_HS host channel-9 interrupt
register</description>
<addressOffset>0x228</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT10</name>
<displayName>OTG_HS_HCINT10</displayName>
<description>OTG_HS host channel-10 interrupt
register</description>
<addressOffset>0x248</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT11</name>
<displayName>OTG_HS_HCINT11</displayName>
<description>OTG_HS host channel-11 interrupt
register</description>
<addressOffset>0x268</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK0</name>
<displayName>OTG_HS_HCINTMSK0</displayName>
<description>OTG_HS host channel-11 interrupt mask
register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK1</name>
<displayName>OTG_HS_HCINTMSK1</displayName>
<description>OTG_HS host channel-1 interrupt mask
register</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK2</name>
<displayName>OTG_HS_HCINTMSK2</displayName>
<description>OTG_HS host channel-2 interrupt mask
register</description>
<addressOffset>0x14C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK3</name>
<displayName>OTG_HS_HCINTMSK3</displayName>
<description>OTG_HS host channel-3 interrupt mask
register</description>
<addressOffset>0x16C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK4</name>
<displayName>OTG_HS_HCINTMSK4</displayName>
<description>OTG_HS host channel-4 interrupt mask
register</description>
<addressOffset>0x18C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK5</name>
<displayName>OTG_HS_HCINTMSK5</displayName>
<description>OTG_HS host channel-5 interrupt mask
register</description>
<addressOffset>0x1AC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK6</name>
<displayName>OTG_HS_HCINTMSK6</displayName>
<description>OTG_HS host channel-6 interrupt mask
register</description>
<addressOffset>0x1CC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK7</name>
<displayName>OTG_HS_HCINTMSK7</displayName>
<description>OTG_HS host channel-7 interrupt mask
register</description>
<addressOffset>0x1EC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK8</name>
<displayName>OTG_HS_HCINTMSK8</displayName>
<description>OTG_HS host channel-8 interrupt mask
register</description>
<addressOffset>0x20C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK9</name>
<displayName>OTG_HS_HCINTMSK9</displayName>
<description>OTG_HS host channel-9 interrupt mask
register</description>
<addressOffset>0x22C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK10</name>
<displayName>OTG_HS_HCINTMSK10</displayName>
<description>OTG_HS host channel-10 interrupt mask
register</description>
<addressOffset>0x24C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK11</name>
<displayName>OTG_HS_HCINTMSK11</displayName>
<description>OTG_HS host channel-11 interrupt mask
register</description>
<addressOffset>0x26C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ0</name>
<displayName>OTG_HS_HCTSIZ0</displayName>
<description>OTG_HS host channel-11 transfer size
register</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ1</name>
<displayName>OTG_HS_HCTSIZ1</displayName>
<description>OTG_HS host channel-1 transfer size
register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ2</name>
<displayName>OTG_HS_HCTSIZ2</displayName>
<description>OTG_HS host channel-2 transfer size
register</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ3</name>
<displayName>OTG_HS_HCTSIZ3</displayName>
<description>OTG_HS host channel-3 transfer size
register</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ4</name>
<displayName>OTG_HS_HCTSIZ4</displayName>
<description>OTG_HS host channel-4 transfer size
register</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ5</name>
<displayName>OTG_HS_HCTSIZ5</displayName>
<description>OTG_HS host channel-5 transfer size
register</description>
<addressOffset>0x1B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ6</name>
<displayName>OTG_HS_HCTSIZ6</displayName>
<description>OTG_HS host channel-6 transfer size
register</description>
<addressOffset>0x1D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ7</name>
<displayName>OTG_HS_HCTSIZ7</displayName>
<description>OTG_HS host channel-7 transfer size
register</description>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ8</name>
<displayName>OTG_HS_HCTSIZ8</displayName>
<description>OTG_HS host channel-8 transfer size
register</description>
<addressOffset>0x210</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ9</name>
<displayName>OTG_HS_HCTSIZ9</displayName>
<description>OTG_HS host channel-9 transfer size
register</description>
<addressOffset>0x230</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ10</name>
<displayName>OTG_HS_HCTSIZ10</displayName>
<description>OTG_HS host channel-10 transfer size
register</description>
<addressOffset>0x250</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ11</name>
<displayName>OTG_HS_HCTSIZ11</displayName>
<description>OTG_HS host channel-11 transfer size
register</description>
<addressOffset>0x270</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA0</name>
<displayName>OTG_HS_HCDMA0</displayName>
<description>OTG_HS host channel-0 DMA address
register</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA1</name>
<displayName>OTG_HS_HCDMA1</displayName>
<description>OTG_HS host channel-1 DMA address
register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA2</name>
<displayName>OTG_HS_HCDMA2</displayName>
<description>OTG_HS host channel-2 DMA address
register</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA3</name>
<displayName>OTG_HS_HCDMA3</displayName>
<description>OTG_HS host channel-3 DMA address
register</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA4</name>
<displayName>OTG_HS_HCDMA4</displayName>
<description>OTG_HS host channel-4 DMA address
register</description>
<addressOffset>0x194</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA5</name>
<displayName>OTG_HS_HCDMA5</displayName>
<description>OTG_HS host channel-5 DMA address
register</description>
<addressOffset>0x1B4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA6</name>
<displayName>OTG_HS_HCDMA6</displayName>
<description>OTG_HS host channel-6 DMA address
register</description>
<addressOffset>0x1D4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA7</name>
<displayName>OTG_HS_HCDMA7</displayName>
<description>OTG_HS host channel-7 DMA address
register</description>
<addressOffset>0x1F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA8</name>
<displayName>OTG_HS_HCDMA8</displayName>
<description>OTG_HS host channel-8 DMA address
register</description>
<addressOffset>0x214</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA9</name>
<displayName>OTG_HS_HCDMA9</displayName>
<description>OTG_HS host channel-9 DMA address
register</description>
<addressOffset>0x234</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA10</name>
<displayName>OTG_HS_HCDMA10</displayName>
<description>OTG_HS host channel-10 DMA address
register</description>
<addressOffset>0x254</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA11</name>
<displayName>OTG_HS_HCDMA11</displayName>
<description>OTG_HS host channel-11 DMA address
register</description>
<addressOffset>0x274</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR12</name>
<displayName>OTG_HS_HCCHAR12</displayName>
<description>OTG_HS host channel-12 characteristics
register</description>
<addressOffset>0x278</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT12</name>
<displayName>OTG_HS_HCSPLT12</displayName>
<description>OTG_HS host channel-12 split control
register</description>
<addressOffset>0x27C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT12</name>
<displayName>OTG_HS_HCINT12</displayName>
<description>OTG_HS host channel-12 interrupt
register</description>
<addressOffset>0x280</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK12</name>
<displayName>OTG_HS_HCINTMSK12</displayName>
<description>OTG_HS host channel-12 interrupt mask
register</description>
<addressOffset>0x284</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ12</name>
<displayName>OTG_HS_HCTSIZ12</displayName>
<description>OTG_HS host channel-12 transfer size
register</description>
<addressOffset>0x288</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA12</name>
<displayName>OTG_HS_HCDMA12</displayName>
<description>OTG_HS host channel-12 DMA address
register</description>
<addressOffset>0x28C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR13</name>
<displayName>OTG_HS_HCCHAR13</displayName>
<description>OTG_HS host channel-13 characteristics
register</description>
<addressOffset>0x290</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT13</name>
<displayName>OTG_HS_HCSPLT13</displayName>
<description>OTG_HS host channel-13 split control
register</description>
<addressOffset>0x294</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT13</name>
<displayName>OTG_HS_HCINT13</displayName>
<description>OTG_HS host channel-13 interrupt
register</description>
<addressOffset>0x298</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK13</name>
<displayName>OTG_HS_HCINTMSK13</displayName>
<description>OTG_HS host channel-13 interrupt mask
register</description>
<addressOffset>0x29C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALLM response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ13</name>
<displayName>OTG_HS_HCTSIZ13</displayName>
<description>OTG_HS host channel-13 transfer size
register</description>
<addressOffset>0x2A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA13</name>
<displayName>OTG_HS_HCDMA13</displayName>
<description>OTG_HS host channel-13 DMA address
register</description>
<addressOffset>0x2A4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR14</name>
<displayName>OTG_HS_HCCHAR14</displayName>
<description>OTG_HS host channel-14 characteristics
register</description>
<addressOffset>0x2A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT14</name>
<displayName>OTG_HS_HCSPLT14</displayName>
<description>OTG_HS host channel-14 split control
register</description>
<addressOffset>0x2AC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT14</name>
<displayName>OTG_HS_HCINT14</displayName>
<description>OTG_HS host channel-14 interrupt
register</description>
<addressOffset>0x2B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK14</name>
<displayName>OTG_HS_HCINTMSK14</displayName>
<description>OTG_HS host channel-14 interrupt mask
register</description>
<addressOffset>0x2B4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAKM response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACKM response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ14</name>
<displayName>OTG_HS_HCTSIZ14</displayName>
<description>OTG_HS host channel-14 transfer size
register</description>
<addressOffset>0x2B8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA14</name>
<displayName>OTG_HS_HCDMA14</displayName>
<description>OTG_HS host channel-14 DMA address
register</description>
<addressOffset>0x2BC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCCHAR15</name>
<displayName>OTG_HS_HCCHAR15</displayName>
<description>OTG_HS host channel-15 characteristics
register</description>
<addressOffset>0x2C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCSPLT15</name>
<displayName>OTG_HS_HCSPLT15</displayName>
<description>OTG_HS host channel-15 split control
register</description>
<addressOffset>0x2C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINT15</name>
<displayName>OTG_HS_HCINT15</displayName>
<description>OTG_HS host channel-15 interrupt
register</description>
<addressOffset>0x2C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCINTMSK15</name>
<displayName>OTG_HS_HCINTMSK15</displayName>
<description>OTG_HS host channel-15 interrupt mask
register</description>
<addressOffset>0x2CC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCTSIZ15</name>
<displayName>OTG_HS_HCTSIZ15</displayName>
<description>OTG_HS host channel-15 transfer size
register</description>
<addressOffset>0x2D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTG_HS_HCDMA15</name>
<displayName>OTG_HS_HCDMA15</displayName>
<description>OTG_HS host channel-15 DMA address
register</description>
<addressOffset>0x2D4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG1_HS_PWRCLK</name>
<description>USB 1 on the go high speed</description>
<groupName>USB_OTG_HS</groupName>
<baseAddress>0x40040E00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x3F200</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>OTG_HS_PCGCR</name>
<displayName>OTG_HS_PCGCR</displayName>
<description>Power and clock gating control
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>STPPCLK</name>
<description>Stop PHY clock</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GATEHCLK</name>
<description>Gate HCLK</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PHYSUSP</name>
<description>PHY suspended</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OctoSPII_O_Manager</name>
<description>OctoSPI IO Manager</description>
<groupName>OctoSPII_O_Manager</groupName>
<baseAddress>0x5200B400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>OctoSPI IO Manager Control
Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MUXEN</name>
<description>Multiplexed mode Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REQ2ACK_TIME</name>
<description>REQ to ACK Time</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>P1CR</name>
<displayName>P1CR</displayName>
<description>OctoSPI IO Manager Port 1 configuration
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x03010111</resetValue>
<fields>
<field>
<name>CLKEN</name>
<description>CLK/CLKn Enable for Port n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSRC</name>
<description>CLK/CLKn Source for Port n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DQSEN</name>
<description>DQSEN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DQSSRC</name>
<description>DQSSRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCSEN</name>
<description>NCSEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCSSRC</name>
<description>NCSSRC</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOLEN</name>
<description>IOLEN</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOLSRC</name>
<description>IOLSRC</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOHEN</name>
<description>IOHEN</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOHSRC</name>
<description>IOHSRC</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>P2CR</name>
<displayName>P2CR</displayName>
<description>OctoSPI IO Manager Port 2 configuration
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x07050333</resetValue>
<fields>
<field>
<name>CLKEN</name>
<description>CLKEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSRC</name>
<description>CLKSRC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DQSEN</name>
<description>DQSEN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DQSSRC</name>
<description>DQSSRC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCSEN</name>
<description>NCSEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCSSRC</name>
<description>NCSSRC</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOLEN</name>
<description>IOLEN</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOLSRC</name>
<description>IOLSRC</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOHEN</name>
<description>IOHEN</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOHSRC</name>
<description>IOHSRC</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PF</name>
<description>Processor features</description>
<groupName>PF</groupName>
<baseAddress>0xE000ED78</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FPU</name>
<description>Floating point unit interrupt</description>
<value>81</value>
</interrupt>
<registers>
<register>
<name>CLIDR</name>
<displayName>CLIDR</displayName>
<description>Cache Level ID register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x09000003</resetValue>
<fields>
<field>
<name>CL1</name>
<description>CL1</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CL2</name>
<description>CL2</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CL3</name>
<description>CL3</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CL4</name>
<description>CL4</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CL5</name>
<description>CL5</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CL6</name>
<description>CL6</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CL7</name>
<description>CL7</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LoUIS</name>
<description>LoUIS</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LoC</name>
<description>LoC</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LoU</name>
<description>LoU</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTR</name>
<displayName>CTR</displayName>
<description>Cache Type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X8303C003</resetValue>
<fields>
<field>
<name>_IminLine</name>
<description>IminLine</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMinLine</name>
<description>DMinLine</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ERG</name>
<description>ERG</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CWG</name>
<description>CWG</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Format</name>
<description>Format</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCSIDR</name>
<displayName>CCSIDR</displayName>
<description>Cache Size ID register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>LineSize</name>
<description>LineSize</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>Associativity</name>
<description>Associativity</description>
<bitOffset>3</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>NumSets</name>
<description>NumSets</description>
<bitOffset>13</bitOffset>
<bitWidth>15</bitWidth>
</field>
<field>
<name>WA</name>
<description>WA</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RA</name>
<description>RA</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WB</name>
<description>WB</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WT</name>
<description>WT</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWR</name>
<description>PWR</description>
<groupName>PWR</groupName>
<baseAddress>0x58024800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WWDG1_RST</name>
<description>Window Watchdog interrupt</description>
<value>143</value>
</interrupt>
<registers>
<register>
<name>PWR_CR1</name>
<displayName>PWR_CR1</displayName>
<description>PWR control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xF000C000</resetValue>
<fields>
<field>
<name>LPDS</name>
<description>Low-power Deepsleep with SVOS3 (SVOS4
and SVOS5 always use low-power, regardless of the
setting of this bit)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVDE</name>
<description>Programmable voltage detector
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLS</name>
<description>Programmable voltage detector level
selection These bits select the voltage threshold
detected by the PVD. Note: Refer to Section
Electrical characteristics of the product datasheet
for more details.</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBP</name>
<description>Disable backup domain write protection
In reset state, the RCC_BDCR register, the RTC
registers (including the backup registers), BREN and
MOEN bits in PWR_CR2 register, are protected against
parasitic write access. This bit must be set to
enable write access to these registers.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLPS</name>
<description>Flash low-power mode in DStop mode This
bit allows to obtain the best trade-off between
low-power consumption and restart time when exiting
from DStop mode. When it is set, the Flash memory
enters low-power mode when D1 domain is in DStop
mode.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOOSTE</name>
<description>BOOSTE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AVD_READY</name>
<description>AVD_READY</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVOS</name>
<description>System Stop mode voltage scaling
selection These bits control the VCORE voltage level
in system Stop mode, to obtain the best trade-off
between power consumption and
performance.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AVDEN</name>
<description>Peripheral voltage monitor on VDDA
enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALS</name>
<description>Analog voltage detector level selection
These bits select the voltage threshold detected by
the AVD.</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AXIRAM1SO</name>
<description>AXIRAM1SO</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AXIRAM2SO</name>
<description>AXIRAM2SO</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AXIRAM3SO</name>
<description>AXIRAM3SO</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBRAM1SO</name>
<description>AHBRAM1SO</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBRAM2SO</name>
<description>AHBRAM2SO</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITCMSO</name>
<description>ITCMSO</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GFXSO</name>
<description>GFXSO</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSITFSO</name>
<description>HSITFSO</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRDRAMSO</name>
<description>SRDRAMSO</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_CSR1</name>
<displayName>PWR_CSR1</displayName>
<description>PWR control status register 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00004000</resetValue>
<fields>
<field>
<name>PVDO</name>
<description>Programmable voltage detect output This
bit is set and cleared by hardware. It is valid only
if the PVD has been enabled by the PVDE bit. Note:
since the PVD is disabled in Standby mode, this bit
is equal to 0 after Standby or reset until the PVDE
bit is set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACTVOSRDY</name>
<description>Voltage levels ready bit for currently
used VOS and SDLEVEL This bit is set to 1 by hardware
when the voltage regulator and the SD converter are
both disabled and Bypass mode is selected in PWR
control register 3 (PWR_CR3).</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACTVOS</name>
<description>VOS currently applied for VCORE voltage
scaling selection. These bits reflect the last VOS
value applied to the PMU.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AVDO</name>
<description>Analog voltage detector output on VDDA
This bit is set and cleared by hardware. It is valid
only if AVD on VDDA is enabled by the AVDEN bit.
Note: Since the AVD is disabled in Standby mode, this
bit is equal to 0 after Standby or reset until the
AVDEN bit is set.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMCVDO</name>
<description>MMCVDO</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_CR2</name>
<displayName>PWR_CR2</displayName>
<description>This register is not reset by wakeup from
Standby mode, RESET signal and VDD POR. It is only reset
by VSW POR and VSWRST reset. This register shall not be
accessed when VSWRST bit in RCC_BDCR register resets the
VSW domain.After reset, PWR_CR2 register is
write-protected. Prior to modifying its content, the DBP
bit in PWR_CR1 register must be set to disable the write
protection.</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BREN</name>
<description>Backup regulator enable When set, the
Backup regulator (used to maintain the backup RAM
content in Standby and VBAT modes) is enabled. If
BREN is reset, the backup regulator is switched off.
The backup RAM can still be used in Run and Stop
modes. However, its content will be lost in Standby
and VBAT modes. If BREN is set, the application must
wait till the Backup Regulator Ready flag (BRRDY) is
set to indicate that the data written into the SRAM
will be maintained in Standby and VBAT
modes.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MONEN</name>
<description>VBAT and temperature monitoring enable
When set, the VBAT supply and temperature monitoring
is enabled.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRRDY</name>
<description>Backup regulator ready This bit is set
by hardware to indicate that the Backup regulator is
ready.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TEMPL</name>
<description>Temperature level monitoring versus low
threshold</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TEMPH</name>
<description>Temperature level monitoring versus high
threshold</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PWR_CR3</name>
<displayName>PWR_CR3</displayName>
<description>Reset only by POR only, not reset by wakeup
from Standby mode and RESET pad. The lower byte of this
register is written once after POR and shall be written
before changing VOS level or ck_sys clock frequency. No
limitation applies to the upper bytes.Programming data
corresponding to an invalid combination of SDLEVEL,
SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be
ignored: data will not be written, the written-once
mechanism will lock the register and any further write
access will be ignored. The default supply configuration
will be kept and the ACTVOSRDY bit in PWR control status
register 1 (PWR_CSR1) will go on indicating invalid
voltage levels. The system shall be power cycled before
writing a new value.</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000006</resetValue>
<fields>
<field>
<name>BYPASS</name>
<description>Power management unit
bypass</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LDOEN</name>
<description>Low drop-out regulator
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SMPSEN</name>
<description>SMPSEN</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SMPSEXTHP</name>
<description>SMPSEXTHP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SMPSLEVEL</name>
<description>SMPSLEVEL</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VBE</name>
<description>VBAT charging enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VBRS</name>
<description>VBAT charging resistor
selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SMPSEXTRDY</name>
<description>SMPSEXTRDY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>USB33DEN</name>
<description>VDD33USB voltage level detector
enable.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBREGEN</name>
<description>USB regulator enable.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USB33RDY</name>
<description>USB supply ready.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PWR_CPUCR</name>
<displayName>PWR_CPUCR</displayName>
<description>This register allows controlling CPU1
power.</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RETDS_CD</name>
<description>RETDS_CD</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PDDS_SRD</name>
<description>PDDS_SRD</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STOPF</name>
<description>STOP flag This bit is set by hardware
and cleared only by any reset or by setting the CPU1
CSSF bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SBF</name>
<description>System Standby flag This bit is set by
hardware and cleared only by a POR (Power-on Reset)
or by setting the CPU1 CSSF bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CSSF</name>
<description>Clear D1 domain CPU1 Standby, Stop and
HOLD flags (always read as 0) This bit is cleared to
0 by hardware.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RUN_SRD</name>
<description>RUN_SRD</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_SRDCR</name>
<displayName>PWR_SRDCR</displayName>
<description>This register allows controlling D3 domain
power.Following reset VOSRDY will be read 1 by
software</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00004000</resetValue>
<fields>
<field>
<name>VOSRDY</name>
<description>VOS Ready bit for VCORE voltage scaling
output selection. This bit is set to 1 by hardware
when Bypass mode is selected in PWR control register
3 (PWR_CR3).</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>VOS</name>
<description>Voltage scaling selection according to
performance These bits control the VCORE voltage
level and allow to obtains the best trade-off between
power consumption and performance: When increasing
the performance, the voltage scaling shall be changed
before increasing the system frequency. When
decreasing performance, the system frequency shall
first be decreased before changing the voltage
scaling.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_WKUPCR</name>
<displayName>PWR_WKUPCR</displayName>
<description>reset only by system reset, not reset by
wakeup from Standby mode5 wait states are required when
writing this register (when clearing a WKUPF bit in
PWR_WKUPFR, the AHB write access will complete after the
WKUPF has been cleared).</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WKUPC1</name>
<description>Clear Wakeup pin flag for WKUP. These
bits are always read as 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPC2</name>
<description>Clear Wakeup pin flag for WKUP. These
bits are always read as 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPC3</name>
<description>Clear Wakeup pin flag for WKUP. These
bits are always read as 0.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPC4</name>
<description>Clear Wakeup pin flag for WKUP. These
bits are always read as 0.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPC5</name>
<description>Clear Wakeup pin flag for WKUP. These
bits are always read as 0.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPC6</name>
<description>Clear Wakeup pin flag for WKUP. These
bits are always read as 0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WKUPFR</name>
<displayName>PWR_WKUPFR</displayName>
<description>reset only by system reset, not reset by
wakeup from Standby mode</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WKUPF1</name>
<description>Wakeup pin WKUPF flag. This bit is set
by hardware and cleared only by a Reset pin or by
setting the WKUPCn+1 bit in the PWR wakeup clear
register (PWR_WKUPCR).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPF2</name>
<description>Wakeup pin WKUPF flag. This bit is set
by hardware and cleared only by a Reset pin or by
setting the WKUPCn+1 bit in the PWR wakeup clear
register (PWR_WKUPCR).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPF3</name>
<description>Wakeup pin WKUPF flag. This bit is set
by hardware and cleared only by a Reset pin or by
setting the WKUPCn+1 bit in the PWR wakeup clear
register (PWR_WKUPCR).</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPF4</name>
<description>Wakeup pin WKUPF flag. This bit is set
by hardware and cleared only by a Reset pin or by
setting the WKUPCn+1 bit in the PWR wakeup clear
register (PWR_WKUPCR).</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPF5</name>
<description>Wakeup pin WKUPF flag. This bit is set
by hardware and cleared only by a Reset pin or by
setting the WKUPCn+1 bit in the PWR wakeup clear
register (PWR_WKUPCR).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPF6</name>
<description>Wakeup pin WKUPF flag. This bit is set
by hardware and cleared only by a Reset pin or by
setting the WKUPCn+1 bit in the PWR wakeup clear
register (PWR_WKUPCR).</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWR_WKUPEPR</name>
<displayName>PWR_WKUPEPR</displayName>
<description>Reset only by system reset, not reset by
wakeup from Standby mode</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WKUPEN1</name>
<description>Enable Wakeup Pin WKUPn+1 Each bit is
set and cleared by software. Note: An additional
wakeup event is detected if WKUPn+1 pin is enabled
(by setting the WKUPENn+1 bit) when WKUPn+1 pin level
is already high when WKUPPn+1 selects rising edge, or
low when WKUPPn+1 selects falling edge.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPEN2</name>
<description>Enable Wakeup Pin WKUPn+1 Each bit is
set and cleared by software. Note: An additional
wakeup event is detected if WKUPn+1 pin is enabled
(by setting the WKUPENn+1 bit) when WKUPn+1 pin level
is already high when WKUPPn+1 selects rising edge, or
low when WKUPPn+1 selects falling edge.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPEN3</name>
<description>Enable Wakeup Pin WKUPn+1 Each bit is
set and cleared by software. Note: An additional
wakeup event is detected if WKUPn+1 pin is enabled
(by setting the WKUPENn+1 bit) when WKUPn+1 pin level
is already high when WKUPPn+1 selects rising edge, or
low when WKUPPn+1 selects falling edge.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPEN4</name>
<description>Enable Wakeup Pin WKUPn+1 Each bit is
set and cleared by software. Note: An additional
wakeup event is detected if WKUPn+1 pin is enabled
(by setting the WKUPENn+1 bit) when WKUPn+1 pin level
is already high when WKUPPn+1 selects rising edge, or
low when WKUPPn+1 selects falling edge.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPEN5</name>
<description>Enable Wakeup Pin WKUPn+1 Each bit is
set and cleared by software. Note: An additional
wakeup event is detected if WKUPn+1 pin is enabled
(by setting the WKUPENn+1 bit) when WKUPn+1 pin level
is already high when WKUPPn+1 selects rising edge, or
low when WKUPPn+1 selects falling edge.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPEN6</name>
<description>Enable Wakeup Pin WKUPn+1 Each bit is
set and cleared by software. Note: An additional
wakeup event is detected if WKUPn+1 pin is enabled
(by setting the WKUPENn+1 bit) when WKUPn+1 pin level
is already high when WKUPPn+1 selects rising edge, or
low when WKUPPn+1 selects falling edge.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPP1</name>
<description>Wakeup pin polarity bit for WKUPn-7
These bits define the polarity used for event
detection on WKUPn-7 external wakeup
pin.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPP2</name>
<description>Wakeup pin polarity bit for WKUPn-7
These bits define the polarity used for event
detection on WKUPn-7 external wakeup
pin.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPP3</name>
<description>Wakeup pin polarity bit for WKUPn-7
These bits define the polarity used for event
detection on WKUPn-7 external wakeup
pin.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPP4</name>
<description>Wakeup pin polarity bit for WKUPn-7
These bits define the polarity used for event
detection on WKUPn-7 external wakeup
pin.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPP5</name>
<description>Wakeup pin polarity bit for WKUPn-7
These bits define the polarity used for event
detection on WKUPn-7 external wakeup
pin.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPP6</name>
<description>Wakeup pin polarity bit for WKUPn-7
These bits define the polarity used for event
detection on WKUPn-7 external wakeup
pin.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPPUPD1</name>
<description>Wakeup pin pull
configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WKUPPUPD2</name>
<description>Wakeup pin pull
configuration</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WKUPPUPD3</name>
<description>Wakeup pin pull
configuration</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WKUPPUPD4</name>
<description>Wakeup pin pull
configuration</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WKUPPUPD5</name>
<description>Wakeup pin pull
configuration</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WKUPPUPD6</name>
<description>Wakeup pin pull configuration for
WKUP(truncate(n/2)-7) These bits define the I/O pad
pull configuration used when WKUPEN(truncate(n/2)-7)
= 1. The associated GPIO port pull configuration
shall be set to the same value or to 00. The Wakeup
pin pull configuration is kept in Standby
mode.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RAMECC</name>
<description>ECC controller is associated to each RAM
area</description>
<groupName>RAMECC</groupName>
<baseAddress>0x52009000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>RAMECC interrupt enable
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GIE</name>
<description>Global interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GECCSEIE_</name>
<description>Global ECC single error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GECCDEIE</name>
<description>Global ECC double error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GECCDEBWIE</name>
<description>Global ECC double error on byte write
(BW) interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M1CR</name>
<displayName>M1CR</displayName>
<description>RAMECC monitor x configuration
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECCSEIE</name>
<description>ECC single error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEIE</name>
<description>ECC double error interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEBWIE</name>
<description>ECC double error on byte write (BW)
interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCELEN</name>
<description>ECC error latching enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M1SR</name>
<displayName>M1SR</displayName>
<description>RAMECC monitor x status
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECCSEIE</name>
<description>ECC single error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEIE</name>
<description>ECC double error interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEBWIE</name>
<description>ECC double error on byte write (BW)
interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCELEN</name>
<description>ECC error latching enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M1FAR</name>
<displayName>M1FAR</displayName>
<description>RAMECC monitor x failing address
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECCSEIE</name>
<description>ECC single error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEIE</name>
<description>ECC double error interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEBWIE</name>
<description>ECC double error on byte write (BW)
interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCELEN</name>
<description>ECC error latching enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M1FDRL</name>
<displayName>M1FDRL</displayName>
<description>RAMECC monitor x failing data low
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECCSEIE</name>
<description>ECC single error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEIE</name>
<description>ECC double error interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEBWIE</name>
<description>ECC double error on byte write (BW)
interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCELEN</name>
<description>ECC error latching enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M1FDRH</name>
<displayName>M1FDRH</displayName>
<description>RAMECC monitor x failing data high
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECCSEIE</name>
<description>ECC single error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEIE</name>
<description>ECC double error interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCDEBWIE</name>
<description>ECC double error on byte write (BW)
interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECCELEN</name>
<description>ECC error latching enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M1FECR</name>
<displayName>M1FECR</displayName>
<description>RAMECC monitor x failing ECC error code
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEDCF</name>
<description>ECC single error detected and corrected
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDF</name>
<description>ECC double error detected
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBWDF</name>
<description>ECC double error on byte write (BW)
detected flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M2CR</name>
<displayName>M2CR</displayName>
<description>RAMECC monitor x configuration
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEDCF</name>
<description>ECC single error detected and corrected
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDF</name>
<description>ECC double error detected
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBWDF</name>
<description>ECC double error on byte write (BW)
detected flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M2SR</name>
<displayName>M2SR</displayName>
<description>RAMECC monitor x status
register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEDCF</name>
<description>ECC single error detected and corrected
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDF</name>
<description>ECC double error detected
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBWDF</name>
<description>ECC double error on byte write (BW)
detected flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M2FAR</name>
<displayName>M2FAR</displayName>
<description>RAMECC monitor x failing address
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEDCF</name>
<description>ECC single error detected and corrected
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDF</name>
<description>ECC double error detected
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBWDF</name>
<description>ECC double error on byte write (BW)
detected flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M2FDRL</name>
<displayName>M2FDRL</displayName>
<description>RAMECC monitor x failing data low
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEDCF</name>
<description>ECC single error detected and corrected
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDF</name>
<description>ECC double error detected
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBWDF</name>
<description>ECC double error on byte write (BW)
detected flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>M2FDRH</name>
<displayName>M2FDRH</displayName>
<description>RAMECC monitor x failing data high
register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FADD</name>
<description>ECC error failing address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M2FECR</name>
<displayName>M2FECR</displayName>
<description>RAMECC monitor x failing ECC error code
register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FADD</name>
<description>ECC error failing address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M3CR</name>
<displayName>M3CR</displayName>
<description>RAMECC monitor x configuration
register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FADD</name>
<description>ECC error failing address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M3SR</name>
<displayName>M3SR</displayName>
<description>RAMECC monitor x status
register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FADD</name>
<description>ECC error failing address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M3FAR</name>
<displayName>M3FAR</displayName>
<description>RAMECC monitor x failing address
register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FADD</name>
<description>ECC error failing address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M3FDRL</name>
<displayName>M3FDRL</displayName>
<description>RAMECC monitor x failing data low
register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAL</name>
<description>Failing data low</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M3FDRH</name>
<displayName>M3FDRH</displayName>
<description>RAMECC monitor x failing data high
register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAL</name>
<description>Failing data low</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M3FECR</name>
<displayName>M3FECR</displayName>
<description>RAMECC monitor x failing ECC error code
register</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAL</name>
<description>Failing data low</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M4CR</name>
<displayName>M4CR</displayName>
<description>RAMECC monitor x configuration
register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAL</name>
<description>Failing data low</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M4SR</name>
<displayName>M4SR</displayName>
<description>RAMECC monitor x status
register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAL</name>
<description>Failing data low</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M4FAR</name>
<displayName>M4FAR</displayName>
<description>RAMECC monitor x failing address
register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAH</name>
<description>Failing data high (64-bit
memory)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M4FDRL</name>
<displayName>M4FDRL</displayName>
<description>RAMECC monitor x failing data low
register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAH</name>
<description>Failing data high (64-bit
memory)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M4FDRH</name>
<displayName>M4FDRH</displayName>
<description>RAMECC monitor x failing data high
register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAH</name>
<description>Failing data high (64-bit
memory)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M4FECR</name>
<displayName>M4FECR</displayName>
<description>RAMECC monitor x failing ECC error code
register</description>
<alternateRegister>M4FDRH</alternateRegister>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FDATAH</name>
<description>Failing data high (64-bit
memory)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M5CR</name>
<displayName>M5CR</displayName>
<description>RAMECC monitor x configuration
register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FEC</name>
<description>Failing error code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M5SR</name>
<displayName>M5SR</displayName>
<description>RAMECC monitor x status
register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FEC</name>
<description>Failing error code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M5FAR</name>
<displayName>M5FAR</displayName>
<description>RAMECC monitor x failing address
register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FEC</name>
<description>Failing error code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M5FDRL</name>
<displayName>M5FDRL</displayName>
<description>RAMECC monitor x failing data low
register</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FEC</name>
<description>Failing error code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M5FDRH</name>
<displayName>M5FDRH</displayName>
<description>RAMECC monitor x failing data high
register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FEC</name>
<description>Failing error code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M5FECR</name>
<displayName>M5FECR</displayName>
<description>RAMECC monitor x failing ECC error code
register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FEC</name>
<description>Failing error code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RCC</name>
<description>Reset and clock control</description>
<groupName>RCC</groupName>
<baseAddress>0x58024400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x180</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RCC</name>
<description>RCC global interrupt</description>
<value>5</value>
</interrupt>
<registers>
<register>
<name>RCC_CR</name>
<displayName>RCC_CR</displayName>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000025</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HSION</name>
<description>HSI clock enable
Set and cleared by software.
Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0.
Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.
This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI is OFF</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI is ON (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIKERON</name>
<description>HSI clock enable in Stop mode
Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no effect on HSI (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI is forced to ON even in Stop mode</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIRDY</name>
<description>HSI clock ready flag
Set by hardware to indicate that the HSI oscillator is stable.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI clock is not ready (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI clock is ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIDIV</name>
<description>HSI clock divider
Set and reset by software.
These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>division by 1, hsi(_ker)_ck = 64 MHz (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>division by 2, hsi(_ker)_ck = 32 MHz</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>division by 4, hsi(_ker)_ck = 16 MHz</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>division by 8, hsi(_ker)_ck = 8 MHz</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIDIVF</name>
<description>HSI divider flag
Set and reset by hardware.
As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV.
clock setting is completed)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>new division ratio not yet propagated to hsi(_ker)_ck (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>hsi(_ker)_ck clock frequency reflects the new HSIDIV value (default register value when the</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSION</name>
<description>CSI clock enable
Set and reset by software to enable/disable CSI clock for system and/or peripheral.
Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.
This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CSI is OFF (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI is ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSIRDY</name>
<description>CSI clock ready flag
Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request).</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CSI clock is not ready (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI clock is ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSIKERON</name>
<description>CSI clock enable in Stop mode
Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no effect on CSI (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI is forced to ON even in Stop mode</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48ON</name>
<description>HSI48 clock enable
Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI48 is OFF (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI48 is ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48RDY</name>
<description>HSI48 clock ready flag
Set by hardware to indicate that the HSI48 oscillator is stable.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI48 clock is not ready (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI48 clock is ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPUCKRDY</name>
<description>CPU related clocks ready flag
Set by hardware to indicate that the CPU related clocks (CPU, APB3, AXI bus matrix and related memories) are available.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CPU related clocks are not available (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CPU related clocks are available</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CDCKRDY</name>
<description>CPU domain clocks ready flag
Set by hardware to indicate that the following CPU domain clocks are available: APB1, APB2, AHB bus matrix.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CPU domain clocks are not available (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CPU domain clocks are available</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSEON</name>
<description>HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE when entering Stop or Standby mode.
This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1).</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE is OFF (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE is ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSERDY</name>
<description>HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE clock is not ready (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE clock is ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSEBYP</name>
<description>HSE clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE oscillator not bypassed (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE oscillator bypassed with an external clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSECSSON</name>
<description>HSE clock security system enable
Set by software to enable clock security system on HSE.
This bit is “set only” (disabled by a system reset or when the system enters in Standby mode).
When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CSS on HSE OFF (clock detector OFF) (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSS on HSE ON (clock detector ON if the HSE oscillator is stable, OFF if not).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSEEXT</name>
<description>external high speed clock type in Bypass mode
Set and reset by software to select the external clock type (analog or digital).
The external clock must be enabled with the HSEON bit to be used by the device.
The HSEEXT bit can be written only if the HSE oscillator is disabled.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE in analog mode (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE in digital mode</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL1ON</name>
<description>PLL1 enable
Set and cleared by software to enable PLL1.
Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL1 OFF (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL1 ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL1RDY</name>
<description>PLL1 clock ready flag
Set by hardware to indicate that the PLL1 is locked.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL1 unlocked (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL1 locked</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL2ON</name>
<description>PLL2 enable
Set and cleared by software to enable PLL2.
Cleared by hardware when entering Stop or Standby mode.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL2 OFF (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL2 ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL2RDY</name>
<description>PLL2 clock ready flag
Set by hardware to indicate that the PLL2 is locked.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL2 unlocked (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL2 locked</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL3ON</name>
<description>PLL3 enable
Set and cleared by software to enable PLL3.
Cleared by hardware when entering Stop or Standby mode.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL3 OFF (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL3 ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL3RDY</name>
<description>PLL3 clock ready flag
Set by hardware to indicate that the PLL3 is locked.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL3 unlocked (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL3 locked</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_HSICFGR</name>
<displayName>RCC_HSICFGR</displayName>
<description>RCC HSI calibration register </description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x40000000</resetValue>
<resetMask>0xFFFFF000</resetMask>
<fields>
<field>
<name>HSICAL</name>
<description>HSI clock calibration
Set by hardware by option byte loading during system reset nreset.
Adjusted by software through trimming bits HSITRIM.
This field represents the sum of engineering option byte calibration value and HSITRIM bits value.</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSITRIM</name>
<description>HSI clock trimming
Set by software to adjust calibration.
HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt.
Note: The reset value of the field is 0x40.</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCC_CRRCR</name>
<displayName>RCC_CRRCR</displayName>
<description>RCC clock recovery RC register </description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFF000</resetMask>
<fields>
<field>
<name>HSI48CAL</name>
<description>Internal RC 48 MHz clock calibration
Set by hardware by option byte loading during system reset nreset.
Read-only.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RCC_CSICFGR</name>
<displayName>RCC_CSICFGR</displayName>
<description>RCC CSI calibration register </description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<resetValue>0x20000000</resetValue>
<resetMask>0xFFFFF000</resetMask>
<fields>
<field>
<name>CSICAL</name>
<description>CSI clock calibration
Set by hardware by option byte loading during system reset nreset.
Adjusted by software through trimming bits CSITRIM.
This field represents the sum of engineering option byte calibration value and CSITRIM bits value.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CSITRIM</name>
<description>CSI clock trimming
Set by software to adjust calibration.
CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value.
CSICAL = CSITRIM + FLASH_CSI_opt.
Note: The reset value of the field is 0x20.</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCC_CFGR</name>
<displayName>RCC_CFGR</displayName>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SW</name>
<description>system clock and trace clock switch
Set and reset by software to select system clock and trace clock sources (sys_ck and traceclk).
Set by hardware in order to:
force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode
force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock
others: reserved</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI selected as system clock (hsi_ck) (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI selected as system clock (csi_ck)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSE selected as system clock (hse_ck)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL1 selected as system clock (pll1_p_ck for sys_ck, pll1_r_ck for traceclk)</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWS</name>
<description>system clock switch status
Set and reset by hardware to indicate which clock source is used as system clock.
others: reserved</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI used as system clock (hsi_ck) (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI used as system clock (csi_ck)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSE used as system clock (hse_ck)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL1 used as system clock (pll1_p_ck)</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPWUCK</name>
<description>system clock selection after a wake up from system Stop
Set and reset by software to select the system wakeup clock from system Stop.
The selected clock is also used as emergency clock for the clock security system (CSS) on HSE.
See for details.
STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI selected as wake up clock from system Stop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI selected as wake up clock from system Stop </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPKERWUCK</name>
<description>kernel clock selection after a wake up from system Stop
Set and reset by software to select the kernel wakeup clock from system Stop.
See for details.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI selected as wake up clock from system Stop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI selected as wake up clock from system Stop </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCPRE</name>
<description>HSE division factor for RTC clock
Set and cleared by software to divide the HSE to generate a clock for RTC.
Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.
...</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>no clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSE/2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>HSE/3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>HSE/4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3E</name>
<description>HSE/62</description>
<value>0x3E</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3F</name>
<description>HSE/63</description>
<value>0x3F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMPRE</name>
<description>timers clocks prescaler selection
This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains.
Refer to for more details.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The timers kernel clock is equal to rcc_hclk1 if CDPPRE1 or CDPPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if CDPPRE1 or CDPPRE2 corresponds to a division by 1, 2or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCO1PRE</name>
<description>MCO1 prescaler
Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.
...</description>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>prescaler disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>division by 1 (bypass)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>division by 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>division by 3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>division by 4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xF</name>
<description>division by 15</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCO1SEL</name>
<description>Microcontroller clock output 1
Set and cleared by software. Clock source selection may generate glitches on MCO1.
It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.
others: reserved</description>
<bitOffset>22</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI clock selected (hsi_ck) (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE oscillator clock selected (lse_ck)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSE clock selected (hse_ck)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL1 clock selected (pll1_q_ck) </description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>HSI48 clock selected (hsi48_ck)</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCO2PRE</name>
<description>MCO2 prescaler
Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.
...</description>
<bitOffset>25</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>prescaler disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>division by 1 (bypass)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>division by 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>division by 3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>division by 4</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xF</name>
<description>division by 15</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCO2SEL</name>
<description>microcontroller clock output 2
Set and cleared by software. Clock source selection may generate glitches on MCO2.
It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.
others: reserved</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>system clock selected (sys_ck) (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL2 oscillator clock selected (pll2_p_ck) </description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSE clock selected (hse_ck)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL1 clock selected (pll1_p_ck) </description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>CSI clock selected (csi_ck)</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>LSI clock selected (lsi_ck)</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CDCFGR1</name>
<displayName>RCC_CDCFGR1</displayName>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HPRE</name>
<description>CPU domain AHB prescaler
Set and reset by software to control the division factor of rcc_hclk3 and rcc_aclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks.
0xxx: rcc_hclk3 = sys_cdcpre_ck (default after reset)
Note: The clocks are divided by the new prescaler factor from1 to 16 periods of the slowest APB clock among rcc_pclk[4:1] after HPRE update.
Note: Note also that rcc_hclk3 = rcc_aclk.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x8</name>
<description>rcc_hclk3 = sys_cdcpre_ck / 2</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x9</name>
<description>rcc_hclk3 = sys_cdcpre_ck / 4</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xA</name>
<description>rcc_hclk3 = sys_cdcpre_ck / 8</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xB</name>
<description>rcc_hclk3 = sys_cdcpre_ck / 16</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xC</name>
<description>rcc_hclk3 = sys_cdcpre_ck / 64</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xD</name>
<description>rcc_hclk3 = sys_cdcpre_ck / 128</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xE</name>
<description>rcc_hclk3 = sys_cdcpre_ck / 256</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xF</name>
<description>rcc_hclk3 = sys_cdcpre_ck / 512</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CDPPRE</name>
<description>CPU domain APB3 prescaler
Set and reset by software to control the division factor of rcc_pclk3.
The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk3 after CDPPRE write.
0xx: rcc_pclk3 = rcc_hclk3 (default after reset)</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x4</name>
<description>rcc_pclk3 = rcc_hclk3 / 2 </description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>rcc_pclk3 = rcc_hclk3 / 4 </description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>rcc_pclk3 = rcc_hclk3 / 8 </description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>rcc_pclk3 = rcc_hclk3 / 16 </description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CDCPRE</name>
<description>CPU domain core prescaler
Set and reset by software to control the CPU domain CPU clock division factor.
Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks.
After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register.
0xxx: sys_ck not divided (default after reset)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x8</name>
<description>sys_ck divided by 2</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x9</name>
<description>sys_ck divided by 4</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xA</name>
<description>sys_ck divided by 8</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xB</name>
<description>sys_ck divided by 16</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xC</name>
<description>sys_ck divided by 64</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xD</name>
<description>sys_ck divided by 128</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xE</name>
<description>sys_ck divided by 256</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xF</name>
<description>sys_ck divided by 512</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CDCFGR2</name>
<displayName>RCC_CDCFGR2</displayName>
<addressOffset>0x1c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CDPPRE1</name>
<description>CPU domain APB1 prescaler
Set and reset by software to control the CPU domain APB1 clock division factor.
The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after CDPPRE1 write.
0xx: rcc_pclk1 = rcc_hclk1 (default after reset)</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x4</name>
<description>rcc_pclk1 = rcc_hclk1 / 2</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>rcc_pclk1 = rcc_hclk1 / 4</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>rcc_pclk1 = rcc_hclk1 / 8</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>rcc_pclk1 = rcc_hclk1 / 16</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CDPPRE2</name>
<description>CPU domain APB2 prescaler
Set and reset by software to control the CPU domain APB2 clock division factor.
The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after CDPPRE2 write.
0xx: rcc_pclk2 = rcc_hclk1 (default after reset)</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x4</name>
<description>rcc_pclk2 = rcc_hclk1 / 2</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>rcc_pclk2 = rcc_hclk1 / 4</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>rcc_pclk2 = rcc_hclk1 / 8</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>rcc_pclk2 = rcc_hclk1 / 16</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_SRDCFGR</name>
<displayName>RCC_SRDCFGR</displayName>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SRDPPRE</name>
<description>SmartRun domain APB4 prescaler
Set and reset by software to control the SmartRun domain APB4 clock division factor.
The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk4 after SRDPPRE write.
0xx: rcc_pclk4 = rcc_hclk4 (default after reset)</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x4</name>
<description>rcc_pclk4 = rcc_hclk4 / 2</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>rcc_pclk4 = rcc_hclk4 / 4</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>rcc_pclk4 = rcc_hclk4 / 8</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>rcc_pclk4 = rcc_hclk4 / 16</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_PLLCKSELR</name>
<displayName>RCC_PLLCKSELR</displayName>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0x02020200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLLSRC</name>
<description>DIVMx and PLLs clock source selection
Set and reset by software to select the PLL clock source.
These bits can be written only when all PLLs are disabled.
In order to save power, when no PLL is used, the value of PLLSRC must be set to '11’.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI selected as PLL clock (hsi_ck) (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI selected as PLL clock (csi_ck)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>HSE selected as PLL clock (hse_ck)</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>no clock send to DIVMx divider and PLLs </description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVM1</name>
<description>prescaler for PLL1
Set and cleared by software to configure the prescaler of the PLL1.
The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1).
In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.
...
...</description>
<bitOffset>4</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>prescaler disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>division by 1 (bypass)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>division by 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>division by 3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x20</name>
<description>division by 32 (default after reset)</description>
<value>0x20</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3F</name>
<description>division by 63</description>
<value>0x3F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVM2</name>
<description>prescaler for PLL2
Set and cleared by software to configure the prescaler of the PLL2.
The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = 1).
In order to save power when PLL2 is not used, the value of DIVM2 must be set to 0.
...
...</description>
<bitOffset>12</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>prescaler disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>division by 1 (bypass)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>division by 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>division by 3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x20</name>
<description>division by 32 (default after reset)</description>
<value>0x20</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3F</name>
<description>division by 63</description>
<value>0x3F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVM3</name>
<description>prescaler for PLL3
Set and cleared by software to configure the prescaler of the PLL3.
The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON = 1).
In order to save power when PLL3 is not used, the value of DIVM3 must be set to 0.
...
...</description>
<bitOffset>20</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>prescaler disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>division by 1 (bypass)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>division by 2</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>division by 3</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x20</name>
<description>division by 32 (default after reset)</description>
<value>0x20</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3F</name>
<description>division by 63</description>
<value>0x3F</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_PLLCFGR</name>
<displayName>RCC_PLLCFGR</displayName>
<addressOffset>0x2c</addressOffset>
<size>0x20</size>
<resetValue>0x01FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PLL1FRACEN</name>
<description>PLL1 fractional latch enable
Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.
In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator.
Refer to for additional information.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLL1VCOSEL</name>
<description>PLL1 VCO selection
Set and reset by software to select the proper VCO frequency range used for PLL1.
These bits must be written before enabling the PLL1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>wide VCO range from 128 to 560 MHz (default after reset) </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>medium VCO range from 150 to 420 MHz </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL1RGE</name>
<description>PLL1 input frequency range
Set and reset by software to select the proper reference frequency range used for PLL1.
This bit must be written before enabling the PLL1.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL1 input (ref1_ck) clock range frequency between 1 and 2 MHz (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL1 input (ref1_ck) clock range frequency between 2 and 4 MHz</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL2FRACEN</name>
<description>PLL2 fractional latch enable
Set and reset by software to latch the content of FRACN2 into the sigma-delta modulator.
In order to latch the FRACN2 value into the sigma-delta modulator, PLL2FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN2 into the modulator.
Refer to for additional information.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLL2VCOSEL</name>
<description>PLL2 VCO selection
Set and reset by software to select the proper VCO frequency range used for PLL2.
This bit must be written before enabling the PLL2.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>wide VCO range 128 to 560 MHz (default after reset) </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>medium VCO range 150 to 420 MHz </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL2RGE</name>
<description>PLL2 input frequency range
Set and reset by software to select the proper reference frequency range used for PLL2.
These bits must be written before enabling the PLL2.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL2 input (ref2_ck) clock range frequency between 1 and 2 MHz (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL2 input (ref2_ck) clock range frequency between 2 and 4 MHz</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL3FRACEN</name>
<description>PLL3 fractional latch enable
Set and reset by software to latch the content of FRACN3 into the sigma-delta modulator.
In order to latch the FRACN3 value into the sigma-delta modulator, PLL3FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN3 into the modulator.
Refer to for additional information.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLL3VCOSEL</name>
<description>PLL3 VCO selection
Set and reset by software to select the proper VCO frequency range used for PLL3.
This bit must be written before enabling the PLL3.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>wide VCO range 128 to 560 MHz (default after reset) </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>medium VCO range 150 to 420 MHz </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL3RGE</name>
<description>PLL3 input frequency range
Set and reset by software to select the proper reference frequency range used for PLL3.
These bits must be written before enabling the PLL3.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL3 input (ref3_ck) clock range frequency between 1 and 2 MHz (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL3 input (ref3_ck) clock range frequency between 2 and 4 MHz</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVP1EN</name>
<description>PLL1 DIVP divider output enable
Set and reset by software to enable the pll1_p_ck output of the PLL1.
This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_p_ck output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_p_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVQ1EN</name>
<description>PLL1 DIVQ divider output enable
Set and reset by software to enable the pll1_q_ck output of the PLL1.
In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.
This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_q_ck output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_q_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVR1EN</name>
<description>PLL1 DIVR divider output enable
Set and reset by software to enable the pll1_r_ck output of the PLL1.
To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used.
This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_r_ck output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_r_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVP2EN</name>
<description>PLL2 DIVP divider output enable
Set and reset by software to enable the pll2_p_ck output of the PLL2.
This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).
To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll2_p_ck output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVQ2EN</name>
<description>PLL2 DIVQ divider output enable
Set and reset by software to enable the pll2_q_ck output of the PLL2.
To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used.
This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll2_q_ck output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_q_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVR2EN</name>
<description>PLL2 DIVR divider output enable
Set and reset by software to enable the pll2_r_ck output of the PLL2.
To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used.
This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll2_r_ck output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_r_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVP3EN</name>
<description>PLL3 DIVP divider output enable
Set and reset by software to enable the pll3_p_ck output of the PLL3.
This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll3_p_ck output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_p_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVQ3EN</name>
<description>PLL3 DIVQ divider output enable
Set and reset by software to enable the pll3_q_ck output of the PLL3.
To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used.
This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll3_q_ck output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_q_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVR3EN</name>
<description>PLL3 DIVR divider output enable
Set and reset by software to enable the pll3_r_ck output of the PLL3.
To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used.
This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll3_r_ck output disabled </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_r_ck output enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_PLL1DIVR</name>
<displayName>RCC_PLL1DIVR</displayName>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x01010280</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVN1</name>
<description>multiplication factor for PLL1 VCO
Set and reset by software to control the multiplication factor of the VCO.
These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0).
..........: not used
...
...
Others: wrong configurations
The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:
128 to 560 MHz if PLL1VCOSEL = 0
150 to 420 MHz if PLL1VCOSEL = 1
VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN1, with:
DIVN1 between 8 and 420
The input frequency Fref1_ck must be between 1 and 16 MHz.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x6</name>
<description>wrong configuration</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>DIVN1 = 8</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x80</name>
<description>DIVN1 = 129 (default after reset)</description>
<value>0x80</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1A3</name>
<description>DIVN1 = 420</description>
<value>0x1A3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVP1</name>
<description>PLL1 DIVP division factor
Set and reset by software to control the frequency of the pll1_p_ck clock.
These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
Note that odd division factors are not allowed.
...</description>
<bitOffset>9</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>not allowed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_p_ck = vco1_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>not allowed</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll1_p_ck = vco1_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll1_p_ck = vco1_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVQ1</name>
<description>PLL1 DIVQ division factor
Set and reset by software to control the frequency of the pll1_q_ck clock.
These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
...</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_q_ck = vco1_ck </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_q_ck = vco1_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll1_q_ck = vco1_ck / 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll1_q_ck = vco1_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll1_q_ck = vco1_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVR1</name>
<description>PLL1 DIVR division factor
Set and reset by software to control the frequency of the pll1_r_ck clock.
These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
...</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_r_ck = vco1_ck </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_r_ck = vco1_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll1_r_ck = vco1_ck / 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll1_r_ck = vco1_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll1_r_ck = vco1_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_PLL1FRACR</name>
<displayName>RCC_PLL1FRACR</displayName>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FRACN1</name>
<description>fractional part of the multiplication factor for PLL1 VCO
Set and reset by software to control the fractional part of the multiplication factor of the VCO.
These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.
The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:
128 to 560 MHz if PLL1VCOSEL = 0
150 to 420 MHz if PLL1VCOSEL = 1
VCO output frequency = Fref1_ck x (DIVN1 + (FRACN1 / 213)), with
DIVN1 between 8 and 420
FRACN1 can be between 0 and 213- 1
The input frequency Fref1_ck must be between 1 and 16 MHz.
To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:
Set the bit PLL1FRACEN to 0.
Write the new fractional value into FRACN1.
Set the bit PLL1FRACEN to 1.</description>
<bitOffset>3</bitOffset>
<bitWidth>13</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCC_PLL2DIVR</name>
<displayName>RCC_PLL2DIVR</displayName>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<resetValue>0x01010280</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVN2</name>
<description>multiplication factor for PLL2 VCO
Set and reset by software to control the multiplication factor of the VCO.
These bits can be written only when the PLL is disabled (PLL2ON = PLL2RDY = 0).
..........: not used
...
...
Others: wrong configurations
The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:
128 to 560 MHz if PLL2VCOSEL = 0
150 to 420 MHz if PLL2VCOSEL = 1
VCO output frequency = Fref2_ck x DIVN2, when fractional value 0 has been loaded into FRACN2, with
DIVN2 between 8 and 420
The input frequency Fref2_ck must be between 1 and 16MHz.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x6</name>
<description>wrong configuration</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>DIVN2 = 8</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x80</name>
<description>DIVN2 = 129 (default after reset)</description>
<value>0x80</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1A3</name>
<description>DIVN2 = 420</description>
<value>0x1A3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVP2</name>
<description>PLL2 DIVP division factor
Set and reset by software to control the frequency of the pll2_p_ck clock.
These bits can be written only when the PLL2 is disabled (PLL2ON = PLL2RDY = 0).
...</description>
<bitOffset>9</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll2_p_ck = vco2_ck</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck = vco2_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll2_p_ck = vco2_ck / 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll2_p_ck = vco2_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll2_p_ck = vco2_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVQ2</name>
<description>PLL2 DIVQ division factor
Set and reset by software to control the frequency of the pll2_q_ck clock.
These bits can be written only when the PLL2 is disabled (PLL2ON = PLL2RDY = 0).
...</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll2_q_ck = vco2_ck </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_q_ck = vco2_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll2_q_ck = vco2_ck / 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll2_q_ck = vco2_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll2_q_ck = vco2_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVR2</name>
<description>PLL2 DIVR division factor
Set and reset by software to control the frequency of the pll2_r_ck clock.
These bits can be written only when the PLL2 is disabled (PLL2ON = PLL2RDY = 0).
...</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll2_r_ck = vco2_ck </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_r_ck = vco2_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll2_r_ck = vco2_ck / 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll2_r_ck = vco2_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll2_r_ck = vco2_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_PLL2FRACR</name>
<displayName>RCC_PLL2FRACR</displayName>
<addressOffset>0x3c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FRACN2</name>
<description>fractional part of the multiplication factor for PLL2 VCO
Set and reset by software to control the fractional part of the multiplication factor of the VCO.
These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.
The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:
128 to 560 MHz if PLL2VCOSEL = 0
150 to 420 MHz if PLL2VCOSEL = 1
VCO output frequency = Fref2_ck x (DIVN2 + (FRACN2 / 213)), with
DIVN2 between 8 and 420
FRACN2 can be between 0 and 213 - 1
The input frequency Fref2_ck must be between 1 and 16 MHz.
In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:
Set the bit PLL2FRACEN to 0.
Write the new fractional value into FRACN2.
Set the bit PLL2FRACEN to 1.</description>
<bitOffset>3</bitOffset>
<bitWidth>13</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCC_PLL3DIVR</name>
<displayName>RCC_PLL3DIVR</displayName>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x01010280</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVN3</name>
<description>Multiplication factor for PLL3 VCO
Set and reset by software to control the multiplication factor of the VCO.
These bits can be written only when the PLL is disabled (PLL3ON = PLL3RDY = 0).
...........: not used
...
...
Others: wrong configurations
The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:
128 to 560 MHz if PLL3VCOSEL = 0
150 to 420 MHz if PLL3VCOSEL = 1
VCO output frequency = Fref3_ck x DIVN3, when fractional value 0 has been loaded into FRACN3, with:
DIVN3 between 8 and 420
The input frequency Fref3_ck must be between 1 and 16MHz</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x6</name>
<description>wrong configuration</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>DIVN3 = 8</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x80</name>
<description>DIVN3 = 129 (default after reset)</description>
<value>0x80</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1A3</name>
<description>DIVN3 = 420</description>
<value>0x1A3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVP3</name>
<description>PLL3 DIVP division factor
Set and reset by software to control the frequency of the pll3_p_ck clock.
These bits can be written only when the PLL3 is disabled (PLL3ON = PLL3RDY = 0).
...</description>
<bitOffset>9</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll3_p_ck = vco3_ck</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_p_ck = vco3_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_p_ck = vco3_ck / 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll3_p_ck = vco3_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll3_p_ck = vco3_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVQ3</name>
<description>PLL3 DIVQ division factor
Set and reset by software to control the frequency of the pll3_q_ck clock.
These bits can be written only when the PLL3 is disabled (PLL3ON = PLL3RDY = 0).
...</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll3_q_ck = vco3_ck </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_q_ck = vco3_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_q_ck = vco3_ck / 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll3_q_ck = vco3_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll3_q_ck = vco3_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVR3</name>
<description>PLL3 DIVR division factor
Set and reset by software to control the frequency of the pll3_r_ck clock.
These bits can be written only when the PLL3 is disabled (PLL3ON = PLL3RDY = 0).
...</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll3_r_ck = vco3_ck </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_r_ck = vco3_ck / 2 (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_r_ck = vco3_ck / 3</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>pll3_r_ck = vco3_ck / 4</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7F</name>
<description>pll3_r_ck = vco3_ck / 128</description>
<value>0x7F</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_PLL3FRACR</name>
<displayName>RCC_PLL3FRACR</displayName>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FRACN3</name>
<description>fractional part of the multiplication factor for PLL3 VCO
Set and reset by software to control the fractional part of the multiplication factor of the VCO.
These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.
The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:
128 to 560 MHz if PLL3VCOSEL = 0
150 to 420 MHz if PLL3VCOSEL = 1
VCO output frequency = Fref3_ck x (DIVN3 + (FRACN3 / 213)), with
DIVN3 between 8 and 420
FRACN3 can be between 0 and 213 - 1
The input frequency Fref3_ck must be between 1 and 16 MHz.
In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:
Set the bit PLL1FRACEN to 0.
Write the new fractional value into FRACN1.
Set the bit PLL1FRACEN to 1.</description>
<bitOffset>3</bitOffset>
<bitWidth>13</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCC_CDCCIPR</name>
<displayName>RCC_CDCCIPR</displayName>
<description>RCC CPU domain kernel clock configuration register </description>
<addressOffset>0x4c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FMCSEL</name>
<description>FMC kernel clock source selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_hclk3 selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_q_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll2_r_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>per_ck selected as kernel peripheral clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPISEL</name>
<description>OCTOSPI kernel clock source selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_hclk3 selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_q_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll2_r_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>per_ck selected as kernel peripheral clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDMMCSEL</name>
<description>SDMMC kernel clock source selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_q_ck selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_r_ck selected as kernel peripheral clock </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKPERSEL</name>
<description>per_ck clock source selection</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>hsi_ker_ck selected as per_ck clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>csi_ker_ck selected as per_ck clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>hse_ck selected as per_ck clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>reserved, the per_ck clock is disabled</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CDCCIP1R</name>
<displayName>RCC_CDCCIP1R</displayName>
<description>RCC CPU domain kernel clock configuration register </description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SAI1SEL</name>
<description>SAI1 and DFSDM1 kernel Aclk clock source selection
Set and reset by software.
If the selected clock is the external clock and this clock is stopped, it isnot be possible to switch to another clock. Refer to for additional information.
Note: DFSDM1 clock source selection is done by DFSDM1SEL.
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_q_ck selected as SAI1 and DFSDM1 Aclk kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck selected as SAI1 and DFSDM1 Aclk kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_p_ck selected as SAI1 and DFSDM1 Aclk kernel clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>I2S_CKIN selected as SAI1 and DFSDM1 Aclk kernel clock </description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>per_ck selected as SAI1 and DFSDM1 Aclk kernel clock</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI2ASEL</name>
<description>SAI2 kernel clock source A selection
Set and reset by software.
If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information.
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the SPDIFRX (see ).</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_q_ck selected as SAI2 kernel clock A (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck selected as SAI2 kernel clock A</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_p_ck selected as SAI2 kernel clock A</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>I2S_CKIN selected as SAI2 kernel clock A</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>per_ck selected as SAI2 kernel clock A</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>spdifrx_symb_ck selected as SAI2 kernel clock A</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI2BSEL</name>
<description>SAI2 kernel clock B source selection
Set and reset by software.
If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information.
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see ).</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_q_ck selected as SAI2 kernel clock B (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck selected as SAI2 kernel clock B</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_p_ck selected as SAI2 kernel clock B</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>I2S_CKIN selected as SAI2 kernel clock B</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>per_ck selected as SAI2 kernel clock B</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>spdifrx_symb_ck selected as SAI2 kernel clock B</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI123SEL</name>
<description>SPI/I2S1,2 and 3 kernel clock source selection
Set and reset by software.
If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information.
others: reserved, the kernel clock is disabled
Note: I2S_CKIN is an external clock taken from a pin.</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_q_ck selected as SPI/I2S1,2 and 3 kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck selected as SPI/I2S1,2 and 3 kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_p_ck selected as SPI/I2S1,2 and 3 kernel clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>I2S_CKIN selected as SPI/I2S1,2 and 3 kernel clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>per_ck selected as SPI/I2S1,2 and 3 kernel clock</description>
<value>0x4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI45SEL</name>
<description>SPI4 and 5 kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk2 clock selected as kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_q_ck is selected as kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_q_ck is selected as kernel clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>hsi_ker_ck is selected as kernel clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>csi_ker_ck is selected as kernel clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>hse_ck is selected as kernel clock</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPDIFRXSEL</name>
<description>SPDIFRX kernel clock source selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll1_q_ck selected as SPDIFRX kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_r_ck selected as SPDIFRX kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_r_ck selected as SPDIFRX kernel clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>hsi_ker_ck selected as SPDIFRX kernel clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM1SEL</name>
<description>DFSDM1 kernel clock Clk source selection
Set and reset by software.
Note: the DFSDM1 Aclk clock source selection is done by SAI1SEL (see ).</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk2 selected as DFSDM1 Clk kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>sys_ck selected as DFSDM1 Clk kernel clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDCANSEL</name>
<description>FDCAN kernel clock source selection
Set and reset by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>hse_ck clock selected as FDCAN kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_q_ck selected as FDCAN kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll2_q_ck selected as FDCAN kernel clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>reserved, the kernel clock is disabled</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWPMISEL</name>
<description>SWPMI kernel clock source selection
Set and reset by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk1 selected as SWPMI kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>hsi_ker_ck selected as SWPMI kernel clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CDCCIP2R</name>
<displayName>RCC_CDCCIP2R</displayName>
<description>RCC CPU domain kernel clock configuration register </description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>USART234578SEL</name>
<description>USART2/3, UART4,5, 7 and 8 (APB1) kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk1 selected as kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_q_ck selected as kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_q_ck selected as kernel clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>hsi_ker_ck selected as kernel clock </description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>csi_ker_ck selected as kernel clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>lse_ck selected as kernel clock</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART16910SEL</name>
<description>USART1, 6, 9 and 10 kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk2 selected as kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_q_ck selected as kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_q_ck selected as kernel clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>hsi_ker_ck selected as kernel clock </description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>csi_ker_ck selected as kernel clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>lse_ck selected as kernel clock</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNGSEL</name>
<description>RNG kernel clock source selection
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>hsi48_ck selected as kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_q_ck selected as kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>lse_ck selected as kernel clock </description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>lsi_ck selected as kernel clock </description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C123SEL</name>
<description>I2C1,2,3 kernel clock source selection
Set and reset by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk1 selected as kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_r_ck selected as kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>hsi_ker_ck selected as kernel clock </description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>csi_ker_ck selected as kernel clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USBSEL</name>
<description>USBOTG 1 and 2 kernel clock source selection
Set and reset by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Disable the kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll1_q_ck selected as kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_q_ck selected as kernel clock </description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>hsi48_ck selected as kernel clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CECSEL</name>
<description>HDMI-CEC kernel clock source selection
Set and reset by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>lse_ck selected as kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>lsi_ck selected as kernel clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>csi_ker_ck divided by 122 selected as kernel clock </description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>reserved, the kernel clock is disabled</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM1SEL</name>
<description>LPTIM1 kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk1 selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_r_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>lse_ck selected as kernel peripheral clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>lsi_ck selected as kernel peripheral clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>per_ck selected as kernel peripheral clock</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_SRDCCIPR</name>
<displayName>RCC_SRDCCIPR</displayName>
<description>RCC SmartRun domain kernel clock configuration register </description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LPUART1SEL</name>
<description>LPUART1 kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk4 selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_q_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_q_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>hsi_ker_ck selected as kernel peripheral clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>csi_ker_ck selected as kernel peripheral clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>lse_ck selected as kernel peripheral clock</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C4SEL</name>
<description>I2C4 kernel clock source selection
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk4 selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_r_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>hsi_ker_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>csi_ker_ck selected as kernel peripheral clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM2SEL</name>
<description>LPTIM2 kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk4 selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_r_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>lse_ck selected as kernel peripheral clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>lsi_ck selected as kernel peripheral clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>per_ck selected as kernel peripheral clock</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM3SEL</name>
<description>LPTIM3 kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk4 selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_p_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_r_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>lse_ck selected as kernel peripheral clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>lsi_ck selected as kernel peripheral clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>per_ck selected as kernel peripheral clock</description>
<value>0x5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCSEL</name>
<description>SAR ADC kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>pll2_p_ck selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll3_r_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>per_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM2SEL</name>
<description>DFSDM2 kernel Clk clock source selection
Set and reset by software.
Note: The DFSDM2 Aclk clock source selection is done by SPI6SEL (see and ).</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk4 selected as DFSDM2 Clk kernel clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>sys_ck selected as DFSDM2 Clk kernel clock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI6SEL</name>
<description>SPI6 kernel clock source selection
Set and reset by software.
others: reserved, the kernel clock is disabled</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rcc_pclk4 selected as kernel peripheral clock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>pll2_q_ck selected as kernel peripheral clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>pll3_q_ck selected as kernel peripheral clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>hsi_ker_ck selected as kernel peripheral clock</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x4</name>
<description>csi_ker_ck selected as kernel peripheral clock</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x5</name>
<description>hse_ck selected as kernel peripheral clock</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x6</name>
<description>I2S_CKIN selected as kernel peripheral clock</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CIER</name>
<displayName>RCC_CIER</displayName>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSIRDYIE</name>
<description>LSI ready interrupt enable
Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSI ready interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSI ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSERDYIE</name>
<description>LSE ready interrupt enable
Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE ready interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIRDYIE</name>
<description>HSI ready interrupt enable
Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI ready interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSERDYIE</name>
<description>HSE ready interrupt enable
Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSE ready interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSE ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSIRDYIE</name>
<description>CSI ready interrupt enable
Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CSI ready interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSI ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48RDYIE</name>
<description>HSI48 ready interrupt enable
Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI48 ready interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI48 ready interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL1RDYIE</name>
<description>PLL1 ready interrupt enable
Set and reset by software to enable/disable interrupt caused by PLL1 lock.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL1 lock interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL1 lock interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL2RDYIE</name>
<description>PLL2 ready interrupt enable
Set and reset by software to enable/disable interrupt caused by PLL2 lock.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL2 lock interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL2 lock interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL3RDYIE</name>
<description>PLL3 ready interrupt enable
Set and reset by software to enable/disable interrupt caused by PLL3 lock.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL3 lock interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL3 lock interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSIE</name>
<description>LSE clock security system interrupt enable
Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE CSS interrupt disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE CSS interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CIFR</name>
<displayName>RCC_CIFR</displayName>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSIRDYF</name>
<description>LSI ready interrupt flag
Reset by software by writing LSIRDYC bit.
Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by the LSI (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by the LSI </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSERDYF</name>
<description>LSE ready interrupt flag
Reset by software by writing LSERDYC bit.
Set by hardware when the LSE clock becomes stable and LSERDYIE is set.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by the LSE (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by the LSE </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIRDYF</name>
<description>HSI ready interrupt flag
Reset by software by writing HSIRDYC bit.
Set by hardware when the HSI clock becomes stable and HSIRDYIE is set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by the HSI (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by the HSI </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSERDYF</name>
<description>HSE ready interrupt flag
Reset by software by writing HSERDYC bit.
Set by hardware when the HSE clock becomes stable and HSERDYIE is set.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by the HSE (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by the HSE </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSIRDYF</name>
<description>CSI ready interrupt flag
Reset by software by writing CSIRDYC bit.
Set by hardware when the CSI clock becomes stable and CSIRDYIE is set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by the CSI (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by the CSI </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48RDYF</name>
<description>HSI48 ready interrupt flag
Reset by software by writing HSI48RDYC bit.
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by the HSI48 oscillator (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by the HSI48 oscillator</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL1RDYF</name>
<description>PLL1 ready interrupt flag
Reset by software by writing PLL1RDYC bit.
Set by hardware when the PLL1 locks and PLL1RDYIE is set.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by PLL1 lock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by PLL1 lock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL2RDYF</name>
<description>PLL2 ready interrupt flag
Reset by software by writing PLL2RDYC bit.
Set by hardware when the PLL2 locks and PLL2RDYIE is set.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by PLL2 lock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by PLL2 lock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL3RDYF</name>
<description>PLL3 ready interrupt flag
Reset by software by writing PLL3RDYC bit.
Set by hardware when the PLL3 locks and PLL3RDYIE is set.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock ready interrupt caused by PLL3 lock (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock ready interrupt caused by PLL3 lock</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSF</name>
<description>LSE clock security system interrupt flag
Reset by software by writing LSECSSC bit.
Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no failure detected on the external 32 kHz oscillator (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>failure detected on the external 32 kHz oscillator</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSECSSF</name>
<description>HSE clock security system interrupt flag
Reset by software by writing HSECSSC bit.
Set by hardware in case of HSE clock failure.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock security interrupt caused by HSE clock failure (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>clock security interrupt caused by HSE clock failure</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CICR</name>
<displayName>RCC_CICR</displayName>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSIRDYC</name>
<description>LSI ready interrupt clear
Set by software to clear LSIRDYF.
Reset by hardware when clear done.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSIRDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSIRDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSERDYC</name>
<description>LSE ready interrupt clear
Set by software to clear LSERDYF.
Reset by hardware when clear done.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSERDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSERDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSIRDYC</name>
<description>HSI ready interrupt clear
Set by software to clear HSIRDYF.
Reset by hardware when clear done.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSIRDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSIRDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSERDYC</name>
<description>HSE ready interrupt clear
Set by software to clear HSERDYF.
Reset by hardware when clear done.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSERDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSERDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSIRDYC</name>
<description>CSI ready interrupt clear
Set by software to clear CSIRDYF.
Reset by hardware when clear done.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CSIRDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSIRDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSI48RDYC</name>
<description>HSI48 ready interrupt clear
Set by software to clear HSI48RDYF.
Reset by hardware when clear done.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSI48RDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSI48RDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL1RDYC</name>
<description>PLL1 ready interrupt clear
Set by software to clear PLL1RDYF.
Reset by hardware when clear done.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL1RDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL1RDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL2RDYC</name>
<description>PLL2 ready interrupt clear
Set by software to clear PLL2RDYF.
Reset by hardware when clear done.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL2RDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL2RDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL3RDYC</name>
<description>PLL3 ready interrupt clear
Set by software to clear PLL3RDYF.
Reset by hardware when clear done.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>PLL3RDYF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PLL3RDYF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSC</name>
<description>LSE clock security system interrupt clear
Set by software to clear LSECSSF.
Reset by hardware when clear done.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSECSSF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSECSSF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSECSSC</name>
<description>HSE clock security system interrupt clear
Set by software to clear HSECSSF.
Reset by hardware when clear done.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSECSSF no effect (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSECSSF cleared</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_BDCR</name>
<displayName>RCC_BDCR</displayName>
<description>RCC Backup domain control register </description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSEON</name>
<description>LSE oscillator enabled
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE oscillator OFF (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE oscillator ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSERDY</name>
<description>LSE oscillator ready
Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE oscillator not ready (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE oscillator ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSEBYP</name>
<description>LSE oscillator bypass
Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE oscillator not bypassed (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE oscillator bypassed</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSEDRV</name>
<description>LSE oscillator driving capability
Set by software to select the driving capability of the LSE oscillator.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>lowest drive (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>medium-low drive</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>medium-high drive</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>highest drive</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSON</name>
<description>LSE clock security system enable
Set by software to enable the clock security system on 32 kHz oscillator.
LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.
Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CSS on 32 kHz oscillator OFF (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CSS on 32 kHz oscillator ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSECSSD</name>
<description>LSE clock security system failure detection
Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no failure detected on 32 kHz oscillator (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>failure detected on 32 kHz oscillator</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSEEXT</name>
<description>low-speed external clock type in Bypass mode
Set and reset by software to select the external clock type (analog or digital).
The external clock must be enabled with the LSEON bit, to be used by the device.
The LSEEXT bit can be written only if the LSE oscillator is disabled.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSE in analog mode (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE in digital mode (do not use if RTC is active).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCSEL</name>
<description>RTC clock source selection
Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again.
If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST).</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-writeOnce</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no clock (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSE selected as RTC clock</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>LSI selected as RTC clock</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>HSE divided by RTCPRE value selected as RTC clock</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCEN</name>
<description>RTC clock enable
Set and reset by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>rtc_ck disabled (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>rtc_ck enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VSWRST</name>
<description>VSwitch domain software reset
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>reset not activated (default after Backup domain reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the entire VSW domain</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CSR</name>
<displayName>RCC_CSR</displayName>
<description>RCC clock control and status register </description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LSION</name>
<description>LSI oscillator enable
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSI is OFF (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSI is ON</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSIRDY</name>
<description>LSI oscillator ready
Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable.
This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0.
This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LSI clock is not ready (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LSI clock is ready</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB3RSTR</name>
<displayName>RCC_AHB3RSTR</displayName>
<addressOffset>0x7c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MDMARST</name>
<description>MDMA block reset
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset MDMA block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets MDMA block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2DRST</name>
<description>DMA2D block reset
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset DMA2D block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets DMA2D block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JPGDECRST</name>
<description>JPGDEC block reset
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset JPGDEC block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets JPGDEC block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMCRST</name>
<description>FMC block reset
Set and reset by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset FMC block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets FMC block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPI1RST</name>
<description>OCTOSPI1 and OCTOSPI1 delay blocks reset
Set and reset by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset OCTOSPI1 and OCTOSPI1 delay blocks (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets OCTOSPI1 and OCTOSPI1 delay blocks</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDMMC1RST</name>
<description>SDMMC1 and SDMMC1 delay blocks reset
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset SDMMC1 and SDMMC1 delay blocks (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets SDMMC1 and SDMMC1 delay blocks</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPI2RST</name>
<description>OCTOSPI2 and OCTOSPI2 delay block reset
Set and reset by software</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the OCTOSPI2 and OCTOSPI2 delay block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the OCTOSPI2 and OCTOSPI2 delay block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPIMRST</name>
<description>OCTOSPIM reset
Set and reset by software</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the OCTOSPIM (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the OCTOSPIM</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OTFD1RST</name>
<description>OTFD1 reset
Set and reset by software
Take care that resetting the OTFD means loosing the decryption key loaded during secure boot.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the OTFD1 (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the OTFD1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OTFD2RST</name>
<description>OTFD2 reset
Set and reset by software
Take care that resetting the OTFD means loosing the decryption key loaded during secure boot.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the OTFD2 (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the OTFD2</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GFXMMURST</name>
<description>GFXMMU reset
Set and reset by software</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GFXMMU (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GFXMMU</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB1RSTR</name>
<displayName>RCC_AHB1RSTR</displayName>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA1RST</name>
<description>DMA1 and DMAMUX1 blocks reset
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset DMA1 and DMAMUX1 blocks (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets DMA1 and DMAMUX1 blocks</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2RST</name>
<description>DMA2 and DMAMUX2 blocks reset
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset DMA2 and DMAMUX2 blocks (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets DMA2 and DMAMUX2 blocks</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC12RST</name>
<description>ADC1 and 2 blocks reset
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset ADC1 and 2 blocks (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets ADC1 and 2 blocks</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRCRST</name>
<description>CRC block reset
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset CRC block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets CRC block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USB1OTGRST</name>
<description>USB1OTG block reset
Set and reset by software.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset USB1OTG block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets USB1OTG block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB2RSTR</name>
<displayName>RCC_AHB2RSTR</displayName>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DCMI_PSSIRST</name>
<description>digital camera interface block reset (DCMI or PSSI depending which IP is active)
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the DCMI/PSSI block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the DCMI/PSSI block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSEMRST</name>
<description>HSEM block reset
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset HSEM block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets HSEM block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNGRST</name>
<description>random number generator block reset
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset RNG block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets RNG block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDMMC2RST</name>
<description>SDMMC2 and SDMMC2 delay blocks reset
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset SDMMC2 and SDMMC2 delay blocks (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets SDMMC2 and SDMMC2 delay blocks</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BDMA1RST</name>
<description>BDMA1 reset (DFSDM dedicated DMA)
Set and reset by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset DMA block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets DMA block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB4RSTR</name>
<displayName>RCC_AHB4RSTR</displayName>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPIOARST</name>
<description>GPIOA block reset
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOA block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOA block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOBRST</name>
<description>GPIOB block reset
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOB block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOB block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOCRST</name>
<description>GPIOC block reset
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOC block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOC block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIODRST</name>
<description>GPIOD block reset
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOD block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOD block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOERST</name>
<description>GPIOE block reset
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOE block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOE block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOFRST</name>
<description>GPIOF block reset
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOF block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOF block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOGRST</name>
<description>GPIOG block reset
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOG block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOG block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOHRST</name>
<description>GPIOH block reset
Set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOH block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOH block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOIRST</name>
<description>GPIOI block reset
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOI block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOI block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOJRST</name>
<description>GPIOJ block reset
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOJ block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOJ block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOKRST</name>
<description>GPIOK block reset
Set and reset by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the GPIOK block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the GPIOK block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BDMA2RST</name>
<description>SmartRun domain DMA and DMAMUX blocks reset
Set and reset by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the DMA and DMAMUX blocks (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the DMA and DMAMUX blocks</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB3RSTR</name>
<displayName>RCC_APB3RSTR</displayName>
<addressOffset>0x8c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LTDCRST</name>
<description>LTDC block reset
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the LTDC block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the LTDC block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1LRSTR</name>
<displayName>RCC_APB1LRSTR</displayName>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM2RST</name>
<description>TIM2 block reset
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM2 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM2 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM3RST</name>
<description>TIM3 block reset
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM3 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM3 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM4RST</name>
<description>TIM4 block reset
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM4 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM4 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM5RST</name>
<description>TIM5 block reset
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM5 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM5 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM6RST</name>
<description>TIM6 block reset
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM6 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM6 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM7RST</name>
<description>TIM7 block reset
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM7 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM7 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM12RST</name>
<description>TIM12 block reset
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM12 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM12 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM13RST</name>
<description>TIM13 block reset
Set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM13 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM13 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM14RST</name>
<description>TIM14 block reset
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM14 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM14 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM1RST</name>
<description>LPTIM1 block reset
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the LPTIM1 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the LPTIM1 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI2RST</name>
<description>SPI2 block reset
Set and reset by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SPI2 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SPI2 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI3RST</name>
<description>SPI3 block reset
Set and reset by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SPI3 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SPI3 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPDIFRXRST</name>
<description>SPDIFRX block reset
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SPDIFRX block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SPDIFRX block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2RST</name>
<description>USART2 block reset
Set and reset by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the USART2 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the USART2 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3RST</name>
<description>USART3 block reset
Set and reset by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the USART3 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the USART3 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART4RST</name>
<description>UART4 block reset
Set and reset by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the UART4 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the UART4 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART5RST</name>
<description>UART5 block reset
Set and reset by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the UART5 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the UART5 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1RST</name>
<description>I2C1 block reset
Set and reset by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the I2C1 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the I2C1 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C2RST</name>
<description>I2C2 block reset
Set and reset by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the I2C2 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the I2C2 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C3RST</name>
<description>I2C3 block reset
Set and reset by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the I2C3 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the I2C3 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CECRST</name>
<description>HDMI-CEC block reset
Set and reset by software.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the HDMI-CEC block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the HDMI-CEC block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC1RST</name>
<description>DAC1 (containing two converters) reset
Set and reset by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the DAC1 (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the DAC1</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART7RST</name>
<description>UART7 block reset
Set and reset by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the UART7 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the UART7 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART8RST</name>
<description>UART8 block reset
Set and reset by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the UART8 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the UART8 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1HRSTR</name>
<displayName>RCC_APB1HRSTR</displayName>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRSRST</name>
<description>clock recovery system reset
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset CRS (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets CRS</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWPMIRST</name>
<description>SWPMI block reset
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SWPMI block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SWPMI block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPAMPRST</name>
<description>OPAMP block reset
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the OPAMP block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the OPAMP block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIOSRST</name>
<description>MDIOS block reset
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the MDIOS block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the MDIOS block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDCANRST</name>
<description>FDCAN block reset
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the FDCAN block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the FDCAN block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB2RSTR</name>
<displayName>RCC_APB2RSTR</displayName>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM1RST</name>
<description>TIM1 block reset
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM1 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM1 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM8RST</name>
<description>TIM8 block reset
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM8 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM8 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1RST</name>
<description>USART1 block reset
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the USART1 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the USART1 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART6RST</name>
<description>USART6 block reset
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the USART6 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the USART6 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART9RST</name>
<description>UART9 block reset
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the UART9 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the UART9 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART10RST</name>
<description>USART10 block reset
Set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the USART10 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the USART10 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1RST</name>
<description>SPI1 block reset
Set and reset by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SPI1 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SPI1 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI4RST</name>
<description>SPI4 block reset
Set and reset by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SPI4 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SPI4 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM15RST</name>
<description>TIM15 block reset
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM15 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM15 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM16RST</name>
<description>TIM16 block reset
Set and reset by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM16 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM16 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM17RST</name>
<description>TIM17 block reset
Set and reset by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the TIM17 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the TIM17 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI5RST</name>
<description>SPI5 block reset
Set and reset by software.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SPI5 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SPI5 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI1RST</name>
<description>SAI1 block reset
Set and reset by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SAI1 (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SAI1 </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI2RST</name>
<description>SAI2 block reset
Set and reset by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SAI2 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SAI2 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM1RST</name>
<description>DFSDM1 block reset
Set and reset by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset DFSDM1 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets DFSDM1 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB4RSTR</name>
<displayName>RCC_APB4RSTR</displayName>
<addressOffset>0x9c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSCFGRST</name>
<description>SYSCFG block reset
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SYSCFG block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SYSCFG block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPUART1RST</name>
<description>LPUART1 block reset
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the LPUART1 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the LPUART1 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI6RST</name>
<description>SPI6 block reset
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the SPI6 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the SPI6 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C4RST</name>
<description>I2C4 block reset
Set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the I2C4 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the I2C4 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM2RST</name>
<description>LPTIM2 block reset
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the LPTIM2 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the LPTIM2 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM3RST</name>
<description>LPTIM3 block reset
Set and reset by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the LPTIM3 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the LPTIM3 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC2RST</name>
<description>DAC2 (containing one converter) reset
Set and reset by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the DAC2 (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the DAC2</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP12RST</name>
<description>COMP1 and 2 blocks reset
Set and reset by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the COMP1 and 2 blocks (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the COMP1 and 2 blocks</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFRST</name>
<description>VREF block reset
Set and reset by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the VREF block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the VREF block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTSRST</name>
<description>Digital temperature sensor block reset
Set and reset by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the DTS block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the DTS block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM2RST</name>
<description>DFSDM2 block reset
Set and reset by software.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>does not reset the DFSDM2 block (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the DFSDM2 block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_SRDAMR</name>
<displayName>RCC_SRDAMR</displayName>
<description>RCC SmartRun domain Autonomous mode register </description>
<addressOffset>0xa8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BDMA2AMEN</name>
<description>SmartRun domain DMA and DMAMUX Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>BDMA2 and DMAMUX2 peripheral clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>BDMA2 and DMAMUX2 peripheral clocks enabled when the SmartRun domain is in Run.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOAMEN</name>
<description>GPIO Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIO peripheral clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIO peripheral clocks enabled when the SmartRun domain is in Run.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPUART1AMEN</name>
<description>LPUART1 Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPUART1 peripheral clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPUART1 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI6AMEN</name>
<description>SPI6 Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI6 peripheral clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI6 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C4AMEN</name>
<description>I2C4 Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C4 peripheral clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C4 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM2AMEN</name>
<description>LPTIM2 Autonomous mode enable
Set and reset by software.
Refer to for additional information</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM2 peripheral clocks are disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM2 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM3AMEN</name>
<description>LPTIM3 Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM3 peripheral clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM3 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC2AMEN</name>
<description>DAC2 (containing one converter) Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC2 peripheral clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC2 peripheral clocks enabled when the SmartRun domain is in Run.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP12AMEN</name>
<description>COMP1 and 2 Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>COMP1 and 2 peripheral clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>COMP1 and 2 peripheral clocks enabled when the SmartRun domain is in Run.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFAMEN</name>
<description>VREF Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>VREF clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>VREF clocks enabled when the SmartRun domain is in Run or Stop mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCAMEN</name>
<description>RTC Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RTC bus clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RTC bus clocks enabled when the SmartRun domain is in Run.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTSAMEN</name>
<description>Digital temperature sensor Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DTS clocks disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DTS clocks enabled when the SmartRun domain is in Run.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM2AMEN</name>
<description>DFSDM2 Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM2 clock disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM2 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock enabled when the SmartRun domain is in Stop mode.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BKPRAMAMEN</name>
<description>Backup RAM Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Backup RAM clock disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Backup RAM clock enabling is controlled by the SmartRun domain state.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRDSRAMAMEN</name>
<description>SmartRun domain SRAM Autonomous mode enable
Set and reset by software.
Refer to for additional information.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SRDSRAM clock disabled when the CPU is in CStop (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SRDSRAM bus clock enabled when the SmartRun domain is in Run.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_CKGAENR</name>
<displayName>RCC_CKGAENR</displayName>
<description>RCC AXI clocks gating enable register </description>
<addressOffset>0xb0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AXICKG</name>
<description>AXI interconnect matrix clock gating
This bit is set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI interconnect matrix clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHBCKG</name>
<description>AXI master AHB clock gating
This bit is set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix master AHB clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPUCKG</name>
<description>AXI master CPU clock gating
This bit is set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix master CPU clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDMMCCKG</name>
<description>AXI master SDMMC clock gating
This bit is set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix master SDMMC clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDMACKG</name>
<description>AXI master MDMA clock gating
This bit is set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix master MDMA clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2DCKG</name>
<description>AXI master DMA2D clock gating
This bit is set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix master DMA2D clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LTDCCKG</name>
<description>AXI master LTDC clock gating
This bit is set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix master LTDC clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GFXMMUMCKG</name>
<description>AXI master GFXMMU clock gating
This bit is set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix master GFXMMU clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHB12CKG</name>
<description>AXI slave AHB12 clock gating
This bit is set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave AHB12 clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHB34CKG</name>
<description>AXI slave AHB34 clock gating
This bit is set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave AHB34 clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLIFTCKG</name>
<description>AXI slave Flash interface (FLIFT) clock gating
This bit is set and reset by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave FLIFT clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPI2CKG</name>
<description>AXI slave OCTOSPI2 clock gating
This bit is set and reset by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave OCTOSPI2 clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMCCKG</name>
<description>AXI slave FMC clock gating
This bit is set and reset by software.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave FMC clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPI1CKG</name>
<description>AXI slave OCTOSPI1 clock gating
This bit is set and reset by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave OCTOSPI1 clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AXIRAM1CKG</name>
<description>AXI slave SRAM1 clock gating
This bit is set and reset by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave SRAM1 clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AXIRAM2CKG</name>
<description>AXI matrix slave SRAM2 clock gating
This bit is set and reset by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave SRAM2 clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AXIRAM3CKG</name>
<description>AXI matrix slave SRAM3 clock gating
This bit is set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave SRAM3 clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GFXMMUSCKG</name>
<description>AXI matrix slave GFXMMU clock gating
This bit is set and reset by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The AXI matrix slave GFXMMU clock is enabled on bus transaction request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ECCRAMCKG</name>
<description>RAM error code correction (ECC) clock gating
This bit is set and reset by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The ECC clock is enabled only during a RAM access.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTICKG</name>
<description>EXTI clock gating
This bit is set and reset by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The clock is enabled after an event detection and stopped again when the event flag is cleared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JTAGCKG</name>
<description>JTAG automatic clock gating
This bit is set and reset by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The clock gating is disabled. The clock is always enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The clock gating is enabled. The clock is disabled except if a JTAG connection has been detected</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_RSR</name>
<displayName>RCC_RSR</displayName>
<description>RCC reset status register </description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<resetValue>0x00E80000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RMVF</name>
<description>remove reset flag
Set and reset by software to reset the value of the reset flags.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>reset of the reset flags not activated (default after power-on reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>resets the value of the reset flags</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CDRSTF</name>
<description>CPU domain power-switch reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a the CPU domain exits from DStop or after of power-on reset. Set also when the CPU domain exists DStop2 but only when a pad reset has occurred during DStop2 (PINRST bit also set by hardware)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no CPU domain power-switch reset occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CPU domain power-switch (ePOD2) reset occurred (default after power-on reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BORRSTF</name>
<description>BOR reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a BOR reset occurs (pwr_bor_rst).</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no BOR reset occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>BOR reset occurred (default after power-on reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PINRSTF</name>
<description>pin reset flag (NRST)
Reset by software by writing the RMVF bit.
Set by hardware when a reset from pin occurs.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no reset from pin occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>reset from pin occurred (default after power-on reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORRSTF</name>
<description>POR/PDR reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a POR/PDR reset occurs.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no POR/PDR reset occurred</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>POR/PDR reset occurred (default after power-on reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SFTRSTF</name>
<description>system reset from CPU reset flag
Reset by software by writing the RMVF bit.
Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no CPU software reset occurred (default after power-on reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>a system reset has been generated by the CPU</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IWDGRSTF</name>
<description>independent watchdog reset flag
Reset by software by writing the RMVF bit.
Set by hardware when an independent watchdog reset occurs.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no independent watchdog reset occurred (default after power-on reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>independent watchdog reset occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDGRSTF</name>
<description>window watchdog reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a window watchdog reset occurs.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no window watchdog reset occurred from WWDG (default after power-on reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>window watchdog reset occurred from WWDG</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPWRRSTF</name>
<description>reset due to illegal CD DStop or CD DStop2 or CPU CStop flag
Reset by software by writing the RMVF bit.
Set by hardware when the CPU domain goes erroneously in DStop or DStop2, or when the CPU goes erroneously in CStop.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no illegal reset occurred (default after power-on reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>illegal CD DStop or CD DStop2 or CPU CStop reset occurred</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB3ENR</name>
<displayName>RCC_AHB3ENR</displayName>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MDMAEN</name>
<description>MDMA peripheral clock enable
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>MDMA peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>MDMA peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2DEN</name>
<description>DMA2D peripheral clock enable
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA2D peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA2D peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JPGDECEN</name>
<description>JPGDEC peripheral clock enable
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>JPGDEC peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>JPGDEC peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMCEN</name>
<description>FMC peripheral clocks enable
Set and reset by software.
The peripheral clocks of the FMC are the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FMC peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FMC peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPI1EN</name>
<description>OCTOSPI1 and OCTOSPI1 delay clock enable
Set and reset by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OCTOSPI1 and OCTOSPI1 delay clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OCTOSPI1 and OCTOSPI1 delay clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDMMC1EN</name>
<description>SDMMC1 and SDMMC1 delay clock enable
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SDMMC1 and SDMMC1 delay clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SDMMC1 and SDMMC1 delay clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPI2EN</name>
<description>OCTOSPI2 clock enable
Set and reset by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OCTOSPI2 and OCTOSPI2 delay clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OCTOSPI2 OCTOSPI2 delay clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPIMEN</name>
<description>OCTOSPIM clock enable
Set and reset by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OCTOSPIM clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OCTOSPIM clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OTFD1EN</name>
<description>OTFD1 clock enable
Set and reset by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OTFD1 clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OTFD1 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OTFD2EN</name>
<description>OTFD2 clock enable
Set and reset by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OTFD2 clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OTFD2 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GFXMMUEN</name>
<description>GFXMMU clock enable
Set and reset by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GFXMMU clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GFXMMU clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB1ENR</name>
<displayName>RCC_AHB1ENR</displayName>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA1EN</name>
<description>DMA1 clock enable
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA1 clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA1 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2EN</name>
<description>DMA2 clock enable
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA2 clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA2 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC12EN</name>
<description>ADC1 and 2 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>ADC1 and 2 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>ADC1 and 2 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRCEN</name>
<description>CRC peripheral clock enable
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CRC peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CRC peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USB1OTGEN</name>
<description>USB1OTG peripheral clocks enable
Set and reset by software.
The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USB1OTG peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USB1OTG peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USB1ULPIEN</name>
<description>USB_PHY1 clocks enable
Set and reset by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USB1ULPI PHY clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USB1ULPI PHY clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB2ENR</name>
<displayName>RCC_AHB2ENR</displayName>
<addressOffset>0x13c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DCMI_PSSIEN</name>
<description>digital camera interface peripheral clock enable (DCMI or PSSI depending which IP is active)
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DCMI/PSSI peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DCMI/PSSI peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSEMEN</name>
<description>HSEM peripheral clock enable
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HSEM peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HSEM peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNGEN</name>
<description>RNG peripheral clocks enable
Set and reset by software.
The peripheral clocks of the RNG are the kernel clock selected by RNGSEL and provided to rng_clk input, and the rcc_hclk2 bus interface clock.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RNG peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RNG peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDMMC2EN</name>
<description>SDMMC2 and SDMMC2 delay clock enable
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SDMMC2 and SDMMC2 delay clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SDMMC2 and SDMMC2 delay clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BDMA1EN</name>
<description>DMA clock enable (DFSDM dedicated DMA)
Set and reset by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHBSRAM1EN</name>
<description>AHBSRAM1 block enable
Set and reset by software.
When set, this bit indicates that the SRAM1 is allocated by the CPU. It causes the CPU domain to take into account also the CPU operation modes, keeping the CPU domain in DRun when the CPU is in CRun.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AHBSRAM1 interface clock is disabled. (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AHBSRAM1 interface clock is enabled. </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHBSRAM2EN</name>
<description>AHBSRAM2 block enable
Set and reset by software.
When set, this bit indicates that the SRAM2 is allocated by the CPU. It causes the CPU domain to take into account also the CPU operation modes, keeping the CPU domain in DRun when the CPU is in CRun.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AHBSRAM2 interface clock is disabled. (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AHBSRAM2 interface clock is enabled. </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB4ENR</name>
<displayName>RCC_AHB4ENR</displayName>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPIOAEN</name>
<description>GPIOA peripheral clock enable
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOA peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOA peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOBEN</name>
<description>GPIOB peripheral clock enable
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOB peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOB peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOCEN</name>
<description>GPIOC peripheral clock enable
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOC peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOC peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIODEN</name>
<description>GPIOD peripheral clock enable
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOD peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOD peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOEEN</name>
<description>GPIOE peripheral clock enable
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOE peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOE peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOFEN</name>
<description>GPIOF peripheral clock enable
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOF peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOF peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOGEN</name>
<description>GPIOG peripheral clock enable
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOG peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOG peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOHEN</name>
<description>GPIOH peripheral clock enable
Set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOH peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOH peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOIEN</name>
<description>GPIOI peripheral clock enable
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOI peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOI peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOJEN</name>
<description>GPIOJ peripheral clock enable
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOJ peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOJ peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOKEN</name>
<description>GPIOK peripheral clock enable
Set and reset by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOK peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOK peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BDMA2EN</name>
<description>SmartRun domain DMA and DMAMUX clock enable
Set and reset by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>BDMA2 and DMAMUX2 clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>BDMA2 and DMAMUX2 clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BKPRAMEN</name>
<description>Backup RAM clock enable
Set and reset by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Backup RAM clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Backup RAM clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRDSRAMEN</name>
<description>SmartRun domain SRAM clock enable
Set and reset by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SRDSRAM clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SRDSRAM clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB3ENR</name>
<displayName>RCC_APB3ENR</displayName>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LTDCEN</name>
<description>LTDC clock enable
Provides the clock (ltdc_pclk, ltdc_aclk, ltdc_ker_ck) to the LTDC block.
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LTDC peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LTDC peripheral clock provided to the LTDC block</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDGEN</name>
<description>WWDG clock enable
Set by software, and reset by hardware when a system reset occurs.
Note that in order to work properly, before enabling the WWDG, the bit WW1RSC must be set to 1.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>WWDG peripheral clock disable (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>WWDG peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1LENR</name>
<displayName>RCC_APB1LENR</displayName>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM2EN</name>
<description>TIM2 peripheral clock enable
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM2 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM2 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM3EN</name>
<description>TIM3 peripheral clock enable
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM3 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM3 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM4EN</name>
<description>TIM4 peripheral clock enable
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM4 peripheral clock disable (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM4 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM5EN</name>
<description>TIM5 peripheral clock enable
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM5 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM5 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM6EN</name>
<description>TIM6 peripheral clock enable
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM6 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM6 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM7EN</name>
<description>TIM7 peripheral clock enable
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM7 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM7 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM12EN</name>
<description>TIM12 peripheral clock enable
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM12 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM12 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM13EN</name>
<description>TIM13 peripheral clock enable
Set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM13 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM13 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM14EN</name>
<description>TIM14 peripheral clock enable
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM14 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM14 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM1EN</name>
<description>LPTIM1 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM1 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM1 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI2EN</name>
<description>SPI2 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI2 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI2 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI3EN</name>
<description>SPI3 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI3 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI3 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPDIFRXEN</name>
<description>SPDIFRX peripheral clocks enable
Set and reset by software.
The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPDIFRX peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPDIFRX peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2EN</name>
<description>USART2peripheral clocks enable
Set and reset by software.
The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART2 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART2 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3EN</name>
<description>USART3 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART3 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART3 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART4EN</name>
<description>UART4 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART4 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART4 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART5EN</name>
<description>UART5 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the UART5 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART5 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART5 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1EN</name>
<description>I2C1 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the I2C1 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C1 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C1 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C2EN</name>
<description>I2C2 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the I2C2 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C2 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C2 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C3EN</name>
<description>I2C3 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the I2C3 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C3 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C3 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CECEN</name>
<description>HDMI-CEC peripheral clock enable
Set and reset by software.
The peripheral clocks of the HDMI-CEC are the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HDMI-CEC peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HDMI-CEC peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC1EN</name>
<description>DAC1 (containing two converters) peripheral clock enable
Set and reset by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC1 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC1 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART7EN</name>
<description>UART7 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the UART7 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART7 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART7 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART8EN</name>
<description>UART8 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the UART8 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART8 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART8 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1HENR</name>
<displayName>RCC_APB1HENR</displayName>
<addressOffset>0x14c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRSEN</name>
<description>clock recovery system peripheral clock enable
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CRS peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CRS peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWPMIEN</name>
<description>SWPMI peripheral clocks enable
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SWPMI peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SWPMI peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPAMPEN</name>
<description>OPAMP peripheral clock enable
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OPAMP peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OPAMP peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIOSEN</name>
<description>MDIOS peripheral clock enable
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>MDIOS peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>MDIOS peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDCANEN</name>
<description>FDCAN peripheral clocks enable
Set and reset by software.
The peripheral clocks of the FDCAN are the kernel clock selected by FDCANSEL and provided to fdcan_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FDCAN peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FDCAN peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB2ENR</name>
<displayName>RCC_APB2ENR</displayName>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM1EN</name>
<description>TIM1 peripheral clock enable
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM1 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM1 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM8EN</name>
<description>TIM8 peripheral clock enable
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM8 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM8 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1EN</name>
<description>USART1 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the USART1 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART1 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART1 peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART6EN</name>
<description>USART6 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the USART6 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART6 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART6 peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART9EN</name>
<description>UART9 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART9 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART9 peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART10EN</name>
<description>USART10 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART10 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART10 peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1EN</name>
<description>SPI1 Peripheral Clocks Enable
Set and reset by software.
The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI1 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI1 peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI4EN</name>
<description>SPI4 Peripheral Clocks Enable
Set and reset by software.
The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI4 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI4 peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM15EN</name>
<description>TIM15 peripheral clock enable
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM15 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM15 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM16EN</name>
<description>TIM16 peripheral clock enable
Set and reset by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM16 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM16 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM17EN</name>
<description>TIM17 peripheral clock enable
Set and reset by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM17 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM17 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI5EN</name>
<description>SPI5 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI5 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI5 peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI1EN</name>
<description>SAI1 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SAI1 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SAI1 peripheral clocks enabled:</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI2EN</name>
<description>SAI2 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SAI2 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SAI2 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM1EN</name>
<description>DFSDM1 peripheral clocks enable
Set and reset by software.
DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively,</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM1 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM1 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB4ENR</name>
<displayName>RCC_APB4ENR</displayName>
<addressOffset>0x154</addressOffset>
<size>0x20</size>
<resetValue>0x00010000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSCFGEN</name>
<description>SYSCFG peripheral clock enable
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SYSCFG peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SYSCFG peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPUART1EN</name>
<description>LPUART1 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPUART1 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPUART1 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI6EN</name>
<description>SPI6 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the SPI6 are the kernel clock selected by SPI6SEL and provided to spi_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI6 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI6 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C4EN</name>
<description>I2C4 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the I2C4 are the kernel clock selected by I2C4SEL and provided to i2C_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C4 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C4 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM2EN</name>
<description>LPTIM2 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM2 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM2 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM3EN</name>
<description>LPTIM3 peripheral clocks enable
Set and reset by software.
The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM3 peripheral clocks disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM3 peripheral clocks enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC2EN</name>
<description>DAC2 (containing one converter) peripheral clock enable
Set and reset by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC2 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC2 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP12EN</name>
<description>COMP1 and 2 peripheral clock enable
Set and reset by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>COMP1 and 2 peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>COMP1 and 2 peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFEN</name>
<description>VREF peripheral clock enable
Set and reset by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>VREF peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>VREF peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCAPBEN</name>
<description>RTC APB clock enable
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The register clock interface of the RTC (APB) is disabled </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The register clock interface of the RTC (APB) is enabled (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTSEN</name>
<description>Digital temperature sensor peripheral clock enable
Set and reset by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DTS peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DTS peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM2EN</name>
<description>DFSDM2peripheral clock enable
Set and reset by software.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM2peripheral peripheral clock disabled (default after reset)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM2peripheral peripheral clock enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB3LPENR</name>
<displayName>RCC_AHB3LPENR</displayName>
<addressOffset>0x15c</addressOffset>
<size>0x20</size>
<resetValue>0xFDE95131</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MDMALPEN</name>
<description>MDMA clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>MDMA peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>MDMA peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2DLPEN</name>
<description>DMA2D clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA2D peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA2D peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JPGDECLPEN</name>
<description>JPGDEC clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>JPGDEC peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>JPGDEC peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLITFLPEN</name>
<description>FLITF clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FLITF clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FLITF clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMCLPEN</name>
<description>FMC peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the FMC are the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FMC peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FMC peripheral clocks enabled during CSleep mode (default after reset):</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPI1LPEN</name>
<description>OCTOSPI1 and OCTOSPI1 delay clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OCTOSPI1 and OCTOSPI1 delay clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OCTOSPI1 and OCTOSPI1 delay clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDMMC1LPEN</name>
<description>SDMMC1 and SDMMC1 delay clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SDMMC1 and SDMMC1 delay clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SDMMC1 and SDMMC1 delay clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPI2LPEN</name>
<description>OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OCTOSPI2 and OCTOSPI2 delay clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OCTOSPI2 and OCTOSPI2 delay clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCTOSPIMLPEN</name>
<description>OCTOSPIM block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OCTOSPIM interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OCTOSPIM interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OTFD1LPEN</name>
<description>OTFD1 block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OTFD1 interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OTFD1 interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OTFD2LPEN</name>
<description>OTFD2 block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OTFD2 interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OTFD2 interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GFXMMULPEN</name>
<description>GFXMMU block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GFXMMU interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GFXMMU interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AXISRAM2LPEN</name>
<description>AXISRAM2 block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AXISRAM2 interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AXISRAM2 interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AXISRAM3LPEN</name>
<description>AXISRAM3 block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AXISRAM3 interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AXISRAM3 interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM1LPEN</name>
<description>DTCM1 block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DTCM1 interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DTCM1 interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTCM2LPEN</name>
<description>DTCM2 block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DTCM2 interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DTCM2 interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITCMLPEN</name>
<description>ITCM block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>ITCM interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>ITCM interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AXISRAM1LPEN</name>
<description>AXISRAM1 block clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AXISRAM1 interface clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AXISRAM1 interface clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB1LPENR</name>
<displayName>RCC_AHB1LPENR</displayName>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<resetValue>0x06000223</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA1LPEN</name>
<description>DMA1 clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA1 clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA1 clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA2LPEN</name>
<description>DMA2 clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DMA2 clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DMA2 clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC12LPEN</name>
<description>ADC1 and 2 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>ADC1 and 2 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>ADC1 and 2 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRCLPEN</name>
<description>CRC peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CRC peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CRC peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USB1OTGLPEN</name>
<description>USB1OTG peripheral clock enable during CSleep mode
Set and reset by software.
The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USB1OTG peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USB1OTG peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USB1ULPILPEN</name>
<description>USB_PHY1 clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USB_PHY1 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USB_PHY1 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB2LPENR</name>
<displayName>RCC_AHB2LPENR</displayName>
<addressOffset>0x164</addressOffset>
<size>0x20</size>
<resetValue>0x60000A71</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DCMI_PSSILPEN</name>
<description>digital camera interface peripheral clock enable during CSleep mode (DCMI or PSSI depending which IP is active)
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DCMI/PSSI peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DCMI/PSSI peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RNGLPEN</name>
<description>RNG peripheral clock enable during CSleep mode
Set and reset by software.
The peripheral clocks of the RNG are the kernel clock selected by RNGSEL and provided to rng_clk input, and the rcc_hclk2 bus interface clock.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RNG peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RNG peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDMMC2LPEN</name>
<description>SDMMC2 and SDMMC2 delay clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SDMMC2 and SDMMC2 delay clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SDMMC2 and SDMMC2 delay clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDMDMALPEN</name>
<description>DFSDMDMA clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDMDMA clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDMDMA clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHBSRAM1LPEN</name>
<description>AHBSRAM1 clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AHBSRAM1 clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AHBSRAM1 clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHBSRAM2LPEN</name>
<description>AHBSRAM2 clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AHBSRAM2 clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AHBSRAM2 clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_AHB4LPENR</name>
<displayName>RCC_AHB4LPENR</displayName>
<addressOffset>0x168</addressOffset>
<size>0x20</size>
<resetValue>0x302007FF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPIOALPEN</name>
<description>GPIOA peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOA peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOA peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOBLPEN</name>
<description>GPIOB peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOB peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOB peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOCLPEN</name>
<description>GPIOC peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOC peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOC peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIODLPEN</name>
<description>GPIOD peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOD peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOD peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOELPEN</name>
<description>GPIOE peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOE peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOE peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOFLPEN</name>
<description>GPIOF peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOF peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOF peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOGLPEN</name>
<description>GPIOG peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOG peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOG peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOHLPEN</name>
<description>GPIOH peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOH peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOH peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOILPEN</name>
<description>GPIOI peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOI peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOI peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOJLPEN</name>
<description>GPIOJ peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOJ peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOJ peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GPIOKLPEN</name>
<description>GPIOK peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>GPIOK peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>GPIOK peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BDMA2LPEN</name>
<description>SmartRun domain DMA and DMAMUX clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>BDMA2 and DMAMUX2 clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>BDMA2 and DMAMUX2 clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BKPRAMLPEN</name>
<description>Backup RAM clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Backup RAM clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Backup RAM clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRDSRAMLPEN</name>
<description>SmartRun domain SRAM clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SRDSRAM clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SRDSRAM clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB3LPENR</name>
<displayName>RCC_APB3LPENR</displayName>
<addressOffset>0x16c</addressOffset>
<size>0x20</size>
<resetValue>0x00000048</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LTDCLPEN</name>
<description>LTDC peripheral clock enable during CSleep mode
Set and reset by software.
The LTDC peripheral clocks are the kernel clock provided to ltdc_ker_ck input and the rcc_pclk3 bus interface clock.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LTDC clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LTDC clock provided to the LTDC during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WWDGLPEN</name>
<description>WWDG clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>WWDG clock disable during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>WWDG clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1LLPENR</name>
<displayName>RCC_APB1LLPENR</displayName>
<addressOffset>0x170</addressOffset>
<size>0x20</size>
<resetValue>0xE8FFC3FF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM2LPEN</name>
<description>TIM2 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM2 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM2 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM3LPEN</name>
<description>TIM3 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM3 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM3 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM4LPEN</name>
<description>TIM4 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM4 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM4 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM5LPEN</name>
<description>TIM5 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM5 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM5 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM6LPEN</name>
<description>TIM6 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM6 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM6 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM7LPEN</name>
<description>TIM7 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM7 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM7 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM12LPEN</name>
<description>TIM12 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM12 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM12 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM13LPEN</name>
<description>TIM13 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM13 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM13 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM14LPEN</name>
<description>TIM14 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM14 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM14 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM1LPEN</name>
<description>LPTIM1 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM1 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM1 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI2LPEN</name>
<description>SPI2 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI2 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI2 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI3LPEN</name>
<description>SPI3 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI3 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI3 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPDIFRXLPEN</name>
<description>SPDIFRX peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SPDIFRX are: the kernel clock selected by SPDIFRXSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPDIFRX peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPDIFRX peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART2LPEN</name>
<description>USART2 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART2 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART2 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART3LPEN</name>
<description>USART3 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART3 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART3 peripheral clocks enabled during CSleep mode (default after reset):</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART4LPEN</name>
<description>UART4 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART4 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART4 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART5LPEN</name>
<description>UART5 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the UART5 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART5 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART5 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1LPEN</name>
<description>I2C1 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the I2C1 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C1 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C1 peripheral clocks enabled during CSleep mode (default after reset):</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C2LPEN</name>
<description>I2C2 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the I2C2 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C2 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C2 peripheral clocks enabled during CSleep mode (default after reset):</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C3LPEN</name>
<description>I2C3 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the I2C3 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C3 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C3 peripheral clocks enabled during CSleep mode (default after reset):</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CECLPEN</name>
<description>HDMI-CEC peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the HDMI-CEC are the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>HDMI-CEC peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>HDMI-CEC peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC1LPEN</name>
<description>DAC1 (containing two converters) peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC1 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC1 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART7LPEN</name>
<description>UART7 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the UART7 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART7 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART7 peripheral clocks enabled during CSleep mode (default after reset):</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART8LPEN</name>
<description>UART8 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the UART8 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART8 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART8 peripheral clocks enabled during CSleep mode (default after reset):</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB1HLPENR</name>
<displayName>RCC_APB1HLPENR</displayName>
<addressOffset>0x174</addressOffset>
<size>0x20</size>
<resetValue>0x00000136</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRSLPEN</name>
<description>clock recovery system peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>CRS peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>CRS peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWPMILPEN</name>
<description>SWPMI peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SWPMI are the kernel clock selected by SWPMISEL and provided to swpmi_ker_ck input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SWPMI peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SWPMI peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPAMPLPEN</name>
<description>OPAMP peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>OPAMP peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>OPAMP peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIOSLPEN</name>
<description>MDIOS peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>MDIOS peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>MDIOS peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDCANLPEN</name>
<description>FDCAN peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the FDCAN are: the kernel clock selected by FDCANSEL and provided to fdcan_clk input, and the rcc_pclk1 bus interface clock.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>FDCAN peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FDCAN peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB2LPENR</name>
<displayName>RCC_APB2LPENR</displayName>
<addressOffset>0x178</addressOffset>
<size>0x20</size>
<resetValue>0x40D730F3</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIM1LPEN</name>
<description>TIM1 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM1 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM1 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM8LPEN</name>
<description>TIM8 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM8 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM8 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART1LPEN</name>
<description>USART1 peripheral clock enable during CSleep mode
Set and reset by software.
The peripheral clocks of the USART1 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck inputs, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART1 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART1 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART6LPEN</name>
<description>USART6 peripheral clock enable during CSleep mode
Set and reset by software.
The peripheral clocks of the USART6 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART6 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART6 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART9LPEN</name>
<description>UART9 peripheral clock enable during CSleep mode
Set and reset by software.
The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>UART9 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>UART9 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART10LPEN</name>
<description>USART10 peripheral clock enable during CSleep mode
Set and reset by software.
The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>USART10 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>USART10 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1LPEN</name>
<description>SPI1 peripheral clock enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI1 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI1 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI4LPEN</name>
<description>SPI4 peripheral clock enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI4 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI4 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM15LPEN</name>
<description>TIM15 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM15 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM15 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM16LPEN</name>
<description>TIM16 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM16 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM16 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIM17LPEN</name>
<description>TIM17 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TIM17 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TIM17 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI5LPEN</name>
<description>SPI5 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI5 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI5 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI1LPEN</name>
<description>SAI1 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SAI1 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SAI1 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAI2LPEN</name>
<description>SAI2 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SAI2 are the kernel clock selected by SAI23EL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SAI2 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SAI2 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM1LPEN</name>
<description>DFSDM1 peripheral clocks enable during CSleep mode
Set and reset by software.
DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively, and the rcc_pclk2 bus interface clock.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM1 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM1 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RCC_APB4LPENR</name>
<displayName>RCC_APB4LPENR</displayName>
<addressOffset>0x17c</addressOffset>
<size>0x20</size>
<resetValue>0x0C01E6AA</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SYSCFGLPEN</name>
<description>SYSCFG peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SYSCFG peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SYSCFG peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPUART1LPEN</name>
<description>LPUART1 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPUART1 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPUART1 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI6LPEN</name>
<description>SPI6 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the SPI6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>SPI6 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SPI6 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C4LPEN</name>
<description>I2C4 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the I2C4 are the kernel clock selected by I2C4SEL and provided to i2C_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>I2C4 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>I2C4 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM2LPEN</name>
<description>LPTIM2 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM2 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM2 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTIM3LPEN</name>
<description>LPTIM3 peripheral clocks enable during CSleep mode
Set and reset by software.
The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>LPTIM3 peripheral clocks disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>LPTIM3 peripheral clocks enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC2LPEN</name>
<description>DAC2 (containing one converter) peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DAC2 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DAC2 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP12LPEN</name>
<description>COMP1 and 2 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>COMP1 and 2 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>COMP1 and 2 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFLPEN</name>
<description>VREF peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>VREF peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>VREF peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCAPBLPEN</name>
<description>RTC APB clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The register clock interface of the RTC (APB) is disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The register clock interface of the RTC (APB) is enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTSLPEN</name>
<description>temperature sensor peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DTS peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DTS peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DFSDM2LPEN</name>
<description>DFSDM2 peripheral clock enable during CSleep mode
Set and reset by software.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DFSDM2 peripheral clock disabled during CSleep mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DFSDM2 peripheral clock enabled during CSleep mode (default after reset)</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RNG</name>
<description>RNG</description>
<groupName>RNG</groupName>
<baseAddress>0x48021800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>QUADSPI</name>
<description>QuadSPI global interrupt</description>
<value>92</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>RNG control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RNGEN</name>
<description>Random number generator
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE</name>
<description>Interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CED</name>
<description>Clock error detection Note: The clock
error detection can be used only when ck_rc48 or
ck_pll1_q (ck_pll1_q = 48MHz) source is selected
otherwise, CED bit must be equal to 1. The clock
error detection cannot be enabled nor disabled on the
fly when RNG peripheral is enabled, to enable or
disable CED the RNG must be disabled.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>RNG status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DRDY</name>
<description>Data ready Note: If IE=1 in RNG_CR, an
interrupt is generated when DRDY=1. It can rise when
the peripheral is disabled. When the output buffer
becomes empty (after reading RNG_DR), this bit
returns to 0 until a new random value is
generated.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CECS</name>
<description>Clock error current status Note: This
bit is meaningless if CED (Clock error detection) bit
in RNG_CR is equal to 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SECS</name>
<description>Seed error current status ** More than
64 consecutive bits at the same value (0 or 1) **
More than 32 consecutive alternances of 0 and 1
(0101010101...01)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CEIS</name>
<description>Clock error interrupt status This bit is
set at the same time as CECS. It is cleared by
writing it to 0. An interrupt is pending if IE = 1 in
the RNG_CR register. Note: This bit is meaningless if
CED (Clock error detection) bit in RNG_CR is equal to
1.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SEIS</name>
<description>Seed error interrupt status This bit is
set at the same time as SECS. It is cleared by
writing it to 0. ** More than 64 consecutive bits at
the same value (0 or 1) ** More than 32 consecutive
alternances of 0 and 1 (0101010101...01) An interrupt
is pending if IE = 1 in the RNG_CR
register.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>The RNG_DR register is a read-only register
that delivers a 32-bit random value when read. The
content of this register is valid when DRDY= 1, even if
RNGEN=0.</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RNDATA</name>
<description>Random data 32-bit random data which are
valid when DRDY=1.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC</name>
<description>RTC</description>
<groupName>RTC</groupName>
<baseAddress>0x58004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC_TAMP_STAMP_CSS_LSE</name>
<description>RTC tamper, timestamp/CSS LSE</description>
<value>2</value>
</interrupt>
<interrupt>
<name>RTC_WKUP</name>
<description>RTC Wakeup interrupt through the EXTI linet</description>
<value>3</value>
</interrupt>
<interrupt>
<name>RTC_ALARM</name>
<description>RTC alarms (A and B) through EXTI Line interrupts)</description>
<value>41</value>
</interrupt>
<registers>
<register>
<name>RTC_TR</name>
<displayName>RTC_TR</displayName>
<description>RTC time register </description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AM or 24-hour format</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PM</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RTC_DR</name>
<displayName>RTC_DR</displayName>
<description>RTC date register </description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00002101</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DU</name>
<description>Date units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MU</name>
<description>Month units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MT</name>
<description>Month tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDU</name>
<description>Week day units
...</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>forbidden</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Monday</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x7</name>
<description>Sunday</description>
<value>0x7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>YU</name>
<description>Year units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>YT</name>
<description>Year tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RTC_SSR</name>
<displayName>RTC_SSR</displayName>
<description>RTC sub second register </description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SS</name>
<description>Sub second value
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below:
Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1)
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_ICSR</name>
<displayName>RTC_ICSR</displayName>
<description>RTC initialization control and status register </description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<resetValue>0x00000007</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALRAWF</name>
<description>Alarm A write flag
This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm A update not allowed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Alarm A update allowed</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALRBWF</name>
<description>Alarm B write flag
This bit is set by hardware when alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm B update not allowed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Alarm B update allowed</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUTWF</name>
<description>Wakeup timer write flag
This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Wakeup timer configuration update not allowed except in initialization mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Wakeup timer configuration update allowed</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHPF</name>
<description>Shift operation pending
This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No shift operation is pending</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A shift operation is pending</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITS</name>
<description>Initialization status flag
This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Calendar has not been initialized</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Calendar has been initialized</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSF</name>
<description>Registers synchronization flag
This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software.
It is cleared either by software or by hardware in initialization mode.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Calendar shadow registers not yet synchronized</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Calendar shadow registers synchronized</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITF</name>
<description>Initialization flag
When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Calendar registers update is not allowed</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Calendar registers update is allowed</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INIT</name>
<description>Initialization mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Free running mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RECALPF</name>
<description>Recalibration pending Flag
The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to .</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_PRER</name>
<displayName>RTC_PRER</displayName>
<description>RTC prescaler register </description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x007F00FF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PREDIV_S</name>
<description>Synchronous prescaler factor
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PREDIV_A</name>
<description>Asynchronous prescaler factor
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RTC_WUTR</name>
<displayName>RTC_WUTR</displayName>
<description>RTC wakeup timer register </description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WUT</name>
<description>Wakeup auto-reload value bits
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register.
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer.
The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RTC_CR</name>
<displayName>RTC_CR</displayName>
<description>RTC control register </description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WUCKSEL</name>
<description>ck_wut wakeup clock selection
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RTC/16 clock is selected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RTC/8 clock is selected</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>RTC/4 clock is selected</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>RTC/2 clock is selected</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSEDGE</name>
<description>Timestamp event active edge
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RTC_TS input rising edge generates a timestamp event</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RTC_TS input falling edge generates a timestamp event</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REFCKON</name>
<description>RTC_REFIN reference clock detection enable (50 or 60 Hz)
Note: PREDIV_S must be 0x00FF.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RTC_REFIN detection disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RTC_REFIN detection enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYPSHAD</name>
<description>Bypass the shadow registers
Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMT</name>
<description>Hour format</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>24 hour/day format</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>AM/PM hour format</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALRAE</name>
<description>Alarm A enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm A disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Alarm A enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALRBE</name>
<description>Alarm B enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm B disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Alarm B enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUTE</name>
<description>Wakeup timer enable
Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Wakeup timer disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Wakeup timer enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSE</name>
<description>timestamp enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>timestamp disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>timestamp enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALRAIE</name>
<description>Alarm A interrupt enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm A interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Alarm A interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALRBIE</name>
<description>Alarm B interrupt enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm B interrupt disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Alarm B interrupt enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUTIE</name>
<description>Wakeup timer interrupt enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Wakeup timer interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Wakeup timer interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSIE</name>
<description>Timestamp interrupt enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Timestamp interrupt disable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Timestamp interrupt enable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADD1H</name>
<description>Add 1 hour (summer time change)
When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Adds 1 hour to the current time. This can be used for summer time change</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SUB1H</name>
<description>Subtract 1 hour (winter time change)
When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0.
Setting this bit has no effect when current hour is 0.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Subtracts 1 hour to the current time. This can be used for winter time change.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BKP</name>
<description>Backup
This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COSEL</name>
<description>Calibration output selection
When COE = 1, this bit selects which signal is output on CALIB.
These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Calibration output is 512 Hz </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Calibration output is 1 Hz </description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL</name>
<description>Output polarity
This bit is used to configure the polarity of TAMPALRM output.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSEL</name>
<description>Output selection
These bits are used to select the flag to be routed to TAMPALRM output.</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Alarm A output enabled</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Alarm B output enabled</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Wakeup output enabled</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COE</name>
<description>Calibration output enable
This bit enables the CALIB output</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Calibration output disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Calibration output enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITSE</name>
<description>timestamp on internal event enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>internal event timestamp disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>internal event timestamp enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAMPTS</name>
<description>Activate timestamp on tamper detection event
TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Tamper detection event does not cause a RTC timestamp to be saved</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Save RTC timestamp on tamper detection event</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAMPOE</name>
<description>Tamper detection output enable on TAMPALRM</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>The tamper flag is not routed on TAMPALRM</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAMPALRM_PU</name>
<description>TAMPALRM pull-up enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No pull-up is applied on TAMPALRM output</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>A pull-up is applied on TAMPALRM output</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TAMPALRM_TYPE</name>
<description>TAMPALRM output type</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>TAMPALRM is push-pull output</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>TAMPALRM is open-drain output</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUT2EN</name>
<description>RTC_OUT2 output enable
Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows:
OUT2EN = 0: RTC output 2 disable
If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1
If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1
OUT2EN = 1: RTC output 2 enable
If (OSEL ≠ 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2
If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2
If (OSEL≠ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RTC_WPR</name>
<displayName>RTC_WPR</displayName>
<description>RTC write protection register </description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to for a description of how to unlock RTC register write protection.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_CALR</name>
<displayName>RTC_CALR</displayName>
<description>RTC calibration register </description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CALM</name>
<description>Calibration minus
The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See .</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CALW16</name>
<description>Use a 16-second calibration cycle period
When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1.
Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CALW8</name>
<description>Use an 8-second calibration cycle period
When CALW8 is set to 1, the 8-second calibration cycle period is selected.
Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CALP</name>
<description>Increase frequency of RTC by 488.5 ppm
This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) - CALM.
Refer to .</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No RTCCLK pulses are added.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5 ppm).</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RTC_SHIFTR</name>
<displayName>RTC_SHIFTR</displayName>
<description>RTC shift control register </description>
<addressOffset>0x2c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SUBFS</name>
<description>Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR).
The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))).
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<access>write-only</access>
</field>
<field>
<name>ADD1S</name>
<description>Add one second
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR).
This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No effect</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Add one second to the clock/calendar</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RTC_TSTR</name>
<displayName>RTC_TSTR</displayName>
<description>RTC timestamp time register </description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SU</name>
<description>Second units in BCD format.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format.</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format.</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format.</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AM or 24-hour format</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PM</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RTC_TSDR</name>
<displayName>RTC_TSDR</displayName>
<description>RTC timestamp date register </description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DU</name>
<description>Date units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MU</name>
<description>Month units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MT</name>
<description>Month tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WDU</name>
<description>Week day units</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_TSSSR</name>
<displayName>RTC_TSSSR</displayName>
<description>RTC timestamp sub second register </description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SS</name>
<description>Sub second value
SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_ALRMAR</name>
<displayName>RTC_ALRMAR</displayName>
<description>RTC alarm A register </description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SU</name>
<description>Second units in BCD format.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format.</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSK1</name>
<description>Alarm A seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm A set if the seconds match</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Seconds don't care in alarm A comparison</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSK2</name>
<description>Alarm A minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm A set if the minutes match</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Minutes don't care in alarm A comparison</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AM or 24-hour format</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PM</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSK3</name>
<description>Alarm A hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm A set if the hours match</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Hours don't care in alarm A comparison</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DU</name>
<description>Date units or day in BCD format</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDSEL</name>
<description>Week day selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DU[3:0] represents the date units</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DU[3:0] represents the week day. DT[1:0] is don't care.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSK4</name>
<description>Alarm A date mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm A set if the date/day match</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Date/day don't care in alarm A comparison</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RTC_ALRMASSR</name>
<displayName>RTC_ALRMASSR</displayName>
<description>RTC alarm A sub second register </description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SS</name>
<description>Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MASKSS</name>
<description>Mask the most-significant bits starting at this bit
2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared.
3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared.
...
12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared.
13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared.
14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared.
15: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SS[14:1] are don't care in alarm A comparison. Only SS[0] is compared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RTC_ALRMBR</name>
<displayName>RTC_ALRMBR</displayName>
<description>RTC alarm B register </description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSK1</name>
<description>Alarm B seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm B set if the seconds match</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Seconds don't care in alarm B comparison</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSK2</name>
<description>Alarm B minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm B set if the minutes match</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Minutes don't care in alarm B comparison</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>AM or 24-hour format</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>PM</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSK3</name>
<description>Alarm B hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm B set if the hours match</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Hours don't care in alarm B comparison</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DU</name>
<description>Date units or day in BCD format</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDSEL</name>
<description>Week day selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>DU[3:0] represents the date units</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>DU[3:0] represents the week day. DT[1:0] is don't care.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSK4</name>
<description>Alarm B date mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Alarm B set if the date and day match</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Date and day don't care in alarm B comparison</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RTC_ALRMBSSR</name>
<displayName>RTC_ALRMBSSR</displayName>
<description>RTC alarm B sub second register </description>
<addressOffset>0x4c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SS</name>
<description>Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MASKSS</name>
<description>Mask the most-significant bits starting at this bit
...
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>No comparison on sub seconds for alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>SS[14:1] are don't care in alarm B comparison. Only SS[0] is compared.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>SS[14:2] are don't care in alarm B comparison. Only SS[1:0] are compared.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>SS[14:3] are don't care in alarm B comparison. Only SS[2:0] are compared.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xC</name>
<description>SS[14:12] are don't care in alarm B comparison. SS[11:0] are compared.</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xD</name>
<description>SS[14:13] are don't care in alarm B comparison. SS[12:0] are compared.</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xE</name>
<description>SS[14] is don't care in alarm B comparison. SS[13:0] are compared.</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0xF</name>
<description>All 15 SS bits are compared and must match to activate alarm.</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RTC_SR</name>
<displayName>RTC_SR</displayName>
<description>RTC status register </description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALRAF</name>
<description>Alarm A flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ALRBF</name>
<description>Alarm B flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm B register (RTC_ALRMBR).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WUTF</name>
<description>Wakeup timer flag
This flag is set by hardware when the wakeup auto-reload counter reaches 0.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TSF</name>
<description>Timestamp flag
This flag is set by hardware when a timestamp event occurs.
If ITSF flag is set, TSF must be cleared together with ITSF.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TSOVF</name>
<description>Timestamp overflow flag
This flag is set by hardware when a timestamp event occurs while TSF is already set.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ITSF</name>
<description>Internal timestamp flag
This flag is set by hardware when a timestamp on the internal event occurs.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_MISR</name>
<displayName>RTC_MISR</displayName>
<description>RTC masked interrupt status register </description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALRAMF</name>
<description>Alarm A masked flag
This flag is set by hardware when the alarm A interrupt occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ALRBMF</name>
<description>Alarm B masked flag
This flag is set by hardware when the alarm B interrupt occurs.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WUTMF</name>
<description>Wakeup timer masked flag
This flag is set by hardware when the wakeup timer interrupt occurs.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TSMF</name>
<description>Timestamp masked flag
This flag is set by hardware when a timestamp interrupt occurs.
If ITSF flag is set, TSF must be cleared together with ITSF.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TSOVMF</name>
<description>Timestamp overflow masked flag
This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ITSMF</name>
<description>Internal timestamp masked flag
This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_SCR</name>
<displayName>RTC_SCR</displayName>
<description>RTC status clear register </description>
<addressOffset>0x5c</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CALRAF</name>
<description>Clear alarm A flag
Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CALRBF</name>
<description>Clear alarm B flag
Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CWUTF</name>
<description>Clear wakeup timer flag
Writing 1 in this bit clears the WUTF bit in the RTC_SR register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CTSF</name>
<description>Clear timestamp flag
Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.
If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CTSOVF</name>
<description>Clear timestamp overflow flag
Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CITSF</name>
<description>Clear internal timestamp flag
Writing 1 in this bit clears the ITSF bit in the RTC_SR register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_CFGR</name>
<displayName>RTC_CFGR</displayName>
<description>RTC configuration register </description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OUT2_RMP</name>
<description>RTC_OUT2 mapping</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>RTC_OUT2 is mapped on PB2</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>RTC_OUT2 is mapped on PI8</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SAI1</name>
<description>SAI</description>
<groupName>SAI</groupName>
<baseAddress>0x40015800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SAI_GCR</name>
<displayName>SAI_GCR</displayName>
<description>Global configuration register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOUT</name>
<description>Synchronization outputs These bits are
set and cleared by software.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCIN</name>
<description>Synchronization inputs</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_ACR1</name>
<displayName>SAI_ACR1</displayName>
<description>Configuration register 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>MODE</name>
<description>SAIx audio block mode
immediately</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRTCFG</name>
<description>Protocol configuration. These bits are
set and cleared by software. These bits have to be
configured when the audio block is
disabled.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DS</name>
<description>Data size. These bits are set and
cleared by software. These bits are ignored when the
SPDIF protocols are selected (bit PRTCFG[1:0]),
because the frame and the data size are fixed in such
case. When the companding mode is selected through
COMP[1:0] bits, DS[1:0] are ignored since the data
size is fixed to 8 bits by the algorithm. These bits
must be configured when the audio block is
disabled.</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>Least significant bit first. This bit is
set and cleared by software. It must be configured
when the audio block is disabled. This bit has no
meaning in AC97 audio protocol since AC97 data are
always transferred with the MSB first. This bit has
no meaning in SPDIF audio protocol since in SPDIF
data are always transferred with LSB
first.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKSTR</name>
<description>Clock strobing edge. This bit is set and
cleared by software. It must be configured when the
audio block is disabled. This bit has no meaning in
SPDIF audio protocol.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCEN</name>
<description>Synchronization enable. These bits are
set and cleared by software. They must be configured
when the audio sub-block is disabled. Note: The audio
sub-block should be configured as asynchronous when
SPDIF mode is enabled.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MONO</name>
<description>Mono mode. This bit is set and cleared
by software. It is meaningful only when the number of
slots is equal to 2. When the mono mode is selected,
slot 0 data are duplicated on slot 1 when the audio
block operates as a transmitter. In reception mode,
the slot1 is discarded and only the data received
from slot 0 are stored. Refer to Section: Mono/stereo
mode for more details.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTDRIV</name>
<description>Output drive. This bit is set and
cleared by software. Note: This bit has to be set
before enabling the audio block and after the audio
block configuration.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAIXEN</name>
<description>Audio block enable where x is A or B.
This bit is set by software. To switch off the audio
block, the application software must program this bit
to 0 and poll the bit till it reads back 0, meaning
that the block is completely disabled. Before setting
this bit to 1, check that it is set to 0, otherwise
the enable command will not be taken into account.
This bit allows to control the state of SAIx audio
block. If it is disabled when an audio frame transfer
is ongoing, the ongoing transfer completes and the
cell is fully disabled at the end of this audio frame
transfer. Note: When SAIx block is configured in
master mode, the clock must be present on the input
of SAIx before setting SAIXEN bit.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable. This bit is set and cleared
by software. Note: Since the audio block defaults to
operate as a transmitter after reset, the MODE[1:0]
bits must be configured before setting DMAEN to avoid
a DMA request in receiver mode.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOMCK</name>
<description>No divider</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCKDIV</name>
<description>Master clock divider. These bits are set
and cleared by software. These bits are meaningless
when the audio block operates in slave mode. They
have to be configured when the audio block is
disabled. Others: the master clock frequency is
calculated accordingly to the following
formula:</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OSR</name>
<description>Oversampling ratio for master
clock</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_ACR2</name>
<displayName>SAI_ACR2</displayName>
<description>Configuration register 2</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FTH</name>
<description>FIFO threshold. This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FFLUSH</name>
<description>FIFO flush. This bit is set by software.
It is always read as 0. This bit should be configured
when the SAI is disabled.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TRIS</name>
<description>Tristate management on data line. This
bit is set and cleared by software. It is meaningful
only if the audio block is configured as a
transmitter. This bit is not used when the audio
block is configured in SPDIF mode. It should be
configured when SAI is disabled. Refer to Section:
Output data line management on an inactive slot for
more details.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MUTE</name>
<description>Mute. This bit is set and cleared by
software. It is meaningful only when the audio block
operates as a transmitter. The MUTE value is linked
to value of MUTEVAL if the number of slots is lower
or equal to 2, or equal to 0 if it is greater than 2.
Refer to Section: Mute mode for more details. Note:
This bit is meaningless and should not be used for
SPDIF audio blocks.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MUTEVAL</name>
<description>Mute value. This bit is set and cleared
by software.It must be written before enabling the
audio block: SAIXEN. This bit is meaningful only when
the audio block operates as a transmitter, the number
of slots is lower or equal to 2 and the MUTE bit is
set. If more slots are declared, the bit value sent
during the transmission in mute mode is equal to 0,
whatever the value of MUTEVAL. if the number of slot
is lower or equal to 2 and MUTEVAL = 1, the MUTE
value transmitted for each slot is the one sent
during the previous frame. Refer to Section: Mute
mode for more details. Note: This bit is meaningless
and should not be used for SPDIF audio
blocks.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MUTECNT</name>
<description>Mute counter. These bits are set and
cleared by software. They are used only in reception
mode. The value set in these bits is compared to the
number of consecutive mute frames detected in
reception. When the number of mute frames is equal to
this value, the flag MUTEDET will be set and an
interrupt will be generated if bit MUTEDETIE is set.
Refer to Section: Mute mode for more
details.</description>
<bitOffset>7</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CPL</name>
<description>Complement bit. This bit is set and
cleared by software. It defines the type of
complement to be used for companding mode Note: This
bit has effect only when the companding mode is -Law
algorithm or A-Law algorithm.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP</name>
<description>Companding mode. These bits are set and
cleared by software. The -Law and the A-Law log are a
part of the CCITT G.711 recommendation, the type of
complement that will be used depends on CPL bit. The
data expansion or data compression are determined by
the state of bit MODE[0]. The data compression is
applied if the audio block is configured as a
transmitter. The data expansion is automatically
applied when the audio block is configured as a
receiver. Refer to Section: Companding mode for more
details. Note: Companding mode is applicable only
when TDM is selected.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SAI_AFRCR</name>
<displayName>SAI_AFRCR</displayName>
<description>This register has no meaning in AC97 and
SPDIF audio protocol</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>FRL</name>
<description>Frame length. These bits are set and
cleared by software. They define the audio frame
length expressed in number of SCK clock cycles: the
number of bits in the frame is equal to FRL[7:0] + 1.
The minimum number of bits to transfer in an audio
frame must be equal to 8, otherwise the audio block
will behaves in an unexpected way. This is the case
when the data size is 8 bits and only one slot 0 is
defined in NBSLOT[4:0] of SAI_xSLOTR register
(NBSLOT[3:0] = 0000). In master mode, if the master
clock (available on MCLK_x pin) is used, the frame
length should be aligned with a number equal to a
power of 2, ranging from 8 to 256. When the master
clock is not used (NODIV = 1), it is recommended to
program the frame length to an value ranging from 8
to 256. These bits are meaningless and are not used
in AC97 or SPDIF audio block
configuration.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSALL</name>
<description>Frame synchronization active level
length. These bits are set and cleared by software.
They specify the length in number of bit clock (SCK)
+ 1 (FSALL[6:0] + 1) of the active level of the FS
signal in the audio frame These bits are meaningless
and are not used in AC97 or SPDIF audio block
configuration. They must be configured when the audio
block is disabled.</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSDEF</name>
<description>Frame synchronization definition. This
bit is set and cleared by software. When the bit is
set, the number of slots defined in the SAI_xSLOTR
register has to be even. It means that half of this
number of slots will be dedicated to the left channel
and the other slots for the right channel (e.g: this
bit has to be set for I2S or MSB/LSB-justified
protocols...). This bit is meaningless and is not
used in AC97 or SPDIF audio block configuration. It
must be configured when the audio block is
disabled.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FSPOL</name>
<description>Frame synchronization polarity. This bit
is set and cleared by software. It is used to
configure the level of the start of frame on the FS
signal. It is meaningless and is not used in AC97 or
SPDIF audio block configuration. This bit must be
configured when the audio block is
disabled.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSOFF</name>
<description>Frame synchronization offset. This bit
is set and cleared by software. It is meaningless and
is not used in AC97 or SPDIF audio block
configuration. This bit must be configured when the
audio block is disabled.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SAI_ASLOTR</name>
<displayName>SAI_ASLOTR</displayName>
<description>This register has no meaning in AC97 and
SPDIF audio protocol</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FBOFF</name>
<description>First bit offset These bits are set and
cleared by software. The value set in this bitfield
defines the position of the first data transfer bit
in the slot. It represents an offset value. In
transmission mode, the bits outside the data field
are forced to 0. In reception mode, the extra
received bits are discarded. These bits must be set
when the audio block is disabled. They are ignored in
AC97 or SPDIF mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SLOTSZ</name>
<description>Slot size This bits is set and cleared
by software. The slot size must be higher or equal to
the data size. If this condition is not respected,
the behavior of the SAI will be undetermined. Refer
to Section: Output data line management on an
inactive slot for information on how to drive SD
line. These bits must be set when the audio block is
disabled. They are ignored in AC97 or SPDIF
mode.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBSLOT</name>
<description>Number of slots in an audio frame. These
bits are set and cleared by software. The value set
in this bitfield represents the number of slots + 1
in the audio frame (including the number of inactive
slots). The maximum number of slots is 16. The number
of slots should be even if FSDEF bit in the SAI_xFRCR
register is set. The number of slots must be
configured when the audio block is disabled. They are
ignored in AC97 or SPDIF mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SLOTEN</name>
<description>Slot enable. These bits are set and
cleared by software. Each SLOTEN bit corresponds to a
slot position from 0 to 15 (maximum 16 slots). The
slot must be enabled when the audio block is
disabled. They are ignored in AC97 or SPDIF
mode.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_AIM</name>
<displayName>SAI_AIM</displayName>
<description>Interrupt mask register 2</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVRUDRIE</name>
<description>Overrun/underrun interrupt enable. This
bit is set and cleared by software. When this bit is
set, an interrupt is generated if the OVRUDR bit in
the SAI_xSR register is set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDETIE</name>
<description>Mute detection interrupt enable. This
bit is set and cleared by software. When this bit is
set, an interrupt is generated if the MUTEDET bit in
the SAI_xSR register is set. This bit has a meaning
only if the audio block is configured in receiver
mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFGIE</name>
<description>Wrong clock configuration interrupt
enable. This bit is set and cleared by software. This
bit is taken into account only if the audio block is
configured as a master (MODE[1] = 0) and NODIV = 0.
It generates an interrupt if the WCKCFG flag in the
SAI_xSR register is set. Note: This bit is used only
in TDM mode and is meaningless in other
modes.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQIE</name>
<description>FIFO request interrupt enable. This bit
is set and cleared by software. When this bit is set,
an interrupt is generated if the FREQ bit in the
SAI_xSR register is set. Since the audio block
defaults to operate as a transmitter after reset, the
MODE bit must be configured before setting FREQIE to
avoid a parasitic interruption in receiver
mode,</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDYIE</name>
<description>Codec not ready interrupt enable (AC97).
This bit is set and cleared by software. When the
interrupt is enabled, the audio block detects in the
slot 0 (tag0) of the AC97 frame if the Codec
connected to this line is ready or not. If it is not
ready, the CNRDY flag in the SAI_xSR register is set
and an interruption i generated. This bit has a
meaning only if the AC97 mode is selected through
PRTCFG[1:0] bits and the audio block is operates as a
receiver.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDETIE</name>
<description>Anticipated frame synchronization
detection interrupt enable. This bit is set and
cleared by software. When this bit is set, an
interrupt will be generated if the AFSDET bit in the
SAI_xSR register is set. This bit is meaningless in
AC97, SPDIF mode or when the audio block operates as
a master.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LFSDETIE</name>
<description>Late frame synchronization detection
interrupt enable. This bit is set and cleared by
software. When this bit is set, an interrupt will be
generated if the LFSDET bit is set in the SAI_xSR
register. This bit is meaningless in AC97, SPDIF mode
or when the audio block operates as a
master.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_ASR</name>
<displayName>SAI_ASR</displayName>
<description>Status register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000008</resetValue>
<fields>
<field>
<name>OVRUDR</name>
<description>Overrun / underrun. This bit is read
only. The overrun and underrun conditions can occur
only when the audio block is configured as a receiver
and a transmitter, respectively. It can generate an
interrupt if OVRUDRIE bit is set in SAI_xIM register.
This flag is cleared when the software sets COVRUDR
bit in SAI_xCLRFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection. This bit is read only.
This flag is set if consecutive 0 values are received
in each slot of a given audio frame and for a
consecutive number of audio frames (set in the
MUTECNT bit in the SAI_xCR2 register). It can
generate an interrupt if MUTEDETIE bit is set in
SAI_xIM register. This flag is cleared when the
software sets bit CMUTEDET in the SAI_xCLRFR
register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration flag. This bit
is read only. This bit is used only when the audio
block operates in master mode (MODE[1] = 0) and NODIV
= 0. It can generate an interrupt if WCKCFGIE bit is
set in SAI_xIM register. This flag is cleared when
the software sets CWCKCFG bit in SAI_xCLRFR
register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQ</name>
<description>FIFO request. This bit is read only. The
request depends on the audio block configuration: If
the block is configured in transmission mode, the
FIFO request is related to a write request operation
in the SAI_xDR. If the block configured in reception,
the FIFO request related to a read request operation
from the SAI_xDR. This flag can generate an interrupt
if FREQIE bit is set in SAI_xIM
register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Codec not ready. This bit is read only.
This bit is used only when the AC97 audio protocol is
selected in the SAI_xCR1 register and configured in
receiver mode. It can generate an interrupt if
CNRDYIE bit is set in SAI_xIM register. This flag is
cleared when the software sets CCNRDY bit in
SAI_xCLRFR register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDET</name>
<description>Anticipated frame synchronization
detection. This bit is read only. This flag can be
set only if the audio block is configured in slave
mode. It is not used in AC97or SPDIF mode. It can
generate an interrupt if AFSDETIE bit is set in
SAI_xIM register. This flag is cleared when the
software sets CAFSDET bit in SAI_xCLRFR
register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LFSDET</name>
<description>Late frame synchronization detection.
This bit is read only. This flag can be set only if
the audio block is configured in slave mode. It is
not used in AC97 or SPDIF mode. It can generate an
interrupt if LFSDETIE bit is set in the SAI_xIM
register. This flag is cleared when the software sets
bit CLFSDET in SAI_xCLRFR register</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLVL</name>
<description>FIFO level threshold. This bit is read
only. The FIFO level threshold flag is managed only
by hardware and its setting depends on SAI block
configuration (transmitter or receiver mode). If the
SAI block is configured as transmitter: If SAI block
is configured as receiver:</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_ACLRFR</name>
<displayName>SAI_ACLRFR</displayName>
<description>Clear flag register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COVRUDR</name>
<description>Clear overrun / underrun. This bit is
write only. Programming this bit to 1 clears the
OVRUDR flag in the SAI_xSR register. Reading this bit
always returns the value 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMUTEDET</name>
<description>Mute detection flag. This bit is write
only. Programming this bit to 1 clears the MUTEDET
flag in the SAI_xSR register. Reading this bit always
returns the value 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWCKCFG</name>
<description>Clear wrong clock configuration flag.
This bit is write only. Programming this bit to 1
clears the WCKCFG flag in the SAI_xSR register. This
bit is used only when the audio block is set as
master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1
register. Reading this bit always returns the value
0.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCNRDY</name>
<description>Clear Codec not ready flag. This bit is
write only. Programming this bit to 1 clears the
CNRDY flag in the SAI_xSR register. This bit is used
only when the AC97 audio protocol is selected in the
SAI_xCR1 register. Reading this bit always returns
the value 0.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAFSDET</name>
<description>Clear anticipated frame synchronization
detection flag. This bit is write only. Programming
this bit to 1 clears the AFSDET flag in the SAI_xSR
register. It is not used in AC97or SPDIF mode.
Reading this bit always returns the value
0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLFSDET</name>
<description>Clear late frame synchronization
detection flag. This bit is write only. Programming
this bit to 1 clears the LFSDET flag in the SAI_xSR
register. This bit is not used in AC97or SPDIF mode
Reading this bit always returns the value
0.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_ADR</name>
<displayName>SAI_ADR</displayName>
<description>Data register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data A write to this register loads the
FIFO provided the FIFO is not full. A read from this
register empties the FIFO if the FIFO is not
empty.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_BCR1</name>
<displayName>SAI_BCR1</displayName>
<description>Configuration register 1</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>MODE</name>
<description>SAIx audio block mode
immediately</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRTCFG</name>
<description>Protocol configuration. These bits are
set and cleared by software. These bits have to be
configured when the audio block is
disabled.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DS</name>
<description>Data size. These bits are set and
cleared by software. These bits are ignored when the
SPDIF protocols are selected (bit PRTCFG[1:0]),
because the frame and the data size are fixed in such
case. When the companding mode is selected through
COMP[1:0] bits, DS[1:0] are ignored since the data
size is fixed to 8 bits by the algorithm. These bits
must be configured when the audio block is
disabled.</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>Least significant bit first. This bit is
set and cleared by software. It must be configured
when the audio block is disabled. This bit has no
meaning in AC97 audio protocol since AC97 data are
always transferred with the MSB first. This bit has
no meaning in SPDIF audio protocol since in SPDIF
data are always transferred with LSB
first.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKSTR</name>
<description>Clock strobing edge. This bit is set and
cleared by software. It must be configured when the
audio block is disabled. This bit has no meaning in
SPDIF audio protocol.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCEN</name>
<description>Synchronization enable. These bits are
set and cleared by software. They must be configured
when the audio sub-block is disabled. Note: The audio
sub-block should be configured as asynchronous when
SPDIF mode is enabled.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MONO</name>
<description>Mono mode. This bit is set and cleared
by software. It is meaningful only when the number of
slots is equal to 2. When the mono mode is selected,
slot 0 data are duplicated on slot 1 when the audio
block operates as a transmitter. In reception mode,
the slot1 is discarded and only the data received
from slot 0 are stored. Refer to Section: Mono/stereo
mode for more details.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTDRIV</name>
<description>Output drive. This bit is set and
cleared by software. Note: This bit has to be set
before enabling the audio block and after the audio
block configuration.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAIXEN</name>
<description>Audio block enable where x is A or B.
This bit is set by software. To switch off the audio
block, the application software must program this bit
to 0 and poll the bit till it reads back 0, meaning
that the block is completely disabled. Before setting
this bit to 1, check that it is set to 0, otherwise
the enable command will not be taken into account.
This bit allows to control the state of SAIx audio
block. If it is disabled when an audio frame transfer
is ongoing, the ongoing transfer completes and the
cell is fully disabled at the end of this audio frame
transfer. Note: When SAIx block is configured in
master mode, the clock must be present on the input
of SAIx before setting SAIXEN bit.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable. This bit is set and cleared
by software. Note: Since the audio block defaults to
operate as a transmitter after reset, the MODE[1:0]
bits must be configured before setting DMAEN to avoid
a DMA request in receiver mode.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOMCK</name>
<description>No divider</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCKDIV</name>
<description>Master clock divider. These bits are set
and cleared by software. These bits are meaningless
when the audio block operates in slave mode. They
have to be configured when the audio block is
disabled. Others: the master clock frequency is
calculated accordingly to the following
formula:</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OSR</name>
<description>Oversampling ratio for master
clock</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_BCR2</name>
<displayName>SAI_BCR2</displayName>
<description>Configuration register 2</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FTH</name>
<description>FIFO threshold. This bit is set and
cleared by software.</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FFLUSH</name>
<description>FIFO flush. This bit is set by software.
It is always read as 0. This bit should be configured
when the SAI is disabled.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TRIS</name>
<description>Tristate management on data line. This
bit is set and cleared by software. It is meaningful
only if the audio block is configured as a
transmitter. This bit is not used when the audio
block is configured in SPDIF mode. It should be
configured when SAI is disabled. Refer to Section:
Output data line management on an inactive slot for
more details.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MUTE</name>
<description>Mute. This bit is set and cleared by
software. It is meaningful only when the audio block
operates as a transmitter. The MUTE value is linked
to value of MUTEVAL if the number of slots is lower
or equal to 2, or equal to 0 if it is greater than 2.
Refer to Section: Mute mode for more details. Note:
This bit is meaningless and should not be used for
SPDIF audio blocks.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MUTEVAL</name>
<description>Mute value. This bit is set and cleared
by software.It must be written before enabling the
audio block: SAIXEN. This bit is meaningful only when
the audio block operates as a transmitter, the number
of slots is lower or equal to 2 and the MUTE bit is
set. If more slots are declared, the bit value sent
during the transmission in mute mode is equal to 0,
whatever the value of MUTEVAL. if the number of slot
is lower or equal to 2 and MUTEVAL = 1, the MUTE
value transmitted for each slot is the one sent
during the previous frame. Refer to Section: Mute
mode for more details. Note: This bit is meaningless
and should not be used for SPDIF audio
blocks.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MUTECNT</name>
<description>Mute counter. These bits are set and
cleared by software. They are used only in reception
mode. The value set in these bits is compared to the
number of consecutive mute frames detected in
reception. When the number of mute frames is equal to
this value, the flag MUTEDET will be set and an
interrupt will be generated if bit MUTEDETIE is set.
Refer to Section: Mute mode for more
details.</description>
<bitOffset>7</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CPL</name>
<description>Complement bit. This bit is set and
cleared by software. It defines the type of
complement to be used for companding mode Note: This
bit has effect only when the companding mode is -Law
algorithm or A-Law algorithm.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP</name>
<description>Companding mode. These bits are set and
cleared by software. The -Law and the A-Law log are a
part of the CCITT G.711 recommendation, the type of
complement that will be used depends on CPL bit. The
data expansion or data compression are determined by
the state of bit MODE[0]. The data compression is
applied if the audio block is configured as a
transmitter. The data expansion is automatically
applied when the audio block is configured as a
receiver. Refer to Section: Companding mode for more
details. Note: Companding mode is applicable only
when TDM is selected.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SAI_BFRCR</name>
<displayName>SAI_BFRCR</displayName>
<description>This register has no meaning in AC97 and
SPDIF audio protocol</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>FRL</name>
<description>Frame length. These bits are set and
cleared by software. They define the audio frame
length expressed in number of SCK clock cycles: the
number of bits in the frame is equal to FRL[7:0] + 1.
The minimum number of bits to transfer in an audio
frame must be equal to 8, otherwise the audio block
will behaves in an unexpected way. This is the case
when the data size is 8 bits and only one slot 0 is
defined in NBSLOT[4:0] of SAI_xSLOTR register
(NBSLOT[3:0] = 0000). In master mode, if the master
clock (available on MCLK_x pin) is used, the frame
length should be aligned with a number equal to a
power of 2, ranging from 8 to 256. When the master
clock is not used (NODIV = 1), it is recommended to
program the frame length to an value ranging from 8
to 256. These bits are meaningless and are not used
in AC97 or SPDIF audio block
configuration.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSALL</name>
<description>Frame synchronization active level
length. These bits are set and cleared by software.
They specify the length in number of bit clock (SCK)
+ 1 (FSALL[6:0] + 1) of the active level of the FS
signal in the audio frame These bits are meaningless
and are not used in AC97 or SPDIF audio block
configuration. They must be configured when the audio
block is disabled.</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSDEF</name>
<description>Frame synchronization definition. This
bit is set and cleared by software. When the bit is
set, the number of slots defined in the SAI_xSLOTR
register has to be even. It means that half of this
number of slots will be dedicated to the left channel
and the other slots for the right channel (e.g: this
bit has to be set for I2S or MSB/LSB-justified
protocols...). This bit is meaningless and is not
used in AC97 or SPDIF audio block configuration. It
must be configured when the audio block is
disabled.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FSPOL</name>
<description>Frame synchronization polarity. This bit
is set and cleared by software. It is used to
configure the level of the start of frame on the FS
signal. It is meaningless and is not used in AC97 or
SPDIF audio block configuration. This bit must be
configured when the audio block is
disabled.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSOFF</name>
<description>Frame synchronization offset. This bit
is set and cleared by software. It is meaningless and
is not used in AC97 or SPDIF audio block
configuration. This bit must be configured when the
audio block is disabled.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SAI_BSLOTR</name>
<displayName>SAI_BSLOTR</displayName>
<description>This register has no meaning in AC97 and
SPDIF audio protocol</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FBOFF</name>
<description>First bit offset These bits are set and
cleared by software. The value set in this bitfield
defines the position of the first data transfer bit
in the slot. It represents an offset value. In
transmission mode, the bits outside the data field
are forced to 0. In reception mode, the extra
received bits are discarded. These bits must be set
when the audio block is disabled. They are ignored in
AC97 or SPDIF mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SLOTSZ</name>
<description>Slot size This bits is set and cleared
by software. The slot size must be higher or equal to
the data size. If this condition is not respected,
the behavior of the SAI will be undetermined. Refer
to Section: Output data line management on an
inactive slot for information on how to drive SD
line. These bits must be set when the audio block is
disabled. They are ignored in AC97 or SPDIF
mode.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NBSLOT</name>
<description>Number of slots in an audio frame. These
bits are set and cleared by software. The value set
in this bitfield represents the number of slots + 1
in the audio frame (including the number of inactive
slots). The maximum number of slots is 16. The number
of slots should be even if FSDEF bit in the SAI_xFRCR
register is set. The number of slots must be
configured when the audio block is disabled. They are
ignored in AC97 or SPDIF mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SLOTEN</name>
<description>Slot enable. These bits are set and
cleared by software. Each SLOTEN bit corresponds to a
slot position from 0 to 15 (maximum 16 slots). The
slot must be enabled when the audio block is
disabled. They are ignored in AC97 or SPDIF
mode.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_BIM</name>
<displayName>SAI_BIM</displayName>
<description>Interrupt mask register 2</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVRUDRIE</name>
<description>Overrun/underrun interrupt enable. This
bit is set and cleared by software. When this bit is
set, an interrupt is generated if the OVRUDR bit in
the SAI_xSR register is set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDETIE</name>
<description>Mute detection interrupt enable. This
bit is set and cleared by software. When this bit is
set, an interrupt is generated if the MUTEDET bit in
the SAI_xSR register is set. This bit has a meaning
only if the audio block is configured in receiver
mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFGIE</name>
<description>Wrong clock configuration interrupt
enable. This bit is set and cleared by software. This
bit is taken into account only if the audio block is
configured as a master (MODE[1] = 0) and NODIV = 0.
It generates an interrupt if the WCKCFG flag in the
SAI_xSR register is set. Note: This bit is used only
in TDM mode and is meaningless in other
modes.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQIE</name>
<description>FIFO request interrupt enable. This bit
is set and cleared by software. When this bit is set,
an interrupt is generated if the FREQ bit in the
SAI_xSR register is set. Since the audio block
defaults to operate as a transmitter after reset, the
MODE bit must be configured before setting FREQIE to
avoid a parasitic interruption in receiver
mode,</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDYIE</name>
<description>Codec not ready interrupt enable (AC97).
This bit is set and cleared by software. When the
interrupt is enabled, the audio block detects in the
slot 0 (tag0) of the AC97 frame if the Codec
connected to this line is ready or not. If it is not
ready, the CNRDY flag in the SAI_xSR register is set
and an interruption i generated. This bit has a
meaning only if the AC97 mode is selected through
PRTCFG[1:0] bits and the audio block is operates as a
receiver.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDETIE</name>
<description>Anticipated frame synchronization
detection interrupt enable. This bit is set and
cleared by software. When this bit is set, an
interrupt will be generated if the AFSDET bit in the
SAI_xSR register is set. This bit is meaningless in
AC97, SPDIF mode or when the audio block operates as
a master.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LFSDETIE</name>
<description>Late frame synchronization detection
interrupt enable. This bit is set and cleared by
software. When this bit is set, an interrupt will be
generated if the LFSDET bit is set in the SAI_xSR
register. This bit is meaningless in AC97, SPDIF mode
or when the audio block operates as a
master.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_BSR</name>
<displayName>SAI_BSR</displayName>
<description>Status register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000008</resetValue>
<fields>
<field>
<name>OVRUDR</name>
<description>Overrun / underrun. This bit is read
only. The overrun and underrun conditions can occur
only when the audio block is configured as a receiver
and a transmitter, respectively. It can generate an
interrupt if OVRUDRIE bit is set in SAI_xIM register.
This flag is cleared when the software sets COVRUDR
bit in SAI_xCLRFR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection. This bit is read only.
This flag is set if consecutive 0 values are received
in each slot of a given audio frame and for a
consecutive number of audio frames (set in the
MUTECNT bit in the SAI_xCR2 register). It can
generate an interrupt if MUTEDETIE bit is set in
SAI_xIM register. This flag is cleared when the
software sets bit CMUTEDET in the SAI_xCLRFR
register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration flag. This bit
is read only. This bit is used only when the audio
block operates in master mode (MODE[1] = 0) and NODIV
= 0. It can generate an interrupt if WCKCFGIE bit is
set in SAI_xIM register. This flag is cleared when
the software sets CWCKCFG bit in SAI_xCLRFR
register.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQ</name>
<description>FIFO request. This bit is read only. The
request depends on the audio block configuration: If
the block is configured in transmission mode, the
FIFO request is related to a write request operation
in the SAI_xDR. If the block configured in reception,
the FIFO request related to a read request operation
from the SAI_xDR. This flag can generate an interrupt
if FREQIE bit is set in SAI_xIM
register.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Codec not ready. This bit is read only.
This bit is used only when the AC97 audio protocol is
selected in the SAI_xCR1 register and configured in
receiver mode. It can generate an interrupt if
CNRDYIE bit is set in SAI_xIM register. This flag is
cleared when the software sets CCNRDY bit in
SAI_xCLRFR register.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDET</name>
<description>Anticipated frame synchronization
detection. This bit is read only. This flag can be
set only if the audio block is configured in slave
mode. It is not used in AC97or SPDIF mode. It can
generate an interrupt if AFSDETIE bit is set in
SAI_xIM register. This flag is cleared when the
software sets CAFSDET bit in SAI_xCLRFR
register.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LFSDET</name>
<description>Late frame synchronization detection.
This bit is read only. This flag can be set only if
the audio block is configured in slave mode. It is
not used in AC97 or SPDIF mode. It can generate an
interrupt if LFSDETIE bit is set in the SAI_xIM
register. This flag is cleared when the software sets
bit CLFSDET in SAI_xCLRFR register</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLVL</name>
<description>FIFO level threshold. This bit is read
only. The FIFO level threshold flag is managed only
by hardware and its setting depends on SAI block
configuration (transmitter or receiver mode). If the
SAI block is configured as transmitter: If SAI block
is configured as receiver:</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_BCLRFR</name>
<displayName>SAI_BCLRFR</displayName>
<description>Clear flag register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COVRUDR</name>
<description>Clear overrun / underrun. This bit is
write only. Programming this bit to 1 clears the
OVRUDR flag in the SAI_xSR register. Reading this bit
always returns the value 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMUTEDET</name>
<description>Mute detection flag. This bit is write
only. Programming this bit to 1 clears the MUTEDET
flag in the SAI_xSR register. Reading this bit always
returns the value 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWCKCFG</name>
<description>Clear wrong clock configuration flag.
This bit is write only. Programming this bit to 1
clears the WCKCFG flag in the SAI_xSR register. This
bit is used only when the audio block is set as
master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1
register. Reading this bit always returns the value
0.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCNRDY</name>
<description>Clear Codec not ready flag. This bit is
write only. Programming this bit to 1 clears the
CNRDY flag in the SAI_xSR register. This bit is used
only when the AC97 audio protocol is selected in the
SAI_xCR1 register. Reading this bit always returns
the value 0.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAFSDET</name>
<description>Clear anticipated frame synchronization
detection flag. This bit is write only. Programming
this bit to 1 clears the AFSDET flag in the SAI_xSR
register. It is not used in AC97or SPDIF mode.
Reading this bit always returns the value
0.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLFSDET</name>
<description>Clear late frame synchronization
detection flag. This bit is write only. Programming
this bit to 1 clears the LFSDET flag in the SAI_xSR
register. This bit is not used in AC97or SPDIF mode
Reading this bit always returns the value
0.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_BDR</name>
<displayName>SAI_BDR</displayName>
<description>Data register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data A write to this register loads the
FIFO provided the FIFO is not full. A read from this
register empties the FIFO if the FIFO is not
empty.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_PDMCR</name>
<displayName>SAI_PDMCR</displayName>
<description>PDM control register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDMEN</name>
<description>PDM enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MICNBR</name>
<description>Number of microphones</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKEN1</name>
<description>Clock enable of bitstream clock number
1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN2</name>
<description>Clock enable of bitstream clock number
2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN3</name>
<description>Clock enable of bitstream clock number
3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN4</name>
<description>Clock enable of bitstream clock number
4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAI_PDMDLY</name>
<displayName>SAI_PDMDLY</displayName>
<description>PDM delay register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYM1L</name>
<description>Delay line adjust for first microphone
of pair 1</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM1R</name>
<description>Delay line adjust for second microphone
of pair 1</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM2L</name>
<description>Delay line for first microphone of pair
2</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM2R</name>
<description>Delay line for second microphone of pair
2</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM3L</name>
<description>Delay line for first microphone of pair
3</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM3R</name>
<description>Delay line for second microphone of pair
3</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM4L</name>
<description>Delay line for first microphone of pair
4</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM4R</name>
<description>Delay line for second microphone of pair
4</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SAI1">
<name>SAI2</name>
<baseAddress>0x40015C00</baseAddress>
<interrupt>
<name>RTC_TAMP_STAMP_CSS_LSE</name>
<description>RTC tamper, timestamp</description>
<value>2</value>
</interrupt>
<interrupt>
<name>RTC_WKUP</name>
<description>RTC Wakeup interrupt</description>
<value>3</value>
</interrupt>
<interrupt>
<name>RTC_ALARM</name>
<description>RTC alarms (A and B)</description>
<value>41</value>
</interrupt>
</peripheral>
<peripheral>
<name>SCB</name>
<description>System control block</description>
<groupName>SCB</groupName>
<baseAddress>0xE000ED00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x41</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CPUID</name>
<displayName>CPUID</displayName>
<description>CPUID base register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x410FC241</resetValue>
<fields>
<field>
<name>Revision</name>
<description>Revision number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PartNo</name>
<description>Part number of the
processor</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>Constant</name>
<description>Reads as 0xF</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Variant</name>
<description>Variant number</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Implementer</name>
<description>Implementer code</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICSR</name>
<displayName>ICSR</displayName>
<description>Interrupt control and state
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTACTIVE</name>
<description>Active vector</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RETTOBASE</name>
<description>Return to base level</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTPENDING</name>
<description>Pending vector</description>
<bitOffset>12</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ISRPENDING</name>
<description>Interrupt pending flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSTCLR</name>
<description>SysTick exception clear-pending
bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSTSET</name>
<description>SysTick exception set-pending
bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVCLR</name>
<description>PendSV clear-pending bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVSET</name>
<description>PendSV set-pending bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NMIPENDSET</name>
<description>NMI set-pending bit.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>VTOR</name>
<displayName>VTOR</displayName>
<description>Vector table offset register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBLOFF</name>
<description>Vector table base offset
field</description>
<bitOffset>9</bitOffset>
<bitWidth>21</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIRCR</name>
<displayName>AIRCR</displayName>
<description>Application interrupt and reset control
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTRESET</name>
<description>VECTRESET</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTCLRACTIVE</name>
<description>VECTCLRACTIVE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSRESETREQ</name>
<description>SYSRESETREQ</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIGROUP</name>
<description>PRIGROUP</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ENDIANESS</name>
<description>ENDIANESS</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<displayName>SCR</displayName>
<description>System control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEPONEXIT</name>
<description>SLEEPONEXIT</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLEEPDEEP</name>
<description>SLEEPDEEP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEVEONPEND</name>
<description>Send Event on Pending bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>Configuration and control
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NONBASETHRDENA</name>
<description>Configures how the processor enters
Thread mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USERSETMPEND</name>
<description>USERSETMPEND</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNALIGN__TRP</name>
<description>UNALIGN_ TRP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_0_TRP</name>
<description>DIV_0_TRP</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFHFNMIGN</name>
<description>BFHFNMIGN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STKALIGN</name>
<description>STKALIGN</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DC</name>
<description>DC</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IC</name>
<description>IC</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BP</name>
<description>BP</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR1</name>
<displayName>SHPR1</displayName>
<description>System handler priority
registers</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_4</name>
<description>Priority of system handler
4</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_5</name>
<description>Priority of system handler
5</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_6</name>
<description>Priority of system handler
6</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR2</name>
<displayName>SHPR2</displayName>
<description>System handler priority
registers</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_11</name>
<description>Priority of system handler
11</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR3</name>
<displayName>SHPR3</displayName>
<description>System handler priority
registers</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_14</name>
<description>Priority of system handler
14</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_15</name>
<description>Priority of system handler
15</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHCSR</name>
<displayName>SHCSR</displayName>
<description>System handler control and state
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEMFAULTACT</name>
<description>Memory management fault exception active
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTACT</name>
<description>Bus fault exception active
bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTACT</name>
<description>Usage fault exception active
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVCALLACT</name>
<description>SVC call active bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONITORACT</name>
<description>Debug monitor active bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVACT</name>
<description>PendSV exception active
bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSTICKACT</name>
<description>SysTick exception active
bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTPENDED</name>
<description>Usage fault exception pending
bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEMFAULTPENDED</name>
<description>Memory management fault exception
pending bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTPENDED</name>
<description>Bus fault exception pending
bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVCALLPENDED</name>
<description>SVC call pending bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEMFAULTENA</name>
<description>Memory management fault enable
bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTENA</name>
<description>Bus fault enable bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTENA</name>
<description>Usage fault enable bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFSR_UFSR_BFSR_MMFSR</name>
<displayName>CFSR_UFSR_BFSR_MMFSR</displayName>
<description>Configurable fault status
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IACCVIOL</name>
<description>IACCVIOL</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DACCVIOL</name>
<description>DACCVIOL</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUNSTKERR</name>
<description>MUNSTKERR</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTKERR</name>
<description>MSTKERR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MLSPERR</name>
<description>MLSPERR</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMARVALID</name>
<description>MMARVALID</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IBUSERR</name>
<description>Instruction bus error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRECISERR</name>
<description>Precise data bus error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IMPRECISERR</name>
<description>Imprecise data bus error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNSTKERR</name>
<description>Bus fault on unstacking for a return
from exception</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STKERR</name>
<description>Bus fault on stacking for exception
entry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPERR</name>
<description>Bus fault on floating-point lazy state
preservation</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFARVALID</name>
<description>Bus Fault Address Register (BFAR) valid
flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDEFINSTR</name>
<description>Undefined instruction usage
fault</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVSTATE</name>
<description>Invalid state usage fault</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVPC</name>
<description>Invalid PC load usage
fault</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOCP</name>
<description>No coprocessor usage
fault.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNALIGNED</name>
<description>Unaligned access usage
fault</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIVBYZERO</name>
<description>Divide by zero usage fault</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HFSR</name>
<displayName>HFSR</displayName>
<description>Hard fault status register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTTBL</name>
<description>Vector table hard fault</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCED</name>
<description>Forced hard fault</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBUG_VT</name>
<description>Reserved for Debug use</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMFAR</name>
<displayName>MMFAR</displayName>
<description>Memory management fault address
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Memory management fault
address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFAR</name>
<displayName>BFAR</displayName>
<description>Bus fault address register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Bus fault address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCB_ACTRL</name>
<description>System control block ACTLR</description>
<groupName>SCB</groupName>
<baseAddress>0xE000E008</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ACTRL</name>
<displayName>ACTRL</displayName>
<description>Auxiliary control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DISFOLD</name>
<description>DISFOLD</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPEXCODIS</name>
<description>FPEXCODIS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISRAMODE</name>
<description>DISRAMODE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISITMATBFLUSH</name>
<description>DISITMATBFLUSH</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SDMMC1</name>
<description>SDMMC1</description>
<groupName>SDMMC</groupName>
<baseAddress>0x52007000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x3FD</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SAI2</name>
<description>SAI2 global interrupt</description>
<value>91</value>
</interrupt>
<registers>
<register>
<name>SDMMC_POWER</name>
<displayName>SDMMC_POWER</displayName>
<description>SDMMC power control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWRCTRL</name>
<description>SDMMC state control bits. These bits can
only be written when the SDMMC is not in the power-on
state (PWRCTRL?11). These bits are used to define the
functional state of the SDMMC signals: Any further
write will be ignored, PWRCTRL value will keep
11.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>VSWITCH</name>
<description>Voltage switch sequence start. This bit
is used to start the timing critical section of the
voltage switch sequence:</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSWITCHEN</name>
<description>Voltage switch procedure enable. This
bit can only be written by firmware when CPSM is
disabled (CPSMEN = 0). This bit is used to stop the
SDMMC_CK after the voltage switch command
response:</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIRPOL</name>
<description>Data and command direction signals
polarity selection. This bit can only be written when
the SDMMC is in the power-off state (PWRCTRL =
00).</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_CLKCR</name>
<displayName>SDMMC_CLKCR</displayName>
<description>The SDMMC_CLKCR register controls the
SDMMC_CK output clock, the SDMMC_RX_CLK receive clock,
and the bus width.</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock divide factor This bit can only be
written when the CPSM and DPSM are not active
(CPSMACT = 0 and DPSMACT = 0). This field defines the
divide factor between the input clock (SDMMCCLK) and
the output clock (SDMMC_CK): SDMMC_CK frequency =
SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx:
etc..</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>PWRSAV</name>
<description>Power saving configuration bit This bit
can only be written when the CPSM and DPSM are not
active (CPSMACT = 0 and DPSMACT = 0) For power
saving, the SDMMC_CK clock output can be disabled
when the bus is idle by setting PWRSAV:</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WIDBUS</name>
<description>Wide bus mode enable bit This bit can
only be written when the CPSM and DPSM are not active
(CPSMACT = 0 and DPSMACT = 0)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NEGEDGE</name>
<description>SDMMC_CK dephasing selection bit for
data and Command. This bit can only be written when
the CPSM and DPSM are not active (CPSMACT = 0 and
DPSMACT = 0). When clock division = 1 (CLKDIV = 0),
this bit has no effect. Data and Command change on
SDMMC_CK falling edge. When clock division &amp;gt;1
(CLKDIV &amp;gt; 0) &amp;amp; DDR = 0: - SDMMC_CK
edge occurs on SDMMCCLK rising edge. When clock
division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 1: - Data
changed on the SDMMCCLK falling edge succeeding a
SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK
rising edge. - Data changed on the SDMMC_CK falling
edge succeeding a SDMMC_CK edge. - SDMMC_CK edge
occurs on SDMMCCLK rising edge.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HWFC_EN</name>
<description>Hardware flow control enable This bit
can only be written when the CPSM and DPSM are not
active (CPSMACT = 0 and DPSMACT = 0) When Hardware
flow control is enabled, the meaning of the TXFIFOE
and RXFIFOF flags change, please see SDMMC status
register definition in Section56.8.11.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDR</name>
<description>Data rate signaling selection This bit
can only be written when the CPSM and DPSM are not
active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall
only be selected with 4-bit or 8-bit wide bus mode.
(WIDBUS &amp;gt; 00). DDR = 1 has no effect when
WIDBUS = 00 (1-bit wide bus). DDR rate shall only be
selected with clock division &amp;gt;1. (CLKDIV
&amp;gt; 0)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSSPEED</name>
<description>Bus speed mode selection between DS, HS,
SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can
only be written when the CPSM and DPSM are not active
(CPSMACT = 0 and DPSMACT = 0)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SELCLKRX</name>
<description>Receive clock selection. These bits can
only be written when the CPSM and DPSM are not active
(CPSMACT = 0 and DPSMACT = 0)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_ARGR</name>
<displayName>SDMMC_ARGR</displayName>
<description>The SDMMC_ARGR register contains a 32-bit
command argument, which is sent to a card as part of a
command message.</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMDARG</name>
<description>Command argument. These bits can only be
written by firmware when CPSM is disabled (CPSMEN =
0). Command argument sent to a card as part of a
command message. If a command contains an argument,
it must be loaded into this register before writing a
command to the command register.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_CMDR</name>
<displayName>SDMMC_CMDR</displayName>
<description>The SDMMC_CMDR register contains the command
index and command type bits. The command index is sent to
a card as part of a command message. The command type
bits control the command path state machine
(CPSM).</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMDINDEX</name>
<description>Command index. This bit can only be
written by firmware when CPSM is disabled (CPSMEN =
0). The command index is sent to the card as part of
a command message.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CMDTRANS</name>
<description>The CPSM treats the command as a data
transfer command, stops the interrupt period, and
signals DataEnable to the DPSM This bit can only be
written by firmware when CPSM is disabled (CPSMEN =
0). If this bit is set, the CPSM issues an end of
interrupt period and issues DataEnable signal to the
DPSM when the command is sent.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDSTOP</name>
<description>The CPSM treats the command as a Stop
Transmission command and signals Abort to the DPSM.
This bit can only be written by firmware when CPSM is
disabled (CPSMEN = 0). If this bit is set, the CPSM
issues the Abort signal to the DPSM when the command
is sent.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITRESP</name>
<description>Wait for response bits. This bit can
only be written by firmware when CPSM is disabled
(CPSMEN = 0). They are used to configure whether the
CPSM is to wait for a response, and if yes, which
kind of response.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WAITINT</name>
<description>CPSM waits for interrupt request. If
this bit is set, the CPSM disables command timeout
and waits for an card interrupt request (Response).
If this bit is cleared in the CPSM Wait state, will
cause the abort of the interrupt mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITPEND</name>
<description>CPSM Waits for end of data transfer
(CmdPend internal signal) from DPSM. This bit when
set, the CPSM waits for the end of data transfer
trigger before it starts sending a command. WAITPEND
is only taken into account when DTMODE = MMC stream
data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT
= 1 and DTDIR = from host to card.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPSMEN</name>
<description>Command path state machine (CPSM) Enable
bit This bit is written 1 by firmware, and cleared by
hardware when the CPSM enters the Idle state. If this
bit is set, the CPSM is enabled. When DTEN = 1, no
command will be transfered nor boot procedure will be
started. CPSMEN is cleared to 0.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTHOLD</name>
<description>Hold new data block transmission and
reception in the DPSM. If this bit is set, the DPSM
will not move from the Wait_S state to the Send state
or from the Wait_R state to the Receive
state.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOOTMODE</name>
<description>Select the boot mode procedure to be
used. This bit can only be written by firmware when
CPSM is disabled (CPSMEN = 0)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOOTEN</name>
<description>Enable boot mode
procedure.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDSUSPEND</name>
<description>The CPSM treats the command as a Suspend
or Resume command and signals interrupt period
start/end. This bit can only be written by firmware
when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1
and CMDTRANS = 0 Suspend command, start interrupt
period when response bit BS=0. CMDSUSPEND = 1 and
CMDTRANS = 1 Resume command with data, end interrupt
period when response bit DF=1.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_RESP1R</name>
<displayName>SDMMC_RESP1R</displayName>
<description>The SDMMC_RESP1/2/3/4R registers contain the
status of a card, which is part of the received
response.</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARDSTATUS1</name>
<description>see Table 432</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_RESP2R</name>
<displayName>SDMMC_RESP2R</displayName>
<description>The SDMMC_RESP1/2/3/4R registers contain the
status of a card, which is part of the received
response.</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARDSTATUS2</name>
<description>see Table404.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_RESP3R</name>
<displayName>SDMMC_RESP3R</displayName>
<description>The SDMMC_RESP1/2/3/4R registers contain the
status of a card, which is part of the received
response.</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARDSTATUS3</name>
<description>see Table404.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_RESP4R</name>
<displayName>SDMMC_RESP4R</displayName>
<description>The SDMMC_RESP1/2/3/4R registers contain the
status of a card, which is part of the received
response.</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARDSTATUS4</name>
<description>see Table404.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_DTIMER</name>
<displayName>SDMMC_DTIMER</displayName>
<description>The SDMMC_DTIMER register contains the data
timeout period, in card bus clock periods. A counter
loads the value from the SDMMC_DTIMER register, and
starts decrementing when the data path state machine
(DPSM) enters the Wait_R or Busy state. If the timer
reaches 0 while the DPSM is in either of these states,
the timeout status flag is set.</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATATIME</name>
<description>Data and R1b busy timeout period This
bit can only be written when the CPSM and DPSM are
not active (CPSMACT = 0 and DPSMACT = 0). Data and
R1b busy timeout period expressed in card bus clock
periods.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_DLENR</name>
<displayName>SDMMC_DLENR</displayName>
<description>The SDMMC_DLENR register contains the number
of data bytes to be transferred. The value is loaded into
the data counter when data transfer starts.</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATALENGTH</name>
<description>Data length value This register can only
be written by firmware when DPSM is inactive (DPSMACT
= 0). Number of data bytes to be transferred. When
DDR = 1 DATALENGTH is truncated to a multiple of 2.
(The last odd byte is not transfered) When DATALENGTH
= 0 no data will be transfered, when requested by a
CPSMEN and CMDTRANS = 1 also no command will be
transfered. DTEN and CPSMEN are cleared to
0.</description>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_DCTRL</name>
<displayName>SDMMC_DCTRL</displayName>
<description>The SDMMC_DCTRL register control the data
path state machine (DPSM).</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTEN</name>
<description>Data transfer enable bit This bit can
only be written by firmware when DPSM is inactive
(DPSMACT = 0). This bit is cleared by Hardware when
data transfer completes. This bit shall only be used
to transfer data when no associated data transfer
command is used, i.e. shall not be used with SD or
eMMC cards.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTDIR</name>
<description>Data transfer direction selection This
bit can only be written by firmware when DPSM is
inactive (DPSMACT = 0).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTMODE</name>
<description>Data transfer mode selection. This bit
can only be written by firmware when DPSM is inactive
(DPSMACT = 0).</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DBLOCKSIZE</name>
<description>Data block size This bit can only be
written by firmware when DPSM is inactive (DPSMACT =
0). Define the data block length when the block data
transfer mode is selected: When DATALENGTH is not a
multiple of DBLOCKSIZE, the transfered data is
truncated at a multiple of DBLOCKSIZE. (Any remain
data will not be transfered.) When DDR = 1,
DBLOCKSIZE = 0000 shall not be used. (No data will be
transfered)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RWSTART</name>
<description>Read wait start. If this bit is set,
read wait operation starts.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWSTOP</name>
<description>Read wait stop This bit is written by
firmware and auto cleared by hardware when the DPSM
moves from the READ_WAIT state to the WAIT_R or IDLE
state.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWMOD</name>
<description>Read wait mode. This bit can only be
written by firmware when DPSM is inactive (DPSMACT =
0).</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOEN</name>
<description>SD I/O interrupt enable functions This
bit can only be written by firmware when DPSM is
inactive (DPSMACT = 0). If this bit is set, the DPSM
enables the SD I/O card specific interrupt
operation.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOOTACKEN</name>
<description>Enable the reception of the boot
acknowledgment. This bit can only be written by
firmware when DPSM is inactive (DPSMACT =
0).</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFORST</name>
<description>FIFO reset, will flush any remaining
data. This bit can only be written by firmware when
IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit
will only take effect when a transfer error or
transfer hold occurs.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_DCNTR</name>
<displayName>SDMMC_DCNTR</displayName>
<description>The SDMMC_DCNTR register loads the value
from the data length register (see SDMMC_DLENR) when the
DPSM moves from the Idle state to the Wait_R or Wait_S
state. As data is transferred, the counter decrements the
value until it reaches 0. The DPSM then moves to the Idle
state and when there has been no error, the data status
end flag (DATAEND) is set.</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATACOUNT</name>
<description>Data count value When read, the number
of remaining data bytes to be transferred is
returned. Write has no effect.</description>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_STAR</name>
<displayName>SDMMC_STAR</displayName>
<description>The SDMMC_STAR register is a read-only
register. It contains two types of flag:Static flags
(bits [29,21,11:0]): these bits remain asserted until
they are cleared by writing to the SDMMC interrupt Clear
register (see SDMMC_ICR)Dynamic flags (bits [20:12]):
these bits change state depending on the state of the
underlying logic (for example, FIFO full and empty flags
are asserted and de-asserted as data while written to the
FIFO)</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCRCFAIL</name>
<description>Command response received (CRC check
failed). Interrupt flag is cleared by writing
corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRCFAIL</name>
<description>Data block sent/received (CRC check
failed). Interrupt flag is cleared by writing
corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTIMEOUT</name>
<description>Command response timeout. Interrupt flag
is cleared by writing corresponding interrupt clear
bit in SDMMC_ICR. The Command Timeout period has a
fixed value of 64 SDMMC_CK clock
periods.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTIMEOUT</name>
<description>Data timeout. Interrupt flag is cleared
by writing corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUNDERR</name>
<description>Transmit FIFO underrun error or IDMA
read transfer error. Interrupt flag is cleared by
writing corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVERR</name>
<description>Received FIFO overrun error or IDMA
write transfer error. Interrupt flag is cleared by
writing corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDREND</name>
<description>Command response received (CRC check
passed, or no CRC). Interrupt flag is cleared by
writing corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDSENT</name>
<description>Command sent (no response required).
Interrupt flag is cleared by writing corresponding
interrupt clear bit in SDMMC_ICR.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAEND</name>
<description>Data transfer ended correctly. (data
counter, DATACOUNT is zero and no errors occur).
Interrupt flag is cleared by writing corresponding
interrupt clear bit in SDMMC_ICR.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DHOLD</name>
<description>Data transfer Hold. Interrupt flag is
cleared by writing corresponding interrupt clear bit
in SDMMC_ICR.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBCKEND</name>
<description>Data block sent/received. (CRC check
passed) and DPSM moves to the READWAIT state.
Interrupt flag is cleared by writing corresponding
interrupt clear bit in SDMMC_ICR.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DABORT</name>
<description>Data transfer aborted by CMD12.
Interrupt flag is cleared by writing corresponding
interrupt clear bit in SDMMC_ICR.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DPSMACT</name>
<description>Data path state machine active, i.e. not
in Idle state. This is a hardware status flag only,
does not generate an interrupt.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPSMACT</name>
<description>Command path state machine active, i.e.
not in Idle state. This is a hardware status flag
only, does not generate an interrupt.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFOHE</name>
<description>Transmit FIFO half empty At least half
the number of words can be written into the FIFO.
This bit is cleared when the FIFO becomes half+1
full.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFOHF</name>
<description>Receive FIFO half full There are at
least half the number of words in the FIFO. This bit
is cleared when the FIFO becomes half+1
empty.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFOF</name>
<description>Transmit FIFO full This is a hardware
status flag only, does not generate an interrupt.
This bit is cleared when one FIFO location becomes
empty.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFOF</name>
<description>Receive FIFO full This bit is cleared
when one FIFO location becomes empty.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFOE</name>
<description>Transmit FIFO empty This bit is cleared
when one FIFO location becomes full.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFOE</name>
<description>Receive FIFO empty This is a hardware
status flag only, does not generate an interrupt.
This bit is cleared when one FIFO location becomes
full.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSYD0</name>
<description>Inverted value of SDMMC_D0 line (Busy),
sampled at the end of a CMD response and a second
time 2 SDMMC_CK cycles after the CMD response. This
bit is reset to not busy when the SDMMCD0 line
changes from busy to not busy. This bit does not
signal busy due to data transfer. This is a hardware
status flag only, it does not generate an
interrupt.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSYD0END</name>
<description>end of SDMMC_D0 Busy following a CMD
response detected. This indicates only end of busy
following a CMD response. This bit does not signal
busy due to data transfer. Interrupt flag is cleared
by writing corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOIT</name>
<description>SDIO interrupt received. Interrupt flag
is cleared by writing corresponding interrupt clear
bit in SDMMC_ICR.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKFAIL</name>
<description>Boot acknowledgment received (boot
acknowledgment check fail). Interrupt flag is cleared
by writing corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKTIMEOUT</name>
<description>Boot acknowledgment timeout. Interrupt
flag is cleared by writing corresponding interrupt
clear bit in SDMMC_ICR.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSWEND</name>
<description>Voltage switch critical timing section
completion. Interrupt flag is cleared by writing
corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKSTOP</name>
<description>SDMMC_CK stopped in Voltage switch
procedure. Interrupt flag is cleared by writing
corresponding interrupt clear bit in
SDMMC_ICR.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDMATE</name>
<description>IDMA transfer error. Interrupt flag is
cleared by writing corresponding interrupt clear bit
in SDMMC_ICR.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDMABTC</name>
<description>IDMA buffer transfer complete. interrupt
flag is cleared by writing corresponding interrupt
clear bit in SDMMC_ICR.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_ICR</name>
<displayName>SDMMC_ICR</displayName>
<description>The SDMMC_ICR register is a write-only
register. Writing a bit with 1 clears the corresponding
bit in the SDMMC_STAR status register.</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCRCFAILC</name>
<description>CCRCFAIL flag clear bit Set by software
to clear the CCRCFAIL flag.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRCFAILC</name>
<description>DCRCFAIL flag clear bit Set by software
to clear the DCRCFAIL flag.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTIMEOUTC</name>
<description>CTIMEOUT flag clear bit Set by software
to clear the CTIMEOUT flag.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTIMEOUTC</name>
<description>DTIMEOUT flag clear bit Set by software
to clear the DTIMEOUT flag.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUNDERRC</name>
<description>TXUNDERR flag clear bit Set by software
to clear TXUNDERR flag.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVERRC</name>
<description>RXOVERR flag clear bit Set by software
to clear the RXOVERR flag.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDRENDC</name>
<description>CMDREND flag clear bit Set by software
to clear the CMDREND flag.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDSENTC</name>
<description>CMDSENT flag clear bit Set by software
to clear the CMDSENT flag.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAENDC</name>
<description>DATAEND flag clear bit Set by software
to clear the DATAEND flag.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DHOLDC</name>
<description>DHOLD flag clear bit Set by software to
clear the DHOLD flag.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBCKENDC</name>
<description>DBCKEND flag clear bit Set by software
to clear the DBCKEND flag.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DABORTC</name>
<description>DABORT flag clear bit Set by software to
clear the DABORT flag.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSYD0ENDC</name>
<description>BUSYD0END flag clear bit Set by software
to clear the BUSYD0END flag.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOITC</name>
<description>SDIOIT flag clear bit Set by software to
clear the SDIOIT flag.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKFAILC</name>
<description>ACKFAIL flag clear bit Set by software
to clear the ACKFAIL flag.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKTIMEOUTC</name>
<description>ACKTIMEOUT flag clear bit Set by
software to clear the ACKTIMEOUT flag.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSWENDC</name>
<description>VSWEND flag clear bit Set by software to
clear the VSWEND flag.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKSTOPC</name>
<description>CKSTOP flag clear bit Set by software to
clear the CKSTOP flag.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDMATEC</name>
<description>IDMA transfer error clear bit Set by
software to clear the IDMATE flag.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDMABTCC</name>
<description>IDMA buffer transfer complete clear bit
Set by software to clear the IDMABTC
flag.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_MASKR</name>
<displayName>SDMMC_MASKR</displayName>
<description>The interrupt mask register determines which
status flags generate an interrupt request by setting the
corresponding bit to 1.</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCRCFAILIE</name>
<description>Command CRC fail interrupt enable Set
and cleared by software to enable/disable interrupt
caused by command CRC failure.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRCFAILIE</name>
<description>Data CRC fail interrupt enable Set and
cleared by software to enable/disable interrupt
caused by data CRC failure.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTIMEOUTIE</name>
<description>Command timeout interrupt enable Set and
cleared by software to enable/disable interrupt
caused by command timeout.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTIMEOUTIE</name>
<description>Data timeout interrupt enable Set and
cleared by software to enable/disable interrupt
caused by data timeout.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUNDERRIE</name>
<description>Tx FIFO underrun error interrupt enable
Set and cleared by software to enable/disable
interrupt caused by Tx FIFO underrun
error.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVERRIE</name>
<description>Rx FIFO overrun error interrupt enable
Set and cleared by software to enable/disable
interrupt caused by Rx FIFO overrun
error.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDRENDIE</name>
<description>Command response received interrupt
enable Set and cleared by software to enable/disable
interrupt caused by receiving command
response.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMDSENTIE</name>
<description>Command sent interrupt enable Set and
cleared by software to enable/disable interrupt
caused by sending command.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATAENDIE</name>
<description>Data end interrupt enable Set and
cleared by software to enable/disable interrupt
caused by data end.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DHOLDIE</name>
<description>Data hold interrupt enable Set and
cleared by software to enable/disable the interrupt
generated when sending new data is hold in the DPSM
Wait_S state.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBCKENDIE</name>
<description>Data block end interrupt enable Set and
cleared by software to enable/disable interrupt
caused by data block end.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DABORTIE</name>
<description>Data transfer aborted interrupt enable
Set and cleared by software to enable/disable
interrupt caused by a data transfer being
aborted.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFOHEIE</name>
<description>Tx FIFO half empty interrupt enable Set
and cleared by software to enable/disable interrupt
caused by Tx FIFO half empty.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFOHFIE</name>
<description>Rx FIFO half full interrupt enable Set
and cleared by software to enable/disable interrupt
caused by Rx FIFO half full.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFOFIE</name>
<description>Rx FIFO full interrupt enable Set and
cleared by software to enable/disable interrupt
caused by Rx FIFO full.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFOEIE</name>
<description>Tx FIFO empty interrupt enable Set and
cleared by software to enable/disable interrupt
caused by Tx FIFO empty.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSYD0ENDIE</name>
<description>BUSYD0END interrupt enable Set and
cleared by software to enable/disable the interrupt
generated when SDMMC_D0 signal changes from busy to
NOT busy following a CMD response.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIOITIE</name>
<description>SDIO mode interrupt received interrupt
enable Set and cleared by software to enable/disable
the interrupt generated when receiving the SDIO mode
interrupt.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKFAILIE</name>
<description>Acknowledgment Fail interrupt enable Set
and cleared by software to enable/disable interrupt
caused by acknowledgment Fail.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKTIMEOUTIE</name>
<description>Acknowledgment timeout interrupt enable
Set and cleared by software to enable/disable
interrupt caused by acknowledgment
timeout.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSWENDIE</name>
<description>Voltage switch critical timing section
completion interrupt enable Set and cleared by
software to enable/disable the interrupt generated
when voltage switch critical timing section
completion.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKSTOPIE</name>
<description>Voltage Switch clock stopped interrupt
enable Set and cleared by software to enable/disable
interrupt caused by Voltage Switch clock
stopped.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDMABTCIE</name>
<description>IDMA buffer transfer complete interrupt
enable Set and cleared by software to enable/disable
the interrupt generated when the IDMA has transferred
all data belonging to a memory buffer.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_ACKTIMER</name>
<displayName>SDMMC_ACKTIMER</displayName>
<description>The SDMMC_ACKTIMER register contains the
acknowledgment timeout period, in SDMMC_CK bus clock
periods. A counter loads the value from the
SDMMC_ACKTIMER register, and starts decrementing when the
data path state machine (DPSM) enters the Wait_Ack state.
If the timer reaches 0 while the DPSM is in this states,
the acknowledgment timeout status flag is
set.</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACKTIME</name>
<description>Boot acknowledgment timeout period This
bit can only be written by firmware when CPSM is
disabled (CPSMEN = 0). Boot acknowledgment timeout
period expressed in card bus clock
periods.</description>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_IDMACTRLR</name>
<displayName>SDMMC_IDMACTRLR</displayName>
<description>The receive and transmit FIFOs can be read
or written as 32-bit wide registers. The FIFOs contain 32
entries on 32 sequential addresses. This allows the CPU
to use its load and store multiple operands to read
from/write to the FIFO.</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDMAEN</name>
<description>IDMA enable This bit can only be written
by firmware when DPSM is inactive (DPSMACT =
0).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDMABMODE</name>
<description>Buffer mode selection. This bit can only
be written by firmware when DPSM is inactive (DPSMACT
= 0).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDMABACT</name>
<description>Double buffer mode active buffer
indication This bit can only be written by firmware
when DPSM is inactive (DPSMACT = 0). When IDMA is
enabled this bit is toggled by
hardware.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_IDMABSIZER</name>
<displayName>SDMMC_IDMABSIZER</displayName>
<description>The SDMMC_IDMABSIZER register contains the
buffers size when in double buffer
configuration.</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDMABNDT</name>
<description>Number of transfers per buffer. This
8-bit value shall be multiplied by 8 to get the size
of the buffer in 32-bit words and by 32 to get the
size of the buffer in bytes. Example: IDMABNDT =
0x01: buffer size = 8 words = 32 bytes. These bits
can only be written by firmware when DPSM is inactive
(DPSMACT = 0).</description>
<bitOffset>5</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_IDMABASE0R</name>
<displayName>SDMMC_IDMABASE0R</displayName>
<description>The SDMMC_IDMABASE0R register contains the
memory buffer base address in single buffer configuration
and the buffer 0 base address in double buffer
configuration.</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDMABASE0</name>
<description>Buffer 0 memory base address bits
[31:2], shall be word aligned (bit [1:0] are always 0
and read only). This register can be written by
firmware when DPSM is inactive (DPSMACT = 0), and can
dynamically be written by firmware when DPSM active
(DPSMACT = 1) and memory buffer 0 is inactive
(IDMABACT = 1).</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_IDMABASE1R</name>
<displayName>SDMMC_IDMABASE1R</displayName>
<description>The SDMMC_IDMABASE1R register contains the
double buffer configuration second buffer memory base
address.</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDMABASE1</name>
<description>Buffer 1 memory base address, shall be
word aligned (bit [1:0] are always 0 and read only).
This register can be written by firmware when DPSM is
inactive (DPSMACT = 0), and can dynamically be
written by firmware when DPSM active (DPSMACT = 1)
and memory buffer 1 is inactive (IDMABACT =
0).</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_FIFOR</name>
<displayName>SDMMC_FIFOR</displayName>
<description>The receive and transmit FIFOs can be only
read or written as word (32-bit) wide registers. The
FIFOs contain 16 entries on sequential addresses. This
allows the CPU to use its load and store multiple
operands to read from/write to the FIFO.When accessing
SDMMC_FIFOR with half word or byte access an AHB bus
fault is generated.</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FIFODATA</name>
<description>Receive and transmit FIFO data This
register can only be read or written by firmware when
the DPSM is active (DPSMACT=1). The FIFO data
occupies 16 entries of 32-bit words.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_VER</name>
<displayName>SDMMC_VER</displayName>
<description>SDMMC IP version register</description>
<addressOffset>0x3F4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>MINREV</name>
<description>IP minor revision number.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MAJREV</name>
<description>IP major revision number.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_ID</name>
<displayName>SDMMC_ID</displayName>
<description>SDMMC IP identification
register</description>
<addressOffset>0x3F8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00140022</resetValue>
<fields>
<field>
<name>IP_ID</name>
<description>SDMMC IP identification.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDMMC_RESPCMDR</name>
<displayName>SDMMC_RESPCMDR</displayName>
<description>SDMMC command response
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xA3C5DD01</resetValue>
<fields>
<field>
<name>RESPCMD</name>
<description>Response command index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SDMMC1">
<name>SDMMC2</name>
<baseAddress>0x48022400</baseAddress>
<interrupt>
<name>SDMMC1</name>
<description>SDMMC global interrupt</description>
<value>49</value>
</interrupt>
<interrupt>
<name>SDMMC</name>
<description>SDMMC global interrupt</description>
<value>124</value>
</interrupt>
</peripheral>
<peripheral>
<name>SPDIFRX</name>
<description>Receiver Interface</description>
<groupName>SPDIFRX</groupName>
<baseAddress>0x40004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LTDC</name>
<description>LCD-TFT global interrupt</description>
<value>88</value>
</interrupt>
<interrupt>
<name>LTDC_ER</name>
<description>LCD-TFT error interrupt</description>
<value>89</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPDIFRXEN</name>
<description>Peripheral Block Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RXDMAEN</name>
<description>Receiver DMA ENable for data
flow</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXSTEO</name>
<description>STerEO Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRFMT</name>
<description>RX Data format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PMSK</name>
<description>Mask Parity error bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VMSK</name>
<description>Mask of Validity bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CUMSK</name>
<description>Mask of channel status and user
bits</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTMSK</name>
<description>Mask of Preamble Type bits</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBDMAEN</name>
<description>Control Buffer DMA ENable for control
flow</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHSEL</name>
<description>Channel Selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBTR</name>
<description>Maximum allowed re-tries during
synchronization phase</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WFA</name>
<description>Wait For Activity</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INSEL</name>
<description>input selection</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CKSEN</name>
<description>Symbol Clock Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKSBKPEN</name>
<description>Backup Symbol Clock Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<displayName>IMR</displayName>
<description>Interrupt mask register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSRNEIE</name>
<description>Control Buffer Ready Interrupt
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERRIE</name>
<description>Parity error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRIE</name>
<description>Overrun error Interrupt
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBLKIE</name>
<description>Synchronization Block Detected Interrupt
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCDIE</name>
<description>Synchronization Done</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IFEIE</name>
<description>Serial Interface Error Interrupt
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXNE</name>
<description>Read data register not
empty</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSRNE</name>
<description>Control Buffer register is not
empty</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PERR</name>
<description>Parity error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>Overrun error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBD</name>
<description>Synchronization Block
Detected</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCD</name>
<description>Synchronization Done</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FERR</name>
<description>Framing error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SERR</name>
<description>Synchronization error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TERR</name>
<description>Time-out error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WIDTH5</name>
<description>Duration of 5 symbols counted with
SPDIF_CLK</description>
<bitOffset>16</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>Interrupt Flag Clear register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERRCF</name>
<description>Clears the Parity error
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRCF</name>
<description>Clears the Overrun error
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBDCF</name>
<description>Clears the Synchronization Block
Detected flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCDCF</name>
<description>Clears the Synchronization Done
flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR_00</name>
<displayName>DR_00</displayName>
<description>Data input register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DR</name>
<description>Parity Error bit</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>PE</name>
<description>Parity Error bit</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>V</name>
<description>Validity bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>U</name>
<description>User bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>Channel Status bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PT</name>
<description>Preamble Type</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>Channel Status register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>USR</name>
<description>User data information</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CS</name>
<description>Channel A status
information</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SOB</name>
<description>Start Of Block</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIR</name>
<displayName>DIR</displayName>
<description>Debug Information register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>THI</name>
<description>Threshold HIGH</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
<field>
<name>TLO</name>
<description>Threshold LOW</description>
<bitOffset>16</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>VERR</name>
<displayName>VERR</displayName>
<description>SPDIFRX version register</description>
<addressOffset>0x3F4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000012</resetValue>
<fields>
<field>
<name>MINREV</name>
<description>Minor revision</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MAJREV</name>
<description>Major revision</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>SPDIFRX identification
register</description>
<addressOffset>0x3F8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00130041</resetValue>
<fields>
<field>
<name>ID</name>
<description>SPDIFRX identifier</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIDR</name>
<displayName>SIDR</displayName>
<description>SPDIFRX size identification
register</description>
<addressOffset>0x3FC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xA3C5DD01</resetValue>
<fields>
<field>
<name>SID</name>
<description>Size identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR_01</name>
<displayName>DR_01</displayName>
<description>Data input register</description>
<alternateRegister>DR_00</alternateRegister>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PE</name>
<description>Parity Error bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>V</name>
<description>Validity bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>U</name>
<description>User bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>Channel Status bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PT</name>
<description>Preamble Type</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DR</name>
<description>Data value</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR_10</name>
<displayName>DR_10</displayName>
<description>Data input register</description>
<alternateRegister>DR_00</alternateRegister>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DRNL1</name>
<description>Data value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DRNL2</name>
<description>Data value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>Serial peripheral interface</description>
<groupName>SPI</groupName>
<baseAddress>0x40013000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<description>SPI1 global interrupt</description>
<value>35</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOLOCK</name>
<description>Locking the AF configuration of
associated IOs</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TCRCI</name>
<description>CRC calculation initialization pattern
control for transmitter</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RCRCI</name>
<description>CRC calculation initialization pattern
control for receiver</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRC33_17</name>
<description>32-bit CRC polynomial
configuration</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SSI</name>
<description>Internal SS signal input
level</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HDDIR</name>
<description>Rx/Tx direction at Half-duplex
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CSUSP</name>
<description>Master SUSPend request</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CSTART</name>
<description>Master transfer start</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MASRX</name>
<description>Master automatic SUSP in Receive
mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPE</name>
<description>Serial Peripheral Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSER</name>
<description>Number of data transfer extension to be
reload into TSIZE just when a previous</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TSIZE</name>
<description>Number of data at current
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFG1</name>
<displayName>CFG1</displayName>
<description>configuration register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00070007</resetValue>
<fields>
<field>
<name>MBR</name>
<description>Master baud rate</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CRCEN</name>
<description>Hardware CRC computation
enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCSIZE</name>
<description>Length of CRC frame to be transacted and
compared</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TXDMAEN</name>
<description>Tx DMA stream enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDMAEN</name>
<description>Rx DMA stream enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRDET</name>
<description>Detection of underrun condition at slave
transmitter</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UDRCFG</name>
<description>Behavior of slave transmitter at
underrun condition</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FTHVL</name>
<description>threshold level</description>
<bitOffset>5</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DSIZE</name>
<description>Number of bits in at single SPI data
frame</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFG2</name>
<displayName>CFG2</displayName>
<description>configuration register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFCNTR</name>
<description>Alternate function GPIOs
control</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSOM</name>
<description>SS output management in master
mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSOE</name>
<description>SS output enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSIOP</name>
<description>SS input/output polarity</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSM</name>
<description>Software management of SS signal
input</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFRST</name>
<description>Data frame format</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASTER</name>
<description>SPI Master</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SP</name>
<description>Serial Protocol</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>COMM</name>
<description>SPI Communication Mode</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IOSWP</name>
<description>Swap functionality of MISO and MOSI
pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MIDI</name>
<description>Master Inter-Data Idleness</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSSI</name>
<description>Master SS Idleness</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>Interrupt Enable Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSERFIE</name>
<description>Additional number of transactions reload
interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MODFIE</name>
<description>Mode Fault interrupt
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TIFREIE</name>
<description>TIFRE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRCEIE</name>
<description>CRC Interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OVRIE</name>
<description>OVR interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UDRIE</name>
<description>UDR interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXTFIE</name>
<description>TXTFIE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOTIE</name>
<description>EOT, SUSP and TXC interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DPXPIE</name>
<description>DXP interrupt enabled</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXPIE</name>
<description>TXP interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXPIE</name>
<description>RXP Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00001002</resetValue>
<fields>
<field>
<name>CTSIZE</name>
<description>Number of data frames remaining in
current TSIZE session</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>RXWNE</name>
<description>RxFIFO Word Not Empty</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXPLVL</name>
<description>RxFIFO Packing LeVeL</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TXC</name>
<description>TxFIFO transmission
complete</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUSP</name>
<description>SUSPend</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSERF</name>
<description>Additional number of SPI data to be
transacted was reload</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODF</name>
<description>Mode Fault</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIFRE</name>
<description>TI frame format error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCE</name>
<description>CRC Error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>Overrun</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>Underrun at slave transmission
mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXTF</name>
<description>Transmission Transfer
Filled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOT</name>
<description>End Of Transfer</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DXP</name>
<description>Duplex Packet</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXP</name>
<description>Tx-Packet space available</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXP</name>
<description>Rx-Packet available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>Interrupt/Status Flags Clear
Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SUSPC</name>
<description>SUSPend flag clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSERFC</name>
<description>TSERFC flag clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODFC</name>
<description>Mode Fault flag clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIFREC</name>
<description>TI frame format error flag
clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCEC</name>
<description>CRC Error flag clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRC</name>
<description>Overrun flag clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRC</name>
<description>Underrun flag clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXTFC</name>
<description>Transmission Transfer Filled flag
clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOTC</name>
<description>End Of Transfer flag clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXDR</name>
<displayName>TXDR</displayName>
<description>Transmit Data Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXDR</name>
<description>Transmit data register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXDR</name>
<displayName>RXDR</displayName>
<description>Receive Data Register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDR</name>
<description>Receive data register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCPOLY</name>
<displayName>CRCPOLY</displayName>
<description>Polynomial Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000107</resetValue>
<fields>
<field>
<name>CRCPOLY</name>
<description>CRC polynomial register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXCRC</name>
<displayName>TXCRC</displayName>
<description>Transmitter CRC Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXCRC</name>
<description>CRC register for
transmitter</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXCRC</name>
<displayName>RXCRC</displayName>
<description>Receiver CRC Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXCRC</name>
<description>CRC register for receiver</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>UDRDR</name>
<displayName>UDRDR</displayName>
<description>Underrun Data Register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UDRDR</name>
<description>Data at slave underrun
condition</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CGFR</name>
<displayName>CGFR</displayName>
<description>configuration register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCKOE</name>
<description>Master clock output enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODD</name>
<description>Odd factor for the
prescaler</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SDIV</name>
<description>I2S linear prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATFMT</name>
<description>Data format</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WSINV</name>
<description>Fixed channel length in
SLAVE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIXCH</name>
<description>Word select inversion</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKPOL</name>
<description>Serial audio clock
polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHLEN</name>
<description>Channel length (number of bits per audio
channel)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATLEN</name>
<description>Data length to be
transferred</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PCMSYNC</name>
<description>PCM frame synchronization</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2SSTD</name>
<description>I2S standard selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>I2SCFG</name>
<description>I2S configuration mode</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>I2SMOD</name>
<description>I2S mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI2</name>
<baseAddress>0x40003800</baseAddress>
<interrupt>
<name>SPI2</name>
<description>SPI2 global interrupt</description>
<value>36</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI3</name>
<baseAddress>0x40003C00</baseAddress>
<interrupt>
<name>SPI3</name>
<description>SPI3 global interrupt</description>
<value>51</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI4</name>
<baseAddress>0x40013400</baseAddress>
<interrupt>
<name>SPI4</name>
<description>SPI4 global interrupt</description>
<value>84</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI5</name>
<baseAddress>0x40015000</baseAddress>
<interrupt>
<name>SPI5</name>
<description>SPI5 global interrupt</description>
<value>85</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI6</name>
<baseAddress>0x58001400</baseAddress>
<interrupt>
<name>SPI6</name>
<description>SPI6 global interrupt</description>
<value>86</value>
</interrupt>
</peripheral>
<peripheral>
<name>STK</name>
<description>SysTick timer</description>
<groupName>STK</groupName>
<baseAddress>0xE000E010</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x11</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>SysTick control and status
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TICKINT</name>
<description>SysTick exception request
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSOURCE</name>
<description>Clock source selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTFLAG</name>
<description>COUNTFLAG</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RVR</name>
<displayName>RVR</displayName>
<description>SysTick reload value register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>RELOAD value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVR</name>
<displayName>CVR</displayName>
<description>SysTick current value register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>CURRENT</name>
<description>Current counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALIB</name>
<displayName>CALIB</displayName>
<description>SysTick calibration value
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>TENMS</name>
<description>Calibration value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>SKEW</name>
<description>SKEW flag: Indicates whether the TENMS
value is exact</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOREF</name>
<description>NOREF flag. Reads as zero</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SWPMI</name>
<description>Single Wire Protocol Master
Interface</description>
<groupName>SWPMI</groupName>
<baseAddress>0x40008800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MDIOS_WKUP</name>
<description>MDIOS wakeup</description>
<value>119</value>
</interrupt>
<interrupt>
<name>MDIOS</name>
<description>MDIOS global interrupt</description>
<value>120</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>SWPMI Configuration/Control
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDMA</name>
<description>Reception DMA enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDMA</name>
<description>Transmission DMA enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXMODE</name>
<description>Reception buffering mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXMODE</name>
<description>Transmission buffering
mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPBK</name>
<description>Loopback mode enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWPACT</name>
<description>Single wire protocol master interface
activate</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEACT</name>
<description>Single wire protocol master interface
deactivate</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWPTEN</name>
<description>Single wire protocol master transceiver
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>SWPMI Bitrate register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>BR</name>
<description>Bitrate prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>SWPMI Interrupt and Status
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x000002C2</resetValue>
<fields>
<field>
<name>RXBFF</name>
<description>Receive buffer full flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXBEF</name>
<description>Transmit buffer empty flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBERF</name>
<description>Receive CRC error flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVRF</name>
<description>Receive overrun error flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUNRF</name>
<description>Transmit underrun error
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>Receive data register not
empty</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>Transmit data register
empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCF</name>
<description>Transfer complete flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRF</name>
<description>Slave resume flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUSP</name>
<description>SUSPEND flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEACTF</name>
<description>DEACTIVATED flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDYF</name>
<description>transceiver ready flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>SWPMI Interrupt Flag Clear
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRXBFF</name>
<description>Clear receive buffer full
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTXBEF</name>
<description>Clear transmit buffer empty
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRXBERF</name>
<description>Clear receive CRC error
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRXOVRF</name>
<description>Clear receive overrun error
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTXUNRF</name>
<description>Clear transmit underrun error
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCF</name>
<description>Clear transfer complete
flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSRF</name>
<description>Clear slave resume flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRDYF</name>
<description>Clear transceiver ready
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>SWPMI Interrupt Enable
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXBFIE</name>
<description>Receive buffer full interrupt
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXBEIE</name>
<description>Transmit buffer empty interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXBERIE</name>
<description>Receive CRC error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOVRIE</name>
<description>Receive overrun error interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUNRIE</name>
<description>Transmit underrun error interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RIE</name>
<description>Receive interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Transmit interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmit complete interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRIE</name>
<description>Slave resume interrupt
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDYIE</name>
<description>Transceiver ready interrupt
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RFL</name>
<displayName>RFL</displayName>
<description>SWPMI Receive Frame Length
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RFL</name>
<description>Receive frame length</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>SWPMI Transmit data register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TD</name>
<description>Transmit data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>SWPMI Receive data register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RD</name>
<description>received data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>SWPMI Option register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWP_TBYP</name>
<description>SWP transceiver bypass</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWP_CLASS</name>
<description>SWP class selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCFG</name>
<description>System configuration controller</description>
<groupName>SYSCFG</groupName>
<baseAddress>0x58000400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPUART</name>
<description>LPUART global interrupt</description>
<value>142</value>
</interrupt>
<registers>
<register>
<name>PMCR</name>
<displayName>PMCR</displayName>
<description>peripheral mode configuration
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2C1FMP</name>
<description>I2C1 Fm+</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C2FMP</name>
<description>I2C2 Fm+</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C3FMP</name>
<description>I2C3 Fm+</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C4FMP</name>
<description>I2C4 Fm+</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB6FMP</name>
<description>PB(6) Fm+</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB7FMP</name>
<description>PB(7) Fast Mode Plus</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB8FMP</name>
<description>PB(8) Fast Mode Plus</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PB9FMP</name>
<description>PB(9) Fm+</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOOSTE</name>
<description>Booster Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPIS</name>
<description>Ethernet PHY Interface
Selection</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PA0SO</name>
<description>PA0 Switch Open</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PA1SO</name>
<description>PA1 Switch Open</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC2SO</name>
<description>PC2 Switch Open</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC3SO</name>
<description>PC3 Switch Open</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR1</name>
<displayName>EXTICR1</displayName>
<description>external interrupt configuration register
1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTI3</name>
<description>EXTI x configuration (x = 0 to
3)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI2</name>
<description>EXTI x configuration (x = 0 to
3)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI1</name>
<description>EXTI x configuration (x = 0 to
3)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI0</name>
<description>EXTI x configuration (x = 0 to
3)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR2</name>
<displayName>EXTICR2</displayName>
<description>external interrupt configuration register
2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTI7</name>
<description>EXTI x configuration (x = 4 to
7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI6</name>
<description>EXTI x configuration (x = 4 to
7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI5</name>
<description>EXTI x configuration (x = 4 to
7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI4</name>
<description>EXTI x configuration (x = 4 to
7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR3</name>
<displayName>EXTICR3</displayName>
<description>external interrupt configuration register
3</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTI11</name>
<description>EXTI x configuration (x = 8 to
11)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI10</name>
<description>EXTI10</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI9</name>
<description>EXTI x configuration (x = 8 to
11)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI8</name>
<description>EXTI x configuration (x = 8 to
11)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR4</name>
<displayName>EXTICR4</displayName>
<description>external interrupt configuration register
4</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTI15</name>
<description>EXTI x configuration (x = 12 to
15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI14</name>
<description>EXTI x configuration (x = 12 to
15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI13</name>
<description>EXTI x configuration (x = 12 to
15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI12</name>
<description>EXTI x configuration (x = 12 to
15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCCSR</name>
<displayName>CCCSR</displayName>
<description>compensation cell control/status
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN</name>
<description>enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS</name>
<description>Code selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>READY</name>
<description>Compensation cell ready
flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSLV</name>
<description>High-speed at low-voltage</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCVR</name>
<displayName>CCVR</displayName>
<description>SYSCFG compensation cell value
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NCV</name>
<description>NMOS compensation value</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PCV</name>
<description>PMOS compensation value</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCCR</name>
<displayName>CCCR</displayName>
<description>SYSCFG compensation cell code
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NCC</name>
<description>NMOS compensation code</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PCC</name>
<description>PMOS compensation code</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_BRK_LOCKUPR</name>
<displayName>SYSCFG_BRK_LOCKUPR</displayName>
<description>SYSCFG timer break lockup
register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PVDL</name>
<description>PVD lock enable bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASHL</name>
<description>Flash double ECC error lock
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CM7L</name>
<description>
Cortex®-M7
LOCKUP (HardFault) output enable bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTCML</name>
<description>D1TCM or D0TCM double ECC error signal
lock</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITCML</name>
<description>ITCM double ECC error signal
lock</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM1</name>
<description>Advanced-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM1_BRK</name>
<description>TIM1 break interrupt</description>
<value>24</value>
</interrupt>
<interrupt>
<name>TIM1_UP</name>
<description>TIM1 update interrupt</description>
<value>25</value>
</interrupt>
<interrupt>
<name>TIM1_TRG_COM</name>
<description>TIM1 trigger and commutation</description>
<value>26</value>
</interrupt>
<interrupt>
<name>TIM1_CC</name>
<description>TIM1 capture / compare</description>
<value>27</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>MMS2</name>
<description>Master mode selection 2</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OIS6</name>
<description>Output Idle state 6</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS5</name>
<description>Output Idle state 5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS4</name>
<description>Output Idle state 4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3N</name>
<description>Output Idle state 3</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3</name>
<description>Output Idle state 3</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2N</name>
<description>Output Idle state 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2</name>
<description>Output Idle state 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update
selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded
control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMS_3</name>
<description>Slave mode selection - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS_4_3</name>
<description>Trigger selection - bit
4:3</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC6IF</name>
<description>Compare 6 interrupt flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5IF</name>
<description>Compare 5 interrupt flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBIF</name>
<description>System Break interrupt
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture
flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2IF</name>
<description>Break 2 interrupt flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3
generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4
generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update
generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2G</name>
<description>Break 2 generation</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1CE</name>
<description>Output Compare 1 clear
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>Output Compare 2 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>Output Compare 2 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>Output Compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2CE</name>
<description>Output Compare 2 clear
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode - bit
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC2PCS</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ICPCS</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC3S</name>
<description>Capture/Compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>Output compare 3 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>Output compare 3 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>Output compare 3 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3CE</name>
<description>Output compare 3 clear
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>Output compare 4 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>Output compare 4 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>Output compare 4 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4CE</name>
<description>Output compare 4 clear
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M_3</name>
<description>Output Compare 3 mode - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M_4</name>
<description>Output Compare 4 mode - bit
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NE</name>
<description>Capture/Compare 2 complementary output
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NE</name>
<description>Capture/Compare 3 complementary output
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 complementary output
polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5E</name>
<description>Capture/Compare 5 output
enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5P</name>
<description>Capture/Compare 5 output
polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6E</name>
<description>Capture/Compare 6 output
enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6P</name>
<description>Capture/Compare 6 output
polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2</name>
<description>Capture/Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>capture/compare register 3</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR3</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR4</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle
mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BK2F</name>
<description>Break 2 filter</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BK2E</name>
<description>Break 2 enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2P</name>
<description>Break 2 polarity</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR3_Output</name>
<displayName>CCMR3_Output</displayName>
<description>capture/compare mode register 3 (output
mode)</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OC5FE</name>
<description>Output compare 5 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5PE</name>
<description>Output compare 5 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M</name>
<description>Output compare 5 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC5CE</name>
<description>Output compare 5 clear
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6FE</name>
<description>Output compare 6 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6PE</name>
<description>Output compare 6 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6M</name>
<description>Output compare 6 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC6CE</name>
<description>Output compare 6 clear
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M3</name>
<description>Output Compare 5 mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6M3</name>
<description>Output Compare 6 mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>capture/compare register 5</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CCR5</name>
<description>Capture/Compare 5 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GC5C1</name>
<description>Group Channel 5 and Channel
1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C2</name>
<description>Group Channel 5 and Channel
2</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C3</name>
<description>Group Channel 5 and Channel
3</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRR6</name>
<displayName>CRR6</displayName>
<description>capture/compare register 6</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CCR6</name>
<description>Capture/Compare 6 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>TIM1 alternate function option register
1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDF1BK0E</name>
<description>BRK dfsdm1_break[0] enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETRSEL</name>
<description>ETR source selection</description>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF2</name>
<displayName>AF2</displayName>
<description>TIM1 Alternate function odfsdm1_breakster
2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BK2INE</name>
<description>BRK2 BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1E</name>
<description>BRK2 COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2E</name>
<description>BRK2 COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2DF1BK1E</name>
<description>BRK2 dfsdm1_break[1]
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2INP</name>
<description>BRK2 BKIN2 input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1P</name>
<description>BRK2 COMP1 input polarit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2P</name>
<description>BRK2 COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>TIM1 timer input selection
register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>selects TI1[0] to TI1[15]
input</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI2SEL</name>
<description>selects TI2[0] to TI2[15]
input</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI3SEL</name>
<description>selects TI3[0] to TI3[15]
input</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI4SEL</name>
<description>selects TI4[0] to TI4[15]
input</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM2</name>
<description>General purpose timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM2</name>
<description>TIM2 global interrupt</description>
<value>28</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TS_4_3</name>
<description>Trigger selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SMS_3</name>
<description>Slave mode selection - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture
flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4
generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3
generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>CC1S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>OC1FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>OC1PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>OC1M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1CE</name>
<description>OC1CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>OC2FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>OC2PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>OC2M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2CE</name>
<description>OC2CE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode - bit
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC2PCS</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ICPCS</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4M_3</name>
<description>Output Compare 2 mode - bit
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M_3</name>
<description>Output Compare 1 mode - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4CE</name>
<description>OC4CE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>OC4M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>OC4PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>OC4FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>CC4S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3CE</name>
<description>OC3CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>OC3M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>OC3PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>OC3FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>CC3S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 output
Polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L</name>
<description>low counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H</name>
<description>High counter value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR_H</name>
<description>High Auto-reload value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ARR_L</name>
<description>Low Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1_H</name>
<description>High Capture/Compare 1
value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR1_L</name>
<description>Low Capture/Compare 1
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2_H</name>
<description>High Capture/Compare 2
value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR2_L</name>
<description>Low Capture/Compare 2
value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>capture/compare register 3</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR3_H</name>
<description>High Capture/Compare value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR3_L</name>
<description>Low Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR4_H</name>
<description>High Capture/Compare value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR4_L</name>
<description>Low Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>TIM alternate function option register
1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ETRSEL</name>
<description>ETR source selection</description>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>TIM timer input selection
register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>TI1[0] to TI1[15] input
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI2SEL</name>
<description>TI2[0] to TI2[15] input
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI3SEL</name>
<description>TI3[0] to TI3[15] input
selection</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI4SEL</name>
<description>TI4[0] to TI4[15] input
selection</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM2">
<name>TIM3</name>
<baseAddress>0x40000400</baseAddress>
<interrupt>
<name>TIM3</name>
<description>TIM3 global interrupt</description>
<value>29</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="TIM2">
<name>TIM4</name>
<baseAddress>0x40000800</baseAddress>
<interrupt>
<name>TIM4</name>
<description>TIM4 global interrupt</description>
<value>30</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="TIM2">
<name>TIM5</name>
<baseAddress>0x40000C00</baseAddress>
<interrupt>
<name>TIM5</name>
<description>TIM5 global interrupt</description>
<value>50</value>
</interrupt>
<interrupt>
<name>SWPMI1</name>
<description>SWPMI global interrupt</description>
<value>115</value>
</interrupt>
</peripheral>
<peripheral>
<name>TIM6</name>
<description>Basic timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Low counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>UIFCPY</name>
<description>UIF Copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Low Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM6">
<name>TIM7</name>
<baseAddress>0x40001400</baseAddress>
</peripheral>
<peripheral>
<name>TIM8</name>
<description>Advanced-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40010400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM8_BRK_TIM12</name>
<description>TIM8 and 12 break global</description>
<value>43</value>
</interrupt>
<interrupt>
<name>TIM8_UP_TIM13</name>
<description>TIM8 and 13 update global</description>
<value>44</value>
</interrupt>
<interrupt>
<name>TIM8_TRG_COM_TIM14</name>
<description>TIM8 and 14 trigger /commutation and
global</description>
<value>45</value>
</interrupt>
<interrupt>
<name>TIM8_CC</name>
<description>TIM8 capture / compare</description>
<value>46</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMS2</name>
<description>Master mode selection 2</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OIS6</name>
<description>Output Idle state 6</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS5</name>
<description>Output Idle state 5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS4</name>
<description>Output Idle state 4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3N</name>
<description>Output Idle state 3</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3</name>
<description>Output Idle state 3</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2N</name>
<description>Output Idle state 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2</name>
<description>Output Idle state 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update
selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded
control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMS_3</name>
<description>Slave mode selection - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS_4_3</name>
<description>Trigger selection - bit
4:3</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC6IF</name>
<description>Compare 6 interrupt flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5IF</name>
<description>Compare 5 interrupt flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBIF</name>
<description>System Break interrupt
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture
flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2IF</name>
<description>Break 2 interrupt flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3
generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4
generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update
generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2G</name>
<description>Break 2 generation</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1CE</name>
<description>Output Compare 1 clear
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>Output Compare 2 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>Output Compare 2 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>Output Compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2CE</name>
<description>Output Compare 2 clear
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode - bit
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC2PCS</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ICPCS</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC3S</name>
<description>Capture/Compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>Output compare 3 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>Output compare 3 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>Output compare 3 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3CE</name>
<description>Output compare 3 clear
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>Output compare 4 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>Output compare 4 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>Output compare 4 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4CE</name>
<description>Output compare 4 clear
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M_3</name>
<description>Output Compare 3 mode - bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M_4</name>
<description>Output Compare 4 mode - bit
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NE</name>
<description>Capture/Compare 2 complementary output
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NE</name>
<description>Capture/Compare 3 complementary output
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 complementary output
polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5E</name>
<description>Capture/Compare 5 output
enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5P</name>
<description>Capture/Compare 5 output
polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6E</name>
<description>Capture/Compare 6 output
enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6P</name>
<description>Capture/Compare 6 output
polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2</name>
<description>Capture/Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>capture/compare register 3</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR3</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR4</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle
mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BK2F</name>
<description>Break 2 filter</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BK2E</name>
<description>Break 2 enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2P</name>
<description>Break 2 polarity</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR3_Output</name>
<displayName>CCMR3_Output</displayName>
<description>capture/compare mode register 3 (output
mode)</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC5FE</name>
<description>Output compare 5 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5PE</name>
<description>Output compare 5 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M</name>
<description>Output compare 5 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC5CE</name>
<description>Output compare 5 clear
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6FE</name>
<description>Output compare 6 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6PE</name>
<description>Output compare 6 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6M</name>
<description>Output compare 6 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC6CE</name>
<description>Output compare 6 clear
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M3</name>
<description>Output Compare 5 mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6M3</name>
<description>Output Compare 6 mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>capture/compare register 5</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR5</name>
<description>Capture/Compare 5 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GC5C1</name>
<description>Group Channel 5 and Channel
1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C2</name>
<description>Group Channel 5 and Channel
2</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C3</name>
<description>Group Channel 5 and Channel
3</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRR6</name>
<displayName>CRR6</displayName>
<description>capture/compare register 6</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR6</name>
<description>Capture/Compare 6 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>TIM1 alternate function option register
1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDF1BK0E</name>
<description>BRK dfsdm1_break[0] enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETRSEL</name>
<description>ETR source selection</description>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF2</name>
<displayName>AF2</displayName>
<description>TIM1 Alternate function odfsdm1_breakster
2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BK2INE</name>
<description>BRK2 BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1E</name>
<description>BRK2 COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2E</name>
<description>BRK2 COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2DF1BK1E</name>
<description>BRK2 dfsdm1_break[1]
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2INP</name>
<description>BRK2 BKIN2 input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1P</name>
<description>BRK2 COMP1 input polarit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2P</name>
<description>BRK2 COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>TIM1 timer input selection
register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>selects TI1[0] to TI1[15]
input</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI2SEL</name>
<description>selects TI2[0] to TI2[15]
input</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI3SEL</name>
<description>selects TI3[0] to TI3[15]
input</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI4SEL</name>
<description>selects TI4[0] to TI4[15]
input</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM2">
<name>TIM12</name>
<baseAddress>0x40001800</baseAddress>
</peripheral>
<peripheral derivedFrom="TIM2">
<name>TIM13</name>
<baseAddress>0x40001C00</baseAddress>
</peripheral>
<peripheral derivedFrom="TIM2">
<name>TIM14</name>
<baseAddress>0x40002000</baseAddress>
</peripheral>
<peripheral>
<name>TIM15</name>
<description>General purpose timers</description>
<groupName>TIMs</groupName>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM16</name>
<description>TIM16 global interrupt</description>
<value>117</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded
control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update
selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2</name>
<description>Output Idle state 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TS_2_0</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMS_3</name>
<description>Slave mode selection bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS_4_3</name>
<description>Trigger selection - bit
4:3</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update
generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>Output Compare 2 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>Output Compare 2 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>Output Compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode bit
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode bit
3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2</name>
<description>Capture/Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle
mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>TIM15 alternate fdfsdm1_breakon register
1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDF1BK0E</name>
<description>BRK dfsdm1_break[0] enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>TIM15 input selection register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>selects TI1[0] to TI1[15]
input</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TI2SEL</name>
<description>selects TI2[0] to TI2[15]
input</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM16</name>
<description>General-purpose-timers</description>
<groupName>TIMs</groupName>
<baseAddress>0x40014400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update
selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded
control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update
generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF Copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle
mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM16_AF1</name>
<displayName>TIM16_AF1</displayName>
<description>TIM16 alternate function register
1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDFBK1E</name>
<description>BRK dfsdm1_break[1] enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM16_TISEL</name>
<displayName>TIM16_TISEL</displayName>
<description>TIM16 input selection register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>selects TI1[0] to TI1[15]
input</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM17</name>
<description>General-purpose-timers</description>
<groupName>TIMs</groupName>
<baseAddress>0x40014800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DFSDM1_FLT0</name>
<description>DFSDM1 filter 0 interrupt</description>
<value>110</value>
</interrupt>
<interrupt>
<name>DFSDM1_FLT1</name>
<description>DFSDM1 filter 1 interrupt</description>
<value>111</value>
</interrupt>
<interrupt>
<name>DFSDM1_FLT2</name>
<description>DFSDM1 filter 2 interrupt</description>
<value>112</value>
</interrupt>
<interrupt>
<name>DFSDM1_FLT3</name>
<description>DFSDM1 filter 3 interrupt</description>
<value>113</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update
selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded
control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update
generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF Copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle
mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM17_AF1</name>
<displayName>TIM17_AF1</displayName>
<description>TIM17 alternate function register
1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDFBK1E</name>
<description>BRK dfsdm1_break[1] enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIM17_TISEL</name>
<displayName>TIM17_TISEL</displayName>
<description>TIM17 input selection register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>selects TI1[0] to TI1[15]
input</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TT_FDCAN</name>
<description>FDCAN1</description>
<groupName>FDCAN</groupName>
<baseAddress>0x4000A000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>FDCAN_CREL</name>
<displayName>FDCAN_CREL</displayName>
<description>FDCAN Core Release Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x32141218</resetValue>
<fields>
<field>
<name>REL</name>
<description>Core release</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STEP</name>
<description>Step of Core release</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SUBSTEP</name>
<description>Sub-step of Core release</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>YEAR</name>
<description>Timestamp Year</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MON</name>
<description>Timestamp Month</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DAY</name>
<description>Timestamp Day</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ENDN</name>
<displayName>FDCAN_ENDN</displayName>
<description>FDCAN Core Release Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x87654321</resetValue>
<fields>
<field>
<name>ETV</name>
<description>Endiannes Test Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_DBTP</name>
<displayName>FDCAN_DBTP</displayName>
<description>FDCAN Data Bit Timing and Prescaler
Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000A33</resetValue>
<fields>
<field>
<name>DSJW</name>
<description>Synchronization Jump Width</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTSEG2</name>
<description>Data time segment after sample
point</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTSEG1</name>
<description>Data time segment after sample
point</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBRP</name>
<description>Data BIt Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TDC</name>
<description>Transceiver Delay
Compensation</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TEST</name>
<displayName>FDCAN_TEST</displayName>
<description>FDCAN Test Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LBCK</name>
<description>Loop Back mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX</name>
<description>Loop Back mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX</name>
<description>Control of Transmit Pin</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RWD</name>
<displayName>FDCAN_RWD</displayName>
<description>FDCAN RAM Watchdog Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDV</name>
<description>Watchdog value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WDC</name>
<description>Watchdog configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_CCCR</name>
<displayName>FDCAN_CCCR</displayName>
<description>FDCAN CC Control Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>INIT</name>
<description>Initialization</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCE</name>
<description>Configuration Change
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASM</name>
<description>ASM Restricted Operation
Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSA</name>
<description>Clock Stop Acknowledge</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSR</name>
<description>Clock Stop Request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MON</name>
<description>Bus Monitoring Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAR</name>
<description>Disable Automatic
Retransmission</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEST</name>
<description>Test Mode Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FDOE</name>
<description>FD Operation Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSE</name>
<description>FDCAN Bit Rate Switching</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXHD</name>
<description>Protocol Exception Handling
Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EFBI</name>
<description>Edge Filtering during Bus
Integration</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXP</name>
<description>TXP</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NISO</name>
<description>Non ISO Operation</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NBTP</name>
<displayName>FDCAN_NBTP</displayName>
<description>FDCAN Nominal Bit Timing and Prescaler
Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000A33</resetValue>
<fields>
<field>
<name>NSJW</name>
<description>NSJW: Nominal (Re)Synchronization Jump
Width</description>
<bitOffset>25</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>NBRP</name>
<description>Bit Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>NTSEG1</name>
<description>Nominal Time segment before sample
point</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TSEG2</name>
<description>Nominal Time segment after sample
point</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TSCC</name>
<displayName>FDCAN_TSCC</displayName>
<description>FDCAN Timestamp Counter Configuration
Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TCP</name>
<description>Timestamp Counter
Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TSS</name>
<description>Timestamp Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TSCV</name>
<displayName>FDCAN_TSCV</displayName>
<description>FDCAN Timestamp Counter Value
Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSC</name>
<description>Timestamp Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TOCC</name>
<displayName>FDCAN_TOCC</displayName>
<description>FDCAN Timeout Counter Configuration
Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFF0000</resetValue>
<fields>
<field>
<name>ETOC</name>
<description>Enable Timeout Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOS</name>
<description>Timeout Select</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TOP</name>
<description>Timeout Period</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TOCV</name>
<displayName>FDCAN_TOCV</displayName>
<description>FDCAN Timeout Counter Value
Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>TOC</name>
<description>Timeout Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ECR</name>
<displayName>FDCAN_ECR</displayName>
<description>FDCAN Error Counter Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEL</name>
<description>AN Error Logging</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RP</name>
<description>Receive Error Passive</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TREC</name>
<description>Receive Error Counter</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TEC</name>
<description>Transmit Error Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_PSR</name>
<displayName>FDCAN_PSR</displayName>
<description>FDCAN Protocol Status Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000707</resetValue>
<fields>
<field>
<name>LEC</name>
<description>Last Error Code</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ACT</name>
<description>Activity</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EP</name>
<description>Error Passive</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>Warning Status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>Bus_Off Status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLEC</name>
<description>Data Last Error Code</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RESI</name>
<description>ESI flag of last received FDCAN
Message</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBRS</name>
<description>BRS flag of last received FDCAN
Message</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REDL</name>
<description>Received FDCAN Message</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PXE</name>
<description>Protocol Exception Event</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDCV</name>
<description>Transmitter Delay Compensation
Value</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TDCR</name>
<displayName>FDCAN_TDCR</displayName>
<description>FDCAN Transmitter Delay Compensation
Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDCF</name>
<description>Transmitter Delay Compensation Filter
Window Length</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TDCO</name>
<description>Transmitter Delay Compensation
Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_IR</name>
<displayName>FDCAN_IR</displayName>
<description>FDCAN Interrupt Register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0N</name>
<description>Rx FIFO 0 New Message</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0W</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0F</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>Rx FIFO 0 Message Lost</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1N</name>
<description>Rx FIFO 1 New Message</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1W</name>
<description>Rx FIFO 1 Watermark
Reached</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1F</name>
<description>Rx FIFO 1 Watermark
Reached</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>Rx FIFO 1 Message Lost</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPM</name>
<description>High Priority Message</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>Transmission Completed</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCF</name>
<description>Transmission Cancellation
Finished</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEF</name>
<description>Tx FIFO Empty</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFN</name>
<description>Tx Event FIFO New Entry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFW</name>
<description>Tx Event FIFO Watermark
Reached</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFF</name>
<description>Tx Event FIFO Full</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx Event FIFO Element Lost</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSW</name>
<description>Timestamp Wraparound</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAF</name>
<description>Message RAM Access Failure</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOO</name>
<description>Timeout Occurred</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRX</name>
<description>Message stored to Dedicated Rx
Buffer</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELO</name>
<description>Error Logging Overflow</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP</name>
<description>Error Passive</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EW</name>
<description>Warning Status</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BO</name>
<description>Bus_Off Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDI</name>
<description>Watchdog Interrupt</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEA</name>
<description>Protocol Error in Arbitration Phase
(Nominal Bit Time is used)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PED</name>
<description>Protocol Error in Data Phase (Data Bit
Time is used)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARA</name>
<description>Access to Reserved Address</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_IE</name>
<displayName>FDCAN_IE</displayName>
<description>FDCAN Interrupt Enable
Register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0NE</name>
<description>Rx FIFO 0 New Message
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0WE</name>
<description>Rx FIFO 0 Full Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FE</name>
<description>Rx FIFO 0 Full Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LE</name>
<description>Rx FIFO 0 Message Lost
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NE</name>
<description>Rx FIFO 1 New Message
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1WE</name>
<description>Rx FIFO 1 Watermark Reached
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FE</name>
<description>Rx FIFO 1 Watermark Reached
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LE</name>
<description>Rx FIFO 1 Message Lost
Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPME</name>
<description>High Priority Message
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCE</name>
<description>Transmission Completed
Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFE</name>
<description>Transmission Cancellation Finished
Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFE</name>
<description>Tx FIFO Empty Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNE</name>
<description>Tx Event FIFO New Entry
Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFWE</name>
<description>Tx Event FIFO Watermark Reached
Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFE</name>
<description>Tx Event FIFO Full Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLE</name>
<description>Tx Event FIFO Element Lost
Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWE</name>
<description>Timestamp Wraparound
Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFE</name>
<description>Message RAM Access Failure
Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOE</name>
<description>Timeout Occurred Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRXE</name>
<description>Message stored to Dedicated Rx Buffer
Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BECE</name>
<description>Bit Error Corrected Interrupt
Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BEUE</name>
<description>Bit Error Uncorrected Interrupt
Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOE</name>
<description>Error Logging Overflow
Enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPE</name>
<description>Error Passive Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWE</name>
<description>Warning Status Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOE</name>
<description>Bus_Off Status Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIE</name>
<description>Watchdog Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAE</name>
<description>Protocol Error in Arbitration Phase
Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDE</name>
<description>Protocol Error in Data Phase
Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAE</name>
<description>Access to Reserved Address
Enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ILS</name>
<displayName>FDCAN_ILS</displayName>
<description>FDCAN Interrupt Line Select
Register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RF0NL</name>
<description>Rx FIFO 0 New Message Interrupt
Line</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0WL</name>
<description>Rx FIFO 0 Watermark Reached Interrupt
Line</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0FL</name>
<description>Rx FIFO 0 Full Interrupt
Line</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0LL</name>
<description>Rx FIFO 0 Message Lost Interrupt
Line</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1NL</name>
<description>Rx FIFO 1 New Message Interrupt
Line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1WL</name>
<description>Rx FIFO 1 Watermark Reached Interrupt
Line</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1FL</name>
<description>Rx FIFO 1 Full Interrupt
Line</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1LL</name>
<description>Rx FIFO 1 Message Lost Interrupt
Line</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HPML</name>
<description>High Priority Message Interrupt
Line</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCL</name>
<description>Transmission Completed Interrupt
Line</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCFL</name>
<description>Transmission Cancellation Finished
Interrupt Line</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx FIFO Empty Interrupt
Line</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFNL</name>
<description>Tx Event FIFO New Entry Interrupt
Line</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFWL</name>
<description>Tx Event FIFO Watermark Reached
Interrupt Line</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFFL</name>
<description>Tx Event FIFO Full Interrupt
Line</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFLL</name>
<description>Tx Event FIFO Element Lost Interrupt
Line</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSWL</name>
<description>Timestamp Wraparound Interrupt
Line</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRAFL</name>
<description>Message RAM Access Failure Interrupt
Line</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOOL</name>
<description>Timeout Occurred Interrupt
Line</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRXL</name>
<description>Message stored to Dedicated Rx Buffer
Interrupt Line</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BECL</name>
<description>Bit Error Corrected Interrupt
Line</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BEUL</name>
<description>Bit Error Uncorrected Interrupt
Line</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELOL</name>
<description>Error Logging Overflow Interrupt
Line</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPL</name>
<description>Error Passive Interrupt
Line</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWL</name>
<description>Warning Status Interrupt
Line</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOL</name>
<description>Bus_Off Status</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDIL</name>
<description>Watchdog Interrupt Line</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEAL</name>
<description>Protocol Error in Arbitration Phase
Line</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEDL</name>
<description>Protocol Error in Data Phase
Line</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARAL</name>
<description>Access to Reserved Address
Line</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_ILE</name>
<displayName>FDCAN_ILE</displayName>
<description>FDCAN Interrupt Line Enable
Register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EINT0</name>
<description>Enable Interrupt Line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EINT1</name>
<description>Enable Interrupt Line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_GFC</name>
<displayName>FDCAN_GFC</displayName>
<description>FDCAN Global Filter Configuration
Register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RRFE</name>
<description>Reject Remote Frames
Extended</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RRFS</name>
<description>Reject Remote Frames
Standard</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ANFE</name>
<description>Accept Non-matching Frames
Extended</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ANFS</name>
<description>Accept Non-matching Frames
Standard</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_SIDFC</name>
<displayName>FDCAN_SIDFC</displayName>
<description>FDCAN Standard ID Filter Configuration
Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLSSA</name>
<description>Filter List Standard Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>LSS</name>
<description>List Size Standard</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_XIDFC</name>
<displayName>FDCAN_XIDFC</displayName>
<description>FDCAN Extended ID Filter Configuration
Register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLESA</name>
<description>Filter List Standard Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>LSE</name>
<description>List Size Extended</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_XIDAM</name>
<displayName>FDCAN_XIDAM</displayName>
<description>FDCAN Extended ID and Mask
Register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EIDM</name>
<description>Extended ID Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_HPMS</name>
<displayName>FDCAN_HPMS</displayName>
<description>FDCAN High Priority Message Status
Register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BIDX</name>
<description>Buffer Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MSI</name>
<description>Message Storage Indicator</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FIDX</name>
<description>Filter Index</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FLST</name>
<description>Filter List</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NDAT1</name>
<displayName>FDCAN_NDAT1</displayName>
<description>FDCAN New Data 1 Register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ND0</name>
<description>New data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND1</name>
<description>New data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND2</name>
<description>New data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND3</name>
<description>New data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND4</name>
<description>New data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND5</name>
<description>New data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND6</name>
<description>New data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND7</name>
<description>New data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND8</name>
<description>New data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND9</name>
<description>New data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND10</name>
<description>New data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND11</name>
<description>New data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND12</name>
<description>New data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND13</name>
<description>New data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND14</name>
<description>New data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND15</name>
<description>New data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND16</name>
<description>New data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND17</name>
<description>New data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND18</name>
<description>New data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND19</name>
<description>New data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND20</name>
<description>New data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND21</name>
<description>New data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND22</name>
<description>New data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND23</name>
<description>New data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND24</name>
<description>New data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND25</name>
<description>New data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND26</name>
<description>New data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND27</name>
<description>New data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND28</name>
<description>New data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND29</name>
<description>New data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND30</name>
<description>New data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND31</name>
<description>New data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_NDAT2</name>
<displayName>FDCAN_NDAT2</displayName>
<description>FDCAN New Data 2 Register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ND32</name>
<description>New data</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND33</name>
<description>New data</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND34</name>
<description>New data</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND35</name>
<description>New data</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND36</name>
<description>New data</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND37</name>
<description>New data</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND38</name>
<description>New data</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND39</name>
<description>New data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND40</name>
<description>New data</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND41</name>
<description>New data</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND42</name>
<description>New data</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND43</name>
<description>New data</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND44</name>
<description>New data</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND45</name>
<description>New data</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND46</name>
<description>New data</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND47</name>
<description>New data</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND48</name>
<description>New data</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND49</name>
<description>New data</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND50</name>
<description>New data</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND51</name>
<description>New data</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND52</name>
<description>New data</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND53</name>
<description>New data</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND54</name>
<description>New data</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND55</name>
<description>New data</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND56</name>
<description>New data</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND57</name>
<description>New data</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND58</name>
<description>New data</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND59</name>
<description>New data</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND60</name>
<description>New data</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND61</name>
<description>New data</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND62</name>
<description>New data</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ND63</name>
<description>New data</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0C</name>
<displayName>FDCAN_RXF0C</displayName>
<description>FDCAN Rx FIFO 0 Configuration
Register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0SA</name>
<description>Rx FIFO 0 Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>F0S</name>
<description>Rx FIFO 0 Size</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>F0WM</name>
<description>FIFO 0 Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0S</name>
<displayName>FDCAN_RXF0S</displayName>
<description>FDCAN Rx FIFO 0 Status
Register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0FL</name>
<description>Rx FIFO 0 Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F0G</name>
<description>Rx FIFO 0 Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F0P</name>
<description>Rx FIFO 0 Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>F0F</name>
<description>Rx FIFO 0 Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF0L</name>
<description>Rx FIFO 0 Message Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF0A</name>
<displayName>FDCAN_RXF0A</displayName>
<description>CAN Rx FIFO 0 Acknowledge
Register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FA01</name>
<description>Rx FIFO 0 Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXBC</name>
<displayName>FDCAN_RXBC</displayName>
<description>FDCAN Rx Buffer Configuration
Register</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RBSA</name>
<description>Rx Buffer Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1C</name>
<displayName>FDCAN_RXF1C</displayName>
<description>FDCAN Rx FIFO 1 Configuration
Register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1SA</name>
<description>Rx FIFO 1 Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>F1S</name>
<description>Rx FIFO 1 Size</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1WM</name>
<description>Rx FIFO 1 Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1S</name>
<displayName>FDCAN_RXF1S</displayName>
<description>FDCAN Rx FIFO 1 Status
Register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1FL</name>
<description>Rx FIFO 1 Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1GI</name>
<description>Rx FIFO 1 Get Index</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1PI</name>
<description>Rx FIFO 1 Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>F1F</name>
<description>Rx FIFO 1 Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RF1L</name>
<description>Rx FIFO 1 Message Lost</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMS</name>
<description>Debug Message Status</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXF1A</name>
<displayName>FDCAN_RXF1A</displayName>
<description>FDCAN Rx FIFO 1 Acknowledge
Register</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F1AI</name>
<description>Rx FIFO 1 Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_RXESC</name>
<displayName>FDCAN_RXESC</displayName>
<description>FDCAN Rx Buffer Element Size Configuration
Register</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>F0DS</name>
<description>Rx FIFO 1 Data Field Size:</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>F1DS</name>
<description>Rx FIFO 0 Data Field Size:</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RBDS</name>
<description>Rx Buffer Data Field Size:</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBC</name>
<displayName>FDCAN_TXBC</displayName>
<description>FDCAN Tx Buffer Configuration
Register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBSA</name>
<description>Tx Buffers Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>NDTB</name>
<description>Number of Dedicated Transmit
Buffers</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFQS</name>
<description>Transmit FIFO/Queue Size</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFQM</name>
<description>Tx FIFO/Queue Mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXFQS</name>
<displayName>FDCAN_TXFQS</displayName>
<description>FDCAN Tx FIFO/Queue Status
Register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TFFL</name>
<description>Tx FIFO Free Level</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TFGI</name>
<description>TFGI</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TFQPI</name>
<description>Tx FIFO/Queue Put Index</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TFQF</name>
<description>Tx FIFO/Queue Full</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXESC</name>
<displayName>FDCAN_TXESC</displayName>
<description>FDCAN Tx Buffer Element Size Configuration
Register</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBDS</name>
<description>Tx Buffer Data Field Size:</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBRP</name>
<displayName>FDCAN_TXBRP</displayName>
<description>FDCAN Tx Buffer Request Pending
Register</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRP</name>
<description>Transmission Request
Pending</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBAR</name>
<displayName>FDCAN_TXBAR</displayName>
<description>FDCAN Tx Buffer Add Request
Register</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AR</name>
<description>Add Request</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCR</name>
<displayName>FDCAN_TXBCR</displayName>
<description>FDCAN Tx Buffer Cancellation Request
Register</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CR</name>
<description>Cancellation Request</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBTO</name>
<displayName>FDCAN_TXBTO</displayName>
<description>FDCAN Tx Buffer Transmission Occurred
Register</description>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TO</name>
<description>Transmission Occurred.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCF</name>
<displayName>FDCAN_TXBCF</displayName>
<description>FDCAN Tx Buffer Cancellation Finished
Register</description>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CF</name>
<description>Cancellation Finished</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBTIE</name>
<displayName>FDCAN_TXBTIE</displayName>
<description>FDCAN Tx Buffer Transmission Interrupt
Enable Register</description>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIE</name>
<description>Transmission Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXBCIE</name>
<displayName>FDCAN_TXBCIE</displayName>
<description>FDCAN Tx Buffer Cancellation Finished
Interrupt Enable Register</description>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CF</name>
<description>Cancellation Finished Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFC</name>
<displayName>FDCAN_TXEFC</displayName>
<description>FDCAN Tx Event FIFO Configuration
Register</description>
<addressOffset>0xF0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFSA</name>
<description>Event FIFO Start Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>EFS</name>
<description>Event FIFO Size</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>EFWM</name>
<description>Event FIFO Watermark</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFS</name>
<displayName>FDCAN_TXEFS</displayName>
<description>FDCAN Tx Event FIFO Status
Register</description>
<addressOffset>0xF4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFFL</name>
<description>Event FIFO Fill Level</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>EFGI</name>
<description>Event FIFO Get Index.</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>EFF</name>
<description>Event FIFO Full.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEFL</name>
<description>Tx Event FIFO Element
Lost.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TXEFA</name>
<displayName>FDCAN_TXEFA</displayName>
<description>FDCAN Tx Event FIFO Acknowledge
Register</description>
<addressOffset>0xF8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFAI</name>
<description>Event FIFO Acknowledge
Index</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTMC</name>
<displayName>FDCAN_TTTMC</displayName>
<description>FDCAN TT Trigger Memory Configuration
Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TMSA</name>
<description>Trigger Memory Start
Address</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>TME</name>
<description>Trigger Memory Elements</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTRMC</name>
<displayName>FDCAN_TTRMC</displayName>
<description>FDCAN TT Reference Message Configuration
Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RID</name>
<description>Reference Identifier.</description>
<bitOffset>0</bitOffset>
<bitWidth>29</bitWidth>
</field>
<field>
<name>XTD</name>
<description>Extended Identifier</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMPS</name>
<description>Reference Message Payload
Select</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOCF</name>
<displayName>FDCAN_TTOCF</displayName>
<description>FDCAN TT Operation Configuration
Register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010000</resetValue>
<fields>
<field>
<name>OM</name>
<description>Operation Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN</name>
<description>Gap Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TM</name>
<description>Time Master</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDSDL</name>
<description>LD of Synchronization Deviation
Limit</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IRTO</name>
<description>Initial Reference Trigger
Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>EECS</name>
<description>Enable External Clock
Synchronization</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWL</name>
<description>Application Watchdog Limit</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>EGTF</name>
<description>Enable Global Time
Filtering</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECC</name>
<description>Enable Clock Calibration</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVTP</name>
<description>Event Trigger Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTMLM</name>
<displayName>FDCAN_TTMLM</displayName>
<description>FDCAN TT Matrix Limits
Register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCM</name>
<description>Cycle Count Max</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CSS</name>
<description>Cycle Start
Synchronization</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TXEW</name>
<description>Tx Enable Window</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ENTT</name>
<description>Expected Number of Tx
Triggers</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TURCF</name>
<displayName>FDCAN_TURCF</displayName>
<description>FDCAN TUR Configuration
Register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NCL</name>
<description>Numerator Configuration
Low.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DC</name>
<description>Denominator Configuration.</description>
<bitOffset>16</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>ELT</name>
<description>Enable Local Time</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOCN</name>
<displayName>FDCAN_TTOCN</displayName>
<description>FDCAN TT Operation Control
Register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SGT</name>
<description>Set Global time</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECS</name>
<description>External Clock
Synchronization</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWP</name>
<description>Stop Watch Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWS</name>
<description>Stop Watch Source.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RTIE</name>
<description>Register Time Mark Interrupt Pulse
Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMC</name>
<description>Register Time Mark Compare</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TTIE</name>
<description>Trigger Time Mark Interrupt Pulse
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCS</name>
<description>Gap Control Select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FGP</name>
<description>Finish Gap.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMG</name>
<description>Time Mark Gap</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NIG</name>
<description>Next is Gap</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESCN</name>
<description>External Synchronization
Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCKC</name>
<description>TT Operation Control Register
Locked</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAN_TTGTP</name>
<displayName>CAN_TTGTP</displayName>
<description>FDCAN TT Global Time Preset
Register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NCL</name>
<description>Time Preset</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CTP</name>
<description>Cycle Time Target Phase</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTMK</name>
<displayName>FDCAN_TTTMK</displayName>
<description>FDCAN TT Time Mark Register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TM</name>
<description>Time Mark</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TICC</name>
<description>Time Mark Cycle Code</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>LCKM</name>
<description>TT Time Mark Register
Locked</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTIR</name>
<displayName>FDCAN_TTIR</displayName>
<description>FDCAN TT Interrupt Register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBC</name>
<description>Start of Basic Cycle</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMC</name>
<description>Start of Matrix Cycle</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSM</name>
<description>Change of Synchronization
Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOG</name>
<description>Start of Gap</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMI</name>
<description>Register Time Mark
Interrupt.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMI</name>
<description>Trigger Time Mark Event
Internal</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWE</name>
<description>Stop Watch Event</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTW</name>
<description>Global Time Wrap</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTD</name>
<description>Global Time Discontinuity</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTE</name>
<description>Global Time Error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXU</name>
<description>Tx Count Underflow</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXO</name>
<description>Tx Count Overflow</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1</name>
<description>Scheduling Error 1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2</name>
<description>Scheduling Error 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELC</name>
<description>Error Level Changed.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTG</name>
<description>Initialization Watch
Trigger</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WT</name>
<description>Watch Trigger</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AW</name>
<description>Application Watchdog</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CER</name>
<description>Configuration Error</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTIE</name>
<displayName>FDCAN_TTIE</displayName>
<description>FDCAN TT Interrupt Enable
Register</description>
<addressOffset>0x124</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBCE</name>
<description>Start of Basic Cycle Interrupt
Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMCE</name>
<description>Start of Matrix Cycle Interrupt
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSME</name>
<description>Change of Synchronization Mode Interrupt
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOGE</name>
<description>Start of Gap Interrupt
Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMIE</name>
<description>Register Time Mark Interrupt
Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMIE</name>
<description>Trigger Time Mark Event Internal
Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWEE</name>
<description>Stop Watch Event Interrupt
Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTWE</name>
<description>Global Time Wrap Interrupt
Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTDE</name>
<description>Global Time Discontinuity Interrupt
Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTEE</name>
<description>Global Time Error Interrupt
Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUE</name>
<description>Tx Count Underflow Interrupt
Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOE</name>
<description>Tx Count Overflow Interrupt
Enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1E</name>
<description>Scheduling Error 1 Interrupt
Enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2E</name>
<description>Scheduling Error 2 Interrupt
Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELCE</name>
<description>Change Error Level Interrupt
Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTGE</name>
<description>Initialization Watch Trigger Interrupt
Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WTE</name>
<description>Watch Trigger Interrupt
Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWE</name>
<description>Application Watchdog Interrupt
Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CERE</name>
<description>Configuration Error Interrupt
Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTILS</name>
<displayName>FDCAN_TTILS</displayName>
<description>FDCAN TT Interrupt Line Select
Register</description>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SBCL</name>
<description>Start of Basic Cycle Interrupt
Line</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMCL</name>
<description>Start of Matrix Cycle Interrupt
Line</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSML</name>
<description>Change of Synchronization Mode Interrupt
Line</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOGL</name>
<description>Start of Gap Interrupt
Line</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTMIL</name>
<description>Register Time Mark Interrupt
Line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTMIL</name>
<description>Trigger Time Mark Event Internal
Interrupt Line</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWEL</name>
<description>Stop Watch Event Interrupt
Line</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTWL</name>
<description>Global Time Wrap Interrupt
Line</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTDL</name>
<description>Global Time Discontinuity Interrupt
Line</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GTEL</name>
<description>Global Time Error Interrupt
Line</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXUL</name>
<description>Tx Count Underflow Interrupt
Line</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXOL</name>
<description>Tx Count Overflow Interrupt
Line</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE1L</name>
<description>Scheduling Error 1 Interrupt
Line</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SE2L</name>
<description>Scheduling Error 2 Interrupt
Line</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ELCL</name>
<description>Change Error Level Interrupt
Line</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWTGL</name>
<description>Initialization Watch Trigger Interrupt
Line</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WTL</name>
<description>Watch Trigger Interrupt
Line</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWL</name>
<description>Application Watchdog Interrupt
Line</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CERL</name>
<description>Configuration Error Interrupt
Line</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTOST</name>
<displayName>FDCAN_TTOST</displayName>
<description>FDCAN TT Operation Status
Register</description>
<addressOffset>0x12C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EL</name>
<description>Error Level</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MS</name>
<description>Master State.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYS</name>
<description>Synchronization State</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GTP</name>
<description>Quality of Global Time
Phase</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QCS</name>
<description>Quality of Clock Speed</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Reference Trigger Offset</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WGTD</name>
<description>Wait for Global Time
Discontinuity</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GFI</name>
<description>Gap Finished Indicator.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TMP</name>
<description>Time Master Priority</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GSI</name>
<description>Gap Started Indicator.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WFE</name>
<description>Wait for Event</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWE</name>
<description>Application Watchdog Event</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WECS</name>
<description>Wait for External Clock
Synchronization</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPL</name>
<description>Schedule Phase Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TURNA</name>
<displayName>FDCAN_TURNA</displayName>
<description>FDCAN TUR Numerator Actual
Register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NAV</name>
<description>Numerator Actual Value</description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTLGT</name>
<displayName>FDCAN_TTLGT</displayName>
<description>FDCAN TT Local and Global Time
Register</description>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LT</name>
<description>Local Time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GT</name>
<description>Global Time</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCTC</name>
<displayName>FDCAN_TTCTC</displayName>
<description>FDCAN TT Cycle Time and Count
Register</description>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CT</name>
<description>Cycle Time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CC</name>
<description>Cycle Count</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCPT</name>
<displayName>FDCAN_TTCPT</displayName>
<description>FDCAN TT Capture Time Register</description>
<addressOffset>0x13C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CT</name>
<description>Cycle Count Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SWV</name>
<description>Stop Watch Value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTCSM</name>
<displayName>FDCAN_TTCSM</displayName>
<description>FDCAN TT Cycle Sync Mark
Register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSM</name>
<description>Cycle Sync Mark</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FDCAN_TTTS</name>
<displayName>FDCAN_TTTS</displayName>
<description>FDCAN TT Trigger Select
Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWTDEL</name>
<description>Stop watch trigger input
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EVTSEL</name>
<description>Event trigger input
selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART4</name>
<description>Universal synchronous asynchronous receiver
transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40004C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART2</name>
<description>USART2 global interrupt</description>
<value>38</value>
</interrupt>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>37</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFIFO Full interrupt
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFIFO empty interrupt
enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFO mode enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>Word length</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBIE</name>
<description>End of Block interrupt
enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOIE</name>
<description>Receiver timeout interrupt
enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion
time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion
time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RTOEN</name>
<description>Receiver timeout enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD1</name>
<description>Auto baud rate mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD0</name>
<description>ABRMOD0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABREN</name>
<description>Auto baud rate enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level
inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level
inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDL</name>
<description>LIN break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address
Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_NSS</name>
<description>When the DSI_NSS bit is set, the NSS pin
input is ignored</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLVEN</name>
<description>Synchronous Slave mode
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFIFO threshold
configuration</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFIFO threshold interrupt
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>Receive FIFO threshold
configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TCBGTIE</name>
<description>Transmission Complete before guard time,
interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFIFO threshold interrupt
enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt
enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag
selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SCARCNT</name>
<description>Smartcard auto-retry count</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception
Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>One sample bit method
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRLP</name>
<description>Ir low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IREN</name>
<description>Ir mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BRR_4_15</name>
<description>DIV_Mantissa</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>BRR_0_3</name>
<description>DIV_Fraction</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush
request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFIFO threshold flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFIFO threshold flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGT</name>
<description>Transmission complete before guard time
flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFIFO Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFIFO Empty</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRF</name>
<description>ABRF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRE</name>
<description>ABRE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>SPI slave underrun error
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBF</name>
<description>EOBF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOF</name>
<description>RTOF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDF</name>
<description>LBDF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear
flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRCF</name>
<description>SPI slave underrun clear
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBCF</name>
<description>End of block clear flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOCF</name>
<description>Receiver timeout clear
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDCF</name>
<description>LIN break detection clear
flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGTC</name>
<description>Transmission complete before Guard time
clear flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear
flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFECF</name>
<description>TXFIFO empty clear flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>USART prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART5</name>
<description>Universal synchronous asynchronous receiver
transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40005000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART3</name>
<description>USART3 global interrupt</description>
<value>39</value>
</interrupt>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>37</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFIFO Full interrupt
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFIFO empty interrupt
enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFO mode enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>Word length</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBIE</name>
<description>End of Block interrupt
enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOIE</name>
<description>Receiver timeout interrupt
enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion
time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion
time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RTOEN</name>
<description>Receiver timeout enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD1</name>
<description>Auto baud rate mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD0</name>
<description>ABRMOD0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABREN</name>
<description>Auto baud rate enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level
inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level
inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDL</name>
<description>LIN break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address
Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_NSS</name>
<description>When the DSI_NSS bit is set, the NSS pin
input is ignored</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLVEN</name>
<description>Synchronous Slave mode
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFIFO threshold
configuration</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFIFO threshold interrupt
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>Receive FIFO threshold
configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TCBGTIE</name>
<description>Transmission Complete before guard time,
interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFIFO threshold interrupt
enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt
enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag
selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SCARCNT</name>
<description>Smartcard auto-retry count</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception
Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>One sample bit method
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRLP</name>
<description>Ir low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IREN</name>
<description>Ir mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BRR_4_15</name>
<description>DIV_Mantissa</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>BRR_0_3</name>
<description>DIV_Fraction</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush
request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFIFO threshold flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFIFO threshold flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGT</name>
<description>Transmission complete before guard time
flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFIFO Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFIFO Empty</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRF</name>
<description>ABRF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRE</name>
<description>ABRE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>SPI slave underrun error
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBF</name>
<description>EOBF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOF</name>
<description>RTOF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDF</name>
<description>LBDF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear
flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRCF</name>
<description>SPI slave underrun clear
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBCF</name>
<description>End of block clear flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOCF</name>
<description>Receiver timeout clear
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDCF</name>
<description>LIN break detection clear
flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGTC</name>
<description>Transmission complete before Guard time
clear flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear
flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFECF</name>
<description>TXFIFO empty clear flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>USART prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART7</name>
<description>Universal synchronous asynchronous receiver
transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40007800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART5</name>
<description>UART5 global interrupt</description>
<value>53</value>
</interrupt>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>37</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFIFO Full interrupt
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFIFO empty interrupt
enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFO mode enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>Word length</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBIE</name>
<description>End of Block interrupt
enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOIE</name>
<description>Receiver timeout interrupt
enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion
time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion
time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RTOEN</name>
<description>Receiver timeout enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD1</name>
<description>Auto baud rate mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD0</name>
<description>ABRMOD0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABREN</name>
<description>Auto baud rate enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level
inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level
inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDL</name>
<description>LIN break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address
Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_NSS</name>
<description>When the DSI_NSS bit is set, the NSS pin
input is ignored</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLVEN</name>
<description>Synchronous Slave mode
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFIFO threshold
configuration</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFIFO threshold interrupt
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>Receive FIFO threshold
configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TCBGTIE</name>
<description>Transmission Complete before guard time,
interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFIFO threshold interrupt
enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt
enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag
selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SCARCNT</name>
<description>Smartcard auto-retry count</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception
Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>One sample bit method
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRLP</name>
<description>Ir low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IREN</name>
<description>Ir mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BRR_4_15</name>
<description>DIV_Mantissa</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>BRR_0_3</name>
<description>DIV_Fraction</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush
request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFIFO threshold flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFIFO threshold flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGT</name>
<description>Transmission complete before guard time
flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFIFO Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFIFO Empty</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRF</name>
<description>ABRF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRE</name>
<description>ABRE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>SPI slave underrun error
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBF</name>
<description>EOBF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOF</name>
<description>RTOF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDF</name>
<description>LBDF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear
flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRCF</name>
<description>SPI slave underrun clear
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBCF</name>
<description>End of block clear flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOCF</name>
<description>Receiver timeout clear
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDCF</name>
<description>LIN break detection clear
flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGTC</name>
<description>Transmission complete before Guard time
clear flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear
flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFECF</name>
<description>TXFIFO empty clear flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>USART prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART8</name>
<description>Universal synchronous asynchronous receiver
transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40007C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART6</name>
<description>USART6 global interrupt</description>
<value>71</value>
</interrupt>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>37</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFIFO Full interrupt
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFIFO empty interrupt
enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFO mode enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>Word length</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBIE</name>
<description>End of Block interrupt
enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOIE</name>
<description>Receiver timeout interrupt
enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion
time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion
time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RTOEN</name>
<description>Receiver timeout enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD1</name>
<description>Auto baud rate mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD0</name>
<description>ABRMOD0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABREN</name>
<description>Auto baud rate enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level
inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level
inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDL</name>
<description>LIN break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address
Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_NSS</name>
<description>When the DSI_NSS bit is set, the NSS pin
input is ignored</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLVEN</name>
<description>Synchronous Slave mode
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFIFO threshold
configuration</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFIFO threshold interrupt
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>Receive FIFO threshold
configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TCBGTIE</name>
<description>Transmission Complete before guard time,
interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFIFO threshold interrupt
enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt
enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag
selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SCARCNT</name>
<description>Smartcard auto-retry count</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception
Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>One sample bit method
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRLP</name>
<description>Ir low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IREN</name>
<description>Ir mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BRR_4_15</name>
<description>DIV_Mantissa</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>BRR_0_3</name>
<description>DIV_Fraction</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush
request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFIFO threshold flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFIFO threshold flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGT</name>
<description>Transmission complete before guard time
flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFIFO Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFIFO Empty</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRF</name>
<description>ABRF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRE</name>
<description>ABRE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>SPI slave underrun error
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBF</name>
<description>EOBF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOF</name>
<description>RTOF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDF</name>
<description>LBDF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear
flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRCF</name>
<description>SPI slave underrun clear
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBCF</name>
<description>End of block clear flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOCF</name>
<description>Receiver timeout clear
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDCF</name>
<description>LIN break detection clear
flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGTC</name>
<description>Transmission complete before Guard time
clear flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear
flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFECF</name>
<description>TXFIFO empty clear flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>USART prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USART1</name>
<description>Universal synchronous asynchronous receiver
transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40011000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM17</name>
<description>TIM17 global interrupt</description>
<value>118</value>
</interrupt>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>37</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFIFO Full interrupt
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFIFO empty interrupt
enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFO mode enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>Word length</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBIE</name>
<description>End of Block interrupt
enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOIE</name>
<description>Receiver timeout interrupt
enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion
time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion
time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RTOEN</name>
<description>Receiver timeout enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD1</name>
<description>Auto baud rate mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD0</name>
<description>ABRMOD0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABREN</name>
<description>Auto baud rate enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level
inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level
inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDL</name>
<description>LIN break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address
Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_NSS</name>
<description>When the DSI_NSS bit is set, the NSS pin
input is ignored</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLVEN</name>
<description>Synchronous Slave mode
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFIFO threshold
configuration</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFIFO threshold interrupt
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>Receive FIFO threshold
configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TCBGTIE</name>
<description>Transmission Complete before guard time,
interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>TXFIFO threshold interrupt
enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt
enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag
selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SCARCNT</name>
<description>Smartcard auto-retry count</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity
selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception
Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>One sample bit method
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRLP</name>
<description>Ir low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IREN</name>
<description>Ir mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BRR_4_15</name>
<description>DIV_Mantissa</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>BRR_0_3</name>
<description>DIV_Fraction</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush
request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt &amp; status
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFIFO threshold flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFIFO threshold flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGT</name>
<description>Transmission complete before guard time
flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFIFO Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFIFO Empty</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRF</name>
<description>ABRF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRE</name>
<description>ABRE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>SPI slave underrun error
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBF</name>
<description>EOBF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOF</name>
<description>RTOF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDF</name>
<description>LBDF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear
flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRCF</name>
<description>SPI slave underrun clear
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBCF</name>
<description>End of block clear flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOCF</name>
<description>Receiver timeout clear
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDCF</name>
<description>LIN break detection clear
flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGTC</name>
<description>Transmission complete before Guard time
clear flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear
flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFECF</name>
<description>TXFIFO empty clear flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>USART prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART2</name>
<baseAddress>0x40004400</baseAddress>
<interrupt>
<name>TIM15</name>
<description>TIM15 global interrupt</description>
<value>116</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART3</name>
<baseAddress>0x40004800</baseAddress>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>37</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART6</name>
<baseAddress>0x40011400</baseAddress>
<interrupt>
<name>UART4</name>
<description>UART4 global interrupt</description>
<value>52</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART9</name>
<baseAddress>0x40011800</baseAddress>
<interrupt>
<name>UART7</name>
<description>UART7 global interrupt</description>
<value>82</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART10</name>
<baseAddress>0x40011C00</baseAddress>
<interrupt>
<name>UART8</name>
<description>UART8 global interrupt</description>
<value>83</value>
</interrupt>
</peripheral>
<peripheral>
<name>VREFBUF</name>
<description>VREFBUF</description>
<groupName>VREFBUF</groupName>
<baseAddress>0x58003C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>VREFBUF_CSR</name>
<displayName>VREFBUF_CSR</displayName>
<description>VREFBUF control and status
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>ENVR</name>
<description>Voltage reference buffer mode enable
This bit is used to enable the voltage reference
buffer mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HIZ</name>
<description>High impedance mode This bit controls
the analog switch to connect or not the VREF+ pin.
Refer to Table196: VREF buffer modes for the mode
descriptions depending on ENVR bit
configuration.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRR</name>
<description>Voltage reference buffer
ready</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>VRS</name>
<description>Voltage reference scale These bits
select the value generated by the voltage reference
buffer. Other: Reserved</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>VREFBUF_CCR</name>
<displayName>VREFBUF_CCR</displayName>
<description>VREFBUF calibration control
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRIM</name>
<description>Trimming code These bits are
automatically initialized after reset with the
trimming value stored in the Flash memory during the
production test. Writing into these bits allows to
tune the internal reference buffer
voltage.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDG</name>
<description>WWDG</description>
<groupName>WWDG</groupName>
<baseAddress>0x50003000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WWDG</name>
<description>Window Watchdog interrupt</description>
<value>0</value>
</interrupt>
<registers>
<register>
<name>WWDG_CR</name>
<displayName>WWDG_CR</displayName>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>T</name>
<description>7-bit counter (MSB to LSB) These bits
contain the value of the watchdog counter. It is
decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A
reset is produced when it is decremented from 0x40 to
0x3F (T6 becomes cleared).</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>WDGA</name>
<description>Activation bit This bit is set by
software and only cleared by hardware after a reset.
When WDGA=1, the watchdog can generate a
reset.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WWDG_CFR</name>
<displayName>WWDG_CFR</displayName>
<description>Configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>W</name>
<description>7-bit window value These bits contain
the window value to be compared to the
downcounter.</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>WDGTB</name>
<description>Timer base The time base of the
prescaler can be modified as follows:</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EWI</name>
<description>Early wakeup interrupt When set, an
interrupt occurs whenever the counter reaches the
value 0x40. This interrupt is only cleared by
hardware after a reset.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WWDG_SR</name>
<displayName>WWDG_SR</displayName>
<description>Status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EWIF</name>
<description>Early wakeup interrupt flag This bit is
set by hardware when the counter has reached the
value 0x40. It must be cleared by software by writing
0. A write of 1 has no effect. This bit is also set
if the interrupt is not enabled.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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