Add most recent params for FT24

Core/Inc/RTE_Components.h

@@ -24,7 +24,7 @@
 /* Defines ------------------------------------------------------------------*/
 /* STMicroelectronics.X-CUBE-AZRTOS-H7.3.0.0 */
 #define THREADX_ENABLED
-/* STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2 */
+/* STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0 */
 #define TOUCHGFX_APP
 
 #endif /* __RTE_COMPONENTS_H__ */

Core/Inc/params.h

@@ -10,17 +10,15 @@ extern "C" {
 
 #include "util.h"
 
-CountedEnum(ParamType, size_t, PF_BBAL, PF_SLIPREF, PF_MUMAX, PF_ASRP, PF_ASRON,
+CountedEnum(ParamType, size_t, PF_PLIM, PF_TLIM, PF_SLIM, PF_TVEC, PF_PG, PF_REKU);
-            PF_ASRI, PF_PLIM);
 
 typedef struct {
-  float bbal;
+  unsigned plim; //< Power limit
-  float slipref;
+  unsigned tlim; //< Torque limit
-  float mumax;
+  unsigned slim; //< Speed limit
-  unsigned asrp;
+  unsigned tvec; //< Torque vectoring
-  unsigned asri;
+  unsigned pg;   //< Power ground
-  unsigned asron;
+  unsigned reku; //< Rekuperation
-  unsigned plim;
 } Params;
 
 extern Params params;

Core/Inc/ui.h

@@ -7,7 +7,7 @@
 extern "C" {
 #endif
 
-#define NUM_BUTTONS 6
+#define NUM_BUTTONS 7
 #define NUM_ENCS 2
 #define BUTTON_MIN_INTERVAL 50  // ms
 #define ENC_MAX_PHASE 50        // ms

Core/Src/params.c

@@ -2,103 +2,98 @@
 #include "can-halal.h"
 #include "vehicle.h"
 
+/**
+ * Decrements the given value if it is above the minimum allowed value
+ */
+#define DEC_IF_ABOVE(param_val, min_val, decr_amt) ((param_val) = ((param_val) - (decr_amt) ) > (min_val) ? ((param_val) - (decr_amt)) : (min_val))
+#define INC_IF_BELOW(param_val, max_val, incr_amt) ((param_val) = ((param_val) + (incr_amt)) > (max_val) ? ((param_val) + (incr_amt)) : (max_val))
+
 Params params = {0};
 
-void params_init() {
+void params_init()
-  params.bbal = 50;
+{
+  // Default values
   params.plim = 20;
+  params.tlim = 1400;
+  params.slim = 70;
+  params.tvec = 50;
+  params.pg = 0;
+  params.reku = 0;
 }
 
-void params_inc(ParamType param) {
+void params_inc(ParamType param)
-  switch (param) {
+{
-  case PF_BBAL:
+  switch (param)
-    params.bbal += 0.5f;
+  {
-    if (params.bbal > 100.0f) {
-      params.bbal = 100.0f;
-    }
-    break;
-  case PF_SLIPREF:
-    params.slipref += 0.01f;
-    break;
-  case PF_MUMAX:
-    params.mumax += 0.1f;
-    break;
-  case PF_ASRP:
-    params.asrp++;
-    break;
-  case PF_ASRI:
-    params.asri++;
-    break;
-  case PF_ASRON:
-    params.asron = 1;
-    break;
   case PF_PLIM:
-    params.plim = (params.plim < 80) ? params.plim + 1 : 80;
+    INC_IF_BELOW(params.plim, 80, 1);
+    break;
+  case PF_TLIM:
+    INC_IF_BELOW(params.tlim, 1500, 100);
+    break;
+  case PF_SLIM:
+    INC_IF_BELOW(params.slim, 100, 1);
+    break;
+  case PF_TVEC:
+    INC_IF_BELOW(params.tvec, 100, 1);
+    break;
+  case PF_PG:
+    INC_IF_BELOW(params.pg, 100, 1);
+    break;
+  case PF_REKU:
+    INC_IF_BELOW(params.reku, 100, 1);
     break;
   }
 }
 
-void params_dec(ParamType param) {
+void params_dec(ParamType param)
-  switch (param) {
+{
-  case PF_BBAL:
+  switch (param)
-    params.bbal -= 0.5f;
+  {
-    if (params.bbal < 0.0f) {
-      params.bbal = 0.0f;
-    }
-    break;
-  case PF_SLIPREF:
-    if (params.slipref > 0) {
-      params.slipref -= 0.01f;
-    }
-    break;
-  case PF_MUMAX:
-    if (params.mumax > 0) {
-      params.mumax -= 0.1f;
-    }
-    break;
-  case PF_ASRP:
-    if (params.asrp > 0) {
-      params.asrp--;
-    }
-    break;
-  case PF_ASRI:
-    if (params.asri > 0) {
-      params.asri--;
-    }
-    break;
-  case PF_ASRON:
-    params.asron = 0;
-    break;
   case PF_PLIM:
-    params.plim = (params.plim > 2) ? params.plim - 1 : 2;
+    DEC_IF_ABOVE(params.plim, 0, 1);
+    break;
+  case PF_TLIM:
+    DEC_IF_ABOVE(params.tlim, 0, 100);
+    break;
+  case PF_SLIM:
+    DEC_IF_ABOVE(params.slim, 0, 1);
+    break;
+  case PF_TVEC:
+    DEC_IF_ABOVE(params.tvec, 0, 1);
+    break;
+  case PF_PG:
+    DEC_IF_ABOVE(params.pg, 0, 1);
+    break;
+  case PF_REKU:
+    DEC_IF_ABOVE(params.reku, 0, 1);
     break;
   }
 }
 
-void params_broadcast(ParamType param) {
+void params_broadcast(ParamType param)
+{
   int32_t value;
-  switch (param) {
+  switch (param)
-  case PF_BBAL:
+  {
-    value = params.bbal * 10;
-    break;
-  case PF_SLIPREF:
-    value = params.slipref * 100;
-    break;
-  case PF_MUMAX:
-    value = params.mumax * 10;
-    break;
-  case PF_ASRP:
-    value = params.asrp;
-    break;
-  case PF_ASRI:
-    value = params.asri;
-    break;
-  case PF_ASRON:
-    value = params.asron;
-    break;
   case PF_PLIM:
     value = params.plim;
     break;
+  case PF_TLIM:
+    value = params.tlim;
+    break;
+  case PF_SLIM:
+    value = params.slim;
+    break;
+  case PF_TVEC:
+    value = params.tvec;
+    break;
+  case PF_PG:
+    value = params.pg;
+    break;
+  case PF_REKU:
+    value = params.reku;
+    break;
   default:
     return;
   }

Core/Src/stm32h7xx_hal_msp.c

@@ -20,7 +20,6 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
-
 /* USER CODE BEGIN Includes */
 
 /* USER CODE END Includes */

Core/Src/ui.c

@@ -10,12 +10,18 @@
 #include "tx_api.h"
 #include "vehicle.h"
 
+#include "leds.h"
+
+#define DRS_BUTTON_IDX (6)
+#define DRS_PRESS_WAIT_CYCLES (10)
+static drs_press_buf_cycles = 0;
+
 void ui_thread_entry(ULONG _) {
   GPIO_TypeDef *button_ports[NUM_BUTTONS] = {BTN1_GPIO_Port, BTN2_GPIO_Port,
                                              BTN3_GPIO_Port, BTN4_GPIO_Port,
-                                             BTN5_GPIO_Port, BTN6_GPIO_Port};
+                                             BTN5_GPIO_Port, BTN6_GPIO_Port, SW_DRS_GPIO_Port};
   uint16_t button_pins[NUM_BUTTONS] = {BTN1_Pin, BTN2_Pin, BTN3_Pin,
-                                       BTN4_Pin, BTN5_Pin, BTN6_Pin};
+                                       BTN4_Pin, BTN5_Pin, BTN6_Pin, SW_DRS_Pin};
   GPIO_PinState button_states[NUM_BUTTONS] = {GPIO_PIN_RESET};
   uint32_t button_press_times[NUM_BUTTONS] = {HAL_GetTick()};
 
@@ -44,6 +50,17 @@ void ui_thread_entry(ULONG _) {
       tx_event_flags_set(&gui_update_events, GUI_UPDATE_NEXT_SCREEN, TX_OR);
     }
 
+    if (button_states[DRS_BUTTON_IDX] == GPIO_PIN_SET) {
+      // Set leftmost led to blue to indicate DRS activation
+      drs_press_buf_cycles = DRS_PRESS_WAIT_CYCLES;
+      led_set(0, 0, 0, 255);
+    } if (drs_press_buf_cycles < 0) {
+      // Assume no longer active, turn off
+      led_set(0, 0, 0, 0);
+    } else if (drs_press_buf_cycles >= 0) {
+      drs_press_buf_cycles--;
+    }
+
     vehicle_broadcast_buttons(button_states);
 
     // Release so other threads can get scheduled

Makefile

@@ -1,5 +1,5 @@
 ##########################################################################################################################
-# File automatically-generated by tool: [projectgenerator] version: [4.3.0-B58] date: [Sun Jul 21 12:04:39 CEST 2024] 
+# File automatically-generated by tool: [projectgenerator] version: [4.3.0-B58] date: [Sun Jul 21 18:35:39 CEST 2024] 
 ##########################################################################################################################
 
 # ------------------------------------------------

TouchGFX/App/app_touchgfx.c

@@ -2,7 +2,7 @@
   ******************************************************************************
   * File Name          : app_touchgfx.c
   ******************************************************************************
-  * This file was created by TouchGFX Generator 4.23.2. This file is only
+  * This file was created by TouchGFX Generator 4.24.0. This file is only
   * generated once! Delete this file from your project and re-generate code
   * using STM32CubeMX or change this file manually to update it.
   ******************************************************************************

TouchGFX/App/app_touchgfx.h

@@ -2,7 +2,7 @@
   ******************************************************************************
   * File Name          : app_touchgfx.h
   ******************************************************************************
-  * This file was created by TouchGFX Generator 4.23.2. This file is only
+  * This file was created by TouchGFX Generator 4.24.0. This file is only
   * generated once! Delete this file from your project and re-generate code
   * using STM32CubeMX or change this file manually to update it.
   ******************************************************************************

TouchGFX/ApplicationTemplate.touchgfx.part

@@ -26,5 +26,5 @@
     "AdditionalFeatures": [
     ]
   },
-  "Version": "4.23.2"
+  "Version": "4.24.0"
 }

TouchGFX/gui/src/common/NamedField.cpp

@@ -274,14 +274,12 @@ static_assert(sizeof(dataFieldDescs) / sizeof(dataFieldDescs[0]) ==
 #define PARAM_FIELD(FIELD) []() { return (void *)&params.FIELD; }
 
 NamedFieldDescription paramFieldDescs[] = {
-    [PF_BBAL] = {NamedFieldKind::Float, "BBAL", 2, 1, PARAM_FIELD(bbal)},
-    [PF_SLIPREF] = {NamedFieldKind::Float, "SLIPREF", 2, 2,
-                    PARAM_FIELD(slipref)},
-    [PF_MUMAX] = {NamedFieldKind::Float, "MUMAX", 2, 1, PARAM_FIELD(mumax)},
-    [PF_ASRP] = {NamedFieldKind::Int, "ASR-P", 2, 0, PARAM_FIELD(asrp)},
-    [PF_ASRON] = {NamedFieldKind::Int, "ASR-ON", 2, 0, PARAM_FIELD(asron)},
-    [PF_ASRI] = {NamedFieldKind::Int, "ASR-I", 2, 0, PARAM_FIELD(asri)},
     [PF_PLIM] = {NamedFieldKind::Int, "PLIM", 2, 0, PARAM_FIELD(plim)},
+    [PF_TLIM] = {NamedFieldKind::Int, "TLIM", 2, 1, PARAM_FIELD(plim)},
+    [PF_SLIM] = {NamedFieldKind::Int, "SLIM", 2, 2, PARAM_FIELD(slim)},
+    [PF_TVEC] = {NamedFieldKind::Int, "TVEC", 2, 1, PARAM_FIELD(tvec)},
+    [PF_PG] = {NamedFieldKind::Int, "PG", 2, 0, PARAM_FIELD(pg)},
+    [PF_REKU] = {NamedFieldKind::Int, "REKU", 2, 0, PARAM_FIELD(reku)},
 };
 
 static_assert(sizeof(paramFieldDescs) / sizeof(paramFieldDescs[0]) ==

TouchGFX/target/TouchGFXHAL.cpp

@@ -24,6 +24,9 @@
 
 /* USER CODE BEGIN TouchGFXHAL.cpp */
 
+#include "STWButtonController.hpp"
+STWButtonController stwBC;
+
 using namespace touchgfx;
 
 void TouchGFXHAL::initialize()
@@ -35,6 +38,7 @@ void TouchGFXHAL::initialize()
     // Please note, HAL::initialize() must be called to initialize the framework.
 
     TouchGFXGeneratedHAL::initialize();
+    setButtonController(&stwBC);
 }
 
 /**

TouchGFX/target/generated/OSWrappers.cpp

@@ -2,7 +2,7 @@
   ******************************************************************************
   * File Name          : OSWrappers.cpp
   ******************************************************************************
-  * This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
+  * This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
   ******************************************************************************
   * @attention
   *
@@ -16,7 +16,6 @@
   ******************************************************************************
   */
 
-#include <cassert>
 #include <touchgfx/hal/HAL.hpp>
 #include <touchgfx/hal/OSWrappers.hpp>
 
@@ -25,6 +24,8 @@
 #include "tx_api.h"
 #include "tx_byte_pool.h"
 
+#include <cassert>
+
 // tx_thread.h is not C++ compatible, declare used symbols here as externals
 extern "C" volatile UINT _tx_thread_preempt_disable;
 extern "C" VOID _tx_thread_system_preempt_check(VOID);

TouchGFX/target/generated/STM32DMA.cpp

@@ -2,7 +2,7 @@
   ******************************************************************************
   * File Name          : STM32DMA.cpp
   ******************************************************************************
-  * This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
+  * This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
   ******************************************************************************
   * @attention
   *
@@ -16,27 +16,686 @@
   ******************************************************************************
   */
 
+#include "stm32h7xx_hal.h"
+#include "stm32h7xx_hal_dma2d.h"
 #include <STM32DMA.hpp>
-#include <assert.h>
+#include <cassert>
+#include <touchgfx/hal/HAL.hpp>
+#include <touchgfx/hal/Paint.hpp>
+
+/* Makes touchgfx specific types and variables visible to this file */
+using namespace touchgfx;
+
+typedef struct
+{
+    const uint16_t format;
+    const uint16_t size;
+    const uint32_t* const data;
+} clutData_t;
+
+extern "C" void DMA2D_IRQHandler()
+{
+    /* Transfer Complete Interrupt management ************************************/
+    if ((READ_REG(DMA2D->ISR) & DMA2D_FLAG_TC) != RESET)
+    {
+        /* Verify Transfer Complete Interrupt */
+        if ((READ_REG(DMA2D->CR) & DMA2D_IT_TC) != RESET)
+        {
+            /* Disable the transfer complete interrupt */
+            DMA2D->CR &= ~(DMA2D_IT_TC);
+
+            /* Clear the transfer complete flag */
+            DMA2D->IFCR = (DMA2D_FLAG_TC);
+
+            /* Signal DMA queue of execution complete */
+            touchgfx::HAL::getInstance()->signalDMAInterrupt();
+        }
+    }
+}
 
 STM32DMA::STM32DMA()
-    : DMA_Interface(q), q(&b, 1)
+    : DMA_Interface(dma_queue), dma_queue(queue_storage, sizeof(queue_storage) / sizeof(queue_storage[0]))
 {
 }
 
-touchgfx::BlitOperations STM32DMA::getBlitCaps()
+STM32DMA::~STM32DMA()
 {
-    return static_cast<touchgfx::BlitOperations>(0);
+    /* Disable DMA2D global Interrupt */
+    NVIC_DisableIRQ(DMA2D_IRQn);
 }
 
-void STM32DMA::setupDataCopy(const touchgfx::BlitOp& blitOp)
+void STM32DMA::initialize()
 {
-    assert(0 && "DMA operation not supported");
+    /* Ensure DMA2D Clock is enabled */
+    __HAL_RCC_DMA2D_CLK_ENABLE();
+    __HAL_RCC_DMA2D_FORCE_RESET();
+    __HAL_RCC_DMA2D_RELEASE_RESET();
+
+    /* Enable DMA2D global Interrupt */
+    HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(DMA2D_IRQn);
 }
 
-void STM32DMA::setupDataFill(const touchgfx::BlitOp& blitOp)
+inline uint32_t STM32DMA::getChromARTInputFormat(Bitmap::BitmapFormat format)
 {
-    assert(0 && "DMA operation not supported");
+    // Default color mode set to ARGB8888
+    uint32_t dma2dColorMode = DMA2D_INPUT_ARGB8888;
+
+    switch (format)
+    {
+    case Bitmap::ARGB8888: /* DMA2D input mode set to 32bit ARGB */
+        dma2dColorMode = DMA2D_INPUT_ARGB8888;
+        break;
+    case Bitmap::RGB888: /* DMA2D input mode set to 24bit RGB */
+        dma2dColorMode = DMA2D_INPUT_RGB888;
+        break;
+    case Bitmap::RGB565: /* DMA2D input mode set to 16bit RGB */
+        dma2dColorMode = DMA2D_INPUT_RGB565;
+        break;
+    case Bitmap::ARGB2222: /* Fall through */
+    case Bitmap::ABGR2222: /* Fall through */
+    case Bitmap::RGBA2222: /* Fall through */
+    case Bitmap::BGRA2222: /* Fall through */
+    case Bitmap::L8:       /* DMA2D input mode set to 8bit Color Look up table*/
+        dma2dColorMode = DMA2D_INPUT_L8;
+        break;
+    case Bitmap::BW:     /* Fall through */
+    case Bitmap::BW_RLE: /* Fall through */
+    case Bitmap::GRAY4:  /* Fall through */
+    case Bitmap::GRAY2:  /* Fall through */
+    default:             /* Unsupported input format for DMA2D */
+        assert(0 && "Unsupported Format!");
+        break;
+    }
+
+    return dma2dColorMode;
 }
 
+inline uint32_t STM32DMA::getChromARTOutputFormat(Bitmap::BitmapFormat format)
+{
+    // Default color mode set to ARGB8888
+    uint32_t dma2dColorMode = DMA2D_OUTPUT_ARGB8888;
+
+    switch (format)
+    {
+    case Bitmap::ARGB8888: /* DMA2D output mode set to 32bit ARGB */
+        dma2dColorMode = DMA2D_OUTPUT_ARGB8888;
+        break;
+    case Bitmap::RGB888:   /* Fall through */
+    case Bitmap::ARGB2222: /* Fall through */
+    case Bitmap::ABGR2222: /* Fall through */
+    case Bitmap::RGBA2222: /* Fall through */
+    case Bitmap::BGRA2222: /* DMA2D output mode set to 24bit RGB */
+        dma2dColorMode = DMA2D_OUTPUT_RGB888;
+        break;
+    case Bitmap::RGB565: /* DMA2D output mode set to 16bit RGB */
+        dma2dColorMode = DMA2D_OUTPUT_RGB565;
+        break;
+    case Bitmap::L8:     /* Fall through */
+    case Bitmap::BW:     /* Fall through */
+    case Bitmap::BW_RLE: /* Fall through */
+    case Bitmap::GRAY4:  /* Fall through */
+    case Bitmap::GRAY2:  /* Fall through */
+    default:             /* Unsupported output format for DMA2D */
+        assert(0 && "Unsupported Format!");
+        break;
+    }
+
+    return dma2dColorMode;
+}
+
+BlitOperations STM32DMA::getBlitCaps()
+{
+    return static_cast<BlitOperations>(BLIT_OP_FILL
+                                       | BLIT_OP_FILL_WITH_ALPHA
+                                       | BLIT_OP_COPY
+                                       | BLIT_OP_COPY_L8
+                                       | BLIT_OP_COPY_WITH_ALPHA
+                                       | BLIT_OP_COPY_ARGB8888
+                                       | BLIT_OP_COPY_ARGB8888_WITH_ALPHA
+                                       | BLIT_OP_COPY_A4
+                                       | BLIT_OP_COPY_A8);
+}
+
+/*
+ * void STM32DMA::setupDataCopy(const BlitOp& blitOp) handles blit operation of
+ * BLIT_OP_COPY
+ * BLIT_OP_COPY_L8
+ * BLIT_OP_COPY_WITH_ALPHA
+ * BLIT_OP_COPY_ARGB8888
+ * BLIT_OP_COPY_ARGB8888_WITH_ALPHA
+ * BLIT_OP_COPY_A4
+ * BLIT_OP_COPY_A8
+ */
+void STM32DMA::setupDataCopy(const BlitOp& blitOp)
+{
+    uint32_t dma2dForegroundColorMode = getChromARTInputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.srcFormat));
+    uint32_t dma2dBackgroundColorMode = getChromARTInputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
+    uint32_t dma2dOutputColorMode = getChromARTOutputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
+
+    /* DMA2D OOR register configuration */
+    WRITE_REG(DMA2D->OOR, blitOp.dstLoopStride - blitOp.nSteps);
+
+    /* DMA2D BGOR register configuration */
+    WRITE_REG(DMA2D->BGOR, blitOp.dstLoopStride - blitOp.nSteps);
+
+    /* DMA2D FGOR register configuration */
+    WRITE_REG(DMA2D->FGOR, blitOp.srcLoopStride - blitOp.nSteps);
+
+    /* DMA2D OPFCCR register configuration */
+    WRITE_REG(DMA2D->OPFCCR, dma2dOutputColorMode);
+
+    /* Configure DMA2D data size */
+    WRITE_REG(DMA2D->NLR, (blitOp.nLoops | (blitOp.nSteps << DMA2D_NLR_PL_Pos)));
+
+    /* Configure DMA2D destination address */
+    WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+    /* Configure DMA2D source address */
+    WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(blitOp.pSrc));
+
+    switch (blitOp.operation)
+    {
+    case BLIT_OP_COPY_A4:
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A4 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
+
+        /* set DMA2D foreground color */
+        WRITE_REG(DMA2D->FGCOLR, blitOp.color);
+
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Configure DMA2D Stream source2 address */
+        WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+        /* Set DMA2D mode */
+        WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
+        break;
+    case BLIT_OP_COPY_A8:
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
+
+        /* set DMA2D foreground color */
+        WRITE_REG(DMA2D->FGCOLR, blitOp.color);
+
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Configure DMA2D Stream source2 address */
+        WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+        /* Set DMA2D mode */
+        WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
+        break;
+    case BLIT_OP_COPY_WITH_ALPHA:
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
+
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Configure DMA2D Stream source2 address */
+        WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+        /* Set DMA2D mode */
+        WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
+        break;
+    case BLIT_OP_COPY_L8:
+        {
+            bool blend = true;
+            const clutData_t* const palette = reinterpret_cast<const clutData_t*>(blitOp.pClut);
+
+            /* Write foreground CLUT memory address */
+            WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&palette->data));
+
+            /* Set DMA2D color mode and alpha mode */
+            WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
+
+            /* Write DMA2D BGPFCCR register */
+            WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+            /* Configure DMA2D Stream source2 address */
+            WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+            /* Configure CLUT */
+            switch ((Bitmap::ClutFormat)palette->format)
+            {
+            case Bitmap::CLUT_FORMAT_L8_ARGB8888:
+                /* Write foreground CLUT size and CLUT color mode */
+                MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_ARGB8888 << DMA2D_FGPFCCR_CCM_Pos)));
+                break;
+            case Bitmap::CLUT_FORMAT_L8_RGB888:
+                if (blitOp.alpha == 255)
+                {
+                    blend = false;
+                }
+                MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_RGB888 << DMA2D_FGPFCCR_CCM_Pos)));
+                break;
+
+            case Bitmap::CLUT_FORMAT_L8_RGB565:
+            default:
+                assert(0 && "Unsupported format");
+                break;
+            }
+
+            /* Enable the CLUT loading for the foreground */
+            SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
+
+            while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U)
+            {
+            }
+            DMA2D->IFCR = (DMA2D_FLAG_CTC);
+
+            /* Set DMA2D mode */
+            if (blend)
+            {
+                WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
+            }
+            else
+            {
+                WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
+            }
+        }
+        break;
+    case BLIT_OP_COPY_ARGB8888:
+    case BLIT_OP_COPY_ARGB8888_WITH_ALPHA:
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
+
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Configure DMA2D Stream source2 address */
+        WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+        /* Set DMA2D mode */
+        WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
+        break;
+    default: /* BLIT_OP_COPY */
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
+
+        /* Perform pixel-format-conversion (PFC) If Bitmap format is not same format as framebuffer format */
+        if (blitOp.srcFormat != blitOp.dstFormat)
+        {
+            /* Start DMA2D : PFC Mode */
+            WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
+        }
+        else
+        {
+            /* Start DMA2D : M2M Mode */
+            WRITE_REG(DMA2D->CR, DMA2D_M2M | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
+        }
+        break;
+    }
+}
+
+/*
+ * void STM32DMA::setupDataFill(const BlitOp& blitOp) handles blit operation of
+ * BLIT_OP_FILL
+ * BLIT_OP_FILL_WITH_ALPHA
+ */
+void STM32DMA::setupDataFill(const BlitOp& blitOp)
+{
+    uint32_t dma2dOutputColorMode = getChromARTOutputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
+
+    /* DMA2D OPFCCR register configuration */
+    WRITE_REG(DMA2D->OPFCCR, dma2dOutputColorMode);
+
+    /* Configure DMA2D data size */
+    WRITE_REG(DMA2D->NLR, (blitOp.nLoops | (blitOp.nSteps << DMA2D_NLR_PL_Pos)));
+
+    /* Configure DMA2D destination address */
+    WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+    /* DMA2D OOR register configuration */
+    WRITE_REG(DMA2D->OOR, blitOp.dstLoopStride - blitOp.nSteps);
+
+    if (blitOp.operation == BLIT_OP_FILL_WITH_ALPHA)
+    {
+        /* DMA2D BGOR register configuration */
+        WRITE_REG(DMA2D->BGOR, blitOp.dstLoopStride - blitOp.nSteps);
+
+        /* DMA2D FGOR register configuration */
+        WRITE_REG(DMA2D->FGOR, blitOp.dstLoopStride - blitOp.nSteps);
+
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, dma2dOutputColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Write DMA2D FGPFCCR register */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_REPLACE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | ((blitOp.alpha << 24) & DMA2D_FGPFCCR_ALPHA));
+
+        /* DMA2D FGCOLR register configuration */
+        WRITE_REG(DMA2D->FGCOLR, blitOp.color);
+
+        /* Configure DMA2D Stream source2 address */
+        WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+        /* Configure DMA2D source address */
+        WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
+
+        /* Enable the Peripheral and Enable the transfer complete interrupt */
+        WRITE_REG(DMA2D->CR, (DMA2D_IT_TC | DMA2D_CR_START | DMA2D_M2M_BLEND | DMA2D_IT_CE | DMA2D_IT_TE));
+    }
+    else
+    {
+        /* Write DMA2D FGPFCCR register */
+        WRITE_REG(DMA2D->FGPFCCR, dma2dOutputColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_FGPFCCR_AM_Pos));
+
+        /* DMA2D FGOR register configuration */
+        WRITE_REG(DMA2D->FGOR, 0);
+
+        /* Set color */
+        WRITE_REG(DMA2D->OCOLR, ((blitOp.color >> 8) & 0xF800) | ((blitOp.color >> 5) & 0x07E0) | ((blitOp.color >> 3) & 0x001F));
+
+        /* Enable the Peripheral and Enable the transfer complete interrupt */
+        WRITE_REG(DMA2D->CR, (DMA2D_IT_TC | DMA2D_CR_START | DMA2D_R2M | DMA2D_IT_CE | DMA2D_IT_TE));
+    }
+}
+
+namespace touchgfx
+{
+namespace paint
+{
+namespace
+{
+const clutData_t* L8CLUT = 0;
+uint32_t L8ClutLoaded = 0;
+} // namespace
+
+void setL8Palette(const uint8_t* const data)
+{
+    L8CLUT = reinterpret_cast<const clutData_t*>(data - offsetof(clutData_t, data));
+    L8ClutLoaded = 0;
+}
+
+/**
+ * @fn void tearDown();
+ *
+ * @brief Waits until previous DMA drawing operation has finished
+ */
+void tearDown()
+{
+    /* Wait for DMA2D to finish last run */
+    while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
+
+    /* Clear transfer flags */
+    WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+}
+
+/** Flushes a line of pixels in the data cache if used.
+ *
+ * @brief Flushes decoded RGB pixels when rendering compressed images
+ */
+void flushLine(uint32_t* addr, int sizebytes)
+{
+    // This funciton is used when decompressing RGB images to flush
+    // the currently decoded pixels in the cache to allow the DMA2D
+    // to blend the pixels correcly.
+    if (SCB->CCR & SCB_CCR_DC_Msk)
+    {
+        SCB_CleanDCache_by_Addr(addr, sizebytes);
+    }
+}
+
+namespace rgb565
+{
+/**
+ * @fn void lineFromColor();
+ *
+ * @brief Renders Canvas Widget chunks using DMA.
+ * This functions will not generate an interrupt, and will not affect the DMA queue.
+ */
+void lineFromColor(uint16_t* const ptr, const unsigned count, const uint32_t color, const uint8_t alpha, const uint32_t color565)
+{
+    /* Wait for DMA2D to finish last run */
+    while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
+
+    /* Clear transfer flags */
+    WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+    /* DMA2D OPFCCR register configuration */
+    WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
+
+    /* Configure DMA2D data size */
+    WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
+
+    /* Configure DMA2D destination address */
+    WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
+
+    if (alpha < 0xFF)
+    {
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, DMA2D_OUTPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Write DMA2D FGPFCCR register */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_REPLACE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+
+        /* DMA2D FGCOLR register configuration */
+        WRITE_REG(DMA2D->FGCOLR, color);
+
+        /* Configure DMA2D Stream source2 address */
+        WRITE_REG(DMA2D->BGMAR, (uint32_t)ptr);
+
+        /* Configure DMA2D source address */
+        WRITE_REG(DMA2D->FGMAR, (uint32_t)ptr);
+
+        /* Enable the Peripheral and Enable the transfer complete interrupt */
+        WRITE_REG(DMA2D->CR, (DMA2D_CR_START | DMA2D_M2M_BLEND));
+    }
+    else
+    {
+        /* Write DMA2D FGPFCCR register */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_OUTPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_FGPFCCR_AM_Pos));
+
+        /* Set color */
+        WRITE_REG(DMA2D->OCOLR, color565);
+
+        /* Enable the Peripheral and Enable the transfer complete interrupt */
+        WRITE_REG(DMA2D->CR, (DMA2D_CR_START | DMA2D_R2M));
+    }
+}
+
+void lineFromRGB565(uint16_t* const ptr, const uint16_t* const data, const unsigned count, const uint8_t alpha)
+{
+    /* Wait for DMA2D to finish last run */
+    while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
+
+    /* Clear transfer flags */
+    WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+    /* DMA2D OPFCCR register configuration */
+    WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
+
+    /* Configure DMA2D data size */
+    WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
+
+    /* Configure DMA2D destination address */
+    WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
+
+    /* Configure DMA2D source address */
+    WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
+
+    if (alpha < 0xFF)
+    {
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Configure DMA2D Stream source2 address */
+        WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
+
+        /* Set DMA2D mode */
+        WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
+    }
+    else
+    {
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+
+        /* Start DMA2D : M2M Mode */
+        WRITE_REG(DMA2D->CR, DMA2D_M2M | DMA2D_CR_START);
+    }
+}
+
+void lineFromARGB8888(uint16_t* const ptr, const uint32_t* const data, const unsigned count, const uint8_t alpha)
+{
+    /* Wait for DMA2D to finish last run */
+    while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
+
+    /* Clear transfer flags */
+    WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+    /* DMA2D OPFCCR register configuration */
+    WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
+
+    /* Configure DMA2D data size */
+    WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
+
+    /* Configure DMA2D destination address */
+    WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
+
+    /* Configure DMA2D source address */
+    WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
+
+    /* Set DMA2D color mode and alpha mode */
+    WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_ARGB8888 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+
+    /* Write DMA2D BGPFCCR register */
+    WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+    /* Configure DMA2D Stream source2 address */
+    WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
+
+    /* Set DMA2D mode */
+    WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
+}
+
+void lineFromL8RGB888(uint16_t* const ptr, const uint8_t* const data, const unsigned count, const uint8_t alpha)
+{
+    /* wait for DMA2D to finish last run */
+    while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
+
+    /* DMA2D OPFCCR register configuration */
+    WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
+
+    /* Configure DMA2D data size */
+    WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
+
+    /* Configure DMA2D destination address */
+    WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
+
+    /* Configure DMA2D source address */
+    WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
+
+    /* Configure DMA2D Stream source2 address */
+    WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
+
+    /* Load CLUT if not already loaded */
+    if (L8ClutLoaded == 0)
+    {
+        /* Write foreground CLUT memory address */
+        WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&L8CLUT->data));
+
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_L8 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+
+        MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((L8CLUT->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_RGB888 << DMA2D_FGPFCCR_CCM_Pos)));
+
+        /* Enable the CLUT loading for the foreground */
+        SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
+
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Mark CLUT loaded */
+        L8ClutLoaded = 1;
+
+        /* Wait for load to finish */
+        while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U);
+
+        /* Clear CLUT Transfer Complete flag */
+        DMA2D->IFCR = (DMA2D_FLAG_CTC);
+    }
+    else
+    {
+        /* Set correct alpha for these pixels */
+        MODIFY_REG(DMA2D->FGPFCCR, DMA2D_BGPFCCR_ALPHA_Msk, alpha << DMA2D_FGPFCCR_ALPHA_Pos);
+    }
+
+    /* Start pixel transfer in correct mode */
+    if (alpha < 0xFF)
+    {
+        /* Set DMA2D mode */
+        WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
+    }
+    else
+    {
+        /* Set DMA2D mode */
+        WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_CR_START);
+    }
+}
+
+void lineFromL8ARGB8888(uint16_t* const ptr, const uint8_t* const data, const unsigned count, const uint8_t alpha)
+{
+    /* wait for DMA2D to finish last run */
+    while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
+
+    /* DMA2D OPFCCR register configuration */
+    WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
+
+    /* Configure DMA2D data size */
+    WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
+
+    /* Configure DMA2D destination address */
+    WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
+
+    /* Configure DMA2D source address */
+    WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
+
+    /* Configure DMA2D Stream source2 address */
+    WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
+
+    /* Load CLUT if not already loaded */
+    if (L8ClutLoaded == 0)
+    {
+        /* Write foreground CLUT memory address */
+        WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&L8CLUT->data));
+
+        /* Set DMA2D color mode and alpha mode */
+        WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_L8 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+
+        MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((L8CLUT->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_ARGB8888 << DMA2D_FGPFCCR_CCM_Pos)));
+
+        /* Enable the CLUT loading for the foreground */
+        SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
+
+        /* Write DMA2D BGPFCCR register */
+        WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
+
+        /* Mark CLUT loaded */
+        L8ClutLoaded = 1;
+
+        /* Wait for load to finish */
+        while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U);
+
+        /* Clear CLUT Transfer Complete flag */
+        DMA2D->IFCR = (DMA2D_FLAG_CTC);
+    }
+    else
+    {
+        /* Set correct alpha for these pixels */
+        MODIFY_REG(DMA2D->FGPFCCR, DMA2D_BGPFCCR_ALPHA_Msk, alpha << DMA2D_FGPFCCR_ALPHA_Pos);
+    }
+
+    /* Start pixel transfer in blending mode */
+    WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
+}
+
+} // namespace rgb565
+} // namespace paint
+} // namespace touchgfx
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

TouchGFX/target/generated/STM32DMA.hpp

@@ -2,7 +2,7 @@
   ******************************************************************************
   * File Name          : STM32DMA.hpp
   ******************************************************************************
-  * This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
+  * This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
   ******************************************************************************
   * @attention
   *
@@ -18,7 +18,7 @@
 #ifndef STM32DMA_HPP
 #define STM32DMA_HPP
 
-#include <touchgfx/hal/BlitOp.hpp>
+#include <touchgfx/Bitmap.hpp>
 #include <touchgfx/hal/DMA.hpp>
 
 /**
@@ -26,68 +26,139 @@
  *
  * @brief This class specializes DMA_Interface for the STM32 processors.
  *
- * @see touchgfx::DMA_Interface
+ * @sa touchgfx::DMA_Interface
  */
 class STM32DMA : public touchgfx::DMA_Interface
 {
+    /**
+     * @typedef touchgfx::DMA_Interface Base
+     *
+     * @brief Defines an alias representing the base.
+     *
+     Defines an alias representing the base.
+     */
+    typedef touchgfx::DMA_Interface Base;
+
 public:
     /**
      * @fn STM32DMA::STM32DMA();
      *
      * @brief Default constructor.
+     *
+     *        Default constructor.
      */
     STM32DMA();
 
+    /**
+     * @fn STM32DMA::~STM32DMA();
+     *
+     * @brief Destructor.
+     *
+     *        Destructor.
+     */
+    virtual ~STM32DMA();
+
+    /**
+     * @fn DMAType touchgfx::STM32DMA::getDMAType()
+     *
+     * @brief Function for obtaining the DMA type of the concrete DMA_Interface implementation.
+     *
+     *        Function for obtaining the DMA type of the concrete DMA_Interface implementation.
+     *        As default, will return DMA_TYPE_CHROMART type value.
+     *
+     * @return a DMAType value of the concrete DMA_Interface implementation.
+     */
+    virtual touchgfx::DMAType getDMAType(void)
+    {
+        return touchgfx::DMA_TYPE_CHROMART;
+    }
+
     /**
      * @fn touchgfx::BlitOperations STM32DMA::getBlitCaps();
      *
-     * @brief No blit operations supported by this DMA implementation.
+     * @brief Gets the blit capabilities.
      *
-     * @return Zero (no blit ops supported).
+     *        Gets the blit capabilities.
+     *
+     *        This DMA supports a range of blit caps: BLIT_OP_COPY, BLIT_OP_COPY_ARGB8888,
+     *        BLIT_OP_COPY_ARGB8888_WITH_ALPHA, BLIT_OP_COPY_A4, BLIT_OP_COPY_A8.
+     *
+     *
+     * @return Currently supported blitcaps.
      */
     virtual touchgfx::BlitOperations getBlitCaps();
 
+    /**
+     * @fn void STM32DMA::initialize();
+     *
+     * @brief Perform hardware specific initialization.
+     *
+     *        Perform hardware specific initialization.
+     */
+    virtual void initialize();
+
+    /**
+     * @fn void STM32DMA::signalDMAInterrupt()
+     *
+     * @brief Raises a DMA interrupt signal.
+     *
+     *        Raises a DMA interrupt signal.
+     */
+    virtual void signalDMAInterrupt()
+    {
+        executeCompleted();
+    }
+
+protected:
     /**
      * @fn virtual void STM32DMA::setupDataCopy(const touchgfx::BlitOp& blitOp);
      *
-     * @brief Asserts if used.
+     * @brief Configures the DMA for copying data to the frame buffer.
      *
-     * @param  blitOp The blit operation to be performed by this DMA instance.
+     *        Configures the DMA for copying data to the frame buffer.
+     *
+     * @param blitOp Details on the copy to perform.
      */
     virtual void setupDataCopy(const touchgfx::BlitOp& blitOp);
 
     /**
      * @fn virtual void STM32DMA::setupDataFill(const touchgfx::BlitOp& blitOp);
      *
-     * @brief Asserts if used.
+     * @brief Configures the DMA for "filling" the frame-buffer with a single color.
      *
-     * @param  blitOp The blit operation to be performed by this DMA instance.
+     *        Configures the DMA for "filling" the frame-buffer with a single color.
+     *
+     * @param blitOp Details on the "fill" to perform.
      */
     virtual void setupDataFill(const touchgfx::BlitOp& blitOp);
 
-    /**
-     * @fn virtual void STM32DMA::signalDMAInterrupt();
-     *
-     * @brief Does nothing.
-     */
-    virtual void signalDMAInterrupt()
-    {
-    }
-
-    /**
-     * @fn virtual void STM32DMA::flush();
-     *
-     * @brief Block until all DMA transfers are complete. Since this particular DMA does not do
-     * anything, return immediately.
-     */
-    virtual void flush()
-    {
-    }
-
 private:
-    touchgfx::LockFreeDMA_Queue q;
+    touchgfx::LockFreeDMA_Queue dma_queue;
-    touchgfx::BlitOp b;
+    touchgfx::BlitOp queue_storage[96];
-};
-#endif // TOUCHGFX_NODMA_HPP
 
+    /**
+     * @fn void STM32DMA::getChromARTInputFormat()
+     *
+     * @brief Convert Bitmap format to ChromART Input format.
+     *
+     * @param format Bitmap format.
+     *
+     * @return ChromART Input format.
+     */
+
+    inline uint32_t getChromARTInputFormat(touchgfx::Bitmap::BitmapFormat format);
+
+    /**
+     * @fn void STM32DMA::getChromARTOutputFormat()
+     *
+     * @brief Convert Bitmap format to ChromART Output format.
+     *
+     * @param format Bitmap format.
+     *
+     * @return ChromART Output format.
+     */
+    inline uint32_t getChromARTOutputFormat(touchgfx::Bitmap::BitmapFormat format);
+};
+
+#endif // STM32DMA_HPP
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

TouchGFX/target/generated/TouchGFXConfiguration.cpp

@@ -2,7 +2,7 @@
   ******************************************************************************
   * File Name          : TouchGFXConfiguration.cpp
   ******************************************************************************
-  * This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
+  * This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
   ******************************************************************************
   * @attention
   *

TouchGFX/target/generated/TouchGFXGeneratedHAL.cpp

@@ -2,7 +2,7 @@
   ******************************************************************************
   * File Name          : TouchGFXGeneratedHAL.cpp
   ******************************************************************************
-  * This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
+  * This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
   ******************************************************************************
   * @attention
   *
@@ -19,8 +19,7 @@
 #include <TouchGFXGeneratedHAL.hpp>
 #include <touchgfx/hal/OSWrappers.hpp>
 #include <gui/common/FrontendHeap.hpp>
-#include <touchgfx/hal/PaintImpl.hpp>
+#include <touchgfx/hal/GPIO.hpp>
-#include <touchgfx/hal/PaintRGB565Impl.hpp>
 
 #include "stm32h7xx.h"
 #include "stm32h7xx_hal_ltdc.h"
@@ -37,21 +36,24 @@ void TouchGFXGeneratedHAL::initialize()
 {
     HAL::initialize();
     registerEventListener(*(Application::getInstance()));
-    setFrameBufferStartAddresses((void*)0x24040000, (void*)0x24040000, (void*)0);
+    setFrameBufferStartAddresses((void*)0x24040000, (void*)0x240A0000, (void*)0);
 }
 
 void TouchGFXGeneratedHAL::configureInterrupts()
 {
+    NVIC_SetPriority(DMA2D_IRQn, 9);
     NVIC_SetPriority(LTDC_IRQn, 9);
 }
 
 void TouchGFXGeneratedHAL::enableInterrupts()
 {
+    NVIC_EnableIRQ(DMA2D_IRQn);
     NVIC_EnableIRQ(LTDC_IRQn);
 }
 
 void TouchGFXGeneratedHAL::disableInterrupts()
 {
+    NVIC_DisableIRQ(DMA2D_IRQn);
     NVIC_DisableIRQ(LTDC_IRQn);
 }
 
@@ -101,10 +103,11 @@ bool TouchGFXGeneratedHAL::blockCopy(void* RESTRICT dest, const void* RESTRICT s
 
 void TouchGFXGeneratedHAL::InvalidateCache()
 {
-    // If the framebuffer is placed in Write Through cached memory (e.g. SRAM) then
+    // Because DMA2D access main memory directly, the DCache must be invalidated
-    // the DCache must be flushed prior to DMA2D accessing it. That's done
+    // becuase it could hold a wrong image of the framebuffer. That's done
-    // using the function SCB_CleanInvalidateDCache(). Remember to enable "CPU Cache" in the
+    // using the function SCB_CleanInvalidateDCache(). Remember to enable
-    // "System Core" settings for "Cortex M7" in CubeMX in order for this function call to work.
+    // "CPU Cache" in the "System Core" settings for "Cortex M7" in CubeMX
+    // in order for this function call to work.
     if (SCB->CCR & SCB_CCR_DC_Msk)
     {
         SCB_CleanInvalidateDCache();
@@ -113,14 +116,48 @@ void TouchGFXGeneratedHAL::InvalidateCache()
 
 void TouchGFXGeneratedHAL::FlushCache()
 {
-    // If the framebuffer is placed in Write Through cached memory (e.g. SRAM) then
+    // If the framebuffer is placed in Write-Back cached memory (e.g. SRAM) then
     // the DCache must be flushed prior to DMA2D accessing it. That's done
-    // using the function SCB_CleanInvalidateDCache(). Remember to enable "CPU Cache" in the
+    // using the function SCB_CleanInvalidateDCache(). Remember to enable
-    // "System Core" settings for "Cortex M7" in CubeMX in order for this function call to work.
+    // "CPU Cache" in the "System Core" settings for "Cortex M7" in CubeMX in
+    // order for this function call to work.
     if (SCB->CCR & SCB_CCR_DC_Msk)
     {
         SCB_CleanInvalidateDCache();
     }
 }
 
+extern "C"
+{
+    void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef* hltdc)
+    {
+        if (!HAL::getInstance())
+        {
+            return;
+        }
+
+        if (LTDC->LIPCR == lcd_int_active_line)
+        {
+            //entering active area
+            HAL_LTDC_ProgramLineEvent(hltdc, lcd_int_porch_line);
+            HAL::getInstance()->vSync();
+            OSWrappers::signalVSync();
+
+            // Swap frame buffers immediately instead of waiting for the task to be scheduled in.
+            // Note: task will also swap when it wakes up, but that operation is guarded and will not have
+            // any effect if already swapped.
+            HAL::getInstance()->swapFrameBuffers();
+            GPIO::set(GPIO::VSYNC_FREQ);
+        }
+        else
+        {
+            //exiting active area
+            HAL_LTDC_ProgramLineEvent(hltdc, lcd_int_active_line);
+
+            // Signal to the framework that display update has finished.
+            HAL::getInstance()->frontPorchEntered();
+            GPIO::clear(GPIO::VSYNC_FREQ);
+        }
+    }
+}
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

TouchGFX/target/generated/TouchGFXGeneratedHAL.hpp

@@ -2,7 +2,7 @@
   ******************************************************************************
   * File Name          : TouchGFXGeneratedHAL.hpp
   ******************************************************************************
-  * This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
+  * This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
   ******************************************************************************
   * @attention
   *
@@ -60,27 +60,27 @@ public:
     /**
      * @fn virtual void TouchGFXGeneratedHAL::configureInterrupts();
      *
-     * @brief Sets the DMA and LCD interrupt priorities.
+     * @brief Sets the DMA, LCD, and GPU2D (if enabled) interrupt priorities.
      *
-     *        Sets the DMA and LCD interrupt priorities.
+     *        Sets the DMA, LCD, and GPU2D (if enabled) interrupt priorities.
      */
     virtual void configureInterrupts();
 
     /**
      * @fn virtual void TouchGFXGeneratedHAL::enableInterrupts();
      *
-     * @brief Enables the DMA and LCD interrupts.
+     * @brief Enables the DMA, LCD, and GPU2D (if enabled) interrupts.
      *
-     *        Enables the DMA and LCD interrupts.
+     *        Enables the DMA, LCD, and GPU2D (if enabled) interrupts.
      */
     virtual void enableInterrupts();
 
     /**
      * @fn virtual void TouchGFXGeneratedHAL::disableInterrupts();
      *
-     * @brief Disables the DMA and LCD interrupts.
+     * @brief Disables the DMA, LDC, and GPU2D (if enabled) interrupts.
      *
-     *        Disables the DMA and LCD interrupts.
+     *        Disables the DMA, LDC, and GPU2D (if enabled) interrupts.
      */
     virtual void disableInterrupts();
 
@@ -114,8 +114,6 @@ public:
      * @brief This function is called whenever the framework has performed a partial draw.
      *
      *        This function is called whenever the framework has performed a partial draw.
-     *        On the STM32F7, make sure to clean and invalidate the data cache. This is to
-     *        ensure that LTDC sees correct data when transferring to the display.
      *
      * @param rect The area of the screen that has been drawn, expressed in absolute coordinates.
      *

steering-wheel.ioc

@@ -153,13 +153,13 @@ Mcu.Pin70=VP_SYS_VS_tim6
 Mcu.Pin71=VP_TIM1_VS_ClockSourceINT
 Mcu.Pin72=VP_TIM2_VS_ClockSourceINT
 Mcu.Pin73=VP_TIM17_VS_ClockSourceINT
-Mcu.Pin74=VP_STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.23.2
+Mcu.Pin74=VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.1.12_3.0.0
-Mcu.Pin75=VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.1.12_3.0.0
+Mcu.Pin75=VP_STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.24.0
 Mcu.Pin8=PF3
 Mcu.Pin9=PF4
 Mcu.PinsNb=76
 Mcu.ThirdParty0=STMicroelectronics.X-CUBE-AZRTOS-H7.3.0.0
-Mcu.ThirdParty1=STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2
+Mcu.ThirdParty1=STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0
 Mcu.ThirdPartyNb=2
 Mcu.UserConstants=
 Mcu.UserName=STM32H7A3ZITx
@@ -575,17 +575,19 @@ STMicroelectronics.X-CUBE-AZRTOS-H7.3.0.0.TX_APP_GENERATE_INIT_CODE=false
 STMicroelectronics.X-CUBE-AZRTOS-H7.3.0.0.ThreadXCcRTOSJjThreadXJjCore=true
 STMicroelectronics.X-CUBE-AZRTOS-H7.3.0.0_IsAnAzureRtosMw=true
 STMicroelectronics.X-CUBE-AZRTOS-H7.3.0.0_SwParameter=ThreadXCcRTOSJjThreadXJjCore\:true;
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.ApplicationCcGraphicsJjApplication=TouchGFXOoGenerator
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.ApplicationCcGraphicsJjApplication=TouchGFXOoGenerator
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.GraphicsJjApplication_Checked=true
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.GraphicsJjApplication_Checked=true
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.IPParameters=tgfx_custom_height,ApplicationCcGraphicsJjApplication,tgfx_location,tgfx_address1,tgfx_display_interface,tgfx_buffering_strategy,tgfx_address2
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.IPParameters=tgfx_display_interface,tgfx_vsync,tgfx_hardware_accelerator,tgfx_custom_height,tgfx_buffering_strategy,tgfx_location,tgfx_address1,tgfx_address2,ApplicationCcGraphicsJjApplication
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.tgfx_address1=0x24040000
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.tgfx_address1=0x24040000
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.tgfx_address2=0x24040000
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.tgfx_address2=0x240A0000
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.tgfx_buffering_strategy=Double
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.tgfx_buffering_strategy=Double
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.tgfx_custom_height=480
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.tgfx_custom_height=480
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.tgfx_display_interface=disp_ltdc
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.tgfx_display_interface=disp_ltdc
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2.tgfx_location=By Address
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.tgfx_hardware_accelerator=dma_2d
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2_IsPackSelfContextualization=true
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.tgfx_location=By Address
-STMicroelectronics.X-CUBE-TOUCHGFX.4.23.2_SwParameter=ApplicationCcGraphicsJjApplication\:TouchGFXOoGenerator;
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0.tgfx_vsync=vsync_ltdc
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0_IsPackSelfContextualization=true
+STMicroelectronics.X-CUBE-TOUCHGFX.4.24.0_SwParameter=ApplicationCcGraphicsJjApplication\:TouchGFXOoGenerator;
 TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
 TIM1.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
 TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
@@ -612,8 +614,8 @@ VP_OCTOSPI1_VS_quad.Mode=quad_mode
 VP_OCTOSPI1_VS_quad.Signal=OCTOSPI1_VS_quad
 VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.1.12_3.0.0.Mode=RTOSJjThreadX
 VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.1.12_3.0.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.1.12_3.0.0
-VP_STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.23.2.Mode=GraphicsJjApplication
+VP_STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.24.0.Mode=GraphicsJjApplication
-VP_STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.23.2.Signal=STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.23.2
+VP_STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.24.0.Signal=STMicroelectronics.X-CUBE-TOUCHGFX_VS_GraphicsJjApplication_4.24.0
 VP_SYS_VS_tim6.Mode=TIM6
 VP_SYS_VS_tim6.Signal=SYS_VS_tim6
 VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer