GFX Develop Branch
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@ -43,42 +43,48 @@
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/** @addtogroup DMA_LL_Private_Macros
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* @{
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*/
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#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
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((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
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((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
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#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
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((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
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((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
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#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
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((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
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((__VALUE__) == LL_DMA_MODE_PFCTRL))
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#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
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((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
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((__VALUE__) == LL_DMA_MODE_PFCTRL))
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#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
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((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
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#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
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((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
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#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
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((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
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#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
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((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
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#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
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((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
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((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
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#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
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((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
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((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
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#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
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((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
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((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
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#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
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((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
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((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
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#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
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#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
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#if defined(TIM24)
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#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_TIM24_TRIG))
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#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_TIM24_TRIG))
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#elif defined(ADC3)
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#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_ADC3))
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#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_ADC3))
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#else
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#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))
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#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))
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#endif /* TIM24 */
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#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
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((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
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((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
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((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
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#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
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((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
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((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
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((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
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#define IS_LL_DMA_DOUBLEBUFFER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DOUBLEBUFFER_MODE_DISABLE) || \
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((__VALUE__) == LL_DMA_DOUBLEBUFFER_MODE_ENABLE))
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#define IS_LL_DMA_DOUBLEBUFFER_TARGETMEM(__VALUE__) (((__VALUE__) == LL_DMA_CURRENTTARGETMEM0) || \
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((__VALUE__) == LL_DMA_CURRENTTARGETMEM1))
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#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
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(((STREAM) == LL_DMA_STREAM_0) || \
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@ -101,23 +107,23 @@
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((STREAM) == LL_DMA_STREAM_7) || \
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((STREAM) == LL_DMA_STREAM_ALL))))
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#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
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((STATE) == LL_DMA_FIFOMODE_ENABLE))
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#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
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((STATE) == LL_DMA_FIFOMODE_ENABLE))
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#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
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#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
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#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
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((BURST) == LL_DMA_MBURST_INC4) || \
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((BURST) == LL_DMA_MBURST_INC8) || \
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((BURST) == LL_DMA_MBURST_INC16))
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#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
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((BURST) == LL_DMA_MBURST_INC4) || \
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((BURST) == LL_DMA_MBURST_INC8) || \
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((BURST) == LL_DMA_MBURST_INC16))
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#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
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((BURST) == LL_DMA_PBURST_INC4) || \
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((BURST) == LL_DMA_PBURST_INC8) || \
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((BURST) == LL_DMA_PBURST_INC16))
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#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
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((BURST) == LL_DMA_PBURST_INC4) || \
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((BURST) == LL_DMA_PBURST_INC8) || \
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((BURST) == LL_DMA_PBURST_INC16))
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/**
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* @}
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@ -296,6 +302,8 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA
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assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
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assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
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assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
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assert_param(IS_LL_DMA_DOUBLEBUFFER_MODE(DMA_InitStruct->DoubleBufferMode));
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assert_param(IS_LL_DMA_DOUBLEBUFFER_TARGETMEM(DMA_InitStruct->TargetMemInDoubleBufferMode));
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/* Check the memory burst, peripheral burst and FIFO threshold parameters only
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when FIFO mode is enabled */
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@ -310,22 +318,26 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA
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* Configure DMAx_Streamy: data transfer direction, data transfer mode,
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* peripheral and memory increment mode,
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* data size alignment and priority level with parameters :
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* - Direction: DMA_SxCR_DIR[1:0] bits
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* - Mode: DMA_SxCR_CIRC bit
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* - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
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* - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
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* - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
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* - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
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* - Priority: DMA_SxCR_PL[1:0] bits
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* - Direction: DMA_SxCR_DIR[1:0] bits
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* - Mode: DMA_SxCR_CIRC bit
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* - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
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* - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
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* - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
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* - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
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* - Priority: DMA_SxCR_PL[1:0] bits
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* - DoubleBufferMode: DMA_SxCR_DBM bit
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* - TargetMemInDoubleBufferMode: DMA_SxCR_CT bit
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*/
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LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
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LL_DMA_ConfigTransfer(DMAx, Stream,
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DMA_InitStruct->Direction | \
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DMA_InitStruct->Mode | \
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DMA_InitStruct->PeriphOrM2MSrcIncMode | \
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DMA_InitStruct->MemoryOrM2MDstIncMode | \
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DMA_InitStruct->PeriphOrM2MSrcDataSize | \
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DMA_InitStruct->MemoryOrM2MDstDataSize | \
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DMA_InitStruct->Priority
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);
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DMA_InitStruct->Priority | \
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DMA_InitStruct->DoubleBufferMode | \
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DMA_InitStruct->TargetMemInDoubleBufferMode);
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if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
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{
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@ -384,21 +396,23 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA
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void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
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{
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/* Set DMA_InitStruct fields to default values */
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DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
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DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
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DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
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DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
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DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
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DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
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DMA_InitStruct->NbData = 0x00000000U;
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DMA_InitStruct->PeriphRequest = LL_DMAMUX1_REQ_MEM2MEM;
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DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
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DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
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DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
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DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
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DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
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DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
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DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
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DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
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DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
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DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
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DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
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DMA_InitStruct->NbData = 0x00000000U;
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DMA_InitStruct->PeriphRequest = LL_DMAMUX1_REQ_MEM2MEM;
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DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
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DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
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DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
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DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
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DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
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DMA_InitStruct->DoubleBufferMode = LL_DMA_DOUBLEBUFFER_MODE_DISABLE;
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DMA_InitStruct->TargetMemInDoubleBufferMode = LL_DMA_CURRENTTARGETMEM0;
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}
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/**
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