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This commit is contained in:
Julian
2024-06-11 19:38:14 +02:00
parent e23389a0b9
commit b0ef96e390
647 changed files with 10174 additions and 6435 deletions
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218
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c
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@ -33,7 +33,6 @@
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
@ -57,6 +56,9 @@
#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
ETH_MACVIR_VLP | ETH_MACVIR_VLC)
#define ETH_MAC_L4_SRSP_MASK 0x0000FFFFU
#define ETH_MAC_L4_DSTP_MASK 0xFFFF0000U
/**
* @}
*/
@ -91,6 +93,7 @@
* the configuration information for ETHERNET module
* @retval None
*/
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
{
SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
@ -133,25 +136,34 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
ETH_L4FilterConfigTypeDef *pL4FilterConfig)
const ETH_L4FilterConfigTypeDef *pL4FilterConfig)
{
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
if (pL4FilterConfig == NULL)
{
return HAL_ERROR;
}
/* Write configuration to (MACL3L4C0R + filter )register */
MODIFY_REG(*configreg, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
pL4FilterConfig->SrcPortFilterMatch |
pL4FilterConfig->DestPortFilterMatch));
if (Filter == ETH_L4_FILTER_0)
{
/* Write configuration to MACL3L4C0R register */
MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
pL4FilterConfig->SrcPortFilterMatch |
pL4FilterConfig->DestPortFilterMatch));
configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
/* Write configuration to MACL4A0R register */
WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
/* Write configuration to (MACL4A0R + filter )register */
MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP), (pL4FilterConfig->SourcePort |
(pL4FilterConfig->DestinationPort << 16)));
}
else /* Filter == ETH_L4_FILTER_1 */
{
/* Write configuration to MACL3L4C1R register */
MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
pL4FilterConfig->SrcPortFilterMatch |
pL4FilterConfig->DestPortFilterMatch));
/* Write configuration to MACL4A1R register */
WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
}
/* Enable L4 filter */
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
@ -172,7 +184,7 @@ HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
* that contains L4 filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
ETH_L4FilterConfigTypeDef *pL4FilterConfig)
{
if (pL4FilterConfig == NULL)
@ -180,18 +192,32 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
return HAL_ERROR;
}
/* Get configuration to (MACL3L4C0R + filter )register */
pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
ETH_MACL3L4CR_L4PEN);
pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
(ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
(ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
if (Filter == ETH_L4_FILTER_0)
{
/* Get configuration from MACL3L4C0R register */
pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4CR_L4PEN);
pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
(ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
(ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
/* Get configuration to (MACL3L4C0R + filter )register */
pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)),
ETH_MACL4AR_L4DP) >> 16);
pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
/* Get configuration from MACL4A0R register */
pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16);
pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK);
}
else /* Filter == ETH_L4_FILTER_1 */
{
/* Get configuration from MACL3L4C1R register */
pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4CR_L4PEN);
pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
(ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
(ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
/* Get configuration from MACL4A1R register */
pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16);
pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK);
}
return HAL_OK;
}
@ -210,43 +236,83 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
ETH_L3FilterConfigTypeDef *pL3FilterConfig)
const ETH_L3FilterConfigTypeDef *pL3FilterConfig)
{
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
if (pL3FilterConfig == NULL)
{
return HAL_ERROR;
}
/* Write configuration to (MACL3L4C0R + filter )register */
MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
pL3FilterConfig->SrcAddrFilterMatch |
pL3FilterConfig->DestAddrFilterMatch |
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
if (Filter == ETH_L3_FILTER_0)
{
/* Write configuration to MACL3L4C0R register */
MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
pL3FilterConfig->SrcAddrFilterMatch |
pL3FilterConfig->DestAddrFilterMatch |
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
}
else /* Filter == ETH_L3_FILTER_1 */
{
/* Write configuration to MACL3L4C1R register */
MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
pL3FilterConfig->SrcAddrFilterMatch |
pL3FilterConfig->DestAddrFilterMatch |
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
}
/* Check if IPv6 protocol is selected */
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
if (Filter == ETH_L3_FILTER_0)
{
/* Set the IPv6 address match */
/* Set Bits[31:0] of 128-bit IP addr */
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
/* Set Bits[63:32] of 128-bit IP addr */
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
/* update Bits[95:64] of 128-bit IP addr */
*((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
/* update Bits[127:96] of 128-bit IP addr */
*((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
/* Check if IPv6 protocol is selected */
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
{
/* Set the IPv6 address match */
/* Set Bits[31:0] of 128-bit IP addr */
WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]);
/* Set Bits[63:32] of 128-bit IP addr */
WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]);
/* update Bits[95:64] of 128-bit IP addr */
WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]);
/* update Bits[127:96] of 128-bit IP addr */
WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]);
}
else /* IPv4 protocol is selected */
{
/* Set the IPv4 source address match */
WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr);
/* Set the IPv4 destination address match */
WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr);
}
}
else /* IPv4 protocol is selected */
else /* Filter == ETH_L3_FILTER_1 */
{
/* Set the IPv4 source address match */
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
/* Set the IPv4 destination address match */
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
/* Check if IPv6 protocol is selected */
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
{
/* Set the IPv6 address match */
/* Set Bits[31:0] of 128-bit IP addr */
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]);
/* Set Bits[63:32] of 128-bit IP addr */
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]);
/* update Bits[95:64] of 128-bit IP addr */
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]);
/* update Bits[127:96] of 128-bit IP addr */
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]);
}
else /* IPv4 protocol is selected */
{
/* Set the IPv4 source address match */
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr);
/* Set the IPv4 destination address match */
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr);
}
}
/* Enable L3 filter */
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
return HAL_OK;
}
@ -263,14 +329,13 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t
* that will contain the L3 filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
ETH_L3FilterConfigTypeDef *pL3FilterConfig)
{
if (pL3FilterConfig == NULL)
{
return HAL_ERROR;
}
pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
ETH_MACL3L4CR_L3PEN);
pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
@ -282,17 +347,35 @@ HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t
pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
ETH_MACL3L4CR_L3HDBM) >> 11);
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
if (Filter == ETH_L3_FILTER_0)
{
pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
{
WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R);
WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R);
WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R);
WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R);
}
else
{
WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R);
WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R);
}
}
else
else /* ETH_L3_FILTER_1 */
{
pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
{
WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R1R);
WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R1R);
WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R1R);
WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R1R);
}
else
{
WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R1R);
WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R1R);
}
}
return HAL_OK;
@ -330,7 +413,7 @@ void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
* that will contain the VLAN filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
{
if (pVlanConfig == NULL)
{
@ -340,12 +423,14 @@ HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC
pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR,
ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR,
ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR,
ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR,
(ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
@ -407,7 +492,7 @@ void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
* that will contain the Tx VLAN filter configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
ETH_TxVLANConfigTypeDef *pVlanConfig)
{
if (pVlanConfig == NULL)
@ -443,7 +528,7 @@ HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
ETH_TxVLANConfigTypeDef *pVlanConfig)
const ETH_TxVLANConfigTypeDef *pVlanConfig)
{
if (VLANTag == ETH_INNER_TX_VLANTAG)
{
@ -544,14 +629,13 @@ void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
__HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
}
/**
* @brief Returns the ETH MAC LPI event
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval ETH MAC WakeUp event
*/
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth)
{
return heth->MACLPIEvent;
}
@ -571,8 +655,6 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
#endif /* ETH */
#endif /* HAL_ETH_MODULE_ENABLED */
/**
* @}
*/