GFX Develop Branch
This commit is contained in:
@ -202,7 +202,7 @@
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#define ETH_MACRFCR_MASK 0x00000003U
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#define ETH_MTLTQOMR_MASK 0x00000072U
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#define ETH_MTLRQOMR_MASK 0x0000007BU
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#define ETH_DMAMR_MASK 0x00007802U
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#define ETH_DMASBMR_MASK 0x0000D001U
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#define ETH_DMACCR_MASK 0x00013FFFU
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@ -250,12 +250,13 @@
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/** @defgroup ETH_Private_Functions ETH Private Functions
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* @{
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*/
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static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
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static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
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static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf);
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static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf);
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static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
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static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
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static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
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static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
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static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
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uint32_t ItMode);
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static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
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#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
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@ -410,6 +411,14 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
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heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
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((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
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/* Disable Rx MMC Interrupts */
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SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
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ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
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/* Disable Tx MMC Interrupts */
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SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
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ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
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heth->ErrorCode = HAL_ETH_ERROR_NONE;
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heth->gState = HAL_ETH_STATE_READY;
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@ -506,7 +515,6 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call
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{
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/* Update the error code */
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heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
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return HAL_ERROR;
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}
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@ -587,7 +595,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call
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/**
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* @brief Unregister an ETH Callback
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* ETH callabck is redirected to the weak predefined callback
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* ETH callback is redirected to the weak predefined callback
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* @param heth eth handle
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* @param CallbackID ID of the callback to be unregistered
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* This parameter can be one of the following values:
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@ -712,7 +720,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
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{
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heth->gState = HAL_ETH_STATE_BUSY;
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/* Set nombre of descriptors to build */
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/* Set number of descriptors to build */
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heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
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/* Build all descriptors */
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@ -760,29 +768,13 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
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/* save IT mode to ETH Handle */
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heth->RxDescList.ItMode = 1U;
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/* Disable Rx MMC Interrupts */
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SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
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ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
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/* Disable Tx MMC Interrupts */
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SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
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ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
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/* Set nombre of descriptors to build */
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/* Set number of descriptors to build */
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heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
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/* Build all descriptors */
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ETH_UpdateDescriptor(heth);
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/* Enable the MAC transmission */
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SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
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/* Enable the MAC reception */
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SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
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/* Set the Flush Transmit FIFO bit */
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SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
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/* Enable the DMA transmission */
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SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
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@ -792,6 +784,15 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
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/* Clear Tx and Rx process stopped flags */
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heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
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/* Set the Flush Transmit FIFO bit */
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SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
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/* Enable the MAC transmission */
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SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
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/* Enable the MAC reception */
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SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
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/* Enable ETH DMA interrupts:
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- Tx complete interrupt
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- Rx complete interrupt
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@ -821,6 +822,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
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{
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/* Set the ETH peripheral state to BUSY */
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heth->gState = HAL_ETH_STATE_BUSY;
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/* Disable the DMA transmission */
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CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
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@ -879,6 +881,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
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/* Disable the MAC reception */
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CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
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/* Set the Flush Transmit FIFO bit */
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SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
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@ -913,7 +916,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
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* @param Timeout: timeout value
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
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HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
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{
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uint32_t tickstart;
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ETH_DMADescTypeDef *dmatxdesc;
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@ -988,7 +991,7 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
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* @param pTxConfig: Hold the configuration of packet to be transmitted
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
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HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
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{
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if (pTxConfig == NULL)
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{
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@ -1043,7 +1046,6 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
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uint32_t bufflength;
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uint8_t rxdataready = 0U;
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if (pAppBuff == NULL)
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{
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heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
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@ -1079,12 +1081,12 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
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heth->RxDescList.RxDataLength = 0;
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}
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/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
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bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
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/* Check if last descriptor */
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bufflength = heth->Init.RxBuffLen;
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if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
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{
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bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
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/* Save Last descriptor index */
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heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3;
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@ -1150,6 +1152,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
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static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
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{
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uint32_t descidx;
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uint32_t tailidx;
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uint32_t desccount;
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ETH_DMADescTypeDef *dmarxdesc;
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uint8_t *buff = NULL;
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@ -1185,8 +1188,6 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
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if (allocStatus != 0U)
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{
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/* Ensure rest of descriptor is written to RAM before the OWN bit */
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__DMB();
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if (heth->RxDescList.ItMode != 0U)
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{
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@ -1207,8 +1208,14 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
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if (heth->RxDescList.RxBuildDescCnt != desccount)
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{
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/* Set the tail pointer index */
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tailidx = (descidx + 1U) % ETH_RX_DESC_CNT;
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/* DMB instruction to avoid race condition */
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__DMB();
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/* Set the Tail pointer address */
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WRITE_REG(heth->Instance->DMACRDTPR, 0);
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WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (tailidx))));
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heth->RxDescList.RxBuildDescIdx = descidx;
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heth->RxDescList.RxBuildDescCnt = desccount;
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@ -1268,7 +1275,7 @@ __weak void HAL_ETH_RxAllocateCallback(uint8_t **buff)
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/**
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* @brief Rx Link callback.
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* @param pStart: pointer to packet start
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* @param pStart: pointer to packet end
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* @param pEnd: pointer to packet end
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* @param buff: pointer to received data
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* @param Length: received data length
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* @retval None
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@ -1327,7 +1334,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
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* @param pErrorCode: pointer to uint32_t to hold the error code
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
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HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
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{
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/* Get error bits. */
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*pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK);
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@ -1410,7 +1417,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
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if (dmatxdesclist->PacketAddress[idx] == NULL)
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{
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/* No packet in use, skip to next. */
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idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
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INCR_TX_DESC_INDEX(idx, 1U);
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pktInUse = 0U;
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}
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@ -1420,20 +1427,32 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
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if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U)
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{
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#ifdef HAL_ETH_USE_PTP
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/* Disable Ptp transmission */
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CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U));
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/* Get timestamp low */
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timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
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/* Get timestamp high */
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timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
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if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD)
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&& (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS))
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{
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/* Get timestamp low */
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timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
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/* Get timestamp high */
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timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
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}
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else
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{
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timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX;
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}
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#endif /* HAL_ETH_USE_PTP */
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#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
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/*Call registered callbacks*/
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#ifdef HAL_ETH_USE_PTP
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/* Handle Ptp */
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heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
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if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
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{
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heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
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}
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#endif /* HAL_ETH_USE_PTP */
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/* Release the packet. */
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heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]);
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@ -1441,7 +1460,10 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
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/* Call callbacks */
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#ifdef HAL_ETH_USE_PTP
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/* Handle Ptp */
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HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
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if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
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{
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HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
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}
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#endif /* HAL_ETH_USE_PTP */
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/* Release the packet. */
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HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
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@ -1451,7 +1473,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
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dmatxdesclist->PacketAddress[idx] = NULL;
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/* Update the transmit relesae index and number of buffers in use. */
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idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
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INCR_TX_DESC_INDEX(idx, 1U);
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dmatxdesclist->BuffersInUse = numOfBuf;
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dmatxdesclist->releaseIndex = idx;
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}
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@ -1511,25 +1533,24 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
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if (ptpconfig->TimestampAddendUpdate == ENABLE)
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{
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SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG);
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while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) {}
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}
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while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0)
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{
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/* Enable Update mode */
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if (ptpconfig->TimestampUpdateMode == ENABLE)
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{
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SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT);
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}
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}
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/* Initialize Time */
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time.Seconds = 0;
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time.NanoSeconds = 0;
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HAL_ETH_PTP_SetTime(heth, &time);
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/* Ptp Init */
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SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
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/* Set PTP Configuration done */
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heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED;
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heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
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/* Set Seconds */
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time.Seconds = heth->Instance->MACSTSR;
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/* Set NanoSeconds */
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time.NanoSeconds = heth->Instance->MACSTNR;
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HAL_ETH_PTP_SetTime(heth, &time);
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/* Return function status */
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return HAL_OK;
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@ -1589,13 +1610,13 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
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* @brief Set Seconds and Nanoseconds for the Ethernet PTP registers.
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* @param heth: pointer to a ETH_HandleTypeDef structure that contains
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* the configuration information for ETHERNET module
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* @param heth: pointer to a ETH_TimeTypeDef structure that contains
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* @param time: pointer to a ETH_TimeTypeDef structure that contains
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* time to set
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
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{
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if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
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if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
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{
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/* Set Seconds */
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heth->Instance->MACSTSUR = time->Seconds;
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@ -1603,6 +1624,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
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/* Set NanoSeconds */
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heth->Instance->MACSTNUR = time->NanoSeconds;
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/* the system time is updated */
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SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
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/* Return function status */
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return HAL_OK;
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}
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@ -1617,19 +1641,18 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
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* @brief Get Seconds and Nanoseconds for the Ethernet PTP registers.
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* @param heth: pointer to a ETH_HandleTypeDef structure that contains
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* the configuration information for ETHERNET module
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* @param heth: pointer to a ETH_TimeTypeDef structure that contains
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* @param time: pointer to a ETH_TimeTypeDef structure that contains
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* time to get
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
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{
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if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
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if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
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{
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/* Get Seconds */
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time->Seconds = heth->Instance->MACSTSUR;
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time->Seconds = heth->Instance->MACSTSR;
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/* Get NanoSeconds */
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time->NanoSeconds = heth->Instance->MACSTNUR;
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time->NanoSeconds = heth->Instance->MACSTNR;
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/* Return function status */
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return HAL_OK;
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@ -1645,14 +1668,14 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
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* @brief Update time for the Ethernet PTP registers.
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* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
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* the configuration information for ETHERNET module
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* @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains
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* @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains
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* the time update information
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* @retval HAL status
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*/
|
||||
HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
|
||||
ETH_TimeTypeDef *timeoffset)
|
||||
{
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE)
|
||||
{
|
||||
@ -1678,6 +1701,8 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda
|
||||
heth->Instance->MACSTNUR = timeoffset->NanoSeconds;
|
||||
}
|
||||
|
||||
SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
@ -1692,7 +1717,6 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda
|
||||
* @brief Insert Timestamp in transmission.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param txtimestampconf: Enable or Disable timestamp in transmission
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
|
||||
@ -1701,7 +1725,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
|
||||
uint32_t descidx = dmatxdesclist->CurTxDesc;
|
||||
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
|
||||
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
/* Enable Time Stamp transmission */
|
||||
SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE);
|
||||
@ -1730,7 +1754,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeSt
|
||||
uint32_t idx = dmatxdesclist->releaseIndex;
|
||||
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
|
||||
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
/* Get timestamp low */
|
||||
timestamp->TimeStampLow = dmatxdesc->DESC0;
|
||||
@ -1757,7 +1781,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeSt
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
|
||||
{
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
/* Get timestamp low */
|
||||
timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow;
|
||||
@ -1811,6 +1835,8 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth)
|
||||
/**
|
||||
* @brief Tx Ptp callback.
|
||||
* @param buff: pointer to application buffer
|
||||
* @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains
|
||||
* transmission timestamp
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
|
||||
@ -1831,88 +1857,82 @@ __weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestam
|
||||
*/
|
||||
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
uint32_t macirqenable;
|
||||
uint32_t mac_flag = READ_REG(heth->Instance->MACISR);
|
||||
uint32_t dma_flag = READ_REG(heth->Instance->DMACSR);
|
||||
uint32_t dma_itsource = READ_REG(heth->Instance->DMACIER);
|
||||
uint32_t exti_d1_flag = READ_REG(EXTI_D1->PR3);
|
||||
#if defined(DUAL_CORE)
|
||||
uint32_t exti_d2_flag = READ_REG(EXTI_D2->PR3);
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/* Packet received */
|
||||
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
|
||||
if (((dma_flag & ETH_DMACSR_RI) != 0U) && ((dma_itsource & ETH_DMACIER_RIE) != 0U))
|
||||
{
|
||||
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
|
||||
{
|
||||
/* Clear the Eth DMA Rx IT pending bits */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
|
||||
/* Clear the Eth DMA Rx IT pending bits */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
|
||||
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Receive complete callback*/
|
||||
heth->RxCpltCallback(heth);
|
||||
/*Call registered Receive complete callback*/
|
||||
heth->RxCpltCallback(heth);
|
||||
#else
|
||||
/* Receive complete callback */
|
||||
HAL_ETH_RxCpltCallback(heth);
|
||||
/* Receive complete callback */
|
||||
HAL_ETH_RxCpltCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
/* Packet transmitted */
|
||||
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
|
||||
if (((dma_flag & ETH_DMACSR_TI) != 0U) && ((dma_itsource & ETH_DMACIER_TIE) != 0U))
|
||||
{
|
||||
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
|
||||
{
|
||||
/* Clear the Eth DMA Tx IT pending bits */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
|
||||
/* Clear the Eth DMA Tx IT pending bits */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
|
||||
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Transmit complete callback*/
|
||||
heth->TxCpltCallback(heth);
|
||||
/*Call registered Transmit complete callback*/
|
||||
heth->TxCpltCallback(heth);
|
||||
#else
|
||||
/* Transfer complete callback */
|
||||
HAL_ETH_TxCpltCallback(heth);
|
||||
/* Transfer complete callback */
|
||||
HAL_ETH_TxCpltCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* ETH DMA Error */
|
||||
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
|
||||
if (((dma_flag & ETH_DMACSR_AIS) != 0U) && ((dma_itsource & ETH_DMACIER_AIE) != 0U))
|
||||
{
|
||||
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
|
||||
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
|
||||
/* if fatal bus error occurred */
|
||||
if ((dma_flag & ETH_DMACSR_FBE) != 0U)
|
||||
{
|
||||
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
|
||||
/* Get DMA error code */
|
||||
heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
|
||||
|
||||
/* if fatal bus error occurred */
|
||||
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
|
||||
{
|
||||
/* Get DMA error code */
|
||||
heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
|
||||
|
||||
/* Disable all interrupts */
|
||||
__HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
|
||||
|
||||
/* Set HAL state to ERROR */
|
||||
heth->gState = HAL_ETH_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA error status */
|
||||
heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
|
||||
ETH_DMACSR_RBU | ETH_DMACSR_AIS));
|
||||
|
||||
/* Clear the interrupt summary flag */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
|
||||
ETH_DMACSR_RBU | ETH_DMACSR_AIS));
|
||||
}
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/* Call registered Error callback*/
|
||||
heth->ErrorCallback(heth);
|
||||
#else
|
||||
/* Ethernet DMA Error callback */
|
||||
HAL_ETH_ErrorCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
/* Disable all interrupts */
|
||||
__HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
|
||||
|
||||
/* Set HAL state to ERROR */
|
||||
heth->gState = HAL_ETH_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA error status */
|
||||
heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
|
||||
ETH_DMACSR_RBU | ETH_DMACSR_AIS));
|
||||
|
||||
/* Clear the interrupt summary flag */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
|
||||
ETH_DMACSR_RBU | ETH_DMACSR_AIS));
|
||||
}
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/* Call registered Error callback*/
|
||||
heth->ErrorCallback(heth);
|
||||
#else
|
||||
/* Ethernet DMA Error callback */
|
||||
HAL_ETH_ErrorCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/* ETH MAC Error IT */
|
||||
macirqenable = heth->Instance->MACIER;
|
||||
if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
|
||||
((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
|
||||
if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
|
||||
((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
|
||||
{
|
||||
heth->ErrorCode |= HAL_ETH_ERROR_MAC;
|
||||
|
||||
@ -1928,12 +1948,11 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
||||
/* Ethernet Error callback */
|
||||
HAL_ETH_ErrorCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
|
||||
heth->MACErrorCode = (uint32_t)(0x0U);
|
||||
}
|
||||
|
||||
/* ETH PMT IT */
|
||||
if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
|
||||
if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
|
||||
{
|
||||
/* Get MAC Wake-up source and clear the status register pending bit */
|
||||
heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
|
||||
@ -1950,10 +1969,10 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
||||
}
|
||||
|
||||
/* ETH EEE IT */
|
||||
if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
|
||||
if ((mac_flag & ETH_MAC_LPI_IT) != 0U)
|
||||
{
|
||||
/* Get MAC LPI interrupt source and clear the status register pending bit */
|
||||
heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
|
||||
heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU);
|
||||
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/* Call registered EEE callback*/
|
||||
@ -1970,7 +1989,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
||||
if (HAL_GetCurrentCPUID() == CM7_CPUID)
|
||||
{
|
||||
/* check ETH WAKEUP exti flag */
|
||||
if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
|
||||
if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
|
||||
{
|
||||
/* Clear ETH WAKEUP Exti pending bit */
|
||||
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
|
||||
@ -1986,7 +2005,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
||||
else
|
||||
{
|
||||
/* check ETH WAKEUP exti flag */
|
||||
if (__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
|
||||
if ((exti_d2_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
|
||||
{
|
||||
/* Clear ETH WAKEUP Exti pending bit */
|
||||
__HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
|
||||
@ -1999,9 +2018,9 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
#else /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
#else /* DUAL_CORE not defined */
|
||||
/* check ETH WAKEUP exti flag */
|
||||
if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
|
||||
if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
|
||||
{
|
||||
/* Clear ETH WAKEUP Exti pending bit */
|
||||
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
|
||||
@ -2013,7 +2032,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
||||
HAL_ETH_WakeUpCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
}
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
#endif /* DUAL_CORE */
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2161,7 +2180,6 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Writes to a PHY register.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
@ -2171,7 +2189,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
|
||||
* @param RegValue: the value to write
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
|
||||
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
|
||||
uint32_t RegValue)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
@ -2197,7 +2215,6 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY
|
||||
MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
|
||||
SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
|
||||
|
||||
|
||||
/* Give the value to the MII data register */
|
||||
WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
|
||||
|
||||
@ -2244,7 +2261,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY
|
||||
* the configuration of the MAC.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
|
||||
{
|
||||
if (macconf == NULL)
|
||||
{
|
||||
@ -2285,7 +2302,6 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
|
||||
? ENABLE : DISABLE;
|
||||
macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
|
||||
|
||||
|
||||
macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
|
||||
macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
|
||||
|
||||
@ -2293,8 +2309,6 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
|
||||
macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
|
||||
macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
|
||||
macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
|
||||
|
||||
|
||||
macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
|
||||
macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
|
||||
? ENABLE : DISABLE;
|
||||
@ -2319,7 +2333,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
|
||||
* the configuration of the ETH DMA.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
|
||||
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
|
||||
{
|
||||
if (dmaconf == NULL)
|
||||
{
|
||||
@ -2341,6 +2355,7 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
|
||||
dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
|
||||
dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
|
||||
dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
@ -2419,31 +2434,36 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
|
||||
hclk = HAL_RCC_GetHCLKFreq();
|
||||
|
||||
/* Set CR bits depending on hclk value */
|
||||
if ((hclk >= 20000000U) && (hclk < 35000000U))
|
||||
if (hclk < 35000000U)
|
||||
{
|
||||
/* CSR Clock Range between 20-35 MHz */
|
||||
/* CSR Clock Range between 0-35 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
|
||||
}
|
||||
else if ((hclk >= 35000000U) && (hclk < 60000000U))
|
||||
else if (hclk < 60000000U)
|
||||
{
|
||||
/* CSR Clock Range between 35-60 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
|
||||
}
|
||||
else if ((hclk >= 60000000U) && (hclk < 100000000U))
|
||||
else if (hclk < 100000000U)
|
||||
{
|
||||
/* CSR Clock Range between 60-100 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
|
||||
}
|
||||
else if ((hclk >= 100000000U) && (hclk < 150000000U))
|
||||
else if (hclk < 150000000U)
|
||||
{
|
||||
/* CSR Clock Range between 100-150 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
|
||||
}
|
||||
else /* (hclk >= 150000000)&&(hclk <= 200000000) */
|
||||
else if (hclk < 250000000U)
|
||||
{
|
||||
/* CSR Clock Range between 150-200 MHz */
|
||||
/* CSR Clock Range between 150-250 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
|
||||
}
|
||||
else /* (hclk >= 250000000U) */
|
||||
{
|
||||
/* CSR Clock >= 250 MHz */
|
||||
tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV124);
|
||||
}
|
||||
|
||||
/* Configure the CSR Clock Range */
|
||||
(heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
|
||||
@ -2457,7 +2477,7 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
|
||||
* the configuration of the ETH MAC filters.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
|
||||
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig)
|
||||
{
|
||||
uint32_t filterconfig;
|
||||
|
||||
@ -2491,7 +2511,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
|
||||
* the configuration of the ETH MAC filters.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
|
||||
{
|
||||
if (pFilterConfig == NULL)
|
||||
{
|
||||
@ -2528,7 +2548,8 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
|
||||
* @param pMACAddr: Pointer to MAC address buffer data (6 bytes)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
|
||||
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
|
||||
const uint8_t *pMACAddr)
|
||||
{
|
||||
uint32_t macaddrlr;
|
||||
uint32_t macaddrhr;
|
||||
@ -2607,7 +2628,7 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBit
|
||||
* that contains the Power Down configuration
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
|
||||
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig)
|
||||
{
|
||||
uint32_t powerdownconfig;
|
||||
|
||||
@ -2702,7 +2723,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
|
||||
HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
|
||||
{
|
||||
return heth->gState;
|
||||
}
|
||||
@ -2713,7 +2734,7 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval ETH Error Code
|
||||
*/
|
||||
uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
|
||||
uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth)
|
||||
{
|
||||
return heth->ErrorCode;
|
||||
}
|
||||
@ -2724,7 +2745,7 @@ uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval ETH DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
|
||||
uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth)
|
||||
{
|
||||
return heth->DMAErrorCode;
|
||||
}
|
||||
@ -2735,7 +2756,7 @@ uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval ETH MAC Error Code
|
||||
*/
|
||||
uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
|
||||
uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth)
|
||||
{
|
||||
return heth->MACErrorCode;
|
||||
}
|
||||
@ -2746,7 +2767,7 @@ uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval ETH MAC WakeUp event source
|
||||
*/
|
||||
uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
|
||||
uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
|
||||
{
|
||||
return heth->MACWakeUpEvent;
|
||||
}
|
||||
@ -2763,8 +2784,7 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
|
||||
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
|
||||
{
|
||||
uint32_t macregval;
|
||||
|
||||
@ -2841,7 +2861,7 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac
|
||||
MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
|
||||
}
|
||||
|
||||
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
|
||||
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
|
||||
{
|
||||
uint32_t dmaregval;
|
||||
|
||||
@ -2858,7 +2878,6 @@ static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dma
|
||||
/*------------------------ DMACCR Configuration --------------------*/
|
||||
dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
|
||||
dmaconf->MaximumSegmentSize);
|
||||
|
||||
MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
|
||||
|
||||
/*------------------------ DMACTCR Configuration --------------------*/
|
||||
@ -2900,17 +2919,17 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
|
||||
macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
|
||||
macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
|
||||
macDefaultConf.ExtendedInterPacketGap = DISABLE;
|
||||
macDefaultConf.ExtendedInterPacketGapVal = 0x0;
|
||||
macDefaultConf.ExtendedInterPacketGapVal = 0x0U;
|
||||
macDefaultConf.ForwardRxErrorPacket = DISABLE;
|
||||
macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
|
||||
macDefaultConf.GiantPacketSizeLimit = 0x618;
|
||||
macDefaultConf.GiantPacketSizeLimit = 0x618U;
|
||||
macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
|
||||
macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
|
||||
macDefaultConf.Jabber = ENABLE;
|
||||
macDefaultConf.JumboPacket = DISABLE;
|
||||
macDefaultConf.LoopbackMode = DISABLE;
|
||||
macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
|
||||
macDefaultConf.PauseTime = 0x0;
|
||||
macDefaultConf.PauseTime = 0x0U;
|
||||
macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
|
||||
macDefaultConf.ProgrammableWatchdog = DISABLE;
|
||||
macDefaultConf.ReceiveFlowControl = DISABLE;
|
||||
@ -2949,7 +2968,6 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
|
||||
ETH_SetDMAConfig(heth, &dmaDefaultConf);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMA Tx descriptors.
|
||||
* called by HAL_ETH_Init() API.
|
||||
@ -2967,10 +2985,10 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
dmatxdesc = heth->Init.TxDesc + i;
|
||||
|
||||
WRITE_REG(dmatxdesc->DESC0, 0x0);
|
||||
WRITE_REG(dmatxdesc->DESC1, 0x0);
|
||||
WRITE_REG(dmatxdesc->DESC2, 0x0);
|
||||
WRITE_REG(dmatxdesc->DESC3, 0x0);
|
||||
WRITE_REG(dmatxdesc->DESC0, 0x0U);
|
||||
WRITE_REG(dmatxdesc->DESC1, 0x0U);
|
||||
WRITE_REG(dmatxdesc->DESC2, 0x0U);
|
||||
WRITE_REG(dmatxdesc->DESC3, 0x0U);
|
||||
|
||||
WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
|
||||
|
||||
@ -3004,24 +3022,23 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
dmarxdesc = heth->Init.RxDesc + i;
|
||||
|
||||
WRITE_REG(dmarxdesc->DESC0, 0x0);
|
||||
WRITE_REG(dmarxdesc->DESC1, 0x0);
|
||||
WRITE_REG(dmarxdesc->DESC2, 0x0);
|
||||
WRITE_REG(dmarxdesc->DESC3, 0x0);
|
||||
WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
|
||||
WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
|
||||
|
||||
WRITE_REG(dmarxdesc->DESC0, 0x0U);
|
||||
WRITE_REG(dmarxdesc->DESC1, 0x0U);
|
||||
WRITE_REG(dmarxdesc->DESC2, 0x0U);
|
||||
WRITE_REG(dmarxdesc->DESC3, 0x0U);
|
||||
WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
|
||||
WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
|
||||
|
||||
/* Set Rx descritors addresses */
|
||||
WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
|
||||
|
||||
}
|
||||
|
||||
WRITE_REG(heth->RxDescList.RxDescIdx, 0);
|
||||
WRITE_REG(heth->RxDescList.RxDescCnt, 0);
|
||||
WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0);
|
||||
WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0);
|
||||
WRITE_REG(heth->RxDescList.ItMode, 0);
|
||||
WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
|
||||
WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
|
||||
WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
|
||||
WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
|
||||
WRITE_REG(heth->RxDescList.ItMode, 0U);
|
||||
|
||||
/* Set Receive Descriptor Ring Length */
|
||||
WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
|
||||
@ -3042,7 +3059,8 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
|
||||
* @param ItMode: Enable or disable Tx EOT interrept
|
||||
* @retval Status
|
||||
*/
|
||||
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
|
||||
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
|
||||
uint32_t ItMode)
|
||||
{
|
||||
ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
|
||||
uint32_t descidx = dmatxdesclist->CurTxDesc;
|
||||
@ -3053,6 +3071,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
|
||||
|
||||
ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
|
||||
uint32_t bd_count = 0;
|
||||
uint32_t primask_bit;
|
||||
|
||||
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
|
||||
if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
|
||||
@ -3151,7 +3170,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(dmatxdesc->DESC1, 0x0);
|
||||
WRITE_REG(dmatxdesc->DESC1, 0x0U);
|
||||
/* Set buffer 2 Length */
|
||||
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
|
||||
}
|
||||
@ -3259,7 +3278,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(dmatxdesc->DESC1, 0x0);
|
||||
WRITE_REG(dmatxdesc->DESC1, 0x0U);
|
||||
/* Set buffer 2 Length */
|
||||
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
|
||||
}
|
||||
@ -3311,14 +3330,14 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
|
||||
|
||||
dmatxdesclist->CurTxDesc = descidx;
|
||||
|
||||
/* disable the interrupt */
|
||||
__disable_irq();
|
||||
/* Enter critical section */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__set_PRIMASK(1);
|
||||
|
||||
dmatxdesclist->BuffersInUse += bd_count + 1U;
|
||||
|
||||
/* Enable interrupts back */
|
||||
__enable_irq();
|
||||
|
||||
/* Exit critical section: restore previous priority mask */
|
||||
__set_PRIMASK(primask_bit);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_ETH_ERROR_NONE;
|
||||
@ -3358,4 +3377,3 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
Reference in New Issue
Block a user