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This commit is contained in:
Julian
2024-06-11 19:38:14 +02:00
parent e23389a0b9
commit b0ef96e390
647 changed files with 10174 additions and 6435 deletions
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37
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h
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@ -386,7 +386,14 @@ extern "C" {
#endif /* ADC_VER_V5_3 */
#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx)
#define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor ,
temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */
#else
#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been
calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */
#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
@ -6025,8 +6032,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
AWDThresholdsHighLow,
AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
(ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)),
AWDThresholdValue << (((AWDThresholdsHighLow * ADC3_TR1_HT1) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
}
else
{
@ -6081,11 +6088,24 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
#if defined(ADC_VER_V5_V90)
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));
if (ADCx == ADC3)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
return (uint32_t)(READ_BIT(*preg,
(ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)))
>> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
& ~(AWDThresholdsHighLow & ADC3_TR1_LT1)));
}
else
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));
return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
}
#else
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
@ -6150,7 +6170,8 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t
/* containing other bits reserved for other purpose. */
if (ADCx == ADC3)
{
uint32_t __IO *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC3_TR1_HT1 | ADC3_TR1_LT1,