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@ -211,7 +211,7 @@ typedef enum
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/**
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* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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*/
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#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
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#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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@ -3864,6 +3864,10 @@ typedef struct
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#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
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#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
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#define ADC3_AWD2CR_AWD2CH_Pos (0U)
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#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
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#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
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/******************** Bit definition for ADC_AWD3CR register ********************/
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#define ADC_AWD3CR_AWD3CH_Pos (0U)
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#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
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@ -3889,6 +3893,10 @@ typedef struct
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#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
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#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
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#define ADC3_AWD3CR_AWD3CH_Pos (0U)
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#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
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#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
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/******************** Bit definition for ADC_DIFSEL register ********************/
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#define ADC_DIFSEL_DIFSEL_Pos (0U)
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#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
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@ -11719,7 +11727,7 @@ typedef struct
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#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
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#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
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#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
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#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
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#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
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#define FMC_SDCMR_CTB2_Pos (3U)
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#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
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@ -18200,6 +18208,7 @@ typedef struct
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/* Serial Peripheral Interface (SPI/I2S) */
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/* */
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/******************************************************************************/
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#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
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/******************* Bit definition for SPI_CR1 register ********************/
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#define SPI_CR1_SPE_Pos (0U)
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#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
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@ -21903,6 +21912,9 @@ typedef struct
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#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
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#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
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#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
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#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
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#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
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#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
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/******************** Bit definition forUSB_OTG_HCFG register ********************/
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@ -21928,7 +21940,7 @@ typedef struct
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#define USB_OTG_DCFG_DAD_Pos (4U)
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#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
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#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
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#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
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#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
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#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
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#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
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@ -21939,13 +21951,21 @@ typedef struct
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#define USB_OTG_DCFG_PFIVL_Pos (11U)
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#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
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#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
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#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
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#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
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#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
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#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
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#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
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#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
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#define USB_OTG_DCFG_ERRATIM_Pos (15U)
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#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
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#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
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#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
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#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
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#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
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#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
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#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
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#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
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@ -22015,6 +22035,12 @@ typedef struct
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#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
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#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
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#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
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#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
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#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
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#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
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#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
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#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
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#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
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/******************** Bit definition forUSB_OTG_HFIR register ********************/
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#define USB_OTG_HFIR_FRIVL_Pos (0U)
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@ -22132,7 +22158,7 @@ typedef struct
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#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
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#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
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#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
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#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
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#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
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/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
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#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
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@ -212,7 +212,7 @@ typedef enum
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/**
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* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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*/
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#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
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#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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@ -3865,6 +3865,10 @@ typedef struct
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#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
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#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
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#define ADC3_AWD2CR_AWD2CH_Pos (0U)
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#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
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#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
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/******************** Bit definition for ADC_AWD3CR register ********************/
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#define ADC_AWD3CR_AWD3CH_Pos (0U)
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#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
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@ -3890,6 +3894,10 @@ typedef struct
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#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
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#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
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#define ADC3_AWD3CR_AWD3CH_Pos (0U)
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#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
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#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
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/******************** Bit definition for ADC_DIFSEL register ********************/
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#define ADC_DIFSEL_DIFSEL_Pos (0U)
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#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
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@ -11720,7 +11728,7 @@ typedef struct
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#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
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#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
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#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
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#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
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#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
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#define FMC_SDCMR_CTB2_Pos (3U)
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#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
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@ -18212,6 +18220,7 @@ typedef struct
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/* Serial Peripheral Interface (SPI/I2S) */
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/* */
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/******************************************************************************/
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#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
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/******************* Bit definition for SPI_CR1 register ********************/
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#define SPI_CR1_SPE_Pos (0U)
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#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
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@ -21915,6 +21924,9 @@ typedef struct
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#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
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#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
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#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
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#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
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#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
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#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
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/******************** Bit definition forUSB_OTG_HCFG register ********************/
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@ -21940,7 +21952,7 @@ typedef struct
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#define USB_OTG_DCFG_DAD_Pos (4U)
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#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
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#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
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#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
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#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
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#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
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#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
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@ -21951,13 +21963,21 @@ typedef struct
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#define USB_OTG_DCFG_PFIVL_Pos (11U)
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#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
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#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
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#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
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#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
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#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
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#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
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#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
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#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
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#define USB_OTG_DCFG_ERRATIM_Pos (15U)
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#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
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#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
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#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
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#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
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#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
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#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
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#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
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#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
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@ -22027,6 +22047,12 @@ typedef struct
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#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
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#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
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#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
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#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
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#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
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#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
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#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
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#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
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#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
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/******************** Bit definition forUSB_OTG_HFIR register ********************/
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#define USB_OTG_HFIR_FRIVL_Pos (0U)
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@ -22144,7 +22170,7 @@ typedef struct
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#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
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#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
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#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
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#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
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#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
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/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
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#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
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@ -214,7 +214,7 @@ typedef enum
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/**
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* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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*/
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#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
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#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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@ -3999,6 +3999,10 @@ typedef struct
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#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
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#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
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#define ADC3_AWD2CR_AWD2CH_Pos (0U)
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#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
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#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
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/******************** Bit definition for ADC_AWD3CR register ********************/
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#define ADC_AWD3CR_AWD3CH_Pos (0U)
|
||||
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
|
||||
@ -4024,6 +4028,10 @@ typedef struct
|
||||
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
|
||||
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
|
||||
|
||||
#define ADC3_AWD3CR_AWD3CH_Pos (0U)
|
||||
#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
|
||||
#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
|
||||
|
||||
/******************** Bit definition for ADC_DIFSEL register ********************/
|
||||
#define ADC_DIFSEL_DIFSEL_Pos (0U)
|
||||
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
|
||||
@ -11973,7 +11981,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -18687,6 +18695,7 @@ typedef struct
|
||||
/* Serial Peripheral Interface (SPI/I2S) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
|
||||
/******************* Bit definition for SPI_CR1 register ********************/
|
||||
#define SPI_CR1_SPE_Pos (0U)
|
||||
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
|
||||
@ -22390,6 +22399,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -22415,7 +22427,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -22426,13 +22438,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -22502,6 +22522,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -22619,7 +22645,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -215,7 +215,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -4000,6 +4000,10 @@ typedef struct
|
||||
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
|
||||
#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
|
||||
|
||||
#define ADC3_AWD2CR_AWD2CH_Pos (0U)
|
||||
#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
|
||||
#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
|
||||
|
||||
/******************** Bit definition for ADC_AWD3CR register ********************/
|
||||
#define ADC_AWD3CR_AWD3CH_Pos (0U)
|
||||
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
|
||||
@ -4025,6 +4029,10 @@ typedef struct
|
||||
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
|
||||
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
|
||||
|
||||
#define ADC3_AWD3CR_AWD3CH_Pos (0U)
|
||||
#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
|
||||
#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
|
||||
|
||||
/******************** Bit definition for ADC_DIFSEL register ********************/
|
||||
#define ADC_DIFSEL_DIFSEL_Pos (0U)
|
||||
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
|
||||
@ -11974,7 +11982,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -18699,6 +18707,7 @@ typedef struct
|
||||
/* Serial Peripheral Interface (SPI/I2S) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
|
||||
/******************* Bit definition for SPI_CR1 register ********************/
|
||||
#define SPI_CR1_SPE_Pos (0U)
|
||||
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
|
||||
@ -22402,6 +22411,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -22427,7 +22439,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -22438,13 +22450,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -22514,6 +22534,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -22631,7 +22657,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -214,7 +214,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -3999,6 +3999,10 @@ typedef struct
|
||||
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
|
||||
#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
|
||||
|
||||
#define ADC3_AWD2CR_AWD2CH_Pos (0U)
|
||||
#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
|
||||
#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
|
||||
|
||||
/******************** Bit definition for ADC_AWD3CR register ********************/
|
||||
#define ADC_AWD3CR_AWD3CH_Pos (0U)
|
||||
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
|
||||
@ -4024,6 +4028,10 @@ typedef struct
|
||||
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
|
||||
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
|
||||
|
||||
#define ADC3_AWD3CR_AWD3CH_Pos (0U)
|
||||
#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
|
||||
#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
|
||||
|
||||
/******************** Bit definition for ADC_DIFSEL register ********************/
|
||||
#define ADC_DIFSEL_DIFSEL_Pos (0U)
|
||||
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
|
||||
@ -18687,6 +18695,7 @@ typedef struct
|
||||
/* Serial Peripheral Interface (SPI/I2S) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
|
||||
/******************* Bit definition for SPI_CR1 register ********************/
|
||||
#define SPI_CR1_SPE_Pos (0U)
|
||||
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
|
||||
@ -22390,6 +22399,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -22415,7 +22427,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -22426,13 +22438,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -22502,6 +22522,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -22619,7 +22645,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -215,7 +215,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -4000,6 +4000,10 @@ typedef struct
|
||||
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
|
||||
#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
|
||||
|
||||
#define ADC3_AWD2CR_AWD2CH_Pos (0U)
|
||||
#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
|
||||
#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
|
||||
|
||||
/******************** Bit definition for ADC_AWD3CR register ********************/
|
||||
#define ADC_AWD3CR_AWD3CH_Pos (0U)
|
||||
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
|
||||
@ -4025,6 +4029,10 @@ typedef struct
|
||||
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
|
||||
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
|
||||
|
||||
#define ADC3_AWD3CR_AWD3CH_Pos (0U)
|
||||
#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
|
||||
#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
|
||||
|
||||
/******************** Bit definition for ADC_DIFSEL register ********************/
|
||||
#define ADC_DIFSEL_DIFSEL_Pos (0U)
|
||||
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
|
||||
@ -11974,7 +11982,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -18699,6 +18707,7 @@ typedef struct
|
||||
/* Serial Peripheral Interface (SPI/I2S) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
|
||||
/******************* Bit definition for SPI_CR1 register ********************/
|
||||
#define SPI_CR1_SPE_Pos (0U)
|
||||
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
|
||||
@ -22402,6 +22411,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -22427,7 +22439,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -22438,13 +22450,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -22514,6 +22534,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -22631,7 +22657,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -210,7 +210,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -225,7 +225,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -11369,7 +11368,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -20660,7 +20659,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -20869,7 +20868,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -23644,6 +23643,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -23669,7 +23671,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -23680,13 +23682,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -23756,6 +23766,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -23873,7 +23889,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -213,7 +213,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -228,7 +228,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -11464,7 +11463,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -13211,7 +13210,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -21308,7 +21307,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -21517,7 +21516,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -24292,6 +24291,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -24317,7 +24319,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -24328,13 +24330,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -24404,6 +24414,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -24521,7 +24537,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -230,7 +230,7 @@ typedef enum
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -250,7 +250,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -11597,7 +11596,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -13735,7 +13734,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -22081,7 +22080,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -22290,7 +22289,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -25065,6 +25064,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -25090,7 +25092,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -25101,13 +25103,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -25177,6 +25187,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -25294,7 +25310,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -230,7 +230,7 @@ typedef enum
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -250,7 +250,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -11597,7 +11596,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -13735,7 +13734,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -22081,7 +22080,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -22290,7 +22289,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -25065,6 +25064,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -25090,7 +25092,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -25101,13 +25103,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -25177,6 +25187,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -25294,7 +25310,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -231,7 +231,7 @@ typedef enum
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -251,7 +251,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -14754,7 +14753,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -16892,7 +16891,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -25254,7 +25253,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -25463,7 +25462,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -28238,6 +28237,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -28263,7 +28265,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -28274,13 +28276,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -28350,6 +28360,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -28467,7 +28483,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -231,7 +231,7 @@ typedef enum
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -251,7 +251,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -14754,7 +14753,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -16892,7 +16891,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -25254,7 +25253,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -25463,7 +25462,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -28238,6 +28237,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -28263,7 +28265,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -28274,13 +28276,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -28350,6 +28360,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -28467,7 +28483,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -214,7 +214,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -229,7 +229,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -11651,7 +11650,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -13474,7 +13473,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -21589,7 +21588,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -21798,7 +21797,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -24573,6 +24572,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -24598,7 +24600,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -24609,13 +24611,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -24685,6 +24695,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -24802,7 +24818,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -214,7 +214,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -229,7 +229,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -11657,7 +11656,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -13480,7 +13479,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -21595,7 +21594,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -21804,7 +21803,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -24579,6 +24578,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -24604,7 +24606,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -24615,13 +24617,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -24691,6 +24701,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -24808,7 +24824,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -231,7 +231,7 @@ typedef enum
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -251,7 +251,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -11790,7 +11789,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -14004,7 +14003,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -22368,7 +22367,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -22577,7 +22576,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -25352,6 +25351,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -25377,7 +25379,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -25388,13 +25390,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -25464,6 +25474,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -25581,7 +25597,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -232,7 +232,7 @@ typedef enum
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#else /* CORE_CM7 */
|
||||
#ifdef CORE_CM7
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -252,7 +252,6 @@ typedef enum
|
||||
|
||||
|
||||
|
||||
|
||||
#include "system_stm32h7xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
@ -14947,7 +14946,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -17161,7 +17160,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -25541,7 +25540,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_MCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
|
||||
@ -25750,7 +25749,7 @@ typedef struct
|
||||
|
||||
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
|
||||
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
|
||||
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
|
||||
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
|
||||
#define HRTIM_TIMCR_PREEN_Pos (27U)
|
||||
@ -28525,6 +28524,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -28550,7 +28552,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -28561,13 +28563,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -28637,6 +28647,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -28754,7 +28770,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -208,7 +208,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -2287,7 +2287,6 @@ typedef struct
|
||||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
@ -9424,7 +9423,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -11314,7 +11313,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -20195,6 +20194,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -20220,7 +20222,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -20231,13 +20233,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -20307,6 +20317,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -20424,7 +20440,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -209,7 +209,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -2288,7 +2288,6 @@ typedef struct
|
||||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
@ -9425,7 +9424,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -11315,7 +11314,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -20207,6 +20206,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -20232,7 +20234,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -20243,13 +20245,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -20319,6 +20329,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -20436,7 +20452,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -211,7 +211,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -2407,7 +2407,6 @@ typedef struct
|
||||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
@ -9671,7 +9670,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -11637,7 +11636,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -20675,6 +20674,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -20700,7 +20702,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -20711,13 +20713,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -20787,6 +20797,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -20904,7 +20920,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -212,7 +212,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -2408,7 +2408,6 @@ typedef struct
|
||||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
@ -9672,7 +9671,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -11638,7 +11637,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -20687,6 +20686,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -20712,7 +20714,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -20723,13 +20725,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -20799,6 +20809,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -20916,7 +20932,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -211,7 +211,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -2407,7 +2407,6 @@ typedef struct
|
||||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
@ -9678,7 +9677,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -11644,7 +11643,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -20682,6 +20681,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -20707,7 +20709,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -20718,13 +20720,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -20794,6 +20804,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -20911,7 +20927,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -212,7 +212,7 @@ typedef enum
|
||||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
@ -2408,7 +2408,6 @@ typedef struct
|
||||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
@ -9679,7 +9678,7 @@ typedef struct
|
||||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
@ -11645,7 +11644,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@ -20694,6 +20693,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@ -20719,7 +20721,7 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
@ -20730,13 +20732,21 @@ typedef struct
|
||||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -20806,6 +20816,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -20923,7 +20939,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -102,11 +102,11 @@
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.10.3
|
||||
* @brief CMSIS Device version number V1.10.4
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -308,6 +307,8 @@ g_pfnVectors:
|
||||
.word TIM23_IRQHandler /* TIM23 global interrupt */
|
||||
.word TIM24_IRQHandler /* TIM24 global interrupt */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -308,6 +307,8 @@ g_pfnVectors:
|
||||
.word TIM23_IRQHandler /* TIM23 global interrupt */
|
||||
.word TIM24_IRQHandler /* TIM24 global interrupt */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -308,6 +307,8 @@ g_pfnVectors:
|
||||
.word TIM23_IRQHandler /* TIM23 global interrupt */
|
||||
.word TIM24_IRQHandler /* TIM24 global interrupt */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -308,6 +307,8 @@ g_pfnVectors:
|
||||
.word TIM23_IRQHandler /* TIM23 global interrupt */
|
||||
.word TIM24_IRQHandler /* TIM24 global interrupt */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -308,6 +307,8 @@ g_pfnVectors:
|
||||
.word TIM23_IRQHandler /* TIM23 global interrupt */
|
||||
.word TIM24_IRQHandler /* TIM24 global interrupt */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -308,6 +307,8 @@ g_pfnVectors:
|
||||
.word TIM23_IRQHandler /* TIM23 global interrupt */
|
||||
.word TIM24_IRQHandler /* TIM24 global interrupt */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word 0 /* Reserved */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word 0 /* Reserved */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word 0 /* Reserved */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word 0 /* Reserved */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -295,6 +294,8 @@ g_pfnVectors:
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -300,6 +299,8 @@ g_pfnVectors:
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word BDMA1_IRQHandler /* BDMA1 */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -300,6 +299,8 @@ g_pfnVectors:
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word BDMA1_IRQHandler /* BDMA1 */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -300,6 +299,8 @@ g_pfnVectors:
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word BDMA1_IRQHandler /* BDMA1 */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -300,6 +299,8 @@ g_pfnVectors:
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word BDMA1_IRQHandler /* BDMA1 */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -300,6 +299,8 @@ g_pfnVectors:
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word BDMA1_IRQHandler /* BDMA1 */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
@ -121,7 +121,6 @@ Infinite_Loop:
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
@ -300,6 +299,8 @@ g_pfnVectors:
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word BDMA1_IRQHandler /* BDMA1 */
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
||||
Reference in New Issue
Block a user