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Fix TouchGFX again again (upgrade to 24)

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This commit is contained in:
Julian
2024-07-21 19:25:19 +02:00
parent a32d497074
commit 6db74c2242
12 changed files with 818 additions and 85 deletions
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2
TouchGFX/App/app_touchgfx.c
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@ -2,7 +2,7 @@
******************************************************************************
* File Name : app_touchgfx.c
******************************************************************************
* This file was created by TouchGFX Generator 4.23.2. This file is only
* This file was created by TouchGFX Generator 4.24.0. This file is only
* generated once! Delete this file from your project and re-generate code
* using STM32CubeMX or change this file manually to update it.
******************************************************************************

2
TouchGFX/App/app_touchgfx.h
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@ -2,7 +2,7 @@
******************************************************************************
* File Name : app_touchgfx.h
******************************************************************************
* This file was created by TouchGFX Generator 4.23.2. This file is only
* This file was created by TouchGFX Generator 4.24.0. This file is only
* generated once! Delete this file from your project and re-generate code
* using STM32CubeMX or change this file manually to update it.
******************************************************************************

2
TouchGFX/ApplicationTemplate.touchgfx.part
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@ -26,5 +26,5 @@
"AdditionalFeatures": [
]
},
"Version": "4.23.2"
"Version": "4.24.0"
}

5
TouchGFX/target/generated/OSWrappers.cpp
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@ -2,7 +2,7 @@
******************************************************************************
* File Name : OSWrappers.cpp
******************************************************************************
* This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
* This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
******************************************************************************
* @attention
*
@ -16,7 +16,6 @@
******************************************************************************
*/
#include <cassert>
#include <touchgfx/hal/HAL.hpp>
#include <touchgfx/hal/OSWrappers.hpp>
@ -25,6 +24,8 @@
#include "tx_api.h"
#include "tx_byte_pool.h"
#include <cassert>
// tx_thread.h is not C++ compatible, declare used symbols here as externals
extern "C" volatile UINT _tx_thread_preempt_disable;
extern "C" VOID _tx_thread_system_preempt_check(VOID);

677
TouchGFX/target/generated/STM32DMA.cpp
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@ -2,7 +2,7 @@
******************************************************************************
* File Name : STM32DMA.cpp
******************************************************************************
* This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
* This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
******************************************************************************
* @attention
*
@ -16,27 +16,686 @@
******************************************************************************
*/
#include "stm32h7xx_hal.h"
#include "stm32h7xx_hal_dma2d.h"
#include <STM32DMA.hpp>
#include <assert.h>
#include <cassert>
#include <touchgfx/hal/HAL.hpp>
#include <touchgfx/hal/Paint.hpp>
/* Makes touchgfx specific types and variables visible to this file */
using namespace touchgfx;
typedef struct
{
const uint16_t format;
const uint16_t size;
const uint32_t* const data;
} clutData_t;
extern "C" void DMA2D_IRQHandler()
{
/* Transfer Complete Interrupt management ************************************/
if ((READ_REG(DMA2D->ISR) & DMA2D_FLAG_TC) != RESET)
{
/* Verify Transfer Complete Interrupt */
if ((READ_REG(DMA2D->CR) & DMA2D_IT_TC) != RESET)
{
/* Disable the transfer complete interrupt */
DMA2D->CR &= ~(DMA2D_IT_TC);
/* Clear the transfer complete flag */
DMA2D->IFCR = (DMA2D_FLAG_TC);
/* Signal DMA queue of execution complete */
touchgfx::HAL::getInstance()->signalDMAInterrupt();
}
}
}
STM32DMA::STM32DMA()
: DMA_Interface(q), q(&b, 1)
: DMA_Interface(dma_queue), dma_queue(queue_storage, sizeof(queue_storage) / sizeof(queue_storage[0]))
{
}
touchgfx::BlitOperations STM32DMA::getBlitCaps()
STM32DMA::~STM32DMA()
{
return static_cast<touchgfx::BlitOperations>(0);
/* Disable DMA2D global Interrupt */
NVIC_DisableIRQ(DMA2D_IRQn);
}
void STM32DMA::setupDataCopy(const touchgfx::BlitOp& blitOp)
void STM32DMA::initialize()
{
assert(0 && "DMA operation not supported");
/* Ensure DMA2D Clock is enabled */
__HAL_RCC_DMA2D_CLK_ENABLE();
__HAL_RCC_DMA2D_FORCE_RESET();
__HAL_RCC_DMA2D_RELEASE_RESET();
/* Enable DMA2D global Interrupt */
HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2D_IRQn);
}
void STM32DMA::setupDataFill(const touchgfx::BlitOp& blitOp)
inline uint32_t STM32DMA::getChromARTInputFormat(Bitmap::BitmapFormat format)
{
assert(0 && "DMA operation not supported");
// Default color mode set to ARGB8888
uint32_t dma2dColorMode = DMA2D_INPUT_ARGB8888;
switch (format)
{
case Bitmap::ARGB8888: /* DMA2D input mode set to 32bit ARGB */
dma2dColorMode = DMA2D_INPUT_ARGB8888;
break;
case Bitmap::RGB888: /* DMA2D input mode set to 24bit RGB */
dma2dColorMode = DMA2D_INPUT_RGB888;
break;
case Bitmap::RGB565: /* DMA2D input mode set to 16bit RGB */
dma2dColorMode = DMA2D_INPUT_RGB565;
break;
case Bitmap::ARGB2222: /* Fall through */
case Bitmap::ABGR2222: /* Fall through */
case Bitmap::RGBA2222: /* Fall through */
case Bitmap::BGRA2222: /* Fall through */
case Bitmap::L8: /* DMA2D input mode set to 8bit Color Look up table*/
dma2dColorMode = DMA2D_INPUT_L8;
break;
case Bitmap::BW: /* Fall through */
case Bitmap::BW_RLE: /* Fall through */
case Bitmap::GRAY4: /* Fall through */
case Bitmap::GRAY2: /* Fall through */
default: /* Unsupported input format for DMA2D */
assert(0 && "Unsupported Format!");
break;
}
return dma2dColorMode;
}
inline uint32_t STM32DMA::getChromARTOutputFormat(Bitmap::BitmapFormat format)
{
// Default color mode set to ARGB8888
uint32_t dma2dColorMode = DMA2D_OUTPUT_ARGB8888;
switch (format)
{
case Bitmap::ARGB8888: /* DMA2D output mode set to 32bit ARGB */
dma2dColorMode = DMA2D_OUTPUT_ARGB8888;
break;
case Bitmap::RGB888: /* Fall through */
case Bitmap::ARGB2222: /* Fall through */
case Bitmap::ABGR2222: /* Fall through */
case Bitmap::RGBA2222: /* Fall through */
case Bitmap::BGRA2222: /* DMA2D output mode set to 24bit RGB */
dma2dColorMode = DMA2D_OUTPUT_RGB888;
break;
case Bitmap::RGB565: /* DMA2D output mode set to 16bit RGB */
dma2dColorMode = DMA2D_OUTPUT_RGB565;
break;
case Bitmap::L8: /* Fall through */
case Bitmap::BW: /* Fall through */
case Bitmap::BW_RLE: /* Fall through */
case Bitmap::GRAY4: /* Fall through */
case Bitmap::GRAY2: /* Fall through */
default: /* Unsupported output format for DMA2D */
assert(0 && "Unsupported Format!");
break;
}
return dma2dColorMode;
}
BlitOperations STM32DMA::getBlitCaps()
{
return static_cast<BlitOperations>(BLIT_OP_FILL
| BLIT_OP_FILL_WITH_ALPHA
| BLIT_OP_COPY
| BLIT_OP_COPY_L8
| BLIT_OP_COPY_WITH_ALPHA
| BLIT_OP_COPY_ARGB8888
| BLIT_OP_COPY_ARGB8888_WITH_ALPHA
| BLIT_OP_COPY_A4
| BLIT_OP_COPY_A8);
}
/*
* void STM32DMA::setupDataCopy(const BlitOp& blitOp) handles blit operation of
* BLIT_OP_COPY
* BLIT_OP_COPY_L8
* BLIT_OP_COPY_WITH_ALPHA
* BLIT_OP_COPY_ARGB8888
* BLIT_OP_COPY_ARGB8888_WITH_ALPHA
* BLIT_OP_COPY_A4
* BLIT_OP_COPY_A8
*/
void STM32DMA::setupDataCopy(const BlitOp& blitOp)
{
uint32_t dma2dForegroundColorMode = getChromARTInputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.srcFormat));
uint32_t dma2dBackgroundColorMode = getChromARTInputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
uint32_t dma2dOutputColorMode = getChromARTOutputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
/* DMA2D OOR register configuration */
WRITE_REG(DMA2D->OOR, blitOp.dstLoopStride - blitOp.nSteps);
/* DMA2D BGOR register configuration */
WRITE_REG(DMA2D->BGOR, blitOp.dstLoopStride - blitOp.nSteps);
/* DMA2D FGOR register configuration */
WRITE_REG(DMA2D->FGOR, blitOp.srcLoopStride - blitOp.nSteps);
/* DMA2D OPFCCR register configuration */
WRITE_REG(DMA2D->OPFCCR, dma2dOutputColorMode);
/* Configure DMA2D data size */
WRITE_REG(DMA2D->NLR, (blitOp.nLoops | (blitOp.nSteps << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* Configure DMA2D source address */
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(blitOp.pSrc));
switch (blitOp.operation)
{
case BLIT_OP_COPY_A4:
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A4 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
/* set DMA2D foreground color */
WRITE_REG(DMA2D->FGCOLR, blitOp.color);
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* Set DMA2D mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
break;
case BLIT_OP_COPY_A8:
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
/* set DMA2D foreground color */
WRITE_REG(DMA2D->FGCOLR, blitOp.color);
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* Set DMA2D mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
break;
case BLIT_OP_COPY_WITH_ALPHA:
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* Set DMA2D mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
break;
case BLIT_OP_COPY_L8:
{
bool blend = true;
const clutData_t* const palette = reinterpret_cast<const clutData_t*>(blitOp.pClut);
/* Write foreground CLUT memory address */
WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&palette->data));
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* Configure CLUT */
switch ((Bitmap::ClutFormat)palette->format)
{
case Bitmap::CLUT_FORMAT_L8_ARGB8888:
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_ARGB8888 << DMA2D_FGPFCCR_CCM_Pos)));
break;
case Bitmap::CLUT_FORMAT_L8_RGB888:
if (blitOp.alpha == 255)
{
blend = false;
}
MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_RGB888 << DMA2D_FGPFCCR_CCM_Pos)));
break;
case Bitmap::CLUT_FORMAT_L8_RGB565:
default:
assert(0 && "Unsupported format");
break;
}
/* Enable the CLUT loading for the foreground */
SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U)
{
}
DMA2D->IFCR = (DMA2D_FLAG_CTC);
/* Set DMA2D mode */
if (blend)
{
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
}
else
{
WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
}
}
break;
case BLIT_OP_COPY_ARGB8888:
case BLIT_OP_COPY_ARGB8888_WITH_ALPHA:
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* Set DMA2D mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
break;
default: /* BLIT_OP_COPY */
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (blitOp.alpha << 24));
/* Perform pixel-format-conversion (PFC) If Bitmap format is not same format as framebuffer format */
if (blitOp.srcFormat != blitOp.dstFormat)
{
/* Start DMA2D : PFC Mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
}
else
{
/* Start DMA2D : M2M Mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M | DMA2D_IT_TC | DMA2D_CR_START | DMA2D_IT_CE | DMA2D_IT_TE);
}
break;
}
}
/*
* void STM32DMA::setupDataFill(const BlitOp& blitOp) handles blit operation of
* BLIT_OP_FILL
* BLIT_OP_FILL_WITH_ALPHA
*/
void STM32DMA::setupDataFill(const BlitOp& blitOp)
{
uint32_t dma2dOutputColorMode = getChromARTOutputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
/* DMA2D OPFCCR register configuration */
WRITE_REG(DMA2D->OPFCCR, dma2dOutputColorMode);
/* Configure DMA2D data size */
WRITE_REG(DMA2D->NLR, (blitOp.nLoops | (blitOp.nSteps << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* DMA2D OOR register configuration */
WRITE_REG(DMA2D->OOR, blitOp.dstLoopStride - blitOp.nSteps);
if (blitOp.operation == BLIT_OP_FILL_WITH_ALPHA)
{
/* DMA2D BGOR register configuration */
WRITE_REG(DMA2D->BGOR, blitOp.dstLoopStride - blitOp.nSteps);
/* DMA2D FGOR register configuration */
WRITE_REG(DMA2D->FGOR, blitOp.dstLoopStride - blitOp.nSteps);
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, dma2dOutputColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Write DMA2D FGPFCCR register */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_REPLACE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | ((blitOp.alpha << 24) & DMA2D_FGPFCCR_ALPHA));
/* DMA2D FGCOLR register configuration */
WRITE_REG(DMA2D->FGCOLR, blitOp.color);
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* Configure DMA2D source address */
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
/* Enable the Peripheral and Enable the transfer complete interrupt */
WRITE_REG(DMA2D->CR, (DMA2D_IT_TC | DMA2D_CR_START | DMA2D_M2M_BLEND | DMA2D_IT_CE | DMA2D_IT_TE));
}
else
{
/* Write DMA2D FGPFCCR register */
WRITE_REG(DMA2D->FGPFCCR, dma2dOutputColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_FGPFCCR_AM_Pos));
/* DMA2D FGOR register configuration */
WRITE_REG(DMA2D->FGOR, 0);
/* Set color */
WRITE_REG(DMA2D->OCOLR, ((blitOp.color >> 8) & 0xF800) | ((blitOp.color >> 5) & 0x07E0) | ((blitOp.color >> 3) & 0x001F));
/* Enable the Peripheral and Enable the transfer complete interrupt */
WRITE_REG(DMA2D->CR, (DMA2D_IT_TC | DMA2D_CR_START | DMA2D_R2M | DMA2D_IT_CE | DMA2D_IT_TE));
}
}
namespace touchgfx
{
namespace paint
{
namespace
{
const clutData_t* L8CLUT = 0;
uint32_t L8ClutLoaded = 0;
} // namespace
void setL8Palette(const uint8_t* const data)
{
L8CLUT = reinterpret_cast<const clutData_t*>(data - offsetof(clutData_t, data));
L8ClutLoaded = 0;
}
/**
* @fn void tearDown();
*
* @brief Waits until previous DMA drawing operation has finished
*/
void tearDown()
{
/* Wait for DMA2D to finish last run */
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
/* Clear transfer flags */
WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
}
/** Flushes a line of pixels in the data cache if used.
*
* @brief Flushes decoded RGB pixels when rendering compressed images
*/
void flushLine(uint32_t* addr, int sizebytes)
{
// This funciton is used when decompressing RGB images to flush
// the currently decoded pixels in the cache to allow the DMA2D
// to blend the pixels correcly.
if (SCB->CCR & SCB_CCR_DC_Msk)
{
SCB_CleanDCache_by_Addr(addr, sizebytes);
}
}
namespace rgb565
{
/**
* @fn void lineFromColor();
*
* @brief Renders Canvas Widget chunks using DMA.
* This functions will not generate an interrupt, and will not affect the DMA queue.
*/
void lineFromColor(uint16_t* const ptr, const unsigned count, const uint32_t color, const uint8_t alpha, const uint32_t color565)
{
/* Wait for DMA2D to finish last run */
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
/* Clear transfer flags */
WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
/* DMA2D OPFCCR register configuration */
WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
/* Configure DMA2D data size */
WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
if (alpha < 0xFF)
{
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, DMA2D_OUTPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Write DMA2D FGPFCCR register */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_REPLACE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
/* DMA2D FGCOLR register configuration */
WRITE_REG(DMA2D->FGCOLR, color);
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, (uint32_t)ptr);
/* Configure DMA2D source address */
WRITE_REG(DMA2D->FGMAR, (uint32_t)ptr);
/* Enable the Peripheral and Enable the transfer complete interrupt */
WRITE_REG(DMA2D->CR, (DMA2D_CR_START | DMA2D_M2M_BLEND));
}
else
{
/* Write DMA2D FGPFCCR register */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_OUTPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_FGPFCCR_AM_Pos));
/* Set color */
WRITE_REG(DMA2D->OCOLR, color565);
/* Enable the Peripheral and Enable the transfer complete interrupt */
WRITE_REG(DMA2D->CR, (DMA2D_CR_START | DMA2D_R2M));
}
}
void lineFromRGB565(uint16_t* const ptr, const uint16_t* const data, const unsigned count, const uint8_t alpha)
{
/* Wait for DMA2D to finish last run */
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
/* Clear transfer flags */
WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
/* DMA2D OPFCCR register configuration */
WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
/* Configure DMA2D data size */
WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
/* Configure DMA2D source address */
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
if (alpha < 0xFF)
{
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
/* Set DMA2D mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
}
else
{
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_COMBINE_ALPHA << DMA2D_FGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
/* Start DMA2D : M2M Mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M | DMA2D_CR_START);
}
}
void lineFromARGB8888(uint16_t* const ptr, const uint32_t* const data, const unsigned count, const uint8_t alpha)
{
/* Wait for DMA2D to finish last run */
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
/* Clear transfer flags */
WRITE_REG(DMA2D->IFCR, DMA2D_FLAG_TC | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
/* DMA2D OPFCCR register configuration */
WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
/* Configure DMA2D data size */
WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
/* Configure DMA2D source address */
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_ARGB8888 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
/* Set DMA2D mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
}
void lineFromL8RGB888(uint16_t* const ptr, const uint8_t* const data, const unsigned count, const uint8_t alpha)
{
/* wait for DMA2D to finish last run */
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
/* DMA2D OPFCCR register configuration */
WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
/* Configure DMA2D data size */
WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
/* Configure DMA2D source address */
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
/* Load CLUT if not already loaded */
if (L8ClutLoaded == 0)
{
/* Write foreground CLUT memory address */
WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&L8CLUT->data));
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_L8 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((L8CLUT->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_RGB888 << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the foreground */
SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Mark CLUT loaded */
L8ClutLoaded = 1;
/* Wait for load to finish */
while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U);
/* Clear CLUT Transfer Complete flag */
DMA2D->IFCR = (DMA2D_FLAG_CTC);
}
else
{
/* Set correct alpha for these pixels */
MODIFY_REG(DMA2D->FGPFCCR, DMA2D_BGPFCCR_ALPHA_Msk, alpha << DMA2D_FGPFCCR_ALPHA_Pos);
}
/* Start pixel transfer in correct mode */
if (alpha < 0xFF)
{
/* Set DMA2D mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
}
else
{
/* Set DMA2D mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_CR_START);
}
}
void lineFromL8ARGB8888(uint16_t* const ptr, const uint8_t* const data, const unsigned count, const uint8_t alpha)
{
/* wait for DMA2D to finish last run */
while ((READ_REG(DMA2D->CR) & DMA2D_CR_START) != 0U);
/* DMA2D OPFCCR register configuration */
WRITE_REG(DMA2D->OPFCCR, DMA2D_OUTPUT_RGB565);
/* Configure DMA2D data size */
WRITE_REG(DMA2D->NLR, (1 | (count << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(ptr));
/* Configure DMA2D source address */
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(data));
/* Configure DMA2D Stream source2 address */
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(ptr));
/* Load CLUT if not already loaded */
if (L8ClutLoaded == 0)
{
/* Write foreground CLUT memory address */
WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&L8CLUT->data));
/* Set DMA2D color mode and alpha mode */
WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_L8 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (alpha << DMA2D_FGPFCCR_ALPHA_Pos));
MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((L8CLUT->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_ARGB8888 << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the foreground */
SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
/* Write DMA2D BGPFCCR register */
WRITE_REG(DMA2D->BGPFCCR, DMA2D_INPUT_RGB565 | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
/* Mark CLUT loaded */
L8ClutLoaded = 1;
/* Wait for load to finish */
while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U);
/* Clear CLUT Transfer Complete flag */
DMA2D->IFCR = (DMA2D_FLAG_CTC);
}
else
{
/* Set correct alpha for these pixels */
MODIFY_REG(DMA2D->FGPFCCR, DMA2D_BGPFCCR_ALPHA_Msk, alpha << DMA2D_FGPFCCR_ALPHA_Pos);
}
/* Start pixel transfer in blending mode */
WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_CR_START);
}
} // namespace rgb565
} // namespace paint
} // namespace touchgfx
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

135
TouchGFX/target/generated/STM32DMA.hpp
View File

@ -2,7 +2,7 @@
******************************************************************************
* File Name : STM32DMA.hpp
******************************************************************************
* This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
* This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
******************************************************************************
* @attention
*
@ -18,7 +18,7 @@
#ifndef STM32DMA_HPP
#define STM32DMA_HPP
#include <touchgfx/hal/BlitOp.hpp>
#include <touchgfx/Bitmap.hpp>
#include <touchgfx/hal/DMA.hpp>
/**
@ -26,68 +26,139 @@
*
* @brief This class specializes DMA_Interface for the STM32 processors.
*
* @see touchgfx::DMA_Interface
* @sa touchgfx::DMA_Interface
*/
class STM32DMA : public touchgfx::DMA_Interface
{
/**
* @typedef touchgfx::DMA_Interface Base
*
* @brief Defines an alias representing the base.
*
Defines an alias representing the base.
*/
typedef touchgfx::DMA_Interface Base;
public:
/**
* @fn STM32DMA::STM32DMA();
*
* @brief Default constructor.
*
* Default constructor.
*/
STM32DMA();
/**
* @fn STM32DMA::~STM32DMA();
*
* @brief Destructor.
*
* Destructor.
*/
virtual ~STM32DMA();
/**
* @fn DMAType touchgfx::STM32DMA::getDMAType()
*
* @brief Function for obtaining the DMA type of the concrete DMA_Interface implementation.
*
* Function for obtaining the DMA type of the concrete DMA_Interface implementation.
* As default, will return DMA_TYPE_CHROMART type value.
*
* @return a DMAType value of the concrete DMA_Interface implementation.
*/
virtual touchgfx::DMAType getDMAType(void)
{
return touchgfx::DMA_TYPE_CHROMART;
}
/**
* @fn touchgfx::BlitOperations STM32DMA::getBlitCaps();
*
* @brief No blit operations supported by this DMA implementation.
* @brief Gets the blit capabilities.
*
* @return Zero (no blit ops supported).
* Gets the blit capabilities.
*
* This DMA supports a range of blit caps: BLIT_OP_COPY, BLIT_OP_COPY_ARGB8888,
* BLIT_OP_COPY_ARGB8888_WITH_ALPHA, BLIT_OP_COPY_A4, BLIT_OP_COPY_A8.
*
*
* @return Currently supported blitcaps.
*/
virtual touchgfx::BlitOperations getBlitCaps();
/**
* @fn void STM32DMA::initialize();
*
* @brief Perform hardware specific initialization.
*
* Perform hardware specific initialization.
*/
virtual void initialize();
/**
* @fn void STM32DMA::signalDMAInterrupt()
*
* @brief Raises a DMA interrupt signal.
*
* Raises a DMA interrupt signal.
*/
virtual void signalDMAInterrupt()
{
executeCompleted();
}
protected:
/**
* @fn virtual void STM32DMA::setupDataCopy(const touchgfx::BlitOp& blitOp);
*
* @brief Asserts if used.
* @brief Configures the DMA for copying data to the frame buffer.
*
* @param blitOp The blit operation to be performed by this DMA instance.
* Configures the DMA for copying data to the frame buffer.
*
* @param blitOp Details on the copy to perform.
*/
virtual void setupDataCopy(const touchgfx::BlitOp& blitOp);
/**
* @fn virtual void STM32DMA::setupDataFill(const touchgfx::BlitOp& blitOp);
*
* @brief Asserts if used.
* @brief Configures the DMA for "filling" the frame-buffer with a single color.
*
* @param blitOp The blit operation to be performed by this DMA instance.
* Configures the DMA for "filling" the frame-buffer with a single color.
*
* @param blitOp Details on the "fill" to perform.
*/
virtual void setupDataFill(const touchgfx::BlitOp& blitOp);
/**
* @fn virtual void STM32DMA::signalDMAInterrupt();
*
* @brief Does nothing.
*/
virtual void signalDMAInterrupt()
{
}
/**
* @fn virtual void STM32DMA::flush();
*
* @brief Block until all DMA transfers are complete. Since this particular DMA does not do
* anything, return immediately.
*/
virtual void flush()
{
}
private:
touchgfx::LockFreeDMA_Queue q;
touchgfx::BlitOp b;
};
#endif // TOUCHGFX_NODMA_HPP
touchgfx::LockFreeDMA_Queue dma_queue;
touchgfx::BlitOp queue_storage[96];
/**
* @fn void STM32DMA::getChromARTInputFormat()
*
* @brief Convert Bitmap format to ChromART Input format.
*
* @param format Bitmap format.
*
* @return ChromART Input format.
*/
inline uint32_t getChromARTInputFormat(touchgfx::Bitmap::BitmapFormat format);
/**
* @fn void STM32DMA::getChromARTOutputFormat()
*
* @brief Convert Bitmap format to ChromART Output format.
*
* @param format Bitmap format.
*
* @return ChromART Output format.
*/
inline uint32_t getChromARTOutputFormat(touchgfx::Bitmap::BitmapFormat format);
};
#endif // STM32DMA_HPP
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
TouchGFX/target/generated/TouchGFXConfiguration.cpp
View File

@ -2,7 +2,7 @@
******************************************************************************
* File Name : TouchGFXConfiguration.cpp
******************************************************************************
* This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
* This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
******************************************************************************
* @attention
*

23
TouchGFX/target/generated/TouchGFXGeneratedHAL.cpp
View File

@ -2,7 +2,7 @@
******************************************************************************
* File Name : TouchGFXGeneratedHAL.cpp
******************************************************************************
* This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
* This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
******************************************************************************
* @attention
*
@ -20,8 +20,6 @@
#include <touchgfx/hal/OSWrappers.hpp>
#include <gui/common/FrontendHeap.hpp>
#include <touchgfx/hal/GPIO.hpp>
#include <touchgfx/hal/PaintImpl.hpp>
#include <touchgfx/hal/PaintRGB565Impl.hpp>
#include "stm32h7xx.h"
#include "stm32h7xx_hal_ltdc.h"
@ -43,16 +41,19 @@ void TouchGFXGeneratedHAL::initialize()
void TouchGFXGeneratedHAL::configureInterrupts()
{
NVIC_SetPriority(DMA2D_IRQn, 9);
NVIC_SetPriority(LTDC_IRQn, 9);
}
void TouchGFXGeneratedHAL::enableInterrupts()
{
NVIC_EnableIRQ(DMA2D_IRQn);
NVIC_EnableIRQ(LTDC_IRQn);
}
void TouchGFXGeneratedHAL::disableInterrupts()
{
NVIC_DisableIRQ(DMA2D_IRQn);
NVIC_DisableIRQ(LTDC_IRQn);
}
@ -102,10 +103,11 @@ bool TouchGFXGeneratedHAL::blockCopy(void* RESTRICT dest, const void* RESTRICT s
void TouchGFXGeneratedHAL::InvalidateCache()
{
// If the framebuffer is placed in Write Through cached memory (e.g. SRAM) then
// the DCache must be flushed prior to DMA2D accessing it. That's done
// using the function SCB_CleanInvalidateDCache(). Remember to enable "CPU Cache" in the
// "System Core" settings for "Cortex M7" in CubeMX in order for this function call to work.
// Because DMA2D access main memory directly, the DCache must be invalidated
// becuase it could hold a wrong image of the framebuffer. That's done
// using the function SCB_CleanInvalidateDCache(). Remember to enable
// "CPU Cache" in the "System Core" settings for "Cortex M7" in CubeMX
// in order for this function call to work.
if (SCB->CCR & SCB_CCR_DC_Msk)
{
SCB_CleanInvalidateDCache();
@ -114,10 +116,11 @@ void TouchGFXGeneratedHAL::InvalidateCache()
void TouchGFXGeneratedHAL::FlushCache()
{
// If the framebuffer is placed in Write Through cached memory (e.g. SRAM) then
// If the framebuffer is placed in Write-Back cached memory (e.g. SRAM) then
// the DCache must be flushed prior to DMA2D accessing it. That's done
// using the function SCB_CleanInvalidateDCache(). Remember to enable "CPU Cache" in the
// "System Core" settings for "Cortex M7" in CubeMX in order for this function call to work.
// using the function SCB_CleanInvalidateDCache(). Remember to enable
// "CPU Cache" in the "System Core" settings for "Cortex M7" in CubeMX in
// order for this function call to work.
if (SCB->CCR & SCB_CCR_DC_Msk)
{
SCB_CleanInvalidateDCache();

16
TouchGFX/target/generated/TouchGFXGeneratedHAL.hpp
View File

@ -2,7 +2,7 @@
******************************************************************************
* File Name : TouchGFXGeneratedHAL.hpp
******************************************************************************
* This file is generated by TouchGFX Generator 4.23.2. Please, do not edit!
* This file is generated by TouchGFX Generator 4.24.0. Please, do not edit!
******************************************************************************
* @attention
*
@ -60,27 +60,27 @@ public:
/**
* @fn virtual void TouchGFXGeneratedHAL::configureInterrupts();
*
* @brief Sets the DMA and LCD interrupt priorities.
* @brief Sets the DMA, LCD, and GPU2D (if enabled) interrupt priorities.
*
* Sets the DMA and LCD interrupt priorities.
* Sets the DMA, LCD, and GPU2D (if enabled) interrupt priorities.
*/
virtual void configureInterrupts();
/**
* @fn virtual void TouchGFXGeneratedHAL::enableInterrupts();
*
* @brief Enables the DMA and LCD interrupts.
* @brief Enables the DMA, LCD, and GPU2D (if enabled) interrupts.
*
* Enables the DMA and LCD interrupts.
* Enables the DMA, LCD, and GPU2D (if enabled) interrupts.
*/
virtual void enableInterrupts();
/**
* @fn virtual void TouchGFXGeneratedHAL::disableInterrupts();
*
* @brief Disables the DMA and LCD interrupts.
* @brief Disables the DMA, LDC, and GPU2D (if enabled) interrupts.
*
* Disables the DMA and LCD interrupts.
* Disables the DMA, LDC, and GPU2D (if enabled) interrupts.
*/
virtual void disableInterrupts();
@ -114,8 +114,6 @@ public:
* @brief This function is called whenever the framework has performed a partial draw.
*
* This function is called whenever the framework has performed a partial draw.
* On the STM32F7, make sure to clean and invalidate the data cache. This is to
* ensure that LTDC sees correct data when transferring to the display.
*
* @param rect The area of the screen that has been drawn, expressed in absolute coordinates.
*