update to CubeMX 6.14.0, FW_H7 1.12.1
This commit is contained in:
@ -30,7 +30,7 @@ extern "C" {
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/** @addtogroup STM32H7xx_Driver
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* @{
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*/
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#if defined (SDMMC1) || defined (SDMMC2)
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/** @addtogroup SDMMC_LL
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* @{
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*/
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@ -61,10 +61,10 @@ typedef struct
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uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
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This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
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#if (USE_SD_TRANSCEIVER != 0U)
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#if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U)
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uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher.
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This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */
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#endif /* USE_SD_TRANSCEIVER */
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#endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */
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} SDMMC_InitTypeDef;
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@ -160,84 +160,128 @@ typedef struct
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#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
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#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
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/**
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* @brief Masks for R5 Response
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*/
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/** this is the reserved for future use in spec RFU */
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#define SDMMC_SDIO_R5_ERROR ((uint32_t)0x00000400U)
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/** Out of range error */
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#define SDMMC_SDIO_R5_OUT_OF_RANGE ((uint32_t)0x00000100U)
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/** Invalid function number */
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#define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER ((uint32_t)0x00000200U)
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/** General or an unknown error */
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#define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00000800U)
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/** SDIO Card current state
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* 00=DIS (card not selected)
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* 01=CMD (data line free)
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* 10=TRN (transfer on data lines) */
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#define SDMMC_SDIO_R5_IO_CURRENT_STATE ((uint32_t)0x00003000U)
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/** Illegal command error */
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#define SDMMC_SDIO_R5_ILLEGAL_CMD ((uint32_t)0x00004000U)
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/** CRC check of previous cmd failed */
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#define SDMMC_SDIO_R5_COM_CRC_FAILED ((uint32_t)0x00008000U)
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#define SDMMC_SDIO_R5_ERRORBITS (SDMMC_SDIO_R5_COM_CRC_FAILED | \
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SDMMC_SDIO_R5_ILLEGAL_CMD | \
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SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR | \
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SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \
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SDMMC_SDIO_R5_OUT_OF_RANGE)
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/**
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* @brief SDIO_CMD53_MODE
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*/
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#define SDMMC_SDIO_MODE_BYTE 0x00U /*!< Byte Mode */
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#define SDMMC_SDIO_MODE_BLOCK 0x01U /*!< Block Mode */
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/**
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* @brief SDIO_CMD53_OP_CODE
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*/
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#define SDMMC_SDIO_NO_INC 0x00U /*!< No auto indentation */
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#define SDMMC_SDIO_AUTO_INC 0x01U /*!< Auto indentation */
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/**
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* @brief SDIO_CMD53_RAW
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*/
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#define SDMMC_SDIO_WO 0x00U /*!< Write only Flag */
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#define SDMMC_SDIO_RAW 0x01U /*!< Read after write Flag */
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/**
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* @brief SDMMC Commands Index
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*/
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#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
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#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
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#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
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#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
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#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
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#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
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#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
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#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
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#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */
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#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
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#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
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#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
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#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
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#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
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#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
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#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
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#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */
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#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */
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#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */
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#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
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#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */
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#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */
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#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
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#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
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#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */
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#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */
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#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
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#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */
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#define SDMMC_CMD_VOLTAGE_SWITCH 11U /*!< SD card Voltage switch to 1.8V mode. */
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#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */
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#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */
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#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */
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#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */
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#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */
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/*!< for SDHS and SDXC. */
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#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
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#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */
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#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
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#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
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#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
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#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
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#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
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#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
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#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
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#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
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#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
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#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
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#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
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#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
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#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */
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#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */
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#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
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#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
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#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
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#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */
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#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */
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#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */
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#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
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#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
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#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */
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#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
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#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */
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#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */
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#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
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#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
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#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */
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#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */
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#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */
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#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */
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#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */
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#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */
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#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */
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#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */
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#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */
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#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */
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#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */
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#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */
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#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */
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#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */
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#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */
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#define SDMMC_CMD_NO_CMD 64U /*!< No command */
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/**
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* @brief Following commands are SD Card Specific commands.
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* SDMMC_APP_CMD should be sent before sending these commands.
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*/
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#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */
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#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
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#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */
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#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
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#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
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#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
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#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
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#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
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#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */
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#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */
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#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */
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#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
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#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
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#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */
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#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */
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#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */
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/**
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* @brief Following commands are MMC Specific commands.
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*/
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#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */
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#define SDMMC_CMD_MMC_SLEEP_AWAKE 5U /*!< Toggle the device between Sleep state and Standby state. */
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/**
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* @brief Following commands are SD Card Specific security commands.
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* SDMMC_CMD_APP_CMD should be sent before sending these commands.
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*/
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#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
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#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
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#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
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#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
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#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
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#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
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#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
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#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
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#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
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#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
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#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
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#define SDMMC_CMD_SD_APP_GET_MKB 43U
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#define SDMMC_CMD_SD_APP_GET_MID 44U
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#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U
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#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U
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#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U
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#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U
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#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U
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#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U
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#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U
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#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U
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#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U
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/**
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* @brief Masks for errors Card Status R1 (OCR Register)
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@ -291,9 +335,14 @@ typedef struct
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#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
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#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
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#ifndef SDMMC_DATATIMEOUT
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#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */
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#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
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#endif /* SDMMC_DATATIMEOUT */
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#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */
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#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU)
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#endif /* SDMMC_SWDATATIMEOUT */
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#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
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#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
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#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
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@ -303,6 +352,8 @@ typedef struct
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#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
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#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
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/* SDMMC FIFO Size */
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#define SDMMC_FIFO_SIZE 32U
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/**
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* @brief Command Class supported
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*/
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@ -543,9 +594,11 @@ typedef struct
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* @{
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*/
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#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
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#define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0
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#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
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#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
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((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \
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((MODE) == SDMMC_TRANSFER_MODE_STREAM))
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/**
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* @}
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@ -657,6 +710,82 @@ typedef struct
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* @}
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*/
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/** @defgroup SDMMC_SDIO_CCCR_Registers
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* @{
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*/
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/*-------------------------------- CCCR0 ----------------------------------*/
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#define SDMMC_SDIO_CCCR0 0x000U /*!< SDIOS Card Common Control Register 0 */
|
||||
#define SDMMC_SDIO_CCCR0_SD_BYTE0 0x000U /*!< SDIOS Card Common Control Register 0 Byte 0 */
|
||||
#define SDMMC_SDIO_CCCR0_SD_BYTE1 0x001U /*!< SDIOS Card Common Control Register 0 Byte 1 */
|
||||
#define SDMMC_SDIO_CCCR0_SD_BYTE2 0x002U /*!< SDIOS Card Common Control Register 0 Byte 2 */
|
||||
#define SDMMC_SDIO_CCCR0_SD_BYTE3 0x003U /*!< SDIOS Card Common Control Register 0 Byte 3 */
|
||||
|
||||
/*-------------------------------- CCCR4 ----------------------------------*/
|
||||
#define SDMMC_SDIO_CCCR4 0x004U /*!< SDIOS Card Common Control Register 4 */
|
||||
#define SDMMC_SDIO_CCCR4_SD_BYTE0 0x004U /*!< SDIOS Card Common Control Register 4 Byte 0 */
|
||||
#define SDMMC_SDIO_CCCR4_SD_BYTE1 0x005U /*!< SDIOS Card Common Control Register 4 Byte 1 */
|
||||
#define SDMMC_SDIO_CCCR4_SD_BYTE2 0x006U /*!< SDIOS Card Common Control Register 4 Byte 2 */
|
||||
#define SDMMC_SDIO_CCCR4_SD_BYTE3 0x007U /*!< SDIOS Card Common Control Register 4 Byte 3 */
|
||||
|
||||
/*-------------------------------- CCCR8 ----------------------------------*/
|
||||
#define SDMMC_SDIO_CCCR8 0x008U /*!< SDIOS Card Common Control Register 8 */
|
||||
#define SDMMC_SDIO_CCCR8_SD_BYTE0 0x008U /*!< SDIOS Card Common Control Register 8 Byte 0 */
|
||||
#define SDMMC_SDIO_CCCR8_SD_BYTE1 0x009U /*!< SDIOS Card Common Control Register 8 Byte 1 */
|
||||
#define SDMMC_SDIO_CCCR8_SD_BYTE2 0x00AU /*!< SDIOS Card Common Control Register 8 Byte 2 */
|
||||
#define SDMMC_SDIO_CCCR8_SD_BYTE3 0x00BU /*!< SDIOS Card Common Control Register 8 Byte 3 */
|
||||
|
||||
/*-------------------------------- CCCR12 ---------------------------------*/
|
||||
#define SDMMC_SDIO_CCCR12 0x00CU /*!< SDIOS Card Common Control Register 12 */
|
||||
#define SDMMC_SDIO_CCCR12_SD_BYTE0 0x00CU /*!< SDIOS Card Common Control Register 12 Byte 0 */
|
||||
#define SDMMC_SDIO_CCCR12_SD_BYTE1 0x00DU /*!< SDIOS Card Common Control Register 12 Byte 1 */
|
||||
#define SDMMC_SDIO_CCCR12_SD_BYTE2 0x00EU /*!< SDIOS Card Common Control Register 12 Byte 2 */
|
||||
#define SDMMC_SDIO_CCCR12_SD_BYTE3 0x00FU /*!< SDIOS Card Common Control Register 12 Byte 3 */
|
||||
|
||||
/*-------------------------------- CCCR16 ---------------------------------*/
|
||||
#define SDMMC_SDIO_CCCR16 0x010U /*!< SDIOS Card Common Control Register 16 */
|
||||
#define SDMMC_SDIO_CCCR16_SD_BYTE0 0x010U /*!< SDIOS Card Common Control Register 16 Byte 0 */
|
||||
#define SDMMC_SDIO_CCCR16_SD_BYTE1 0x011U /*!< SDIOS Card Common Control Register 16 Byte 1 */
|
||||
#define SDMMC_SDIO_CCCR16_SD_BYTE2 0x012U /*!< SDIOS Card Common Control Register 16 Byte 2 */
|
||||
#define SDMMC_SDIO_CCCR16_SD_BYTE3 0x013U /*!< SDIOS Card Common Control Register 16 Byte 3 */
|
||||
|
||||
/*-------------------------------- CCCR20 ---------------------------------*/
|
||||
#define SDMMC_SDIO_CCCR20 0x014U /*!< SDIOS Card Common Control Register 20 */
|
||||
#define SDMMC_SDIO_CCCR20_SD_BYTE0 0x014U /*!< SDIOS Card Common Control Register 20 Byte 0 */
|
||||
#define SDMMC_SDIO_CCCR20_SD_BYTE1 0x015U /*!< SDIOS Card Common Control Register 20 Byte 1 */
|
||||
#define SDMMC_SDIO_CCCR20_SD_BYTE2 0x016U /*!< SDIOS Card Common Control Register 20 Byte 2 */
|
||||
#define SDMMC_SDIO_CCCR20_SD_BYTE3 0x017U /*!< SDIOS Card Common Control Register 20 Byte 3 */
|
||||
|
||||
/*-------------------------------- F1BR0 ----------------------------------*/
|
||||
#define SDMMC_SDIO_F1BR0 0x100U /*!< SDIOS Function 1 Basic Register 0 */
|
||||
#define SDMMC_SDIO_F1BR0_SD_BYTE0 0x100U /*!< SDIOS Function 1 Basic Register 0 Byte 0 */
|
||||
#define SDMMC_SDIO_F1BR0_SD_BYTE1 0x101U /*!< SDIOS Function 1 Basic Register 0 Byte 1 */
|
||||
#define SDMMC_SDIO_F1BR0_SD_BYTE2 0x102U /*!< SDIOS Function 1 Basic Register 0 Byte 2 */
|
||||
#define SDMMC_SDIO_F1BR0_SD_BYTE3 0x103U /*!< SDIOS Function 1 Basic Register 0 Byte 3 */
|
||||
|
||||
/*-------------------------------- F1BR8 ----------------------------------*/
|
||||
#define SDMMC_SDIO_F1BR8 0x108U /*!< SDIOS Function 1 Basic Register 8 */
|
||||
#define SDMMC_SDIO_F1BR8_SD_BYTE0 0x108U /*!< SDIOS Function 1 Basic Register 8 Byte 0 */
|
||||
#define SDMMC_SDIO_F1BR8_SD_BYTE1 0x109U /*!< SDIOS Function 1 Basic Register 8 Byte 1 */
|
||||
#define SDMMC_SDIO_F1BR8_SD_BYTE2 0x10AU /*!< SDIOS Function 1 Basic Register 8 Byte 2 */
|
||||
#define SDMMC_SDIO_F1BR8_SD_BYTE3 0x10BU /*!< SDIOS Function 1 Basic Register 8 Byte 3 */
|
||||
|
||||
/*-------------------------------- F1BR12 ---------------------------------*/
|
||||
#define SDMMC_SDIO_F1BR12 0x10CU /*!< SDIOS Function 1 Basic Register 12 */
|
||||
#define SDMMC_SDIO_F1BR12_SD_BYTE0 0x10CU /*!< SDIOS Function 1 Basic Register 12 Byte 0 */
|
||||
#define SDMMC_SDIO_F1BR12_SD_BYTE1 0x10DU /*!< SDIOS Function 1 Basic Register 12 Byte 1 */
|
||||
#define SDMMC_SDIO_F1BR12_SD_BYTE2 0x10EU /*!< SDIOS Function 1 Basic Register 12 Byte 2 */
|
||||
#define SDMMC_SDIO_F1BR12_SD_BYTE3 0x10FU /*!< SDIOS Function 1 Basic Register 12 Byte 3 */
|
||||
|
||||
/*-------------------------------- F1BR16 ---------------------------------*/
|
||||
#define SDMMC_SDIO_F1BR16 0x110U /*!< SDIOS Function 1 Basic Register 16 */
|
||||
#define SDMMC_SDIO_F1BR16_SD_BYTE0 0x110U /*!< SDIOS Function 1 Basic Register 16 Byte 0 */
|
||||
#define SDMMC_SDIO_F1BR16_SD_BYTE1 0x111U /*!< SDIOS Function 1 Basic Register 16 Byte 1 */
|
||||
#define SDMMC_SDIO_F1BR16_SD_BYTE2 0x112U /*!< SDIOS Function 1 Basic Register 16 Byte 2 */
|
||||
#define SDMMC_SDIO_F1BR16_SD_BYTE3 0x113U /*!< SDIOS Function 1 Basic Register 16 Byte 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -871,6 +1000,38 @@ typedef struct
|
||||
*/
|
||||
#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Checks the source of specified interrupt.
|
||||
* @param __INSTANCE__ Pointer to SDMMC register base
|
||||
* @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
|
||||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
|
||||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
|
||||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
|
||||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
|
||||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
|
||||
* @retval The new state of SDMMC_IT (SET or RESET).
|
||||
*/
|
||||
#define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Clears the SDMMC's interrupt pending bits.
|
||||
* @param __INSTANCE__ Pointer to SDMMC register base
|
||||
@ -1009,7 +1170,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
|
||||
/** @addtogroup HAL_SDMMC_LL_Group2
|
||||
* @{
|
||||
*/
|
||||
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx);
|
||||
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
|
||||
/**
|
||||
* @}
|
||||
@ -1022,17 +1183,17 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
|
||||
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
|
||||
HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
|
||||
HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx);
|
||||
|
||||
/* Command path state machine (CPSM) management functions */
|
||||
HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
|
||||
uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
|
||||
HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command);
|
||||
uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response);
|
||||
|
||||
/* Data path state machine (DPSM) management functions */
|
||||
HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data);
|
||||
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
|
||||
HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data);
|
||||
uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx);
|
||||
|
||||
/* SDMMC Cards mode management functions */
|
||||
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
|
||||
@ -1073,6 +1234,10 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount);
|
||||
uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse);
|
||||
uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1084,6 +1249,8 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
|
||||
uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
|
||||
uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
|
||||
uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp);
|
||||
uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData);
|
||||
uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
|
||||
uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
|
||||
/**
|
||||
@ -1106,7 +1273,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* SDMMC1 || SDMMC2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user