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This commit is contained in:
Jasper Blanckenburg
2023-03-05 21:24:12 +01:00
parent f92a5ff28d
commit 2cadbff590
419 changed files with 89874 additions and 19575 deletions
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314
Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
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@ -979,51 +979,51 @@ typedef struct
* @}
*/
#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */
#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */
#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */
#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */
#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */
#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */
#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */
#define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */
#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */
#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */
#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */
#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */
#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
#define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */
#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */
#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */
#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */
#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */
#define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
#define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
#define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */
#define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */
#define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */
#define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
#define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */
#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */
#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */
#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */
#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */
/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
* @{
@ -1219,8 +1219,8 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */
#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */
#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1 OUT */
/**
* @}
*/
@ -1228,8 +1228,8 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */
#define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */
#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
#define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP2 OUT */
/**
* @}
*/
@ -1237,10 +1237,10 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
* @{
*/
#define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */
#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */
#define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */
#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
#define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1 OUT */
#define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2 OUT */
#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
/**
* @}
*/
@ -1248,10 +1248,10 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */
#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */
#define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */
#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1 OUT */
#define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2 OUT */
#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
/**
* @}
*/
@ -1259,9 +1259,9 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */
#define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */
#define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */
#define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
#define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to CAN TMP */
#define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to CAN RTP */
/**
* @}
*/
@ -1269,8 +1269,8 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */
#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */
#define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /*!< TIM12 input 1 is connected to GPIO */
#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 input 1 is connected to SPDIF FS */
/**
* @}
*/
@ -1278,13 +1278,13 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */
#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */
#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */
#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
#define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */
#define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */
#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 CH1 */
#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 CH1 */
#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to TIM4 CH1 */
#define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15 input 1 is connected to RCC LSE */
#define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to RCC CSI */
#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to RCC MCO2 */
/**
* @}
*/
@ -1292,10 +1292,10 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */
#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */
#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */
#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to TIM2 CH2 */
#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM3 CH2 */
#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM4 CH2 */
/**
* @}
*/
@ -1303,10 +1303,10 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */
#define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */
#define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */
#define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
#define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to RCC LSI */
#define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to RCC LSE */
#define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to WKUP_IT */
/**
* @}
*/
@ -1314,10 +1314,10 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */
#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */
#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to SPDIF FS */
#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to RCC HSE 1Mhz */
#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to RCC MCO1 */
/**
* @}
*/
@ -1325,10 +1325,10 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM23_TI4_RMP TIM23 Timer Input Ch4 Remap
* @{
*/
#define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */
#define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */
#define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */
#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
#define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /*!< TIM23 input 4 is connected to GPIO */
#define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23 input 4 is connected to COMP1 OUT */
#define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23 input 4 is connected to COMP2 OUT */
#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
/**
* @}
*/
@ -1336,10 +1336,10 @@ typedef struct
/** @defgroup TIM_LL_EC_TIM24_TI1_RMP TIM24 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */
#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */
#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */
#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
#define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /*!< TIM24 input 1 is connected to GPIO */
#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24 input 1 is connected to CAN TMP */
#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24 input 1 is connected to CAN RTP */
#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */
#if defined(TIM_BREAK_INPUT_SUPPORT)
/** Legacy definitions for compatibility purpose
@ -1382,10 +1382,6 @@ typedef struct
* @}
*/
/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
* @{
*/
/**
* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
@ -1529,7 +1525,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
}
@ -1562,7 +1558,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval Inverted state of bit (0 or 1).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
}
@ -1596,7 +1592,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo
* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
*/
__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
}
@ -1623,7 +1619,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse
* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
*/
__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
}
@ -1667,7 +1663,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
{
uint32_t counter_mode;
@ -1709,7 +1705,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
}
@ -1746,7 +1742,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
*/
__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
}
@ -1773,7 +1769,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
* @param TIMx Timer instance
* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CNT));
}
@ -1786,7 +1782,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
* @arg @ref LL_TIM_COUNTERDIRECTION_UP
* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
*/
__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
}
@ -1813,7 +1809,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
* @param TIMx Timer instance
* @retval Prescaler value between Min_Data=0 and Max_Data=65535
*/
__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->PSC));
}
@ -1842,7 +1838,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload
* @param TIMx Timer instance
* @retval Auto-reload value
*/
__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->ARR));
}
@ -1870,7 +1866,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep
* @param TIMx Timer instance
* @retval Repetition counter value
*/
__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->RCR));
}
@ -1904,7 +1900,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
* @param Counter Counter value
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
{
return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
}
@ -1983,7 +1979,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR
* @arg @ref LL_TIM_CCDMAREQUEST_CC
* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
*/
__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
}
@ -2218,7 +2214,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@ -2284,7 +2280,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
* @arg @ref LL_TIM_OCPOLARITY_HIGH
* @arg @ref LL_TIM_OCPOLARITY_LOW
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
@ -2353,7 +2349,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
* @arg @ref LL_TIM_OCIDLESTATE_LOW
* @arg @ref LL_TIM_OCIDLESTATE_HIGH
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
@ -2722,7 +2718,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR1));
}
@ -2738,7 +2734,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR2));
}
@ -2754,7 +2750,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR3));
}
@ -2770,7 +2766,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR4));
}
@ -2783,7 +2779,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
}
@ -2796,7 +2792,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR6));
}
@ -2916,7 +2912,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_TRC
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@ -2967,7 +2963,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
* @arg @ref LL_TIM_ICPSC_DIV4
* @arg @ref LL_TIM_ICPSC_DIV8
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@ -3042,7 +3038,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@ -3099,7 +3095,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
* @arg @ref LL_TIM_IC_POLARITY_FALLING
* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
@ -3156,7 +3152,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR1));
}
@ -3172,7 +3168,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR2));
}
@ -3188,7 +3184,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR3));
}
@ -3204,7 +3200,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR4));
}
@ -3251,7 +3247,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
}
@ -3443,7 +3439,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
}
@ -3899,7 +3895,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
}
@ -3942,7 +3938,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
}
@ -4211,7 +4207,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
}
@ -4233,7 +4229,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
}
@ -4255,7 +4251,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
}
@ -4277,7 +4273,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
}
@ -4299,7 +4295,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
}
@ -4321,7 +4317,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
}
@ -4343,7 +4339,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
}
@ -4365,7 +4361,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
}
@ -4387,7 +4383,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
}
@ -4409,7 +4405,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
}
@ -4431,7 +4427,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
}
@ -4454,7 +4450,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
}
@ -4477,7 +4473,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
}
@ -4500,7 +4496,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
}
@ -4523,7 +4519,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
}
@ -4545,7 +4541,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
}
@ -4585,7 +4581,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
}
@ -4618,7 +4614,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
}
@ -4651,7 +4647,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
}
@ -4684,7 +4680,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
}
@ -4717,7 +4713,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
}
@ -4750,7 +4746,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
}
@ -4783,7 +4779,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
}
@ -4816,7 +4812,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
}
@ -4856,7 +4852,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
}
@ -4889,7 +4885,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
}
@ -4922,7 +4918,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
}
@ -4955,7 +4951,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
}
@ -4988,7 +4984,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
}
@ -5021,7 +5017,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
}
@ -5054,7 +5050,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
}
@ -5176,17 +5172,17 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
/**
* @}
*/