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@ -20,7 +20,7 @@
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#define STM32H7xx_HAL_RCC_EX_H
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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@ -51,7 +51,7 @@ typedef struct
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uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
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This parameter must be a number between Min_Data = 4 and Max_Data = 512
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or between Min_Data = 8 and Max_Data = 420(*)
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(*) : For stm32h7a3xx and stm32h7b3xx family lines. */
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(*) : For stm32h7a3xx and stm32h7b3xx family lines. */
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uint32_t PLL2P; /*!< PLL2P: Division factor for system clock.
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This parameter must be a number between Min_Data = 2 and Max_Data = 128
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@ -69,7 +69,7 @@ typedef struct
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uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
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PLL2 VCO It should be a value between 0 and 8191 */
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}RCC_PLL2InitTypeDef;
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} RCC_PLL2InitTypeDef;
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/**
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* @brief PLL3 Clock structure definition
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@ -83,7 +83,7 @@ typedef struct
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uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
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This parameter must be a number between Min_Data = 4 and Max_Data = 512
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or between Min_Data = 8 and Max_Data = 420(*)
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(*) : For stm32h7a3xx and stm32h7b3xx family lines. */
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(*) : For stm32h7a3xx and stm32h7b3xx family lines. */
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uint32_t PLL3P; /*!< PLL3P: Division factor for system clock.
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This parameter must be a number between Min_Data = 2 and Max_Data = 128
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@ -101,7 +101,7 @@ typedef struct
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uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
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PLL3 VCO It should be a value between 0 and 8191 */
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}RCC_PLL3InitTypeDef;
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} RCC_PLL3InitTypeDef;
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/**
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* @brief RCC PLL1 Clocks structure definition
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@ -111,7 +111,7 @@ typedef struct
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uint32_t PLL1_P_Frequency;
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uint32_t PLL1_Q_Frequency;
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uint32_t PLL1_R_Frequency;
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}PLL1_ClocksTypeDef;
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} PLL1_ClocksTypeDef;
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/**
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* @brief RCC PLL2 Clocks structure definition
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@ -121,7 +121,7 @@ typedef struct
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uint32_t PLL2_P_Frequency;
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uint32_t PLL2_Q_Frequency;
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uint32_t PLL2_R_Frequency;
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}PLL2_ClocksTypeDef;
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} PLL2_ClocksTypeDef;
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/**
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* @brief RCC PLL3 Clocks structure definition
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@ -131,7 +131,7 @@ typedef struct
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uint32_t PLL3_P_Frequency;
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uint32_t PLL3_Q_Frequency;
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uint32_t PLL3_R_Frequency;
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}PLL3_ClocksTypeDef;
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} PLL3_ClocksTypeDef;
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/**
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@ -139,7 +139,7 @@ typedef struct
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*/
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typedef struct
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{
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uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
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RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters.
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@ -222,14 +222,14 @@ typedef struct
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uint32_t Usart16ClockSelection; /*!< Specifies USART1/6 clock source
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This parameter can be a value of @ref RCCEx_USART16_Clock_Source */
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uint32_t RngClockSelection; /*!< Specifies RNG clock source
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uint32_t RngClockSelection; /*!< Specifies RNG clock source
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This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
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#if defined(I2C5)
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uint32_t I2c1235ClockSelection; /*!< Specifies I2C1/2/3/5 clock source
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uint32_t I2c1235ClockSelection; /*!< Specifies I2C1/2/3/5 clock source
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This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */
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#else
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uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source
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#else
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uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source
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This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */
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#endif /*I2C5*/
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@ -277,7 +277,7 @@ typedef struct
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uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
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This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
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}RCC_PeriphCLKInitTypeDef;
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} RCC_PeriphCLKInitTypeDef;
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/*!< Alias for Inter STM32H7 lines compatibility regarding RCC_PeriphCLKInitTypeDef field : I2C5 available on some lines only */
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#if defined(I2C5)
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@ -311,7 +311,7 @@ typedef struct
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uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
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This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
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}RCC_CRSInitTypeDef;
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} RCC_CRSInitTypeDef;
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/**
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* @brief RCC_CRS Synchronization structure definition
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@ -333,7 +333,7 @@ typedef struct
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It shows whether the actual frequency is below or above the target.
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This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
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}RCC_CRSSynchroInfoTypeDef;
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} RCC_CRSSynchroInfoTypeDef;
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/**
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* @}
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@ -350,7 +350,7 @@ typedef struct
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*/
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#if defined(UART9) && defined(USART10)
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#define RCC_PERIPHCLK_USART16910 (0x00000001U)
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#define RCC_PERIPHCLK_USART16910 ((uint64_t)(0x00000001U))
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#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910
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#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910
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#define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910
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@ -358,40 +358,40 @@ typedef struct
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/*alias*/
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#define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910
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#else
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#define RCC_PERIPHCLK_USART16 (0x00000001U)
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#define RCC_PERIPHCLK_USART16 ((uint64_t)(0x00000001U))
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#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16
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#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16
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/* alias */
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#define RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16
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#endif /* UART9 && USART10*/
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#define RCC_PERIPHCLK_USART234578 (0x00000002U)
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#define RCC_PERIPHCLK_USART234578 ((uint64_t)(0x00000002U))
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#define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578
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#define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578
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#define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578
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#define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578
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#define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
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#define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
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#define RCC_PERIPHCLK_LPUART1 (0x00000004U)
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#define RCC_PERIPHCLK_LPUART1 ((uint64_t)(0x00000004U))
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#if defined(I2C5)
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#define RCC_PERIPHCLK_I2C1235 (0x00000008U)
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#define RCC_PERIPHCLK_I2C1235 ((uint64_t)(0x00000008U))
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#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235
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#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235
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#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235
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/* alias */
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#define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235
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#else
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#define RCC_PERIPHCLK_I2C123 (0x00000008U)
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#define RCC_PERIPHCLK_I2C123 ((uint64_t)(0x00000008U))
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#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
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#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
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#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
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#endif /*I2C5*/
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#define RCC_PERIPHCLK_I2C4 (0x00000010U)
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#define RCC_PERIPHCLK_I2C4 ((uint64_t)(0x00000010U))
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#if defined(I2C5)
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#define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235
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#endif /*I2C5*/
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#define RCC_PERIPHCLK_LPTIM1 (0x00000020U)
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#define RCC_PERIPHCLK_LPTIM2 (0x00000040U)
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#define RCC_PERIPHCLK_LPTIM345 (0x00000080U)
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#define RCC_PERIPHCLK_LPTIM1 ((uint64_t)(0x00000020U))
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#define RCC_PERIPHCLK_LPTIM2 ((uint64_t)(0x00000040U))
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#define RCC_PERIPHCLK_LPTIM345 ((uint64_t)(0x00000080U))
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#define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345
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#if defined(LPTIM4)
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#define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345
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@ -399,59 +399,66 @@ typedef struct
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#if defined(LPTIM5)
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#define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345
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#endif /*LPTIM5*/
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#define RCC_PERIPHCLK_SAI1 (0x00000100U)
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#define RCC_PERIPHCLK_SAI1 ((uint64_t)(0x00000100U))
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#if defined(SAI3)
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#define RCC_PERIPHCLK_SAI23 (0x00000200U)
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#define RCC_PERIPHCLK_SAI23 ((uint64_t)(0x00000200U))
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#define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23
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#define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23
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#endif /* SAI3 */
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#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
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#define RCC_PERIPHCLK_SAI2A (0x00000200U)
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#define RCC_PERIPHCLK_SAI2A ((uint64_t)(0x00000200U))
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#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
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#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
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#define RCC_PERIPHCLK_SAI2B (0x00000400U)
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#define RCC_PERIPHCLK_SAI2B ((uint64_t)(0x00000400U))
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#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
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#if defined(SAI4)
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#define RCC_PERIPHCLK_SAI4A (0x00000400U)
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#define RCC_PERIPHCLK_SAI4B (0x00000800U)
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#define RCC_PERIPHCLK_SAI4A ((uint64_t)(0x00000400U))
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#define RCC_PERIPHCLK_SAI4B ((uint64_t)(0x00000800U))
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#endif /* SAI4 */
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#define RCC_PERIPHCLK_SPI123 (0x00001000U)
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#define RCC_PERIPHCLK_SPI123 ((uint64_t)(0x00001000U))
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#define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123
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#define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123
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#define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123
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#define RCC_PERIPHCLK_SPI45 (0x00002000U)
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#define RCC_PERIPHCLK_SPI45 ((uint64_t)(0x00002000U))
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#define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45
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#define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45
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#define RCC_PERIPHCLK_SPI6 (0x00004000U)
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#define RCC_PERIPHCLK_FDCAN (0x00008000U)
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#define RCC_PERIPHCLK_SDMMC (0x00010000U)
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#define RCC_PERIPHCLK_RNG (0x00020000U)
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#define RCC_PERIPHCLK_USB (0x00040000U)
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#define RCC_PERIPHCLK_ADC (0x00080000U)
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#define RCC_PERIPHCLK_SWPMI1 (0x00100000U)
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#define RCC_PERIPHCLK_DFSDM1 (0x00200000U)
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#define RCC_PERIPHCLK_SPI6 ((uint64_t)(0x00004000U))
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#define RCC_PERIPHCLK_FDCAN ((uint64_t)(0x00008000U))
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#define RCC_PERIPHCLK_SDMMC ((uint64_t)(0x00010000U))
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#define RCC_PERIPHCLK_RNG ((uint64_t)(0x00020000U))
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#define RCC_PERIPHCLK_USB ((uint64_t)(0x00040000U))
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#define RCC_PERIPHCLK_ADC ((uint64_t)(0x00080000U))
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#define RCC_PERIPHCLK_SWPMI1 ((uint64_t)(0x00100000U))
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#define RCC_PERIPHCLK_DFSDM1 ((uint64_t)(0x00200000U))
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#if defined(DFSDM2_BASE)
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#define RCC_PERIPHCLK_DFSDM2 (0x00000800U)
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#define RCC_PERIPHCLK_DFSDM2 ((uint64_t)(0x00000800U))
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#endif /* DFSDM2 */
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#define RCC_PERIPHCLK_RTC (0x00400000U)
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#define RCC_PERIPHCLK_CEC (0x00800000U)
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#define RCC_PERIPHCLK_FMC (0x01000000U)
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#define RCC_PERIPHCLK_RTC ((uint64_t)(0x00400000U))
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#define RCC_PERIPHCLK_CEC ((uint64_t)(0x00800000U))
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#define RCC_PERIPHCLK_FMC ((uint64_t)(0x01000000U))
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#if defined(QUADSPI)
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#define RCC_PERIPHCLK_QSPI (0x02000000U)
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#define RCC_PERIPHCLK_QSPI ((uint64_t)(0x02000000U))
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#endif /* QUADSPI */
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#if defined(OCTOSPI1) || defined(OCTOSPI2)
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#define RCC_PERIPHCLK_OSPI (0x02000000U)
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#define RCC_PERIPHCLK_OSPI ((uint64_t)(0x02000000U))
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#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
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#define RCC_PERIPHCLK_DSI (0x04000000U)
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#define RCC_PERIPHCLK_SPDIFRX (0x08000000U)
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#define RCC_PERIPHCLK_DSI ((uint64_t)(0x04000000U))
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#define RCC_PERIPHCLK_SPDIFRX ((uint64_t)(0x08000000U))
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#if defined(HRTIM1)
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#define RCC_PERIPHCLK_HRTIM1 (0x10000000U)
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#define RCC_PERIPHCLK_HRTIM1 ((uint64_t)(0x10000000U))
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#endif /* HRTIM1 */
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#if defined(LTDC)
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#define RCC_PERIPHCLK_LTDC (0x20000000U)
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#define RCC_PERIPHCLK_LTDC ((uint64_t)(0x20000000U))
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#endif /* LTDC */
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#define RCC_PERIPHCLK_TIM (0x40000000U)
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#define RCC_PERIPHCLK_CKPER (0x80000000U)
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#define RCC_PERIPHCLK_TIM ((uint64_t)(0x40000000U))
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#define RCC_PERIPHCLK_CKPER ((uint64_t)(0x80000000U))
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#define RCC_PERIPHCLK_PLL2_DIVP ((uint64_t)(0x0000000100000000U))
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#define RCC_PERIPHCLK_PLL2_DIVQ ((uint64_t)(0x0000000200000000U))
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#define RCC_PERIPHCLK_PLL2_DIVR ((uint64_t)(0x0000000400000000U))
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#define RCC_PERIPHCLK_PLL3_DIVP ((uint64_t)(0x0000000800000000U))
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#define RCC_PERIPHCLK_PLL3_DIVQ ((uint64_t)(0x0000001000000000U))
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#define RCC_PERIPHCLK_PLL3_DIVR ((uint64_t)(0x0000002000000000U))
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/**
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* @}
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@ -1023,9 +1030,9 @@ typedef struct
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#define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
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#define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2
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#define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* RCC_CDCCIP1R_SAI2ASEL */
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#if defined(RCC_CDCCIP1R_SAI2BSEL)
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@ -1107,18 +1114,18 @@ typedef struct
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* @{
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*/
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#if defined(RCC_D2CCIP1R_SPI45SEL)
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#define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U)
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#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
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#define RCC_SPI45CLKSOURCE_D2PCLK2 (0x00000000U)
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#define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2
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#define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
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#define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
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#define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
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#define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
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#define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
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#else
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#define RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U)
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#define RCC_SPI45CLKSOURCE_CDPCLK2 (0x00000000U)
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/* aliases */
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#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
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#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1
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#define RCC_SPI45CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_CDPCLK2 /* D2PCLK2 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
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#define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CLKSOURCE_CDPCLK2
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#define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0
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#define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1
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#define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
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@ -1132,7 +1139,7 @@ typedef struct
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/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
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* @{
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*/
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#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
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#define RCC_SPI4CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2
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#define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
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#define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
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#define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
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@ -1146,7 +1153,7 @@ typedef struct
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/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
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* @{
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*/
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#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
|
||||
#define RCC_SPI5CLKSOURCE_D2PCLK2 RCC_SPI45CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
|
||||
#define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
|
||||
#define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
|
||||
@ -1972,7 +1979,7 @@ typedef struct
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
|
||||
#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
|
||||
|
||||
/** @brief Macro to select the PLL3 reference frequency range.
|
||||
* @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range
|
||||
@ -3127,12 +3134,12 @@ typedef struct
|
||||
#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
|
||||
#endif /* RCC_D3CCIPR_ADCSEL */
|
||||
|
||||
/** @brief Macro to configure the SWPMI1 clock
|
||||
* @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
|
||||
* @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
|
||||
*/
|
||||
/** @brief Macro to configure the SWPMI1 clock
|
||||
* @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
|
||||
* @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
|
||||
*/
|
||||
#if defined(RCC_D2CCIP1R_SWPSEL)
|
||||
#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
|
||||
MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
|
||||
@ -3152,12 +3159,12 @@ typedef struct
|
||||
#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
|
||||
#endif /* RCC_D2CCIP1R_SWPSEL */
|
||||
|
||||
/** @brief Macro to configure the DFSDM1 clock
|
||||
* @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
|
||||
* @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
|
||||
*/
|
||||
/** @brief Macro to configure the DFSDM1 clock
|
||||
* @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
|
||||
* @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
|
||||
*/
|
||||
#if defined(RCC_D2CCIP1R_DFSDM1SEL)
|
||||
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
|
||||
MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
|
||||
@ -3178,12 +3185,12 @@ typedef struct
|
||||
#endif /* RCC_D2CCIP1R_DFSDM1SEL */
|
||||
|
||||
#if defined(DFSDM2_BASE)
|
||||
/** @brief Macro to configure the DFSDM2 clock
|
||||
* @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock
|
||||
* @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock
|
||||
*/
|
||||
/** @brief Macro to configure the DFSDM2 clock
|
||||
* @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock
|
||||
* @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock
|
||||
*/
|
||||
#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
|
||||
MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
|
||||
|
||||
@ -3391,7 +3398,7 @@ typedef struct
|
||||
* @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived
|
||||
* from system PCLK, PLL2, PLL3, OSC
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
|
||||
* @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2
|
||||
* @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
|
||||
* @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
|
||||
* @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
|
||||
@ -3409,7 +3416,7 @@ typedef struct
|
||||
|
||||
/** @brief Macro to get the SPI4/5 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
|
||||
* @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2
|
||||
* @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
|
||||
* @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
|
||||
* @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
|
||||
@ -3427,7 +3434,7 @@ typedef struct
|
||||
* @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived
|
||||
* from system PCLK, PLL2, PLL3, OSC
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
|
||||
* @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2
|
||||
* @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
|
||||
* @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
|
||||
* @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
|
||||
@ -3439,7 +3446,7 @@ typedef struct
|
||||
|
||||
/** @brief Macro to get the SPI4 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
|
||||
* @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2
|
||||
* @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
|
||||
* @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
|
||||
* @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
|
||||
@ -3453,7 +3460,7 @@ typedef struct
|
||||
* @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived
|
||||
* from system PCLK, PLL2, PLL3, OSC
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
|
||||
* @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2
|
||||
* @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
|
||||
* @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
|
||||
* @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
|
||||
@ -3465,7 +3472,7 @@ typedef struct
|
||||
|
||||
/** @brief Macro to get the SPI5 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
|
||||
* @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2
|
||||
* @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
|
||||
* @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
|
||||
* @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
|
||||
@ -3726,7 +3733,7 @@ typedef struct
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CRS interrupts.
|
||||
* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
|
||||
@ -3831,9 +3838,9 @@ typedef struct
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the oscillator clock for frequency error counter.
|
||||
* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
|
||||
@ -3884,22 +3891,22 @@ typedef struct
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RCCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup RCCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
|
||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk);
|
||||
uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
|
||||
uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
|
||||
uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
|
||||
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
|
||||
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
|
||||
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
|
||||
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks);
|
||||
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks);
|
||||
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -3947,7 +3954,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
@ -4112,7 +4119,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
||||
#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \
|
||||
((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \
|
||||
((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
|
||||
((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
|
||||
((SOURCE) == RCC_I2C4CLKSOURCE_CSI))
|
||||
|
||||
#if defined(I2C5)
|
||||
#define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \
|
||||
@ -4215,7 +4222,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
||||
((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
|
||||
|
||||
#define IS_RCC_SPI45CLK(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \
|
||||
(((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || \
|
||||
((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \
|
||||
((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \
|
||||
((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \
|
||||
@ -4223,7 +4230,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
||||
((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
|
||||
|
||||
#define IS_RCC_SPI4CLK(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \
|
||||
(((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || \
|
||||
((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \
|
||||
((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \
|
||||
((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \
|
||||
@ -4231,7 +4238,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
||||
((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
|
||||
|
||||
#define IS_RCC_SPI5CLK(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
|
||||
(((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \
|
||||
((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \
|
||||
((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \
|
||||
((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \
|
||||
|
||||
Reference in New Issue
Block a user