Use AzureRTOS ThreadX
This commit is contained in:
@ -48,15 +48,15 @@ extern "C" {
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#endif /* ETH_RX_DESC_CNT */
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#ifndef ETH_SWRESET_TIMEOUT
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#define ETH_SWRESET_TIMEOUT ((uint32_t)500U)
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#define ETH_SWRESET_TIMEOUT 500U
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#endif /* ETH_SWRESET_TIMEOUT */
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#ifndef ETH_MDIO_BUS_TIMEOUT
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#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
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#define ETH_MDIO_BUS_TIMEOUT 1000U
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#endif /* ETH_MDIO_BUS_TIMEOUT */
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#ifndef ETH_MAC_US_TICK
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#define ETH_MAC_US_TICK ((uint32_t)1000000U)
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#define ETH_MAC_US_TICK 1000000U
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#endif /* ETH_MAC_US_TICK */
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/*********************** Descriptors struct def section ************************/
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@ -178,6 +178,7 @@ typedef struct
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*
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*/
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#ifdef HAL_ETH_USE_PTP
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/**
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* @brief ETH Timeupdate structure definition
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*/
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@ -189,6 +190,7 @@ typedef struct
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/**
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*
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*/
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#endif /* HAL_ETH_USE_PTP */
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/**
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* @brief DMA Receive Descriptors Wrapper structure definition
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@ -400,6 +402,7 @@ typedef enum
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*
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*/
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#ifdef HAL_ETH_USE_PTP
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/**
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* @brief HAL ETH PTP Update type enum definition
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*/
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@ -411,6 +414,7 @@ typedef enum
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/**
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*
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*/
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#endif /* HAL_ETH_USE_PTP */
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/**
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* @brief ETH Init Structure definition
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@ -436,6 +440,7 @@ typedef struct
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*
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*/
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#ifdef HAL_ETH_USE_PTP
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/**
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* @brief ETH PTP Init Structure definition
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*/
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@ -466,6 +471,7 @@ typedef struct
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/**
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*
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*/
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#endif /* HAL_ETH_USE_PTP */
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/**
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* @brief HAL State structures definition
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@ -689,58 +695,58 @@ typedef struct
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/**
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* @brief Bit definition of TDES0 RF register
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*/
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#define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */
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#define ETH_DMATXNDESCRF_B1AP 0xFFFFFFFFU /*!< Transmit Packet Timestamp Low */
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/**
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* @brief Bit definition of TDES1 RF register
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*/
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#define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */
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#define ETH_DMATXNDESCRF_B2AP 0xFFFFFFFFU /*!< Transmit Packet Timestamp High */
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/**
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* @brief Bit definition of TDES2 RF register
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*/
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#define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) /*!< Interrupt on Completion */
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#define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) /*!< Transmit Timestamp Enable */
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#define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) /*!< Buffer 2 Length */
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#define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) /*!< VLAN Tag Insertion or Replacement mask */
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#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add a VLAN tag. */
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#define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) /*!< Remove the VLAN tag from the packets before transmission. */
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#define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) /*!< Insert a VLAN tag. */
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#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) /*!< Replace the VLAN tag. */
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#define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) /*!< Buffer 1 Length */
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#define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) /*!< Header Length */
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#define ETH_DMATXNDESCRF_IOC 0x80000000U /*!< Interrupt on Completion */
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#define ETH_DMATXNDESCRF_TTSE 0x40000000U /*!< Transmit Timestamp Enable */
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#define ETH_DMATXNDESCRF_B2L 0x3FFF0000U /*!< Buffer 2 Length */
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#define ETH_DMATXNDESCRF_VTIR 0x0000C000U /*!< VLAN Tag Insertion or Replacement mask */
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#define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U /*!< Do not add a VLAN tag. */
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#define ETH_DMATXNDESCRF_VTIR_REMOVE 0x00004000U /*!< Remove the VLAN tag from the packets before transmission. */
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#define ETH_DMATXNDESCRF_VTIR_INSERT 0x00008000U /*!< Insert a VLAN tag. */
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#define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U /*!< Replace the VLAN tag. */
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#define ETH_DMATXNDESCRF_B1L 0x00003FFFU /*!< Buffer 1 Length */
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#define ETH_DMATXNDESCRF_HL 0x000003FFU /*!< Header Length */
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/**
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* @brief Bit definition of TDES3 RF register
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*/
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#define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
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#define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
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#define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
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#define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) /*!< CRC Pad Control mask */
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#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) /*!< CRC Pad Control: CRC and Pad Insertion */
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#define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
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#define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) /*!< CRC Pad Control: Disable CRC Insertion */
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#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) /*!< CRC Pad Control: CRC Replacement */
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#define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) /*!< SA Insertion Control mask*/
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#define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) /*!< SA Insertion Control: Do not include the source address */
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#define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) /*!< SA Insertion Control: Include or insert the source address */
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#define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) /*!< SA Insertion Control: Replace the source address */
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#define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) /*!< TCP Header Length */
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#define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) /*!< TCP segmentation enable */
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#define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) /*!< Checksum Insertion Control: 4 cases */
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#define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is disabled */
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#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /*!< Only IP header checksum calculation and insertion are enabled. */
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#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are
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enabled, but pseudo header
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checksum is not
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calculated in hardware */
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#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are
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enabled, and pseudo header
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checksum is
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calculated in hardware. */
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#define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /*!< TCP Payload Length */
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#define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /*!< Transmit End of Ring */
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#define ETH_DMATXNDESCRF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATXNDESCRF_CTXT 0x40000000U /*!< Context Type */
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#define ETH_DMATXNDESCRF_FD 0x20000000U /*!< First Descriptor */
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#define ETH_DMATXNDESCRF_LD 0x10000000U /*!< Last Descriptor */
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#define ETH_DMATXNDESCRF_CPC 0x0C000000U /*!< CRC Pad Control mask */
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#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT 0x00000000U /*!< CRC Pad Control: CRC and Pad Insertion */
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#define ETH_DMATXNDESCRF_CPC_CRC_INSERT 0x04000000U /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
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#define ETH_DMATXNDESCRF_CPC_DISABLE 0x08000000U /*!< CRC Pad Control: Disable CRC Insertion */
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#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE 0x0C000000U /*!< CRC Pad Control: CRC Replacement */
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#define ETH_DMATXNDESCRF_SAIC 0x03800000U /*!< SA Insertion Control mask*/
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#define ETH_DMATXNDESCRF_SAIC_DISABLE 0x00000000U /*!< SA Insertion Control: Do not include the source address */
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#define ETH_DMATXNDESCRF_SAIC_INSERT 0x00800000U /*!< SA Insertion Control: Include or insert the source address */
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#define ETH_DMATXNDESCRF_SAIC_REPLACE 0x01000000U /*!< SA Insertion Control: Replace the source address */
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#define ETH_DMATXNDESCRF_THL 0x00780000U /*!< TCP Header Length */
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#define ETH_DMATXNDESCRF_TSE 0x00040000U /*!< TCP segmentation enable */
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#define ETH_DMATXNDESCRF_CIC 0x00030000U /*!< Checksum Insertion Control: 4 cases */
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#define ETH_DMATXNDESCRF_CIC_DISABLE 0x00000000U /*!< Do Nothing: Checksum Engine is disabled */
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#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 0x00010000U /*!< Only IP header checksum calculation and insertion are enabled. */
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#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 0x00020000U /*!< IP header checksum and payload checksum calculation and insertion are
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enabled, but pseudo header
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checksum is not
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calculated in hardware */
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#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 0x00030000U /*!< IP Header checksum and payload checksum calculation and insertion are
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enabled, and pseudo header
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checksum is
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calculated in hardware. */
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#define ETH_DMATXNDESCRF_TPL 0x0003FFFFU /*!< TCP Payload Length */
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#define ETH_DMATXNDESCRF_FL 0x00007FFFU /*!< Transmit End of Ring */
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/*
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DMA Tx Normal Descriptor Write Back Format
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@ -758,36 +764,36 @@ typedef struct
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/**
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* @brief Bit definition of TDES0 WBF register
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*/
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#define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
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#define ETH_DMATXNDESCWBF_TTSL 0xFFFFFFFFU /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
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/**
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* @brief Bit definition of TDES1 WBF register
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*/
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#define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
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#define ETH_DMATXNDESCWBF_TTSH 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
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/**
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* @brief Bit definition of TDES3 WBF register
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*/
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#define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
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#define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
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#define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
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#define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) /*!< Tx Timestamp Status */
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#define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) /*!< Disable Padding */
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#define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) /*!< Transmit Timestamp Enable */
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#define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
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#define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */
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#define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
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#define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */
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#define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */
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#define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */
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#define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */
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#define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */
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#define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) /*!< Collision Count */
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#define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) /*!< Excessive Deferral */
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#define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) /*!< Underflow Error: late data arrival from the memory */
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#define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) /*!< Deferred Bit */
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#define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) /*!< IP Header Error */
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#define ETH_DMATXNDESCWBF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATXNDESCWBF_CTXT 0x40000000U /*!< Context Type */
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#define ETH_DMATXNDESCWBF_FD 0x20000000U /*!< First Descriptor */
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#define ETH_DMATXNDESCWBF_LD 0x10000000U /*!< Last Descriptor */
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#define ETH_DMATXNDESCWBF_TTSS 0x00020000U /*!< Tx Timestamp Status */
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#define ETH_DMATXNDESCWBF_DP 0x04000000U /*!< Disable Padding */
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#define ETH_DMATXNDESCWBF_TTSE 0x02000000U /*!< Transmit Timestamp Enable */
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#define ETH_DMATXNDESCWBF_ES 0x00008000U /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
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#define ETH_DMATXNDESCWBF_JT 0x00004000U /*!< Jabber Timeout */
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#define ETH_DMATXNDESCWBF_FF 0x00002000U /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
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#define ETH_DMATXNDESCWBF_PCE 0x00001000U /*!< Payload Checksum Error */
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#define ETH_DMATXNDESCWBF_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
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#define ETH_DMATXNDESCWBF_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
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#define ETH_DMATXNDESCWBF_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
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#define ETH_DMATXNDESCWBF_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
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#define ETH_DMATXNDESCWBF_CC 0x000000F0U /*!< Collision Count */
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#define ETH_DMATXNDESCWBF_ED 0x00000008U /*!< Excessive Deferral */
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#define ETH_DMATXNDESCWBF_UF 0x00000004U /*!< Underflow Error: late data arrival from the memory */
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#define ETH_DMATXNDESCWBF_DB 0x00000002U /*!< Deferred Bit */
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#define ETH_DMATXNDESCWBF_IHE 0x00000004U /*!< IP Header Error */
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/*
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@ -806,35 +812,35 @@ typedef struct
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/**
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* @brief Bit definition of Tx context descriptor register 0
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*/
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#define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */
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#define ETH_DMATXCDESC_TTSL 0xFFFFFFFFU /*!< Transmit Packet Timestamp Low */
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/**
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* @brief Bit definition of Tx context descriptor register 1
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*/
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#define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */
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#define ETH_DMATXCDESC_TTSH 0xFFFFFFFFU /*!< Transmit Packet Timestamp High */
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/**
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* @brief Bit definition of Tx context descriptor register 2
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*/
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#define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */
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#define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) /*!< Maximum Segment Size */
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#define ETH_DMATXCDESC_IVT 0xFFFF0000U /*!< Inner VLAN Tag */
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#define ETH_DMATXCDESC_MSS 0x00003FFFU /*!< Maximum Segment Size */
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/**
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* @brief Bit definition of Tx context descriptor register 3
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*/
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#define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
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#define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) /*!< One-Step Timestamp Correction Enable */
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#define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) /*!< One-Step Timestamp Correction Input or MSS Valid */
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#define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) /*!< Context Descriptor Error */
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#define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) /*!< Inner VLAN Tag Insert or Replace Mask */
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#define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add the inner VLAN tag. */
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#define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) /*!< Remove the inner VLAN tag from the packets before transmission. */
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#define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) /*!< Insert the inner VLAN tag. */
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#define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) /*!< Replace the inner VLAN tag. */
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#define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) /*!< Inner VLAN Tag Valid */
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#define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) /*!< VLAN Tag Valid */
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#define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) /*!< VLAN Tag */
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#define ETH_DMATXCDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATXCDESC_CTXT 0x40000000U /*!< Context Type */
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#define ETH_DMATXCDESC_OSTC 0x08000000U /*!< One-Step Timestamp Correction Enable */
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#define ETH_DMATXCDESC_TCMSSV 0x04000000U /*!< One-Step Timestamp Correction Input or MSS Valid */
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#define ETH_DMATXCDESC_CDE 0x00800000U /*!< Context Descriptor Error */
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#define ETH_DMATXCDESC_IVTIR 0x000C0000U /*!< Inner VLAN Tag Insert or Replace Mask */
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#define ETH_DMATXCDESC_IVTIR_DISABLE 0x00000000U /*!< Do not add the inner VLAN tag. */
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#define ETH_DMATXCDESC_IVTIR_REMOVE 0x00040000U /*!< Remove the inner VLAN tag from the packets before transmission. */
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#define ETH_DMATXCDESC_IVTIR_INSERT 0x00080000U /*!< Insert the inner VLAN tag. */
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#define ETH_DMATXCDESC_IVTIR_REPLACE 0x000C0000U /*!< Replace the inner VLAN tag. */
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#define ETH_DMATXCDESC_IVLTV 0x00020000U /*!< Inner VLAN Tag Valid */
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#define ETH_DMATXCDESC_VLTV 0x00010000U /*!< VLAN Tag Valid */
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#define ETH_DMATXCDESC_VT 0x0000FFFFU /*!< VLAN Tag */
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/**
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* @}
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@ -861,20 +867,20 @@ typedef struct
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/**
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* @brief Bit definition of Rx normal descriptor register 0 read format
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*/
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#define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) /*!< Header or Buffer 1 Address Pointer */
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#define ETH_DMARXNDESCRF_BUF1AP 0xFFFFFFFFU /*!< Header or Buffer 1 Address Pointer */
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/**
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* @brief Bit definition of Rx normal descriptor register 2 read format
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*/
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#define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer 2 Address Pointer */
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#define ETH_DMARXNDESCRF_BUF2AP 0xFFFFFFFFU /*!< Buffer 2 Address Pointer */
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/**
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* @brief Bit definition of Rx normal descriptor register 3 read format
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||||
*/
|
||||
#define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
|
||||
#define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) /*!< Interrupt Enabled on Completion */
|
||||
#define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) /*!< Buffer 2 Address Valid */
|
||||
#define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) /*!< Buffer 1 Address Valid */
|
||||
#define ETH_DMARXNDESCRF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
|
||||
#define ETH_DMARXNDESCRF_IOC 0x40000000U /*!< Interrupt Enabled on Completion */
|
||||
#define ETH_DMARXNDESCRF_BUF2V 0x02000000U /*!< Buffer 2 Address Valid */
|
||||
#define ETH_DMARXNDESCRF_BUF1V 0x01000000U /*!< Buffer 1 Address Valid */
|
||||
|
||||
/*
|
||||
DMA Rx Normal Descriptor write back format
|
||||
@ -892,80 +898,80 @@ typedef struct
|
||||
/**
|
||||
* @brief Bit definition of Rx normal descriptor register 0 write back format
|
||||
*/
|
||||
#define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */
|
||||
#define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) /*!< Outer VLAN Tag */
|
||||
#define ETH_DMARXNDESCWBF_IVT 0xFFFF0000U /*!< Inner VLAN Tag */
|
||||
#define ETH_DMARXNDESCWBF_OVT 0x0000FFFFU /*!< Outer VLAN Tag */
|
||||
|
||||
/**
|
||||
* @brief Bit definition of Rx normal descriptor register 1 write back format
|
||||
*/
|
||||
#define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) /*!< OAM Sub-Type Code, or MAC Control Packet opcode */
|
||||
#define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) /*!< Timestamp Dropped */
|
||||
#define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) /*!< Timestamp Available */
|
||||
#define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) /*!< PTP Version */
|
||||
#define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) /*!< PTP Packet Type */
|
||||
#define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) /*!< PTP Message Type: No PTP message received */
|
||||
#define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) /*!< PTP Message Type: SYNC (all clock types) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) /*!< PTP Message Type: Follow_Up (all clock types) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) /*!< PTP Message Type: Delay_Req (all clock types) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) /*!< PTP Message Type: Delay_Resp (all clock types) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) /*!< PTP Message Type: Announce */
|
||||
#define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) /*!< PTP Message Type: Management */
|
||||
#define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) /*!< PTP Message Type: Signaling */
|
||||
#define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) /*!< PTP Message Type: PTP packet with Reserved message type */
|
||||
#define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) /*!< IP Payload Error */
|
||||
#define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) /*!< IP Checksum Bypassed */
|
||||
#define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) /*!< IPv6 header Present */
|
||||
#define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) /*!< IPv4 header Present */
|
||||
#define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) /*!< IP Header Error */
|
||||
#define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) /*!< Payload Type mask */
|
||||
#define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) /*!< Payload Type: Unknown type or IP/AV payload not processed */
|
||||
#define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) /*!< Payload Type: UDP */
|
||||
#define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) /*!< Payload Type: TCP */
|
||||
#define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) /*!< Payload Type: ICMP */
|
||||
#define ETH_DMARXNDESCWBF_OPC 0xFFFF0000U /*!< OAM Sub-Type Code, or MAC Control Packet opcode */
|
||||
#define ETH_DMARXNDESCWBF_TD 0x00008000U /*!< Timestamp Dropped */
|
||||
#define ETH_DMARXNDESCWBF_TSA 0x00004000U /*!< Timestamp Available */
|
||||
#define ETH_DMARXNDESCWBF_PV 0x00002000U /*!< PTP Version */
|
||||
#define ETH_DMARXNDESCWBF_PFT 0x00001000U /*!< PTP Packet Type */
|
||||
#define ETH_DMARXNDESCWBF_PMT_NO 0x00000000U /*!< PTP Message Type: No PTP message received */
|
||||
#define ETH_DMARXNDESCWBF_PMT_SYNC 0x00000100U /*!< PTP Message Type: SYNC (all clock types) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_FUP 0x00000200U /*!< PTP Message Type: Follow_Up (all clock types) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_DREQ 0x00000300U /*!< PTP Message Type: Delay_Req (all clock types) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_DRESP 0x00000400U /*!< PTP Message Type: Delay_Resp (all clock types) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_PDREQ 0x00000500U /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_PDRESP 0x00000600U /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP 0x00000700U /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */
|
||||
#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE 0x00000800U /*!< PTP Message Type: Announce */
|
||||
#define ETH_DMARXNDESCWBF_PMT_MANAG 0x00000900U /*!< PTP Message Type: Management */
|
||||
#define ETH_DMARXNDESCWBF_PMT_SIGN 0x00000A00U /*!< PTP Message Type: Signaling */
|
||||
#define ETH_DMARXNDESCWBF_PMT_RESERVED 0x00000F00U /*!< PTP Message Type: PTP packet with Reserved message type */
|
||||
#define ETH_DMARXNDESCWBF_IPCE 0x00000080U /*!< IP Payload Error */
|
||||
#define ETH_DMARXNDESCWBF_IPCB 0x00000040U /*!< IP Checksum Bypassed */
|
||||
#define ETH_DMARXNDESCWBF_IPV6 0x00000020U /*!< IPv6 header Present */
|
||||
#define ETH_DMARXNDESCWBF_IPV4 0x00000010U /*!< IPv4 header Present */
|
||||
#define ETH_DMARXNDESCWBF_IPHE 0x00000008U /*!< IP Header Error */
|
||||
#define ETH_DMARXNDESCWBF_PT 0x00000003U /*!< Payload Type mask */
|
||||
#define ETH_DMARXNDESCWBF_PT_UNKNOWN 0x00000000U /*!< Payload Type: Unknown type or IP/AV payload not processed */
|
||||
#define ETH_DMARXNDESCWBF_PT_UDP 0x00000001U /*!< Payload Type: UDP */
|
||||
#define ETH_DMARXNDESCWBF_PT_TCP 0x00000002U /*!< Payload Type: TCP */
|
||||
#define ETH_DMARXNDESCWBF_PT_ICMP 0x00000003U /*!< Payload Type: ICMP */
|
||||
|
||||
/**
|
||||
* @brief Bit definition of Rx normal descriptor register 2 write back format
|
||||
*/
|
||||
#define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
|
||||
#define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) /*!< Layer 4 Filter Match */
|
||||
#define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) /*!< Layer 3 Filter Match */
|
||||
#define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) /*!< MAC Address Match or Hash Value */
|
||||
#define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) /*!< Hash Filter Status */
|
||||
#define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) /*!< Destination Address Filter Fail */
|
||||
#define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) /*!< SA Address Filter Fail */
|
||||
#define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) /*!< VLAN Filter Status */
|
||||
#define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) /*!< ARP Reply Not Generated */
|
||||
#define ETH_DMARXNDESCWBF_L3L4FM 0x20000000U /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
|
||||
#define ETH_DMARXNDESCWBF_L4FM 0x10000000U /*!< Layer 4 Filter Match */
|
||||
#define ETH_DMARXNDESCWBF_L3FM 0x08000000U /*!< Layer 3 Filter Match */
|
||||
#define ETH_DMARXNDESCWBF_MADRM 0x07F80000U /*!< MAC Address Match or Hash Value */
|
||||
#define ETH_DMARXNDESCWBF_HF 0x00040000U /*!< Hash Filter Status */
|
||||
#define ETH_DMARXNDESCWBF_DAF 0x00020000U /*!< Destination Address Filter Fail */
|
||||
#define ETH_DMARXNDESCWBF_SAF 0x00010000U /*!< SA Address Filter Fail */
|
||||
#define ETH_DMARXNDESCWBF_VF 0x00008000U /*!< VLAN Filter Status */
|
||||
#define ETH_DMARXNDESCWBF_ARPNR 0x00000400U /*!< ARP Reply Not Generated */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Bit definition of Rx normal descriptor register 3 write back format
|
||||
*/
|
||||
#define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< Own Bit */
|
||||
#define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */
|
||||
#define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
|
||||
#define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
|
||||
#define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) /*!< Receive Status RDES2 Valid */
|
||||
#define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) /*!< Receive Status RDES1 Valid */
|
||||
#define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) /*!< Receive Status RDES0 Valid */
|
||||
#define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) /*!< CRC Error */
|
||||
#define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) /*!< Giant Packet */
|
||||
#define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) /*!< Receive Watchdog Timeout */
|
||||
#define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) /*!< Overflow Error */
|
||||
#define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) /*!< Receive Error */
|
||||
#define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) /*!< Dribble Bit Error */
|
||||
#define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) /*!< Length/Type Field */
|
||||
#define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) /*!< The packet is a length packet */
|
||||
#define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) /*!< The packet is a type packet */
|
||||
#define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) /*!< The packet is a ARP Request packet type */
|
||||
#define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) /*!< The packet is a type packet with VLAN Tag */
|
||||
#define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) /*!< The packet is a type packet with Double VLAN Tag */
|
||||
#define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) /*!< The packet is a MAC Control packet type */
|
||||
#define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) /*!< The packet is a OAM packet type */
|
||||
#define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error Summary */
|
||||
#define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) /*!< Packet Length */
|
||||
#define ETH_DMARXNDESCWBF_OWN 0x80000000U /*!< Own Bit */
|
||||
#define ETH_DMARXNDESCWBF_CTXT 0x40000000U /*!< Receive Context Descriptor */
|
||||
#define ETH_DMARXNDESCWBF_FD 0x20000000U /*!< First Descriptor */
|
||||
#define ETH_DMARXNDESCWBF_LD 0x10000000U /*!< Last Descriptor */
|
||||
#define ETH_DMARXNDESCWBF_RS2V 0x08000000U /*!< Receive Status RDES2 Valid */
|
||||
#define ETH_DMARXNDESCWBF_RS1V 0x04000000U /*!< Receive Status RDES1 Valid */
|
||||
#define ETH_DMARXNDESCWBF_RS0V 0x02000000U /*!< Receive Status RDES0 Valid */
|
||||
#define ETH_DMARXNDESCWBF_CE 0x01000000U /*!< CRC Error */
|
||||
#define ETH_DMARXNDESCWBF_GP 0x00800000U /*!< Giant Packet */
|
||||
#define ETH_DMARXNDESCWBF_RWT 0x00400000U /*!< Receive Watchdog Timeout */
|
||||
#define ETH_DMARXNDESCWBF_OE 0x00200000U /*!< Overflow Error */
|
||||
#define ETH_DMARXNDESCWBF_RE 0x00100000U /*!< Receive Error */
|
||||
#define ETH_DMARXNDESCWBF_DE 0x00080000U /*!< Dribble Bit Error */
|
||||
#define ETH_DMARXNDESCWBF_LT 0x00070000U /*!< Length/Type Field */
|
||||
#define ETH_DMARXNDESCWBF_LT_LP 0x00000000U /*!< The packet is a length packet */
|
||||
#define ETH_DMARXNDESCWBF_LT_TP 0x00010000U /*!< The packet is a type packet */
|
||||
#define ETH_DMARXNDESCWBF_LT_ARP 0x00030000U /*!< The packet is a ARP Request packet type */
|
||||
#define ETH_DMARXNDESCWBF_LT_VLAN 0x00040000U /*!< The packet is a type packet with VLAN Tag */
|
||||
#define ETH_DMARXNDESCWBF_LT_DVLAN 0x00050000U /*!< The packet is a type packet with Double VLAN Tag */
|
||||
#define ETH_DMARXNDESCWBF_LT_MAC 0x00060000U /*!< The packet is a MAC Control packet type */
|
||||
#define ETH_DMARXNDESCWBF_LT_OAM 0x00070000U /*!< The packet is a OAM packet type */
|
||||
#define ETH_DMARXNDESCWBF_ES 0x00008000U /*!< Error Summary */
|
||||
#define ETH_DMARXNDESCWBF_PL 0x00007FFFU /*!< Packet Length */
|
||||
|
||||
/*
|
||||
DMA Rx context Descriptor
|
||||
@ -983,18 +989,18 @@ typedef struct
|
||||
/**
|
||||
* @brief Bit definition of Rx context descriptor register 0
|
||||
*/
|
||||
#define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp Low */
|
||||
#define ETH_DMARXCDESC_RTSL 0xFFFFFFFFU /*!< Receive Packet Timestamp Low */
|
||||
|
||||
/**
|
||||
* @brief Bit definition of Rx context descriptor register 1
|
||||
*/
|
||||
#define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp High */
|
||||
#define ETH_DMARXCDESC_RTSH 0xFFFFFFFFU /*!< Receive Packet Timestamp High */
|
||||
|
||||
/**
|
||||
* @brief Bit definition of Rx context descriptor register 3
|
||||
*/
|
||||
#define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) /*!< Own Bit */
|
||||
#define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */
|
||||
#define ETH_DMARXCDESC_OWN 0x80000000U /*!< Own Bit */
|
||||
#define ETH_DMARXCDESC_CTXT 0x40000000U /*!< Receive Context Descriptor */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -1003,13 +1009,13 @@ typedef struct
|
||||
/** @defgroup ETH_Frame_settings ETH frame settings
|
||||
* @{
|
||||
*/
|
||||
#define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
|
||||
#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
|
||||
#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */
|
||||
#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
|
||||
#define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */
|
||||
#define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
|
||||
#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */
|
||||
#define ETH_MAX_PACKET_SIZE 1528U /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
|
||||
#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
|
||||
#define ETH_CRC 4U /*!< Ethernet CRC */
|
||||
#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
|
||||
#define ETH_MIN_PAYLOAD 46U /*!< Minimum Ethernet payload size */
|
||||
#define ETH_MAX_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
|
||||
#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1017,14 +1023,14 @@ typedef struct
|
||||
/** @defgroup ETH_Error_Code ETH Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */
|
||||
#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */
|
||||
#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
|
||||
#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
|
||||
#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */
|
||||
#define HAL_ETH_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_ETH_ERROR_PARAM 0x00000001U /*!< Busy error */
|
||||
#define HAL_ETH_ERROR_BUSY 0x00000002U /*!< Parameter error */
|
||||
#define HAL_ETH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */
|
||||
#define HAL_ETH_ERROR_DMA 0x00000008U /*!< DMA transfer error */
|
||||
#define HAL_ETH_ERROR_MAC 0x00000010U /*!< MAC transfer error */
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
|
||||
#define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
@ -1033,12 +1039,12 @@ typedef struct
|
||||
/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
|
||||
* @{
|
||||
*/
|
||||
#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
|
||||
#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
|
||||
#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
|
||||
#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
|
||||
#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
|
||||
#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
|
||||
#define ETH_TX_PACKETS_FEATURES_CSUM 0x00000001U
|
||||
#define ETH_TX_PACKETS_FEATURES_SAIC 0x00000002U
|
||||
#define ETH_TX_PACKETS_FEATURES_VLANTAG 0x00000004U
|
||||
#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG 0x00000008U
|
||||
#define ETH_TX_PACKETS_FEATURES_TSO 0x00000010U
|
||||
#define ETH_TX_PACKETS_FEATURES_CRCPAD 0x00000020U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1172,7 +1178,7 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
#define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
|
||||
#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
|
||||
#define ETH_DMAARBITRATION_RX1_TX1 0x00000000U
|
||||
#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
|
||||
#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
|
||||
#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
|
||||
@ -1181,7 +1187,7 @@ typedef struct
|
||||
#define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
|
||||
#define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
|
||||
#define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
|
||||
#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
|
||||
#define ETH_DMAARBITRATION_TX1_RX1 0x00000000U
|
||||
#define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
|
||||
#define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
|
||||
#define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
|
||||
@ -1198,7 +1204,7 @@ typedef struct
|
||||
*/
|
||||
#define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
|
||||
#define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
|
||||
#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
|
||||
#define ETH_BURSTLENGTH_UNSPECIFIED 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1252,12 +1258,12 @@ typedef struct
|
||||
/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
|
||||
* @{
|
||||
*/
|
||||
#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
|
||||
#define ETH_DMA_RX_NO_ERROR_FLAG 0x00000000U
|
||||
#define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
|
||||
#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
|
||||
#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
|
||||
#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
|
||||
#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
|
||||
#define ETH_DMA_TX_NO_ERROR_FLAG 0x00000000U
|
||||
#define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
|
||||
#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
|
||||
#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
|
||||
@ -1354,7 +1360,7 @@ typedef struct
|
||||
/** @defgroup ETH_Speed ETH Speed
|
||||
* @{
|
||||
*/
|
||||
#define ETH_SPEED_10M ((uint32_t)0x00000000U)
|
||||
#define ETH_SPEED_10M 0x00000000U
|
||||
#define ETH_SPEED_100M ETH_MACCR_FES
|
||||
/**
|
||||
* @}
|
||||
@ -1364,7 +1370,7 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
#define ETH_FULLDUPLEX_MODE ETH_MACCR_DM
|
||||
#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
|
||||
#define ETH_HALFDUPLEX_MODE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1393,7 +1399,7 @@ typedef struct
|
||||
/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
|
||||
* @{
|
||||
*/
|
||||
#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
|
||||
#define ETH_SOURCEADDRESS_DISABLE 0x00000000U
|
||||
#define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
|
||||
#define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
|
||||
#define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
|
||||
@ -1416,7 +1422,7 @@ typedef struct
|
||||
/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
|
||||
#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
|
||||
#define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV
|
||||
/**
|
||||
* @}
|
||||
@ -1425,10 +1431,10 @@ typedef struct
|
||||
/** @defgroup ETH_MAC_addresses ETH MAC addresses
|
||||
* @{
|
||||
*/
|
||||
#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
|
||||
#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
|
||||
#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
|
||||
#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
|
||||
#define ETH_MAC_ADDRESS0 0x00000000U
|
||||
#define ETH_MAC_ADDRESS1 0x00000008U
|
||||
#define ETH_MAC_ADDRESS2 0x00000010U
|
||||
#define ETH_MAC_ADDRESS3 0x00000018U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1472,11 +1478,11 @@ typedef struct
|
||||
/** @defgroup HAL_ETH_StateTypeDef ETH States
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */
|
||||
#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */
|
||||
#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */
|
||||
#define HAL_ETH_STATE_STARTED ((uint32_t)0x00000023U) /*!< an internal process is started */
|
||||
#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */
|
||||
#define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */
|
||||
#define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */
|
||||
#define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */
|
||||
#define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */
|
||||
#define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1484,8 +1490,8 @@ typedef struct
|
||||
/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ETH_PTP_NOT_CONFIGURATED ((uint32_t)0x00000000U) /*!< ETH PTP Configuration not done */
|
||||
#define HAL_ETH_PTP_CONFIGURATED ((uint32_t)0x00000001U) /*!< ETH PTP Configuration done */
|
||||
#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */
|
||||
#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1602,7 +1608,7 @@ typedef struct
|
||||
(((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
|
||||
|
||||
/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
|
||||
#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */
|
||||
#define ETH_WAKEUP_EXTI_LINE 0x00400000U /* !< 86 - 64 = 22 */
|
||||
|
||||
/**
|
||||
* @brief Enable the ETH WAKEUP Exti Line.
|
||||
|
||||
Reference in New Issue
Block a user