BMS_Software.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00006358 08000188 08000188 00010188 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000030 080064e0 080064e0 000164e0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08006510 08006510 00020014 2**0 CONTENTS 4 .ARM 00000000 08006510 08006510 00020014 2**0 CONTENTS 5 .preinit_array 00000000 08006510 08006510 00020014 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08006510 08006510 00016510 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08006514 08006514 00016514 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000014 20000000 08006518 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000258 20000018 0800652c 00020018 2**3 ALLOC 10 ._user_heap_stack 00000600 20000270 0800652c 00020270 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 00020014 2**0 CONTENTS, READONLY 12 .debug_info 0000f54c 00000000 00000000 00020044 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002965 00000000 00000000 0002f590 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000cc8 00000000 00000000 00031ef8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000bf0 00000000 00000000 00032bc0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0001c25c 00000000 00000000 000337b0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000feb9 00000000 00000000 0004fa0c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000a2242 00000000 00000000 0005f8c5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 00101b07 2**0 CONTENTS, READONLY 20 .debug_frame 000033cc 00000000 00000000 00101b58 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000188 <__do_global_dtors_aux>: 8000188: b510 push {r4, lr} 800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>) 800018c: 7823 ldrb r3, [r4, #0] 800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16> 8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>) 8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12> 8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>) 8000196: f3af 8000 nop.w 800019a: 2301 movs r3, #1 800019c: 7023 strb r3, [r4, #0] 800019e: bd10 pop {r4, pc} 80001a0: 20000018 .word 0x20000018 80001a4: 00000000 .word 0x00000000 80001a8: 080064c8 .word 0x080064c8 080001ac : 80001ac: b508 push {r3, lr} 80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc ) 80001b0: b11b cbz r3, 80001ba 80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 ) 80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 ) 80001b6: f3af 8000 nop.w 80001ba: bd08 pop {r3, pc} 80001bc: 00000000 .word 0x00000000 80001c0: 2000001c .word 0x2000001c 80001c4: 080064c8 .word 0x080064c8 080001c8 : uint8 numberofcells; uint8 numberofauxchannels; uint8 initAMS(SPI_HandleTypeDef* hspi, uint8 numofcells, uint8 numofaux) { 80001c8: b580 push {r7, lr} 80001ca: b082 sub sp, #8 80001cc: af00 add r7, sp, #0 80001ce: 6078 str r0, [r7, #4] 80001d0: 460b mov r3, r1 80001d2: 70fb strb r3, [r7, #3] 80001d4: 4613 mov r3, r2 80001d6: 70bb strb r3, [r7, #2] adbmsDriverInit(hspi); 80001d8: 6878 ldr r0, [r7, #4] 80001da: f000 fba7 bl 800092c numberofcells = numofcells; 80001de: 4a0d ldr r2, [pc, #52] ; (8000214 ) 80001e0: 78fb ldrb r3, [r7, #3] 80001e2: 7013 strb r3, [r2, #0] numberofauxchannels = numofaux; 80001e4: 4a0c ldr r2, [pc, #48] ; (8000218 ) 80001e6: 78bb ldrb r3, [r7, #2] 80001e8: 7013 strb r3, [r2, #0] amsWakeUp(); 80001ea: f000 f817 bl 800021c amsStopBalancing(); 80001ee: f000 f9ad bl 800054c amsConfigOverVoltage(DEFAULT_OV); 80001f2: f640 2041 movw r0, #2625 ; 0xa41 80001f6: f000 fa6e bl 80006d6 amsConfigUnderVoltage(DEFAULT_UV); 80001fa: f240 601a movw r0, #1562 ; 0x61a 80001fe: f000 f9af bl 8000560 amsConfigAuxMeasurement(0xFFFF); 8000202: f64f 70ff movw r0, #65535 ; 0xffff 8000206: f000 f90d bl 8000424 return 0; 800020a: 2300 movs r3, #0 } 800020c: 4618 mov r0, r3 800020e: 3708 adds r7, #8 8000210: 46bd mov sp, r7 8000212: bd80 pop {r7, pc} 8000214: 20000034 .word 0x20000034 8000218: 20000035 .word 0x20000035 0800021c : uint8 amsWakeUp() { 800021c: b580 push {r7, lr} 800021e: b082 sub sp, #8 8000220: af00 add r7, sp, #0 uint8 buf[6]; readCMD(RDCFGA, buf, 6); 8000222: 463b mov r3, r7 8000224: 2206 movs r2, #6 8000226: 4619 mov r1, r3 8000228: 2002 movs r0, #2 800022a: f000 fdab bl 8000d84 return 0; 800022e: 2300 movs r3, #0 } 8000230: 4618 mov r0, r3 8000232: 3708 adds r7, #8 8000234: 46bd mov sp, r7 8000236: bd80 pop {r7, pc} 08000238 : uint8 amsCellMeasurement(Cell_Module *module) { 8000238: b580 push {r7, lr} 800023a: b084 sub sp, #16 800023c: af00 add r7, sp, #0 800023e: 6078 str r0, [r7, #4] uint8_t rxbuffer[CV_GROUP_A_SIZE]; writeCMD((ADCV | CH000 | MD10), rxbuffer, 0); 8000240: f107 0308 add.w r3, r7, #8 8000244: 2200 movs r2, #0 8000246: 4619 mov r1, r3 8000248: f44f 7058 mov.w r0, #864 ; 0x360 800024c: f000 fd11 bl 8000c72 mcuDelay(5); 8000250: 2005 movs r0, #5 8000252: f000 fecd bl 8000ff0 amsReadCellVoltages(module); 8000256: 6878 ldr r0, [r7, #4] 8000258: f000 fa80 bl 800075c return 0; 800025c: 2300 movs r3, #0 } 800025e: 4618 mov r0, r3 8000260: 3710 adds r7, #16 8000262: 46bd mov sp, r7 8000264: bd80 pop {r7, pc} 08000266 : numberofcells = numberofChannels; return 0; } uint8 amsAuxMeasurement(Cell_Module *module) { 8000266: b580 push {r7, lr} 8000268: b084 sub sp, #16 800026a: af00 add r7, sp, #0 800026c: 6078 str r0, [r7, #4] uint8 args; uint8 rxbuf[AUX_GROUP_A_SIZE]; writeCMD(ADAX | MD01 | CHG000, &args, 0); 800026e: f107 030f add.w r3, r7, #15 8000272: 2200 movs r2, #0 8000274: 4619 mov r1, r3 8000276: f44f 609c mov.w r0, #1248 ; 0x4e0 800027a: f000 fcfa bl 8000c72 mcuDelay(5); 800027e: 2005 movs r0, #5 8000280: f000 feb6 bl 8000ff0 readCMD(RDAUXA, rxbuf, AUX_GROUP_A_SIZE); 8000284: f107 0308 add.w r3, r7, #8 8000288: 2206 movs r2, #6 800028a: 4619 mov r1, r3 800028c: 200c movs r0, #12 800028e: f000 fd79 bl 8000d84 module->auxVoltages[0] = rxbuf[0] | (rxbuf[1]<<8); 8000292: 7a3b ldrb r3, [r7, #8] 8000294: b21a sxth r2, r3 8000296: 7a7b ldrb r3, [r7, #9] 8000298: 021b lsls r3, r3, #8 800029a: b21b sxth r3, r3 800029c: 4313 orrs r3, r2 800029e: b21b sxth r3, r3 80002a0: b29a uxth r2, r3 80002a2: 687b ldr r3, [r7, #4] 80002a4: 849a strh r2, [r3, #36] ; 0x24 module->auxVoltages[1] = rxbuf[2] | (rxbuf[3]<<8); 80002a6: 7abb ldrb r3, [r7, #10] 80002a8: b21a sxth r2, r3 80002aa: 7afb ldrb r3, [r7, #11] 80002ac: 021b lsls r3, r3, #8 80002ae: b21b sxth r3, r3 80002b0: 4313 orrs r3, r2 80002b2: b21b sxth r3, r3 80002b4: b29a uxth r2, r3 80002b6: 687b ldr r3, [r7, #4] 80002b8: 84da strh r2, [r3, #38] ; 0x26 module->auxVoltages[2] = rxbuf[4] | (rxbuf[5]<<8); 80002ba: 7b3b ldrb r3, [r7, #12] 80002bc: b21a sxth r2, r3 80002be: 7b7b ldrb r3, [r7, #13] 80002c0: 021b lsls r3, r3, #8 80002c2: b21b sxth r3, r3 80002c4: 4313 orrs r3, r2 80002c6: b21b sxth r3, r3 80002c8: b29a uxth r2, r3 80002ca: 687b ldr r3, [r7, #4] 80002cc: 851a strh r2, [r3, #40] ; 0x28 readCMD(RDAUXB, rxbuf, AUX_GROUP_A_SIZE); 80002ce: f107 0308 add.w r3, r7, #8 80002d2: 2206 movs r2, #6 80002d4: 4619 mov r1, r3 80002d6: 200e movs r0, #14 80002d8: f000 fd54 bl 8000d84 module->auxVoltages[3] = rxbuf[0] | (rxbuf[1]<<8); 80002dc: 7a3b ldrb r3, [r7, #8] 80002de: b21a sxth r2, r3 80002e0: 7a7b ldrb r3, [r7, #9] 80002e2: 021b lsls r3, r3, #8 80002e4: b21b sxth r3, r3 80002e6: 4313 orrs r3, r2 80002e8: b21b sxth r3, r3 80002ea: b29a uxth r2, r3 80002ec: 687b ldr r3, [r7, #4] 80002ee: 855a strh r2, [r3, #42] ; 0x2a module->auxVoltages[4] = rxbuf[2] | (rxbuf[3]<<8); 80002f0: 7abb ldrb r3, [r7, #10] 80002f2: b21a sxth r2, r3 80002f4: 7afb ldrb r3, [r7, #11] 80002f6: 021b lsls r3, r3, #8 80002f8: b21b sxth r3, r3 80002fa: 4313 orrs r3, r2 80002fc: b21b sxth r3, r3 80002fe: b29a uxth r2, r3 8000300: 687b ldr r3, [r7, #4] 8000302: 859a strh r2, [r3, #44] ; 0x2c module->refVoltage = rxbuf[4] | (rxbuf[5]<<8); 8000304: 7b3b ldrb r3, [r7, #12] 8000306: b21a sxth r2, r3 8000308: 7b7b ldrb r3, [r7, #13] 800030a: 021b lsls r3, r3, #8 800030c: b21b sxth r3, r3 800030e: 4313 orrs r3, r2 8000310: b21b sxth r3, r3 8000312: b29a uxth r2, r3 8000314: 687b ldr r3, [r7, #4] 8000316: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 readCMD(RDAUXC, rxbuf, AUX_GROUP_A_SIZE); 800031a: f107 0308 add.w r3, r7, #8 800031e: 2206 movs r2, #6 8000320: 4619 mov r1, r3 8000322: 200d movs r0, #13 8000324: f000 fd2e bl 8000d84 module->auxVoltages[5] = rxbuf[0] | (rxbuf[1]<<8); 8000328: 7a3b ldrb r3, [r7, #8] 800032a: b21a sxth r2, r3 800032c: 7a7b ldrb r3, [r7, #9] 800032e: 021b lsls r3, r3, #8 8000330: b21b sxth r3, r3 8000332: 4313 orrs r3, r2 8000334: b21b sxth r3, r3 8000336: b29a uxth r2, r3 8000338: 687b ldr r3, [r7, #4] 800033a: 85da strh r2, [r3, #46] ; 0x2e module->auxVoltages[6] = rxbuf[2] | (rxbuf[3]<<8); 800033c: 7abb ldrb r3, [r7, #10] 800033e: b21a sxth r2, r3 8000340: 7afb ldrb r3, [r7, #11] 8000342: 021b lsls r3, r3, #8 8000344: b21b sxth r3, r3 8000346: 4313 orrs r3, r2 8000348: b21b sxth r3, r3 800034a: b29a uxth r2, r3 800034c: 687b ldr r3, [r7, #4] 800034e: 861a strh r2, [r3, #48] ; 0x30 module->auxVoltages[7] = rxbuf[4] | (rxbuf[5]<<8); 8000350: 7b3b ldrb r3, [r7, #12] 8000352: b21a sxth r2, r3 8000354: 7b7b ldrb r3, [r7, #13] 8000356: 021b lsls r3, r3, #8 8000358: b21b sxth r3, r3 800035a: 4313 orrs r3, r2 800035c: b21b sxth r3, r3 800035e: b29a uxth r2, r3 8000360: 687b ldr r3, [r7, #4] 8000362: 865a strh r2, [r3, #50] ; 0x32 readCMD(RDAUXD, rxbuf, AUX_GROUP_A_SIZE); 8000364: f107 0308 add.w r3, r7, #8 8000368: 2206 movs r2, #6 800036a: 4619 mov r1, r3 800036c: 200f movs r0, #15 800036e: f000 fd09 bl 8000d84 module->auxVoltages[8] = rxbuf[0] | (rxbuf[1]<<8); 8000372: 7a3b ldrb r3, [r7, #8] 8000374: b21a sxth r2, r3 8000376: 7a7b ldrb r3, [r7, #9] 8000378: 021b lsls r3, r3, #8 800037a: b21b sxth r3, r3 800037c: 4313 orrs r3, r2 800037e: b21b sxth r3, r3 8000380: b29a uxth r2, r3 8000382: 687b ldr r3, [r7, #4] 8000384: 869a strh r2, [r3, #52] ; 0x34 return 0; 8000386: 2300 movs r3, #0 } 8000388: 4618 mov r0, r3 800038a: 3710 adds r7, #16 800038c: 46bd mov sp, r7 800038e: bd80 pop {r7, pc} 08000390 : uint8 amsInternalStatusMeasurement(Cell_Module *module) { 8000390: b580 push {r7, lr} 8000392: b084 sub sp, #16 8000394: af00 add r7, sp, #0 8000396: 6078 str r0, [r7, #4] uint8 rxbuffer[STATUS_GROUP_A_SIZE]; writeCMD(ADSTAT | MD01 | CHST000, rxbuffer, STATUS_GROUP_A_SIZE); 8000398: f107 0308 add.w r3, r7, #8 800039c: 2206 movs r2, #6 800039e: 4619 mov r1, r3 80003a0: f44f 609d mov.w r0, #1256 ; 0x4e8 80003a4: f000 fc65 bl 8000c72 mcuDelay(5); 80003a8: 2005 movs r0, #5 80003aa: f000 fe21 bl 8000ff0 readCMD(RDSTATA, rxbuffer, STATUS_GROUP_A_SIZE); 80003ae: f107 0308 add.w r3, r7, #8 80003b2: 2206 movs r2, #6 80003b4: 4619 mov r1, r3 80003b6: 2010 movs r0, #16 80003b8: f000 fce4 bl 8000d84 module->sumOfCellMeasurements = rxbuffer[0] | (rxbuffer[1]<<8); 80003bc: 7a3b ldrb r3, [r7, #8] 80003be: b21a sxth r2, r3 80003c0: 7a7b ldrb r3, [r7, #9] 80003c2: 021b lsls r3, r3, #8 80003c4: b21b sxth r3, r3 80003c6: 4313 orrs r3, r2 80003c8: b21b sxth r3, r3 80003ca: b29a uxth r2, r3 80003cc: 687b ldr r3, [r7, #4] 80003ce: 87da strh r2, [r3, #62] ; 0x3e module->internalDieTemp = rxbuffer[2] | (rxbuffer[3]<<8); 80003d0: 7abb ldrb r3, [r7, #10] 80003d2: b21a sxth r2, r3 80003d4: 7afb ldrb r3, [r7, #11] 80003d6: 021b lsls r3, r3, #8 80003d8: b21b sxth r3, r3 80003da: 4313 orrs r3, r2 80003dc: b21b sxth r3, r3 80003de: b29a uxth r2, r3 80003e0: 687b ldr r3, [r7, #4] 80003e2: 871a strh r2, [r3, #56] ; 0x38 module->analogSupplyVoltage = rxbuffer[4] | (rxbuffer[5]<<8); 80003e4: 7b3b ldrb r3, [r7, #12] 80003e6: b21a sxth r2, r3 80003e8: 7b7b ldrb r3, [r7, #13] 80003ea: 021b lsls r3, r3, #8 80003ec: b21b sxth r3, r3 80003ee: 4313 orrs r3, r2 80003f0: b21b sxth r3, r3 80003f2: b29a uxth r2, r3 80003f4: 687b ldr r3, [r7, #4] 80003f6: 875a strh r2, [r3, #58] ; 0x3a readCMD(RDSTATB, rxbuffer, STATUS_GROUP_B_SIZE); 80003f8: f107 0308 add.w r3, r7, #8 80003fc: 2206 movs r2, #6 80003fe: 4619 mov r1, r3 8000400: 2012 movs r0, #18 8000402: f000 fcbf bl 8000d84 module->digitalSupplyVoltage = rxbuffer[0] | (rxbuffer[1]<<8); 8000406: 7a3b ldrb r3, [r7, #8] 8000408: b21a sxth r2, r3 800040a: 7a7b ldrb r3, [r7, #9] 800040c: 021b lsls r3, r3, #8 800040e: b21b sxth r3, r3 8000410: 4313 orrs r3, r2 8000412: b21b sxth r3, r3 8000414: b29a uxth r2, r3 8000416: 687b ldr r3, [r7, #4] 8000418: 879a strh r2, [r3, #60] ; 0x3c return 0; 800041a: 2300 movs r3, #0 } 800041c: 4618 mov r0, r3 800041e: 3710 adds r7, #16 8000420: 46bd mov sp, r7 8000422: bd80 pop {r7, pc} 08000424 : uint8 amsConfigAuxMeasurement(uint16 Channels) { 8000424: b580 push {r7, lr} 8000426: b084 sub sp, #16 8000428: af00 add r7, sp, #0 800042a: 4603 mov r3, r0 800042c: 80fb strh r3, [r7, #6] uint8 buf[CFG_GROUP_A_SIZE]; readCMD(RDCFGA, buf, CFG_GROUP_A_SIZE); 800042e: f107 0308 add.w r3, r7, #8 8000432: 2206 movs r2, #6 8000434: 4619 mov r1, r3 8000436: 2002 movs r0, #2 8000438: f000 fca4 bl 8000d84 buf[0] |= 0xF8; 800043c: 7a3b ldrb r3, [r7, #8] 800043e: f063 0307 orn r3, r3, #7 8000442: b2db uxtb r3, r3 8000444: 723b strb r3, [r7, #8] writeCMD(WRCFGA, buf, CFG_GROUP_A_SIZE); 8000446: f107 0308 add.w r3, r7, #8 800044a: 2206 movs r2, #6 800044c: 4619 mov r1, r3 800044e: 2001 movs r0, #1 8000450: f000 fc0f bl 8000c72 readCMD(RDCFGB, buf, CFG_GROUP_B_SIZE); 8000454: f107 0308 add.w r3, r7, #8 8000458: 2206 movs r2, #6 800045a: 4619 mov r1, r3 800045c: 2026 movs r0, #38 ; 0x26 800045e: f000 fc91 bl 8000d84 buf[0] |= 0x0F; 8000462: 7a3b ldrb r3, [r7, #8] 8000464: f043 030f orr.w r3, r3, #15 8000468: b2db uxtb r3, r3 800046a: 723b strb r3, [r7, #8] writeCMD(WRCFGB, buf, CFG_GROUP_B_SIZE); 800046c: f107 0308 add.w r3, r7, #8 8000470: 2206 movs r2, #6 8000472: 4619 mov r1, r3 8000474: 2024 movs r0, #36 ; 0x24 8000476: f000 fbfc bl 8000c72 return 0; 800047a: 2300 movs r3, #0 } 800047c: 4618 mov r0, r3 800047e: 3710 adds r7, #16 8000480: 46bd mov sp, r7 8000482: bd80 pop {r7, pc} 08000484 : { return 0; } uint8 amsConfigBalancing(uint32 Channels) { 8000484: b580 push {r7, lr} 8000486: b084 sub sp, #16 8000488: af00 add r7, sp, #0 800048a: 6078 str r0, [r7, #4] uint8 regbuffer[CFG_GROUP_A_SIZE]; readCMD(RDCFGA, regbuffer, CFG_GROUP_A_SIZE); 800048c: f107 0308 add.w r3, r7, #8 8000490: 2206 movs r2, #6 8000492: 4619 mov r1, r3 8000494: 2002 movs r0, #2 8000496: f000 fc75 bl 8000d84 regbuffer[4] = Channels & 0xFF; 800049a: 687b ldr r3, [r7, #4] 800049c: b2db uxtb r3, r3 800049e: 733b strb r3, [r7, #12] regbuffer[5] &= 0xF0; 80004a0: 7b7b ldrb r3, [r7, #13] 80004a2: f023 030f bic.w r3, r3, #15 80004a6: b2db uxtb r3, r3 80004a8: 737b strb r3, [r7, #13] regbuffer[5] |= (Channels>>8) & 0x0F; 80004aa: 7b7a ldrb r2, [r7, #13] 80004ac: 687b ldr r3, [r7, #4] 80004ae: 0a1b lsrs r3, r3, #8 80004b0: b2db uxtb r3, r3 80004b2: f003 030f and.w r3, r3, #15 80004b6: b2db uxtb r3, r3 80004b8: 4313 orrs r3, r2 80004ba: b2db uxtb r3, r3 80004bc: 737b strb r3, [r7, #13] writeCMD(WRCFGA, regbuffer, CFG_GROUP_A_SIZE); 80004be: f107 0308 add.w r3, r7, #8 80004c2: 2206 movs r2, #6 80004c4: 4619 mov r1, r3 80004c6: 2001 movs r0, #1 80004c8: f000 fbd3 bl 8000c72 readCMD(RDCFGB, regbuffer, CFG_GROUP_B_SIZE); 80004cc: f107 0308 add.w r3, r7, #8 80004d0: 2206 movs r2, #6 80004d2: 4619 mov r1, r3 80004d4: 2026 movs r0, #38 ; 0x26 80004d6: f000 fc55 bl 8000d84 regbuffer[0] &= 0x0F; 80004da: 7a3b ldrb r3, [r7, #8] 80004dc: f003 030f and.w r3, r3, #15 80004e0: b2db uxtb r3, r3 80004e2: 723b strb r3, [r7, #8] regbuffer[0] |= (Channels>>8) & 0xF0; 80004e4: 7a3a ldrb r2, [r7, #8] 80004e6: 687b ldr r3, [r7, #4] 80004e8: 0a1b lsrs r3, r3, #8 80004ea: b2db uxtb r3, r3 80004ec: f023 030f bic.w r3, r3, #15 80004f0: b2db uxtb r3, r3 80004f2: 4313 orrs r3, r2 80004f4: b2db uxtb r3, r3 80004f6: 723b strb r3, [r7, #8] regbuffer[1] &= 0xFC; 80004f8: 7a7b ldrb r3, [r7, #9] 80004fa: f023 0303 bic.w r3, r3, #3 80004fe: b2db uxtb r3, r3 8000500: 727b strb r3, [r7, #9] regbuffer[1] |= 0x03 & (Channels>>16); 8000502: 7a7a ldrb r2, [r7, #9] 8000504: 687b ldr r3, [r7, #4] 8000506: 0c1b lsrs r3, r3, #16 8000508: b2db uxtb r3, r3 800050a: f003 0303 and.w r3, r3, #3 800050e: b2db uxtb r3, r3 8000510: 4313 orrs r3, r2 8000512: b2db uxtb r3, r3 8000514: 727b strb r3, [r7, #9] writeCMD(WRCFGB, regbuffer, CFG_GROUP_B_SIZE); 8000516: f107 0308 add.w r3, r7, #8 800051a: 2206 movs r2, #6 800051c: 4619 mov r1, r3 800051e: 2024 movs r0, #36 ; 0x24 8000520: f000 fba7 bl 8000c72 return 0; 8000524: 2300 movs r3, #0 } 8000526: 4618 mov r0, r3 8000528: 3710 adds r7, #16 800052a: 46bd mov sp, r7 800052c: bd80 pop {r7, pc} 0800052e : uint8 amsStartBalancing(uint8 dutyCycle) { 800052e: b580 push {r7, lr} 8000530: b082 sub sp, #8 8000532: af00 add r7, sp, #0 8000534: 4603 mov r3, r0 8000536: 71fb strb r3, [r7, #7] writeCMD(UNMUTE, NULL, 0); 8000538: 2200 movs r2, #0 800053a: 2100 movs r1, #0 800053c: 2029 movs r0, #41 ; 0x29 800053e: f000 fb98 bl 8000c72 return 0; 8000542: 2300 movs r3, #0 } 8000544: 4618 mov r0, r3 8000546: 3708 adds r7, #8 8000548: 46bd mov sp, r7 800054a: bd80 pop {r7, pc} 0800054c : uint8 amsStopBalancing() { 800054c: b580 push {r7, lr} 800054e: af00 add r7, sp, #0 writeCMD(MUTE, NULL, 0); 8000550: 2200 movs r2, #0 8000552: 2100 movs r1, #0 8000554: 2028 movs r0, #40 ; 0x28 8000556: f000 fb8c bl 8000c72 return 0; 800055a: 2300 movs r3, #0 } 800055c: 4618 mov r0, r3 800055e: bd80 pop {r7, pc} 08000560 : } uint8 amsConfigUnderVoltage(uint16 underVoltage) { 8000560: b580 push {r7, lr} 8000562: b084 sub sp, #16 8000564: af00 add r7, sp, #0 8000566: 4603 mov r3, r0 8000568: 80fb strh r3, [r7, #6] uint8 buffer[CFG_GROUP_A_SIZE]; readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); 800056a: f107 0308 add.w r3, r7, #8 800056e: 2206 movs r2, #6 8000570: 4619 mov r1, r3 8000572: 2002 movs r0, #2 8000574: f000 fc06 bl 8000d84 buffer[1] = (uint8) underVoltage & 0xFF; 8000578: 88fb ldrh r3, [r7, #6] 800057a: b2db uxtb r3, r3 800057c: 727b strb r3, [r7, #9] uint8 ovuv = buffer[2] & 0xF0; 800057e: 7abb ldrb r3, [r7, #10] 8000580: f023 030f bic.w r3, r3, #15 8000584: 73fb strb r3, [r7, #15] ovuv |= (uint8) (underVoltage >> 8) & 0x0F; 8000586: 88fb ldrh r3, [r7, #6] 8000588: 0a1b lsrs r3, r3, #8 800058a: b29b uxth r3, r3 800058c: b25b sxtb r3, r3 800058e: f003 030f and.w r3, r3, #15 8000592: b25a sxtb r2, r3 8000594: f997 300f ldrsb.w r3, [r7, #15] 8000598: 4313 orrs r3, r2 800059a: b25b sxtb r3, r3 800059c: 73fb strb r3, [r7, #15] buffer[2] = ovuv; 800059e: 7bfb ldrb r3, [r7, #15] 80005a0: 72bb strb r3, [r7, #10] writeCMD(WRCFGA, buffer, CFG_GROUP_A_SIZE); 80005a2: f107 0308 add.w r3, r7, #8 80005a6: 2206 movs r2, #6 80005a8: 4619 mov r1, r3 80005aa: 2001 movs r0, #1 80005ac: f000 fb61 bl 8000c72 return 0; 80005b0: 2300 movs r3, #0 } 80005b2: 4618 mov r0, r3 80005b4: 3710 adds r7, #16 80005b6: 46bd mov sp, r7 80005b8: bd80 pop {r7, pc} 080005ba : uint8 amsCheckUnderOverVoltage(Cell_Module *module) { 80005ba: b580 push {r7, lr} 80005bc: b088 sub sp, #32 80005be: af00 add r7, sp, #0 80005c0: 6078 str r0, [r7, #4] uint8 regbuffer[STATUS_GROUP_B_SIZE]; uint32 overundervoltages = 0; 80005c2: 2300 movs r3, #0 80005c4: 61bb str r3, [r7, #24] readCMD(RDSTATB, regbuffer, STATUS_GROUP_B_SIZE); 80005c6: f107 030c add.w r3, r7, #12 80005ca: 2206 movs r2, #6 80005cc: 4619 mov r1, r3 80005ce: 2012 movs r0, #18 80005d0: f000 fbd8 bl 8000d84 overundervoltages = regbuffer[2] | (regbuffer[3]<<8) | (regbuffer[4]<<16); 80005d4: 7bbb ldrb r3, [r7, #14] 80005d6: 461a mov r2, r3 80005d8: 7bfb ldrb r3, [r7, #15] 80005da: 021b lsls r3, r3, #8 80005dc: 431a orrs r2, r3 80005de: 7c3b ldrb r3, [r7, #16] 80005e0: 041b lsls r3, r3, #16 80005e2: 4313 orrs r3, r2 80005e4: 61bb str r3, [r7, #24] module->overVoltage = 0; 80005e6: 687b ldr r3, [r7, #4] 80005e8: 2200 movs r2, #0 80005ea: 659a str r2, [r3, #88] ; 0x58 module->underVoltage = 0; 80005ec: 687b ldr r3, [r7, #4] 80005ee: 2200 movs r2, #0 80005f0: 65da str r2, [r3, #92] ; 0x5c for(uint8 n = 0; n < 12; n++) 80005f2: 2300 movs r3, #0 80005f4: 77fb strb r3, [r7, #31] 80005f6: e027 b.n 8000648 { uint8 overvolt = (overundervoltages>>(2*n+1)) & 0x01; 80005f8: 7ffb ldrb r3, [r7, #31] 80005fa: 005b lsls r3, r3, #1 80005fc: 3301 adds r3, #1 80005fe: 69ba ldr r2, [r7, #24] 8000600: fa22 f303 lsr.w r3, r2, r3 8000604: b2db uxtb r3, r3 8000606: f003 0301 and.w r3, r3, #1 800060a: 757b strb r3, [r7, #21] uint8 undervolt = (overundervoltages>>(2*n))&0x01; 800060c: 7ffb ldrb r3, [r7, #31] 800060e: 005b lsls r3, r3, #1 8000610: 69ba ldr r2, [r7, #24] 8000612: fa22 f303 lsr.w r3, r2, r3 8000616: b2db uxtb r3, r3 8000618: f003 0301 and.w r3, r3, #1 800061c: 753b strb r3, [r7, #20] module->overVoltage |= overvolt<underVoltage |= undervolt< } readCMD(RDAUXD,regbuffer,AUX_GROUP_D_SIZE); 800064e: f107 030c add.w r3, r7, #12 8000652: 2206 movs r2, #6 8000654: 4619 mov r1, r3 8000656: 200f movs r0, #15 8000658: f000 fb94 bl 8000d84 overundervoltages = 0; 800065c: 2300 movs r3, #0 800065e: 61bb str r3, [r7, #24] overundervoltages = regbuffer[4] | (regbuffer[5]<<8); 8000660: 7c3b ldrb r3, [r7, #16] 8000662: 461a mov r2, r3 8000664: 7c7b ldrb r3, [r7, #17] 8000666: 021b lsls r3, r3, #8 8000668: 4313 orrs r3, r2 800066a: 61bb str r3, [r7, #24] for(uint8 n = 0; n < 6; n++) 800066c: 2300 movs r3, #0 800066e: 77bb strb r3, [r7, #30] 8000670: e029 b.n 80006c6 { uint8 overvolt = (overundervoltages>>(2*n+1)) & 0x01; 8000672: 7fbb ldrb r3, [r7, #30] 8000674: 005b lsls r3, r3, #1 8000676: 3301 adds r3, #1 8000678: 69ba ldr r2, [r7, #24] 800067a: fa22 f303 lsr.w r3, r2, r3 800067e: b2db uxtb r3, r3 8000680: f003 0301 and.w r3, r3, #1 8000684: 75fb strb r3, [r7, #23] uint8 undervolt = (overundervoltages>>(2*n))&0x01; 8000686: 7fbb ldrb r3, [r7, #30] 8000688: 005b lsls r3, r3, #1 800068a: 69ba ldr r2, [r7, #24] 800068c: fa22 f303 lsr.w r3, r2, r3 8000690: b2db uxtb r3, r3 8000692: f003 0301 and.w r3, r3, #1 8000696: 75bb strb r3, [r7, #22] module->overVoltage |= (uint32) overvolt<<(n+12); 8000698: 687b ldr r3, [r7, #4] 800069a: 6d9a ldr r2, [r3, #88] ; 0x58 800069c: 7df9 ldrb r1, [r7, #23] 800069e: 7fbb ldrb r3, [r7, #30] 80006a0: 330c adds r3, #12 80006a2: fa01 f303 lsl.w r3, r1, r3 80006a6: 431a orrs r2, r3 80006a8: 687b ldr r3, [r7, #4] 80006aa: 659a str r2, [r3, #88] ; 0x58 module->underVoltage |= (uint32) undervolt<<(n+12); 80006ac: 687b ldr r3, [r7, #4] 80006ae: 6dda ldr r2, [r3, #92] ; 0x5c 80006b0: 7db9 ldrb r1, [r7, #22] 80006b2: 7fbb ldrb r3, [r7, #30] 80006b4: 330c adds r3, #12 80006b6: fa01 f303 lsl.w r3, r1, r3 80006ba: 431a orrs r2, r3 80006bc: 687b ldr r3, [r7, #4] 80006be: 65da str r2, [r3, #92] ; 0x5c for(uint8 n = 0; n < 6; n++) 80006c0: 7fbb ldrb r3, [r7, #30] 80006c2: 3301 adds r3, #1 80006c4: 77bb strb r3, [r7, #30] 80006c6: 7fbb ldrb r3, [r7, #30] 80006c8: 2b05 cmp r3, #5 80006ca: d9d2 bls.n 8000672 } return 0; 80006cc: 2300 movs r3, #0 } 80006ce: 4618 mov r0, r3 80006d0: 3720 adds r7, #32 80006d2: 46bd mov sp, r7 80006d4: bd80 pop {r7, pc} 080006d6 : uint8 amsConfigOverVoltage(uint16 overVoltage) { 80006d6: b580 push {r7, lr} 80006d8: b084 sub sp, #16 80006da: af00 add r7, sp, #0 80006dc: 4603 mov r3, r0 80006de: 80fb strh r3, [r7, #6] uint8 buffer[CFG_GROUP_B_SIZE]; readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); 80006e0: f107 0308 add.w r3, r7, #8 80006e4: 2206 movs r2, #6 80006e6: 4619 mov r1, r3 80006e8: 2002 movs r0, #2 80006ea: f000 fb4b bl 8000d84 buffer[2] &= 0x0F; 80006ee: 7abb ldrb r3, [r7, #10] 80006f0: f003 030f and.w r3, r3, #15 80006f4: b2db uxtb r3, r3 80006f6: 72bb strb r3, [r7, #10] buffer[2] |= (uint8) overVoltage << 4; 80006f8: 7abb ldrb r3, [r7, #10] 80006fa: b25a sxtb r2, r3 80006fc: 88fb ldrh r3, [r7, #6] 80006fe: b2db uxtb r3, r3 8000700: 011b lsls r3, r3, #4 8000702: b25b sxtb r3, r3 8000704: 4313 orrs r3, r2 8000706: b25b sxtb r3, r3 8000708: b2db uxtb r3, r3 800070a: 72bb strb r3, [r7, #10] buffer[3] = (uint8)(overVoltage>>4); 800070c: 88fb ldrh r3, [r7, #6] 800070e: 091b lsrs r3, r3, #4 8000710: b29b uxth r3, r3 8000712: b2db uxtb r3, r3 8000714: 72fb strb r3, [r7, #11] writeCMD(WRCFGA, buffer, CFG_GROUP_A_SIZE); 8000716: f107 0308 add.w r3, r7, #8 800071a: 2206 movs r2, #6 800071c: 4619 mov r1, r3 800071e: 2001 movs r0, #1 8000720: f000 faa7 bl 8000c72 return 0; 8000724: 2300 movs r3, #0 } 8000726: 4618 mov r0, r3 8000728: 3710 adds r7, #16 800072a: 46bd mov sp, r7 800072c: bd80 pop {r7, pc} 0800072e : uint8 buffer[6]; writeCMD(CLRSTAT, buffer, 0); return 0; } uint8 amsClearAux() { 800072e: b580 push {r7, lr} 8000730: b082 sub sp, #8 8000732: af00 add r7, sp, #0 uint8 buffer[6]; writeCMD(CLRAUX, buffer, 0); 8000734: 463b mov r3, r7 8000736: 2200 movs r2, #0 8000738: 4619 mov r1, r3 800073a: f240 7012 movw r0, #1810 ; 0x712 800073e: f000 fa98 bl 8000c72 return 0; 8000742: 2300 movs r3, #0 } 8000744: 4618 mov r0, r3 8000746: 3708 adds r7, #8 8000748: 46bd mov sp, r7 800074a: bd80 pop {r7, pc} 0800074c : //HAL_GPIO_WritePin(AMS_Error_GPIO_Port, AMS_Error_Pin, GPIO_PIN_SET); return 0; } uint8 amsClearWarning() { 800074c: b480 push {r7} 800074e: af00 add r7, sp, #0 //HAL_GPIO_WritePin(AMS_Warning_GPIO_Port, AMS_Warning_Pin, GPIO_PIN_RESET); return 0; 8000750: 2300 movs r3, #0 } 8000752: 4618 mov r0, r3 8000754: 46bd mov sp, r7 8000756: f85d 7b04 ldr.w r7, [sp], #4 800075a: 4770 bx lr 0800075c : return 0; } uint8 amsReadCellVoltages(Cell_Module *module) { 800075c: b580 push {r7, lr} 800075e: b084 sub sp, #16 8000760: af00 add r7, sp, #0 8000762: 6078 str r0, [r7, #4] uint8 rxbuffer[CV_GROUP_A_SIZE]; readCMD(RDCVA, rxbuffer, CV_GROUP_A_SIZE); 8000764: f107 0308 add.w r3, r7, #8 8000768: 2206 movs r2, #6 800076a: 4619 mov r1, r3 800076c: 2004 movs r0, #4 800076e: f000 fb09 bl 8000d84 module->cellVoltages[0] = rxbuffer[0] | (rxbuffer[1]<<8); 8000772: 7a3b ldrb r3, [r7, #8] 8000774: b21a sxth r2, r3 8000776: 7a7b ldrb r3, [r7, #9] 8000778: 021b lsls r3, r3, #8 800077a: b21b sxth r3, r3 800077c: 4313 orrs r3, r2 800077e: b21b sxth r3, r3 8000780: b29a uxth r2, r3 8000782: 687b ldr r3, [r7, #4] 8000784: 801a strh r2, [r3, #0] module->cellVoltages[1] = rxbuffer[2] | (rxbuffer[3]<<8); 8000786: 7abb ldrb r3, [r7, #10] 8000788: b21a sxth r2, r3 800078a: 7afb ldrb r3, [r7, #11] 800078c: 021b lsls r3, r3, #8 800078e: b21b sxth r3, r3 8000790: 4313 orrs r3, r2 8000792: b21b sxth r3, r3 8000794: b29a uxth r2, r3 8000796: 687b ldr r3, [r7, #4] 8000798: 805a strh r2, [r3, #2] module->cellVoltages[2] = rxbuffer[4] | (rxbuffer[5]<<8); 800079a: 7b3b ldrb r3, [r7, #12] 800079c: b21a sxth r2, r3 800079e: 7b7b ldrb r3, [r7, #13] 80007a0: 021b lsls r3, r3, #8 80007a2: b21b sxth r3, r3 80007a4: 4313 orrs r3, r2 80007a6: b21b sxth r3, r3 80007a8: b29a uxth r2, r3 80007aa: 687b ldr r3, [r7, #4] 80007ac: 809a strh r2, [r3, #4] readCMD(RDCVB, rxbuffer, CV_GROUP_A_SIZE); 80007ae: f107 0308 add.w r3, r7, #8 80007b2: 2206 movs r2, #6 80007b4: 4619 mov r1, r3 80007b6: 2006 movs r0, #6 80007b8: f000 fae4 bl 8000d84 module->cellVoltages[3] = rxbuffer[0] | (rxbuffer[1]<<8); 80007bc: 7a3b ldrb r3, [r7, #8] 80007be: b21a sxth r2, r3 80007c0: 7a7b ldrb r3, [r7, #9] 80007c2: 021b lsls r3, r3, #8 80007c4: b21b sxth r3, r3 80007c6: 4313 orrs r3, r2 80007c8: b21b sxth r3, r3 80007ca: b29a uxth r2, r3 80007cc: 687b ldr r3, [r7, #4] 80007ce: 80da strh r2, [r3, #6] module->cellVoltages[4] = rxbuffer[2] | (rxbuffer[3]<<8); 80007d0: 7abb ldrb r3, [r7, #10] 80007d2: b21a sxth r2, r3 80007d4: 7afb ldrb r3, [r7, #11] 80007d6: 021b lsls r3, r3, #8 80007d8: b21b sxth r3, r3 80007da: 4313 orrs r3, r2 80007dc: b21b sxth r3, r3 80007de: b29a uxth r2, r3 80007e0: 687b ldr r3, [r7, #4] 80007e2: 811a strh r2, [r3, #8] module->cellVoltages[5] = rxbuffer[4] | (rxbuffer[5]<<8); 80007e4: 7b3b ldrb r3, [r7, #12] 80007e6: b21a sxth r2, r3 80007e8: 7b7b ldrb r3, [r7, #13] 80007ea: 021b lsls r3, r3, #8 80007ec: b21b sxth r3, r3 80007ee: 4313 orrs r3, r2 80007f0: b21b sxth r3, r3 80007f2: b29a uxth r2, r3 80007f4: 687b ldr r3, [r7, #4] 80007f6: 815a strh r2, [r3, #10] readCMD(RDCVC, rxbuffer, CV_GROUP_A_SIZE); 80007f8: f107 0308 add.w r3, r7, #8 80007fc: 2206 movs r2, #6 80007fe: 4619 mov r1, r3 8000800: 2008 movs r0, #8 8000802: f000 fabf bl 8000d84 module->cellVoltages[6] = rxbuffer[0] | (rxbuffer[1]<<8); 8000806: 7a3b ldrb r3, [r7, #8] 8000808: b21a sxth r2, r3 800080a: 7a7b ldrb r3, [r7, #9] 800080c: 021b lsls r3, r3, #8 800080e: b21b sxth r3, r3 8000810: 4313 orrs r3, r2 8000812: b21b sxth r3, r3 8000814: b29a uxth r2, r3 8000816: 687b ldr r3, [r7, #4] 8000818: 819a strh r2, [r3, #12] module->cellVoltages[7] = rxbuffer[2] | (rxbuffer[3]<<8); 800081a: 7abb ldrb r3, [r7, #10] 800081c: b21a sxth r2, r3 800081e: 7afb ldrb r3, [r7, #11] 8000820: 021b lsls r3, r3, #8 8000822: b21b sxth r3, r3 8000824: 4313 orrs r3, r2 8000826: b21b sxth r3, r3 8000828: b29a uxth r2, r3 800082a: 687b ldr r3, [r7, #4] 800082c: 81da strh r2, [r3, #14] module->cellVoltages[8] = rxbuffer[4] | (rxbuffer[5]<<8); 800082e: 7b3b ldrb r3, [r7, #12] 8000830: b21a sxth r2, r3 8000832: 7b7b ldrb r3, [r7, #13] 8000834: 021b lsls r3, r3, #8 8000836: b21b sxth r3, r3 8000838: 4313 orrs r3, r2 800083a: b21b sxth r3, r3 800083c: b29a uxth r2, r3 800083e: 687b ldr r3, [r7, #4] 8000840: 821a strh r2, [r3, #16] readCMD(RDCVD, rxbuffer, CV_GROUP_A_SIZE); 8000842: f107 0308 add.w r3, r7, #8 8000846: 2206 movs r2, #6 8000848: 4619 mov r1, r3 800084a: 200a movs r0, #10 800084c: f000 fa9a bl 8000d84 module->cellVoltages[9] = rxbuffer[0] | (rxbuffer[1]<<8); 8000850: 7a3b ldrb r3, [r7, #8] 8000852: b21a sxth r2, r3 8000854: 7a7b ldrb r3, [r7, #9] 8000856: 021b lsls r3, r3, #8 8000858: b21b sxth r3, r3 800085a: 4313 orrs r3, r2 800085c: b21b sxth r3, r3 800085e: b29a uxth r2, r3 8000860: 687b ldr r3, [r7, #4] 8000862: 825a strh r2, [r3, #18] module->cellVoltages[10] = rxbuffer[2] | (rxbuffer[3]<<8); 8000864: 7abb ldrb r3, [r7, #10] 8000866: b21a sxth r2, r3 8000868: 7afb ldrb r3, [r7, #11] 800086a: 021b lsls r3, r3, #8 800086c: b21b sxth r3, r3 800086e: 4313 orrs r3, r2 8000870: b21b sxth r3, r3 8000872: b29a uxth r2, r3 8000874: 687b ldr r3, [r7, #4] 8000876: 829a strh r2, [r3, #20] module->cellVoltages[11] = rxbuffer[4] | (rxbuffer[5]<<8); 8000878: 7b3b ldrb r3, [r7, #12] 800087a: b21a sxth r2, r3 800087c: 7b7b ldrb r3, [r7, #13] 800087e: 021b lsls r3, r3, #8 8000880: b21b sxth r3, r3 8000882: 4313 orrs r3, r2 8000884: b21b sxth r3, r3 8000886: b29a uxth r2, r3 8000888: 687b ldr r3, [r7, #4] 800088a: 82da strh r2, [r3, #22] readCMD(RDCVE, rxbuffer, CV_GROUP_A_SIZE); 800088c: f107 0308 add.w r3, r7, #8 8000890: 2206 movs r2, #6 8000892: 4619 mov r1, r3 8000894: 2009 movs r0, #9 8000896: f000 fa75 bl 8000d84 module->cellVoltages[12] = rxbuffer[0] | (rxbuffer[1]<<8); 800089a: 7a3b ldrb r3, [r7, #8] 800089c: b21a sxth r2, r3 800089e: 7a7b ldrb r3, [r7, #9] 80008a0: 021b lsls r3, r3, #8 80008a2: b21b sxth r3, r3 80008a4: 4313 orrs r3, r2 80008a6: b21b sxth r3, r3 80008a8: b29a uxth r2, r3 80008aa: 687b ldr r3, [r7, #4] 80008ac: 831a strh r2, [r3, #24] module->cellVoltages[13] = rxbuffer[2] | (rxbuffer[3]<<8); 80008ae: 7abb ldrb r3, [r7, #10] 80008b0: b21a sxth r2, r3 80008b2: 7afb ldrb r3, [r7, #11] 80008b4: 021b lsls r3, r3, #8 80008b6: b21b sxth r3, r3 80008b8: 4313 orrs r3, r2 80008ba: b21b sxth r3, r3 80008bc: b29a uxth r2, r3 80008be: 687b ldr r3, [r7, #4] 80008c0: 835a strh r2, [r3, #26] module->cellVoltages[14] = rxbuffer[4] | (rxbuffer[5]<<8); 80008c2: 7b3b ldrb r3, [r7, #12] 80008c4: b21a sxth r2, r3 80008c6: 7b7b ldrb r3, [r7, #13] 80008c8: 021b lsls r3, r3, #8 80008ca: b21b sxth r3, r3 80008cc: 4313 orrs r3, r2 80008ce: b21b sxth r3, r3 80008d0: b29a uxth r2, r3 80008d2: 687b ldr r3, [r7, #4] 80008d4: 839a strh r2, [r3, #28] readCMD(RDCVF, rxbuffer, CV_GROUP_A_SIZE); 80008d6: f107 0308 add.w r3, r7, #8 80008da: 2206 movs r2, #6 80008dc: 4619 mov r1, r3 80008de: 200b movs r0, #11 80008e0: f000 fa50 bl 8000d84 module->cellVoltages[15] = rxbuffer[0] | (rxbuffer[1]<<8); 80008e4: 7a3b ldrb r3, [r7, #8] 80008e6: b21a sxth r2, r3 80008e8: 7a7b ldrb r3, [r7, #9] 80008ea: 021b lsls r3, r3, #8 80008ec: b21b sxth r3, r3 80008ee: 4313 orrs r3, r2 80008f0: b21b sxth r3, r3 80008f2: b29a uxth r2, r3 80008f4: 687b ldr r3, [r7, #4] 80008f6: 83da strh r2, [r3, #30] module->cellVoltages[16] = rxbuffer[2] | (rxbuffer[3]<<8); 80008f8: 7abb ldrb r3, [r7, #10] 80008fa: b21a sxth r2, r3 80008fc: 7afb ldrb r3, [r7, #11] 80008fe: 021b lsls r3, r3, #8 8000900: b21b sxth r3, r3 8000902: 4313 orrs r3, r2 8000904: b21b sxth r3, r3 8000906: b29a uxth r2, r3 8000908: 687b ldr r3, [r7, #4] 800090a: 841a strh r2, [r3, #32] module->cellVoltages[17] = rxbuffer[4] | (rxbuffer[5]<<8); 800090c: 7b3b ldrb r3, [r7, #12] 800090e: b21a sxth r2, r3 8000910: 7b7b ldrb r3, [r7, #13] 8000912: 021b lsls r3, r3, #8 8000914: b21b sxth r3, r3 8000916: 4313 orrs r3, r2 8000918: b21b sxth r3, r3 800091a: b29a uxth r2, r3 800091c: 687b ldr r3, [r7, #4] 800091e: 845a strh r2, [r3, #34] ; 0x22 return 0; 8000920: 2300 movs r3, #0 } 8000922: 4618 mov r0, r3 8000924: 3710 adds r7, #16 8000926: 46bd mov sp, r7 8000928: bd80 pop {r7, pc} ... 0800092c : #define ADBMS_SPI_TIMEOUT 1000 //Timeout in ms SPI_HandleTypeDef* adbmsspi; uint8 adbmsDriverInit(SPI_HandleTypeDef* hspi) { 800092c: b580 push {r7, lr} 800092e: b082 sub sp, #8 8000930: af00 add r7, sp, #0 8000932: 6078 str r0, [r7, #4] mcuAdbmsCSLow(); 8000934: f000 fad8 bl 8000ee8 HAL_Delay(1); 8000938: 2001 movs r0, #1 800093a: f001 fc9f bl 800227c mcuAdbmsCSHigh(); 800093e: f000 fadd bl 8000efc adbmsspi = hspi; 8000942: 4a04 ldr r2, [pc, #16] ; (8000954 ) 8000944: 687b ldr r3, [r7, #4] 8000946: 6013 str r3, [r2, #0] return 0; 8000948: 2300 movs r3, #0 } 800094a: 4618 mov r0, r3 800094c: 3708 adds r7, #8 800094e: 46bd mov sp, r7 8000950: bd80 pop {r7, pc} 8000952: bf00 nop 8000954: 20000038 .word 0x20000038 08000958 : uint8 calculatePEC(uint8_t* data, uint8_t datalen) { 8000958: b580 push {r7, lr} 800095a: b086 sub sp, #24 800095c: af00 add r7, sp, #0 800095e: 6078 str r0, [r7, #4] 8000960: 460b mov r3, r1 8000962: 70fb strb r3, [r7, #3] uint16 currentpec = INITAL_PEC; 8000964: 2310 movs r3, #16 8000966: 82fb strh r3, [r7, #22] if(datalen >= 3) 8000968: 78fb ldrb r3, [r7, #3] 800096a: 2b02 cmp r3, #2 800096c: d937 bls.n 80009de { for(int i = 0; i < (datalen-2); i++) 800096e: 2300 movs r3, #0 8000970: 613b str r3, [r7, #16] 8000972: e01c b.n 80009ae { for(int n = 0; n < 8;n++) 8000974: 2300 movs r3, #0 8000976: 60fb str r3, [r7, #12] 8000978: e013 b.n 80009a2 { uint8 din = data[i] << (n); 800097a: 693b ldr r3, [r7, #16] 800097c: 687a ldr r2, [r7, #4] 800097e: 4413 add r3, r2 8000980: 781b ldrb r3, [r3, #0] 8000982: 461a mov r2, r3 8000984: 68fb ldr r3, [r7, #12] 8000986: fa02 f303 lsl.w r3, r2, r3 800098a: 72fb strb r3, [r7, #11] currentpec = updatePEC(currentpec, din); 800098c: 7afa ldrb r2, [r7, #11] 800098e: 8afb ldrh r3, [r7, #22] 8000990: 4611 mov r1, r2 8000992: 4618 mov r0, r3 8000994: f000 f878 bl 8000a88 8000998: 4603 mov r3, r0 800099a: 82fb strh r3, [r7, #22] for(int n = 0; n < 8;n++) 800099c: 68fb ldr r3, [r7, #12] 800099e: 3301 adds r3, #1 80009a0: 60fb str r3, [r7, #12] 80009a2: 68fb ldr r3, [r7, #12] 80009a4: 2b07 cmp r3, #7 80009a6: dde8 ble.n 800097a for(int i = 0; i < (datalen-2); i++) 80009a8: 693b ldr r3, [r7, #16] 80009aa: 3301 adds r3, #1 80009ac: 613b str r3, [r7, #16] 80009ae: 78fb ldrb r3, [r7, #3] 80009b0: 3b02 subs r3, #2 80009b2: 693a ldr r2, [r7, #16] 80009b4: 429a cmp r2, r3 80009b6: dbdd blt.n 8000974 } } data[datalen-2] = (currentpec>>7) & 0xFF; 80009b8: 8afb ldrh r3, [r7, #22] 80009ba: 09db lsrs r3, r3, #7 80009bc: b299 uxth r1, r3 80009be: 78fb ldrb r3, [r7, #3] 80009c0: 3b02 subs r3, #2 80009c2: 687a ldr r2, [r7, #4] 80009c4: 4413 add r3, r2 80009c6: b2ca uxtb r2, r1 80009c8: 701a strb r2, [r3, #0] data[datalen-1] = (currentpec<<1) & 0xFF; 80009ca: 8afb ldrh r3, [r7, #22] 80009cc: 0059 lsls r1, r3, #1 80009ce: 78fb ldrb r3, [r7, #3] 80009d0: 3b01 subs r3, #1 80009d2: 687a ldr r2, [r7, #4] 80009d4: 4413 add r3, r2 80009d6: b2ca uxtb r2, r1 80009d8: 701a strb r2, [r3, #0] return 0; 80009da: 2300 movs r3, #0 80009dc: e000 b.n 80009e0 } else { return 1; 80009de: 2301 movs r3, #1 } } 80009e0: 4618 mov r0, r3 80009e2: 3718 adds r7, #24 80009e4: 46bd mov sp, r7 80009e6: bd80 pop {r7, pc} 080009e8 : uint8 checkPEC(uint8* data, uint8 datalen) { 80009e8: b580 push {r7, lr} 80009ea: b086 sub sp, #24 80009ec: af00 add r7, sp, #0 80009ee: 6078 str r0, [r7, #4] 80009f0: 460b mov r3, r1 80009f2: 70fb strb r3, [r7, #3] if(datalen <= 3) 80009f4: 78fb ldrb r3, [r7, #3] 80009f6: 2b03 cmp r3, #3 80009f8: d801 bhi.n 80009fe { return 255; 80009fa: 23ff movs r3, #255 ; 0xff 80009fc: e040 b.n 8000a80 } uint16 currentpec = INITAL_PEC; 80009fe: 2310 movs r3, #16 8000a00: 82fb strh r3, [r7, #22] for(int i = 0; i < (datalen-2); i++) 8000a02: 2300 movs r3, #0 8000a04: 613b str r3, [r7, #16] 8000a06: e01c b.n 8000a42 { for(int n = 0; n < 8;n++) 8000a08: 2300 movs r3, #0 8000a0a: 60fb str r3, [r7, #12] 8000a0c: e013 b.n 8000a36 { uint8 din = data[i] << (n); 8000a0e: 693b ldr r3, [r7, #16] 8000a10: 687a ldr r2, [r7, #4] 8000a12: 4413 add r3, r2 8000a14: 781b ldrb r3, [r3, #0] 8000a16: 461a mov r2, r3 8000a18: 68fb ldr r3, [r7, #12] 8000a1a: fa02 f303 lsl.w r3, r2, r3 8000a1e: 727b strb r3, [r7, #9] currentpec = updatePEC(currentpec, din); 8000a20: 7a7a ldrb r2, [r7, #9] 8000a22: 8afb ldrh r3, [r7, #22] 8000a24: 4611 mov r1, r2 8000a26: 4618 mov r0, r3 8000a28: f000 f82e bl 8000a88 8000a2c: 4603 mov r3, r0 8000a2e: 82fb strh r3, [r7, #22] for(int n = 0; n < 8;n++) 8000a30: 68fb ldr r3, [r7, #12] 8000a32: 3301 adds r3, #1 8000a34: 60fb str r3, [r7, #12] 8000a36: 68fb ldr r3, [r7, #12] 8000a38: 2b07 cmp r3, #7 8000a3a: dde8 ble.n 8000a0e for(int i = 0; i < (datalen-2); i++) 8000a3c: 693b ldr r3, [r7, #16] 8000a3e: 3301 adds r3, #1 8000a40: 613b str r3, [r7, #16] 8000a42: 78fb ldrb r3, [r7, #3] 8000a44: 3b02 subs r3, #2 8000a46: 693a ldr r2, [r7, #16] 8000a48: 429a cmp r2, r3 8000a4a: dbdd blt.n 8000a08 } } uint8 pechigh = (currentpec>>7) & 0xFF; 8000a4c: 8afb ldrh r3, [r7, #22] 8000a4e: 09db lsrs r3, r3, #7 8000a50: b29b uxth r3, r3 8000a52: 72fb strb r3, [r7, #11] uint8 peclow = (currentpec<<1) & 0xFF; 8000a54: 8afb ldrh r3, [r7, #22] 8000a56: 005b lsls r3, r3, #1 8000a58: 72bb strb r3, [r7, #10] if((pechigh == data[datalen-2]) && (peclow == data[datalen-1])) 8000a5a: 78fb ldrb r3, [r7, #3] 8000a5c: 3b02 subs r3, #2 8000a5e: 687a ldr r2, [r7, #4] 8000a60: 4413 add r3, r2 8000a62: 781b ldrb r3, [r3, #0] 8000a64: 7afa ldrb r2, [r7, #11] 8000a66: 429a cmp r2, r3 8000a68: d109 bne.n 8000a7e 8000a6a: 78fb ldrb r3, [r7, #3] 8000a6c: 3b01 subs r3, #1 8000a6e: 687a ldr r2, [r7, #4] 8000a70: 4413 add r3, r2 8000a72: 781b ldrb r3, [r3, #0] 8000a74: 7aba ldrb r2, [r7, #10] 8000a76: 429a cmp r2, r3 8000a78: d101 bne.n 8000a7e { return 0; 8000a7a: 2300 movs r3, #0 8000a7c: e000 b.n 8000a80 } return 1; 8000a7e: 2301 movs r3, #1 } 8000a80: 4618 mov r0, r3 8000a82: 3718 adds r7, #24 8000a84: 46bd mov sp, r7 8000a86: bd80 pop {r7, pc} 08000a88 : uint16 updatePEC(uint16 currentPEC, uint8 din) { 8000a88: b480 push {r7} 8000a8a: b087 sub sp, #28 8000a8c: af00 add r7, sp, #0 8000a8e: 4603 mov r3, r0 8000a90: 460a mov r2, r1 8000a92: 80fb strh r3, [r7, #6] 8000a94: 4613 mov r3, r2 8000a96: 717b strb r3, [r7, #5] din = (din>>7) & 0x01; 8000a98: 797b ldrb r3, [r7, #5] 8000a9a: 09db lsrs r3, r3, #7 8000a9c: 717b strb r3, [r7, #5] uint8 in0 = din ^ ((currentPEC >> 14) &0x01); 8000a9e: 88fb ldrh r3, [r7, #6] 8000aa0: 0b9b lsrs r3, r3, #14 8000aa2: b29b uxth r3, r3 8000aa4: b25b sxtb r3, r3 8000aa6: f003 0301 and.w r3, r3, #1 8000aaa: b25a sxtb r2, r3 8000aac: f997 3005 ldrsb.w r3, [r7, #5] 8000ab0: 4053 eors r3, r2 8000ab2: b25b sxtb r3, r3 8000ab4: 75fb strb r3, [r7, #23] uint8 in3 = in0 ^ ((currentPEC >> 2) &0x01); 8000ab6: 88fb ldrh r3, [r7, #6] 8000ab8: 089b lsrs r3, r3, #2 8000aba: b29b uxth r3, r3 8000abc: b25b sxtb r3, r3 8000abe: f003 0301 and.w r3, r3, #1 8000ac2: b25a sxtb r2, r3 8000ac4: f997 3017 ldrsb.w r3, [r7, #23] 8000ac8: 4053 eors r3, r2 8000aca: b25b sxtb r3, r3 8000acc: 75bb strb r3, [r7, #22] uint8 in4 = in0 ^ ((currentPEC >> 3) &0x01); 8000ace: 88fb ldrh r3, [r7, #6] 8000ad0: 08db lsrs r3, r3, #3 8000ad2: b29b uxth r3, r3 8000ad4: b25b sxtb r3, r3 8000ad6: f003 0301 and.w r3, r3, #1 8000ada: b25a sxtb r2, r3 8000adc: f997 3017 ldrsb.w r3, [r7, #23] 8000ae0: 4053 eors r3, r2 8000ae2: b25b sxtb r3, r3 8000ae4: 757b strb r3, [r7, #21] uint8 in7 = in0 ^ ((currentPEC >> 6) &0x01); 8000ae6: 88fb ldrh r3, [r7, #6] 8000ae8: 099b lsrs r3, r3, #6 8000aea: b29b uxth r3, r3 8000aec: b25b sxtb r3, r3 8000aee: f003 0301 and.w r3, r3, #1 8000af2: b25a sxtb r2, r3 8000af4: f997 3017 ldrsb.w r3, [r7, #23] 8000af8: 4053 eors r3, r2 8000afa: b25b sxtb r3, r3 8000afc: 753b strb r3, [r7, #20] uint8 in8 = in0 ^ ((currentPEC >> 7) &0x01); 8000afe: 88fb ldrh r3, [r7, #6] 8000b00: 09db lsrs r3, r3, #7 8000b02: b29b uxth r3, r3 8000b04: b25b sxtb r3, r3 8000b06: f003 0301 and.w r3, r3, #1 8000b0a: b25a sxtb r2, r3 8000b0c: f997 3017 ldrsb.w r3, [r7, #23] 8000b10: 4053 eors r3, r2 8000b12: b25b sxtb r3, r3 8000b14: 74fb strb r3, [r7, #19] uint8 in10 = in0 ^ ((currentPEC >> 9) &0x01); 8000b16: 88fb ldrh r3, [r7, #6] 8000b18: 0a5b lsrs r3, r3, #9 8000b1a: b29b uxth r3, r3 8000b1c: b25b sxtb r3, r3 8000b1e: f003 0301 and.w r3, r3, #1 8000b22: b25a sxtb r2, r3 8000b24: f997 3017 ldrsb.w r3, [r7, #23] 8000b28: 4053 eors r3, r2 8000b2a: b25b sxtb r3, r3 8000b2c: 74bb strb r3, [r7, #18] uint8 in14 = in0 ^ ((currentPEC >> 13) &0x01); 8000b2e: 88fb ldrh r3, [r7, #6] 8000b30: 0b5b lsrs r3, r3, #13 8000b32: b29b uxth r3, r3 8000b34: b25b sxtb r3, r3 8000b36: f003 0301 and.w r3, r3, #1 8000b3a: b25a sxtb r2, r3 8000b3c: f997 3017 ldrsb.w r3, [r7, #23] 8000b40: 4053 eors r3, r2 8000b42: b25b sxtb r3, r3 8000b44: 747b strb r3, [r7, #17] uint16 newPEC = 0; 8000b46: 2300 movs r3, #0 8000b48: 81fb strh r3, [r7, #14] newPEC |= in14<<14; 8000b4a: 7c7b ldrb r3, [r7, #17] 8000b4c: 039b lsls r3, r3, #14 8000b4e: b21a sxth r2, r3 8000b50: f9b7 300e ldrsh.w r3, [r7, #14] 8000b54: 4313 orrs r3, r2 8000b56: b21b sxth r3, r3 8000b58: 81fb strh r3, [r7, #14] newPEC |= (currentPEC & (0x01<<12))<<1; 8000b5a: 88fb ldrh r3, [r7, #6] 8000b5c: 005b lsls r3, r3, #1 8000b5e: b21b sxth r3, r3 8000b60: f403 5300 and.w r3, r3, #8192 ; 0x2000 8000b64: b21a sxth r2, r3 8000b66: f9b7 300e ldrsh.w r3, [r7, #14] 8000b6a: 4313 orrs r3, r2 8000b6c: b21b sxth r3, r3 8000b6e: 81fb strh r3, [r7, #14] newPEC |= (currentPEC & (0x01<<11))<<1; 8000b70: 88fb ldrh r3, [r7, #6] 8000b72: 005b lsls r3, r3, #1 8000b74: b21b sxth r3, r3 8000b76: f403 5380 and.w r3, r3, #4096 ; 0x1000 8000b7a: b21a sxth r2, r3 8000b7c: f9b7 300e ldrsh.w r3, [r7, #14] 8000b80: 4313 orrs r3, r2 8000b82: b21b sxth r3, r3 8000b84: 81fb strh r3, [r7, #14] newPEC |= (currentPEC & (0x01<<10))<<1; 8000b86: 88fb ldrh r3, [r7, #6] 8000b88: 005b lsls r3, r3, #1 8000b8a: b21b sxth r3, r3 8000b8c: f403 6300 and.w r3, r3, #2048 ; 0x800 8000b90: b21a sxth r2, r3 8000b92: f9b7 300e ldrsh.w r3, [r7, #14] 8000b96: 4313 orrs r3, r2 8000b98: b21b sxth r3, r3 8000b9a: 81fb strh r3, [r7, #14] newPEC |= in10<<10; 8000b9c: 7cbb ldrb r3, [r7, #18] 8000b9e: 029b lsls r3, r3, #10 8000ba0: b21a sxth r2, r3 8000ba2: f9b7 300e ldrsh.w r3, [r7, #14] 8000ba6: 4313 orrs r3, r2 8000ba8: b21b sxth r3, r3 8000baa: 81fb strh r3, [r7, #14] newPEC |= (currentPEC & (0x01<<8))<<1; 8000bac: 88fb ldrh r3, [r7, #6] 8000bae: 005b lsls r3, r3, #1 8000bb0: b21b sxth r3, r3 8000bb2: f403 7300 and.w r3, r3, #512 ; 0x200 8000bb6: b21a sxth r2, r3 8000bb8: f9b7 300e ldrsh.w r3, [r7, #14] 8000bbc: 4313 orrs r3, r2 8000bbe: b21b sxth r3, r3 8000bc0: 81fb strh r3, [r7, #14] newPEC |= in8<<8; 8000bc2: 7cfb ldrb r3, [r7, #19] 8000bc4: 021b lsls r3, r3, #8 8000bc6: b21a sxth r2, r3 8000bc8: f9b7 300e ldrsh.w r3, [r7, #14] 8000bcc: 4313 orrs r3, r2 8000bce: b21b sxth r3, r3 8000bd0: 81fb strh r3, [r7, #14] newPEC |= in7<<7; 8000bd2: 7d3b ldrb r3, [r7, #20] 8000bd4: 01db lsls r3, r3, #7 8000bd6: b21a sxth r2, r3 8000bd8: f9b7 300e ldrsh.w r3, [r7, #14] 8000bdc: 4313 orrs r3, r2 8000bde: b21b sxth r3, r3 8000be0: 81fb strh r3, [r7, #14] newPEC |= (currentPEC & (0x01<<5))<<1; 8000be2: 88fb ldrh r3, [r7, #6] 8000be4: 005b lsls r3, r3, #1 8000be6: b21b sxth r3, r3 8000be8: f003 0340 and.w r3, r3, #64 ; 0x40 8000bec: b21a sxth r2, r3 8000bee: f9b7 300e ldrsh.w r3, [r7, #14] 8000bf2: 4313 orrs r3, r2 8000bf4: b21b sxth r3, r3 8000bf6: 81fb strh r3, [r7, #14] newPEC |= (currentPEC & (0x01<<4))<<1; 8000bf8: 88fb ldrh r3, [r7, #6] 8000bfa: 005b lsls r3, r3, #1 8000bfc: b21b sxth r3, r3 8000bfe: f003 0320 and.w r3, r3, #32 8000c02: b21a sxth r2, r3 8000c04: f9b7 300e ldrsh.w r3, [r7, #14] 8000c08: 4313 orrs r3, r2 8000c0a: b21b sxth r3, r3 8000c0c: 81fb strh r3, [r7, #14] newPEC |= in4<<4; 8000c0e: 7d7b ldrb r3, [r7, #21] 8000c10: 011b lsls r3, r3, #4 8000c12: b21a sxth r2, r3 8000c14: f9b7 300e ldrsh.w r3, [r7, #14] 8000c18: 4313 orrs r3, r2 8000c1a: b21b sxth r3, r3 8000c1c: 81fb strh r3, [r7, #14] newPEC |= in3<<3; 8000c1e: 7dbb ldrb r3, [r7, #22] 8000c20: 00db lsls r3, r3, #3 8000c22: b21a sxth r2, r3 8000c24: f9b7 300e ldrsh.w r3, [r7, #14] 8000c28: 4313 orrs r3, r2 8000c2a: b21b sxth r3, r3 8000c2c: 81fb strh r3, [r7, #14] newPEC |= (currentPEC & (0x01<<1))<<1; 8000c2e: 88fb ldrh r3, [r7, #6] 8000c30: 005b lsls r3, r3, #1 8000c32: b21b sxth r3, r3 8000c34: f003 0304 and.w r3, r3, #4 8000c38: b21a sxth r2, r3 8000c3a: f9b7 300e ldrsh.w r3, [r7, #14] 8000c3e: 4313 orrs r3, r2 8000c40: b21b sxth r3, r3 8000c42: 81fb strh r3, [r7, #14] newPEC |= (currentPEC & (0x01))<<1; 8000c44: 88fb ldrh r3, [r7, #6] 8000c46: 005b lsls r3, r3, #1 8000c48: b21b sxth r3, r3 8000c4a: f003 0302 and.w r3, r3, #2 8000c4e: b21a sxth r2, r3 8000c50: f9b7 300e ldrsh.w r3, [r7, #14] 8000c54: 4313 orrs r3, r2 8000c56: b21b sxth r3, r3 8000c58: 81fb strh r3, [r7, #14] newPEC |= in0; 8000c5a: 7dfb ldrb r3, [r7, #23] 8000c5c: b29a uxth r2, r3 8000c5e: 89fb ldrh r3, [r7, #14] 8000c60: 4313 orrs r3, r2 8000c62: 81fb strh r3, [r7, #14] return newPEC; 8000c64: 89fb ldrh r3, [r7, #14] } 8000c66: 4618 mov r0, r3 8000c68: 371c adds r7, #28 8000c6a: 46bd mov sp, r7 8000c6c: f85d 7b04 ldr.w r7, [sp], #4 8000c70: 4770 bx lr 08000c72 : uint8 writeCMD(uint16 command, uint8* args, uint8 arglen) { 8000c72: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8000c76: b087 sub sp, #28 8000c78: af00 add r7, sp, #0 8000c7a: 4603 mov r3, r0 8000c7c: 6039 str r1, [r7, #0] 8000c7e: 80fb strh r3, [r7, #6] 8000c80: 4613 mov r3, r2 8000c82: 717b strb r3, [r7, #5] if(arglen > 0) 8000c84: 797b ldrb r3, [r7, #5] 8000c86: 2b00 cmp r3, #0 8000c88: d05e beq.n 8000d48 { 8000c8a: 466b mov r3, sp 8000c8c: 461e mov r6, r3 uint8 buffer[6+arglen]; 8000c8e: 797b ldrb r3, [r7, #5] 8000c90: 1d99 adds r1, r3, #6 8000c92: 1e4b subs r3, r1, #1 8000c94: 613b str r3, [r7, #16] 8000c96: 460a mov r2, r1 8000c98: 2300 movs r3, #0 8000c9a: 4690 mov r8, r2 8000c9c: 4699 mov r9, r3 8000c9e: f04f 0200 mov.w r2, #0 8000ca2: f04f 0300 mov.w r3, #0 8000ca6: ea4f 03c9 mov.w r3, r9, lsl #3 8000caa: ea43 7358 orr.w r3, r3, r8, lsr #29 8000cae: ea4f 02c8 mov.w r2, r8, lsl #3 8000cb2: 460a mov r2, r1 8000cb4: 2300 movs r3, #0 8000cb6: 4614 mov r4, r2 8000cb8: 461d mov r5, r3 8000cba: f04f 0200 mov.w r2, #0 8000cbe: f04f 0300 mov.w r3, #0 8000cc2: 00eb lsls r3, r5, #3 8000cc4: ea43 7354 orr.w r3, r3, r4, lsr #29 8000cc8: 00e2 lsls r2, r4, #3 8000cca: 460b mov r3, r1 8000ccc: 3307 adds r3, #7 8000cce: 08db lsrs r3, r3, #3 8000cd0: 00db lsls r3, r3, #3 8000cd2: ebad 0d03 sub.w sp, sp, r3 8000cd6: 466b mov r3, sp 8000cd8: 3300 adds r3, #0 8000cda: 60fb str r3, [r7, #12] buffer[0] = (command >> 8) & 0xFF; 8000cdc: 88fb ldrh r3, [r7, #6] 8000cde: 0a1b lsrs r3, r3, #8 8000ce0: b29b uxth r3, r3 8000ce2: b2da uxtb r2, r3 8000ce4: 68fb ldr r3, [r7, #12] 8000ce6: 701a strb r2, [r3, #0] buffer[1] = (command) & 0xFF; 8000ce8: 88fb ldrh r3, [r7, #6] 8000cea: b2da uxtb r2, r3 8000cec: 68fb ldr r3, [r7, #12] 8000cee: 705a strb r2, [r3, #1] calculatePEC(buffer, 4); 8000cf0: 2104 movs r1, #4 8000cf2: 68f8 ldr r0, [r7, #12] 8000cf4: f7ff fe30 bl 8000958 for(uint8 i = 0; i < arglen; i++) 8000cf8: 2300 movs r3, #0 8000cfa: 75fb strb r3, [r7, #23] 8000cfc: e00a b.n 8000d14 { buffer[4+i] = args[i]; 8000cfe: 7dfb ldrb r3, [r7, #23] 8000d00: 683a ldr r2, [r7, #0] 8000d02: 441a add r2, r3 8000d04: 7dfb ldrb r3, [r7, #23] 8000d06: 3304 adds r3, #4 8000d08: 7811 ldrb r1, [r2, #0] 8000d0a: 68fa ldr r2, [r7, #12] 8000d0c: 54d1 strb r1, [r2, r3] for(uint8 i = 0; i < arglen; i++) 8000d0e: 7dfb ldrb r3, [r7, #23] 8000d10: 3301 adds r3, #1 8000d12: 75fb strb r3, [r7, #23] 8000d14: 7dfa ldrb r2, [r7, #23] 8000d16: 797b ldrb r3, [r7, #5] 8000d18: 429a cmp r2, r3 8000d1a: d3f0 bcc.n 8000cfe } calculatePEC(&buffer[4], arglen+2); //Calculate PEC of Data Part with offset of 4 Bytes for CMD and CMD PEC 8000d1c: 68fb ldr r3, [r7, #12] 8000d1e: 1d1a adds r2, r3, #4 8000d20: 797b ldrb r3, [r7, #5] 8000d22: 3302 adds r3, #2 8000d24: b2db uxtb r3, r3 8000d26: 4619 mov r1, r3 8000d28: 4610 mov r0, r2 8000d2a: f7ff fe15 bl 8000958 mcuAdbmsCSLow(); 8000d2e: f000 f8db bl 8000ee8 mcuSPITransmit(buffer, 6+arglen); 8000d32: 797b ldrb r3, [r7, #5] 8000d34: 3306 adds r3, #6 8000d36: b2db uxtb r3, r3 8000d38: 4619 mov r1, r3 8000d3a: 68f8 ldr r0, [r7, #12] 8000d3c: f000 f8e8 bl 8000f10 mcuAdbmsCSHigh(); 8000d40: f000 f8dc bl 8000efc 8000d44: 46b5 mov sp, r6 8000d46: e017 b.n 8000d78 } else { uint8 buffer[4]; buffer[0] = (command >> 8) & 0xFF; 8000d48: 88fb ldrh r3, [r7, #6] 8000d4a: 0a1b lsrs r3, r3, #8 8000d4c: b29b uxth r3, r3 8000d4e: b2db uxtb r3, r3 8000d50: 723b strb r3, [r7, #8] buffer[1] = (command) & 0xFF; 8000d52: 88fb ldrh r3, [r7, #6] 8000d54: b2db uxtb r3, r3 8000d56: 727b strb r3, [r7, #9] calculatePEC(buffer, 4); 8000d58: f107 0308 add.w r3, r7, #8 8000d5c: 2104 movs r1, #4 8000d5e: 4618 mov r0, r3 8000d60: f7ff fdfa bl 8000958 mcuAdbmsCSLow(); 8000d64: f000 f8c0 bl 8000ee8 mcuSPITransmit(buffer, 4); 8000d68: f107 0308 add.w r3, r7, #8 8000d6c: 2104 movs r1, #4 8000d6e: 4618 mov r0, r3 8000d70: f000 f8ce bl 8000f10 mcuAdbmsCSHigh(); 8000d74: f000 f8c2 bl 8000efc } return 0; 8000d78: 2300 movs r3, #0 } 8000d7a: 4618 mov r0, r3 8000d7c: 371c adds r7, #28 8000d7e: 46bd mov sp, r7 8000d80: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 08000d84 : uint8 readCMD(uint16 command, uint8* buffer, uint8 buflen) { 8000d84: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8000d88: b08b sub sp, #44 ; 0x2c 8000d8a: af00 add r7, sp, #0 8000d8c: 4603 mov r3, r0 8000d8e: 60b9 str r1, [r7, #8] 8000d90: 81fb strh r3, [r7, #14] 8000d92: 4613 mov r3, r2 8000d94: 737b strb r3, [r7, #13] 8000d96: 466b mov r3, sp 8000d98: 461e mov r6, r3 //uint8* txbuffer = (uint8*) malloc(6+buflen); //uint8* rxbuffer = (uint8*) malloc(6+buflen); uint8 txbuffer[6+buflen]; 8000d9a: 7b7b ldrb r3, [r7, #13] 8000d9c: 1d99 adds r1, r3, #6 8000d9e: 1e4b subs r3, r1, #1 8000da0: 627b str r3, [r7, #36] ; 0x24 8000da2: 460a mov r2, r1 8000da4: 2300 movs r3, #0 8000da6: 603a str r2, [r7, #0] 8000da8: 607b str r3, [r7, #4] 8000daa: f04f 0200 mov.w r2, #0 8000dae: f04f 0300 mov.w r3, #0 8000db2: 6878 ldr r0, [r7, #4] 8000db4: 00c3 lsls r3, r0, #3 8000db6: 6838 ldr r0, [r7, #0] 8000db8: ea43 7350 orr.w r3, r3, r0, lsr #29 8000dbc: 6838 ldr r0, [r7, #0] 8000dbe: 00c2 lsls r2, r0, #3 8000dc0: 460a mov r2, r1 8000dc2: 2300 movs r3, #0 8000dc4: 4692 mov sl, r2 8000dc6: 469b mov fp, r3 8000dc8: f04f 0200 mov.w r2, #0 8000dcc: f04f 0300 mov.w r3, #0 8000dd0: ea4f 03cb mov.w r3, fp, lsl #3 8000dd4: ea43 735a orr.w r3, r3, sl, lsr #29 8000dd8: ea4f 02ca mov.w r2, sl, lsl #3 8000ddc: 460b mov r3, r1 8000dde: 3307 adds r3, #7 8000de0: 08db lsrs r3, r3, #3 8000de2: 00db lsls r3, r3, #3 8000de4: ebad 0d03 sub.w sp, sp, r3 8000de8: 466b mov r3, sp 8000dea: 3300 adds r3, #0 8000dec: 61fb str r3, [r7, #28] uint8 rxbuffer[6+buflen]; 8000dee: 7b7b ldrb r3, [r7, #13] 8000df0: 1d99 adds r1, r3, #6 8000df2: 1e4b subs r3, r1, #1 8000df4: 61bb str r3, [r7, #24] 8000df6: 460a mov r2, r1 8000df8: 2300 movs r3, #0 8000dfa: 4690 mov r8, r2 8000dfc: 4699 mov r9, r3 8000dfe: f04f 0200 mov.w r2, #0 8000e02: f04f 0300 mov.w r3, #0 8000e06: ea4f 03c9 mov.w r3, r9, lsl #3 8000e0a: ea43 7358 orr.w r3, r3, r8, lsr #29 8000e0e: ea4f 02c8 mov.w r2, r8, lsl #3 8000e12: 460a mov r2, r1 8000e14: 2300 movs r3, #0 8000e16: 4614 mov r4, r2 8000e18: 461d mov r5, r3 8000e1a: f04f 0200 mov.w r2, #0 8000e1e: f04f 0300 mov.w r3, #0 8000e22: 00eb lsls r3, r5, #3 8000e24: ea43 7354 orr.w r3, r3, r4, lsr #29 8000e28: 00e2 lsls r2, r4, #3 8000e2a: 460b mov r3, r1 8000e2c: 3307 adds r3, #7 8000e2e: 08db lsrs r3, r3, #3 8000e30: 00db lsls r3, r3, #3 8000e32: ebad 0d03 sub.w sp, sp, r3 8000e36: 466b mov r3, sp 8000e38: 3300 adds r3, #0 8000e3a: 617b str r3, [r7, #20] txbuffer[0] = (command >> 8) & 0xFF; 8000e3c: 89fb ldrh r3, [r7, #14] 8000e3e: 0a1b lsrs r3, r3, #8 8000e40: b29b uxth r3, r3 8000e42: b2da uxtb r2, r3 8000e44: 69fb ldr r3, [r7, #28] 8000e46: 701a strb r2, [r3, #0] txbuffer[1] = (command) & 0xFF; 8000e48: 89fb ldrh r3, [r7, #14] 8000e4a: b2da uxtb r2, r3 8000e4c: 69fb ldr r3, [r7, #28] 8000e4e: 705a strb r2, [r3, #1] calculatePEC(txbuffer, 4); 8000e50: 2104 movs r1, #4 8000e52: 69f8 ldr r0, [r7, #28] 8000e54: f7ff fd80 bl 8000958 mcuAdbmsCSLow(); 8000e58: f000 f846 bl 8000ee8 mcuSPITransmitReceive(rxbuffer, txbuffer, 6+buflen); 8000e5c: 7b7b ldrb r3, [r7, #13] 8000e5e: 3306 adds r3, #6 8000e60: b2db uxtb r3, r3 8000e62: 461a mov r2, r3 8000e64: 69f9 ldr r1, [r7, #28] 8000e66: 6978 ldr r0, [r7, #20] 8000e68: f000 f8a6 bl 8000fb8 mcuAdbmsCSHigh(); 8000e6c: f000 f846 bl 8000efc for(uint8 i = 0; i { buffer[i] = rxbuffer[i+4]; 8000e78: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 8000e7c: 1d1a adds r2, r3, #4 8000e7e: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 8000e82: 68b9 ldr r1, [r7, #8] 8000e84: 440b add r3, r1 8000e86: 6979 ldr r1, [r7, #20] 8000e88: 5c8a ldrb r2, [r1, r2] 8000e8a: 701a strb r2, [r3, #0] for(uint8 i = 0; i } uint8 peccheck = checkPEC(&rxbuffer[4], buflen+2); 8000ea0: 697b ldr r3, [r7, #20] 8000ea2: 1d1a adds r2, r3, #4 8000ea4: 7b7b ldrb r3, [r7, #13] 8000ea6: 3302 adds r3, #2 8000ea8: b2db uxtb r3, r3 8000eaa: 4619 mov r1, r3 8000eac: 4610 mov r0, r2 8000eae: f7ff fd9b bl 80009e8 8000eb2: 4603 mov r3, r0 8000eb4: 74fb strb r3, [r7, #19] //free(txbuffer); //free(rxbuffer); if(peccheck == 0) 8000eb6: 7cfb ldrb r3, [r7, #19] 8000eb8: 2b00 cmp r3, #0 8000eba: d101 bne.n 8000ec0 return 0; 8000ebc: 2300 movs r3, #0 8000ebe: e00b b.n 8000ed8 else { static int err_cnt = 0; if (err_cnt++ > 100) { 8000ec0: 4b08 ldr r3, [pc, #32] ; (8000ee4 ) 8000ec2: 681b ldr r3, [r3, #0] 8000ec4: 1c5a adds r2, r3, #1 8000ec6: 4907 ldr r1, [pc, #28] ; (8000ee4 ) 8000ec8: 600a str r2, [r1, #0] 8000eca: 2b64 cmp r3, #100 ; 0x64 8000ecc: dd03 ble.n 8000ed6 Error_Handler(); 8000ece: f000 ffb3 bl 8001e38 8000ed2: 46b5 mov sp, r6 } else { return 1; } } } 8000ed4: e001 b.n 8000eda return 1; 8000ed6: 2301 movs r3, #1 8000ed8: 46b5 mov sp, r6 } 8000eda: 4618 mov r0, r3 8000edc: 372c adds r7, #44 ; 0x2c 8000ede: 46bd mov sp, r7 8000ee0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8000ee4: 2000003c .word 0x2000003c 08000ee8 : void mcuAdbmsCSLow() { 8000ee8: b580 push {r7, lr} 8000eea: af00 add r7, sp, #0 HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_RESET); 8000eec: 2200 movs r2, #0 8000eee: 2110 movs r1, #16 8000ef0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8000ef4: f002 faf2 bl 80034dc } 8000ef8: bf00 nop 8000efa: bd80 pop {r7, pc} 08000efc : void mcuAdbmsCSHigh() { 8000efc: b580 push {r7, lr} 8000efe: af00 add r7, sp, #0 HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_SET); 8000f00: 2201 movs r2, #1 8000f02: 2110 movs r1, #16 8000f04: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8000f08: f002 fae8 bl 80034dc } 8000f0c: bf00 nop 8000f0e: bd80 pop {r7, pc} 08000f10 : uint8 mcuSPITransmit(uint8* buffer, uint8 buffersize) { 8000f10: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8000f14: b089 sub sp, #36 ; 0x24 8000f16: af02 add r7, sp, #8 8000f18: 6078 str r0, [r7, #4] 8000f1a: 460b mov r3, r1 8000f1c: 70fb strb r3, [r7, #3] 8000f1e: 466b mov r3, sp 8000f20: 461e mov r6, r3 HAL_StatusTypeDef status; //status = HAL_SPI_Transmit(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOUT); //uint8 *rxbuf = (uint8*) malloc(buffersize); uint8 rxbuf[buffersize]; 8000f22: 78f9 ldrb r1, [r7, #3] 8000f24: 460b mov r3, r1 8000f26: 3b01 subs r3, #1 8000f28: 617b str r3, [r7, #20] 8000f2a: b2cb uxtb r3, r1 8000f2c: 2200 movs r2, #0 8000f2e: 4698 mov r8, r3 8000f30: 4691 mov r9, r2 8000f32: f04f 0200 mov.w r2, #0 8000f36: f04f 0300 mov.w r3, #0 8000f3a: ea4f 03c9 mov.w r3, r9, lsl #3 8000f3e: ea43 7358 orr.w r3, r3, r8, lsr #29 8000f42: ea4f 02c8 mov.w r2, r8, lsl #3 8000f46: b2cb uxtb r3, r1 8000f48: 2200 movs r2, #0 8000f4a: 461c mov r4, r3 8000f4c: 4615 mov r5, r2 8000f4e: f04f 0200 mov.w r2, #0 8000f52: f04f 0300 mov.w r3, #0 8000f56: 00eb lsls r3, r5, #3 8000f58: ea43 7354 orr.w r3, r3, r4, lsr #29 8000f5c: 00e2 lsls r2, r4, #3 8000f5e: 460b mov r3, r1 8000f60: 3307 adds r3, #7 8000f62: 08db lsrs r3, r3, #3 8000f64: 00db lsls r3, r3, #3 8000f66: ebad 0d03 sub.w sp, sp, r3 8000f6a: ab02 add r3, sp, #8 8000f6c: 3300 adds r3, #0 8000f6e: 613b str r3, [r7, #16] status = HAL_SPI_TransmitReceive(adbmsspi, buffer, rxbuf, buffersize, ADBMS_SPI_TIMEOUT); 8000f70: 4b10 ldr r3, [pc, #64] ; (8000fb4 ) 8000f72: 6818 ldr r0, [r3, #0] 8000f74: 78fb ldrb r3, [r7, #3] 8000f76: b29b uxth r3, r3 8000f78: f44f 727a mov.w r2, #1000 ; 0x3e8 8000f7c: 9200 str r2, [sp, #0] 8000f7e: 693a ldr r2, [r7, #16] 8000f80: 6879 ldr r1, [r7, #4] 8000f82: f004 fefe bl 8005d82 8000f86: 4603 mov r3, r0 8000f88: 73fb strb r3, [r7, #15] __HAL_SPI_CLEAR_OVRFLAG(adbmsspi); 8000f8a: 2300 movs r3, #0 8000f8c: 60bb str r3, [r7, #8] 8000f8e: 4b09 ldr r3, [pc, #36] ; (8000fb4 ) 8000f90: 681b ldr r3, [r3, #0] 8000f92: 681b ldr r3, [r3, #0] 8000f94: 68db ldr r3, [r3, #12] 8000f96: 60bb str r3, [r7, #8] 8000f98: 4b06 ldr r3, [pc, #24] ; (8000fb4 ) 8000f9a: 681b ldr r3, [r3, #0] 8000f9c: 681b ldr r3, [r3, #0] 8000f9e: 689b ldr r3, [r3, #8] 8000fa0: 60bb str r3, [r7, #8] 8000fa2: 68bb ldr r3, [r7, #8] //free(rxbuf); return status; 8000fa4: 7bfb ldrb r3, [r7, #15] 8000fa6: 46b5 mov sp, r6 } 8000fa8: 4618 mov r0, r3 8000faa: 371c adds r7, #28 8000fac: 46bd mov sp, r7 8000fae: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8000fb2: bf00 nop 8000fb4: 20000038 .word 0x20000038 08000fb8 : status = HAL_SPI_Receive(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOUT); return status; } uint8 mcuSPITransmitReceive(uint8* rxbuffer, uint8* txbuffer, uint8 buffersize) { 8000fb8: b580 push {r7, lr} 8000fba: b088 sub sp, #32 8000fbc: af02 add r7, sp, #8 8000fbe: 60f8 str r0, [r7, #12] 8000fc0: 60b9 str r1, [r7, #8] 8000fc2: 4613 mov r3, r2 8000fc4: 71fb strb r3, [r7, #7] HAL_StatusTypeDef status; status = HAL_SPI_TransmitReceive(adbmsspi, txbuffer, rxbuffer, buffersize, ADBMS_SPI_TIMEOUT); 8000fc6: 4b09 ldr r3, [pc, #36] ; (8000fec ) 8000fc8: 6818 ldr r0, [r3, #0] 8000fca: 79fb ldrb r3, [r7, #7] 8000fcc: b29b uxth r3, r3 8000fce: f44f 727a mov.w r2, #1000 ; 0x3e8 8000fd2: 9200 str r2, [sp, #0] 8000fd4: 68fa ldr r2, [r7, #12] 8000fd6: 68b9 ldr r1, [r7, #8] 8000fd8: f004 fed3 bl 8005d82 8000fdc: 4603 mov r3, r0 8000fde: 75fb strb r3, [r7, #23] return status; 8000fe0: 7dfb ldrb r3, [r7, #23] } 8000fe2: 4618 mov r0, r3 8000fe4: 3718 adds r7, #24 8000fe6: 46bd mov sp, r7 8000fe8: bd80 pop {r7, pc} 8000fea: bf00 nop 8000fec: 20000038 .word 0x20000038 08000ff0 : inline void mcuDelay(uint16 delay) { 8000ff0: b580 push {r7, lr} 8000ff2: b082 sub sp, #8 8000ff4: af00 add r7, sp, #0 8000ff6: 4603 mov r3, r0 8000ff8: 80fb strh r3, [r7, #6] HAL_Delay(delay); 8000ffa: 88fb ldrh r3, [r7, #6] 8000ffc: 4618 mov r0, r3 8000ffe: f001 f93d bl 800227c } 8001002: bf00 nop 8001004: 3708 adds r7, #8 8001006: 46bd mov sp, r7 8001008: bd80 pop {r7, pc} ... 0800100c : CAN_HandleTypeDef* ams_can_handle; void ams_can_init(CAN_HandleTypeDef* ams_handle, CAN_HandleTypeDef* car_handle) { 800100c: b580 push {r7, lr} 800100e: b08c sub sp, #48 ; 0x30 8001010: af00 add r7, sp, #0 8001012: 6078 str r0, [r7, #4] 8001014: 6039 str r1, [r7, #0] ams_can_handle = ams_handle; 8001016: 4a2e ldr r2, [pc, #184] ; (80010d0 ) 8001018: 687b ldr r3, [r7, #4] 800101a: 6013 str r3, [r2, #0] // Start peripheral if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { 800101c: 4b2c ldr r3, [pc, #176] ; (80010d0 ) 800101e: 681b ldr r3, [r3, #0] 8001020: 4618 mov r0, r3 8001022: f001 fb14 bl 800264e 8001026: 4603 mov r3, r0 8001028: 2b00 cmp r3, #0 800102a: d00c beq.n 8001046 ams_can_handle = car_handle; 800102c: 4a28 ldr r2, [pc, #160] ; (80010d0 ) 800102e: 683b ldr r3, [r7, #0] 8001030: 6013 str r3, [r2, #0] if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { 8001032: 4b27 ldr r3, [pc, #156] ; (80010d0 ) 8001034: 681b ldr r3, [r3, #0] 8001036: 4618 mov r0, r3 8001038: f001 fb09 bl 800264e 800103c: 4603 mov r3, r0 800103e: 2b00 cmp r3, #0 8001040: d001 beq.n 8001046 Error_Handler(); 8001042: f000 fef9 bl 8001e38 } } // Config filter CAN_FilterTypeDef can_filter; can_filter.FilterActivation = CAN_FILTER_ENABLE; 8001046: 2301 movs r3, #1 8001048: 62bb str r3, [r7, #40] ; 0x28 can_filter.FilterBank = 0; 800104a: 2300 movs r3, #0 800104c: 61fb str r3, [r7, #28] can_filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; 800104e: 2300 movs r3, #0 8001050: 61bb str r3, [r7, #24] /* Message ID is in the MSBs of the FilterId register */ can_filter.FilterIdHigh = CAN_ID_CLOCK_SYNC << (16 - 11); 8001052: 2340 movs r3, #64 ; 0x40 8001054: 60bb str r3, [r7, #8] can_filter.FilterIdLow = 0; 8001056: 2300 movs r3, #0 8001058: 60fb str r3, [r7, #12] /* Filter the 11 MSBs (i.e. a StdId) */ if(BMS_IN_TEST_MODE == 1){ can_filter.FilterMaskIdHigh = BMS_TEST_ID; // alleNachrichtenIds werden akzeptiert 800105a: 2300 movs r3, #0 800105c: 613b str r3, [r7, #16] }else{ can_filter.FilterMaskIdHigh = 0xFFE0; } can_filter.FilterMaskIdLow = 0; 800105e: 2300 movs r3, #0 8001060: 617b str r3, [r7, #20] can_filter.FilterMode = CAN_FILTERMODE_IDMASK; 8001062: 2300 movs r3, #0 8001064: 623b str r3, [r7, #32] can_filter.FilterScale = CAN_FILTERSCALE_32BIT; 8001066: 2301 movs r3, #1 8001068: 627b str r3, [r7, #36] ; 0x24 can_filter.SlaveStartFilterBank = 0; 800106a: 2300 movs r3, #0 800106c: 62fb str r3, [r7, #44] ; 0x2c if (HAL_CAN_ConfigFilter(ams_can_handle, &can_filter) != HAL_OK) { 800106e: 4b18 ldr r3, [pc, #96] ; (80010d0 ) 8001070: 681b ldr r3, [r3, #0] 8001072: f107 0208 add.w r2, r7, #8 8001076: 4611 mov r1, r2 8001078: 4618 mov r0, r3 800107a: f001 fa1e bl 80024ba 800107e: 4603 mov r3, r0 8001080: 2b00 cmp r3, #0 8001082: d001 beq.n 8001088 Error_Handler(); 8001084: f000 fed8 bl 8001e38 } can_filter.FilterBank++; 8001088: 69fb ldr r3, [r7, #28] 800108a: 3301 adds r3, #1 800108c: 61fb str r3, [r7, #28] can_filter.FilterIdHigh = CAN_ID_MASTER_HEARTBEAT << (16 - 11); 800108e: f44f 7300 mov.w r3, #512 ; 0x200 8001092: 60bb str r3, [r7, #8] can_filter.FilterIdLow = 0; 8001094: 2300 movs r3, #0 8001096: 60fb str r3, [r7, #12] if (HAL_CAN_ConfigFilter(ams_can_handle, &can_filter) != HAL_OK) { 8001098: 4b0d ldr r3, [pc, #52] ; (80010d0 ) 800109a: 681b ldr r3, [r3, #0] 800109c: f107 0208 add.w r2, r7, #8 80010a0: 4611 mov r1, r2 80010a2: 4618 mov r0, r3 80010a4: f001 fa09 bl 80024ba 80010a8: 4603 mov r3, r0 80010aa: 2b00 cmp r3, #0 80010ac: d001 beq.n 80010b2 Error_Handler(); 80010ae: f000 fec3 bl 8001e38 } // Activate RX notifications if (HAL_CAN_ActivateNotification(ams_can_handle, 80010b2: 4b07 ldr r3, [pc, #28] ; (80010d0 ) 80010b4: 681b ldr r3, [r3, #0] 80010b6: 2102 movs r1, #2 80010b8: 4618 mov r0, r3 80010ba: f001 fd2e bl 8002b1a 80010be: 4603 mov r3, r0 80010c0: 2b00 cmp r3, #0 80010c2: d001 beq.n 80010c8 CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { Error_Handler(); 80010c4: f000 feb8 bl 8001e38 } } 80010c8: bf00 nop 80010ca: 3730 adds r7, #48 ; 0x30 80010cc: 46bd mov sp, r7 80010ce: bd80 pop {r7, pc} 80010d0: 2000004c .word 0x2000004c 080010d4 : static int cb_triggered = 0; void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef* handle) { 80010d4: b580 push {r7, lr} 80010d6: b082 sub sp, #8 80010d8: af00 add r7, sp, #0 80010da: 6078 str r0, [r7, #4] static CAN_RxHeaderTypeDef header; static uint8_t data[8]; cb_triggered = 1; 80010dc: 4b0e ldr r3, [pc, #56] ; (8001118 ) 80010de: 2201 movs r2, #1 80010e0: 601a str r2, [r3, #0] if (HAL_CAN_GetRxMessage(handle, CAN_RX_FIFO0, &header, data) != HAL_OK) { 80010e2: 4b0e ldr r3, [pc, #56] ; (800111c ) 80010e4: 4a0e ldr r2, [pc, #56] ; (8001120 ) 80010e6: 2100 movs r1, #0 80010e8: 6878 ldr r0, [r7, #4] 80010ea: f001 fc04 bl 80028f6 80010ee: 4603 mov r3, r0 80010f0: 2b00 cmp r3, #0 80010f2: d001 beq.n 80010f8 Error_Handler(); 80010f4: f000 fea0 bl 8001e38 } if (handle == ams_can_handle) { 80010f8: 4b0a ldr r3, [pc, #40] ; (8001124 ) 80010fa: 681b ldr r3, [r3, #0] 80010fc: 687a ldr r2, [r7, #4] 80010fe: 429a cmp r2, r3 8001100: d104 bne.n 800110c ams_can_handle_ams_msg(&header, data); 8001102: 4906 ldr r1, [pc, #24] ; (800111c ) 8001104: 4806 ldr r0, [pc, #24] ; (8001120 ) 8001106: f000 f80f bl 8001128 } else { Error_Handler(); } } 800110a: e001 b.n 8001110 Error_Handler(); 800110c: f000 fe94 bl 8001e38 } 8001110: bf00 nop 8001112: 3708 adds r7, #8 8001114: 46bd mov sp, r7 8001116: bd80 pop {r7, pc} 8001118: 20000050 .word 0x20000050 800111c: 20000070 .word 0x20000070 8001120: 20000054 .word 0x20000054 8001124: 2000004c .word 0x2000004c 08001128 : void ams_can_handle_ams_msg(CAN_RxHeaderTypeDef* header, uint8_t* data) { 8001128: b480 push {r7} 800112a: b085 sub sp, #20 800112c: af00 add r7, sp, #0 800112e: 6078 str r0, [r7, #4] 8001130: 6039 str r1, [r7, #0] if(BMS_IN_TEST_MODE == 1){ PENDING_MESSAGE_HANDLE = 1; 8001132: 4b0e ldr r3, [pc, #56] ; (800116c ) 8001134: 2201 movs r2, #1 8001136: 601a str r2, [r3, #0] for(int i = 0; i < 8; i++){ 8001138: 2300 movs r3, #0 800113a: 60fb str r3, [r7, #12] 800113c: e00b b.n 8001156 canTestData[i] = data[i]; 800113e: 68fb ldr r3, [r7, #12] 8001140: 683a ldr r2, [r7, #0] 8001142: 4413 add r3, r2 8001144: 7819 ldrb r1, [r3, #0] 8001146: 4a0a ldr r2, [pc, #40] ; (8001170 ) 8001148: 68fb ldr r3, [r7, #12] 800114a: 4413 add r3, r2 800114c: 460a mov r2, r1 800114e: 701a strb r2, [r3, #0] for(int i = 0; i < 8; i++){ 8001150: 68fb ldr r3, [r7, #12] 8001152: 3301 adds r3, #1 8001154: 60fb str r3, [r7, #12] 8001156: 68fb ldr r3, [r7, #12] 8001158: 2b07 cmp r3, #7 800115a: ddf0 ble.n 800113e } return; 800115c: bf00 nop 800115e: bf00 nop break; case CAN_ID_MASTER_HEARTBEAT: // clock_sync_handle_master_heartbeat(); break; } } 8001160: 3714 adds r7, #20 8001162: 46bd mov sp, r7 8001164: f85d 7b04 ldr.w r7, [sp], #4 8001168: 4770 bx lr 800116a: bf00 nop 800116c: 20000040 .word 0x20000040 8001170: 20000044 .word 0x20000044 08001174 : void ams_can_send_heartbeat() { 8001174: b580 push {r7, lr} 8001176: b086 sub sp, #24 8001178: af00 add r7, sp, #0 static CAN_TxHeaderTypeDef header; static uint8_t data[8]; header.IDE = CAN_ID_STD; 800117a: 4b2c ldr r3, [pc, #176] ; (800122c ) 800117c: 2200 movs r2, #0 800117e: 609a str r2, [r3, #8] header.DLC = 8; 8001180: 4b2a ldr r3, [pc, #168] ; (800122c ) 8001182: 2208 movs r2, #8 8001184: 611a str r2, [r3, #16] header.RTR = CAN_RTR_DATA; 8001186: 4b29 ldr r3, [pc, #164] ; (800122c ) 8001188: 2200 movs r2, #0 800118a: 60da str r2, [r3, #12] header.TransmitGlobalTime = DISABLE; 800118c: 4b27 ldr r3, [pc, #156] ; (800122c ) 800118e: 2200 movs r2, #0 8001190: 751a strb r2, [r3, #20] // Send voltages for (int msg_id = 0; msg_id < 5; msg_id++) { 8001192: 2300 movs r3, #0 8001194: 617b str r3, [r7, #20] 8001196: e040 b.n 800121a header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new format 8001198: 697b ldr r3, [r7, #20] 800119a: f443 63c0 orr.w r3, r3, #1536 ; 0x600 800119e: 461a mov r2, r3 80011a0: 4b22 ldr r3, [pc, #136] ; (800122c ) 80011a2: 601a str r2, [r3, #0] for (int i = 0; i < 4; i++) { 80011a4: 2300 movs r3, #0 80011a6: 613b str r3, [r7, #16] 80011a8: e020 b.n 80011ec int cell = msg_id * 4 + i; 80011aa: 697b ldr r3, [r7, #20] 80011ac: 009b lsls r3, r3, #2 80011ae: 693a ldr r2, [r7, #16] 80011b0: 4413 add r3, r2 80011b2: 60fb str r3, [r7, #12] uint16_t v = (cell < N_CELLS) ? module.cellVoltages[cell] : 0; 80011b4: 68fb ldr r3, [r7, #12] 80011b6: 2b10 cmp r3, #16 80011b8: dc04 bgt.n 80011c4 80011ba: 4a1d ldr r2, [pc, #116] ; (8001230 ) 80011bc: 68fb ldr r3, [r7, #12] 80011be: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80011c2: e000 b.n 80011c6 80011c4: 2300 movs r3, #0 80011c6: 817b strh r3, [r7, #10] data[2 * i + 0] = v & 0xFF; 80011c8: 693b ldr r3, [r7, #16] 80011ca: 005b lsls r3, r3, #1 80011cc: 897a ldrh r2, [r7, #10] 80011ce: b2d1 uxtb r1, r2 80011d0: 4a18 ldr r2, [pc, #96] ; (8001234 ) 80011d2: 54d1 strb r1, [r2, r3] data[2 * i + 1] = v >> 8; 80011d4: 897b ldrh r3, [r7, #10] 80011d6: 0a1b lsrs r3, r3, #8 80011d8: b29a uxth r2, r3 80011da: 693b ldr r3, [r7, #16] 80011dc: 005b lsls r3, r3, #1 80011de: 3301 adds r3, #1 80011e0: b2d1 uxtb r1, r2 80011e2: 4a14 ldr r2, [pc, #80] ; (8001234 ) 80011e4: 54d1 strb r1, [r2, r3] for (int i = 0; i < 4; i++) { 80011e6: 693b ldr r3, [r7, #16] 80011e8: 3301 adds r3, #1 80011ea: 613b str r3, [r7, #16] 80011ec: 693b ldr r3, [r7, #16] 80011ee: 2b03 cmp r3, #3 80011f0: dddb ble.n 80011aa } if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, 80011f2: 4b11 ldr r3, [pc, #68] ; (8001238 ) 80011f4: 681b ldr r3, [r3, #0] 80011f6: 220a movs r2, #10 80011f8: 2101 movs r1, #1 80011fa: 4618 mov r0, r3 80011fc: f000 f81e bl 800123c 8001200: 4603 mov r3, r0 8001202: 2b00 cmp r3, #0 8001204: d106 bne.n 8001214 CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { uint32_t mailbox; HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); 8001206: 4b0c ldr r3, [pc, #48] ; (8001238 ) 8001208: 6818 ldr r0, [r3, #0] 800120a: 1d3b adds r3, r7, #4 800120c: 4a09 ldr r2, [pc, #36] ; (8001234 ) 800120e: 4907 ldr r1, [pc, #28] ; (800122c ) 8001210: f001 fa61 bl 80026d6 for (int msg_id = 0; msg_id < 5; msg_id++) { 8001214: 697b ldr r3, [r7, #20] 8001216: 3301 adds r3, #1 8001218: 617b str r3, [r7, #20] 800121a: 697b ldr r3, [r7, #20] 800121c: 2b04 cmp r3, #4 800121e: ddbb ble.n 8001198 CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { uint32_t mailbox; HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); } }*/ } 8001220: bf00 nop 8001222: bf00 nop 8001224: 3718 adds r7, #24 8001226: 46bd mov sp, r7 8001228: bd80 pop {r7, pc} 800122a: bf00 nop 800122c: 20000078 .word 0x20000078 8001230: 20000098 .word 0x20000098 8001234: 20000090 .word 0x20000090 8001238: 2000004c .word 0x2000004c 0800123c : ams_can_wait_for_free_mailboxes(ams_can_handle, 3, transmission_timeout); }*/ HAL_StatusTypeDef ams_can_wait_for_free_mailboxes(CAN_HandleTypeDef* handle, int num_mailboxes, uint32_t timeout) { 800123c: b580 push {r7, lr} 800123e: b086 sub sp, #24 8001240: af00 add r7, sp, #0 8001242: 60f8 str r0, [r7, #12] 8001244: 60b9 str r1, [r7, #8] 8001246: 607a str r2, [r7, #4] uint32_t end = HAL_GetTick() + timeout; 8001248: f001 f80c bl 8002264 800124c: 4602 mov r2, r0 800124e: 687b ldr r3, [r7, #4] 8001250: 4413 add r3, r2 8001252: 617b str r3, [r7, #20] while (HAL_GetTick() < end) { 8001254: e008 b.n 8001268 if (HAL_CAN_GetTxMailboxesFreeLevel(handle) >= num_mailboxes) { 8001256: 68f8 ldr r0, [r7, #12] 8001258: f001 fb18 bl 800288c 800125c: 4602 mov r2, r0 800125e: 68bb ldr r3, [r7, #8] 8001260: 429a cmp r2, r3 8001262: d301 bcc.n 8001268 return HAL_OK; 8001264: 2300 movs r3, #0 8001266: e006 b.n 8001276 while (HAL_GetTick() < end) { 8001268: f000 fffc bl 8002264 800126c: 4602 mov r2, r0 800126e: 697b ldr r3, [r7, #20] 8001270: 4293 cmp r3, r2 8001272: d8f0 bhi.n 8001256 } } return HAL_TIMEOUT; 8001274: 2303 movs r3, #3 } 8001276: 4618 mov r0, r3 8001278: 3718 adds r7, #24 800127a: 46bd mov sp, r7 800127c: bd80 pop {r7, pc} ... 08001280 : amsState currentAMSState = AMSDEACTIVE; amsState lastAMSState = AMSDEACTIVE; void AMS_Init(SPI_HandleTypeDef *hspi) { 8001280: b580 push {r7, lr} 8001282: b082 sub sp, #8 8001284: af00 add r7, sp, #0 8001286: 6078 str r0, [r7, #4] if(eepromconfigured == 1) 8001288: 4b12 ldr r3, [pc, #72] ; (80012d4 ) 800128a: 781b ldrb r3, [r3, #0] 800128c: 2b01 cmp r3, #1 800128e: d10a bne.n 80012a6 /*amsov = eepromcellovervoltage>>4; amsuv = (eepromcellundervoltage-1)>>4; numberofCells = eepromnumofcells; numberofAux = eepromnumofaux; initAMS(hspi, eepromnumofcells, eepromnumofaux);*/ amsConfigOverVoltage(amsov); 8001290: 4b11 ldr r3, [pc, #68] ; (80012d8 ) 8001292: 881b ldrh r3, [r3, #0] 8001294: 4618 mov r0, r3 8001296: f7ff fa1e bl 80006d6 amsConfigUnderVoltage(amsuv); 800129a: 4b10 ldr r3, [pc, #64] ; (80012dc ) 800129c: 881b ldrh r3, [r3, #0] 800129e: 4618 mov r0, r3 80012a0: f7ff f95e bl 8000560 80012a4: e00f b.n 80012c6 } else { initAMS(hspi, numberofCells, numberofAux); 80012a6: 4b0e ldr r3, [pc, #56] ; (80012e0 ) 80012a8: 781b ldrb r3, [r3, #0] 80012aa: 4a0e ldr r2, [pc, #56] ; (80012e4 ) 80012ac: 7812 ldrb r2, [r2, #0] 80012ae: 4619 mov r1, r3 80012b0: 6878 ldr r0, [r7, #4] 80012b2: f7fe ff89 bl 80001c8 amsov = DEFAULT_OV; 80012b6: 4b08 ldr r3, [pc, #32] ; (80012d8 ) 80012b8: f640 2241 movw r2, #2625 ; 0xa41 80012bc: 801a strh r2, [r3, #0] amsuv = DEFAULT_UV; 80012be: 4b07 ldr r3, [pc, #28] ; (80012dc ) 80012c0: f240 621a movw r2, #1562 ; 0x61a 80012c4: 801a strh r2, [r3, #0] } currentAMSState = AMSIDLE; 80012c6: 4b08 ldr r3, [pc, #32] ; (80012e8 ) 80012c8: 2201 movs r2, #1 80012ca: 701a strb r2, [r3, #0] } 80012cc: bf00 nop 80012ce: 3708 adds r7, #8 80012d0: 46bd mov sp, r7 80012d2: bd80 pop {r7, pc} 80012d4: 20000108 .word 0x20000108 80012d8: 2000010c .word 0x2000010c 80012dc: 2000010a .word 0x2000010a 80012e0: 20000000 .word 0x20000000 80012e4: 2000010f .word 0x2000010f 80012e8: 20000110 .word 0x20000110 080012ec : void AMS_Loop() { 80012ec: b580 push {r7, lr} 80012ee: af00 add r7, sp, #0 //On Transition Functions called ones if the State Changed if(currentAMSState != lastAMSState) 80012f0: 4b25 ldr r3, [pc, #148] ; (8001388 ) 80012f2: 781a ldrb r2, [r3, #0] 80012f4: 4b25 ldr r3, [pc, #148] ; (800138c ) 80012f6: 781b ldrb r3, [r3, #0] 80012f8: 429a cmp r2, r3 80012fa: d023 beq.n 8001344 { switch(currentAMSState) 80012fc: 4b22 ldr r3, [pc, #136] ; (8001388 ) 80012fe: 781b ldrb r3, [r3, #0] 8001300: 2b06 cmp r3, #6 8001302: d81b bhi.n 800133c 8001304: a201 add r2, pc, #4 ; (adr r2, 800130c ) 8001306: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800130a: bf00 nop 800130c: 0800133d .word 0x0800133d 8001310: 0800133d .word 0x0800133d 8001314: 0800133d .word 0x0800133d 8001318: 0800133d .word 0x0800133d 800131c: 0800133d .word 0x0800133d 8001320: 08001329 .word 0x08001329 8001324: 08001331 .word 0x08001331 case AMSIDLEBALANCING: break; case AMSDISCHARGING: break; case AMSWARNING: writeWarningLog(0x01); 8001328: 2001 movs r0, #1 800132a: f000 f8a7 bl 800147c break; 800132e: e005 b.n 800133c case AMSERROR: writeErrorLog(amserrorcode); 8001330: 4b17 ldr r3, [pc, #92] ; (8001390 ) 8001332: 781b ldrb r3, [r3, #0] 8001334: 4618 mov r0, r3 8001336: f000 f8ad bl 8001494 break; 800133a: bf00 nop } lastAMSState = currentAMSState; 800133c: 4b12 ldr r3, [pc, #72] ; (8001388 ) 800133e: 781a ldrb r2, [r3, #0] 8001340: 4b12 ldr r3, [pc, #72] ; (800138c ) 8001342: 701a strb r2, [r3, #0] } //Main Loops for different AMS States switch(currentAMSState) 8001344: 4b10 ldr r3, [pc, #64] ; (8001388 ) 8001346: 781b ldrb r3, [r3, #0] 8001348: 2b06 cmp r3, #6 800134a: d81b bhi.n 8001384 800134c: a201 add r2, pc, #4 ; (adr r2, 8001354 ) 800134e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001352: bf00 nop 8001354: 08001383 .word 0x08001383 8001358: 08001371 .word 0x08001371 800135c: 08001383 .word 0x08001383 8001360: 08001377 .word 0x08001377 8001364: 08001383 .word 0x08001383 8001368: 0800137d .word 0x0800137d 800136c: 08001383 .word 0x08001383 { case AMSIDLE: AMS_Idle_Loop(); 8001370: f000 f810 bl 8001394 break; 8001374: e006 b.n 8001384 case AMSDEACTIVE: break; case AMSCHARGING: break; case AMSIDLEBALANCING: AMS_Idle_Loop(); 8001376: f000 f80d bl 8001394 break; 800137a: e003 b.n 8001384 case AMSDISCHARGING: break; case AMSWARNING: AMS_Warning_Loop(); 800137c: f000 f844 bl 8001408 break; 8001380: e000 b.n 8001384 break; 8001382: bf00 nop case AMSERROR: break; } } 8001384: bf00 nop 8001386: bd80 pop {r7, pc} 8001388: 20000110 .word 0x20000110 800138c: 20000111 .word 0x20000111 8001390: 2000010e .word 0x2000010e 08001394 : uint8_t AMS_Idle_Loop() { 8001394: b580 push {r7, lr} 8001396: af00 add r7, sp, #0 amsWakeUp(); 8001398: f7fe ff40 bl 800021c amsConfigOverVoltage(amsov); 800139c: 4b15 ldr r3, [pc, #84] ; (80013f4 ) 800139e: 881b ldrh r3, [r3, #0] 80013a0: 4618 mov r0, r3 80013a2: f7ff f998 bl 80006d6 amsConfigUnderVoltage(amsuv); 80013a6: 4b14 ldr r3, [pc, #80] ; (80013f8 ) 80013a8: 881b ldrh r3, [r3, #0] 80013aa: 4618 mov r0, r3 80013ac: f7ff f8d8 bl 8000560 amsConfigAuxMeasurement(0xFFFF); 80013b0: f64f 70ff movw r0, #65535 ; 0xffff 80013b4: f7ff f836 bl 8000424 amsClearAux(); 80013b8: f7ff f9b9 bl 800072e amsCellMeasurement(&module); 80013bc: 480f ldr r0, [pc, #60] ; (80013fc ) 80013be: f7fe ff3b bl 8000238 amsInternalStatusMeasurement(&module); 80013c2: 480e ldr r0, [pc, #56] ; (80013fc ) 80013c4: f7fe ffe4 bl 8000390 amsAuxMeasurement(&module); 80013c8: 480c ldr r0, [pc, #48] ; (80013fc ) 80013ca: f7fe ff4c bl 8000266 amsCheckUnderOverVoltage(&module); 80013ce: 480b ldr r0, [pc, #44] ; (80013fc ) 80013d0: f7ff f8f3 bl 80005ba integrateCurrent(); 80013d4: f000 f86a bl 80014ac static uint32_t channelstobalance = 1; channelstobalance = 0x1FFFF; 80013d8: 4b09 ldr r3, [pc, #36] ; (8001400 ) 80013da: 4a0a ldr r2, [pc, #40] ; (8001404 ) 80013dc: 601a str r2, [r3, #0] /* if(channelstobalance & 0x20000){ channelstobalance = 1; }*/ amsConfigBalancing(channelstobalance); 80013de: 4b08 ldr r3, [pc, #32] ; (8001400 ) 80013e0: 681b ldr r3, [r3, #0] 80013e2: 4618 mov r0, r3 80013e4: f7ff f84e bl 8000484 amsStartBalancing(100); 80013e8: 2064 movs r0, #100 ; 0x64 80013ea: f7ff f8a0 bl 800052e { amsStopBalancing(); }*/ //amsConfigBalancing(balancedCells); //volatile amscheck = amscheckOpenCellWire(&module); return 0; 80013ee: 2300 movs r3, #0 } 80013f0: 4618 mov r0, r3 80013f2: bd80 pop {r7, pc} 80013f4: 2000010c .word 0x2000010c 80013f8: 2000010a .word 0x2000010a 80013fc: 20000098 .word 0x20000098 8001400: 20000004 .word 0x20000004 8001404: 0001ffff .word 0x0001ffff 08001408 : uint8_t AMS_Warning_Loop() { 8001408: b580 push {r7, lr} 800140a: af00 add r7, sp, #0 amsWakeUp(); 800140c: f7fe ff06 bl 800021c amsConfigOverVoltage(amsov); 8001410: 4b16 ldr r3, [pc, #88] ; (800146c ) 8001412: 881b ldrh r3, [r3, #0] 8001414: 4618 mov r0, r3 8001416: f7ff f95e bl 80006d6 amsConfigUnderVoltage(amsuv); 800141a: 4b15 ldr r3, [pc, #84] ; (8001470 ) 800141c: 881b ldrh r3, [r3, #0] 800141e: 4618 mov r0, r3 8001420: f7ff f89e bl 8000560 amsConfigAuxMeasurement(0xFFFF); 8001424: f64f 70ff movw r0, #65535 ; 0xffff 8001428: f7fe fffc bl 8000424 amsClearAux(); 800142c: f7ff f97f bl 800072e amsCellMeasurement(&module); 8001430: 4810 ldr r0, [pc, #64] ; (8001474 ) 8001432: f7fe ff01 bl 8000238 amsInternalStatusMeasurement(&module); 8001436: 480f ldr r0, [pc, #60] ; (8001474 ) 8001438: f7fe ffaa bl 8000390 amsAuxMeasurement(&module); 800143c: 480d ldr r0, [pc, #52] ; (8001474 ) 800143e: f7fe ff12 bl 8000266 amsCheckUnderOverVoltage(&module); 8001442: 480c ldr r0, [pc, #48] ; (8001474 ) 8001444: f7ff f8b9 bl 80005ba if(!(module.overVoltage | module.underVoltage)) 8001448: 4b0a ldr r3, [pc, #40] ; (8001474 ) 800144a: 6d9a ldr r2, [r3, #88] ; 0x58 800144c: 4b09 ldr r3, [pc, #36] ; (8001474 ) 800144e: 6ddb ldr r3, [r3, #92] ; 0x5c 8001450: 4313 orrs r3, r2 8001452: 2b00 cmp r3, #0 8001454: d104 bne.n 8001460 { currentAMSState = AMSIDLE; 8001456: 4b08 ldr r3, [pc, #32] ; (8001478 ) 8001458: 2201 movs r2, #1 800145a: 701a strb r2, [r3, #0] amsClearWarning(); 800145c: f7ff f976 bl 800074c } amsStopBalancing(); 8001460: f7ff f874 bl 800054c return 0; 8001464: 2300 movs r3, #0 } 8001466: 4618 mov r0, r3 8001468: bd80 pop {r7, pc} 800146a: bf00 nop 800146c: 2000010c .word 0x2000010c 8001470: 2000010a .word 0x2000010a 8001474: 20000098 .word 0x20000098 8001478: 20000110 .word 0x20000110 0800147c : } return balancingdone; } uint8_t writeWarningLog(uint8_t warningCode) { 800147c: b480 push {r7} 800147e: b083 sub sp, #12 8001480: af00 add r7, sp, #0 8001482: 4603 mov r3, r0 8001484: 71fb strb r3, [r7, #7] //eepromWriteWarningLog(warningCode); return 0; 8001486: 2300 movs r3, #0 } 8001488: 4618 mov r0, r3 800148a: 370c adds r7, #12 800148c: 46bd mov sp, r7 800148e: f85d 7b04 ldr.w r7, [sp], #4 8001492: 4770 bx lr 08001494 : uint8_t writeErrorLog(uint8_t errorCode) { 8001494: b480 push {r7} 8001496: b083 sub sp, #12 8001498: af00 add r7, sp, #0 800149a: 4603 mov r3, r0 800149c: 71fb strb r3, [r7, #7] //eepromWriteErrorLog(errorCode); return 0; 800149e: 2300 movs r3, #0 } 80014a0: 4618 mov r0, r3 80014a2: 370c adds r7, #12 80014a4: 46bd mov sp, r7 80014a6: f85d 7b04 ldr.w r7, [sp], #4 80014aa: 4770 bx lr 080014ac : uint8_t integrateCurrent() { 80014ac: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 80014b0: af00 add r7, sp, #0 lastticks = currenttick; 80014b2: 4b17 ldr r3, [pc, #92] ; (8001510 ) 80014b4: 681b ldr r3, [r3, #0] 80014b6: 4a17 ldr r2, [pc, #92] ; (8001514 ) 80014b8: 6013 str r3, [r2, #0] currenttick = HAL_GetTick(); 80014ba: f000 fed3 bl 8002264 80014be: 4603 mov r3, r0 80014c0: 4a13 ldr r2, [pc, #76] ; (8001510 ) 80014c2: 6013 str r3, [r2, #0] if(currenttick < lastticks) 80014c4: 4b12 ldr r3, [pc, #72] ; (8001510 ) 80014c6: 681a ldr r2, [r3, #0] 80014c8: 4b12 ldr r3, [pc, #72] ; (8001514 ) 80014ca: 681b ldr r3, [r3, #0] 80014cc: 429a cmp r2, r3 80014ce: d21a bcs.n 8001506 { currentintegrator += (module.auxVoltages[0] - module.auxVoltages[2])*(currenttick-lastticks); 80014d0: 4b11 ldr r3, [pc, #68] ; (8001518 ) 80014d2: 8c9b ldrh r3, [r3, #36] ; 0x24 80014d4: 461a mov r2, r3 80014d6: 4b10 ldr r3, [pc, #64] ; (8001518 ) 80014d8: 8d1b ldrh r3, [r3, #40] ; 0x28 80014da: 1ad3 subs r3, r2, r3 80014dc: 4619 mov r1, r3 80014de: 4b0c ldr r3, [pc, #48] ; (8001510 ) 80014e0: 681a ldr r2, [r3, #0] 80014e2: 4b0c ldr r3, [pc, #48] ; (8001514 ) 80014e4: 681b ldr r3, [r3, #0] 80014e6: 1ad3 subs r3, r2, r3 80014e8: fb01 f303 mul.w r3, r1, r3 80014ec: 2200 movs r2, #0 80014ee: 461c mov r4, r3 80014f0: 4615 mov r5, r2 80014f2: 4b0a ldr r3, [pc, #40] ; (800151c ) 80014f4: e9d3 2300 ldrd r2, r3, [r3] 80014f8: eb14 0802 adds.w r8, r4, r2 80014fc: eb45 0903 adc.w r9, r5, r3 8001500: 4b06 ldr r3, [pc, #24] ; (800151c ) 8001502: e9c3 8900 strd r8, r9, [r3] } return 0; 8001506: 2300 movs r3, #0 } 8001508: 4618 mov r0, r3 800150a: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800150e: bf00 nop 8001510: 20000104 .word 0x20000104 8001514: 20000100 .word 0x20000100 8001518: 20000098 .word 0x20000098 800151c: 200000f8 .word 0x200000f8 08001520 : #include #include "ADBMS_Abstraction.h" #include "main.h" void canTestSendTemperatures(uint16_t* data){ 8001520: b580 push {r7, lr} 8001522: b092 sub sp, #72 ; 0x48 8001524: af00 add r7, sp, #0 8001526: 6078 str r0, [r7, #4] static CAN_TxHeaderTypeDef header; header.IDE = CAN_ID_STD; 8001528: 4b59 ldr r3, [pc, #356] ; (8001690 ) 800152a: 2200 movs r2, #0 800152c: 609a str r2, [r3, #8] header.DLC = 8; 800152e: 4b58 ldr r3, [pc, #352] ; (8001690 ) 8001530: 2208 movs r2, #8 8001532: 611a str r2, [r3, #16] header.RTR = CAN_RTR_DATA; 8001534: 4b56 ldr r3, [pc, #344] ; (8001690 ) 8001536: 2200 movs r2, #0 8001538: 60da str r2, [r3, #12] header.TransmitGlobalTime = DISABLE; 800153a: 4b55 ldr r3, [pc, #340] ; (8001690 ) 800153c: 2200 movs r2, #0 800153e: 751a strb r2, [r3, #20] uint8_t buffer[24]; uint8_t tmp[8]; for(int i = 0; i < 12; i++){ 8001540: 2300 movs r3, #0 8001542: 647b str r3, [r7, #68] ; 0x44 8001544: e01d b.n 8001582 buffer[((i*2)+1)] = data[i] >> 8; 8001546: 6c7b ldr r3, [r7, #68] ; 0x44 8001548: 005b lsls r3, r3, #1 800154a: 687a ldr r2, [r7, #4] 800154c: 4413 add r3, r2 800154e: 881b ldrh r3, [r3, #0] 8001550: 0a1b lsrs r3, r3, #8 8001552: b29a uxth r2, r3 8001554: 6c7b ldr r3, [r7, #68] ; 0x44 8001556: 005b lsls r3, r3, #1 8001558: 3301 adds r3, #1 800155a: b2d2 uxtb r2, r2 800155c: 3348 adds r3, #72 ; 0x48 800155e: 443b add r3, r7 8001560: f803 2c2c strb.w r2, [r3, #-44] buffer[(i*2)] = data[i]; 8001564: 6c7b ldr r3, [r7, #68] ; 0x44 8001566: 005b lsls r3, r3, #1 8001568: 687a ldr r2, [r7, #4] 800156a: 4413 add r3, r2 800156c: 881a ldrh r2, [r3, #0] 800156e: 6c7b ldr r3, [r7, #68] ; 0x44 8001570: 005b lsls r3, r3, #1 8001572: b2d2 uxtb r2, r2 8001574: 3348 adds r3, #72 ; 0x48 8001576: 443b add r3, r7 8001578: f803 2c2c strb.w r2, [r3, #-44] for(int i = 0; i < 12; i++){ 800157c: 6c7b ldr r3, [r7, #68] ; 0x44 800157e: 3301 adds r3, #1 8001580: 647b str r3, [r7, #68] ; 0x44 8001582: 6c7b ldr r3, [r7, #68] ; 0x44 8001584: 2b0b cmp r3, #11 8001586: ddde ble.n 8001546 } for(int i = 0; i < 8; i++){ 8001588: 2300 movs r3, #0 800158a: 643b str r3, [r7, #64] ; 0x40 800158c: e00d b.n 80015aa tmp[i] = buffer[i]; 800158e: f107 021c add.w r2, r7, #28 8001592: 6c3b ldr r3, [r7, #64] ; 0x40 8001594: 4413 add r3, r2 8001596: 7819 ldrb r1, [r3, #0] 8001598: f107 0214 add.w r2, r7, #20 800159c: 6c3b ldr r3, [r7, #64] ; 0x40 800159e: 4413 add r3, r2 80015a0: 460a mov r2, r1 80015a2: 701a strb r2, [r3, #0] for(int i = 0; i < 8; i++){ 80015a4: 6c3b ldr r3, [r7, #64] ; 0x40 80015a6: 3301 adds r3, #1 80015a8: 643b str r3, [r7, #64] ; 0x40 80015aa: 6c3b ldr r3, [r7, #64] ; 0x40 80015ac: 2b07 cmp r3, #7 80015ae: ddee ble.n 800158e } if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { 80015b0: 4b38 ldr r3, [pc, #224] ; (8001694 ) 80015b2: 681b ldr r3, [r3, #0] 80015b4: 220a movs r2, #10 80015b6: 2101 movs r1, #1 80015b8: 4618 mov r0, r3 80015ba: f7ff fe3f bl 800123c 80015be: 4603 mov r3, r0 80015c0: 2b00 cmp r3, #0 80015c2: d108 bne.n 80015d6 uint32_t mailbox; HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); 80015c4: 4b33 ldr r3, [pc, #204] ; (8001694 ) 80015c6: 6818 ldr r0, [r3, #0] 80015c8: f107 0310 add.w r3, r7, #16 80015cc: f107 0214 add.w r2, r7, #20 80015d0: 492f ldr r1, [pc, #188] ; (8001690 ) 80015d2: f001 f880 bl 80026d6 } int m = 0; 80015d6: 2300 movs r3, #0 80015d8: 63fb str r3, [r7, #60] ; 0x3c for(int i = 8; i < 16; i++){ 80015da: 2308 movs r3, #8 80015dc: 63bb str r3, [r7, #56] ; 0x38 80015de: e010 b.n 8001602 tmp[m] = buffer[i]; 80015e0: f107 021c add.w r2, r7, #28 80015e4: 6bbb ldr r3, [r7, #56] ; 0x38 80015e6: 4413 add r3, r2 80015e8: 7819 ldrb r1, [r3, #0] 80015ea: f107 0214 add.w r2, r7, #20 80015ee: 6bfb ldr r3, [r7, #60] ; 0x3c 80015f0: 4413 add r3, r2 80015f2: 460a mov r2, r1 80015f4: 701a strb r2, [r3, #0] m++; 80015f6: 6bfb ldr r3, [r7, #60] ; 0x3c 80015f8: 3301 adds r3, #1 80015fa: 63fb str r3, [r7, #60] ; 0x3c for(int i = 8; i < 16; i++){ 80015fc: 6bbb ldr r3, [r7, #56] ; 0x38 80015fe: 3301 adds r3, #1 8001600: 63bb str r3, [r7, #56] ; 0x38 8001602: 6bbb ldr r3, [r7, #56] ; 0x38 8001604: 2b0f cmp r3, #15 8001606: ddeb ble.n 80015e0 } if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { 8001608: 4b22 ldr r3, [pc, #136] ; (8001694 ) 800160a: 681b ldr r3, [r3, #0] 800160c: 220a movs r2, #10 800160e: 2101 movs r1, #1 8001610: 4618 mov r0, r3 8001612: f7ff fe13 bl 800123c 8001616: 4603 mov r3, r0 8001618: 2b00 cmp r3, #0 800161a: d108 bne.n 800162e uint32_t mailbox; HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); 800161c: 4b1d ldr r3, [pc, #116] ; (8001694 ) 800161e: 6818 ldr r0, [r3, #0] 8001620: f107 030c add.w r3, r7, #12 8001624: f107 0214 add.w r2, r7, #20 8001628: 4919 ldr r1, [pc, #100] ; (8001690 ) 800162a: f001 f854 bl 80026d6 } m = 0; 800162e: 2300 movs r3, #0 8001630: 63fb str r3, [r7, #60] ; 0x3c for(int i = 16; i < 24; i++){ 8001632: 2310 movs r3, #16 8001634: 637b str r3, [r7, #52] ; 0x34 8001636: e010 b.n 800165a tmp[m] = buffer[i]; 8001638: f107 021c add.w r2, r7, #28 800163c: 6b7b ldr r3, [r7, #52] ; 0x34 800163e: 4413 add r3, r2 8001640: 7819 ldrb r1, [r3, #0] 8001642: f107 0214 add.w r2, r7, #20 8001646: 6bfb ldr r3, [r7, #60] ; 0x3c 8001648: 4413 add r3, r2 800164a: 460a mov r2, r1 800164c: 701a strb r2, [r3, #0] m++; 800164e: 6bfb ldr r3, [r7, #60] ; 0x3c 8001650: 3301 adds r3, #1 8001652: 63fb str r3, [r7, #60] ; 0x3c for(int i = 16; i < 24; i++){ 8001654: 6b7b ldr r3, [r7, #52] ; 0x34 8001656: 3301 adds r3, #1 8001658: 637b str r3, [r7, #52] ; 0x34 800165a: 6b7b ldr r3, [r7, #52] ; 0x34 800165c: 2b17 cmp r3, #23 800165e: ddeb ble.n 8001638 } if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { 8001660: 4b0c ldr r3, [pc, #48] ; (8001694 ) 8001662: 681b ldr r3, [r3, #0] 8001664: 220a movs r2, #10 8001666: 2101 movs r1, #1 8001668: 4618 mov r0, r3 800166a: f7ff fde7 bl 800123c 800166e: 4603 mov r3, r0 8001670: 2b00 cmp r3, #0 8001672: d108 bne.n 8001686 uint32_t mailbox; HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); 8001674: 4b07 ldr r3, [pc, #28] ; (8001694 ) 8001676: 6818 ldr r0, [r3, #0] 8001678: f107 0308 add.w r3, r7, #8 800167c: f107 0214 add.w r2, r7, #20 8001680: 4903 ldr r1, [pc, #12] ; (8001690 ) 8001682: f001 f828 bl 80026d6 } } 8001686: bf00 nop 8001688: 3748 adds r7, #72 ; 0x48 800168a: 46bd mov sp, r7 800168c: bd80 pop {r7, pc} 800168e: bf00 nop 8001690: 20000114 .word 0x20000114 8001694: 2000004c .word 0x2000004c 08001698 : void canTestSendAnswer(uint8_t* data){ 8001698: b580 push {r7, lr} 800169a: b084 sub sp, #16 800169c: af00 add r7, sp, #0 800169e: 6078 str r0, [r7, #4] static CAN_TxHeaderTypeDef header; header.IDE = CAN_ID_STD; 80016a0: 4b10 ldr r3, [pc, #64] ; (80016e4 ) 80016a2: 2200 movs r2, #0 80016a4: 609a str r2, [r3, #8] header.DLC = 8; 80016a6: 4b0f ldr r3, [pc, #60] ; (80016e4 ) 80016a8: 2208 movs r2, #8 80016aa: 611a str r2, [r3, #16] header.RTR = CAN_RTR_DATA; 80016ac: 4b0d ldr r3, [pc, #52] ; (80016e4 ) 80016ae: 2200 movs r2, #0 80016b0: 60da str r2, [r3, #12] header.TransmitGlobalTime = DISABLE; 80016b2: 4b0c ldr r3, [pc, #48] ; (80016e4 ) 80016b4: 2200 movs r2, #0 80016b6: 751a strb r2, [r3, #20] if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, 80016b8: 4b0b ldr r3, [pc, #44] ; (80016e8 ) 80016ba: 681b ldr r3, [r3, #0] 80016bc: 220a movs r2, #10 80016be: 2101 movs r1, #1 80016c0: 4618 mov r0, r3 80016c2: f7ff fdbb bl 800123c 80016c6: 4603 mov r3, r0 80016c8: 2b00 cmp r3, #0 80016ca: d107 bne.n 80016dc CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { uint32_t mailbox; HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); 80016cc: 4b06 ldr r3, [pc, #24] ; (80016e8 ) 80016ce: 6818 ldr r0, [r3, #0] 80016d0: f107 030c add.w r3, r7, #12 80016d4: 687a ldr r2, [r7, #4] 80016d6: 4903 ldr r1, [pc, #12] ; (80016e4 ) 80016d8: f000 fffd bl 80026d6 } } 80016dc: bf00 nop 80016de: 3710 adds r7, #16 80016e0: 46bd mov sp, r7 80016e2: bd80 pop {r7, pc} 80016e4: 2000012c .word 0x2000012c 80016e8: 2000004c .word 0x2000004c 080016ec : void resetData(uint8_t* data){ 80016ec: b480 push {r7} 80016ee: b085 sub sp, #20 80016f0: af00 add r7, sp, #0 80016f2: 6078 str r0, [r7, #4] for(int i = 0; i < 8; i++){ 80016f4: 2300 movs r3, #0 80016f6: 60fb str r3, [r7, #12] 80016f8: e005 b.n 8001706 data[0] = 0; 80016fa: 687b ldr r3, [r7, #4] 80016fc: 2200 movs r2, #0 80016fe: 701a strb r2, [r3, #0] for(int i = 0; i < 8; i++){ 8001700: 68fb ldr r3, [r7, #12] 8001702: 3301 adds r3, #1 8001704: 60fb str r3, [r7, #12] 8001706: 68fb ldr r3, [r7, #12] 8001708: 2b07 cmp r3, #7 800170a: ddf6 ble.n 80016fa } } 800170c: bf00 nop 800170e: bf00 nop 8001710: 3714 adds r7, #20 8001712: 46bd mov sp, r7 8001714: f85d 7b04 ldr.w r7, [sp], #4 8001718: 4770 bx lr 0800171a : void readTemperatures(){ 800171a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800171e: b086 sub sp, #24 8001720: af00 add r7, sp, #0 8001722: 466b mov r3, sp 8001724: 4698 mov r8, r3 uint8_t last_error = 0; 8001726: 2300 movs r3, #0 8001728: 74fb strb r3, [r7, #19] int N_SENSORS = 12; 800172a: 230c movs r3, #12 800172c: 60fb str r3, [r7, #12] uint16_t temperatures[N_SENSORS]; 800172e: 68fe ldr r6, [r7, #12] 8001730: 1e73 subs r3, r6, #1 8001732: 60bb str r3, [r7, #8] 8001734: 4632 mov r2, r6 8001736: 2300 movs r3, #0 8001738: 4614 mov r4, r2 800173a: 461d mov r5, r3 800173c: f04f 0200 mov.w r2, #0 8001740: f04f 0300 mov.w r3, #0 8001744: 012b lsls r3, r5, #4 8001746: ea43 7314 orr.w r3, r3, r4, lsr #28 800174a: 0122 lsls r2, r4, #4 800174c: 4632 mov r2, r6 800174e: 2300 movs r3, #0 8001750: 4610 mov r0, r2 8001752: 4619 mov r1, r3 8001754: f04f 0200 mov.w r2, #0 8001758: f04f 0300 mov.w r3, #0 800175c: 010b lsls r3, r1, #4 800175e: ea43 7310 orr.w r3, r3, r0, lsr #28 8001762: 0102 lsls r2, r0, #4 8001764: 4633 mov r3, r6 8001766: 005b lsls r3, r3, #1 8001768: 3307 adds r3, #7 800176a: 08db lsrs r3, r3, #3 800176c: 00db lsls r3, r3, #3 800176e: ebad 0d03 sub.w sp, sp, r3 8001772: 466b mov r3, sp 8001774: 3301 adds r3, #1 8001776: 085b lsrs r3, r3, #1 8001778: 005b lsls r3, r3, #1 800177a: 607b str r3, [r7, #4] for (int i = 0; i < N_SENSORS; i++) { 800177c: 2300 movs r3, #0 800177e: 617b str r3, [r7, #20] 8001780: e014 b.n 80017ac if (sensor_read(i, &temperatures[i]) != HAL_OK) { 8001782: 697b ldr r3, [r7, #20] 8001784: 005b lsls r3, r3, #1 8001786: 687a ldr r2, [r7, #4] 8001788: 4413 add r3, r2 800178a: 4619 mov r1, r3 800178c: 6978 ldr r0, [r7, #20] 800178e: f000 fae9 bl 8001d64 8001792: 4603 mov r3, r0 8001794: 2b00 cmp r3, #0 8001796: d006 beq.n 80017a6 sensor_init(i); 8001798: 6978 ldr r0, [r7, #20] 800179a: f000 fac5 bl 8001d28 last_error = HAL_GetTick(); 800179e: f000 fd61 bl 8002264 80017a2: 4603 mov r3, r0 80017a4: 74fb strb r3, [r7, #19] for (int i = 0; i < N_SENSORS; i++) { 80017a6: 697b ldr r3, [r7, #20] 80017a8: 3301 adds r3, #1 80017aa: 617b str r3, [r7, #20] 80017ac: 697a ldr r2, [r7, #20] 80017ae: 68fb ldr r3, [r7, #12] 80017b0: 429a cmp r2, r3 80017b2: dbe6 blt.n 8001782 } } canTestSendTemperatures(temperatures); 80017b4: 6878 ldr r0, [r7, #4] 80017b6: f7ff feb3 bl 8001520 80017ba: 46c5 mov sp, r8 } 80017bc: bf00 nop 80017be: 3718 adds r7, #24 80017c0: 46bd mov sp, r7 80017c2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} ... 080017c8 : void testLoop(uint8_t* data){ 80017c8: b580 push {r7, lr} 80017ca: b086 sub sp, #24 80017cc: af00 add r7, sp, #0 80017ce: 6078 str r0, [r7, #4] uint8_t action = data[0]; 80017d0: 687b ldr r3, [r7, #4] 80017d2: 781b ldrb r3, [r3, #0] 80017d4: 73fb strb r3, [r7, #15] switch(action){ 80017d6: 7bfb ldrb r3, [r7, #15] 80017d8: 3b01 subs r3, #1 80017da: 2b04 cmp r3, #4 80017dc: f200 8091 bhi.w 8001902 80017e0: a201 add r2, pc, #4 ; (adr r2, 80017e8 ) 80017e2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80017e6: bf00 nop 80017e8: 080017fd .word 0x080017fd 80017ec: 0800180b .word 0x0800180b 80017f0: 0800181d .word 0x0800181d 80017f4: 0800182b .word 0x0800182b 80017f8: 080018ab .word 0x080018ab case CAN_TEST: HAL_Delay(100); 80017fc: 2064 movs r0, #100 ; 0x64 80017fe: f000 fd3d bl 800227c canTestSendAnswer(data); 8001802: 6878 ldr r0, [r7, #4] 8001804: f7ff ff48 bl 8001698 break; 8001808: e07b b.n 8001902 case VOLTAGE_TEST: HAL_Delay(100); 800180a: 2064 movs r0, #100 ; 0x64 800180c: f000 fd36 bl 800227c amsReadCellVoltages(&module); 8001810: 483f ldr r0, [pc, #252] ; (8001910 ) 8001812: f7fe ffa3 bl 800075c ams_can_send_heartbeat(); 8001816: f7ff fcad bl 8001174 break; 800181a: e072 b.n 8001902 case TEMP_TEST: HAL_Delay(1000); 800181c: f44f 707a mov.w r0, #1000 ; 0x3e8 8001820: f000 fd2c bl 800227c readTemperatures(); 8001824: f7ff ff79 bl 800171a break; 8001828: e06b b.n 8001902 case EPROM_TEST: HAL_Delay(1000); 800182a: f44f 707a mov.w r0, #1000 ; 0x3e8 800182e: f000 fd25 bl 800227c for(uint16_t i = 1; i < 9; i++ ){ 8001832: 2301 movs r3, #1 8001834: 82fb strh r3, [r7, #22] 8001836: e016 b.n 8001866 if(i == 4){ 8001838: 8afb ldrh r3, [r7, #22] 800183a: 2b04 cmp r3, #4 800183c: d108 bne.n 8001850 writeeeprom(i*3, 0x42); 800183e: 8afa ldrh r2, [r7, #22] 8001840: 4613 mov r3, r2 8001842: 005b lsls r3, r3, #1 8001844: 4413 add r3, r2 8001846: 2142 movs r1, #66 ; 0x42 8001848: 4618 mov r0, r3 800184a: f000 fad7 bl 8001dfc 800184e: e007 b.n 8001860 }else{ writeeeprom(i*3, 0x69); 8001850: 8afa ldrh r2, [r7, #22] 8001852: 4613 mov r3, r2 8001854: 005b lsls r3, r3, #1 8001856: 4413 add r3, r2 8001858: 2169 movs r1, #105 ; 0x69 800185a: 4618 mov r0, r3 800185c: f000 face bl 8001dfc for(uint16_t i = 1; i < 9; i++ ){ 8001860: 8afb ldrh r3, [r7, #22] 8001862: 3301 adds r3, #1 8001864: 82fb strh r3, [r7, #22] 8001866: 8afb ldrh r3, [r7, #22] 8001868: 2b08 cmp r3, #8 800186a: d9e5 bls.n 8001838 } } HAL_Delay(1000); 800186c: f44f 707a mov.w r0, #1000 ; 0x3e8 8001870: f000 fd04 bl 800227c for(uint16_t i = 1; i < 9; i++ ){ 8001874: 2301 movs r3, #1 8001876: 82bb strh r3, [r7, #20] 8001878: e010 b.n 800189c data[i-1] = readeeprom(i*3); 800187a: 8aba ldrh r2, [r7, #20] 800187c: 4613 mov r3, r2 800187e: 005b lsls r3, r3, #1 8001880: 4413 add r3, r2 8001882: 4618 mov r0, r3 8001884: f000 fa9e bl 8001dc4 8001888: 4601 mov r1, r0 800188a: 8abb ldrh r3, [r7, #20] 800188c: 3b01 subs r3, #1 800188e: 687a ldr r2, [r7, #4] 8001890: 4413 add r3, r2 8001892: b2ca uxtb r2, r1 8001894: 701a strb r2, [r3, #0] for(uint16_t i = 1; i < 9; i++ ){ 8001896: 8abb ldrh r3, [r7, #20] 8001898: 3301 adds r3, #1 800189a: 82bb strh r3, [r7, #20] 800189c: 8abb ldrh r3, [r7, #20] 800189e: 2b08 cmp r3, #8 80018a0: d9eb bls.n 800187a } canTestSendAnswer(data); 80018a2: 6878 ldr r0, [r7, #4] 80018a4: f7ff fef8 bl 8001698 break; 80018a8: e02b b.n 8001902 case BALANCING_TEST: HAL_Delay(1000); 80018aa: f44f 707a mov.w r0, #1000 ; 0x3e8 80018ae: f000 fce5 bl 800227c for(int i = 0; i < 17; i++){ 80018b2: 2300 movs r3, #0 80018b4: 613b str r3, [r7, #16] 80018b6: e010 b.n 80018da amsConfigBalancing(0x00001< amsStartBalancing(10); 80018c6: 200a movs r0, #10 80018c8: f7fe fe31 bl 800052e HAL_Delay(1000); 80018cc: f44f 707a mov.w r0, #1000 ; 0x3e8 80018d0: f000 fcd4 bl 800227c for(int i = 0; i < 17; i++){ 80018d4: 693b ldr r3, [r7, #16] 80018d6: 3301 adds r3, #1 80018d8: 613b str r3, [r7, #16] 80018da: 693b ldr r3, [r7, #16] 80018dc: 2b10 cmp r3, #16 80018de: ddeb ble.n 80018b8 } HAL_Delay(1000); 80018e0: f44f 707a mov.w r0, #1000 ; 0x3e8 80018e4: f000 fcca bl 800227c amsConfigBalancing(0x1FFFF); 80018e8: 480a ldr r0, [pc, #40] ; (8001914 ) 80018ea: f7fe fdcb bl 8000484 amsStartBalancing(10); 80018ee: 200a movs r0, #10 80018f0: f7fe fe1d bl 800052e HAL_Delay(1000); 80018f4: f44f 707a mov.w r0, #1000 ; 0x3e8 80018f8: f000 fcc0 bl 800227c amsStopBalancing(); 80018fc: f7fe fe26 bl 800054c break; 8001900: bf00 nop } resetData(data); 8001902: 6878 ldr r0, [r7, #4] 8001904: f7ff fef2 bl 80016ec } 8001908: bf00 nop 800190a: 3718 adds r7, #24 800190c: 46bd mov sp, r7 800190e: bd80 pop {r7, pc} 8001910: 20000098 .word 0x20000098 8001914: 0001ffff .word 0x0001ffff 08001918
: /** * @brief The application entry point. * @retval int */ int main(void) { 8001918: b580 push {r7, lr} 800191a: b088 sub sp, #32 800191c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800191e: f000 fc47 bl 80021b0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001922: f000 f853 bl 80019cc /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001926: f000 f99b bl 8001c60 MX_CAN_Init(); 800192a: f000 f8a5 bl 8001a78 MX_I2C1_Init(); 800192e: f000 f8d9 bl 8001ae4 MX_I2C2_Init(); 8001932: f000 f917 bl 8001b64 MX_SPI1_Init(); 8001936: f000 f955 bl 8001be4 /* USER CODE BEGIN 2 */ // eepromInitParameters(); for (int i = 0; i < N_SENSORS; i++) { 800193a: 2300 movs r3, #0 800193c: 61fb str r3, [r7, #28] 800193e: e00d b.n 800195c if (sensor_init(i) != HAL_OK) { 8001940: 69f8 ldr r0, [r7, #28] 8001942: f000 f9f1 bl 8001d28 8001946: 4603 mov r3, r0 8001948: 2b00 cmp r3, #0 800194a: d004 beq.n 8001956 last_error = HAL_GetTick(); 800194c: f000 fc8a bl 8002264 8001950: 4603 mov r3, r0 8001952: 4a1a ldr r2, [pc, #104] ; (80019bc ) 8001954: 6013 str r3, [r2, #0] for (int i = 0; i < N_SENSORS; i++) { 8001956: 69fb ldr r3, [r7, #28] 8001958: 3301 adds r3, #1 800195a: 61fb str r3, [r7, #28] 800195c: 69fb ldr r3, [r7, #28] 800195e: 2b0b cmp r3, #11 8001960: ddee ble.n 8001940 } } AMS_Init(&hspi1); 8001962: 4817 ldr r0, [pc, #92] ; (80019c0 ) 8001964: f7ff fc8c bl 8001280 ams_can_init(&hcan, &hcan); 8001968: 4916 ldr r1, [pc, #88] ; (80019c4 ) 800196a: 4816 ldr r0, [pc, #88] ; (80019c4 ) 800196c: f7ff fb4e bl 800100c // HAL_TIM_Base_Start(&htim2); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ writeeeprom(1, 69); 8001970: 2145 movs r1, #69 ; 0x45 8001972: 2001 movs r0, #1 8001974: f000 fa42 bl 8001dfc uint16_t temperatures[N_SENSORS]; AMS_Loop(); 8001978: f7ff fcb8 bl 80012ec while (1){ if(BMS_IN_TEST_MODE == 1 ){ ////&& PENDING_MESSAGE_HANDLE == 1 testLoop(&canTestData); 800197c: 4812 ldr r0, [pc, #72] ; (80019c8 ) 800197e: f7ff ff23 bl 80017c8 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ for (int i = 0; i < N_SENSORS; i++) { 8001982: 2300 movs r3, #0 8001984: 61bb str r3, [r7, #24] 8001986: e015 b.n 80019b4 if (sensor_read(i, &temperatures[i]) != HAL_OK) { 8001988: 463a mov r2, r7 800198a: 69bb ldr r3, [r7, #24] 800198c: 005b lsls r3, r3, #1 800198e: 4413 add r3, r2 8001990: 4619 mov r1, r3 8001992: 69b8 ldr r0, [r7, #24] 8001994: f000 f9e6 bl 8001d64 8001998: 4603 mov r3, r0 800199a: 2b00 cmp r3, #0 800199c: d007 beq.n 80019ae sensor_init(i); 800199e: 69b8 ldr r0, [r7, #24] 80019a0: f000 f9c2 bl 8001d28 last_error = HAL_GetTick(); 80019a4: f000 fc5e bl 8002264 80019a8: 4603 mov r3, r0 80019aa: 4a04 ldr r2, [pc, #16] ; (80019bc ) 80019ac: 6013 str r3, [r2, #0] for (int i = 0; i < N_SENSORS; i++) { 80019ae: 69bb ldr r3, [r7, #24] 80019b0: 3301 adds r3, #1 80019b2: 61bb str r3, [r7, #24] 80019b4: 69bb ldr r3, [r7, #24] 80019b6: 2b0b cmp r3, #11 80019b8: dde6 ble.n 8001988 if(BMS_IN_TEST_MODE == 1 ){ ////&& PENDING_MESSAGE_HANDLE == 1 80019ba: e7df b.n 800197c 80019bc: 20000268 .word 0x20000268 80019c0: 20000204 .word 0x20000204 80019c4: 20000144 .word 0x20000144 80019c8: 20000044 .word 0x20000044 080019cc : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80019cc: b580 push {r7, lr} 80019ce: b09c sub sp, #112 ; 0x70 80019d0: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80019d2: f107 0348 add.w r3, r7, #72 ; 0x48 80019d6: 2228 movs r2, #40 ; 0x28 80019d8: 2100 movs r1, #0 80019da: 4618 mov r0, r3 80019dc: f004 fd6c bl 80064b8 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80019e0: f107 0334 add.w r3, r7, #52 ; 0x34 80019e4: 2200 movs r2, #0 80019e6: 601a str r2, [r3, #0] 80019e8: 605a str r2, [r3, #4] 80019ea: 609a str r2, [r3, #8] 80019ec: 60da str r2, [r3, #12] 80019ee: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 80019f0: 463b mov r3, r7 80019f2: 2234 movs r2, #52 ; 0x34 80019f4: 2100 movs r1, #0 80019f6: 4618 mov r0, r3 80019f8: f004 fd5e bl 80064b8 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE; 80019fc: 2303 movs r3, #3 80019fe: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8001a00: f44f 3380 mov.w r3, #65536 ; 0x10000 8001a04: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001a06: 2301 movs r3, #1 8001a08: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8001a0a: 2310 movs r3, #16 8001a0c: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8001a0e: 2300 movs r3, #0 8001a10: 667b str r3, [r7, #100] ; 0x64 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001a12: f107 0348 add.w r3, r7, #72 ; 0x48 8001a16: 4618 mov r0, r3 8001a18: f002 fd50 bl 80044bc 8001a1c: 4603 mov r3, r0 8001a1e: 2b00 cmp r3, #0 8001a20: d001 beq.n 8001a26 { Error_Handler(); 8001a22: f000 fa09 bl 8001e38 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001a26: 230f movs r3, #15 8001a28: 637b str r3, [r7, #52] ; 0x34 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 8001a2a: 2301 movs r3, #1 8001a2c: 63bb str r3, [r7, #56] ; 0x38 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001a2e: 2300 movs r3, #0 8001a30: 63fb str r3, [r7, #60] ; 0x3c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8001a32: 2300 movs r3, #0 8001a34: 643b str r3, [r7, #64] ; 0x40 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001a36: 2300 movs r3, #0 8001a38: 647b str r3, [r7, #68] ; 0x44 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8001a3a: f107 0334 add.w r3, r7, #52 ; 0x34 8001a3e: 2100 movs r1, #0 8001a40: 4618 mov r0, r3 8001a42: f003 fd79 bl 8005538 8001a46: 4603 mov r3, r0 8001a48: 2b00 cmp r3, #0 8001a4a: d001 beq.n 8001a50 { Error_Handler(); 8001a4c: f000 f9f4 bl 8001e38 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C2; 8001a50: 2360 movs r3, #96 ; 0x60 8001a52: 603b str r3, [r7, #0] PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; 8001a54: 2300 movs r3, #0 8001a56: 61fb str r3, [r7, #28] PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_HSI; 8001a58: 2300 movs r3, #0 8001a5a: 623b str r3, [r7, #32] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001a5c: 463b mov r3, r7 8001a5e: 4618 mov r0, r3 8001a60: f003 ff52 bl 8005908 8001a64: 4603 mov r3, r0 8001a66: 2b00 cmp r3, #0 8001a68: d001 beq.n 8001a6e { Error_Handler(); 8001a6a: f000 f9e5 bl 8001e38 } } 8001a6e: bf00 nop 8001a70: 3770 adds r7, #112 ; 0x70 8001a72: 46bd mov sp, r7 8001a74: bd80 pop {r7, pc} ... 08001a78 : * @brief CAN Initialization Function * @param None * @retval None */ static void MX_CAN_Init(void) { 8001a78: b580 push {r7, lr} 8001a7a: af00 add r7, sp, #0 /* USER CODE END CAN_Init 0 */ /* USER CODE BEGIN CAN_Init 1 */ /* USER CODE END CAN_Init 1 */ hcan.Instance = CAN; 8001a7c: 4b17 ldr r3, [pc, #92] ; (8001adc ) 8001a7e: 4a18 ldr r2, [pc, #96] ; (8001ae0 ) 8001a80: 601a str r2, [r3, #0] hcan.Init.Prescaler = 2; 8001a82: 4b16 ldr r3, [pc, #88] ; (8001adc ) 8001a84: 2202 movs r2, #2 8001a86: 605a str r2, [r3, #4] hcan.Init.Mode = CAN_MODE_NORMAL; 8001a88: 4b14 ldr r3, [pc, #80] ; (8001adc ) 8001a8a: 2200 movs r2, #0 8001a8c: 609a str r2, [r3, #8] hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; 8001a8e: 4b13 ldr r3, [pc, #76] ; (8001adc ) 8001a90: 2200 movs r2, #0 8001a92: 60da str r2, [r3, #12] hcan.Init.TimeSeg1 = CAN_BS1_13TQ; 8001a94: 4b11 ldr r3, [pc, #68] ; (8001adc ) 8001a96: f44f 2240 mov.w r2, #786432 ; 0xc0000 8001a9a: 611a str r2, [r3, #16] hcan.Init.TimeSeg2 = CAN_BS2_2TQ; 8001a9c: 4b0f ldr r3, [pc, #60] ; (8001adc ) 8001a9e: f44f 1280 mov.w r2, #1048576 ; 0x100000 8001aa2: 615a str r2, [r3, #20] hcan.Init.TimeTriggeredMode = DISABLE; 8001aa4: 4b0d ldr r3, [pc, #52] ; (8001adc ) 8001aa6: 2200 movs r2, #0 8001aa8: 761a strb r2, [r3, #24] hcan.Init.AutoBusOff = ENABLE; 8001aaa: 4b0c ldr r3, [pc, #48] ; (8001adc ) 8001aac: 2201 movs r2, #1 8001aae: 765a strb r2, [r3, #25] hcan.Init.AutoWakeUp = DISABLE; 8001ab0: 4b0a ldr r3, [pc, #40] ; (8001adc ) 8001ab2: 2200 movs r2, #0 8001ab4: 769a strb r2, [r3, #26] hcan.Init.AutoRetransmission = ENABLE; 8001ab6: 4b09 ldr r3, [pc, #36] ; (8001adc ) 8001ab8: 2201 movs r2, #1 8001aba: 76da strb r2, [r3, #27] hcan.Init.ReceiveFifoLocked = DISABLE; 8001abc: 4b07 ldr r3, [pc, #28] ; (8001adc ) 8001abe: 2200 movs r2, #0 8001ac0: 771a strb r2, [r3, #28] hcan.Init.TransmitFifoPriority = DISABLE; 8001ac2: 4b06 ldr r3, [pc, #24] ; (8001adc ) 8001ac4: 2200 movs r2, #0 8001ac6: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan) != HAL_OK) 8001ac8: 4804 ldr r0, [pc, #16] ; (8001adc ) 8001aca: f000 fbfb bl 80022c4 8001ace: 4603 mov r3, r0 8001ad0: 2b00 cmp r3, #0 8001ad2: d001 beq.n 8001ad8 { Error_Handler(); 8001ad4: f000 f9b0 bl 8001e38 } /* USER CODE BEGIN CAN_Init 2 */ /* USER CODE END CAN_Init 2 */ } 8001ad8: bf00 nop 8001ada: bd80 pop {r7, pc} 8001adc: 20000144 .word 0x20000144 8001ae0: 40006400 .word 0x40006400 08001ae4 : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_Init(void) { 8001ae4: b580 push {r7, lr} 8001ae6: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8001ae8: 4b1b ldr r3, [pc, #108] ; (8001b58 ) 8001aea: 4a1c ldr r2, [pc, #112] ; (8001b5c ) 8001aec: 601a str r2, [r3, #0] hi2c1.Init.Timing = 0x2000090E; 8001aee: 4b1a ldr r3, [pc, #104] ; (8001b58 ) 8001af0: 4a1b ldr r2, [pc, #108] ; (8001b60 ) 8001af2: 605a str r2, [r3, #4] hi2c1.Init.OwnAddress1 = 0; 8001af4: 4b18 ldr r3, [pc, #96] ; (8001b58 ) 8001af6: 2200 movs r2, #0 8001af8: 609a str r2, [r3, #8] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8001afa: 4b17 ldr r3, [pc, #92] ; (8001b58 ) 8001afc: 2201 movs r2, #1 8001afe: 60da str r2, [r3, #12] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8001b00: 4b15 ldr r3, [pc, #84] ; (8001b58 ) 8001b02: 2200 movs r2, #0 8001b04: 611a str r2, [r3, #16] hi2c1.Init.OwnAddress2 = 0; 8001b06: 4b14 ldr r3, [pc, #80] ; (8001b58 ) 8001b08: 2200 movs r2, #0 8001b0a: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 8001b0c: 4b12 ldr r3, [pc, #72] ; (8001b58 ) 8001b0e: 2200 movs r2, #0 8001b10: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8001b12: 4b11 ldr r3, [pc, #68] ; (8001b58 ) 8001b14: 2200 movs r2, #0 8001b16: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8001b18: 4b0f ldr r3, [pc, #60] ; (8001b58 ) 8001b1a: 2200 movs r2, #0 8001b1c: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8001b1e: 480e ldr r0, [pc, #56] ; (8001b58 ) 8001b20: f001 fcf4 bl 800350c 8001b24: 4603 mov r3, r0 8001b26: 2b00 cmp r3, #0 8001b28: d001 beq.n 8001b2e { Error_Handler(); 8001b2a: f000 f985 bl 8001e38 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8001b2e: 2100 movs r1, #0 8001b30: 4809 ldr r0, [pc, #36] ; (8001b58 ) 8001b32: f002 fc2b bl 800438c 8001b36: 4603 mov r3, r0 8001b38: 2b00 cmp r3, #0 8001b3a: d001 beq.n 8001b40 { Error_Handler(); 8001b3c: f000 f97c bl 8001e38 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 8001b40: 2100 movs r1, #0 8001b42: 4805 ldr r0, [pc, #20] ; (8001b58 ) 8001b44: f002 fc6d bl 8004422 8001b48: 4603 mov r3, r0 8001b4a: 2b00 cmp r3, #0 8001b4c: d001 beq.n 8001b52 { Error_Handler(); 8001b4e: f000 f973 bl 8001e38 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8001b52: bf00 nop 8001b54: bd80 pop {r7, pc} 8001b56: bf00 nop 8001b58: 2000016c .word 0x2000016c 8001b5c: 40005400 .word 0x40005400 8001b60: 2000090e .word 0x2000090e 08001b64 : * @brief I2C2 Initialization Function * @param None * @retval None */ static void MX_I2C2_Init(void) { 8001b64: b580 push {r7, lr} 8001b66: af00 add r7, sp, #0 /* USER CODE END I2C2_Init 0 */ /* USER CODE BEGIN I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */ hi2c2.Instance = I2C2; 8001b68: 4b1b ldr r3, [pc, #108] ; (8001bd8 ) 8001b6a: 4a1c ldr r2, [pc, #112] ; (8001bdc ) 8001b6c: 601a str r2, [r3, #0] hi2c2.Init.Timing = 0x2000090E; 8001b6e: 4b1a ldr r3, [pc, #104] ; (8001bd8 ) 8001b70: 4a1b ldr r2, [pc, #108] ; (8001be0 ) 8001b72: 605a str r2, [r3, #4] hi2c2.Init.OwnAddress1 = 0; 8001b74: 4b18 ldr r3, [pc, #96] ; (8001bd8 ) 8001b76: 2200 movs r2, #0 8001b78: 609a str r2, [r3, #8] hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8001b7a: 4b17 ldr r3, [pc, #92] ; (8001bd8 ) 8001b7c: 2201 movs r2, #1 8001b7e: 60da str r2, [r3, #12] hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8001b80: 4b15 ldr r3, [pc, #84] ; (8001bd8 ) 8001b82: 2200 movs r2, #0 8001b84: 611a str r2, [r3, #16] hi2c2.Init.OwnAddress2 = 0; 8001b86: 4b14 ldr r3, [pc, #80] ; (8001bd8 ) 8001b88: 2200 movs r2, #0 8001b8a: 615a str r2, [r3, #20] hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 8001b8c: 4b12 ldr r3, [pc, #72] ; (8001bd8 ) 8001b8e: 2200 movs r2, #0 8001b90: 619a str r2, [r3, #24] hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8001b92: 4b11 ldr r3, [pc, #68] ; (8001bd8 ) 8001b94: 2200 movs r2, #0 8001b96: 61da str r2, [r3, #28] hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8001b98: 4b0f ldr r3, [pc, #60] ; (8001bd8 ) 8001b9a: 2200 movs r2, #0 8001b9c: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c2) != HAL_OK) 8001b9e: 480e ldr r0, [pc, #56] ; (8001bd8 ) 8001ba0: f001 fcb4 bl 800350c 8001ba4: 4603 mov r3, r0 8001ba6: 2b00 cmp r3, #0 8001ba8: d001 beq.n 8001bae { Error_Handler(); 8001baa: f000 f945 bl 8001e38 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8001bae: 2100 movs r1, #0 8001bb0: 4809 ldr r0, [pc, #36] ; (8001bd8 ) 8001bb2: f002 fbeb bl 800438c 8001bb6: 4603 mov r3, r0 8001bb8: 2b00 cmp r3, #0 8001bba: d001 beq.n 8001bc0 { Error_Handler(); 8001bbc: f000 f93c bl 8001e38 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) 8001bc0: 2100 movs r1, #0 8001bc2: 4805 ldr r0, [pc, #20] ; (8001bd8 ) 8001bc4: f002 fc2d bl 8004422 8001bc8: 4603 mov r3, r0 8001bca: 2b00 cmp r3, #0 8001bcc: d001 beq.n 8001bd2 { Error_Handler(); 8001bce: f000 f933 bl 8001e38 } /* USER CODE BEGIN I2C2_Init 2 */ /* USER CODE END I2C2_Init 2 */ } 8001bd2: bf00 nop 8001bd4: bd80 pop {r7, pc} 8001bd6: bf00 nop 8001bd8: 200001b8 .word 0x200001b8 8001bdc: 40005800 .word 0x40005800 8001be0: 2000090e .word 0x2000090e 08001be4 : * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 8001be4: b580 push {r7, lr} 8001be6: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; 8001be8: 4b1b ldr r3, [pc, #108] ; (8001c58 ) 8001bea: 4a1c ldr r2, [pc, #112] ; (8001c5c ) 8001bec: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 8001bee: 4b1a ldr r3, [pc, #104] ; (8001c58 ) 8001bf0: f44f 7282 mov.w r2, #260 ; 0x104 8001bf4: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 8001bf6: 4b18 ldr r3, [pc, #96] ; (8001c58 ) 8001bf8: 2200 movs r2, #0 8001bfa: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 8001bfc: 4b16 ldr r3, [pc, #88] ; (8001c58 ) 8001bfe: f44f 62e0 mov.w r2, #1792 ; 0x700 8001c02: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 8001c04: 4b14 ldr r3, [pc, #80] ; (8001c58 ) 8001c06: 2200 movs r2, #0 8001c08: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 8001c0a: 4b13 ldr r3, [pc, #76] ; (8001c58 ) 8001c0c: 2200 movs r2, #0 8001c0e: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_SOFT; 8001c10: 4b11 ldr r3, [pc, #68] ; (8001c58 ) 8001c12: f44f 7200 mov.w r2, #512 ; 0x200 8001c16: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; 8001c18: 4b0f ldr r3, [pc, #60] ; (8001c58 ) 8001c1a: 2220 movs r2, #32 8001c1c: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 8001c1e: 4b0e ldr r3, [pc, #56] ; (8001c58 ) 8001c20: 2200 movs r2, #0 8001c22: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 8001c24: 4b0c ldr r3, [pc, #48] ; (8001c58 ) 8001c26: 2200 movs r2, #0 8001c28: 625a str r2, [r3, #36] ; 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8001c2a: 4b0b ldr r3, [pc, #44] ; (8001c58 ) 8001c2c: 2200 movs r2, #0 8001c2e: 629a str r2, [r3, #40] ; 0x28 hspi1.Init.CRCPolynomial = 7; 8001c30: 4b09 ldr r3, [pc, #36] ; (8001c58 ) 8001c32: 2207 movs r2, #7 8001c34: 62da str r2, [r3, #44] ; 0x2c hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 8001c36: 4b08 ldr r3, [pc, #32] ; (8001c58 ) 8001c38: 2200 movs r2, #0 8001c3a: 631a str r2, [r3, #48] ; 0x30 hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 8001c3c: 4b06 ldr r3, [pc, #24] ; (8001c58 ) 8001c3e: 2208 movs r2, #8 8001c40: 635a str r2, [r3, #52] ; 0x34 if (HAL_SPI_Init(&hspi1) != HAL_OK) 8001c42: 4805 ldr r0, [pc, #20] ; (8001c58 ) 8001c44: f003 fff2 bl 8005c2c 8001c48: 4603 mov r3, r0 8001c4a: 2b00 cmp r3, #0 8001c4c: d001 beq.n 8001c52 { Error_Handler(); 8001c4e: f000 f8f3 bl 8001e38 } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 8001c52: bf00 nop 8001c54: bd80 pop {r7, pc} 8001c56: bf00 nop 8001c58: 20000204 .word 0x20000204 8001c5c: 40013000 .word 0x40013000 08001c60 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001c60: b580 push {r7, lr} 8001c62: b088 sub sp, #32 8001c64: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001c66: f107 030c add.w r3, r7, #12 8001c6a: 2200 movs r2, #0 8001c6c: 601a str r2, [r3, #0] 8001c6e: 605a str r2, [r3, #4] 8001c70: 609a str r2, [r3, #8] 8001c72: 60da str r2, [r3, #12] 8001c74: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 8001c76: 4b2a ldr r3, [pc, #168] ; (8001d20 ) 8001c78: 695b ldr r3, [r3, #20] 8001c7a: 4a29 ldr r2, [pc, #164] ; (8001d20 ) 8001c7c: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 8001c80: 6153 str r3, [r2, #20] 8001c82: 4b27 ldr r3, [pc, #156] ; (8001d20 ) 8001c84: 695b ldr r3, [r3, #20] 8001c86: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8001c8a: 60bb str r3, [r7, #8] 8001c8c: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c8e: 4b24 ldr r3, [pc, #144] ; (8001d20 ) 8001c90: 695b ldr r3, [r3, #20] 8001c92: 4a23 ldr r2, [pc, #140] ; (8001d20 ) 8001c94: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001c98: 6153 str r3, [r2, #20] 8001c9a: 4b21 ldr r3, [pc, #132] ; (8001d20 ) 8001c9c: 695b ldr r3, [r3, #20] 8001c9e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001ca2: 607b str r3, [r7, #4] 8001ca4: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001ca6: 4b1e ldr r3, [pc, #120] ; (8001d20 ) 8001ca8: 695b ldr r3, [r3, #20] 8001caa: 4a1d ldr r2, [pc, #116] ; (8001d20 ) 8001cac: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8001cb0: 6153 str r3, [r2, #20] 8001cb2: 4b1b ldr r3, [pc, #108] ; (8001d20 ) 8001cb4: 695b ldr r3, [r3, #20] 8001cb6: f403 2380 and.w r3, r3, #262144 ; 0x40000 8001cba: 603b str r3, [r7, #0] 8001cbc: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, CSB_Pin|Status_3_Pin, GPIO_PIN_RESET); 8001cbe: 2200 movs r2, #0 8001cc0: f44f 7188 mov.w r1, #272 ; 0x110 8001cc4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8001cc8: f001 fc08 bl 80034dc /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, Status_0_Pin|Status_1_Pin|Status_2_Pin, GPIO_PIN_RESET); 8001ccc: 2200 movs r2, #0 8001cce: f44f 4160 mov.w r1, #57344 ; 0xe000 8001cd2: 4814 ldr r0, [pc, #80] ; (8001d24 ) 8001cd4: f001 fc02 bl 80034dc /*Configure GPIO pins : CSB_Pin Status_3_Pin */ GPIO_InitStruct.Pin = CSB_Pin|Status_3_Pin; 8001cd8: f44f 7388 mov.w r3, #272 ; 0x110 8001cdc: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001cde: 2301 movs r3, #1 8001ce0: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001ce2: 2300 movs r3, #0 8001ce4: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001ce6: 2300 movs r3, #0 8001ce8: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001cea: f107 030c add.w r3, r7, #12 8001cee: 4619 mov r1, r3 8001cf0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8001cf4: f001 fa78 bl 80031e8 /*Configure GPIO pins : Status_0_Pin Status_1_Pin Status_2_Pin */ GPIO_InitStruct.Pin = Status_0_Pin|Status_1_Pin|Status_2_Pin; 8001cf8: f44f 4360 mov.w r3, #57344 ; 0xe000 8001cfc: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001cfe: 2301 movs r3, #1 8001d00: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d02: 2300 movs r3, #0 8001d04: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001d06: 2300 movs r3, #0 8001d08: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001d0a: f107 030c add.w r3, r7, #12 8001d0e: 4619 mov r1, r3 8001d10: 4804 ldr r0, [pc, #16] ; (8001d24 ) 8001d12: f001 fa69 bl 80031e8 } 8001d16: bf00 nop 8001d18: 3720 adds r7, #32 8001d1a: 46bd mov sp, r7 8001d1c: bd80 pop {r7, pc} 8001d1e: bf00 nop 8001d20: 40021000 .word 0x40021000 8001d24: 48000400 .word 0x48000400 08001d28 : /* USER CODE BEGIN 4 */ HAL_StatusTypeDef sensor_init(int n) { 8001d28: b580 push {r7, lr} 8001d2a: b086 sub sp, #24 8001d2c: af02 add r7, sp, #8 8001d2e: 6078 str r0, [r7, #4] uint16_t addr = (0b1000000 | n) << 1; 8001d30: 687b ldr r3, [r7, #4] 8001d32: 005b lsls r3, r3, #1 8001d34: b21b sxth r3, r3 8001d36: f043 0380 orr.w r3, r3, #128 ; 0x80 8001d3a: b21b sxth r3, r3 8001d3c: 81fb strh r3, [r7, #14] uint8_t data[] = {0}; 8001d3e: 2300 movs r3, #0 8001d40: 733b strb r3, [r7, #12] return HAL_I2C_Master_Transmit(&hi2c1, addr, data, sizeof(data), 100); 8001d42: f107 020c add.w r2, r7, #12 8001d46: 89f9 ldrh r1, [r7, #14] 8001d48: 2364 movs r3, #100 ; 0x64 8001d4a: 9300 str r3, [sp, #0] 8001d4c: 2301 movs r3, #1 8001d4e: 4804 ldr r0, [pc, #16] ; (8001d60 ) 8001d50: f001 fc6c bl 800362c 8001d54: 4603 mov r3, r0 } 8001d56: 4618 mov r0, r3 8001d58: 3710 adds r7, #16 8001d5a: 46bd mov sp, r7 8001d5c: bd80 pop {r7, pc} 8001d5e: bf00 nop 8001d60: 2000016c .word 0x2000016c 08001d64 : HAL_StatusTypeDef sensor_read(int n, uint16_t *res) { 8001d64: b580 push {r7, lr} 8001d66: b086 sub sp, #24 8001d68: af02 add r7, sp, #8 8001d6a: 6078 str r0, [r7, #4] 8001d6c: 6039 str r1, [r7, #0] uint16_t addr = (0b1000000 | n) << 1; 8001d6e: 687b ldr r3, [r7, #4] 8001d70: 005b lsls r3, r3, #1 8001d72: b21b sxth r3, r3 8001d74: f043 0380 orr.w r3, r3, #128 ; 0x80 8001d78: b21b sxth r3, r3 8001d7a: 81fb strh r3, [r7, #14] addr |= 1; // Read 8001d7c: 89fb ldrh r3, [r7, #14] 8001d7e: f043 0301 orr.w r3, r3, #1 8001d82: 81fb strh r3, [r7, #14] uint8_t result[2]; HAL_StatusTypeDef status = HAL_I2C_Master_Receive(&hi2c1, addr, result, sizeof(result), 100); 8001d84: f107 0208 add.w r2, r7, #8 8001d88: 89f9 ldrh r1, [r7, #14] 8001d8a: 2364 movs r3, #100 ; 0x64 8001d8c: 9300 str r3, [sp, #0] 8001d8e: 2302 movs r3, #2 8001d90: 480b ldr r0, [pc, #44] ; (8001dc0 ) 8001d92: f001 fd3f bl 8003814 8001d96: 4603 mov r3, r0 8001d98: 737b strb r3, [r7, #13] if (status == HAL_OK) { 8001d9a: 7b7b ldrb r3, [r7, #13] 8001d9c: 2b00 cmp r3, #0 8001d9e: d109 bne.n 8001db4 *res = (result[0] << 8) | result[1]; 8001da0: 7a3b ldrb r3, [r7, #8] 8001da2: 021b lsls r3, r3, #8 8001da4: b21a sxth r2, r3 8001da6: 7a7b ldrb r3, [r7, #9] 8001da8: b21b sxth r3, r3 8001daa: 4313 orrs r3, r2 8001dac: b21b sxth r3, r3 8001dae: b29a uxth r2, r3 8001db0: 683b ldr r3, [r7, #0] 8001db2: 801a strh r2, [r3, #0] } return status; 8001db4: 7b7b ldrb r3, [r7, #13] } 8001db6: 4618 mov r0, r3 8001db8: 3710 adds r7, #16 8001dba: 46bd mov sp, r7 8001dbc: bd80 pop {r7, pc} 8001dbe: bf00 nop 8001dc0: 2000016c .word 0x2000016c 08001dc4 : uint8_t readeeprom(uint16_t address){ 8001dc4: b580 push {r7, lr} 8001dc6: b088 sub sp, #32 8001dc8: af04 add r7, sp, #16 8001dca: 4603 mov r3, r0 8001dcc: 80fb strh r3, [r7, #6] uint8_t data = 0; 8001dce: 2300 movs r3, #0 8001dd0: 73fb strb r3, [r7, #15] //uint8_t* address2 = (uint8_t*) &address; //HAL_I2C_Master_Transmit(&hi2c2, 0xA0, address2, 2, 1000); //HAL_I2C_Master_Receive(&hi2c2, 0xA0, &data, 1, 1000); HAL_I2C_Mem_Read(&hi2c2, 0xA0, address, 2, &data, 1 , 1000); 8001dd2: 88fa ldrh r2, [r7, #6] 8001dd4: f44f 737a mov.w r3, #1000 ; 0x3e8 8001dd8: 9302 str r3, [sp, #8] 8001dda: 2301 movs r3, #1 8001ddc: 9301 str r3, [sp, #4] 8001dde: f107 030f add.w r3, r7, #15 8001de2: 9300 str r3, [sp, #0] 8001de4: 2302 movs r3, #2 8001de6: 21a0 movs r1, #160 ; 0xa0 8001de8: 4803 ldr r0, [pc, #12] ; (8001df8 ) 8001dea: f001 ff1d bl 8003c28 //HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, // uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) return data; 8001dee: 7bfb ldrb r3, [r7, #15] } 8001df0: 4618 mov r0, r3 8001df2: 3710 adds r7, #16 8001df4: 46bd mov sp, r7 8001df6: bd80 pop {r7, pc} 8001df8: 200001b8 .word 0x200001b8 08001dfc : void writeeeprom(uint16_t address, uint8_t data){ 8001dfc: b580 push {r7, lr} 8001dfe: b086 sub sp, #24 8001e00: af04 add r7, sp, #16 8001e02: 4603 mov r3, r0 8001e04: 460a mov r2, r1 8001e06: 80fb strh r3, [r7, #6] 8001e08: 4613 mov r3, r2 8001e0a: 717b strb r3, [r7, #5] HAL_I2C_Mem_Write(&hi2c2, 0xA0, address, 2, &data, 1, 1000); 8001e0c: 88fa ldrh r2, [r7, #6] 8001e0e: f44f 737a mov.w r3, #1000 ; 0x3e8 8001e12: 9302 str r3, [sp, #8] 8001e14: 2301 movs r3, #1 8001e16: 9301 str r3, [sp, #4] 8001e18: 1d7b adds r3, r7, #5 8001e1a: 9300 str r3, [sp, #0] 8001e1c: 2302 movs r3, #2 8001e1e: 21a0 movs r1, #160 ; 0xa0 8001e20: 4804 ldr r0, [pc, #16] ; (8001e34 ) 8001e22: f001 fded bl 8003a00 HAL_Delay(5); 8001e26: 2005 movs r0, #5 8001e28: f000 fa28 bl 800227c } 8001e2c: bf00 nop 8001e2e: 3708 adds r7, #8 8001e30: 46bd mov sp, r7 8001e32: bd80 pop {r7, pc} 8001e34: 200001b8 .word 0x200001b8 08001e38 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001e38: b480 push {r7} 8001e3a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001e3c: b672 cpsid i } 8001e3e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001e40: e7fe b.n 8001e40 ... 08001e44 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001e44: b480 push {r7} 8001e46: b083 sub sp, #12 8001e48: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001e4a: 4b0f ldr r3, [pc, #60] ; (8001e88 ) 8001e4c: 699b ldr r3, [r3, #24] 8001e4e: 4a0e ldr r2, [pc, #56] ; (8001e88 ) 8001e50: f043 0301 orr.w r3, r3, #1 8001e54: 6193 str r3, [r2, #24] 8001e56: 4b0c ldr r3, [pc, #48] ; (8001e88 ) 8001e58: 699b ldr r3, [r3, #24] 8001e5a: f003 0301 and.w r3, r3, #1 8001e5e: 607b str r3, [r7, #4] 8001e60: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8001e62: 4b09 ldr r3, [pc, #36] ; (8001e88 ) 8001e64: 69db ldr r3, [r3, #28] 8001e66: 4a08 ldr r2, [pc, #32] ; (8001e88 ) 8001e68: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001e6c: 61d3 str r3, [r2, #28] 8001e6e: 4b06 ldr r3, [pc, #24] ; (8001e88 ) 8001e70: 69db ldr r3, [r3, #28] 8001e72: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001e76: 603b str r3, [r7, #0] 8001e78: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001e7a: bf00 nop 8001e7c: 370c adds r7, #12 8001e7e: 46bd mov sp, r7 8001e80: f85d 7b04 ldr.w r7, [sp], #4 8001e84: 4770 bx lr 8001e86: bf00 nop 8001e88: 40021000 .word 0x40021000 08001e8c : * This function configures the hardware resources used in this example * @param hcan: CAN handle pointer * @retval None */ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) { 8001e8c: b580 push {r7, lr} 8001e8e: b08a sub sp, #40 ; 0x28 8001e90: af00 add r7, sp, #0 8001e92: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001e94: f107 0314 add.w r3, r7, #20 8001e98: 2200 movs r2, #0 8001e9a: 601a str r2, [r3, #0] 8001e9c: 605a str r2, [r3, #4] 8001e9e: 609a str r2, [r3, #8] 8001ea0: 60da str r2, [r3, #12] 8001ea2: 611a str r2, [r3, #16] if(hcan->Instance==CAN) 8001ea4: 687b ldr r3, [r7, #4] 8001ea6: 681b ldr r3, [r3, #0] 8001ea8: 4a1c ldr r2, [pc, #112] ; (8001f1c ) 8001eaa: 4293 cmp r3, r2 8001eac: d131 bne.n 8001f12 { /* USER CODE BEGIN CAN_MspInit 0 */ /* USER CODE END CAN_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CAN1_CLK_ENABLE(); 8001eae: 4b1c ldr r3, [pc, #112] ; (8001f20 ) 8001eb0: 69db ldr r3, [r3, #28] 8001eb2: 4a1b ldr r2, [pc, #108] ; (8001f20 ) 8001eb4: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8001eb8: 61d3 str r3, [r2, #28] 8001eba: 4b19 ldr r3, [pc, #100] ; (8001f20 ) 8001ebc: 69db ldr r3, [r3, #28] 8001ebe: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001ec2: 613b str r3, [r7, #16] 8001ec4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001ec6: 4b16 ldr r3, [pc, #88] ; (8001f20 ) 8001ec8: 695b ldr r3, [r3, #20] 8001eca: 4a15 ldr r2, [pc, #84] ; (8001f20 ) 8001ecc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001ed0: 6153 str r3, [r2, #20] 8001ed2: 4b13 ldr r3, [pc, #76] ; (8001f20 ) 8001ed4: 695b ldr r3, [r3, #20] 8001ed6: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001eda: 60fb str r3, [r7, #12] 8001edc: 68fb ldr r3, [r7, #12] /**CAN GPIO Configuration PA11 ------> CAN_RX PA12 ------> CAN_TX */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 8001ede: f44f 53c0 mov.w r3, #6144 ; 0x1800 8001ee2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001ee4: 2302 movs r3, #2 8001ee6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001ee8: 2300 movs r3, #0 8001eea: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001eec: 2303 movs r3, #3 8001eee: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF9_CAN; 8001ef0: 2309 movs r3, #9 8001ef2: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001ef4: f107 0314 add.w r3, r7, #20 8001ef8: 4619 mov r1, r3 8001efa: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8001efe: f001 f973 bl 80031e8 /* CAN interrupt Init */ HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); 8001f02: 2200 movs r2, #0 8001f04: 2100 movs r1, #0 8001f06: 2014 movs r0, #20 8001f08: f001 f937 bl 800317a HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); 8001f0c: 2014 movs r0, #20 8001f0e: f001 f950 bl 80031b2 /* USER CODE BEGIN CAN_MspInit 1 */ /* USER CODE END CAN_MspInit 1 */ } } 8001f12: bf00 nop 8001f14: 3728 adds r7, #40 ; 0x28 8001f16: 46bd mov sp, r7 8001f18: bd80 pop {r7, pc} 8001f1a: bf00 nop 8001f1c: 40006400 .word 0x40006400 8001f20: 40021000 .word 0x40021000 08001f24 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8001f24: b580 push {r7, lr} 8001f26: b08c sub sp, #48 ; 0x30 8001f28: af00 add r7, sp, #0 8001f2a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001f2c: f107 031c add.w r3, r7, #28 8001f30: 2200 movs r2, #0 8001f32: 601a str r2, [r3, #0] 8001f34: 605a str r2, [r3, #4] 8001f36: 609a str r2, [r3, #8] 8001f38: 60da str r2, [r3, #12] 8001f3a: 611a str r2, [r3, #16] if(hi2c->Instance==I2C1) 8001f3c: 687b ldr r3, [r7, #4] 8001f3e: 681b ldr r3, [r3, #0] 8001f40: 4a3e ldr r2, [pc, #248] ; (800203c ) 8001f42: 4293 cmp r3, r2 8001f44: d146 bne.n 8001fd4 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001f46: 4b3e ldr r3, [pc, #248] ; (8002040 ) 8001f48: 695b ldr r3, [r3, #20] 8001f4a: 4a3d ldr r2, [pc, #244] ; (8002040 ) 8001f4c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001f50: 6153 str r3, [r2, #20] 8001f52: 4b3b ldr r3, [pc, #236] ; (8002040 ) 8001f54: 695b ldr r3, [r3, #20] 8001f56: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001f5a: 61bb str r3, [r7, #24] 8001f5c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001f5e: 4b38 ldr r3, [pc, #224] ; (8002040 ) 8001f60: 695b ldr r3, [r3, #20] 8001f62: 4a37 ldr r2, [pc, #220] ; (8002040 ) 8001f64: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8001f68: 6153 str r3, [r2, #20] 8001f6a: 4b35 ldr r3, [pc, #212] ; (8002040 ) 8001f6c: 695b ldr r3, [r3, #20] 8001f6e: f403 2380 and.w r3, r3, #262144 ; 0x40000 8001f72: 617b str r3, [r7, #20] 8001f74: 697b ldr r3, [r7, #20] /**I2C1 GPIO Configuration PA15 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = TMP_SCL_Pin; 8001f76: f44f 4300 mov.w r3, #32768 ; 0x8000 8001f7a: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8001f7c: 2312 movs r3, #18 8001f7e: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001f80: 2300 movs r3, #0 8001f82: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001f84: 2303 movs r3, #3 8001f86: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 8001f88: 2304 movs r3, #4 8001f8a: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(TMP_SCL_GPIO_Port, &GPIO_InitStruct); 8001f8c: f107 031c add.w r3, r7, #28 8001f90: 4619 mov r1, r3 8001f92: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8001f96: f001 f927 bl 80031e8 GPIO_InitStruct.Pin = TMP_SDA_Pin; 8001f9a: 2380 movs r3, #128 ; 0x80 8001f9c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8001f9e: 2312 movs r3, #18 8001fa0: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001fa2: 2300 movs r3, #0 8001fa4: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001fa6: 2303 movs r3, #3 8001fa8: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 8001faa: 2304 movs r3, #4 8001fac: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(TMP_SDA_GPIO_Port, &GPIO_InitStruct); 8001fae: f107 031c add.w r3, r7, #28 8001fb2: 4619 mov r1, r3 8001fb4: 4823 ldr r0, [pc, #140] ; (8002044 ) 8001fb6: f001 f917 bl 80031e8 /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8001fba: 4b21 ldr r3, [pc, #132] ; (8002040 ) 8001fbc: 69db ldr r3, [r3, #28] 8001fbe: 4a20 ldr r2, [pc, #128] ; (8002040 ) 8001fc0: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8001fc4: 61d3 str r3, [r2, #28] 8001fc6: 4b1e ldr r3, [pc, #120] ; (8002040 ) 8001fc8: 69db ldr r3, [r3, #28] 8001fca: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001fce: 613b str r3, [r7, #16] 8001fd0: 693b ldr r3, [r7, #16] /* USER CODE BEGIN I2C2_MspInit 1 */ /* USER CODE END I2C2_MspInit 1 */ } } 8001fd2: e02e b.n 8002032 else if(hi2c->Instance==I2C2) 8001fd4: 687b ldr r3, [r7, #4] 8001fd6: 681b ldr r3, [r3, #0] 8001fd8: 4a1b ldr r2, [pc, #108] ; (8002048 ) 8001fda: 4293 cmp r3, r2 8001fdc: d129 bne.n 8002032 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001fde: 4b18 ldr r3, [pc, #96] ; (8002040 ) 8001fe0: 695b ldr r3, [r3, #20] 8001fe2: 4a17 ldr r2, [pc, #92] ; (8002040 ) 8001fe4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001fe8: 6153 str r3, [r2, #20] 8001fea: 4b15 ldr r3, [pc, #84] ; (8002040 ) 8001fec: 695b ldr r3, [r3, #20] 8001fee: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001ff2: 60fb str r3, [r7, #12] 8001ff4: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 8001ff6: f44f 63c0 mov.w r3, #1536 ; 0x600 8001ffa: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8001ffc: 2312 movs r3, #18 8001ffe: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002000: 2300 movs r3, #0 8002002: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8002004: 2303 movs r3, #3 8002006: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; 8002008: 2304 movs r3, #4 800200a: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800200c: f107 031c add.w r3, r7, #28 8002010: 4619 mov r1, r3 8002012: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8002016: f001 f8e7 bl 80031e8 __HAL_RCC_I2C2_CLK_ENABLE(); 800201a: 4b09 ldr r3, [pc, #36] ; (8002040 ) 800201c: 69db ldr r3, [r3, #28] 800201e: 4a08 ldr r2, [pc, #32] ; (8002040 ) 8002020: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 8002024: 61d3 str r3, [r2, #28] 8002026: 4b06 ldr r3, [pc, #24] ; (8002040 ) 8002028: 69db ldr r3, [r3, #28] 800202a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 800202e: 60bb str r3, [r7, #8] 8002030: 68bb ldr r3, [r7, #8] } 8002032: bf00 nop 8002034: 3730 adds r7, #48 ; 0x30 8002036: 46bd mov sp, r7 8002038: bd80 pop {r7, pc} 800203a: bf00 nop 800203c: 40005400 .word 0x40005400 8002040: 40021000 .word 0x40021000 8002044: 48000400 .word 0x48000400 8002048: 40005800 .word 0x40005800 0800204c : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 800204c: b580 push {r7, lr} 800204e: b08a sub sp, #40 ; 0x28 8002050: af00 add r7, sp, #0 8002052: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002054: f107 0314 add.w r3, r7, #20 8002058: 2200 movs r2, #0 800205a: 601a str r2, [r3, #0] 800205c: 605a str r2, [r3, #4] 800205e: 609a str r2, [r3, #8] 8002060: 60da str r2, [r3, #12] 8002062: 611a str r2, [r3, #16] if(hspi->Instance==SPI1) 8002064: 687b ldr r3, [r7, #4] 8002066: 681b ldr r3, [r3, #0] 8002068: 4a17 ldr r2, [pc, #92] ; (80020c8 ) 800206a: 4293 cmp r3, r2 800206c: d128 bne.n 80020c0 { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 800206e: 4b17 ldr r3, [pc, #92] ; (80020cc ) 8002070: 699b ldr r3, [r3, #24] 8002072: 4a16 ldr r2, [pc, #88] ; (80020cc ) 8002074: f443 5380 orr.w r3, r3, #4096 ; 0x1000 8002078: 6193 str r3, [r2, #24] 800207a: 4b14 ldr r3, [pc, #80] ; (80020cc ) 800207c: 699b ldr r3, [r3, #24] 800207e: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002082: 613b str r3, [r7, #16] 8002084: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002086: 4b11 ldr r3, [pc, #68] ; (80020cc ) 8002088: 695b ldr r3, [r3, #20] 800208a: 4a10 ldr r2, [pc, #64] ; (80020cc ) 800208c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8002090: 6153 str r3, [r2, #20] 8002092: 4b0e ldr r3, [pc, #56] ; (80020cc ) 8002094: 695b ldr r3, [r3, #20] 8002096: f403 3300 and.w r3, r3, #131072 ; 0x20000 800209a: 60fb str r3, [r7, #12] 800209c: 68fb ldr r3, [r7, #12] /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 800209e: 23e0 movs r3, #224 ; 0xe0 80020a0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80020a2: 2302 movs r3, #2 80020a4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80020a6: 2300 movs r3, #0 80020a8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80020aa: 2303 movs r3, #3 80020ac: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; 80020ae: 2305 movs r3, #5 80020b0: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80020b2: f107 0314 add.w r3, r7, #20 80020b6: 4619 mov r1, r3 80020b8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 80020bc: f001 f894 bl 80031e8 /* USER CODE BEGIN SPI1_MspInit 1 */ /* USER CODE END SPI1_MspInit 1 */ } } 80020c0: bf00 nop 80020c2: 3728 adds r7, #40 ; 0x28 80020c4: 46bd mov sp, r7 80020c6: bd80 pop {r7, pc} 80020c8: 40013000 .word 0x40013000 80020cc: 40021000 .word 0x40021000 080020d0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80020d0: b480 push {r7} 80020d2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80020d4: e7fe b.n 80020d4 080020d6 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80020d6: b480 push {r7} 80020d8: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80020da: e7fe b.n 80020da 080020dc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80020dc: b480 push {r7} 80020de: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80020e0: e7fe b.n 80020e0 080020e2 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 80020e2: b480 push {r7} 80020e4: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80020e6: e7fe b.n 80020e6 080020e8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80020e8: b480 push {r7} 80020ea: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80020ec: e7fe b.n 80020ec 080020ee : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80020ee: b480 push {r7} 80020f0: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80020f2: bf00 nop 80020f4: 46bd mov sp, r7 80020f6: f85d 7b04 ldr.w r7, [sp], #4 80020fa: 4770 bx lr 080020fc : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80020fc: b480 push {r7} 80020fe: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002100: bf00 nop 8002102: 46bd mov sp, r7 8002104: f85d 7b04 ldr.w r7, [sp], #4 8002108: 4770 bx lr 0800210a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800210a: b480 push {r7} 800210c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800210e: bf00 nop 8002110: 46bd mov sp, r7 8002112: f85d 7b04 ldr.w r7, [sp], #4 8002116: 4770 bx lr 08002118 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002118: b580 push {r7, lr} 800211a: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800211c: f000 f88e bl 800223c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002120: bf00 nop 8002122: bd80 pop {r7, pc} 08002124 : /** * @brief This function handles USB low priority or CAN_RX0 interrupts. */ void USB_LP_CAN_RX0_IRQHandler(void) { 8002124: b580 push {r7, lr} 8002126: af00 add r7, sp, #0 /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan); 8002128: 4802 ldr r0, [pc, #8] ; (8002134 ) 800212a: f000 fd1c bl 8002b66 /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ } 800212e: bf00 nop 8002130: bd80 pop {r7, pc} 8002132: bf00 nop 8002134: 20000144 .word 0x20000144 08002138 : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 8002138: b480 push {r7} 800213a: af00 add r7, sp, #0 /* FPU settings --------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 800213c: 4b06 ldr r3, [pc, #24] ; (8002158 ) 800213e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8002142: 4a05 ldr r2, [pc, #20] ; (8002158 ) 8002144: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8002148: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 800214c: bf00 nop 800214e: 46bd mov sp, r7 8002150: f85d 7b04 ldr.w r7, [sp], #4 8002154: 4770 bx lr 8002156: bf00 nop 8002158: e000ed00 .word 0xe000ed00 0800215c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ 800215c: f8df d034 ldr.w sp, [pc, #52] ; 8002194 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002160: 480d ldr r0, [pc, #52] ; (8002198 ) ldr r1, =_edata 8002162: 490e ldr r1, [pc, #56] ; (800219c ) ldr r2, =_sidata 8002164: 4a0e ldr r2, [pc, #56] ; (80021a0 ) movs r3, #0 8002166: 2300 movs r3, #0 b LoopCopyDataInit 8002168: e002 b.n 8002170 0800216a : CopyDataInit: ldr r4, [r2, r3] 800216a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800216c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800216e: 3304 adds r3, #4 08002170 : LoopCopyDataInit: adds r4, r0, r3 8002170: 18c4 adds r4, r0, r3 cmp r4, r1 8002172: 428c cmp r4, r1 bcc CopyDataInit 8002174: d3f9 bcc.n 800216a /* Zero fill the bss segment. */ ldr r2, =_sbss 8002176: 4a0b ldr r2, [pc, #44] ; (80021a4 ) ldr r4, =_ebss 8002178: 4c0b ldr r4, [pc, #44] ; (80021a8 ) movs r3, #0 800217a: 2300 movs r3, #0 b LoopFillZerobss 800217c: e001 b.n 8002182 0800217e : FillZerobss: str r3, [r2] 800217e: 6013 str r3, [r2, #0] adds r2, r2, #4 8002180: 3204 adds r2, #4 08002182 : LoopFillZerobss: cmp r2, r4 8002182: 42a2 cmp r2, r4 bcc FillZerobss 8002184: d3fb bcc.n 800217e /* Call the clock system intitialization function.*/ bl SystemInit 8002186: f7ff ffd7 bl 8002138 /* Call static constructors */ bl __libc_init_array 800218a: f004 f971 bl 8006470 <__libc_init_array> /* Call the application's entry point.*/ bl main 800218e: f7ff fbc3 bl 8001918
08002192 : LoopForever: b LoopForever 8002192: e7fe b.n 8002192 ldr sp, =_estack /* Atollic update: set stack pointer */ 8002194: 2000a000 .word 0x2000a000 ldr r0, =_sdata 8002198: 20000000 .word 0x20000000 ldr r1, =_edata 800219c: 20000014 .word 0x20000014 ldr r2, =_sidata 80021a0: 08006518 .word 0x08006518 ldr r2, =_sbss 80021a4: 20000018 .word 0x20000018 ldr r4, =_ebss 80021a8: 20000270 .word 0x20000270 080021ac : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80021ac: e7fe b.n 80021ac ... 080021b0 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80021b0: b580 push {r7, lr} 80021b2: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80021b4: 4b08 ldr r3, [pc, #32] ; (80021d8 ) 80021b6: 681b ldr r3, [r3, #0] 80021b8: 4a07 ldr r2, [pc, #28] ; (80021d8 ) 80021ba: f043 0310 orr.w r3, r3, #16 80021be: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80021c0: 2003 movs r0, #3 80021c2: f000 ffcf bl 8003164 /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80021c6: 200f movs r0, #15 80021c8: f000 f808 bl 80021dc /* Init the low level hardware */ HAL_MspInit(); 80021cc: f7ff fe3a bl 8001e44 /* Return function status */ return HAL_OK; 80021d0: 2300 movs r3, #0 } 80021d2: 4618 mov r0, r3 80021d4: bd80 pop {r7, pc} 80021d6: bf00 nop 80021d8: 40022000 .word 0x40022000 080021dc : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80021dc: b580 push {r7, lr} 80021de: b082 sub sp, #8 80021e0: af00 add r7, sp, #0 80021e2: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80021e4: 4b12 ldr r3, [pc, #72] ; (8002230 ) 80021e6: 681a ldr r2, [r3, #0] 80021e8: 4b12 ldr r3, [pc, #72] ; (8002234 ) 80021ea: 781b ldrb r3, [r3, #0] 80021ec: 4619 mov r1, r3 80021ee: f44f 737a mov.w r3, #1000 ; 0x3e8 80021f2: fbb3 f3f1 udiv r3, r3, r1 80021f6: fbb2 f3f3 udiv r3, r2, r3 80021fa: 4618 mov r0, r3 80021fc: f000 ffe7 bl 80031ce 8002200: 4603 mov r3, r0 8002202: 2b00 cmp r3, #0 8002204: d001 beq.n 800220a { return HAL_ERROR; 8002206: 2301 movs r3, #1 8002208: e00e b.n 8002228 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800220a: 687b ldr r3, [r7, #4] 800220c: 2b0f cmp r3, #15 800220e: d80a bhi.n 8002226 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8002210: 2200 movs r2, #0 8002212: 6879 ldr r1, [r7, #4] 8002214: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8002218: f000 ffaf bl 800317a uwTickPrio = TickPriority; 800221c: 4a06 ldr r2, [pc, #24] ; (8002238 ) 800221e: 687b ldr r3, [r7, #4] 8002220: 6013 str r3, [r2, #0] else { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8002222: 2300 movs r3, #0 8002224: e000 b.n 8002228 return HAL_ERROR; 8002226: 2301 movs r3, #1 } 8002228: 4618 mov r0, r3 800222a: 3708 adds r7, #8 800222c: 46bd mov sp, r7 800222e: bd80 pop {r7, pc} 8002230: 20000008 .word 0x20000008 8002234: 20000010 .word 0x20000010 8002238: 2000000c .word 0x2000000c 0800223c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800223c: b480 push {r7} 800223e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8002240: 4b06 ldr r3, [pc, #24] ; (800225c ) 8002242: 781b ldrb r3, [r3, #0] 8002244: 461a mov r2, r3 8002246: 4b06 ldr r3, [pc, #24] ; (8002260 ) 8002248: 681b ldr r3, [r3, #0] 800224a: 4413 add r3, r2 800224c: 4a04 ldr r2, [pc, #16] ; (8002260 ) 800224e: 6013 str r3, [r2, #0] } 8002250: bf00 nop 8002252: 46bd mov sp, r7 8002254: f85d 7b04 ldr.w r7, [sp], #4 8002258: 4770 bx lr 800225a: bf00 nop 800225c: 20000010 .word 0x20000010 8002260: 2000026c .word 0x2000026c 08002264 : * @note The function is declared as __Weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002264: b480 push {r7} 8002266: af00 add r7, sp, #0 return uwTick; 8002268: 4b03 ldr r3, [pc, #12] ; (8002278 ) 800226a: 681b ldr r3, [r3, #0] } 800226c: 4618 mov r0, r3 800226e: 46bd mov sp, r7 8002270: f85d 7b04 ldr.w r7, [sp], #4 8002274: 4770 bx lr 8002276: bf00 nop 8002278: 2000026c .word 0x2000026c 0800227c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800227c: b580 push {r7, lr} 800227e: b084 sub sp, #16 8002280: af00 add r7, sp, #0 8002282: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8002284: f7ff ffee bl 8002264 8002288: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800228a: 687b ldr r3, [r7, #4] 800228c: 60fb str r3, [r7, #12] /* Add freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800228e: 68fb ldr r3, [r7, #12] 8002290: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8002294: d005 beq.n 80022a2 { wait += (uint32_t)(uwTickFreq); 8002296: 4b0a ldr r3, [pc, #40] ; (80022c0 ) 8002298: 781b ldrb r3, [r3, #0] 800229a: 461a mov r2, r3 800229c: 68fb ldr r3, [r7, #12] 800229e: 4413 add r3, r2 80022a0: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 80022a2: bf00 nop 80022a4: f7ff ffde bl 8002264 80022a8: 4602 mov r2, r0 80022aa: 68bb ldr r3, [r7, #8] 80022ac: 1ad3 subs r3, r2, r3 80022ae: 68fa ldr r2, [r7, #12] 80022b0: 429a cmp r2, r3 80022b2: d8f7 bhi.n 80022a4 { } } 80022b4: bf00 nop 80022b6: bf00 nop 80022b8: 3710 adds r7, #16 80022ba: 46bd mov sp, r7 80022bc: bd80 pop {r7, pc} 80022be: bf00 nop 80022c0: 20000010 .word 0x20000010 080022c4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 80022c4: b580 push {r7, lr} 80022c6: b084 sub sp, #16 80022c8: af00 add r7, sp, #0 80022ca: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 80022cc: 687b ldr r3, [r7, #4] 80022ce: 2b00 cmp r3, #0 80022d0: d101 bne.n 80022d6 { return HAL_ERROR; 80022d2: 2301 movs r3, #1 80022d4: e0ed b.n 80024b2 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 80022d6: 687b ldr r3, [r7, #4] 80022d8: f893 3020 ldrb.w r3, [r3, #32] 80022dc: b2db uxtb r3, r3 80022de: 2b00 cmp r3, #0 80022e0: d102 bne.n 80022e8 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 80022e2: 6878 ldr r0, [r7, #4] 80022e4: f7ff fdd2 bl 8001e8c } #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 80022e8: 687b ldr r3, [r7, #4] 80022ea: 681b ldr r3, [r3, #0] 80022ec: 681a ldr r2, [r3, #0] 80022ee: 687b ldr r3, [r7, #4] 80022f0: 681b ldr r3, [r3, #0] 80022f2: f042 0201 orr.w r2, r2, #1 80022f6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80022f8: f7ff ffb4 bl 8002264 80022fc: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 80022fe: e012 b.n 8002326 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8002300: f7ff ffb0 bl 8002264 8002304: 4602 mov r2, r0 8002306: 68fb ldr r3, [r7, #12] 8002308: 1ad3 subs r3, r2, r3 800230a: 2b0a cmp r3, #10 800230c: d90b bls.n 8002326 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800230e: 687b ldr r3, [r7, #4] 8002310: 6a5b ldr r3, [r3, #36] ; 0x24 8002312: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8002316: 687b ldr r3, [r7, #4] 8002318: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800231a: 687b ldr r3, [r7, #4] 800231c: 2205 movs r2, #5 800231e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8002322: 2301 movs r3, #1 8002324: e0c5 b.n 80024b2 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8002326: 687b ldr r3, [r7, #4] 8002328: 681b ldr r3, [r3, #0] 800232a: 685b ldr r3, [r3, #4] 800232c: f003 0301 and.w r3, r3, #1 8002330: 2b00 cmp r3, #0 8002332: d0e5 beq.n 8002300 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 8002334: 687b ldr r3, [r7, #4] 8002336: 681b ldr r3, [r3, #0] 8002338: 681a ldr r2, [r3, #0] 800233a: 687b ldr r3, [r7, #4] 800233c: 681b ldr r3, [r3, #0] 800233e: f022 0202 bic.w r2, r2, #2 8002342: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8002344: f7ff ff8e bl 8002264 8002348: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800234a: e012 b.n 8002372 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800234c: f7ff ff8a bl 8002264 8002350: 4602 mov r2, r0 8002352: 68fb ldr r3, [r7, #12] 8002354: 1ad3 subs r3, r2, r3 8002356: 2b0a cmp r3, #10 8002358: d90b bls.n 8002372 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800235a: 687b ldr r3, [r7, #4] 800235c: 6a5b ldr r3, [r3, #36] ; 0x24 800235e: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8002362: 687b ldr r3, [r7, #4] 8002364: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8002366: 687b ldr r3, [r7, #4] 8002368: 2205 movs r2, #5 800236a: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800236e: 2301 movs r3, #1 8002370: e09f b.n 80024b2 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 8002372: 687b ldr r3, [r7, #4] 8002374: 681b ldr r3, [r3, #0] 8002376: 685b ldr r3, [r3, #4] 8002378: f003 0302 and.w r3, r3, #2 800237c: 2b00 cmp r3, #0 800237e: d1e5 bne.n 800234c } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 8002380: 687b ldr r3, [r7, #4] 8002382: 7e1b ldrb r3, [r3, #24] 8002384: 2b01 cmp r3, #1 8002386: d108 bne.n 800239a { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 8002388: 687b ldr r3, [r7, #4] 800238a: 681b ldr r3, [r3, #0] 800238c: 681a ldr r2, [r3, #0] 800238e: 687b ldr r3, [r7, #4] 8002390: 681b ldr r3, [r3, #0] 8002392: f042 0280 orr.w r2, r2, #128 ; 0x80 8002396: 601a str r2, [r3, #0] 8002398: e007 b.n 80023aa } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800239a: 687b ldr r3, [r7, #4] 800239c: 681b ldr r3, [r3, #0] 800239e: 681a ldr r2, [r3, #0] 80023a0: 687b ldr r3, [r7, #4] 80023a2: 681b ldr r3, [r3, #0] 80023a4: f022 0280 bic.w r2, r2, #128 ; 0x80 80023a8: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 80023aa: 687b ldr r3, [r7, #4] 80023ac: 7e5b ldrb r3, [r3, #25] 80023ae: 2b01 cmp r3, #1 80023b0: d108 bne.n 80023c4 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 80023b2: 687b ldr r3, [r7, #4] 80023b4: 681b ldr r3, [r3, #0] 80023b6: 681a ldr r2, [r3, #0] 80023b8: 687b ldr r3, [r7, #4] 80023ba: 681b ldr r3, [r3, #0] 80023bc: f042 0240 orr.w r2, r2, #64 ; 0x40 80023c0: 601a str r2, [r3, #0] 80023c2: e007 b.n 80023d4 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 80023c4: 687b ldr r3, [r7, #4] 80023c6: 681b ldr r3, [r3, #0] 80023c8: 681a ldr r2, [r3, #0] 80023ca: 687b ldr r3, [r7, #4] 80023cc: 681b ldr r3, [r3, #0] 80023ce: f022 0240 bic.w r2, r2, #64 ; 0x40 80023d2: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 80023d4: 687b ldr r3, [r7, #4] 80023d6: 7e9b ldrb r3, [r3, #26] 80023d8: 2b01 cmp r3, #1 80023da: d108 bne.n 80023ee { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 80023dc: 687b ldr r3, [r7, #4] 80023de: 681b ldr r3, [r3, #0] 80023e0: 681a ldr r2, [r3, #0] 80023e2: 687b ldr r3, [r7, #4] 80023e4: 681b ldr r3, [r3, #0] 80023e6: f042 0220 orr.w r2, r2, #32 80023ea: 601a str r2, [r3, #0] 80023ec: e007 b.n 80023fe } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 80023ee: 687b ldr r3, [r7, #4] 80023f0: 681b ldr r3, [r3, #0] 80023f2: 681a ldr r2, [r3, #0] 80023f4: 687b ldr r3, [r7, #4] 80023f6: 681b ldr r3, [r3, #0] 80023f8: f022 0220 bic.w r2, r2, #32 80023fc: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 80023fe: 687b ldr r3, [r7, #4] 8002400: 7edb ldrb r3, [r3, #27] 8002402: 2b01 cmp r3, #1 8002404: d108 bne.n 8002418 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8002406: 687b ldr r3, [r7, #4] 8002408: 681b ldr r3, [r3, #0] 800240a: 681a ldr r2, [r3, #0] 800240c: 687b ldr r3, [r7, #4] 800240e: 681b ldr r3, [r3, #0] 8002410: f022 0210 bic.w r2, r2, #16 8002414: 601a str r2, [r3, #0] 8002416: e007 b.n 8002428 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8002418: 687b ldr r3, [r7, #4] 800241a: 681b ldr r3, [r3, #0] 800241c: 681a ldr r2, [r3, #0] 800241e: 687b ldr r3, [r7, #4] 8002420: 681b ldr r3, [r3, #0] 8002422: f042 0210 orr.w r2, r2, #16 8002426: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 8002428: 687b ldr r3, [r7, #4] 800242a: 7f1b ldrb r3, [r3, #28] 800242c: 2b01 cmp r3, #1 800242e: d108 bne.n 8002442 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8002430: 687b ldr r3, [r7, #4] 8002432: 681b ldr r3, [r3, #0] 8002434: 681a ldr r2, [r3, #0] 8002436: 687b ldr r3, [r7, #4] 8002438: 681b ldr r3, [r3, #0] 800243a: f042 0208 orr.w r2, r2, #8 800243e: 601a str r2, [r3, #0] 8002440: e007 b.n 8002452 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8002442: 687b ldr r3, [r7, #4] 8002444: 681b ldr r3, [r3, #0] 8002446: 681a ldr r2, [r3, #0] 8002448: 687b ldr r3, [r7, #4] 800244a: 681b ldr r3, [r3, #0] 800244c: f022 0208 bic.w r2, r2, #8 8002450: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 8002452: 687b ldr r3, [r7, #4] 8002454: 7f5b ldrb r3, [r3, #29] 8002456: 2b01 cmp r3, #1 8002458: d108 bne.n 800246c { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800245a: 687b ldr r3, [r7, #4] 800245c: 681b ldr r3, [r3, #0] 800245e: 681a ldr r2, [r3, #0] 8002460: 687b ldr r3, [r7, #4] 8002462: 681b ldr r3, [r3, #0] 8002464: f042 0204 orr.w r2, r2, #4 8002468: 601a str r2, [r3, #0] 800246a: e007 b.n 800247c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800246c: 687b ldr r3, [r7, #4] 800246e: 681b ldr r3, [r3, #0] 8002470: 681a ldr r2, [r3, #0] 8002472: 687b ldr r3, [r7, #4] 8002474: 681b ldr r3, [r3, #0] 8002476: f022 0204 bic.w r2, r2, #4 800247a: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800247c: 687b ldr r3, [r7, #4] 800247e: 689a ldr r2, [r3, #8] 8002480: 687b ldr r3, [r7, #4] 8002482: 68db ldr r3, [r3, #12] 8002484: 431a orrs r2, r3 8002486: 687b ldr r3, [r7, #4] 8002488: 691b ldr r3, [r3, #16] 800248a: 431a orrs r2, r3 800248c: 687b ldr r3, [r7, #4] 800248e: 695b ldr r3, [r3, #20] 8002490: ea42 0103 orr.w r1, r2, r3 8002494: 687b ldr r3, [r7, #4] 8002496: 685b ldr r3, [r3, #4] 8002498: 1e5a subs r2, r3, #1 800249a: 687b ldr r3, [r7, #4] 800249c: 681b ldr r3, [r3, #0] 800249e: 430a orrs r2, r1 80024a0: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 80024a2: 687b ldr r3, [r7, #4] 80024a4: 2200 movs r2, #0 80024a6: 625a str r2, [r3, #36] ; 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 80024a8: 687b ldr r3, [r7, #4] 80024aa: 2201 movs r2, #1 80024ac: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 80024b0: 2300 movs r3, #0 } 80024b2: 4618 mov r0, r3 80024b4: 3710 adds r7, #16 80024b6: 46bd mov sp, r7 80024b8: bd80 pop {r7, pc} 080024ba : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { 80024ba: b480 push {r7} 80024bc: b087 sub sp, #28 80024be: af00 add r7, sp, #0 80024c0: 6078 str r0, [r7, #4] 80024c2: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 80024c4: 687b ldr r3, [r7, #4] 80024c6: 681b ldr r3, [r3, #0] 80024c8: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 80024ca: 687b ldr r3, [r7, #4] 80024cc: f893 3020 ldrb.w r3, [r3, #32] 80024d0: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 80024d2: 7cfb ldrb r3, [r7, #19] 80024d4: 2b01 cmp r3, #1 80024d6: d003 beq.n 80024e0 80024d8: 7cfb ldrb r3, [r7, #19] 80024da: 2b02 cmp r3, #2 80024dc: f040 80aa bne.w 8002634 /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 80024e0: 697b ldr r3, [r7, #20] 80024e2: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 80024e6: f043 0201 orr.w r2, r3, #1 80024ea: 697b ldr r3, [r7, #20] 80024ec: f8c3 2200 str.w r2, [r3, #512] ; 0x200 /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 80024f0: 683b ldr r3, [r7, #0] 80024f2: 695b ldr r3, [r3, #20] 80024f4: f003 031f and.w r3, r3, #31 80024f8: 2201 movs r2, #1 80024fa: fa02 f303 lsl.w r3, r2, r3 80024fe: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 8002500: 697b ldr r3, [r7, #20] 8002502: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c 8002506: 68fb ldr r3, [r7, #12] 8002508: 43db mvns r3, r3 800250a: 401a ands r2, r3 800250c: 697b ldr r3, [r7, #20] 800250e: f8c3 221c str.w r2, [r3, #540] ; 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 8002512: 683b ldr r3, [r7, #0] 8002514: 69db ldr r3, [r3, #28] 8002516: 2b00 cmp r3, #0 8002518: d123 bne.n 8002562 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800251a: 697b ldr r3, [r7, #20] 800251c: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c 8002520: 68fb ldr r3, [r7, #12] 8002522: 43db mvns r3, r3 8002524: 401a ands r2, r3 8002526: 697b ldr r3, [r7, #20] 8002528: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800252c: 683b ldr r3, [r7, #0] 800252e: 68db ldr r3, [r3, #12] 8002530: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 8002532: 683b ldr r3, [r7, #0] 8002534: 685b ldr r3, [r3, #4] 8002536: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8002538: 683a ldr r2, [r7, #0] 800253a: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800253c: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800253e: 697b ldr r3, [r7, #20] 8002540: 3248 adds r2, #72 ; 0x48 8002542: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8002546: 683b ldr r3, [r7, #0] 8002548: 689b ldr r3, [r3, #8] 800254a: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800254c: 683b ldr r3, [r7, #0] 800254e: 681b ldr r3, [r3, #0] 8002550: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8002552: 683b ldr r3, [r7, #0] 8002554: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8002556: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8002558: 6979 ldr r1, [r7, #20] 800255a: 3348 adds r3, #72 ; 0x48 800255c: 00db lsls r3, r3, #3 800255e: 440b add r3, r1 8002560: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 8002562: 683b ldr r3, [r7, #0] 8002564: 69db ldr r3, [r3, #28] 8002566: 2b01 cmp r3, #1 8002568: d122 bne.n 80025b0 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800256a: 697b ldr r3, [r7, #20] 800256c: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c 8002570: 68fb ldr r3, [r7, #12] 8002572: 431a orrs r2, r3 8002574: 697b ldr r3, [r7, #20] 8002576: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800257a: 683b ldr r3, [r7, #0] 800257c: 681b ldr r3, [r3, #0] 800257e: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 8002580: 683b ldr r3, [r7, #0] 8002582: 685b ldr r3, [r3, #4] 8002584: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8002586: 683a ldr r2, [r7, #0] 8002588: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800258a: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800258c: 697b ldr r3, [r7, #20] 800258e: 3248 adds r2, #72 ; 0x48 8002590: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8002594: 683b ldr r3, [r7, #0] 8002596: 689b ldr r3, [r3, #8] 8002598: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800259a: 683b ldr r3, [r7, #0] 800259c: 68db ldr r3, [r3, #12] 800259e: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 80025a0: 683b ldr r3, [r7, #0] 80025a2: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80025a4: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 80025a6: 6979 ldr r1, [r7, #20] 80025a8: 3348 adds r3, #72 ; 0x48 80025aa: 00db lsls r3, r3, #3 80025ac: 440b add r3, r1 80025ae: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 80025b0: 683b ldr r3, [r7, #0] 80025b2: 699b ldr r3, [r3, #24] 80025b4: 2b00 cmp r3, #0 80025b6: d109 bne.n 80025cc { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 80025b8: 697b ldr r3, [r7, #20] 80025ba: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 80025be: 68fb ldr r3, [r7, #12] 80025c0: 43db mvns r3, r3 80025c2: 401a ands r2, r3 80025c4: 697b ldr r3, [r7, #20] 80025c6: f8c3 2204 str.w r2, [r3, #516] ; 0x204 80025ca: e007 b.n 80025dc } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 80025cc: 697b ldr r3, [r7, #20] 80025ce: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 80025d2: 68fb ldr r3, [r7, #12] 80025d4: 431a orrs r2, r3 80025d6: 697b ldr r3, [r7, #20] 80025d8: f8c3 2204 str.w r2, [r3, #516] ; 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 80025dc: 683b ldr r3, [r7, #0] 80025de: 691b ldr r3, [r3, #16] 80025e0: 2b00 cmp r3, #0 80025e2: d109 bne.n 80025f8 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 80025e4: 697b ldr r3, [r7, #20] 80025e6: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214 80025ea: 68fb ldr r3, [r7, #12] 80025ec: 43db mvns r3, r3 80025ee: 401a ands r2, r3 80025f0: 697b ldr r3, [r7, #20] 80025f2: f8c3 2214 str.w r2, [r3, #532] ; 0x214 80025f6: e007 b.n 8002608 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 80025f8: 697b ldr r3, [r7, #20] 80025fa: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214 80025fe: 68fb ldr r3, [r7, #12] 8002600: 431a orrs r2, r3 8002602: 697b ldr r3, [r7, #20] 8002604: f8c3 2214 str.w r2, [r3, #532] ; 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 8002608: 683b ldr r3, [r7, #0] 800260a: 6a1b ldr r3, [r3, #32] 800260c: 2b01 cmp r3, #1 800260e: d107 bne.n 8002620 { SET_BIT(can_ip->FA1R, filternbrbitpos); 8002610: 697b ldr r3, [r7, #20] 8002612: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c 8002616: 68fb ldr r3, [r7, #12] 8002618: 431a orrs r2, r3 800261a: 697b ldr r3, [r7, #20] 800261c: f8c3 221c str.w r2, [r3, #540] ; 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 8002620: 697b ldr r3, [r7, #20] 8002622: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8002626: f023 0201 bic.w r2, r3, #1 800262a: 697b ldr r3, [r7, #20] 800262c: f8c3 2200 str.w r2, [r3, #512] ; 0x200 /* Return function status */ return HAL_OK; 8002630: 2300 movs r3, #0 8002632: e006 b.n 8002642 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8002634: 687b ldr r3, [r7, #4] 8002636: 6a5b ldr r3, [r3, #36] ; 0x24 8002638: f443 2280 orr.w r2, r3, #262144 ; 0x40000 800263c: 687b ldr r3, [r7, #4] 800263e: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002640: 2301 movs r3, #1 } } 8002642: 4618 mov r0, r3 8002644: 371c adds r7, #28 8002646: 46bd mov sp, r7 8002648: f85d 7b04 ldr.w r7, [sp], #4 800264c: 4770 bx lr 0800264e : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800264e: b580 push {r7, lr} 8002650: b084 sub sp, #16 8002652: af00 add r7, sp, #0 8002654: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 8002656: 687b ldr r3, [r7, #4] 8002658: f893 3020 ldrb.w r3, [r3, #32] 800265c: b2db uxtb r3, r3 800265e: 2b01 cmp r3, #1 8002660: d12e bne.n 80026c0 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 8002662: 687b ldr r3, [r7, #4] 8002664: 2202 movs r2, #2 8002666: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800266a: 687b ldr r3, [r7, #4] 800266c: 681b ldr r3, [r3, #0] 800266e: 681a ldr r2, [r3, #0] 8002670: 687b ldr r3, [r7, #4] 8002672: 681b ldr r3, [r3, #0] 8002674: f022 0201 bic.w r2, r2, #1 8002678: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800267a: f7ff fdf3 bl 8002264 800267e: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 8002680: e012 b.n 80026a8 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8002682: f7ff fdef bl 8002264 8002686: 4602 mov r2, r0 8002688: 68fb ldr r3, [r7, #12] 800268a: 1ad3 subs r3, r2, r3 800268c: 2b0a cmp r3, #10 800268e: d90b bls.n 80026a8 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8002690: 687b ldr r3, [r7, #4] 8002692: 6a5b ldr r3, [r3, #36] ; 0x24 8002694: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8002698: 687b ldr r3, [r7, #4] 800269a: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800269c: 687b ldr r3, [r7, #4] 800269e: 2205 movs r2, #5 80026a0: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 80026a4: 2301 movs r3, #1 80026a6: e012 b.n 80026ce while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 80026a8: 687b ldr r3, [r7, #4] 80026aa: 681b ldr r3, [r3, #0] 80026ac: 685b ldr r3, [r3, #4] 80026ae: f003 0301 and.w r3, r3, #1 80026b2: 2b00 cmp r3, #0 80026b4: d1e5 bne.n 8002682 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 80026b6: 687b ldr r3, [r7, #4] 80026b8: 2200 movs r2, #0 80026ba: 625a str r2, [r3, #36] ; 0x24 /* Return function status */ return HAL_OK; 80026bc: 2300 movs r3, #0 80026be: e006 b.n 80026ce } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 80026c0: 687b ldr r3, [r7, #4] 80026c2: 6a5b ldr r3, [r3, #36] ; 0x24 80026c4: f443 2200 orr.w r2, r3, #524288 ; 0x80000 80026c8: 687b ldr r3, [r7, #4] 80026ca: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 80026cc: 2301 movs r3, #1 } } 80026ce: 4618 mov r0, r3 80026d0: 3710 adds r7, #16 80026d2: 46bd mov sp, r7 80026d4: bd80 pop {r7, pc} 080026d6 : * the TxMailbox used to store the Tx message. * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { 80026d6: b480 push {r7} 80026d8: b089 sub sp, #36 ; 0x24 80026da: af00 add r7, sp, #0 80026dc: 60f8 str r0, [r7, #12] 80026de: 60b9 str r1, [r7, #8] 80026e0: 607a str r2, [r7, #4] 80026e2: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 80026e4: 68fb ldr r3, [r7, #12] 80026e6: f893 3020 ldrb.w r3, [r3, #32] 80026ea: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 80026ec: 68fb ldr r3, [r7, #12] 80026ee: 681b ldr r3, [r3, #0] 80026f0: 689b ldr r3, [r3, #8] 80026f2: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 80026f4: 7ffb ldrb r3, [r7, #31] 80026f6: 2b01 cmp r3, #1 80026f8: d003 beq.n 8002702 80026fa: 7ffb ldrb r3, [r7, #31] 80026fc: 2b02 cmp r3, #2 80026fe: f040 80b8 bne.w 8002872 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 8002702: 69bb ldr r3, [r7, #24] 8002704: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8002708: 2b00 cmp r3, #0 800270a: d10a bne.n 8002722 ((tsr & CAN_TSR_TME1) != 0U) || 800270c: 69bb ldr r3, [r7, #24] 800270e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 8002712: 2b00 cmp r3, #0 8002714: d105 bne.n 8002722 ((tsr & CAN_TSR_TME2) != 0U)) 8002716: 69bb ldr r3, [r7, #24] 8002718: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800271c: 2b00 cmp r3, #0 800271e: f000 80a0 beq.w 8002862 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 8002722: 69bb ldr r3, [r7, #24] 8002724: 0e1b lsrs r3, r3, #24 8002726: f003 0303 and.w r3, r3, #3 800272a: 617b str r3, [r7, #20] /* Check transmit mailbox value */ if (transmitmailbox > 2U) 800272c: 697b ldr r3, [r7, #20] 800272e: 2b02 cmp r3, #2 8002730: d907 bls.n 8002742 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; 8002732: 68fb ldr r3, [r7, #12] 8002734: 6a5b ldr r3, [r3, #36] ; 0x24 8002736: f443 0200 orr.w r2, r3, #8388608 ; 0x800000 800273a: 68fb ldr r3, [r7, #12] 800273c: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 800273e: 2301 movs r3, #1 8002740: e09e b.n 8002880 } /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 8002742: 2201 movs r2, #1 8002744: 697b ldr r3, [r7, #20] 8002746: 409a lsls r2, r3 8002748: 683b ldr r3, [r7, #0] 800274a: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800274c: 68bb ldr r3, [r7, #8] 800274e: 689b ldr r3, [r3, #8] 8002750: 2b00 cmp r3, #0 8002752: d10d bne.n 8002770 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8002754: 68bb ldr r3, [r7, #8] 8002756: 681b ldr r3, [r3, #0] 8002758: 055a lsls r2, r3, #21 pHeader->RTR); 800275a: 68bb ldr r3, [r7, #8] 800275c: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800275e: 68f9 ldr r1, [r7, #12] 8002760: 6809 ldr r1, [r1, #0] 8002762: 431a orrs r2, r3 8002764: 697b ldr r3, [r7, #20] 8002766: 3318 adds r3, #24 8002768: 011b lsls r3, r3, #4 800276a: 440b add r3, r1 800276c: 601a str r2, [r3, #0] 800276e: e00f b.n 8002790 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8002770: 68bb ldr r3, [r7, #8] 8002772: 685b ldr r3, [r3, #4] 8002774: 00da lsls r2, r3, #3 pHeader->IDE | 8002776: 68bb ldr r3, [r7, #8] 8002778: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800277a: 431a orrs r2, r3 pHeader->RTR); 800277c: 68bb ldr r3, [r7, #8] 800277e: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8002780: 68f9 ldr r1, [r7, #12] 8002782: 6809 ldr r1, [r1, #0] pHeader->IDE | 8002784: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8002786: 697b ldr r3, [r7, #20] 8002788: 3318 adds r3, #24 800278a: 011b lsls r3, r3, #4 800278c: 440b add r3, r1 800278e: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 8002790: 68fb ldr r3, [r7, #12] 8002792: 6819 ldr r1, [r3, #0] 8002794: 68bb ldr r3, [r7, #8] 8002796: 691a ldr r2, [r3, #16] 8002798: 697b ldr r3, [r7, #20] 800279a: 3318 adds r3, #24 800279c: 011b lsls r3, r3, #4 800279e: 440b add r3, r1 80027a0: 3304 adds r3, #4 80027a2: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 80027a4: 68bb ldr r3, [r7, #8] 80027a6: 7d1b ldrb r3, [r3, #20] 80027a8: 2b01 cmp r3, #1 80027aa: d111 bne.n 80027d0 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 80027ac: 68fb ldr r3, [r7, #12] 80027ae: 681a ldr r2, [r3, #0] 80027b0: 697b ldr r3, [r7, #20] 80027b2: 3318 adds r3, #24 80027b4: 011b lsls r3, r3, #4 80027b6: 4413 add r3, r2 80027b8: 3304 adds r3, #4 80027ba: 681b ldr r3, [r3, #0] 80027bc: 68fa ldr r2, [r7, #12] 80027be: 6811 ldr r1, [r2, #0] 80027c0: f443 7280 orr.w r2, r3, #256 ; 0x100 80027c4: 697b ldr r3, [r7, #20] 80027c6: 3318 adds r3, #24 80027c8: 011b lsls r3, r3, #4 80027ca: 440b add r3, r1 80027cc: 3304 adds r3, #4 80027ce: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 80027d0: 687b ldr r3, [r7, #4] 80027d2: 3307 adds r3, #7 80027d4: 781b ldrb r3, [r3, #0] 80027d6: 061a lsls r2, r3, #24 80027d8: 687b ldr r3, [r7, #4] 80027da: 3306 adds r3, #6 80027dc: 781b ldrb r3, [r3, #0] 80027de: 041b lsls r3, r3, #16 80027e0: 431a orrs r2, r3 80027e2: 687b ldr r3, [r7, #4] 80027e4: 3305 adds r3, #5 80027e6: 781b ldrb r3, [r3, #0] 80027e8: 021b lsls r3, r3, #8 80027ea: 4313 orrs r3, r2 80027ec: 687a ldr r2, [r7, #4] 80027ee: 3204 adds r2, #4 80027f0: 7812 ldrb r2, [r2, #0] 80027f2: 4610 mov r0, r2 80027f4: 68fa ldr r2, [r7, #12] 80027f6: 6811 ldr r1, [r2, #0] 80027f8: ea43 0200 orr.w r2, r3, r0 80027fc: 697b ldr r3, [r7, #20] 80027fe: 011b lsls r3, r3, #4 8002800: 440b add r3, r1 8002802: f503 73c6 add.w r3, r3, #396 ; 0x18c 8002806: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 8002808: 687b ldr r3, [r7, #4] 800280a: 3303 adds r3, #3 800280c: 781b ldrb r3, [r3, #0] 800280e: 061a lsls r2, r3, #24 8002810: 687b ldr r3, [r7, #4] 8002812: 3302 adds r3, #2 8002814: 781b ldrb r3, [r3, #0] 8002816: 041b lsls r3, r3, #16 8002818: 431a orrs r2, r3 800281a: 687b ldr r3, [r7, #4] 800281c: 3301 adds r3, #1 800281e: 781b ldrb r3, [r3, #0] 8002820: 021b lsls r3, r3, #8 8002822: 4313 orrs r3, r2 8002824: 687a ldr r2, [r7, #4] 8002826: 7812 ldrb r2, [r2, #0] 8002828: 4610 mov r0, r2 800282a: 68fa ldr r2, [r7, #12] 800282c: 6811 ldr r1, [r2, #0] 800282e: ea43 0200 orr.w r2, r3, r0 8002832: 697b ldr r3, [r7, #20] 8002834: 011b lsls r3, r3, #4 8002836: 440b add r3, r1 8002838: f503 73c4 add.w r3, r3, #392 ; 0x188 800283c: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800283e: 68fb ldr r3, [r7, #12] 8002840: 681a ldr r2, [r3, #0] 8002842: 697b ldr r3, [r7, #20] 8002844: 3318 adds r3, #24 8002846: 011b lsls r3, r3, #4 8002848: 4413 add r3, r2 800284a: 681b ldr r3, [r3, #0] 800284c: 68fa ldr r2, [r7, #12] 800284e: 6811 ldr r1, [r2, #0] 8002850: f043 0201 orr.w r2, r3, #1 8002854: 697b ldr r3, [r7, #20] 8002856: 3318 adds r3, #24 8002858: 011b lsls r3, r3, #4 800285a: 440b add r3, r1 800285c: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800285e: 2300 movs r3, #0 8002860: e00e b.n 8002880 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8002862: 68fb ldr r3, [r7, #12] 8002864: 6a5b ldr r3, [r3, #36] ; 0x24 8002866: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 800286a: 68fb ldr r3, [r7, #12] 800286c: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 800286e: 2301 movs r3, #1 8002870: e006 b.n 8002880 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8002872: 68fb ldr r3, [r7, #12] 8002874: 6a5b ldr r3, [r3, #36] ; 0x24 8002876: f443 2280 orr.w r2, r3, #262144 ; 0x40000 800287a: 68fb ldr r3, [r7, #12] 800287c: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 800287e: 2301 movs r3, #1 } } 8002880: 4618 mov r0, r3 8002882: 3724 adds r7, #36 ; 0x24 8002884: 46bd mov sp, r7 8002886: f85d 7b04 ldr.w r7, [sp], #4 800288a: 4770 bx lr 0800288c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) { 800288c: b480 push {r7} 800288e: b085 sub sp, #20 8002890: af00 add r7, sp, #0 8002892: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 8002894: 2300 movs r3, #0 8002896: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 8002898: 687b ldr r3, [r7, #4] 800289a: f893 3020 ldrb.w r3, [r3, #32] 800289e: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 80028a0: 7afb ldrb r3, [r7, #11] 80028a2: 2b01 cmp r3, #1 80028a4: d002 beq.n 80028ac 80028a6: 7afb ldrb r3, [r7, #11] 80028a8: 2b02 cmp r3, #2 80028aa: d11d bne.n 80028e8 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 80028ac: 687b ldr r3, [r7, #4] 80028ae: 681b ldr r3, [r3, #0] 80028b0: 689b ldr r3, [r3, #8] 80028b2: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 80028b6: 2b00 cmp r3, #0 80028b8: d002 beq.n 80028c0 { freelevel++; 80028ba: 68fb ldr r3, [r7, #12] 80028bc: 3301 adds r3, #1 80028be: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 80028c0: 687b ldr r3, [r7, #4] 80028c2: 681b ldr r3, [r3, #0] 80028c4: 689b ldr r3, [r3, #8] 80028c6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80028ca: 2b00 cmp r3, #0 80028cc: d002 beq.n 80028d4 { freelevel++; 80028ce: 68fb ldr r3, [r7, #12] 80028d0: 3301 adds r3, #1 80028d2: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 80028d4: 687b ldr r3, [r7, #4] 80028d6: 681b ldr r3, [r3, #0] 80028d8: 689b ldr r3, [r3, #8] 80028da: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80028de: 2b00 cmp r3, #0 80028e0: d002 beq.n 80028e8 { freelevel++; 80028e2: 68fb ldr r3, [r7, #12] 80028e4: 3301 adds r3, #1 80028e6: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 80028e8: 68fb ldr r3, [r7, #12] } 80028ea: 4618 mov r0, r3 80028ec: 3714 adds r7, #20 80028ee: 46bd mov sp, r7 80028f0: f85d 7b04 ldr.w r7, [sp], #4 80028f4: 4770 bx lr 080028f6 : * of the Rx frame will be stored. * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 80028f6: b480 push {r7} 80028f8: b087 sub sp, #28 80028fa: af00 add r7, sp, #0 80028fc: 60f8 str r0, [r7, #12] 80028fe: 60b9 str r1, [r7, #8] 8002900: 607a str r2, [r7, #4] 8002902: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8002904: 68fb ldr r3, [r7, #12] 8002906: f893 3020 ldrb.w r3, [r3, #32] 800290a: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800290c: 7dfb ldrb r3, [r7, #23] 800290e: 2b01 cmp r3, #1 8002910: d003 beq.n 800291a 8002912: 7dfb ldrb r3, [r7, #23] 8002914: 2b02 cmp r3, #2 8002916: f040 80f3 bne.w 8002b00 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800291a: 68bb ldr r3, [r7, #8] 800291c: 2b00 cmp r3, #0 800291e: d10e bne.n 800293e { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 8002920: 68fb ldr r3, [r7, #12] 8002922: 681b ldr r3, [r3, #0] 8002924: 68db ldr r3, [r3, #12] 8002926: f003 0303 and.w r3, r3, #3 800292a: 2b00 cmp r3, #0 800292c: d116 bne.n 800295c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800292e: 68fb ldr r3, [r7, #12] 8002930: 6a5b ldr r3, [r3, #36] ; 0x24 8002932: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 8002936: 68fb ldr r3, [r7, #12] 8002938: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 800293a: 2301 movs r3, #1 800293c: e0e7 b.n 8002b0e } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800293e: 68fb ldr r3, [r7, #12] 8002940: 681b ldr r3, [r3, #0] 8002942: 691b ldr r3, [r3, #16] 8002944: f003 0303 and.w r3, r3, #3 8002948: 2b00 cmp r3, #0 800294a: d107 bne.n 800295c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800294c: 68fb ldr r3, [r7, #12] 800294e: 6a5b ldr r3, [r3, #36] ; 0x24 8002950: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 8002954: 68fb ldr r3, [r7, #12] 8002956: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002958: 2301 movs r3, #1 800295a: e0d8 b.n 8002b0e } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800295c: 68fb ldr r3, [r7, #12] 800295e: 681a ldr r2, [r3, #0] 8002960: 68bb ldr r3, [r7, #8] 8002962: 331b adds r3, #27 8002964: 011b lsls r3, r3, #4 8002966: 4413 add r3, r2 8002968: 681b ldr r3, [r3, #0] 800296a: f003 0204 and.w r2, r3, #4 800296e: 687b ldr r3, [r7, #4] 8002970: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 8002972: 687b ldr r3, [r7, #4] 8002974: 689b ldr r3, [r3, #8] 8002976: 2b00 cmp r3, #0 8002978: d10c bne.n 8002994 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800297a: 68fb ldr r3, [r7, #12] 800297c: 681a ldr r2, [r3, #0] 800297e: 68bb ldr r3, [r7, #8] 8002980: 331b adds r3, #27 8002982: 011b lsls r3, r3, #4 8002984: 4413 add r3, r2 8002986: 681b ldr r3, [r3, #0] 8002988: 0d5b lsrs r3, r3, #21 800298a: f3c3 020a ubfx r2, r3, #0, #11 800298e: 687b ldr r3, [r7, #4] 8002990: 601a str r2, [r3, #0] 8002992: e00b b.n 80029ac } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 8002994: 68fb ldr r3, [r7, #12] 8002996: 681a ldr r2, [r3, #0] 8002998: 68bb ldr r3, [r7, #8] 800299a: 331b adds r3, #27 800299c: 011b lsls r3, r3, #4 800299e: 4413 add r3, r2 80029a0: 681b ldr r3, [r3, #0] 80029a2: 08db lsrs r3, r3, #3 80029a4: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000 80029a8: 687b ldr r3, [r7, #4] 80029aa: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 80029ac: 68fb ldr r3, [r7, #12] 80029ae: 681a ldr r2, [r3, #0] 80029b0: 68bb ldr r3, [r7, #8] 80029b2: 331b adds r3, #27 80029b4: 011b lsls r3, r3, #4 80029b6: 4413 add r3, r2 80029b8: 681b ldr r3, [r3, #0] 80029ba: f003 0202 and.w r2, r3, #2 80029be: 687b ldr r3, [r7, #4] 80029c0: 60da str r2, [r3, #12] pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 80029c2: 68fb ldr r3, [r7, #12] 80029c4: 681a ldr r2, [r3, #0] 80029c6: 68bb ldr r3, [r7, #8] 80029c8: 331b adds r3, #27 80029ca: 011b lsls r3, r3, #4 80029cc: 4413 add r3, r2 80029ce: 3304 adds r3, #4 80029d0: 681b ldr r3, [r3, #0] 80029d2: f003 020f and.w r2, r3, #15 80029d6: 687b ldr r3, [r7, #4] 80029d8: 611a str r2, [r3, #16] pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 80029da: 68fb ldr r3, [r7, #12] 80029dc: 681a ldr r2, [r3, #0] 80029de: 68bb ldr r3, [r7, #8] 80029e0: 331b adds r3, #27 80029e2: 011b lsls r3, r3, #4 80029e4: 4413 add r3, r2 80029e6: 3304 adds r3, #4 80029e8: 681b ldr r3, [r3, #0] 80029ea: 0a1b lsrs r3, r3, #8 80029ec: b2da uxtb r2, r3 80029ee: 687b ldr r3, [r7, #4] 80029f0: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 80029f2: 68fb ldr r3, [r7, #12] 80029f4: 681a ldr r2, [r3, #0] 80029f6: 68bb ldr r3, [r7, #8] 80029f8: 331b adds r3, #27 80029fa: 011b lsls r3, r3, #4 80029fc: 4413 add r3, r2 80029fe: 3304 adds r3, #4 8002a00: 681b ldr r3, [r3, #0] 8002a02: 0c1b lsrs r3, r3, #16 8002a04: b29a uxth r2, r3 8002a06: 687b ldr r3, [r7, #4] 8002a08: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 8002a0a: 68fb ldr r3, [r7, #12] 8002a0c: 681a ldr r2, [r3, #0] 8002a0e: 68bb ldr r3, [r7, #8] 8002a10: 011b lsls r3, r3, #4 8002a12: 4413 add r3, r2 8002a14: f503 73dc add.w r3, r3, #440 ; 0x1b8 8002a18: 681b ldr r3, [r3, #0] 8002a1a: b2da uxtb r2, r3 8002a1c: 683b ldr r3, [r7, #0] 8002a1e: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 8002a20: 68fb ldr r3, [r7, #12] 8002a22: 681a ldr r2, [r3, #0] 8002a24: 68bb ldr r3, [r7, #8] 8002a26: 011b lsls r3, r3, #4 8002a28: 4413 add r3, r2 8002a2a: f503 73dc add.w r3, r3, #440 ; 0x1b8 8002a2e: 681b ldr r3, [r3, #0] 8002a30: 0a1a lsrs r2, r3, #8 8002a32: 683b ldr r3, [r7, #0] 8002a34: 3301 adds r3, #1 8002a36: b2d2 uxtb r2, r2 8002a38: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 8002a3a: 68fb ldr r3, [r7, #12] 8002a3c: 681a ldr r2, [r3, #0] 8002a3e: 68bb ldr r3, [r7, #8] 8002a40: 011b lsls r3, r3, #4 8002a42: 4413 add r3, r2 8002a44: f503 73dc add.w r3, r3, #440 ; 0x1b8 8002a48: 681b ldr r3, [r3, #0] 8002a4a: 0c1a lsrs r2, r3, #16 8002a4c: 683b ldr r3, [r7, #0] 8002a4e: 3302 adds r3, #2 8002a50: b2d2 uxtb r2, r2 8002a52: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 8002a54: 68fb ldr r3, [r7, #12] 8002a56: 681a ldr r2, [r3, #0] 8002a58: 68bb ldr r3, [r7, #8] 8002a5a: 011b lsls r3, r3, #4 8002a5c: 4413 add r3, r2 8002a5e: f503 73dc add.w r3, r3, #440 ; 0x1b8 8002a62: 681b ldr r3, [r3, #0] 8002a64: 0e1a lsrs r2, r3, #24 8002a66: 683b ldr r3, [r7, #0] 8002a68: 3303 adds r3, #3 8002a6a: b2d2 uxtb r2, r2 8002a6c: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 8002a6e: 68fb ldr r3, [r7, #12] 8002a70: 681a ldr r2, [r3, #0] 8002a72: 68bb ldr r3, [r7, #8] 8002a74: 011b lsls r3, r3, #4 8002a76: 4413 add r3, r2 8002a78: f503 73de add.w r3, r3, #444 ; 0x1bc 8002a7c: 681a ldr r2, [r3, #0] 8002a7e: 683b ldr r3, [r7, #0] 8002a80: 3304 adds r3, #4 8002a82: b2d2 uxtb r2, r2 8002a84: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 8002a86: 68fb ldr r3, [r7, #12] 8002a88: 681a ldr r2, [r3, #0] 8002a8a: 68bb ldr r3, [r7, #8] 8002a8c: 011b lsls r3, r3, #4 8002a8e: 4413 add r3, r2 8002a90: f503 73de add.w r3, r3, #444 ; 0x1bc 8002a94: 681b ldr r3, [r3, #0] 8002a96: 0a1a lsrs r2, r3, #8 8002a98: 683b ldr r3, [r7, #0] 8002a9a: 3305 adds r3, #5 8002a9c: b2d2 uxtb r2, r2 8002a9e: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 8002aa0: 68fb ldr r3, [r7, #12] 8002aa2: 681a ldr r2, [r3, #0] 8002aa4: 68bb ldr r3, [r7, #8] 8002aa6: 011b lsls r3, r3, #4 8002aa8: 4413 add r3, r2 8002aaa: f503 73de add.w r3, r3, #444 ; 0x1bc 8002aae: 681b ldr r3, [r3, #0] 8002ab0: 0c1a lsrs r2, r3, #16 8002ab2: 683b ldr r3, [r7, #0] 8002ab4: 3306 adds r3, #6 8002ab6: b2d2 uxtb r2, r2 8002ab8: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 8002aba: 68fb ldr r3, [r7, #12] 8002abc: 681a ldr r2, [r3, #0] 8002abe: 68bb ldr r3, [r7, #8] 8002ac0: 011b lsls r3, r3, #4 8002ac2: 4413 add r3, r2 8002ac4: f503 73de add.w r3, r3, #444 ; 0x1bc 8002ac8: 681b ldr r3, [r3, #0] 8002aca: 0e1a lsrs r2, r3, #24 8002acc: 683b ldr r3, [r7, #0] 8002ace: 3307 adds r3, #7 8002ad0: b2d2 uxtb r2, r2 8002ad2: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 8002ad4: 68bb ldr r3, [r7, #8] 8002ad6: 2b00 cmp r3, #0 8002ad8: d108 bne.n 8002aec { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 8002ada: 68fb ldr r3, [r7, #12] 8002adc: 681b ldr r3, [r3, #0] 8002ade: 68da ldr r2, [r3, #12] 8002ae0: 68fb ldr r3, [r7, #12] 8002ae2: 681b ldr r3, [r3, #0] 8002ae4: f042 0220 orr.w r2, r2, #32 8002ae8: 60da str r2, [r3, #12] 8002aea: e007 b.n 8002afc } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 8002aec: 68fb ldr r3, [r7, #12] 8002aee: 681b ldr r3, [r3, #0] 8002af0: 691a ldr r2, [r3, #16] 8002af2: 68fb ldr r3, [r7, #12] 8002af4: 681b ldr r3, [r3, #0] 8002af6: f042 0220 orr.w r2, r2, #32 8002afa: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 8002afc: 2300 movs r3, #0 8002afe: e006 b.n 8002b0e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8002b00: 68fb ldr r3, [r7, #12] 8002b02: 6a5b ldr r3, [r3, #36] ; 0x24 8002b04: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8002b08: 68fb ldr r3, [r7, #12] 8002b0a: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002b0c: 2301 movs r3, #1 } } 8002b0e: 4618 mov r0, r3 8002b10: 371c adds r7, #28 8002b12: 46bd mov sp, r7 8002b14: f85d 7b04 ldr.w r7, [sp], #4 8002b18: 4770 bx lr 08002b1a : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 8002b1a: b480 push {r7} 8002b1c: b085 sub sp, #20 8002b1e: af00 add r7, sp, #0 8002b20: 6078 str r0, [r7, #4] 8002b22: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8002b24: 687b ldr r3, [r7, #4] 8002b26: f893 3020 ldrb.w r3, [r3, #32] 8002b2a: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 8002b2c: 7bfb ldrb r3, [r7, #15] 8002b2e: 2b01 cmp r3, #1 8002b30: d002 beq.n 8002b38 8002b32: 7bfb ldrb r3, [r7, #15] 8002b34: 2b02 cmp r3, #2 8002b36: d109 bne.n 8002b4c (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 8002b38: 687b ldr r3, [r7, #4] 8002b3a: 681b ldr r3, [r3, #0] 8002b3c: 6959 ldr r1, [r3, #20] 8002b3e: 687b ldr r3, [r7, #4] 8002b40: 681b ldr r3, [r3, #0] 8002b42: 683a ldr r2, [r7, #0] 8002b44: 430a orrs r2, r1 8002b46: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 8002b48: 2300 movs r3, #0 8002b4a: e006 b.n 8002b5a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8002b4c: 687b ldr r3, [r7, #4] 8002b4e: 6a5b ldr r3, [r3, #36] ; 0x24 8002b50: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8002b54: 687b ldr r3, [r7, #4] 8002b56: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002b58: 2301 movs r3, #1 } } 8002b5a: 4618 mov r0, r3 8002b5c: 3714 adds r7, #20 8002b5e: 46bd mov sp, r7 8002b60: f85d 7b04 ldr.w r7, [sp], #4 8002b64: 4770 bx lr 08002b66 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 8002b66: b580 push {r7, lr} 8002b68: b08a sub sp, #40 ; 0x28 8002b6a: af00 add r7, sp, #0 8002b6c: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 8002b6e: 2300 movs r3, #0 8002b70: 627b str r3, [r7, #36] ; 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 8002b72: 687b ldr r3, [r7, #4] 8002b74: 681b ldr r3, [r3, #0] 8002b76: 695b ldr r3, [r3, #20] 8002b78: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 8002b7a: 687b ldr r3, [r7, #4] 8002b7c: 681b ldr r3, [r3, #0] 8002b7e: 685b ldr r3, [r3, #4] 8002b80: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 8002b82: 687b ldr r3, [r7, #4] 8002b84: 681b ldr r3, [r3, #0] 8002b86: 689b ldr r3, [r3, #8] 8002b88: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 8002b8a: 687b ldr r3, [r7, #4] 8002b8c: 681b ldr r3, [r3, #0] 8002b8e: 68db ldr r3, [r3, #12] 8002b90: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 8002b92: 687b ldr r3, [r7, #4] 8002b94: 681b ldr r3, [r3, #0] 8002b96: 691b ldr r3, [r3, #16] 8002b98: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 8002b9a: 687b ldr r3, [r7, #4] 8002b9c: 681b ldr r3, [r3, #0] 8002b9e: 699b ldr r3, [r3, #24] 8002ba0: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 8002ba2: 6a3b ldr r3, [r7, #32] 8002ba4: f003 0301 and.w r3, r3, #1 8002ba8: 2b00 cmp r3, #0 8002baa: d07c beq.n 8002ca6 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 8002bac: 69bb ldr r3, [r7, #24] 8002bae: f003 0301 and.w r3, r3, #1 8002bb2: 2b00 cmp r3, #0 8002bb4: d023 beq.n 8002bfe { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 8002bb6: 687b ldr r3, [r7, #4] 8002bb8: 681b ldr r3, [r3, #0] 8002bba: 2201 movs r2, #1 8002bbc: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 8002bbe: 69bb ldr r3, [r7, #24] 8002bc0: f003 0302 and.w r3, r3, #2 8002bc4: 2b00 cmp r3, #0 8002bc6: d003 beq.n 8002bd0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 8002bc8: 6878 ldr r0, [r7, #4] 8002bca: f000 f983 bl 8002ed4 8002bce: e016 b.n 8002bfe #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 8002bd0: 69bb ldr r3, [r7, #24] 8002bd2: f003 0304 and.w r3, r3, #4 8002bd6: 2b00 cmp r3, #0 8002bd8: d004 beq.n 8002be4 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 8002bda: 6a7b ldr r3, [r7, #36] ; 0x24 8002bdc: f443 6300 orr.w r3, r3, #2048 ; 0x800 8002be0: 627b str r3, [r7, #36] ; 0x24 8002be2: e00c b.n 8002bfe } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 8002be4: 69bb ldr r3, [r7, #24] 8002be6: f003 0308 and.w r3, r3, #8 8002bea: 2b00 cmp r3, #0 8002bec: d004 beq.n 8002bf8 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 8002bee: 6a7b ldr r3, [r7, #36] ; 0x24 8002bf0: f443 5380 orr.w r3, r3, #4096 ; 0x1000 8002bf4: 627b str r3, [r7, #36] ; 0x24 8002bf6: e002 b.n 8002bfe #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 8002bf8: 6878 ldr r0, [r7, #4] 8002bfa: f000 f989 bl 8002f10 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 8002bfe: 69bb ldr r3, [r7, #24] 8002c00: f403 7380 and.w r3, r3, #256 ; 0x100 8002c04: 2b00 cmp r3, #0 8002c06: d024 beq.n 8002c52 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 8002c08: 687b ldr r3, [r7, #4] 8002c0a: 681b ldr r3, [r3, #0] 8002c0c: f44f 7280 mov.w r2, #256 ; 0x100 8002c10: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 8002c12: 69bb ldr r3, [r7, #24] 8002c14: f403 7300 and.w r3, r3, #512 ; 0x200 8002c18: 2b00 cmp r3, #0 8002c1a: d003 beq.n 8002c24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 8002c1c: 6878 ldr r0, [r7, #4] 8002c1e: f000 f963 bl 8002ee8 8002c22: e016 b.n 8002c52 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 8002c24: 69bb ldr r3, [r7, #24] 8002c26: f403 6380 and.w r3, r3, #1024 ; 0x400 8002c2a: 2b00 cmp r3, #0 8002c2c: d004 beq.n 8002c38 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 8002c2e: 6a7b ldr r3, [r7, #36] ; 0x24 8002c30: f443 5300 orr.w r3, r3, #8192 ; 0x2000 8002c34: 627b str r3, [r7, #36] ; 0x24 8002c36: e00c b.n 8002c52 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 8002c38: 69bb ldr r3, [r7, #24] 8002c3a: f403 6300 and.w r3, r3, #2048 ; 0x800 8002c3e: 2b00 cmp r3, #0 8002c40: d004 beq.n 8002c4c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 8002c42: 6a7b ldr r3, [r7, #36] ; 0x24 8002c44: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8002c48: 627b str r3, [r7, #36] ; 0x24 8002c4a: e002 b.n 8002c52 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 8002c4c: 6878 ldr r0, [r7, #4] 8002c4e: f000 f969 bl 8002f24 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 8002c52: 69bb ldr r3, [r7, #24] 8002c54: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002c58: 2b00 cmp r3, #0 8002c5a: d024 beq.n 8002ca6 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 8002c5c: 687b ldr r3, [r7, #4] 8002c5e: 681b ldr r3, [r3, #0] 8002c60: f44f 3280 mov.w r2, #65536 ; 0x10000 8002c64: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 8002c66: 69bb ldr r3, [r7, #24] 8002c68: f403 3300 and.w r3, r3, #131072 ; 0x20000 8002c6c: 2b00 cmp r3, #0 8002c6e: d003 beq.n 8002c78 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 8002c70: 6878 ldr r0, [r7, #4] 8002c72: f000 f943 bl 8002efc 8002c76: e016 b.n 8002ca6 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 8002c78: 69bb ldr r3, [r7, #24] 8002c7a: f403 2380 and.w r3, r3, #262144 ; 0x40000 8002c7e: 2b00 cmp r3, #0 8002c80: d004 beq.n 8002c8c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 8002c82: 6a7b ldr r3, [r7, #36] ; 0x24 8002c84: f443 4300 orr.w r3, r3, #32768 ; 0x8000 8002c88: 627b str r3, [r7, #36] ; 0x24 8002c8a: e00c b.n 8002ca6 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 8002c8c: 69bb ldr r3, [r7, #24] 8002c8e: f403 2300 and.w r3, r3, #524288 ; 0x80000 8002c92: 2b00 cmp r3, #0 8002c94: d004 beq.n 8002ca0 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 8002c96: 6a7b ldr r3, [r7, #36] ; 0x24 8002c98: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8002c9c: 627b str r3, [r7, #36] ; 0x24 8002c9e: e002 b.n 8002ca6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 8002ca0: 6878 ldr r0, [r7, #4] 8002ca2: f000 f949 bl 8002f38 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 8002ca6: 6a3b ldr r3, [r7, #32] 8002ca8: f003 0308 and.w r3, r3, #8 8002cac: 2b00 cmp r3, #0 8002cae: d00c beq.n 8002cca { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 8002cb0: 697b ldr r3, [r7, #20] 8002cb2: f003 0310 and.w r3, r3, #16 8002cb6: 2b00 cmp r3, #0 8002cb8: d007 beq.n 8002cca { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 8002cba: 6a7b ldr r3, [r7, #36] ; 0x24 8002cbc: f443 7300 orr.w r3, r3, #512 ; 0x200 8002cc0: 627b str r3, [r7, #36] ; 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 8002cc2: 687b ldr r3, [r7, #4] 8002cc4: 681b ldr r3, [r3, #0] 8002cc6: 2210 movs r2, #16 8002cc8: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 8002cca: 6a3b ldr r3, [r7, #32] 8002ccc: f003 0304 and.w r3, r3, #4 8002cd0: 2b00 cmp r3, #0 8002cd2: d00b beq.n 8002cec { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 8002cd4: 697b ldr r3, [r7, #20] 8002cd6: f003 0308 and.w r3, r3, #8 8002cda: 2b00 cmp r3, #0 8002cdc: d006 beq.n 8002cec { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 8002cde: 687b ldr r3, [r7, #4] 8002ce0: 681b ldr r3, [r3, #0] 8002ce2: 2208 movs r2, #8 8002ce4: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 8002ce6: 6878 ldr r0, [r7, #4] 8002ce8: f000 f930 bl 8002f4c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 8002cec: 6a3b ldr r3, [r7, #32] 8002cee: f003 0302 and.w r3, r3, #2 8002cf2: 2b00 cmp r3, #0 8002cf4: d009 beq.n 8002d0a { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 8002cf6: 687b ldr r3, [r7, #4] 8002cf8: 681b ldr r3, [r3, #0] 8002cfa: 68db ldr r3, [r3, #12] 8002cfc: f003 0303 and.w r3, r3, #3 8002d00: 2b00 cmp r3, #0 8002d02: d002 beq.n 8002d0a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 8002d04: 6878 ldr r0, [r7, #4] 8002d06: f7fe f9e5 bl 80010d4 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 8002d0a: 6a3b ldr r3, [r7, #32] 8002d0c: f003 0340 and.w r3, r3, #64 ; 0x40 8002d10: 2b00 cmp r3, #0 8002d12: d00c beq.n 8002d2e { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 8002d14: 693b ldr r3, [r7, #16] 8002d16: f003 0310 and.w r3, r3, #16 8002d1a: 2b00 cmp r3, #0 8002d1c: d007 beq.n 8002d2e { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 8002d1e: 6a7b ldr r3, [r7, #36] ; 0x24 8002d20: f443 6380 orr.w r3, r3, #1024 ; 0x400 8002d24: 627b str r3, [r7, #36] ; 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 8002d26: 687b ldr r3, [r7, #4] 8002d28: 681b ldr r3, [r3, #0] 8002d2a: 2210 movs r2, #16 8002d2c: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 8002d2e: 6a3b ldr r3, [r7, #32] 8002d30: f003 0320 and.w r3, r3, #32 8002d34: 2b00 cmp r3, #0 8002d36: d00b beq.n 8002d50 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 8002d38: 693b ldr r3, [r7, #16] 8002d3a: f003 0308 and.w r3, r3, #8 8002d3e: 2b00 cmp r3, #0 8002d40: d006 beq.n 8002d50 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 8002d42: 687b ldr r3, [r7, #4] 8002d44: 681b ldr r3, [r3, #0] 8002d46: 2208 movs r2, #8 8002d48: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 8002d4a: 6878 ldr r0, [r7, #4] 8002d4c: f000 f912 bl 8002f74 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 8002d50: 6a3b ldr r3, [r7, #32] 8002d52: f003 0310 and.w r3, r3, #16 8002d56: 2b00 cmp r3, #0 8002d58: d009 beq.n 8002d6e { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 8002d5a: 687b ldr r3, [r7, #4] 8002d5c: 681b ldr r3, [r3, #0] 8002d5e: 691b ldr r3, [r3, #16] 8002d60: f003 0303 and.w r3, r3, #3 8002d64: 2b00 cmp r3, #0 8002d66: d002 beq.n 8002d6e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 8002d68: 6878 ldr r0, [r7, #4] 8002d6a: f000 f8f9 bl 8002f60 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 8002d6e: 6a3b ldr r3, [r7, #32] 8002d70: f403 3300 and.w r3, r3, #131072 ; 0x20000 8002d74: 2b00 cmp r3, #0 8002d76: d00b beq.n 8002d90 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 8002d78: 69fb ldr r3, [r7, #28] 8002d7a: f003 0310 and.w r3, r3, #16 8002d7e: 2b00 cmp r3, #0 8002d80: d006 beq.n 8002d90 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 8002d82: 687b ldr r3, [r7, #4] 8002d84: 681b ldr r3, [r3, #0] 8002d86: 2210 movs r2, #16 8002d88: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 8002d8a: 6878 ldr r0, [r7, #4] 8002d8c: f000 f8fc bl 8002f88 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 8002d90: 6a3b ldr r3, [r7, #32] 8002d92: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002d96: 2b00 cmp r3, #0 8002d98: d00b beq.n 8002db2 { if ((msrflags & CAN_MSR_WKUI) != 0U) 8002d9a: 69fb ldr r3, [r7, #28] 8002d9c: f003 0308 and.w r3, r3, #8 8002da0: 2b00 cmp r3, #0 8002da2: d006 beq.n 8002db2 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 8002da4: 687b ldr r3, [r7, #4] 8002da6: 681b ldr r3, [r3, #0] 8002da8: 2208 movs r2, #8 8002daa: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 8002dac: 6878 ldr r0, [r7, #4] 8002dae: f000 f8f5 bl 8002f9c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 8002db2: 6a3b ldr r3, [r7, #32] 8002db4: f403 4300 and.w r3, r3, #32768 ; 0x8000 8002db8: 2b00 cmp r3, #0 8002dba: d07b beq.n 8002eb4 { if ((msrflags & CAN_MSR_ERRI) != 0U) 8002dbc: 69fb ldr r3, [r7, #28] 8002dbe: f003 0304 and.w r3, r3, #4 8002dc2: 2b00 cmp r3, #0 8002dc4: d072 beq.n 8002eac { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 8002dc6: 6a3b ldr r3, [r7, #32] 8002dc8: f403 7380 and.w r3, r3, #256 ; 0x100 8002dcc: 2b00 cmp r3, #0 8002dce: d008 beq.n 8002de2 ((esrflags & CAN_ESR_EWGF) != 0U)) 8002dd0: 68fb ldr r3, [r7, #12] 8002dd2: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 8002dd6: 2b00 cmp r3, #0 8002dd8: d003 beq.n 8002de2 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 8002dda: 6a7b ldr r3, [r7, #36] ; 0x24 8002ddc: f043 0301 orr.w r3, r3, #1 8002de0: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 8002de2: 6a3b ldr r3, [r7, #32] 8002de4: f403 7300 and.w r3, r3, #512 ; 0x200 8002de8: 2b00 cmp r3, #0 8002dea: d008 beq.n 8002dfe ((esrflags & CAN_ESR_EPVF) != 0U)) 8002dec: 68fb ldr r3, [r7, #12] 8002dee: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 8002df2: 2b00 cmp r3, #0 8002df4: d003 beq.n 8002dfe { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 8002df6: 6a7b ldr r3, [r7, #36] ; 0x24 8002df8: f043 0302 orr.w r3, r3, #2 8002dfc: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 8002dfe: 6a3b ldr r3, [r7, #32] 8002e00: f403 6380 and.w r3, r3, #1024 ; 0x400 8002e04: 2b00 cmp r3, #0 8002e06: d008 beq.n 8002e1a ((esrflags & CAN_ESR_BOFF) != 0U)) 8002e08: 68fb ldr r3, [r7, #12] 8002e0a: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 8002e0e: 2b00 cmp r3, #0 8002e10: d003 beq.n 8002e1a { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 8002e12: 6a7b ldr r3, [r7, #36] ; 0x24 8002e14: f043 0304 orr.w r3, r3, #4 8002e18: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 8002e1a: 6a3b ldr r3, [r7, #32] 8002e1c: f403 6300 and.w r3, r3, #2048 ; 0x800 8002e20: 2b00 cmp r3, #0 8002e22: d043 beq.n 8002eac ((esrflags & CAN_ESR_LEC) != 0U)) 8002e24: 68fb ldr r3, [r7, #12] 8002e26: f003 0370 and.w r3, r3, #112 ; 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 8002e2a: 2b00 cmp r3, #0 8002e2c: d03e beq.n 8002eac { switch (esrflags & CAN_ESR_LEC) 8002e2e: 68fb ldr r3, [r7, #12] 8002e30: f003 0370 and.w r3, r3, #112 ; 0x70 8002e34: 2b60 cmp r3, #96 ; 0x60 8002e36: d02b beq.n 8002e90 8002e38: 2b60 cmp r3, #96 ; 0x60 8002e3a: d82e bhi.n 8002e9a 8002e3c: 2b50 cmp r3, #80 ; 0x50 8002e3e: d022 beq.n 8002e86 8002e40: 2b50 cmp r3, #80 ; 0x50 8002e42: d82a bhi.n 8002e9a 8002e44: 2b40 cmp r3, #64 ; 0x40 8002e46: d019 beq.n 8002e7c 8002e48: 2b40 cmp r3, #64 ; 0x40 8002e4a: d826 bhi.n 8002e9a 8002e4c: 2b30 cmp r3, #48 ; 0x30 8002e4e: d010 beq.n 8002e72 8002e50: 2b30 cmp r3, #48 ; 0x30 8002e52: d822 bhi.n 8002e9a 8002e54: 2b10 cmp r3, #16 8002e56: d002 beq.n 8002e5e 8002e58: 2b20 cmp r3, #32 8002e5a: d005 beq.n 8002e68 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 8002e5c: e01d b.n 8002e9a errorcode |= HAL_CAN_ERROR_STF; 8002e5e: 6a7b ldr r3, [r7, #36] ; 0x24 8002e60: f043 0308 orr.w r3, r3, #8 8002e64: 627b str r3, [r7, #36] ; 0x24 break; 8002e66: e019 b.n 8002e9c errorcode |= HAL_CAN_ERROR_FOR; 8002e68: 6a7b ldr r3, [r7, #36] ; 0x24 8002e6a: f043 0310 orr.w r3, r3, #16 8002e6e: 627b str r3, [r7, #36] ; 0x24 break; 8002e70: e014 b.n 8002e9c errorcode |= HAL_CAN_ERROR_ACK; 8002e72: 6a7b ldr r3, [r7, #36] ; 0x24 8002e74: f043 0320 orr.w r3, r3, #32 8002e78: 627b str r3, [r7, #36] ; 0x24 break; 8002e7a: e00f b.n 8002e9c errorcode |= HAL_CAN_ERROR_BR; 8002e7c: 6a7b ldr r3, [r7, #36] ; 0x24 8002e7e: f043 0340 orr.w r3, r3, #64 ; 0x40 8002e82: 627b str r3, [r7, #36] ; 0x24 break; 8002e84: e00a b.n 8002e9c errorcode |= HAL_CAN_ERROR_BD; 8002e86: 6a7b ldr r3, [r7, #36] ; 0x24 8002e88: f043 0380 orr.w r3, r3, #128 ; 0x80 8002e8c: 627b str r3, [r7, #36] ; 0x24 break; 8002e8e: e005 b.n 8002e9c errorcode |= HAL_CAN_ERROR_CRC; 8002e90: 6a7b ldr r3, [r7, #36] ; 0x24 8002e92: f443 7380 orr.w r3, r3, #256 ; 0x100 8002e96: 627b str r3, [r7, #36] ; 0x24 break; 8002e98: e000 b.n 8002e9c break; 8002e9a: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 8002e9c: 687b ldr r3, [r7, #4] 8002e9e: 681b ldr r3, [r3, #0] 8002ea0: 699a ldr r2, [r3, #24] 8002ea2: 687b ldr r3, [r7, #4] 8002ea4: 681b ldr r3, [r3, #0] 8002ea6: f022 0270 bic.w r2, r2, #112 ; 0x70 8002eaa: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 8002eac: 687b ldr r3, [r7, #4] 8002eae: 681b ldr r3, [r3, #0] 8002eb0: 2204 movs r2, #4 8002eb2: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 8002eb4: 6a7b ldr r3, [r7, #36] ; 0x24 8002eb6: 2b00 cmp r3, #0 8002eb8: d008 beq.n 8002ecc { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 8002eba: 687b ldr r3, [r7, #4] 8002ebc: 6a5a ldr r2, [r3, #36] ; 0x24 8002ebe: 6a7b ldr r3, [r7, #36] ; 0x24 8002ec0: 431a orrs r2, r3 8002ec2: 687b ldr r3, [r7, #4] 8002ec4: 625a str r2, [r3, #36] ; 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 8002ec6: 6878 ldr r0, [r7, #4] 8002ec8: f000 f872 bl 8002fb0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 8002ecc: bf00 nop 8002ece: 3728 adds r7, #40 ; 0x28 8002ed0: 46bd mov sp, r7 8002ed2: bd80 pop {r7, pc} 08002ed4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 8002ed4: b480 push {r7} 8002ed6: b083 sub sp, #12 8002ed8: af00 add r7, sp, #0 8002eda: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 8002edc: bf00 nop 8002ede: 370c adds r7, #12 8002ee0: 46bd mov sp, r7 8002ee2: f85d 7b04 ldr.w r7, [sp], #4 8002ee6: 4770 bx lr 08002ee8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 8002ee8: b480 push {r7} 8002eea: b083 sub sp, #12 8002eec: af00 add r7, sp, #0 8002eee: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 8002ef0: bf00 nop 8002ef2: 370c adds r7, #12 8002ef4: 46bd mov sp, r7 8002ef6: f85d 7b04 ldr.w r7, [sp], #4 8002efa: 4770 bx lr 08002efc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 8002efc: b480 push {r7} 8002efe: b083 sub sp, #12 8002f00: af00 add r7, sp, #0 8002f02: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 8002f04: bf00 nop 8002f06: 370c adds r7, #12 8002f08: 46bd mov sp, r7 8002f0a: f85d 7b04 ldr.w r7, [sp], #4 8002f0e: 4770 bx lr 08002f10 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 8002f10: b480 push {r7} 8002f12: b083 sub sp, #12 8002f14: af00 add r7, sp, #0 8002f16: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 8002f18: bf00 nop 8002f1a: 370c adds r7, #12 8002f1c: 46bd mov sp, r7 8002f1e: f85d 7b04 ldr.w r7, [sp], #4 8002f22: 4770 bx lr 08002f24 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 8002f24: b480 push {r7} 8002f26: b083 sub sp, #12 8002f28: af00 add r7, sp, #0 8002f2a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 8002f2c: bf00 nop 8002f2e: 370c adds r7, #12 8002f30: 46bd mov sp, r7 8002f32: f85d 7b04 ldr.w r7, [sp], #4 8002f36: 4770 bx lr 08002f38 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 8002f38: b480 push {r7} 8002f3a: b083 sub sp, #12 8002f3c: af00 add r7, sp, #0 8002f3e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 8002f40: bf00 nop 8002f42: 370c adds r7, #12 8002f44: 46bd mov sp, r7 8002f46: f85d 7b04 ldr.w r7, [sp], #4 8002f4a: 4770 bx lr 08002f4c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 8002f4c: b480 push {r7} 8002f4e: b083 sub sp, #12 8002f50: af00 add r7, sp, #0 8002f52: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 8002f54: bf00 nop 8002f56: 370c adds r7, #12 8002f58: 46bd mov sp, r7 8002f5a: f85d 7b04 ldr.w r7, [sp], #4 8002f5e: 4770 bx lr 08002f60 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) { 8002f60: b480 push {r7} 8002f62: b083 sub sp, #12 8002f64: af00 add r7, sp, #0 8002f66: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the user file */ } 8002f68: bf00 nop 8002f6a: 370c adds r7, #12 8002f6c: 46bd mov sp, r7 8002f6e: f85d 7b04 ldr.w r7, [sp], #4 8002f72: 4770 bx lr 08002f74 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 8002f74: b480 push {r7} 8002f76: b083 sub sp, #12 8002f78: af00 add r7, sp, #0 8002f7a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 8002f7c: bf00 nop 8002f7e: 370c adds r7, #12 8002f80: 46bd mov sp, r7 8002f82: f85d 7b04 ldr.w r7, [sp], #4 8002f86: 4770 bx lr 08002f88 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 8002f88: b480 push {r7} 8002f8a: b083 sub sp, #12 8002f8c: af00 add r7, sp, #0 8002f8e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 8002f90: bf00 nop 8002f92: 370c adds r7, #12 8002f94: 46bd mov sp, r7 8002f96: f85d 7b04 ldr.w r7, [sp], #4 8002f9a: 4770 bx lr 08002f9c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 8002f9c: b480 push {r7} 8002f9e: b083 sub sp, #12 8002fa0: af00 add r7, sp, #0 8002fa2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 8002fa4: bf00 nop 8002fa6: 370c adds r7, #12 8002fa8: 46bd mov sp, r7 8002faa: f85d 7b04 ldr.w r7, [sp], #4 8002fae: 4770 bx lr 08002fb0 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 8002fb0: b480 push {r7} 8002fb2: b083 sub sp, #12 8002fb4: af00 add r7, sp, #0 8002fb6: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 8002fb8: bf00 nop 8002fba: 370c adds r7, #12 8002fbc: 46bd mov sp, r7 8002fbe: f85d 7b04 ldr.w r7, [sp], #4 8002fc2: 4770 bx lr 08002fc4 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002fc4: b480 push {r7} 8002fc6: b085 sub sp, #20 8002fc8: af00 add r7, sp, #0 8002fca: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002fcc: 687b ldr r3, [r7, #4] 8002fce: f003 0307 and.w r3, r3, #7 8002fd2: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8002fd4: 4b0c ldr r3, [pc, #48] ; (8003008 <__NVIC_SetPriorityGrouping+0x44>) 8002fd6: 68db ldr r3, [r3, #12] 8002fd8: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8002fda: 68ba ldr r2, [r7, #8] 8002fdc: f64f 03ff movw r3, #63743 ; 0xf8ff 8002fe0: 4013 ands r3, r2 8002fe2: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002fe4: 68fb ldr r3, [r7, #12] 8002fe6: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002fe8: 68bb ldr r3, [r7, #8] 8002fea: 4313 orrs r3, r2 reg_value = (reg_value | 8002fec: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8002ff0: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8002ff4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8002ff6: 4a04 ldr r2, [pc, #16] ; (8003008 <__NVIC_SetPriorityGrouping+0x44>) 8002ff8: 68bb ldr r3, [r7, #8] 8002ffa: 60d3 str r3, [r2, #12] } 8002ffc: bf00 nop 8002ffe: 3714 adds r7, #20 8003000: 46bd mov sp, r7 8003002: f85d 7b04 ldr.w r7, [sp], #4 8003006: 4770 bx lr 8003008: e000ed00 .word 0xe000ed00 0800300c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 800300c: b480 push {r7} 800300e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8003010: 4b04 ldr r3, [pc, #16] ; (8003024 <__NVIC_GetPriorityGrouping+0x18>) 8003012: 68db ldr r3, [r3, #12] 8003014: 0a1b lsrs r3, r3, #8 8003016: f003 0307 and.w r3, r3, #7 } 800301a: 4618 mov r0, r3 800301c: 46bd mov sp, r7 800301e: f85d 7b04 ldr.w r7, [sp], #4 8003022: 4770 bx lr 8003024: e000ed00 .word 0xe000ed00 08003028 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8003028: b480 push {r7} 800302a: b083 sub sp, #12 800302c: af00 add r7, sp, #0 800302e: 4603 mov r3, r0 8003030: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8003032: f997 3007 ldrsb.w r3, [r7, #7] 8003036: 2b00 cmp r3, #0 8003038: db0b blt.n 8003052 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800303a: 79fb ldrb r3, [r7, #7] 800303c: f003 021f and.w r2, r3, #31 8003040: 4907 ldr r1, [pc, #28] ; (8003060 <__NVIC_EnableIRQ+0x38>) 8003042: f997 3007 ldrsb.w r3, [r7, #7] 8003046: 095b lsrs r3, r3, #5 8003048: 2001 movs r0, #1 800304a: fa00 f202 lsl.w r2, r0, r2 800304e: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8003052: bf00 nop 8003054: 370c adds r7, #12 8003056: 46bd mov sp, r7 8003058: f85d 7b04 ldr.w r7, [sp], #4 800305c: 4770 bx lr 800305e: bf00 nop 8003060: e000e100 .word 0xe000e100 08003064 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8003064: b480 push {r7} 8003066: b083 sub sp, #12 8003068: af00 add r7, sp, #0 800306a: 4603 mov r3, r0 800306c: 6039 str r1, [r7, #0] 800306e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8003070: f997 3007 ldrsb.w r3, [r7, #7] 8003074: 2b00 cmp r3, #0 8003076: db0a blt.n 800308e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003078: 683b ldr r3, [r7, #0] 800307a: b2da uxtb r2, r3 800307c: 490c ldr r1, [pc, #48] ; (80030b0 <__NVIC_SetPriority+0x4c>) 800307e: f997 3007 ldrsb.w r3, [r7, #7] 8003082: 0112 lsls r2, r2, #4 8003084: b2d2 uxtb r2, r2 8003086: 440b add r3, r1 8003088: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 800308c: e00a b.n 80030a4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800308e: 683b ldr r3, [r7, #0] 8003090: b2da uxtb r2, r3 8003092: 4908 ldr r1, [pc, #32] ; (80030b4 <__NVIC_SetPriority+0x50>) 8003094: 79fb ldrb r3, [r7, #7] 8003096: f003 030f and.w r3, r3, #15 800309a: 3b04 subs r3, #4 800309c: 0112 lsls r2, r2, #4 800309e: b2d2 uxtb r2, r2 80030a0: 440b add r3, r1 80030a2: 761a strb r2, [r3, #24] } 80030a4: bf00 nop 80030a6: 370c adds r7, #12 80030a8: 46bd mov sp, r7 80030aa: f85d 7b04 ldr.w r7, [sp], #4 80030ae: 4770 bx lr 80030b0: e000e100 .word 0xe000e100 80030b4: e000ed00 .word 0xe000ed00 080030b8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80030b8: b480 push {r7} 80030ba: b089 sub sp, #36 ; 0x24 80030bc: af00 add r7, sp, #0 80030be: 60f8 str r0, [r7, #12] 80030c0: 60b9 str r1, [r7, #8] 80030c2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80030c4: 68fb ldr r3, [r7, #12] 80030c6: f003 0307 and.w r3, r3, #7 80030ca: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80030cc: 69fb ldr r3, [r7, #28] 80030ce: f1c3 0307 rsb r3, r3, #7 80030d2: 2b04 cmp r3, #4 80030d4: bf28 it cs 80030d6: 2304 movcs r3, #4 80030d8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80030da: 69fb ldr r3, [r7, #28] 80030dc: 3304 adds r3, #4 80030de: 2b06 cmp r3, #6 80030e0: d902 bls.n 80030e8 80030e2: 69fb ldr r3, [r7, #28] 80030e4: 3b03 subs r3, #3 80030e6: e000 b.n 80030ea 80030e8: 2300 movs r3, #0 80030ea: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80030ec: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80030f0: 69bb ldr r3, [r7, #24] 80030f2: fa02 f303 lsl.w r3, r2, r3 80030f6: 43da mvns r2, r3 80030f8: 68bb ldr r3, [r7, #8] 80030fa: 401a ands r2, r3 80030fc: 697b ldr r3, [r7, #20] 80030fe: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8003100: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8003104: 697b ldr r3, [r7, #20] 8003106: fa01 f303 lsl.w r3, r1, r3 800310a: 43d9 mvns r1, r3 800310c: 687b ldr r3, [r7, #4] 800310e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8003110: 4313 orrs r3, r2 ); } 8003112: 4618 mov r0, r3 8003114: 3724 adds r7, #36 ; 0x24 8003116: 46bd mov sp, r7 8003118: f85d 7b04 ldr.w r7, [sp], #4 800311c: 4770 bx lr ... 08003120 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8003120: b580 push {r7, lr} 8003122: b082 sub sp, #8 8003124: af00 add r7, sp, #0 8003126: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8003128: 687b ldr r3, [r7, #4] 800312a: 3b01 subs r3, #1 800312c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8003130: d301 bcc.n 8003136 { return (1UL); /* Reload value impossible */ 8003132: 2301 movs r3, #1 8003134: e00f b.n 8003156 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8003136: 4a0a ldr r2, [pc, #40] ; (8003160 ) 8003138: 687b ldr r3, [r7, #4] 800313a: 3b01 subs r3, #1 800313c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800313e: 210f movs r1, #15 8003140: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8003144: f7ff ff8e bl 8003064 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8003148: 4b05 ldr r3, [pc, #20] ; (8003160 ) 800314a: 2200 movs r2, #0 800314c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800314e: 4b04 ldr r3, [pc, #16] ; (8003160 ) 8003150: 2207 movs r2, #7 8003152: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8003154: 2300 movs r3, #0 } 8003156: 4618 mov r0, r3 8003158: 3708 adds r7, #8 800315a: 46bd mov sp, r7 800315c: bd80 pop {r7, pc} 800315e: bf00 nop 8003160: e000e010 .word 0xe000e010 08003164 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8003164: b580 push {r7, lr} 8003166: b082 sub sp, #8 8003168: af00 add r7, sp, #0 800316a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800316c: 6878 ldr r0, [r7, #4] 800316e: f7ff ff29 bl 8002fc4 <__NVIC_SetPriorityGrouping> } 8003172: bf00 nop 8003174: 3708 adds r7, #8 8003176: 46bd mov sp, r7 8003178: bd80 pop {r7, pc} 0800317a : * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800317a: b580 push {r7, lr} 800317c: b086 sub sp, #24 800317e: af00 add r7, sp, #0 8003180: 4603 mov r3, r0 8003182: 60b9 str r1, [r7, #8] 8003184: 607a str r2, [r7, #4] 8003186: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8003188: 2300 movs r3, #0 800318a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800318c: f7ff ff3e bl 800300c <__NVIC_GetPriorityGrouping> 8003190: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8003192: 687a ldr r2, [r7, #4] 8003194: 68b9 ldr r1, [r7, #8] 8003196: 6978 ldr r0, [r7, #20] 8003198: f7ff ff8e bl 80030b8 800319c: 4602 mov r2, r0 800319e: f997 300f ldrsb.w r3, [r7, #15] 80031a2: 4611 mov r1, r2 80031a4: 4618 mov r0, r3 80031a6: f7ff ff5d bl 8003064 <__NVIC_SetPriority> } 80031aa: bf00 nop 80031ac: 3718 adds r7, #24 80031ae: 46bd mov sp, r7 80031b0: bd80 pop {r7, pc} 080031b2 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80031b2: b580 push {r7, lr} 80031b4: b082 sub sp, #8 80031b6: af00 add r7, sp, #0 80031b8: 4603 mov r3, r0 80031ba: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80031bc: f997 3007 ldrsb.w r3, [r7, #7] 80031c0: 4618 mov r0, r3 80031c2: f7ff ff31 bl 8003028 <__NVIC_EnableIRQ> } 80031c6: bf00 nop 80031c8: 3708 adds r7, #8 80031ca: 46bd mov sp, r7 80031cc: bd80 pop {r7, pc} 080031ce : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80031ce: b580 push {r7, lr} 80031d0: b082 sub sp, #8 80031d2: af00 add r7, sp, #0 80031d4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80031d6: 6878 ldr r0, [r7, #4] 80031d8: f7ff ffa2 bl 8003120 80031dc: 4603 mov r3, r0 } 80031de: 4618 mov r0, r3 80031e0: 3708 adds r7, #8 80031e2: 46bd mov sp, r7 80031e4: bd80 pop {r7, pc} ... 080031e8 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80031e8: b480 push {r7} 80031ea: b087 sub sp, #28 80031ec: af00 add r7, sp, #0 80031ee: 6078 str r0, [r7, #4] 80031f0: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80031f2: 2300 movs r3, #0 80031f4: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80031f6: e154 b.n 80034a2 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 80031f8: 683b ldr r3, [r7, #0] 80031fa: 681a ldr r2, [r3, #0] 80031fc: 2101 movs r1, #1 80031fe: 697b ldr r3, [r7, #20] 8003200: fa01 f303 lsl.w r3, r1, r3 8003204: 4013 ands r3, r2 8003206: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8003208: 68fb ldr r3, [r7, #12] 800320a: 2b00 cmp r3, #0 800320c: f000 8146 beq.w 800349c { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8003210: 683b ldr r3, [r7, #0] 8003212: 685b ldr r3, [r3, #4] 8003214: f003 0303 and.w r3, r3, #3 8003218: 2b01 cmp r3, #1 800321a: d005 beq.n 8003228 800321c: 683b ldr r3, [r7, #0] 800321e: 685b ldr r3, [r3, #4] 8003220: f003 0303 and.w r3, r3, #3 8003224: 2b02 cmp r3, #2 8003226: d130 bne.n 800328a { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8003228: 687b ldr r3, [r7, #4] 800322a: 689b ldr r3, [r3, #8] 800322c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 800322e: 697b ldr r3, [r7, #20] 8003230: 005b lsls r3, r3, #1 8003232: 2203 movs r2, #3 8003234: fa02 f303 lsl.w r3, r2, r3 8003238: 43db mvns r3, r3 800323a: 693a ldr r2, [r7, #16] 800323c: 4013 ands r3, r2 800323e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8003240: 683b ldr r3, [r7, #0] 8003242: 68da ldr r2, [r3, #12] 8003244: 697b ldr r3, [r7, #20] 8003246: 005b lsls r3, r3, #1 8003248: fa02 f303 lsl.w r3, r2, r3 800324c: 693a ldr r2, [r7, #16] 800324e: 4313 orrs r3, r2 8003250: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8003252: 687b ldr r3, [r7, #4] 8003254: 693a ldr r2, [r7, #16] 8003256: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8003258: 687b ldr r3, [r7, #4] 800325a: 685b ldr r3, [r3, #4] 800325c: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 800325e: 2201 movs r2, #1 8003260: 697b ldr r3, [r7, #20] 8003262: fa02 f303 lsl.w r3, r2, r3 8003266: 43db mvns r3, r3 8003268: 693a ldr r2, [r7, #16] 800326a: 4013 ands r3, r2 800326c: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800326e: 683b ldr r3, [r7, #0] 8003270: 685b ldr r3, [r3, #4] 8003272: 091b lsrs r3, r3, #4 8003274: f003 0201 and.w r2, r3, #1 8003278: 697b ldr r3, [r7, #20] 800327a: fa02 f303 lsl.w r3, r2, r3 800327e: 693a ldr r2, [r7, #16] 8003280: 4313 orrs r3, r2 8003282: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8003284: 687b ldr r3, [r7, #4] 8003286: 693a ldr r2, [r7, #16] 8003288: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800328a: 683b ldr r3, [r7, #0] 800328c: 685b ldr r3, [r3, #4] 800328e: f003 0303 and.w r3, r3, #3 8003292: 2b03 cmp r3, #3 8003294: d017 beq.n 80032c6 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8003296: 687b ldr r3, [r7, #4] 8003298: 68db ldr r3, [r3, #12] 800329a: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 800329c: 697b ldr r3, [r7, #20] 800329e: 005b lsls r3, r3, #1 80032a0: 2203 movs r2, #3 80032a2: fa02 f303 lsl.w r3, r2, r3 80032a6: 43db mvns r3, r3 80032a8: 693a ldr r2, [r7, #16] 80032aa: 4013 ands r3, r2 80032ac: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 80032ae: 683b ldr r3, [r7, #0] 80032b0: 689a ldr r2, [r3, #8] 80032b2: 697b ldr r3, [r7, #20] 80032b4: 005b lsls r3, r3, #1 80032b6: fa02 f303 lsl.w r3, r2, r3 80032ba: 693a ldr r2, [r7, #16] 80032bc: 4313 orrs r3, r2 80032be: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 80032c0: 687b ldr r3, [r7, #4] 80032c2: 693a ldr r2, [r7, #16] 80032c4: 60da str r2, [r3, #12] } /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80032c6: 683b ldr r3, [r7, #0] 80032c8: 685b ldr r3, [r3, #4] 80032ca: f003 0303 and.w r3, r3, #3 80032ce: 2b02 cmp r3, #2 80032d0: d123 bne.n 800331a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 80032d2: 697b ldr r3, [r7, #20] 80032d4: 08da lsrs r2, r3, #3 80032d6: 687b ldr r3, [r7, #4] 80032d8: 3208 adds r2, #8 80032da: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80032de: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 80032e0: 697b ldr r3, [r7, #20] 80032e2: f003 0307 and.w r3, r3, #7 80032e6: 009b lsls r3, r3, #2 80032e8: 220f movs r2, #15 80032ea: fa02 f303 lsl.w r3, r2, r3 80032ee: 43db mvns r3, r3 80032f0: 693a ldr r2, [r7, #16] 80032f2: 4013 ands r3, r2 80032f4: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 80032f6: 683b ldr r3, [r7, #0] 80032f8: 691a ldr r2, [r3, #16] 80032fa: 697b ldr r3, [r7, #20] 80032fc: f003 0307 and.w r3, r3, #7 8003300: 009b lsls r3, r3, #2 8003302: fa02 f303 lsl.w r3, r2, r3 8003306: 693a ldr r2, [r7, #16] 8003308: 4313 orrs r3, r2 800330a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 800330c: 697b ldr r3, [r7, #20] 800330e: 08da lsrs r2, r3, #3 8003310: 687b ldr r3, [r7, #4] 8003312: 3208 adds r2, #8 8003314: 6939 ldr r1, [r7, #16] 8003316: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800331a: 687b ldr r3, [r7, #4] 800331c: 681b ldr r3, [r3, #0] 800331e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8003320: 697b ldr r3, [r7, #20] 8003322: 005b lsls r3, r3, #1 8003324: 2203 movs r2, #3 8003326: fa02 f303 lsl.w r3, r2, r3 800332a: 43db mvns r3, r3 800332c: 693a ldr r2, [r7, #16] 800332e: 4013 ands r3, r2 8003330: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8003332: 683b ldr r3, [r7, #0] 8003334: 685b ldr r3, [r3, #4] 8003336: f003 0203 and.w r2, r3, #3 800333a: 697b ldr r3, [r7, #20] 800333c: 005b lsls r3, r3, #1 800333e: fa02 f303 lsl.w r3, r2, r3 8003342: 693a ldr r2, [r7, #16] 8003344: 4313 orrs r3, r2 8003346: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8003348: 687b ldr r3, [r7, #4] 800334a: 693a ldr r2, [r7, #16] 800334c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 800334e: 683b ldr r3, [r7, #0] 8003350: 685b ldr r3, [r3, #4] 8003352: f403 3340 and.w r3, r3, #196608 ; 0x30000 8003356: 2b00 cmp r3, #0 8003358: f000 80a0 beq.w 800349c { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800335c: 4b58 ldr r3, [pc, #352] ; (80034c0 ) 800335e: 699b ldr r3, [r3, #24] 8003360: 4a57 ldr r2, [pc, #348] ; (80034c0 ) 8003362: f043 0301 orr.w r3, r3, #1 8003366: 6193 str r3, [r2, #24] 8003368: 4b55 ldr r3, [pc, #340] ; (80034c0 ) 800336a: 699b ldr r3, [r3, #24] 800336c: f003 0301 and.w r3, r3, #1 8003370: 60bb str r3, [r7, #8] 8003372: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 8003374: 4a53 ldr r2, [pc, #332] ; (80034c4 ) 8003376: 697b ldr r3, [r7, #20] 8003378: 089b lsrs r3, r3, #2 800337a: 3302 adds r3, #2 800337c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003380: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 8003382: 697b ldr r3, [r7, #20] 8003384: f003 0303 and.w r3, r3, #3 8003388: 009b lsls r3, r3, #2 800338a: 220f movs r2, #15 800338c: fa02 f303 lsl.w r3, r2, r3 8003390: 43db mvns r3, r3 8003392: 693a ldr r2, [r7, #16] 8003394: 4013 ands r3, r2 8003396: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 8003398: 687b ldr r3, [r7, #4] 800339a: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 800339e: d019 beq.n 80033d4 80033a0: 687b ldr r3, [r7, #4] 80033a2: 4a49 ldr r2, [pc, #292] ; (80034c8 ) 80033a4: 4293 cmp r3, r2 80033a6: d013 beq.n 80033d0 80033a8: 687b ldr r3, [r7, #4] 80033aa: 4a48 ldr r2, [pc, #288] ; (80034cc ) 80033ac: 4293 cmp r3, r2 80033ae: d00d beq.n 80033cc 80033b0: 687b ldr r3, [r7, #4] 80033b2: 4a47 ldr r2, [pc, #284] ; (80034d0 ) 80033b4: 4293 cmp r3, r2 80033b6: d007 beq.n 80033c8 80033b8: 687b ldr r3, [r7, #4] 80033ba: 4a46 ldr r2, [pc, #280] ; (80034d4 ) 80033bc: 4293 cmp r3, r2 80033be: d101 bne.n 80033c4 80033c0: 2304 movs r3, #4 80033c2: e008 b.n 80033d6 80033c4: 2305 movs r3, #5 80033c6: e006 b.n 80033d6 80033c8: 2303 movs r3, #3 80033ca: e004 b.n 80033d6 80033cc: 2302 movs r3, #2 80033ce: e002 b.n 80033d6 80033d0: 2301 movs r3, #1 80033d2: e000 b.n 80033d6 80033d4: 2300 movs r3, #0 80033d6: 697a ldr r2, [r7, #20] 80033d8: f002 0203 and.w r2, r2, #3 80033dc: 0092 lsls r2, r2, #2 80033de: 4093 lsls r3, r2 80033e0: 693a ldr r2, [r7, #16] 80033e2: 4313 orrs r3, r2 80033e4: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 80033e6: 4937 ldr r1, [pc, #220] ; (80034c4 ) 80033e8: 697b ldr r3, [r7, #20] 80033ea: 089b lsrs r3, r3, #2 80033ec: 3302 adds r3, #2 80033ee: 693a ldr r2, [r7, #16] 80033f0: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR; 80033f4: 4b38 ldr r3, [pc, #224] ; (80034d8 ) 80033f6: 681b ldr r3, [r3, #0] 80033f8: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80033fa: 68fb ldr r3, [r7, #12] 80033fc: 43db mvns r3, r3 80033fe: 693a ldr r2, [r7, #16] 8003400: 4013 ands r3, r2 8003402: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8003404: 683b ldr r3, [r7, #0] 8003406: 685b ldr r3, [r3, #4] 8003408: f403 3380 and.w r3, r3, #65536 ; 0x10000 800340c: 2b00 cmp r3, #0 800340e: d003 beq.n 8003418 { temp |= iocurrent; 8003410: 693a ldr r2, [r7, #16] 8003412: 68fb ldr r3, [r7, #12] 8003414: 4313 orrs r3, r2 8003416: 613b str r3, [r7, #16] } EXTI->IMR = temp; 8003418: 4a2f ldr r2, [pc, #188] ; (80034d8 ) 800341a: 693b ldr r3, [r7, #16] 800341c: 6013 str r3, [r2, #0] temp = EXTI->EMR; 800341e: 4b2e ldr r3, [pc, #184] ; (80034d8 ) 8003420: 685b ldr r3, [r3, #4] 8003422: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8003424: 68fb ldr r3, [r7, #12] 8003426: 43db mvns r3, r3 8003428: 693a ldr r2, [r7, #16] 800342a: 4013 ands r3, r2 800342c: 613b str r3, [r7, #16] if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 800342e: 683b ldr r3, [r7, #0] 8003430: 685b ldr r3, [r3, #4] 8003432: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003436: 2b00 cmp r3, #0 8003438: d003 beq.n 8003442 { temp |= iocurrent; 800343a: 693a ldr r2, [r7, #16] 800343c: 68fb ldr r3, [r7, #12] 800343e: 4313 orrs r3, r2 8003440: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8003442: 4a25 ldr r2, [pc, #148] ; (80034d8 ) 8003444: 693b ldr r3, [r7, #16] 8003446: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8003448: 4b23 ldr r3, [pc, #140] ; (80034d8 ) 800344a: 689b ldr r3, [r3, #8] 800344c: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800344e: 68fb ldr r3, [r7, #12] 8003450: 43db mvns r3, r3 8003452: 693a ldr r2, [r7, #16] 8003454: 4013 ands r3, r2 8003456: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8003458: 683b ldr r3, [r7, #0] 800345a: 685b ldr r3, [r3, #4] 800345c: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8003460: 2b00 cmp r3, #0 8003462: d003 beq.n 800346c { temp |= iocurrent; 8003464: 693a ldr r2, [r7, #16] 8003466: 68fb ldr r3, [r7, #12] 8003468: 4313 orrs r3, r2 800346a: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 800346c: 4a1a ldr r2, [pc, #104] ; (80034d8 ) 800346e: 693b ldr r3, [r7, #16] 8003470: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8003472: 4b19 ldr r3, [pc, #100] ; (80034d8 ) 8003474: 68db ldr r3, [r3, #12] 8003476: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8003478: 68fb ldr r3, [r7, #12] 800347a: 43db mvns r3, r3 800347c: 693a ldr r2, [r7, #16] 800347e: 4013 ands r3, r2 8003480: 613b str r3, [r7, #16] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8003482: 683b ldr r3, [r7, #0] 8003484: 685b ldr r3, [r3, #4] 8003486: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800348a: 2b00 cmp r3, #0 800348c: d003 beq.n 8003496 { temp |= iocurrent; 800348e: 693a ldr r2, [r7, #16] 8003490: 68fb ldr r3, [r7, #12] 8003492: 4313 orrs r3, r2 8003494: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 8003496: 4a10 ldr r2, [pc, #64] ; (80034d8 ) 8003498: 693b ldr r3, [r7, #16] 800349a: 60d3 str r3, [r2, #12] } } position++; 800349c: 697b ldr r3, [r7, #20] 800349e: 3301 adds r3, #1 80034a0: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 80034a2: 683b ldr r3, [r7, #0] 80034a4: 681a ldr r2, [r3, #0] 80034a6: 697b ldr r3, [r7, #20] 80034a8: fa22 f303 lsr.w r3, r2, r3 80034ac: 2b00 cmp r3, #0 80034ae: f47f aea3 bne.w 80031f8 } } 80034b2: bf00 nop 80034b4: bf00 nop 80034b6: 371c adds r7, #28 80034b8: 46bd mov sp, r7 80034ba: f85d 7b04 ldr.w r7, [sp], #4 80034be: 4770 bx lr 80034c0: 40021000 .word 0x40021000 80034c4: 40010000 .word 0x40010000 80034c8: 48000400 .word 0x48000400 80034cc: 48000800 .word 0x48000800 80034d0: 48000c00 .word 0x48000c00 80034d4: 48001000 .word 0x48001000 80034d8: 40010400 .word 0x40010400 080034dc : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80034dc: b480 push {r7} 80034de: b083 sub sp, #12 80034e0: af00 add r7, sp, #0 80034e2: 6078 str r0, [r7, #4] 80034e4: 460b mov r3, r1 80034e6: 807b strh r3, [r7, #2] 80034e8: 4613 mov r3, r2 80034ea: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 80034ec: 787b ldrb r3, [r7, #1] 80034ee: 2b00 cmp r3, #0 80034f0: d003 beq.n 80034fa { GPIOx->BSRR = (uint32_t)GPIO_Pin; 80034f2: 887a ldrh r2, [r7, #2] 80034f4: 687b ldr r3, [r7, #4] 80034f6: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 80034f8: e002 b.n 8003500 GPIOx->BRR = (uint32_t)GPIO_Pin; 80034fa: 887a ldrh r2, [r7, #2] 80034fc: 687b ldr r3, [r7, #4] 80034fe: 629a str r2, [r3, #40] ; 0x28 } 8003500: bf00 nop 8003502: 370c adds r7, #12 8003504: 46bd mov sp, r7 8003506: f85d 7b04 ldr.w r7, [sp], #4 800350a: 4770 bx lr 0800350c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 800350c: b580 push {r7, lr} 800350e: b082 sub sp, #8 8003510: af00 add r7, sp, #0 8003512: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 8003514: 687b ldr r3, [r7, #4] 8003516: 2b00 cmp r3, #0 8003518: d101 bne.n 800351e { return HAL_ERROR; 800351a: 2301 movs r3, #1 800351c: e081 b.n 8003622 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 800351e: 687b ldr r3, [r7, #4] 8003520: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 8003524: b2db uxtb r3, r3 8003526: 2b00 cmp r3, #0 8003528: d106 bne.n 8003538 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 800352a: 687b ldr r3, [r7, #4] 800352c: 2200 movs r2, #0 800352e: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 8003532: 6878 ldr r0, [r7, #4] 8003534: f7fe fcf6 bl 8001f24 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8003538: 687b ldr r3, [r7, #4] 800353a: 2224 movs r2, #36 ; 0x24 800353c: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8003540: 687b ldr r3, [r7, #4] 8003542: 681b ldr r3, [r3, #0] 8003544: 681a ldr r2, [r3, #0] 8003546: 687b ldr r3, [r7, #4] 8003548: 681b ldr r3, [r3, #0] 800354a: f022 0201 bic.w r2, r2, #1 800354e: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 8003550: 687b ldr r3, [r7, #4] 8003552: 685a ldr r2, [r3, #4] 8003554: 687b ldr r3, [r7, #4] 8003556: 681b ldr r3, [r3, #0] 8003558: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 800355c: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 800355e: 687b ldr r3, [r7, #4] 8003560: 681b ldr r3, [r3, #0] 8003562: 689a ldr r2, [r3, #8] 8003564: 687b ldr r3, [r7, #4] 8003566: 681b ldr r3, [r3, #0] 8003568: f422 4200 bic.w r2, r2, #32768 ; 0x8000 800356c: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 800356e: 687b ldr r3, [r7, #4] 8003570: 68db ldr r3, [r3, #12] 8003572: 2b01 cmp r3, #1 8003574: d107 bne.n 8003586 { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 8003576: 687b ldr r3, [r7, #4] 8003578: 689a ldr r2, [r3, #8] 800357a: 687b ldr r3, [r7, #4] 800357c: 681b ldr r3, [r3, #0] 800357e: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8003582: 609a str r2, [r3, #8] 8003584: e006 b.n 8003594 } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 8003586: 687b ldr r3, [r7, #4] 8003588: 689a ldr r2, [r3, #8] 800358a: 687b ldr r3, [r7, #4] 800358c: 681b ldr r3, [r3, #0] 800358e: f442 4204 orr.w r2, r2, #33792 ; 0x8400 8003592: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8003594: 687b ldr r3, [r7, #4] 8003596: 68db ldr r3, [r3, #12] 8003598: 2b02 cmp r3, #2 800359a: d104 bne.n 80035a6 { hi2c->Instance->CR2 = (I2C_CR2_ADD10); 800359c: 687b ldr r3, [r7, #4] 800359e: 681b ldr r3, [r3, #0] 80035a0: f44f 6200 mov.w r2, #2048 ; 0x800 80035a4: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 80035a6: 687b ldr r3, [r7, #4] 80035a8: 681b ldr r3, [r3, #0] 80035aa: 685b ldr r3, [r3, #4] 80035ac: 687a ldr r2, [r7, #4] 80035ae: 6812 ldr r2, [r2, #0] 80035b0: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 80035b4: f443 4300 orr.w r3, r3, #32768 ; 0x8000 80035b8: 6053 str r3, [r2, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 80035ba: 687b ldr r3, [r7, #4] 80035bc: 681b ldr r3, [r3, #0] 80035be: 68da ldr r2, [r3, #12] 80035c0: 687b ldr r3, [r7, #4] 80035c2: 681b ldr r3, [r3, #0] 80035c4: f422 4200 bic.w r2, r2, #32768 ; 0x8000 80035c8: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 80035ca: 687b ldr r3, [r7, #4] 80035cc: 691a ldr r2, [r3, #16] 80035ce: 687b ldr r3, [r7, #4] 80035d0: 695b ldr r3, [r3, #20] 80035d2: ea42 0103 orr.w r1, r2, r3 (hi2c->Init.OwnAddress2Masks << 8)); 80035d6: 687b ldr r3, [r7, #4] 80035d8: 699b ldr r3, [r3, #24] 80035da: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 80035dc: 687b ldr r3, [r7, #4] 80035de: 681b ldr r3, [r3, #0] 80035e0: 430a orrs r2, r1 80035e2: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 80035e4: 687b ldr r3, [r7, #4] 80035e6: 69d9 ldr r1, [r3, #28] 80035e8: 687b ldr r3, [r7, #4] 80035ea: 6a1a ldr r2, [r3, #32] 80035ec: 687b ldr r3, [r7, #4] 80035ee: 681b ldr r3, [r3, #0] 80035f0: 430a orrs r2, r1 80035f2: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 80035f4: 687b ldr r3, [r7, #4] 80035f6: 681b ldr r3, [r3, #0] 80035f8: 681a ldr r2, [r3, #0] 80035fa: 687b ldr r3, [r7, #4] 80035fc: 681b ldr r3, [r3, #0] 80035fe: f042 0201 orr.w r2, r2, #1 8003602: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8003604: 687b ldr r3, [r7, #4] 8003606: 2200 movs r2, #0 8003608: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 800360a: 687b ldr r3, [r7, #4] 800360c: 2220 movs r2, #32 800360e: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->PreviousState = I2C_STATE_NONE; 8003612: 687b ldr r3, [r7, #4] 8003614: 2200 movs r2, #0 8003616: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8003618: 687b ldr r3, [r7, #4] 800361a: 2200 movs r2, #0 800361c: f883 2042 strb.w r2, [r3, #66] ; 0x42 return HAL_OK; 8003620: 2300 movs r3, #0 } 8003622: 4618 mov r0, r3 8003624: 3708 adds r7, #8 8003626: 46bd mov sp, r7 8003628: bd80 pop {r7, pc} ... 0800362c : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 800362c: b580 push {r7, lr} 800362e: b088 sub sp, #32 8003630: af02 add r7, sp, #8 8003632: 60f8 str r0, [r7, #12] 8003634: 607a str r2, [r7, #4] 8003636: 461a mov r2, r3 8003638: 460b mov r3, r1 800363a: 817b strh r3, [r7, #10] 800363c: 4613 mov r3, r2 800363e: 813b strh r3, [r7, #8] uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) 8003640: 68fb ldr r3, [r7, #12] 8003642: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 8003646: b2db uxtb r3, r3 8003648: 2b20 cmp r3, #32 800364a: f040 80da bne.w 8003802 { /* Process Locked */ __HAL_LOCK(hi2c); 800364e: 68fb ldr r3, [r7, #12] 8003650: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 8003654: 2b01 cmp r3, #1 8003656: d101 bne.n 800365c 8003658: 2302 movs r3, #2 800365a: e0d3 b.n 8003804 800365c: 68fb ldr r3, [r7, #12] 800365e: 2201 movs r2, #1 8003660: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8003664: f7fe fdfe bl 8002264 8003668: 6178 str r0, [r7, #20] if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) 800366a: 697b ldr r3, [r7, #20] 800366c: 9300 str r3, [sp, #0] 800366e: 2319 movs r3, #25 8003670: 2201 movs r2, #1 8003672: f44f 4100 mov.w r1, #32768 ; 0x8000 8003676: 68f8 ldr r0, [r7, #12] 8003678: f000 fcbc bl 8003ff4 800367c: 4603 mov r3, r0 800367e: 2b00 cmp r3, #0 8003680: d001 beq.n 8003686 { return HAL_ERROR; 8003682: 2301 movs r3, #1 8003684: e0be b.n 8003804 } hi2c->State = HAL_I2C_STATE_BUSY_TX; 8003686: 68fb ldr r3, [r7, #12] 8003688: 2221 movs r2, #33 ; 0x21 800368a: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_MASTER; 800368e: 68fb ldr r3, [r7, #12] 8003690: 2210 movs r2, #16 8003692: f883 2042 strb.w r2, [r3, #66] ; 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8003696: 68fb ldr r3, [r7, #12] 8003698: 2200 movs r2, #0 800369a: 645a str r2, [r3, #68] ; 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 800369c: 68fb ldr r3, [r7, #12] 800369e: 687a ldr r2, [r7, #4] 80036a0: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 80036a2: 68fb ldr r3, [r7, #12] 80036a4: 893a ldrh r2, [r7, #8] 80036a6: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferISR = NULL; 80036a8: 68fb ldr r3, [r7, #12] 80036aa: 2200 movs r2, #0 80036ac: 635a str r2, [r3, #52] ; 0x34 /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 80036ae: 68fb ldr r3, [r7, #12] 80036b0: 8d5b ldrh r3, [r3, #42] ; 0x2a 80036b2: b29b uxth r3, r3 80036b4: 2bff cmp r3, #255 ; 0xff 80036b6: d90e bls.n 80036d6 { hi2c->XferSize = MAX_NBYTE_SIZE; 80036b8: 68fb ldr r3, [r7, #12] 80036ba: 22ff movs r2, #255 ; 0xff 80036bc: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 80036be: 68fb ldr r3, [r7, #12] 80036c0: 8d1b ldrh r3, [r3, #40] ; 0x28 80036c2: b2da uxtb r2, r3 80036c4: 8979 ldrh r1, [r7, #10] 80036c6: 4b51 ldr r3, [pc, #324] ; (800380c ) 80036c8: 9300 str r3, [sp, #0] 80036ca: f04f 7380 mov.w r3, #16777216 ; 0x1000000 80036ce: 68f8 ldr r0, [r7, #12] 80036d0: f000 fe2e bl 8004330 80036d4: e06c b.n 80037b0 I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; 80036d6: 68fb ldr r3, [r7, #12] 80036d8: 8d5b ldrh r3, [r3, #42] ; 0x2a 80036da: b29a uxth r2, r3 80036dc: 68fb ldr r3, [r7, #12] 80036de: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 80036e0: 68fb ldr r3, [r7, #12] 80036e2: 8d1b ldrh r3, [r3, #40] ; 0x28 80036e4: b2da uxtb r2, r3 80036e6: 8979 ldrh r1, [r7, #10] 80036e8: 4b48 ldr r3, [pc, #288] ; (800380c ) 80036ea: 9300 str r3, [sp, #0] 80036ec: f04f 7300 mov.w r3, #33554432 ; 0x2000000 80036f0: 68f8 ldr r0, [r7, #12] 80036f2: f000 fe1d bl 8004330 I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) 80036f6: e05b b.n 80037b0 { /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80036f8: 697a ldr r2, [r7, #20] 80036fa: 6a39 ldr r1, [r7, #32] 80036fc: 68f8 ldr r0, [r7, #12] 80036fe: f000 fcb9 bl 8004074 8003702: 4603 mov r3, r0 8003704: 2b00 cmp r3, #0 8003706: d001 beq.n 800370c { return HAL_ERROR; 8003708: 2301 movs r3, #1 800370a: e07b b.n 8003804 } /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 800370c: 68fb ldr r3, [r7, #12] 800370e: 6a5b ldr r3, [r3, #36] ; 0x24 8003710: 781a ldrb r2, [r3, #0] 8003712: 68fb ldr r3, [r7, #12] 8003714: 681b ldr r3, [r3, #0] 8003716: 629a str r2, [r3, #40] ; 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003718: 68fb ldr r3, [r7, #12] 800371a: 6a5b ldr r3, [r3, #36] ; 0x24 800371c: 1c5a adds r2, r3, #1 800371e: 68fb ldr r3, [r7, #12] 8003720: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount--; 8003722: 68fb ldr r3, [r7, #12] 8003724: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003726: b29b uxth r3, r3 8003728: 3b01 subs r3, #1 800372a: b29a uxth r2, r3 800372c: 68fb ldr r3, [r7, #12] 800372e: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize--; 8003730: 68fb ldr r3, [r7, #12] 8003732: 8d1b ldrh r3, [r3, #40] ; 0x28 8003734: 3b01 subs r3, #1 8003736: b29a uxth r2, r3 8003738: 68fb ldr r3, [r7, #12] 800373a: 851a strh r2, [r3, #40] ; 0x28 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 800373c: 68fb ldr r3, [r7, #12] 800373e: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003740: b29b uxth r3, r3 8003742: 2b00 cmp r3, #0 8003744: d034 beq.n 80037b0 8003746: 68fb ldr r3, [r7, #12] 8003748: 8d1b ldrh r3, [r3, #40] ; 0x28 800374a: 2b00 cmp r3, #0 800374c: d130 bne.n 80037b0 { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) 800374e: 697b ldr r3, [r7, #20] 8003750: 9300 str r3, [sp, #0] 8003752: 6a3b ldr r3, [r7, #32] 8003754: 2200 movs r2, #0 8003756: 2180 movs r1, #128 ; 0x80 8003758: 68f8 ldr r0, [r7, #12] 800375a: f000 fc4b bl 8003ff4 800375e: 4603 mov r3, r0 8003760: 2b00 cmp r3, #0 8003762: d001 beq.n 8003768 { return HAL_ERROR; 8003764: 2301 movs r3, #1 8003766: e04d b.n 8003804 } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8003768: 68fb ldr r3, [r7, #12] 800376a: 8d5b ldrh r3, [r3, #42] ; 0x2a 800376c: b29b uxth r3, r3 800376e: 2bff cmp r3, #255 ; 0xff 8003770: d90e bls.n 8003790 { hi2c->XferSize = MAX_NBYTE_SIZE; 8003772: 68fb ldr r3, [r7, #12] 8003774: 22ff movs r2, #255 ; 0xff 8003776: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 8003778: 68fb ldr r3, [r7, #12] 800377a: 8d1b ldrh r3, [r3, #40] ; 0x28 800377c: b2da uxtb r2, r3 800377e: 8979 ldrh r1, [r7, #10] 8003780: 2300 movs r3, #0 8003782: 9300 str r3, [sp, #0] 8003784: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003788: 68f8 ldr r0, [r7, #12] 800378a: f000 fdd1 bl 8004330 800378e: e00f b.n 80037b0 I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 8003790: 68fb ldr r3, [r7, #12] 8003792: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003794: b29a uxth r2, r3 8003796: 68fb ldr r3, [r7, #12] 8003798: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 800379a: 68fb ldr r3, [r7, #12] 800379c: 8d1b ldrh r3, [r3, #40] ; 0x28 800379e: b2da uxtb r2, r3 80037a0: 8979 ldrh r1, [r7, #10] 80037a2: 2300 movs r3, #0 80037a4: 9300 str r3, [sp, #0] 80037a6: f04f 7300 mov.w r3, #33554432 ; 0x2000000 80037aa: 68f8 ldr r0, [r7, #12] 80037ac: f000 fdc0 bl 8004330 while (hi2c->XferCount > 0U) 80037b0: 68fb ldr r3, [r7, #12] 80037b2: 8d5b ldrh r3, [r3, #42] ; 0x2a 80037b4: b29b uxth r3, r3 80037b6: 2b00 cmp r3, #0 80037b8: d19e bne.n 80036f8 } } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80037ba: 697a ldr r2, [r7, #20] 80037bc: 6a39 ldr r1, [r7, #32] 80037be: 68f8 ldr r0, [r7, #12] 80037c0: f000 fc98 bl 80040f4 80037c4: 4603 mov r3, r0 80037c6: 2b00 cmp r3, #0 80037c8: d001 beq.n 80037ce { return HAL_ERROR; 80037ca: 2301 movs r3, #1 80037cc: e01a b.n 8003804 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 80037ce: 68fb ldr r3, [r7, #12] 80037d0: 681b ldr r3, [r3, #0] 80037d2: 2220 movs r2, #32 80037d4: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80037d6: 68fb ldr r3, [r7, #12] 80037d8: 681b ldr r3, [r3, #0] 80037da: 6859 ldr r1, [r3, #4] 80037dc: 68fb ldr r3, [r7, #12] 80037de: 681a ldr r2, [r3, #0] 80037e0: 4b0b ldr r3, [pc, #44] ; (8003810 ) 80037e2: 400b ands r3, r1 80037e4: 6053 str r3, [r2, #4] hi2c->State = HAL_I2C_STATE_READY; 80037e6: 68fb ldr r3, [r7, #12] 80037e8: 2220 movs r2, #32 80037ea: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 80037ee: 68fb ldr r3, [r7, #12] 80037f0: 2200 movs r2, #0 80037f2: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80037f6: 68fb ldr r3, [r7, #12] 80037f8: 2200 movs r2, #0 80037fa: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; 80037fe: 2300 movs r3, #0 8003800: e000 b.n 8003804 } else { return HAL_BUSY; 8003802: 2302 movs r3, #2 } } 8003804: 4618 mov r0, r3 8003806: 3718 adds r7, #24 8003808: 46bd mov sp, r7 800380a: bd80 pop {r7, pc} 800380c: 80002000 .word 0x80002000 8003810: fe00e800 .word 0xfe00e800 08003814 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8003814: b580 push {r7, lr} 8003816: b088 sub sp, #32 8003818: af02 add r7, sp, #8 800381a: 60f8 str r0, [r7, #12] 800381c: 607a str r2, [r7, #4] 800381e: 461a mov r2, r3 8003820: 460b mov r3, r1 8003822: 817b strh r3, [r7, #10] 8003824: 4613 mov r3, r2 8003826: 813b strh r3, [r7, #8] uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) 8003828: 68fb ldr r3, [r7, #12] 800382a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 800382e: b2db uxtb r3, r3 8003830: 2b20 cmp r3, #32 8003832: f040 80db bne.w 80039ec { /* Process Locked */ __HAL_LOCK(hi2c); 8003836: 68fb ldr r3, [r7, #12] 8003838: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 800383c: 2b01 cmp r3, #1 800383e: d101 bne.n 8003844 8003840: 2302 movs r3, #2 8003842: e0d4 b.n 80039ee 8003844: 68fb ldr r3, [r7, #12] 8003846: 2201 movs r2, #1 8003848: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800384c: f7fe fd0a bl 8002264 8003850: 6178 str r0, [r7, #20] if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) 8003852: 697b ldr r3, [r7, #20] 8003854: 9300 str r3, [sp, #0] 8003856: 2319 movs r3, #25 8003858: 2201 movs r2, #1 800385a: f44f 4100 mov.w r1, #32768 ; 0x8000 800385e: 68f8 ldr r0, [r7, #12] 8003860: f000 fbc8 bl 8003ff4 8003864: 4603 mov r3, r0 8003866: 2b00 cmp r3, #0 8003868: d001 beq.n 800386e { return HAL_ERROR; 800386a: 2301 movs r3, #1 800386c: e0bf b.n 80039ee } hi2c->State = HAL_I2C_STATE_BUSY_RX; 800386e: 68fb ldr r3, [r7, #12] 8003870: 2222 movs r2, #34 ; 0x22 8003872: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_MASTER; 8003876: 68fb ldr r3, [r7, #12] 8003878: 2210 movs r2, #16 800387a: f883 2042 strb.w r2, [r3, #66] ; 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800387e: 68fb ldr r3, [r7, #12] 8003880: 2200 movs r2, #0 8003882: 645a str r2, [r3, #68] ; 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8003884: 68fb ldr r3, [r7, #12] 8003886: 687a ldr r2, [r7, #4] 8003888: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 800388a: 68fb ldr r3, [r7, #12] 800388c: 893a ldrh r2, [r7, #8] 800388e: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferISR = NULL; 8003890: 68fb ldr r3, [r7, #12] 8003892: 2200 movs r2, #0 8003894: 635a str r2, [r3, #52] ; 0x34 /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8003896: 68fb ldr r3, [r7, #12] 8003898: 8d5b ldrh r3, [r3, #42] ; 0x2a 800389a: b29b uxth r3, r3 800389c: 2bff cmp r3, #255 ; 0xff 800389e: d90e bls.n 80038be { hi2c->XferSize = MAX_NBYTE_SIZE; 80038a0: 68fb ldr r3, [r7, #12] 80038a2: 22ff movs r2, #255 ; 0xff 80038a4: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 80038a6: 68fb ldr r3, [r7, #12] 80038a8: 8d1b ldrh r3, [r3, #40] ; 0x28 80038aa: b2da uxtb r2, r3 80038ac: 8979 ldrh r1, [r7, #10] 80038ae: 4b52 ldr r3, [pc, #328] ; (80039f8 ) 80038b0: 9300 str r3, [sp, #0] 80038b2: f04f 7380 mov.w r3, #16777216 ; 0x1000000 80038b6: 68f8 ldr r0, [r7, #12] 80038b8: f000 fd3a bl 8004330 80038bc: e06d b.n 800399a I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; 80038be: 68fb ldr r3, [r7, #12] 80038c0: 8d5b ldrh r3, [r3, #42] ; 0x2a 80038c2: b29a uxth r2, r3 80038c4: 68fb ldr r3, [r7, #12] 80038c6: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 80038c8: 68fb ldr r3, [r7, #12] 80038ca: 8d1b ldrh r3, [r3, #40] ; 0x28 80038cc: b2da uxtb r2, r3 80038ce: 8979 ldrh r1, [r7, #10] 80038d0: 4b49 ldr r3, [pc, #292] ; (80039f8 ) 80038d2: 9300 str r3, [sp, #0] 80038d4: f04f 7300 mov.w r3, #33554432 ; 0x2000000 80038d8: 68f8 ldr r0, [r7, #12] 80038da: f000 fd29 bl 8004330 I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) 80038de: e05c b.n 800399a { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80038e0: 697a ldr r2, [r7, #20] 80038e2: 6a39 ldr r1, [r7, #32] 80038e4: 68f8 ldr r0, [r7, #12] 80038e6: f000 fc41 bl 800416c 80038ea: 4603 mov r3, r0 80038ec: 2b00 cmp r3, #0 80038ee: d001 beq.n 80038f4 { return HAL_ERROR; 80038f0: 2301 movs r3, #1 80038f2: e07c b.n 80039ee } /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 80038f4: 68fb ldr r3, [r7, #12] 80038f6: 681b ldr r3, [r3, #0] 80038f8: 6a5a ldr r2, [r3, #36] ; 0x24 80038fa: 68fb ldr r3, [r7, #12] 80038fc: 6a5b ldr r3, [r3, #36] ; 0x24 80038fe: b2d2 uxtb r2, r2 8003900: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003902: 68fb ldr r3, [r7, #12] 8003904: 6a5b ldr r3, [r3, #36] ; 0x24 8003906: 1c5a adds r2, r3, #1 8003908: 68fb ldr r3, [r7, #12] 800390a: 625a str r2, [r3, #36] ; 0x24 hi2c->XferSize--; 800390c: 68fb ldr r3, [r7, #12] 800390e: 8d1b ldrh r3, [r3, #40] ; 0x28 8003910: 3b01 subs r3, #1 8003912: b29a uxth r2, r3 8003914: 68fb ldr r3, [r7, #12] 8003916: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8003918: 68fb ldr r3, [r7, #12] 800391a: 8d5b ldrh r3, [r3, #42] ; 0x2a 800391c: b29b uxth r3, r3 800391e: 3b01 subs r3, #1 8003920: b29a uxth r2, r3 8003922: 68fb ldr r3, [r7, #12] 8003924: 855a strh r2, [r3, #42] ; 0x2a if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 8003926: 68fb ldr r3, [r7, #12] 8003928: 8d5b ldrh r3, [r3, #42] ; 0x2a 800392a: b29b uxth r3, r3 800392c: 2b00 cmp r3, #0 800392e: d034 beq.n 800399a 8003930: 68fb ldr r3, [r7, #12] 8003932: 8d1b ldrh r3, [r3, #40] ; 0x28 8003934: 2b00 cmp r3, #0 8003936: d130 bne.n 800399a { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) 8003938: 697b ldr r3, [r7, #20] 800393a: 9300 str r3, [sp, #0] 800393c: 6a3b ldr r3, [r7, #32] 800393e: 2200 movs r2, #0 8003940: 2180 movs r1, #128 ; 0x80 8003942: 68f8 ldr r0, [r7, #12] 8003944: f000 fb56 bl 8003ff4 8003948: 4603 mov r3, r0 800394a: 2b00 cmp r3, #0 800394c: d001 beq.n 8003952 { return HAL_ERROR; 800394e: 2301 movs r3, #1 8003950: e04d b.n 80039ee } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8003952: 68fb ldr r3, [r7, #12] 8003954: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003956: b29b uxth r3, r3 8003958: 2bff cmp r3, #255 ; 0xff 800395a: d90e bls.n 800397a { hi2c->XferSize = MAX_NBYTE_SIZE; 800395c: 68fb ldr r3, [r7, #12] 800395e: 22ff movs r2, #255 ; 0xff 8003960: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 8003962: 68fb ldr r3, [r7, #12] 8003964: 8d1b ldrh r3, [r3, #40] ; 0x28 8003966: b2da uxtb r2, r3 8003968: 8979 ldrh r1, [r7, #10] 800396a: 2300 movs r3, #0 800396c: 9300 str r3, [sp, #0] 800396e: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003972: 68f8 ldr r0, [r7, #12] 8003974: f000 fcdc bl 8004330 8003978: e00f b.n 800399a I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 800397a: 68fb ldr r3, [r7, #12] 800397c: 8d5b ldrh r3, [r3, #42] ; 0x2a 800397e: b29a uxth r2, r3 8003980: 68fb ldr r3, [r7, #12] 8003982: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 8003984: 68fb ldr r3, [r7, #12] 8003986: 8d1b ldrh r3, [r3, #40] ; 0x28 8003988: b2da uxtb r2, r3 800398a: 8979 ldrh r1, [r7, #10] 800398c: 2300 movs r3, #0 800398e: 9300 str r3, [sp, #0] 8003990: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8003994: 68f8 ldr r0, [r7, #12] 8003996: f000 fccb bl 8004330 while (hi2c->XferCount > 0U) 800399a: 68fb ldr r3, [r7, #12] 800399c: 8d5b ldrh r3, [r3, #42] ; 0x2a 800399e: b29b uxth r3, r3 80039a0: 2b00 cmp r3, #0 80039a2: d19d bne.n 80038e0 } } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 80039a4: 697a ldr r2, [r7, #20] 80039a6: 6a39 ldr r1, [r7, #32] 80039a8: 68f8 ldr r0, [r7, #12] 80039aa: f000 fba3 bl 80040f4 80039ae: 4603 mov r3, r0 80039b0: 2b00 cmp r3, #0 80039b2: d001 beq.n 80039b8 { return HAL_ERROR; 80039b4: 2301 movs r3, #1 80039b6: e01a b.n 80039ee } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 80039b8: 68fb ldr r3, [r7, #12] 80039ba: 681b ldr r3, [r3, #0] 80039bc: 2220 movs r2, #32 80039be: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80039c0: 68fb ldr r3, [r7, #12] 80039c2: 681b ldr r3, [r3, #0] 80039c4: 6859 ldr r1, [r3, #4] 80039c6: 68fb ldr r3, [r7, #12] 80039c8: 681a ldr r2, [r3, #0] 80039ca: 4b0c ldr r3, [pc, #48] ; (80039fc ) 80039cc: 400b ands r3, r1 80039ce: 6053 str r3, [r2, #4] hi2c->State = HAL_I2C_STATE_READY; 80039d0: 68fb ldr r3, [r7, #12] 80039d2: 2220 movs r2, #32 80039d4: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 80039d8: 68fb ldr r3, [r7, #12] 80039da: 2200 movs r2, #0 80039dc: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80039e0: 68fb ldr r3, [r7, #12] 80039e2: 2200 movs r2, #0 80039e4: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; 80039e8: 2300 movs r3, #0 80039ea: e000 b.n 80039ee } else { return HAL_BUSY; 80039ec: 2302 movs r3, #2 } } 80039ee: 4618 mov r0, r3 80039f0: 3718 adds r7, #24 80039f2: 46bd mov sp, r7 80039f4: bd80 pop {r7, pc} 80039f6: bf00 nop 80039f8: 80002400 .word 0x80002400 80039fc: fe00e800 .word 0xfe00e800 08003a00 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8003a00: b580 push {r7, lr} 8003a02: b088 sub sp, #32 8003a04: af02 add r7, sp, #8 8003a06: 60f8 str r0, [r7, #12] 8003a08: 4608 mov r0, r1 8003a0a: 4611 mov r1, r2 8003a0c: 461a mov r2, r3 8003a0e: 4603 mov r3, r0 8003a10: 817b strh r3, [r7, #10] 8003a12: 460b mov r3, r1 8003a14: 813b strh r3, [r7, #8] 8003a16: 4613 mov r3, r2 8003a18: 80fb strh r3, [r7, #6] uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 8003a1a: 68fb ldr r3, [r7, #12] 8003a1c: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 8003a20: b2db uxtb r3, r3 8003a22: 2b20 cmp r3, #32 8003a24: f040 80f9 bne.w 8003c1a { if ((pData == NULL) || (Size == 0U)) 8003a28: 6a3b ldr r3, [r7, #32] 8003a2a: 2b00 cmp r3, #0 8003a2c: d002 beq.n 8003a34 8003a2e: 8cbb ldrh r3, [r7, #36] ; 0x24 8003a30: 2b00 cmp r3, #0 8003a32: d105 bne.n 8003a40 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 8003a34: 68fb ldr r3, [r7, #12] 8003a36: f44f 7200 mov.w r2, #512 ; 0x200 8003a3a: 645a str r2, [r3, #68] ; 0x44 return HAL_ERROR; 8003a3c: 2301 movs r3, #1 8003a3e: e0ed b.n 8003c1c } /* Process Locked */ __HAL_LOCK(hi2c); 8003a40: 68fb ldr r3, [r7, #12] 8003a42: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 8003a46: 2b01 cmp r3, #1 8003a48: d101 bne.n 8003a4e 8003a4a: 2302 movs r3, #2 8003a4c: e0e6 b.n 8003c1c 8003a4e: 68fb ldr r3, [r7, #12] 8003a50: 2201 movs r2, #1 8003a52: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8003a56: f7fe fc05 bl 8002264 8003a5a: 6178 str r0, [r7, #20] if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) 8003a5c: 697b ldr r3, [r7, #20] 8003a5e: 9300 str r3, [sp, #0] 8003a60: 2319 movs r3, #25 8003a62: 2201 movs r2, #1 8003a64: f44f 4100 mov.w r1, #32768 ; 0x8000 8003a68: 68f8 ldr r0, [r7, #12] 8003a6a: f000 fac3 bl 8003ff4 8003a6e: 4603 mov r3, r0 8003a70: 2b00 cmp r3, #0 8003a72: d001 beq.n 8003a78 { return HAL_ERROR; 8003a74: 2301 movs r3, #1 8003a76: e0d1 b.n 8003c1c } hi2c->State = HAL_I2C_STATE_BUSY_TX; 8003a78: 68fb ldr r3, [r7, #12] 8003a7a: 2221 movs r2, #33 ; 0x21 8003a7c: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_MEM; 8003a80: 68fb ldr r3, [r7, #12] 8003a82: 2240 movs r2, #64 ; 0x40 8003a84: f883 2042 strb.w r2, [r3, #66] ; 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8003a88: 68fb ldr r3, [r7, #12] 8003a8a: 2200 movs r2, #0 8003a8c: 645a str r2, [r3, #68] ; 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8003a8e: 68fb ldr r3, [r7, #12] 8003a90: 6a3a ldr r2, [r7, #32] 8003a92: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 8003a94: 68fb ldr r3, [r7, #12] 8003a96: 8cba ldrh r2, [r7, #36] ; 0x24 8003a98: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferISR = NULL; 8003a9a: 68fb ldr r3, [r7, #12] 8003a9c: 2200 movs r2, #0 8003a9e: 635a str r2, [r3, #52] ; 0x34 /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 8003aa0: 88f8 ldrh r0, [r7, #6] 8003aa2: 893a ldrh r2, [r7, #8] 8003aa4: 8979 ldrh r1, [r7, #10] 8003aa6: 697b ldr r3, [r7, #20] 8003aa8: 9301 str r3, [sp, #4] 8003aaa: 6abb ldr r3, [r7, #40] ; 0x28 8003aac: 9300 str r3, [sp, #0] 8003aae: 4603 mov r3, r0 8003ab0: 68f8 ldr r0, [r7, #12] 8003ab2: f000 f9d3 bl 8003e5c 8003ab6: 4603 mov r3, r0 8003ab8: 2b00 cmp r3, #0 8003aba: d005 beq.n 8003ac8 { /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8003abc: 68fb ldr r3, [r7, #12] 8003abe: 2200 movs r2, #0 8003ac0: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 8003ac4: 2301 movs r3, #1 8003ac6: e0a9 b.n 8003c1c } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8003ac8: 68fb ldr r3, [r7, #12] 8003aca: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003acc: b29b uxth r3, r3 8003ace: 2bff cmp r3, #255 ; 0xff 8003ad0: d90e bls.n 8003af0 { hi2c->XferSize = MAX_NBYTE_SIZE; 8003ad2: 68fb ldr r3, [r7, #12] 8003ad4: 22ff movs r2, #255 ; 0xff 8003ad6: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 8003ad8: 68fb ldr r3, [r7, #12] 8003ada: 8d1b ldrh r3, [r3, #40] ; 0x28 8003adc: b2da uxtb r2, r3 8003ade: 8979 ldrh r1, [r7, #10] 8003ae0: 2300 movs r3, #0 8003ae2: 9300 str r3, [sp, #0] 8003ae4: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003ae8: 68f8 ldr r0, [r7, #12] 8003aea: f000 fc21 bl 8004330 8003aee: e00f b.n 8003b10 } else { hi2c->XferSize = hi2c->XferCount; 8003af0: 68fb ldr r3, [r7, #12] 8003af2: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003af4: b29a uxth r2, r3 8003af6: 68fb ldr r3, [r7, #12] 8003af8: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 8003afa: 68fb ldr r3, [r7, #12] 8003afc: 8d1b ldrh r3, [r3, #40] ; 0x28 8003afe: b2da uxtb r2, r3 8003b00: 8979 ldrh r1, [r7, #10] 8003b02: 2300 movs r3, #0 8003b04: 9300 str r3, [sp, #0] 8003b06: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8003b0a: 68f8 ldr r0, [r7, #12] 8003b0c: f000 fc10 bl 8004330 } do { /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8003b10: 697a ldr r2, [r7, #20] 8003b12: 6ab9 ldr r1, [r7, #40] ; 0x28 8003b14: 68f8 ldr r0, [r7, #12] 8003b16: f000 faad bl 8004074 8003b1a: 4603 mov r3, r0 8003b1c: 2b00 cmp r3, #0 8003b1e: d001 beq.n 8003b24 { return HAL_ERROR; 8003b20: 2301 movs r3, #1 8003b22: e07b b.n 8003c1c } /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 8003b24: 68fb ldr r3, [r7, #12] 8003b26: 6a5b ldr r3, [r3, #36] ; 0x24 8003b28: 781a ldrb r2, [r3, #0] 8003b2a: 68fb ldr r3, [r7, #12] 8003b2c: 681b ldr r3, [r3, #0] 8003b2e: 629a str r2, [r3, #40] ; 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003b30: 68fb ldr r3, [r7, #12] 8003b32: 6a5b ldr r3, [r3, #36] ; 0x24 8003b34: 1c5a adds r2, r3, #1 8003b36: 68fb ldr r3, [r7, #12] 8003b38: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount--; 8003b3a: 68fb ldr r3, [r7, #12] 8003b3c: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003b3e: b29b uxth r3, r3 8003b40: 3b01 subs r3, #1 8003b42: b29a uxth r2, r3 8003b44: 68fb ldr r3, [r7, #12] 8003b46: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize--; 8003b48: 68fb ldr r3, [r7, #12] 8003b4a: 8d1b ldrh r3, [r3, #40] ; 0x28 8003b4c: 3b01 subs r3, #1 8003b4e: b29a uxth r2, r3 8003b50: 68fb ldr r3, [r7, #12] 8003b52: 851a strh r2, [r3, #40] ; 0x28 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 8003b54: 68fb ldr r3, [r7, #12] 8003b56: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003b58: b29b uxth r3, r3 8003b5a: 2b00 cmp r3, #0 8003b5c: d034 beq.n 8003bc8 8003b5e: 68fb ldr r3, [r7, #12] 8003b60: 8d1b ldrh r3, [r3, #40] ; 0x28 8003b62: 2b00 cmp r3, #0 8003b64: d130 bne.n 8003bc8 { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) 8003b66: 697b ldr r3, [r7, #20] 8003b68: 9300 str r3, [sp, #0] 8003b6a: 6abb ldr r3, [r7, #40] ; 0x28 8003b6c: 2200 movs r2, #0 8003b6e: 2180 movs r1, #128 ; 0x80 8003b70: 68f8 ldr r0, [r7, #12] 8003b72: f000 fa3f bl 8003ff4 8003b76: 4603 mov r3, r0 8003b78: 2b00 cmp r3, #0 8003b7a: d001 beq.n 8003b80 { return HAL_ERROR; 8003b7c: 2301 movs r3, #1 8003b7e: e04d b.n 8003c1c } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8003b80: 68fb ldr r3, [r7, #12] 8003b82: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003b84: b29b uxth r3, r3 8003b86: 2bff cmp r3, #255 ; 0xff 8003b88: d90e bls.n 8003ba8 { hi2c->XferSize = MAX_NBYTE_SIZE; 8003b8a: 68fb ldr r3, [r7, #12] 8003b8c: 22ff movs r2, #255 ; 0xff 8003b8e: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 8003b90: 68fb ldr r3, [r7, #12] 8003b92: 8d1b ldrh r3, [r3, #40] ; 0x28 8003b94: b2da uxtb r2, r3 8003b96: 8979 ldrh r1, [r7, #10] 8003b98: 2300 movs r3, #0 8003b9a: 9300 str r3, [sp, #0] 8003b9c: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003ba0: 68f8 ldr r0, [r7, #12] 8003ba2: f000 fbc5 bl 8004330 8003ba6: e00f b.n 8003bc8 I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 8003ba8: 68fb ldr r3, [r7, #12] 8003baa: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003bac: b29a uxth r2, r3 8003bae: 68fb ldr r3, [r7, #12] 8003bb0: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 8003bb2: 68fb ldr r3, [r7, #12] 8003bb4: 8d1b ldrh r3, [r3, #40] ; 0x28 8003bb6: b2da uxtb r2, r3 8003bb8: 8979 ldrh r1, [r7, #10] 8003bba: 2300 movs r3, #0 8003bbc: 9300 str r3, [sp, #0] 8003bbe: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8003bc2: 68f8 ldr r0, [r7, #12] 8003bc4: f000 fbb4 bl 8004330 I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); 8003bc8: 68fb ldr r3, [r7, #12] 8003bca: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003bcc: b29b uxth r3, r3 8003bce: 2b00 cmp r3, #0 8003bd0: d19e bne.n 8003b10 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8003bd2: 697a ldr r2, [r7, #20] 8003bd4: 6ab9 ldr r1, [r7, #40] ; 0x28 8003bd6: 68f8 ldr r0, [r7, #12] 8003bd8: f000 fa8c bl 80040f4 8003bdc: 4603 mov r3, r0 8003bde: 2b00 cmp r3, #0 8003be0: d001 beq.n 8003be6 { return HAL_ERROR; 8003be2: 2301 movs r3, #1 8003be4: e01a b.n 8003c1c } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8003be6: 68fb ldr r3, [r7, #12] 8003be8: 681b ldr r3, [r3, #0] 8003bea: 2220 movs r2, #32 8003bec: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8003bee: 68fb ldr r3, [r7, #12] 8003bf0: 681b ldr r3, [r3, #0] 8003bf2: 6859 ldr r1, [r3, #4] 8003bf4: 68fb ldr r3, [r7, #12] 8003bf6: 681a ldr r2, [r3, #0] 8003bf8: 4b0a ldr r3, [pc, #40] ; (8003c24 ) 8003bfa: 400b ands r3, r1 8003bfc: 6053 str r3, [r2, #4] hi2c->State = HAL_I2C_STATE_READY; 8003bfe: 68fb ldr r3, [r7, #12] 8003c00: 2220 movs r2, #32 8003c02: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8003c06: 68fb ldr r3, [r7, #12] 8003c08: 2200 movs r2, #0 8003c0a: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8003c0e: 68fb ldr r3, [r7, #12] 8003c10: 2200 movs r2, #0 8003c12: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; 8003c16: 2300 movs r3, #0 8003c18: e000 b.n 8003c1c } else { return HAL_BUSY; 8003c1a: 2302 movs r3, #2 } } 8003c1c: 4618 mov r0, r3 8003c1e: 3718 adds r7, #24 8003c20: 46bd mov sp, r7 8003c22: bd80 pop {r7, pc} 8003c24: fe00e800 .word 0xfe00e800 08003c28 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8003c28: b580 push {r7, lr} 8003c2a: b088 sub sp, #32 8003c2c: af02 add r7, sp, #8 8003c2e: 60f8 str r0, [r7, #12] 8003c30: 4608 mov r0, r1 8003c32: 4611 mov r1, r2 8003c34: 461a mov r2, r3 8003c36: 4603 mov r3, r0 8003c38: 817b strh r3, [r7, #10] 8003c3a: 460b mov r3, r1 8003c3c: 813b strh r3, [r7, #8] 8003c3e: 4613 mov r3, r2 8003c40: 80fb strh r3, [r7, #6] uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 8003c42: 68fb ldr r3, [r7, #12] 8003c44: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 8003c48: b2db uxtb r3, r3 8003c4a: 2b20 cmp r3, #32 8003c4c: f040 80fd bne.w 8003e4a { if ((pData == NULL) || (Size == 0U)) 8003c50: 6a3b ldr r3, [r7, #32] 8003c52: 2b00 cmp r3, #0 8003c54: d002 beq.n 8003c5c 8003c56: 8cbb ldrh r3, [r7, #36] ; 0x24 8003c58: 2b00 cmp r3, #0 8003c5a: d105 bne.n 8003c68 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 8003c5c: 68fb ldr r3, [r7, #12] 8003c5e: f44f 7200 mov.w r2, #512 ; 0x200 8003c62: 645a str r2, [r3, #68] ; 0x44 return HAL_ERROR; 8003c64: 2301 movs r3, #1 8003c66: e0f1 b.n 8003e4c } /* Process Locked */ __HAL_LOCK(hi2c); 8003c68: 68fb ldr r3, [r7, #12] 8003c6a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 8003c6e: 2b01 cmp r3, #1 8003c70: d101 bne.n 8003c76 8003c72: 2302 movs r3, #2 8003c74: e0ea b.n 8003e4c 8003c76: 68fb ldr r3, [r7, #12] 8003c78: 2201 movs r2, #1 8003c7a: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8003c7e: f7fe faf1 bl 8002264 8003c82: 6178 str r0, [r7, #20] if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) 8003c84: 697b ldr r3, [r7, #20] 8003c86: 9300 str r3, [sp, #0] 8003c88: 2319 movs r3, #25 8003c8a: 2201 movs r2, #1 8003c8c: f44f 4100 mov.w r1, #32768 ; 0x8000 8003c90: 68f8 ldr r0, [r7, #12] 8003c92: f000 f9af bl 8003ff4 8003c96: 4603 mov r3, r0 8003c98: 2b00 cmp r3, #0 8003c9a: d001 beq.n 8003ca0 { return HAL_ERROR; 8003c9c: 2301 movs r3, #1 8003c9e: e0d5 b.n 8003e4c } hi2c->State = HAL_I2C_STATE_BUSY_RX; 8003ca0: 68fb ldr r3, [r7, #12] 8003ca2: 2222 movs r2, #34 ; 0x22 8003ca4: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_MEM; 8003ca8: 68fb ldr r3, [r7, #12] 8003caa: 2240 movs r2, #64 ; 0x40 8003cac: f883 2042 strb.w r2, [r3, #66] ; 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8003cb0: 68fb ldr r3, [r7, #12] 8003cb2: 2200 movs r2, #0 8003cb4: 645a str r2, [r3, #68] ; 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8003cb6: 68fb ldr r3, [r7, #12] 8003cb8: 6a3a ldr r2, [r7, #32] 8003cba: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; 8003cbc: 68fb ldr r3, [r7, #12] 8003cbe: 8cba ldrh r2, [r7, #36] ; 0x24 8003cc0: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferISR = NULL; 8003cc2: 68fb ldr r3, [r7, #12] 8003cc4: 2200 movs r2, #0 8003cc6: 635a str r2, [r3, #52] ; 0x34 /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 8003cc8: 88f8 ldrh r0, [r7, #6] 8003cca: 893a ldrh r2, [r7, #8] 8003ccc: 8979 ldrh r1, [r7, #10] 8003cce: 697b ldr r3, [r7, #20] 8003cd0: 9301 str r3, [sp, #4] 8003cd2: 6abb ldr r3, [r7, #40] ; 0x28 8003cd4: 9300 str r3, [sp, #0] 8003cd6: 4603 mov r3, r0 8003cd8: 68f8 ldr r0, [r7, #12] 8003cda: f000 f913 bl 8003f04 8003cde: 4603 mov r3, r0 8003ce0: 2b00 cmp r3, #0 8003ce2: d005 beq.n 8003cf0 { /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8003ce4: 68fb ldr r3, [r7, #12] 8003ce6: 2200 movs r2, #0 8003ce8: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 8003cec: 2301 movs r3, #1 8003cee: e0ad b.n 8003e4c } /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8003cf0: 68fb ldr r3, [r7, #12] 8003cf2: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003cf4: b29b uxth r3, r3 8003cf6: 2bff cmp r3, #255 ; 0xff 8003cf8: d90e bls.n 8003d18 { hi2c->XferSize = MAX_NBYTE_SIZE; 8003cfa: 68fb ldr r3, [r7, #12] 8003cfc: 22ff movs r2, #255 ; 0xff 8003cfe: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 8003d00: 68fb ldr r3, [r7, #12] 8003d02: 8d1b ldrh r3, [r3, #40] ; 0x28 8003d04: b2da uxtb r2, r3 8003d06: 8979 ldrh r1, [r7, #10] 8003d08: 4b52 ldr r3, [pc, #328] ; (8003e54 ) 8003d0a: 9300 str r3, [sp, #0] 8003d0c: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003d10: 68f8 ldr r0, [r7, #12] 8003d12: f000 fb0d bl 8004330 8003d16: e00f b.n 8003d38 I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; 8003d18: 68fb ldr r3, [r7, #12] 8003d1a: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003d1c: b29a uxth r2, r3 8003d1e: 68fb ldr r3, [r7, #12] 8003d20: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 8003d22: 68fb ldr r3, [r7, #12] 8003d24: 8d1b ldrh r3, [r3, #40] ; 0x28 8003d26: b2da uxtb r2, r3 8003d28: 8979 ldrh r1, [r7, #10] 8003d2a: 4b4a ldr r3, [pc, #296] ; (8003e54 ) 8003d2c: 9300 str r3, [sp, #0] 8003d2e: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8003d32: 68f8 ldr r0, [r7, #12] 8003d34: f000 fafc bl 8004330 } do { /* Wait until RXNE flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) 8003d38: 697b ldr r3, [r7, #20] 8003d3a: 9300 str r3, [sp, #0] 8003d3c: 6abb ldr r3, [r7, #40] ; 0x28 8003d3e: 2200 movs r2, #0 8003d40: 2104 movs r1, #4 8003d42: 68f8 ldr r0, [r7, #12] 8003d44: f000 f956 bl 8003ff4 8003d48: 4603 mov r3, r0 8003d4a: 2b00 cmp r3, #0 8003d4c: d001 beq.n 8003d52 { return HAL_ERROR; 8003d4e: 2301 movs r3, #1 8003d50: e07c b.n 8003e4c } /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8003d52: 68fb ldr r3, [r7, #12] 8003d54: 681b ldr r3, [r3, #0] 8003d56: 6a5a ldr r2, [r3, #36] ; 0x24 8003d58: 68fb ldr r3, [r7, #12] 8003d5a: 6a5b ldr r3, [r3, #36] ; 0x24 8003d5c: b2d2 uxtb r2, r2 8003d5e: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8003d60: 68fb ldr r3, [r7, #12] 8003d62: 6a5b ldr r3, [r3, #36] ; 0x24 8003d64: 1c5a adds r2, r3, #1 8003d66: 68fb ldr r3, [r7, #12] 8003d68: 625a str r2, [r3, #36] ; 0x24 hi2c->XferSize--; 8003d6a: 68fb ldr r3, [r7, #12] 8003d6c: 8d1b ldrh r3, [r3, #40] ; 0x28 8003d6e: 3b01 subs r3, #1 8003d70: b29a uxth r2, r3 8003d72: 68fb ldr r3, [r7, #12] 8003d74: 851a strh r2, [r3, #40] ; 0x28 hi2c->XferCount--; 8003d76: 68fb ldr r3, [r7, #12] 8003d78: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003d7a: b29b uxth r3, r3 8003d7c: 3b01 subs r3, #1 8003d7e: b29a uxth r2, r3 8003d80: 68fb ldr r3, [r7, #12] 8003d82: 855a strh r2, [r3, #42] ; 0x2a if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 8003d84: 68fb ldr r3, [r7, #12] 8003d86: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003d88: b29b uxth r3, r3 8003d8a: 2b00 cmp r3, #0 8003d8c: d034 beq.n 8003df8 8003d8e: 68fb ldr r3, [r7, #12] 8003d90: 8d1b ldrh r3, [r3, #40] ; 0x28 8003d92: 2b00 cmp r3, #0 8003d94: d130 bne.n 8003df8 { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) 8003d96: 697b ldr r3, [r7, #20] 8003d98: 9300 str r3, [sp, #0] 8003d9a: 6abb ldr r3, [r7, #40] ; 0x28 8003d9c: 2200 movs r2, #0 8003d9e: 2180 movs r1, #128 ; 0x80 8003da0: 68f8 ldr r0, [r7, #12] 8003da2: f000 f927 bl 8003ff4 8003da6: 4603 mov r3, r0 8003da8: 2b00 cmp r3, #0 8003daa: d001 beq.n 8003db0 { return HAL_ERROR; 8003dac: 2301 movs r3, #1 8003dae: e04d b.n 8003e4c } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8003db0: 68fb ldr r3, [r7, #12] 8003db2: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003db4: b29b uxth r3, r3 8003db6: 2bff cmp r3, #255 ; 0xff 8003db8: d90e bls.n 8003dd8 { hi2c->XferSize = MAX_NBYTE_SIZE; 8003dba: 68fb ldr r3, [r7, #12] 8003dbc: 22ff movs r2, #255 ; 0xff 8003dbe: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, 8003dc0: 68fb ldr r3, [r7, #12] 8003dc2: 8d1b ldrh r3, [r3, #40] ; 0x28 8003dc4: b2da uxtb r2, r3 8003dc6: 8979 ldrh r1, [r7, #10] 8003dc8: 2300 movs r3, #0 8003dca: 9300 str r3, [sp, #0] 8003dcc: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003dd0: 68f8 ldr r0, [r7, #12] 8003dd2: f000 faad bl 8004330 8003dd6: e00f b.n 8003df8 I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 8003dd8: 68fb ldr r3, [r7, #12] 8003dda: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003ddc: b29a uxth r2, r3 8003dde: 68fb ldr r3, [r7, #12] 8003de0: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 8003de2: 68fb ldr r3, [r7, #12] 8003de4: 8d1b ldrh r3, [r3, #40] ; 0x28 8003de6: b2da uxtb r2, r3 8003de8: 8979 ldrh r1, [r7, #10] 8003dea: 2300 movs r3, #0 8003dec: 9300 str r3, [sp, #0] 8003dee: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8003df2: 68f8 ldr r0, [r7, #12] 8003df4: f000 fa9c bl 8004330 I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); 8003df8: 68fb ldr r3, [r7, #12] 8003dfa: 8d5b ldrh r3, [r3, #42] ; 0x2a 8003dfc: b29b uxth r3, r3 8003dfe: 2b00 cmp r3, #0 8003e00: d19a bne.n 8003d38 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8003e02: 697a ldr r2, [r7, #20] 8003e04: 6ab9 ldr r1, [r7, #40] ; 0x28 8003e06: 68f8 ldr r0, [r7, #12] 8003e08: f000 f974 bl 80040f4 8003e0c: 4603 mov r3, r0 8003e0e: 2b00 cmp r3, #0 8003e10: d001 beq.n 8003e16 { return HAL_ERROR; 8003e12: 2301 movs r3, #1 8003e14: e01a b.n 8003e4c } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8003e16: 68fb ldr r3, [r7, #12] 8003e18: 681b ldr r3, [r3, #0] 8003e1a: 2220 movs r2, #32 8003e1c: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8003e1e: 68fb ldr r3, [r7, #12] 8003e20: 681b ldr r3, [r3, #0] 8003e22: 6859 ldr r1, [r3, #4] 8003e24: 68fb ldr r3, [r7, #12] 8003e26: 681a ldr r2, [r3, #0] 8003e28: 4b0b ldr r3, [pc, #44] ; (8003e58 ) 8003e2a: 400b ands r3, r1 8003e2c: 6053 str r3, [r2, #4] hi2c->State = HAL_I2C_STATE_READY; 8003e2e: 68fb ldr r3, [r7, #12] 8003e30: 2220 movs r2, #32 8003e32: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8003e36: 68fb ldr r3, [r7, #12] 8003e38: 2200 movs r2, #0 8003e3a: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8003e3e: 68fb ldr r3, [r7, #12] 8003e40: 2200 movs r2, #0 8003e42: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; 8003e46: 2300 movs r3, #0 8003e48: e000 b.n 8003e4c } else { return HAL_BUSY; 8003e4a: 2302 movs r3, #2 } } 8003e4c: 4618 mov r0, r3 8003e4e: 3718 adds r7, #24 8003e50: 46bd mov sp, r7 8003e52: bd80 pop {r7, pc} 8003e54: 80002400 .word 0x80002400 8003e58: fe00e800 .word 0xfe00e800 08003e5c : * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { 8003e5c: b580 push {r7, lr} 8003e5e: b086 sub sp, #24 8003e60: af02 add r7, sp, #8 8003e62: 60f8 str r0, [r7, #12] 8003e64: 4608 mov r0, r1 8003e66: 4611 mov r1, r2 8003e68: 461a mov r2, r3 8003e6a: 4603 mov r3, r0 8003e6c: 817b strh r3, [r7, #10] 8003e6e: 460b mov r3, r1 8003e70: 813b strh r3, [r7, #8] 8003e72: 4613 mov r3, r2 8003e74: 80fb strh r3, [r7, #6] I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 8003e76: 88fb ldrh r3, [r7, #6] 8003e78: b2da uxtb r2, r3 8003e7a: 8979 ldrh r1, [r7, #10] 8003e7c: 4b20 ldr r3, [pc, #128] ; (8003f00 ) 8003e7e: 9300 str r3, [sp, #0] 8003e80: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8003e84: 68f8 ldr r0, [r7, #12] 8003e86: f000 fa53 bl 8004330 /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 8003e8a: 69fa ldr r2, [r7, #28] 8003e8c: 69b9 ldr r1, [r7, #24] 8003e8e: 68f8 ldr r0, [r7, #12] 8003e90: f000 f8f0 bl 8004074 8003e94: 4603 mov r3, r0 8003e96: 2b00 cmp r3, #0 8003e98: d001 beq.n 8003e9e { return HAL_ERROR; 8003e9a: 2301 movs r3, #1 8003e9c: e02c b.n 8003ef8 } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 8003e9e: 88fb ldrh r3, [r7, #6] 8003ea0: 2b01 cmp r3, #1 8003ea2: d105 bne.n 8003eb0 { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8003ea4: 893b ldrh r3, [r7, #8] 8003ea6: b2da uxtb r2, r3 8003ea8: 68fb ldr r3, [r7, #12] 8003eaa: 681b ldr r3, [r3, #0] 8003eac: 629a str r2, [r3, #40] ; 0x28 8003eae: e015 b.n 8003edc } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); 8003eb0: 893b ldrh r3, [r7, #8] 8003eb2: 0a1b lsrs r3, r3, #8 8003eb4: b29b uxth r3, r3 8003eb6: b2da uxtb r2, r3 8003eb8: 68fb ldr r3, [r7, #12] 8003eba: 681b ldr r3, [r3, #0] 8003ebc: 629a str r2, [r3, #40] ; 0x28 /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 8003ebe: 69fa ldr r2, [r7, #28] 8003ec0: 69b9 ldr r1, [r7, #24] 8003ec2: 68f8 ldr r0, [r7, #12] 8003ec4: f000 f8d6 bl 8004074 8003ec8: 4603 mov r3, r0 8003eca: 2b00 cmp r3, #0 8003ecc: d001 beq.n 8003ed2 { return HAL_ERROR; 8003ece: 2301 movs r3, #1 8003ed0: e012 b.n 8003ef8 } /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8003ed2: 893b ldrh r3, [r7, #8] 8003ed4: b2da uxtb r2, r3 8003ed6: 68fb ldr r3, [r7, #12] 8003ed8: 681b ldr r3, [r3, #0] 8003eda: 629a str r2, [r3, #40] ; 0x28 } /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) 8003edc: 69fb ldr r3, [r7, #28] 8003ede: 9300 str r3, [sp, #0] 8003ee0: 69bb ldr r3, [r7, #24] 8003ee2: 2200 movs r2, #0 8003ee4: 2180 movs r1, #128 ; 0x80 8003ee6: 68f8 ldr r0, [r7, #12] 8003ee8: f000 f884 bl 8003ff4 8003eec: 4603 mov r3, r0 8003eee: 2b00 cmp r3, #0 8003ef0: d001 beq.n 8003ef6 { return HAL_ERROR; 8003ef2: 2301 movs r3, #1 8003ef4: e000 b.n 8003ef8 } return HAL_OK; 8003ef6: 2300 movs r3, #0 } 8003ef8: 4618 mov r0, r3 8003efa: 3710 adds r7, #16 8003efc: 46bd mov sp, r7 8003efe: bd80 pop {r7, pc} 8003f00: 80002000 .word 0x80002000 08003f04 : * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { 8003f04: b580 push {r7, lr} 8003f06: b086 sub sp, #24 8003f08: af02 add r7, sp, #8 8003f0a: 60f8 str r0, [r7, #12] 8003f0c: 4608 mov r0, r1 8003f0e: 4611 mov r1, r2 8003f10: 461a mov r2, r3 8003f12: 4603 mov r3, r0 8003f14: 817b strh r3, [r7, #10] 8003f16: 460b mov r3, r1 8003f18: 813b strh r3, [r7, #8] 8003f1a: 4613 mov r3, r2 8003f1c: 80fb strh r3, [r7, #6] I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 8003f1e: 88fb ldrh r3, [r7, #6] 8003f20: b2da uxtb r2, r3 8003f22: 8979 ldrh r1, [r7, #10] 8003f24: 4b20 ldr r3, [pc, #128] ; (8003fa8 ) 8003f26: 9300 str r3, [sp, #0] 8003f28: 2300 movs r3, #0 8003f2a: 68f8 ldr r0, [r7, #12] 8003f2c: f000 fa00 bl 8004330 /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 8003f30: 69fa ldr r2, [r7, #28] 8003f32: 69b9 ldr r1, [r7, #24] 8003f34: 68f8 ldr r0, [r7, #12] 8003f36: f000 f89d bl 8004074 8003f3a: 4603 mov r3, r0 8003f3c: 2b00 cmp r3, #0 8003f3e: d001 beq.n 8003f44 { return HAL_ERROR; 8003f40: 2301 movs r3, #1 8003f42: e02c b.n 8003f9e } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 8003f44: 88fb ldrh r3, [r7, #6] 8003f46: 2b01 cmp r3, #1 8003f48: d105 bne.n 8003f56 { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8003f4a: 893b ldrh r3, [r7, #8] 8003f4c: b2da uxtb r2, r3 8003f4e: 68fb ldr r3, [r7, #12] 8003f50: 681b ldr r3, [r3, #0] 8003f52: 629a str r2, [r3, #40] ; 0x28 8003f54: e015 b.n 8003f82 } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); 8003f56: 893b ldrh r3, [r7, #8] 8003f58: 0a1b lsrs r3, r3, #8 8003f5a: b29b uxth r3, r3 8003f5c: b2da uxtb r2, r3 8003f5e: 68fb ldr r3, [r7, #12] 8003f60: 681b ldr r3, [r3, #0] 8003f62: 629a str r2, [r3, #40] ; 0x28 /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 8003f64: 69fa ldr r2, [r7, #28] 8003f66: 69b9 ldr r1, [r7, #24] 8003f68: 68f8 ldr r0, [r7, #12] 8003f6a: f000 f883 bl 8004074 8003f6e: 4603 mov r3, r0 8003f70: 2b00 cmp r3, #0 8003f72: d001 beq.n 8003f78 { return HAL_ERROR; 8003f74: 2301 movs r3, #1 8003f76: e012 b.n 8003f9e } /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8003f78: 893b ldrh r3, [r7, #8] 8003f7a: b2da uxtb r2, r3 8003f7c: 68fb ldr r3, [r7, #12] 8003f7e: 681b ldr r3, [r3, #0] 8003f80: 629a str r2, [r3, #40] ; 0x28 } /* Wait until TC flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) 8003f82: 69fb ldr r3, [r7, #28] 8003f84: 9300 str r3, [sp, #0] 8003f86: 69bb ldr r3, [r7, #24] 8003f88: 2200 movs r2, #0 8003f8a: 2140 movs r1, #64 ; 0x40 8003f8c: 68f8 ldr r0, [r7, #12] 8003f8e: f000 f831 bl 8003ff4 8003f92: 4603 mov r3, r0 8003f94: 2b00 cmp r3, #0 8003f96: d001 beq.n 8003f9c { return HAL_ERROR; 8003f98: 2301 movs r3, #1 8003f9a: e000 b.n 8003f9e } return HAL_OK; 8003f9c: 2300 movs r3, #0 } 8003f9e: 4618 mov r0, r3 8003fa0: 3710 adds r7, #16 8003fa2: 46bd mov sp, r7 8003fa4: bd80 pop {r7, pc} 8003fa6: bf00 nop 8003fa8: 80002000 .word 0x80002000 08003fac : * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { 8003fac: b480 push {r7} 8003fae: b083 sub sp, #12 8003fb0: af00 add r7, sp, #0 8003fb2: 6078 str r0, [r7, #4] /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) 8003fb4: 687b ldr r3, [r7, #4] 8003fb6: 681b ldr r3, [r3, #0] 8003fb8: 699b ldr r3, [r3, #24] 8003fba: f003 0302 and.w r3, r3, #2 8003fbe: 2b02 cmp r3, #2 8003fc0: d103 bne.n 8003fca { hi2c->Instance->TXDR = 0x00U; 8003fc2: 687b ldr r3, [r7, #4] 8003fc4: 681b ldr r3, [r3, #0] 8003fc6: 2200 movs r2, #0 8003fc8: 629a str r2, [r3, #40] ; 0x28 } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 8003fca: 687b ldr r3, [r7, #4] 8003fcc: 681b ldr r3, [r3, #0] 8003fce: 699b ldr r3, [r3, #24] 8003fd0: f003 0301 and.w r3, r3, #1 8003fd4: 2b01 cmp r3, #1 8003fd6: d007 beq.n 8003fe8 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); 8003fd8: 687b ldr r3, [r7, #4] 8003fda: 681b ldr r3, [r3, #0] 8003fdc: 699a ldr r2, [r3, #24] 8003fde: 687b ldr r3, [r7, #4] 8003fe0: 681b ldr r3, [r3, #0] 8003fe2: f042 0201 orr.w r2, r2, #1 8003fe6: 619a str r2, [r3, #24] } } 8003fe8: bf00 nop 8003fea: 370c adds r7, #12 8003fec: 46bd mov sp, r7 8003fee: f85d 7b04 ldr.w r7, [sp], #4 8003ff2: 4770 bx lr 08003ff4 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { 8003ff4: b580 push {r7, lr} 8003ff6: b084 sub sp, #16 8003ff8: af00 add r7, sp, #0 8003ffa: 60f8 str r0, [r7, #12] 8003ffc: 60b9 str r1, [r7, #8] 8003ffe: 603b str r3, [r7, #0] 8004000: 4613 mov r3, r2 8004002: 71fb strb r3, [r7, #7] while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 8004004: e022 b.n 800404c { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004006: 683b ldr r3, [r7, #0] 8004008: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 800400c: d01e beq.n 800404c { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800400e: f7fe f929 bl 8002264 8004012: 4602 mov r2, r0 8004014: 69bb ldr r3, [r7, #24] 8004016: 1ad3 subs r3, r2, r3 8004018: 683a ldr r2, [r7, #0] 800401a: 429a cmp r2, r3 800401c: d302 bcc.n 8004024 800401e: 683b ldr r3, [r7, #0] 8004020: 2b00 cmp r3, #0 8004022: d113 bne.n 800404c { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8004024: 68fb ldr r3, [r7, #12] 8004026: 6c5b ldr r3, [r3, #68] ; 0x44 8004028: f043 0220 orr.w r2, r3, #32 800402c: 68fb ldr r3, [r7, #12] 800402e: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 8004030: 68fb ldr r3, [r7, #12] 8004032: 2220 movs r2, #32 8004034: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8004038: 68fb ldr r3, [r7, #12] 800403a: 2200 movs r2, #0 800403c: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8004040: 68fb ldr r3, [r7, #12] 8004042: 2200 movs r2, #0 8004044: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 8004048: 2301 movs r3, #1 800404a: e00f b.n 800406c while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 800404c: 68fb ldr r3, [r7, #12] 800404e: 681b ldr r3, [r3, #0] 8004050: 699a ldr r2, [r3, #24] 8004052: 68bb ldr r3, [r7, #8] 8004054: 4013 ands r3, r2 8004056: 68ba ldr r2, [r7, #8] 8004058: 429a cmp r2, r3 800405a: bf0c ite eq 800405c: 2301 moveq r3, #1 800405e: 2300 movne r3, #0 8004060: b2db uxtb r3, r3 8004062: 461a mov r2, r3 8004064: 79fb ldrb r3, [r7, #7] 8004066: 429a cmp r2, r3 8004068: d0cd beq.n 8004006 } } } return HAL_OK; 800406a: 2300 movs r3, #0 } 800406c: 4618 mov r0, r3 800406e: 3710 adds r7, #16 8004070: 46bd mov sp, r7 8004072: bd80 pop {r7, pc} 08004074 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 8004074: b580 push {r7, lr} 8004076: b084 sub sp, #16 8004078: af00 add r7, sp, #0 800407a: 60f8 str r0, [r7, #12] 800407c: 60b9 str r1, [r7, #8] 800407e: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) 8004080: e02c b.n 80040dc { /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) 8004082: 687a ldr r2, [r7, #4] 8004084: 68b9 ldr r1, [r7, #8] 8004086: 68f8 ldr r0, [r7, #12] 8004088: f000 f8dc bl 8004244 800408c: 4603 mov r3, r0 800408e: 2b00 cmp r3, #0 8004090: d001 beq.n 8004096 { return HAL_ERROR; 8004092: 2301 movs r3, #1 8004094: e02a b.n 80040ec } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004096: 68bb ldr r3, [r7, #8] 8004098: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 800409c: d01e beq.n 80040dc { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800409e: f7fe f8e1 bl 8002264 80040a2: 4602 mov r2, r0 80040a4: 687b ldr r3, [r7, #4] 80040a6: 1ad3 subs r3, r2, r3 80040a8: 68ba ldr r2, [r7, #8] 80040aa: 429a cmp r2, r3 80040ac: d302 bcc.n 80040b4 80040ae: 68bb ldr r3, [r7, #8] 80040b0: 2b00 cmp r3, #0 80040b2: d113 bne.n 80040dc { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 80040b4: 68fb ldr r3, [r7, #12] 80040b6: 6c5b ldr r3, [r3, #68] ; 0x44 80040b8: f043 0220 orr.w r2, r3, #32 80040bc: 68fb ldr r3, [r7, #12] 80040be: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 80040c0: 68fb ldr r3, [r7, #12] 80040c2: 2220 movs r2, #32 80040c4: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 80040c8: 68fb ldr r3, [r7, #12] 80040ca: 2200 movs r2, #0 80040cc: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80040d0: 68fb ldr r3, [r7, #12] 80040d2: 2200 movs r2, #0 80040d4: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 80040d8: 2301 movs r3, #1 80040da: e007 b.n 80040ec while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) 80040dc: 68fb ldr r3, [r7, #12] 80040de: 681b ldr r3, [r3, #0] 80040e0: 699b ldr r3, [r3, #24] 80040e2: f003 0302 and.w r3, r3, #2 80040e6: 2b02 cmp r3, #2 80040e8: d1cb bne.n 8004082 } } } return HAL_OK; 80040ea: 2300 movs r3, #0 } 80040ec: 4618 mov r0, r3 80040ee: 3710 adds r7, #16 80040f0: 46bd mov sp, r7 80040f2: bd80 pop {r7, pc} 080040f4 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 80040f4: b580 push {r7, lr} 80040f6: b084 sub sp, #16 80040f8: af00 add r7, sp, #0 80040fa: 60f8 str r0, [r7, #12] 80040fc: 60b9 str r1, [r7, #8] 80040fe: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 8004100: e028 b.n 8004154 { /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) 8004102: 687a ldr r2, [r7, #4] 8004104: 68b9 ldr r1, [r7, #8] 8004106: 68f8 ldr r0, [r7, #12] 8004108: f000 f89c bl 8004244 800410c: 4603 mov r3, r0 800410e: 2b00 cmp r3, #0 8004110: d001 beq.n 8004116 { return HAL_ERROR; 8004112: 2301 movs r3, #1 8004114: e026 b.n 8004164 } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8004116: f7fe f8a5 bl 8002264 800411a: 4602 mov r2, r0 800411c: 687b ldr r3, [r7, #4] 800411e: 1ad3 subs r3, r2, r3 8004120: 68ba ldr r2, [r7, #8] 8004122: 429a cmp r2, r3 8004124: d302 bcc.n 800412c 8004126: 68bb ldr r3, [r7, #8] 8004128: 2b00 cmp r3, #0 800412a: d113 bne.n 8004154 { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 800412c: 68fb ldr r3, [r7, #12] 800412e: 6c5b ldr r3, [r3, #68] ; 0x44 8004130: f043 0220 orr.w r2, r3, #32 8004134: 68fb ldr r3, [r7, #12] 8004136: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 8004138: 68fb ldr r3, [r7, #12] 800413a: 2220 movs r2, #32 800413c: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8004140: 68fb ldr r3, [r7, #12] 8004142: 2200 movs r2, #0 8004144: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8004148: 68fb ldr r3, [r7, #12] 800414a: 2200 movs r2, #0 800414c: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 8004150: 2301 movs r3, #1 8004152: e007 b.n 8004164 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 8004154: 68fb ldr r3, [r7, #12] 8004156: 681b ldr r3, [r3, #0] 8004158: 699b ldr r3, [r3, #24] 800415a: f003 0320 and.w r3, r3, #32 800415e: 2b20 cmp r3, #32 8004160: d1cf bne.n 8004102 } } return HAL_OK; 8004162: 2300 movs r3, #0 } 8004164: 4618 mov r0, r3 8004166: 3710 adds r7, #16 8004168: 46bd mov sp, r7 800416a: bd80 pop {r7, pc} 0800416c : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 800416c: b580 push {r7, lr} 800416e: b084 sub sp, #16 8004170: af00 add r7, sp, #0 8004172: 60f8 str r0, [r7, #12] 8004174: 60b9 str r1, [r7, #8] 8004176: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 8004178: e055 b.n 8004226 { /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) 800417a: 687a ldr r2, [r7, #4] 800417c: 68b9 ldr r1, [r7, #8] 800417e: 68f8 ldr r0, [r7, #12] 8004180: f000 f860 bl 8004244 8004184: 4603 mov r3, r0 8004186: 2b00 cmp r3, #0 8004188: d001 beq.n 800418e { return HAL_ERROR; 800418a: 2301 movs r3, #1 800418c: e053 b.n 8004236 } /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 800418e: 68fb ldr r3, [r7, #12] 8004190: 681b ldr r3, [r3, #0] 8004192: 699b ldr r3, [r3, #24] 8004194: f003 0320 and.w r3, r3, #32 8004198: 2b20 cmp r3, #32 800419a: d129 bne.n 80041f0 { /* Check if an RXNE is pending */ /* Store Last receive data if any */ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) 800419c: 68fb ldr r3, [r7, #12] 800419e: 681b ldr r3, [r3, #0] 80041a0: 699b ldr r3, [r3, #24] 80041a2: f003 0304 and.w r3, r3, #4 80041a6: 2b04 cmp r3, #4 80041a8: d105 bne.n 80041b6 80041aa: 68fb ldr r3, [r7, #12] 80041ac: 8d1b ldrh r3, [r3, #40] ; 0x28 80041ae: 2b00 cmp r3, #0 80041b0: d001 beq.n 80041b6 { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ return HAL_OK; 80041b2: 2300 movs r3, #0 80041b4: e03f b.n 8004236 } else { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 80041b6: 68fb ldr r3, [r7, #12] 80041b8: 681b ldr r3, [r3, #0] 80041ba: 2220 movs r2, #32 80041bc: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80041be: 68fb ldr r3, [r7, #12] 80041c0: 681b ldr r3, [r3, #0] 80041c2: 6859 ldr r1, [r3, #4] 80041c4: 68fb ldr r3, [r7, #12] 80041c6: 681a ldr r2, [r3, #0] 80041c8: 4b1d ldr r3, [pc, #116] ; (8004240 ) 80041ca: 400b ands r3, r1 80041cc: 6053 str r3, [r2, #4] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80041ce: 68fb ldr r3, [r7, #12] 80041d0: 2200 movs r2, #0 80041d2: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 80041d4: 68fb ldr r3, [r7, #12] 80041d6: 2220 movs r2, #32 80041d8: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 80041dc: 68fb ldr r3, [r7, #12] 80041de: 2200 movs r2, #0 80041e0: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80041e4: 68fb ldr r3, [r7, #12] 80041e6: 2200 movs r2, #0 80041e8: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 80041ec: 2301 movs r3, #1 80041ee: e022 b.n 8004236 } } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80041f0: f7fe f838 bl 8002264 80041f4: 4602 mov r2, r0 80041f6: 687b ldr r3, [r7, #4] 80041f8: 1ad3 subs r3, r2, r3 80041fa: 68ba ldr r2, [r7, #8] 80041fc: 429a cmp r2, r3 80041fe: d302 bcc.n 8004206 8004200: 68bb ldr r3, [r7, #8] 8004202: 2b00 cmp r3, #0 8004204: d10f bne.n 8004226 { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8004206: 68fb ldr r3, [r7, #12] 8004208: 6c5b ldr r3, [r3, #68] ; 0x44 800420a: f043 0220 orr.w r2, r3, #32 800420e: 68fb ldr r3, [r7, #12] 8004210: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 8004212: 68fb ldr r3, [r7, #12] 8004214: 2220 movs r2, #32 8004216: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800421a: 68fb ldr r3, [r7, #12] 800421c: 2200 movs r2, #0 800421e: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 8004222: 2301 movs r3, #1 8004224: e007 b.n 8004236 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 8004226: 68fb ldr r3, [r7, #12] 8004228: 681b ldr r3, [r3, #0] 800422a: 699b ldr r3, [r3, #24] 800422c: f003 0304 and.w r3, r3, #4 8004230: 2b04 cmp r3, #4 8004232: d1a2 bne.n 800417a } } return HAL_OK; 8004234: 2300 movs r3, #0 } 8004236: 4618 mov r0, r3 8004238: 3710 adds r7, #16 800423a: 46bd mov sp, r7 800423c: bd80 pop {r7, pc} 800423e: bf00 nop 8004240: fe00e800 .word 0xfe00e800 08004244 : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 8004244: b580 push {r7, lr} 8004246: b084 sub sp, #16 8004248: af00 add r7, sp, #0 800424a: 60f8 str r0, [r7, #12] 800424c: 60b9 str r1, [r7, #8] 800424e: 607a str r2, [r7, #4] if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 8004250: 68fb ldr r3, [r7, #12] 8004252: 681b ldr r3, [r3, #0] 8004254: 699b ldr r3, [r3, #24] 8004256: f003 0310 and.w r3, r3, #16 800425a: 2b10 cmp r3, #16 800425c: d161 bne.n 8004322 { /* In case of Soft End condition, generate the STOP condition */ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 800425e: 68fb ldr r3, [r7, #12] 8004260: 681b ldr r3, [r3, #0] 8004262: 685b ldr r3, [r3, #4] 8004264: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8004268: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800426c: d02b beq.n 80042c6 { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; 800426e: 68fb ldr r3, [r7, #12] 8004270: 681b ldr r3, [r3, #0] 8004272: 685a ldr r2, [r3, #4] 8004274: 68fb ldr r3, [r7, #12] 8004276: 681b ldr r3, [r3, #0] 8004278: f442 4280 orr.w r2, r2, #16384 ; 0x4000 800427c: 605a str r2, [r3, #4] } /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 800427e: e022 b.n 80042c6 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004280: 68bb ldr r3, [r7, #8] 8004282: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8004286: d01e beq.n 80042c6 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8004288: f7fd ffec bl 8002264 800428c: 4602 mov r2, r0 800428e: 687b ldr r3, [r7, #4] 8004290: 1ad3 subs r3, r2, r3 8004292: 68ba ldr r2, [r7, #8] 8004294: 429a cmp r2, r3 8004296: d302 bcc.n 800429e 8004298: 68bb ldr r3, [r7, #8] 800429a: 2b00 cmp r3, #0 800429c: d113 bne.n 80042c6 { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 800429e: 68fb ldr r3, [r7, #12] 80042a0: 6c5b ldr r3, [r3, #68] ; 0x44 80042a2: f043 0220 orr.w r2, r3, #32 80042a6: 68fb ldr r3, [r7, #12] 80042a8: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 80042aa: 68fb ldr r3, [r7, #12] 80042ac: 2220 movs r2, #32 80042ae: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 80042b2: 68fb ldr r3, [r7, #12] 80042b4: 2200 movs r2, #0 80042b6: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80042ba: 68fb ldr r3, [r7, #12] 80042bc: 2200 movs r2, #0 80042be: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 80042c2: 2301 movs r3, #1 80042c4: e02e b.n 8004324 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 80042c6: 68fb ldr r3, [r7, #12] 80042c8: 681b ldr r3, [r3, #0] 80042ca: 699b ldr r3, [r3, #24] 80042cc: f003 0320 and.w r3, r3, #32 80042d0: 2b20 cmp r3, #32 80042d2: d1d5 bne.n 8004280 } } } /* Clear NACKF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80042d4: 68fb ldr r3, [r7, #12] 80042d6: 681b ldr r3, [r3, #0] 80042d8: 2210 movs r2, #16 80042da: 61da str r2, [r3, #28] /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 80042dc: 68fb ldr r3, [r7, #12] 80042de: 681b ldr r3, [r3, #0] 80042e0: 2220 movs r2, #32 80042e2: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80042e4: 68f8 ldr r0, [r7, #12] 80042e6: f7ff fe61 bl 8003fac /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80042ea: 68fb ldr r3, [r7, #12] 80042ec: 681b ldr r3, [r3, #0] 80042ee: 6859 ldr r1, [r3, #4] 80042f0: 68fb ldr r3, [r7, #12] 80042f2: 681a ldr r2, [r3, #0] 80042f4: 4b0d ldr r3, [pc, #52] ; (800432c ) 80042f6: 400b ands r3, r1 80042f8: 6053 str r3, [r2, #4] hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80042fa: 68fb ldr r3, [r7, #12] 80042fc: 6c5b ldr r3, [r3, #68] ; 0x44 80042fe: f043 0204 orr.w r2, r3, #4 8004302: 68fb ldr r3, [r7, #12] 8004304: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 8004306: 68fb ldr r3, [r7, #12] 8004308: 2220 movs r2, #32 800430a: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 800430e: 68fb ldr r3, [r7, #12] 8004310: 2200 movs r2, #0 8004312: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8004316: 68fb ldr r3, [r7, #12] 8004318: 2200 movs r2, #0 800431a: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; 800431e: 2301 movs r3, #1 8004320: e000 b.n 8004324 } return HAL_OK; 8004322: 2300 movs r3, #0 } 8004324: 4618 mov r0, r3 8004326: 3710 adds r7, #16 8004328: 46bd mov sp, r7 800432a: bd80 pop {r7, pc} 800432c: fe00e800 .word 0xfe00e800 08004330 : * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { 8004330: b480 push {r7} 8004332: b085 sub sp, #20 8004334: af00 add r7, sp, #0 8004336: 60f8 str r0, [r7, #12] 8004338: 607b str r3, [r7, #4] 800433a: 460b mov r3, r1 800433c: 817b strh r3, [r7, #10] 800433e: 4613 mov r3, r2 8004340: 727b strb r3, [r7, #9] assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, 8004342: 68fb ldr r3, [r7, #12] 8004344: 681b ldr r3, [r3, #0] 8004346: 685a ldr r2, [r3, #4] 8004348: 69bb ldr r3, [r7, #24] 800434a: 0d5b lsrs r3, r3, #21 800434c: f403 6180 and.w r1, r3, #1024 ; 0x400 8004350: 4b0d ldr r3, [pc, #52] ; (8004388 ) 8004352: 430b orrs r3, r1 8004354: 43db mvns r3, r3 8004356: ea02 0103 and.w r1, r2, r3 800435a: 897b ldrh r3, [r7, #10] 800435c: f3c3 0209 ubfx r2, r3, #0, #10 8004360: 7a7b ldrb r3, [r7, #9] 8004362: 041b lsls r3, r3, #16 8004364: f403 037f and.w r3, r3, #16711680 ; 0xff0000 8004368: 431a orrs r2, r3 800436a: 687b ldr r3, [r7, #4] 800436c: 431a orrs r2, r3 800436e: 69bb ldr r3, [r7, #24] 8004370: 431a orrs r2, r3 8004372: 68fb ldr r3, [r7, #12] 8004374: 681b ldr r3, [r3, #0] 8004376: 430a orrs r2, r1 8004378: 605a str r2, [r3, #4] (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ I2C_CR2_START | I2C_CR2_STOP)), \ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ (uint32_t)Mode | (uint32_t)Request)); } 800437a: bf00 nop 800437c: 3714 adds r7, #20 800437e: 46bd mov sp, r7 8004380: f85d 7b04 ldr.w r7, [sp], #4 8004384: 4770 bx lr 8004386: bf00 nop 8004388: 03ff63ff .word 0x03ff63ff 0800438c : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 800438c: b480 push {r7} 800438e: b083 sub sp, #12 8004390: af00 add r7, sp, #0 8004392: 6078 str r0, [r7, #4] 8004394: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8004396: 687b ldr r3, [r7, #4] 8004398: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 800439c: b2db uxtb r3, r3 800439e: 2b20 cmp r3, #32 80043a0: d138 bne.n 8004414 { /* Process Locked */ __HAL_LOCK(hi2c); 80043a2: 687b ldr r3, [r7, #4] 80043a4: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 80043a8: 2b01 cmp r3, #1 80043aa: d101 bne.n 80043b0 80043ac: 2302 movs r3, #2 80043ae: e032 b.n 8004416 80043b0: 687b ldr r3, [r7, #4] 80043b2: 2201 movs r2, #1 80043b4: f883 2040 strb.w r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 80043b8: 687b ldr r3, [r7, #4] 80043ba: 2224 movs r2, #36 ; 0x24 80043bc: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80043c0: 687b ldr r3, [r7, #4] 80043c2: 681b ldr r3, [r3, #0] 80043c4: 681a ldr r2, [r3, #0] 80043c6: 687b ldr r3, [r7, #4] 80043c8: 681b ldr r3, [r3, #0] 80043ca: f022 0201 bic.w r2, r2, #1 80043ce: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 80043d0: 687b ldr r3, [r7, #4] 80043d2: 681b ldr r3, [r3, #0] 80043d4: 681a ldr r2, [r3, #0] 80043d6: 687b ldr r3, [r7, #4] 80043d8: 681b ldr r3, [r3, #0] 80043da: f422 5280 bic.w r2, r2, #4096 ; 0x1000 80043de: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 80043e0: 687b ldr r3, [r7, #4] 80043e2: 681b ldr r3, [r3, #0] 80043e4: 6819 ldr r1, [r3, #0] 80043e6: 687b ldr r3, [r7, #4] 80043e8: 681b ldr r3, [r3, #0] 80043ea: 683a ldr r2, [r7, #0] 80043ec: 430a orrs r2, r1 80043ee: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 80043f0: 687b ldr r3, [r7, #4] 80043f2: 681b ldr r3, [r3, #0] 80043f4: 681a ldr r2, [r3, #0] 80043f6: 687b ldr r3, [r7, #4] 80043f8: 681b ldr r3, [r3, #0] 80043fa: f042 0201 orr.w r2, r2, #1 80043fe: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8004400: 687b ldr r3, [r7, #4] 8004402: 2220 movs r2, #32 8004404: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8004408: 687b ldr r3, [r7, #4] 800440a: 2200 movs r2, #0 800440c: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; 8004410: 2300 movs r3, #0 8004412: e000 b.n 8004416 } else { return HAL_BUSY; 8004414: 2302 movs r3, #2 } } 8004416: 4618 mov r0, r3 8004418: 370c adds r7, #12 800441a: 46bd mov sp, r7 800441c: f85d 7b04 ldr.w r7, [sp], #4 8004420: 4770 bx lr 08004422 : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8004422: b480 push {r7} 8004424: b085 sub sp, #20 8004426: af00 add r7, sp, #0 8004428: 6078 str r0, [r7, #4] 800442a: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 800442c: 687b ldr r3, [r7, #4] 800442e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 8004432: b2db uxtb r3, r3 8004434: 2b20 cmp r3, #32 8004436: d139 bne.n 80044ac { /* Process Locked */ __HAL_LOCK(hi2c); 8004438: 687b ldr r3, [r7, #4] 800443a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 800443e: 2b01 cmp r3, #1 8004440: d101 bne.n 8004446 8004442: 2302 movs r3, #2 8004444: e033 b.n 80044ae 8004446: 687b ldr r3, [r7, #4] 8004448: 2201 movs r2, #1 800444a: f883 2040 strb.w r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 800444e: 687b ldr r3, [r7, #4] 8004450: 2224 movs r2, #36 ; 0x24 8004452: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8004456: 687b ldr r3, [r7, #4] 8004458: 681b ldr r3, [r3, #0] 800445a: 681a ldr r2, [r3, #0] 800445c: 687b ldr r3, [r7, #4] 800445e: 681b ldr r3, [r3, #0] 8004460: f022 0201 bic.w r2, r2, #1 8004464: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 8004466: 687b ldr r3, [r7, #4] 8004468: 681b ldr r3, [r3, #0] 800446a: 681b ldr r3, [r3, #0] 800446c: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 800446e: 68fb ldr r3, [r7, #12] 8004470: f423 6370 bic.w r3, r3, #3840 ; 0xf00 8004474: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 8004476: 683b ldr r3, [r7, #0] 8004478: 021b lsls r3, r3, #8 800447a: 68fa ldr r2, [r7, #12] 800447c: 4313 orrs r3, r2 800447e: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 8004480: 687b ldr r3, [r7, #4] 8004482: 681b ldr r3, [r3, #0] 8004484: 68fa ldr r2, [r7, #12] 8004486: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8004488: 687b ldr r3, [r7, #4] 800448a: 681b ldr r3, [r3, #0] 800448c: 681a ldr r2, [r3, #0] 800448e: 687b ldr r3, [r7, #4] 8004490: 681b ldr r3, [r3, #0] 8004492: f042 0201 orr.w r2, r2, #1 8004496: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8004498: 687b ldr r3, [r7, #4] 800449a: 2220 movs r2, #32 800449c: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80044a0: 687b ldr r3, [r7, #4] 80044a2: 2200 movs r2, #0 80044a4: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; 80044a8: 2300 movs r3, #0 80044aa: e000 b.n 80044ae } else { return HAL_BUSY; 80044ac: 2302 movs r3, #2 } } 80044ae: 4618 mov r0, r3 80044b0: 3714 adds r7, #20 80044b2: 46bd mov sp, r7 80044b4: f85d 7b04 ldr.w r7, [sp], #4 80044b8: 4770 bx lr ... 080044bc : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80044bc: b580 push {r7, lr} 80044be: f5ad 7d00 sub.w sp, sp, #512 ; 0x200 80044c2: af00 add r7, sp, #0 80044c4: f507 7300 add.w r3, r7, #512 ; 0x200 80044c8: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80044cc: 6018 str r0, [r3, #0] #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) uint32_t pll_config2; #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 80044ce: f507 7300 add.w r3, r7, #512 ; 0x200 80044d2: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80044d6: 681b ldr r3, [r3, #0] 80044d8: 2b00 cmp r3, #0 80044da: d102 bne.n 80044e2 { return HAL_ERROR; 80044dc: 2301 movs r3, #1 80044de: f001 b823 b.w 8005528 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80044e2: f507 7300 add.w r3, r7, #512 ; 0x200 80044e6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80044ea: 681b ldr r3, [r3, #0] 80044ec: 681b ldr r3, [r3, #0] 80044ee: f003 0301 and.w r3, r3, #1 80044f2: 2b00 cmp r3, #0 80044f4: f000 817d beq.w 80047f2 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80044f8: 4bbc ldr r3, [pc, #752] ; (80047ec ) 80044fa: 685b ldr r3, [r3, #4] 80044fc: f003 030c and.w r3, r3, #12 8004500: 2b04 cmp r3, #4 8004502: d00c beq.n 800451e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8004504: 4bb9 ldr r3, [pc, #740] ; (80047ec ) 8004506: 685b ldr r3, [r3, #4] 8004508: f003 030c and.w r3, r3, #12 800450c: 2b08 cmp r3, #8 800450e: d15c bne.n 80045ca 8004510: 4bb6 ldr r3, [pc, #728] ; (80047ec ) 8004512: 685b ldr r3, [r3, #4] 8004514: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004518: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800451c: d155 bne.n 80045ca 800451e: f44f 3300 mov.w r3, #131072 ; 0x20000 8004522: f8c7 31f0 str.w r3, [r7, #496] ; 0x1f0 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004526: f8d7 31f0 ldr.w r3, [r7, #496] ; 0x1f0 800452a: fa93 f3a3 rbit r3, r3 800452e: f8c7 31ec str.w r3, [r7, #492] ; 0x1ec result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8004532: f8d7 31ec ldr.w r3, [r7, #492] ; 0x1ec { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004536: fab3 f383 clz r3, r3 800453a: b2db uxtb r3, r3 800453c: 095b lsrs r3, r3, #5 800453e: b2db uxtb r3, r3 8004540: f043 0301 orr.w r3, r3, #1 8004544: b2db uxtb r3, r3 8004546: 2b01 cmp r3, #1 8004548: d102 bne.n 8004550 800454a: 4ba8 ldr r3, [pc, #672] ; (80047ec ) 800454c: 681b ldr r3, [r3, #0] 800454e: e015 b.n 800457c 8004550: f44f 3300 mov.w r3, #131072 ; 0x20000 8004554: f8c7 31e8 str.w r3, [r7, #488] ; 0x1e8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004558: f8d7 31e8 ldr.w r3, [r7, #488] ; 0x1e8 800455c: fa93 f3a3 rbit r3, r3 8004560: f8c7 31e4 str.w r3, [r7, #484] ; 0x1e4 8004564: f44f 3300 mov.w r3, #131072 ; 0x20000 8004568: f8c7 31e0 str.w r3, [r7, #480] ; 0x1e0 800456c: f8d7 31e0 ldr.w r3, [r7, #480] ; 0x1e0 8004570: fa93 f3a3 rbit r3, r3 8004574: f8c7 31dc str.w r3, [r7, #476] ; 0x1dc 8004578: 4b9c ldr r3, [pc, #624] ; (80047ec ) 800457a: 6a5b ldr r3, [r3, #36] ; 0x24 800457c: f44f 3200 mov.w r2, #131072 ; 0x20000 8004580: f8c7 21d8 str.w r2, [r7, #472] ; 0x1d8 8004584: f8d7 21d8 ldr.w r2, [r7, #472] ; 0x1d8 8004588: fa92 f2a2 rbit r2, r2 800458c: f8c7 21d4 str.w r2, [r7, #468] ; 0x1d4 return result; 8004590: f8d7 21d4 ldr.w r2, [r7, #468] ; 0x1d4 8004594: fab2 f282 clz r2, r2 8004598: b2d2 uxtb r2, r2 800459a: f042 0220 orr.w r2, r2, #32 800459e: b2d2 uxtb r2, r2 80045a0: f002 021f and.w r2, r2, #31 80045a4: 2101 movs r1, #1 80045a6: fa01 f202 lsl.w r2, r1, r2 80045aa: 4013 ands r3, r2 80045ac: 2b00 cmp r3, #0 80045ae: f000 811f beq.w 80047f0 80045b2: f507 7300 add.w r3, r7, #512 ; 0x200 80045b6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80045ba: 681b ldr r3, [r3, #0] 80045bc: 685b ldr r3, [r3, #4] 80045be: 2b00 cmp r3, #0 80045c0: f040 8116 bne.w 80047f0 { return HAL_ERROR; 80045c4: 2301 movs r3, #1 80045c6: f000 bfaf b.w 8005528 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80045ca: f507 7300 add.w r3, r7, #512 ; 0x200 80045ce: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80045d2: 681b ldr r3, [r3, #0] 80045d4: 685b ldr r3, [r3, #4] 80045d6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80045da: d106 bne.n 80045ea 80045dc: 4b83 ldr r3, [pc, #524] ; (80047ec ) 80045de: 681b ldr r3, [r3, #0] 80045e0: 4a82 ldr r2, [pc, #520] ; (80047ec ) 80045e2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80045e6: 6013 str r3, [r2, #0] 80045e8: e036 b.n 8004658 80045ea: f507 7300 add.w r3, r7, #512 ; 0x200 80045ee: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80045f2: 681b ldr r3, [r3, #0] 80045f4: 685b ldr r3, [r3, #4] 80045f6: 2b00 cmp r3, #0 80045f8: d10c bne.n 8004614 80045fa: 4b7c ldr r3, [pc, #496] ; (80047ec ) 80045fc: 681b ldr r3, [r3, #0] 80045fe: 4a7b ldr r2, [pc, #492] ; (80047ec ) 8004600: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8004604: 6013 str r3, [r2, #0] 8004606: 4b79 ldr r3, [pc, #484] ; (80047ec ) 8004608: 681b ldr r3, [r3, #0] 800460a: 4a78 ldr r2, [pc, #480] ; (80047ec ) 800460c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8004610: 6013 str r3, [r2, #0] 8004612: e021 b.n 8004658 8004614: f507 7300 add.w r3, r7, #512 ; 0x200 8004618: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 800461c: 681b ldr r3, [r3, #0] 800461e: 685b ldr r3, [r3, #4] 8004620: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8004624: d10c bne.n 8004640 8004626: 4b71 ldr r3, [pc, #452] ; (80047ec ) 8004628: 681b ldr r3, [r3, #0] 800462a: 4a70 ldr r2, [pc, #448] ; (80047ec ) 800462c: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8004630: 6013 str r3, [r2, #0] 8004632: 4b6e ldr r3, [pc, #440] ; (80047ec ) 8004634: 681b ldr r3, [r3, #0] 8004636: 4a6d ldr r2, [pc, #436] ; (80047ec ) 8004638: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800463c: 6013 str r3, [r2, #0] 800463e: e00b b.n 8004658 8004640: 4b6a ldr r3, [pc, #424] ; (80047ec ) 8004642: 681b ldr r3, [r3, #0] 8004644: 4a69 ldr r2, [pc, #420] ; (80047ec ) 8004646: f423 3380 bic.w r3, r3, #65536 ; 0x10000 800464a: 6013 str r3, [r2, #0] 800464c: 4b67 ldr r3, [pc, #412] ; (80047ec ) 800464e: 681b ldr r3, [r3, #0] 8004650: 4a66 ldr r2, [pc, #408] ; (80047ec ) 8004652: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8004656: 6013 str r3, [r2, #0] #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) /* Configure the HSE predivision factor --------------------------------*/ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8004658: 4b64 ldr r3, [pc, #400] ; (80047ec ) 800465a: 6adb ldr r3, [r3, #44] ; 0x2c 800465c: f023 020f bic.w r2, r3, #15 8004660: f507 7300 add.w r3, r7, #512 ; 0x200 8004664: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8004668: 681b ldr r3, [r3, #0] 800466a: 689b ldr r3, [r3, #8] 800466c: 495f ldr r1, [pc, #380] ; (80047ec ) 800466e: 4313 orrs r3, r2 8004670: 62cb str r3, [r1, #44] ; 0x2c #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8004672: f507 7300 add.w r3, r7, #512 ; 0x200 8004676: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 800467a: 681b ldr r3, [r3, #0] 800467c: 685b ldr r3, [r3, #4] 800467e: 2b00 cmp r3, #0 8004680: d059 beq.n 8004736 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004682: f7fd fdef bl 8002264 8004686: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800468a: e00a b.n 80046a2 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 800468c: f7fd fdea bl 8002264 8004690: 4602 mov r2, r0 8004692: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8004696: 1ad3 subs r3, r2, r3 8004698: 2b64 cmp r3, #100 ; 0x64 800469a: d902 bls.n 80046a2 { return HAL_TIMEOUT; 800469c: 2303 movs r3, #3 800469e: f000 bf43 b.w 8005528 80046a2: f44f 3300 mov.w r3, #131072 ; 0x20000 80046a6: f8c7 31d0 str.w r3, [r7, #464] ; 0x1d0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80046aa: f8d7 31d0 ldr.w r3, [r7, #464] ; 0x1d0 80046ae: fa93 f3a3 rbit r3, r3 80046b2: f8c7 31cc str.w r3, [r7, #460] ; 0x1cc return result; 80046b6: f8d7 31cc ldr.w r3, [r7, #460] ; 0x1cc while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80046ba: fab3 f383 clz r3, r3 80046be: b2db uxtb r3, r3 80046c0: 095b lsrs r3, r3, #5 80046c2: b2db uxtb r3, r3 80046c4: f043 0301 orr.w r3, r3, #1 80046c8: b2db uxtb r3, r3 80046ca: 2b01 cmp r3, #1 80046cc: d102 bne.n 80046d4 80046ce: 4b47 ldr r3, [pc, #284] ; (80047ec ) 80046d0: 681b ldr r3, [r3, #0] 80046d2: e015 b.n 8004700 80046d4: f44f 3300 mov.w r3, #131072 ; 0x20000 80046d8: f8c7 31c8 str.w r3, [r7, #456] ; 0x1c8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80046dc: f8d7 31c8 ldr.w r3, [r7, #456] ; 0x1c8 80046e0: fa93 f3a3 rbit r3, r3 80046e4: f8c7 31c4 str.w r3, [r7, #452] ; 0x1c4 80046e8: f44f 3300 mov.w r3, #131072 ; 0x20000 80046ec: f8c7 31c0 str.w r3, [r7, #448] ; 0x1c0 80046f0: f8d7 31c0 ldr.w r3, [r7, #448] ; 0x1c0 80046f4: fa93 f3a3 rbit r3, r3 80046f8: f8c7 31bc str.w r3, [r7, #444] ; 0x1bc 80046fc: 4b3b ldr r3, [pc, #236] ; (80047ec ) 80046fe: 6a5b ldr r3, [r3, #36] ; 0x24 8004700: f44f 3200 mov.w r2, #131072 ; 0x20000 8004704: f8c7 21b8 str.w r2, [r7, #440] ; 0x1b8 8004708: f8d7 21b8 ldr.w r2, [r7, #440] ; 0x1b8 800470c: fa92 f2a2 rbit r2, r2 8004710: f8c7 21b4 str.w r2, [r7, #436] ; 0x1b4 return result; 8004714: f8d7 21b4 ldr.w r2, [r7, #436] ; 0x1b4 8004718: fab2 f282 clz r2, r2 800471c: b2d2 uxtb r2, r2 800471e: f042 0220 orr.w r2, r2, #32 8004722: b2d2 uxtb r2, r2 8004724: f002 021f and.w r2, r2, #31 8004728: 2101 movs r1, #1 800472a: fa01 f202 lsl.w r2, r1, r2 800472e: 4013 ands r3, r2 8004730: 2b00 cmp r3, #0 8004732: d0ab beq.n 800468c 8004734: e05d b.n 80047f2 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004736: f7fd fd95 bl 8002264 800473a: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800473e: e00a b.n 8004756 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8004740: f7fd fd90 bl 8002264 8004744: 4602 mov r2, r0 8004746: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 800474a: 1ad3 subs r3, r2, r3 800474c: 2b64 cmp r3, #100 ; 0x64 800474e: d902 bls.n 8004756 { return HAL_TIMEOUT; 8004750: 2303 movs r3, #3 8004752: f000 bee9 b.w 8005528 8004756: f44f 3300 mov.w r3, #131072 ; 0x20000 800475a: f8c7 31b0 str.w r3, [r7, #432] ; 0x1b0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800475e: f8d7 31b0 ldr.w r3, [r7, #432] ; 0x1b0 8004762: fa93 f3a3 rbit r3, r3 8004766: f8c7 31ac str.w r3, [r7, #428] ; 0x1ac return result; 800476a: f8d7 31ac ldr.w r3, [r7, #428] ; 0x1ac while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800476e: fab3 f383 clz r3, r3 8004772: b2db uxtb r3, r3 8004774: 095b lsrs r3, r3, #5 8004776: b2db uxtb r3, r3 8004778: f043 0301 orr.w r3, r3, #1 800477c: b2db uxtb r3, r3 800477e: 2b01 cmp r3, #1 8004780: d102 bne.n 8004788 8004782: 4b1a ldr r3, [pc, #104] ; (80047ec ) 8004784: 681b ldr r3, [r3, #0] 8004786: e015 b.n 80047b4 8004788: f44f 3300 mov.w r3, #131072 ; 0x20000 800478c: f8c7 31a8 str.w r3, [r7, #424] ; 0x1a8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004790: f8d7 31a8 ldr.w r3, [r7, #424] ; 0x1a8 8004794: fa93 f3a3 rbit r3, r3 8004798: f8c7 31a4 str.w r3, [r7, #420] ; 0x1a4 800479c: f44f 3300 mov.w r3, #131072 ; 0x20000 80047a0: f8c7 31a0 str.w r3, [r7, #416] ; 0x1a0 80047a4: f8d7 31a0 ldr.w r3, [r7, #416] ; 0x1a0 80047a8: fa93 f3a3 rbit r3, r3 80047ac: f8c7 319c str.w r3, [r7, #412] ; 0x19c 80047b0: 4b0e ldr r3, [pc, #56] ; (80047ec ) 80047b2: 6a5b ldr r3, [r3, #36] ; 0x24 80047b4: f44f 3200 mov.w r2, #131072 ; 0x20000 80047b8: f8c7 2198 str.w r2, [r7, #408] ; 0x198 80047bc: f8d7 2198 ldr.w r2, [r7, #408] ; 0x198 80047c0: fa92 f2a2 rbit r2, r2 80047c4: f8c7 2194 str.w r2, [r7, #404] ; 0x194 return result; 80047c8: f8d7 2194 ldr.w r2, [r7, #404] ; 0x194 80047cc: fab2 f282 clz r2, r2 80047d0: b2d2 uxtb r2, r2 80047d2: f042 0220 orr.w r2, r2, #32 80047d6: b2d2 uxtb r2, r2 80047d8: f002 021f and.w r2, r2, #31 80047dc: 2101 movs r1, #1 80047de: fa01 f202 lsl.w r2, r1, r2 80047e2: 4013 ands r3, r2 80047e4: 2b00 cmp r3, #0 80047e6: d1ab bne.n 8004740 80047e8: e003 b.n 80047f2 80047ea: bf00 nop 80047ec: 40021000 .word 0x40021000 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80047f0: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80047f2: f507 7300 add.w r3, r7, #512 ; 0x200 80047f6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80047fa: 681b ldr r3, [r3, #0] 80047fc: 681b ldr r3, [r3, #0] 80047fe: f003 0302 and.w r3, r3, #2 8004802: 2b00 cmp r3, #0 8004804: f000 817d beq.w 8004b02 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8004808: 4ba6 ldr r3, [pc, #664] ; (8004aa4 ) 800480a: 685b ldr r3, [r3, #4] 800480c: f003 030c and.w r3, r3, #12 8004810: 2b00 cmp r3, #0 8004812: d00b beq.n 800482c || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8004814: 4ba3 ldr r3, [pc, #652] ; (8004aa4 ) 8004816: 685b ldr r3, [r3, #4] 8004818: f003 030c and.w r3, r3, #12 800481c: 2b08 cmp r3, #8 800481e: d172 bne.n 8004906 8004820: 4ba0 ldr r3, [pc, #640] ; (8004aa4 ) 8004822: 685b ldr r3, [r3, #4] 8004824: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004828: 2b00 cmp r3, #0 800482a: d16c bne.n 8004906 800482c: 2302 movs r3, #2 800482e: f8c7 3190 str.w r3, [r7, #400] ; 0x190 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004832: f8d7 3190 ldr.w r3, [r7, #400] ; 0x190 8004836: fa93 f3a3 rbit r3, r3 800483a: f8c7 318c str.w r3, [r7, #396] ; 0x18c return result; 800483e: f8d7 318c ldr.w r3, [r7, #396] ; 0x18c { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004842: fab3 f383 clz r3, r3 8004846: b2db uxtb r3, r3 8004848: 095b lsrs r3, r3, #5 800484a: b2db uxtb r3, r3 800484c: f043 0301 orr.w r3, r3, #1 8004850: b2db uxtb r3, r3 8004852: 2b01 cmp r3, #1 8004854: d102 bne.n 800485c 8004856: 4b93 ldr r3, [pc, #588] ; (8004aa4 ) 8004858: 681b ldr r3, [r3, #0] 800485a: e013 b.n 8004884 800485c: 2302 movs r3, #2 800485e: f8c7 3188 str.w r3, [r7, #392] ; 0x188 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004862: f8d7 3188 ldr.w r3, [r7, #392] ; 0x188 8004866: fa93 f3a3 rbit r3, r3 800486a: f8c7 3184 str.w r3, [r7, #388] ; 0x184 800486e: 2302 movs r3, #2 8004870: f8c7 3180 str.w r3, [r7, #384] ; 0x180 8004874: f8d7 3180 ldr.w r3, [r7, #384] ; 0x180 8004878: fa93 f3a3 rbit r3, r3 800487c: f8c7 317c str.w r3, [r7, #380] ; 0x17c 8004880: 4b88 ldr r3, [pc, #544] ; (8004aa4 ) 8004882: 6a5b ldr r3, [r3, #36] ; 0x24 8004884: 2202 movs r2, #2 8004886: f8c7 2178 str.w r2, [r7, #376] ; 0x178 800488a: f8d7 2178 ldr.w r2, [r7, #376] ; 0x178 800488e: fa92 f2a2 rbit r2, r2 8004892: f8c7 2174 str.w r2, [r7, #372] ; 0x174 return result; 8004896: f8d7 2174 ldr.w r2, [r7, #372] ; 0x174 800489a: fab2 f282 clz r2, r2 800489e: b2d2 uxtb r2, r2 80048a0: f042 0220 orr.w r2, r2, #32 80048a4: b2d2 uxtb r2, r2 80048a6: f002 021f and.w r2, r2, #31 80048aa: 2101 movs r1, #1 80048ac: fa01 f202 lsl.w r2, r1, r2 80048b0: 4013 ands r3, r2 80048b2: 2b00 cmp r3, #0 80048b4: d00a beq.n 80048cc 80048b6: f507 7300 add.w r3, r7, #512 ; 0x200 80048ba: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80048be: 681b ldr r3, [r3, #0] 80048c0: 691b ldr r3, [r3, #16] 80048c2: 2b01 cmp r3, #1 80048c4: d002 beq.n 80048cc { return HAL_ERROR; 80048c6: 2301 movs r3, #1 80048c8: f000 be2e b.w 8005528 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80048cc: 4b75 ldr r3, [pc, #468] ; (8004aa4 ) 80048ce: 681b ldr r3, [r3, #0] 80048d0: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80048d4: f507 7300 add.w r3, r7, #512 ; 0x200 80048d8: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80048dc: 681b ldr r3, [r3, #0] 80048de: 695b ldr r3, [r3, #20] 80048e0: 21f8 movs r1, #248 ; 0xf8 80048e2: f8c7 1170 str.w r1, [r7, #368] ; 0x170 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80048e6: f8d7 1170 ldr.w r1, [r7, #368] ; 0x170 80048ea: fa91 f1a1 rbit r1, r1 80048ee: f8c7 116c str.w r1, [r7, #364] ; 0x16c return result; 80048f2: f8d7 116c ldr.w r1, [r7, #364] ; 0x16c 80048f6: fab1 f181 clz r1, r1 80048fa: b2c9 uxtb r1, r1 80048fc: 408b lsls r3, r1 80048fe: 4969 ldr r1, [pc, #420] ; (8004aa4 ) 8004900: 4313 orrs r3, r2 8004902: 600b str r3, [r1, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004904: e0fd b.n 8004b02 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8004906: f507 7300 add.w r3, r7, #512 ; 0x200 800490a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 800490e: 681b ldr r3, [r3, #0] 8004910: 691b ldr r3, [r3, #16] 8004912: 2b00 cmp r3, #0 8004914: f000 8088 beq.w 8004a28 8004918: 2301 movs r3, #1 800491a: f8c7 3168 str.w r3, [r7, #360] ; 0x168 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800491e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168 8004922: fa93 f3a3 rbit r3, r3 8004926: f8c7 3164 str.w r3, [r7, #356] ; 0x164 return result; 800492a: f8d7 3164 ldr.w r3, [r7, #356] ; 0x164 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800492e: fab3 f383 clz r3, r3 8004932: b2db uxtb r3, r3 8004934: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 8004938: f503 1384 add.w r3, r3, #1081344 ; 0x108000 800493c: 009b lsls r3, r3, #2 800493e: 461a mov r2, r3 8004940: 2301 movs r3, #1 8004942: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004944: f7fd fc8e bl 8002264 8004948: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800494c: e00a b.n 8004964 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800494e: f7fd fc89 bl 8002264 8004952: 4602 mov r2, r0 8004954: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8004958: 1ad3 subs r3, r2, r3 800495a: 2b02 cmp r3, #2 800495c: d902 bls.n 8004964 { return HAL_TIMEOUT; 800495e: 2303 movs r3, #3 8004960: f000 bde2 b.w 8005528 8004964: 2302 movs r3, #2 8004966: f8c7 3160 str.w r3, [r7, #352] ; 0x160 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800496a: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160 800496e: fa93 f3a3 rbit r3, r3 8004972: f8c7 315c str.w r3, [r7, #348] ; 0x15c return result; 8004976: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800497a: fab3 f383 clz r3, r3 800497e: b2db uxtb r3, r3 8004980: 095b lsrs r3, r3, #5 8004982: b2db uxtb r3, r3 8004984: f043 0301 orr.w r3, r3, #1 8004988: b2db uxtb r3, r3 800498a: 2b01 cmp r3, #1 800498c: d102 bne.n 8004994 800498e: 4b45 ldr r3, [pc, #276] ; (8004aa4 ) 8004990: 681b ldr r3, [r3, #0] 8004992: e013 b.n 80049bc 8004994: 2302 movs r3, #2 8004996: f8c7 3158 str.w r3, [r7, #344] ; 0x158 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800499a: f8d7 3158 ldr.w r3, [r7, #344] ; 0x158 800499e: fa93 f3a3 rbit r3, r3 80049a2: f8c7 3154 str.w r3, [r7, #340] ; 0x154 80049a6: 2302 movs r3, #2 80049a8: f8c7 3150 str.w r3, [r7, #336] ; 0x150 80049ac: f8d7 3150 ldr.w r3, [r7, #336] ; 0x150 80049b0: fa93 f3a3 rbit r3, r3 80049b4: f8c7 314c str.w r3, [r7, #332] ; 0x14c 80049b8: 4b3a ldr r3, [pc, #232] ; (8004aa4 ) 80049ba: 6a5b ldr r3, [r3, #36] ; 0x24 80049bc: 2202 movs r2, #2 80049be: f8c7 2148 str.w r2, [r7, #328] ; 0x148 80049c2: f8d7 2148 ldr.w r2, [r7, #328] ; 0x148 80049c6: fa92 f2a2 rbit r2, r2 80049ca: f8c7 2144 str.w r2, [r7, #324] ; 0x144 return result; 80049ce: f8d7 2144 ldr.w r2, [r7, #324] ; 0x144 80049d2: fab2 f282 clz r2, r2 80049d6: b2d2 uxtb r2, r2 80049d8: f042 0220 orr.w r2, r2, #32 80049dc: b2d2 uxtb r2, r2 80049de: f002 021f and.w r2, r2, #31 80049e2: 2101 movs r1, #1 80049e4: fa01 f202 lsl.w r2, r1, r2 80049e8: 4013 ands r3, r2 80049ea: 2b00 cmp r3, #0 80049ec: d0af beq.n 800494e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80049ee: 4b2d ldr r3, [pc, #180] ; (8004aa4 ) 80049f0: 681b ldr r3, [r3, #0] 80049f2: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80049f6: f507 7300 add.w r3, r7, #512 ; 0x200 80049fa: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80049fe: 681b ldr r3, [r3, #0] 8004a00: 695b ldr r3, [r3, #20] 8004a02: 21f8 movs r1, #248 ; 0xf8 8004a04: f8c7 1140 str.w r1, [r7, #320] ; 0x140 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004a08: f8d7 1140 ldr.w r1, [r7, #320] ; 0x140 8004a0c: fa91 f1a1 rbit r1, r1 8004a10: f8c7 113c str.w r1, [r7, #316] ; 0x13c return result; 8004a14: f8d7 113c ldr.w r1, [r7, #316] ; 0x13c 8004a18: fab1 f181 clz r1, r1 8004a1c: b2c9 uxtb r1, r1 8004a1e: 408b lsls r3, r1 8004a20: 4920 ldr r1, [pc, #128] ; (8004aa4 ) 8004a22: 4313 orrs r3, r2 8004a24: 600b str r3, [r1, #0] 8004a26: e06c b.n 8004b02 8004a28: 2301 movs r3, #1 8004a2a: f8c7 3138 str.w r3, [r7, #312] ; 0x138 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004a2e: f8d7 3138 ldr.w r3, [r7, #312] ; 0x138 8004a32: fa93 f3a3 rbit r3, r3 8004a36: f8c7 3134 str.w r3, [r7, #308] ; 0x134 return result; 8004a3a: f8d7 3134 ldr.w r3, [r7, #308] ; 0x134 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8004a3e: fab3 f383 clz r3, r3 8004a42: b2db uxtb r3, r3 8004a44: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 8004a48: f503 1384 add.w r3, r3, #1081344 ; 0x108000 8004a4c: 009b lsls r3, r3, #2 8004a4e: 461a mov r2, r3 8004a50: 2300 movs r3, #0 8004a52: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004a54: f7fd fc06 bl 8002264 8004a58: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004a5c: e00a b.n 8004a74 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8004a5e: f7fd fc01 bl 8002264 8004a62: 4602 mov r2, r0 8004a64: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8004a68: 1ad3 subs r3, r2, r3 8004a6a: 2b02 cmp r3, #2 8004a6c: d902 bls.n 8004a74 { return HAL_TIMEOUT; 8004a6e: 2303 movs r3, #3 8004a70: f000 bd5a b.w 8005528 8004a74: 2302 movs r3, #2 8004a76: f8c7 3130 str.w r3, [r7, #304] ; 0x130 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004a7a: f8d7 3130 ldr.w r3, [r7, #304] ; 0x130 8004a7e: fa93 f3a3 rbit r3, r3 8004a82: f8c7 312c str.w r3, [r7, #300] ; 0x12c return result; 8004a86: f8d7 312c ldr.w r3, [r7, #300] ; 0x12c while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004a8a: fab3 f383 clz r3, r3 8004a8e: b2db uxtb r3, r3 8004a90: 095b lsrs r3, r3, #5 8004a92: b2db uxtb r3, r3 8004a94: f043 0301 orr.w r3, r3, #1 8004a98: b2db uxtb r3, r3 8004a9a: 2b01 cmp r3, #1 8004a9c: d104 bne.n 8004aa8 8004a9e: 4b01 ldr r3, [pc, #4] ; (8004aa4 ) 8004aa0: 681b ldr r3, [r3, #0] 8004aa2: e015 b.n 8004ad0 8004aa4: 40021000 .word 0x40021000 8004aa8: 2302 movs r3, #2 8004aaa: f8c7 3128 str.w r3, [r7, #296] ; 0x128 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004aae: f8d7 3128 ldr.w r3, [r7, #296] ; 0x128 8004ab2: fa93 f3a3 rbit r3, r3 8004ab6: f8c7 3124 str.w r3, [r7, #292] ; 0x124 8004aba: 2302 movs r3, #2 8004abc: f8c7 3120 str.w r3, [r7, #288] ; 0x120 8004ac0: f8d7 3120 ldr.w r3, [r7, #288] ; 0x120 8004ac4: fa93 f3a3 rbit r3, r3 8004ac8: f8c7 311c str.w r3, [r7, #284] ; 0x11c 8004acc: 4bc8 ldr r3, [pc, #800] ; (8004df0 ) 8004ace: 6a5b ldr r3, [r3, #36] ; 0x24 8004ad0: 2202 movs r2, #2 8004ad2: f8c7 2118 str.w r2, [r7, #280] ; 0x118 8004ad6: f8d7 2118 ldr.w r2, [r7, #280] ; 0x118 8004ada: fa92 f2a2 rbit r2, r2 8004ade: f8c7 2114 str.w r2, [r7, #276] ; 0x114 return result; 8004ae2: f8d7 2114 ldr.w r2, [r7, #276] ; 0x114 8004ae6: fab2 f282 clz r2, r2 8004aea: b2d2 uxtb r2, r2 8004aec: f042 0220 orr.w r2, r2, #32 8004af0: b2d2 uxtb r2, r2 8004af2: f002 021f and.w r2, r2, #31 8004af6: 2101 movs r1, #1 8004af8: fa01 f202 lsl.w r2, r1, r2 8004afc: 4013 ands r3, r2 8004afe: 2b00 cmp r3, #0 8004b00: d1ad bne.n 8004a5e } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004b02: f507 7300 add.w r3, r7, #512 ; 0x200 8004b06: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8004b0a: 681b ldr r3, [r3, #0] 8004b0c: 681b ldr r3, [r3, #0] 8004b0e: f003 0308 and.w r3, r3, #8 8004b12: 2b00 cmp r3, #0 8004b14: f000 8110 beq.w 8004d38 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8004b18: f507 7300 add.w r3, r7, #512 ; 0x200 8004b1c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8004b20: 681b ldr r3, [r3, #0] 8004b22: 699b ldr r3, [r3, #24] 8004b24: 2b00 cmp r3, #0 8004b26: d079 beq.n 8004c1c 8004b28: 2301 movs r3, #1 8004b2a: f8c7 3110 str.w r3, [r7, #272] ; 0x110 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004b2e: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8004b32: fa93 f3a3 rbit r3, r3 8004b36: f8c7 310c str.w r3, [r7, #268] ; 0x10c return result; 8004b3a: f8d7 310c ldr.w r3, [r7, #268] ; 0x10c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004b3e: fab3 f383 clz r3, r3 8004b42: b2db uxtb r3, r3 8004b44: 461a mov r2, r3 8004b46: 4bab ldr r3, [pc, #684] ; (8004df4 ) 8004b48: 4413 add r3, r2 8004b4a: 009b lsls r3, r3, #2 8004b4c: 461a mov r2, r3 8004b4e: 2301 movs r3, #1 8004b50: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004b52: f7fd fb87 bl 8002264 8004b56: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004b5a: e00a b.n 8004b72 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8004b5c: f7fd fb82 bl 8002264 8004b60: 4602 mov r2, r0 8004b62: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8004b66: 1ad3 subs r3, r2, r3 8004b68: 2b02 cmp r3, #2 8004b6a: d902 bls.n 8004b72 { return HAL_TIMEOUT; 8004b6c: 2303 movs r3, #3 8004b6e: f000 bcdb b.w 8005528 8004b72: 2302 movs r3, #2 8004b74: f8c7 3108 str.w r3, [r7, #264] ; 0x108 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004b78: f8d7 3108 ldr.w r3, [r7, #264] ; 0x108 8004b7c: fa93 f3a3 rbit r3, r3 8004b80: f8c7 3104 str.w r3, [r7, #260] ; 0x104 8004b84: f507 7300 add.w r3, r7, #512 ; 0x200 8004b88: f5a3 7380 sub.w r3, r3, #256 ; 0x100 8004b8c: 2202 movs r2, #2 8004b8e: 601a str r2, [r3, #0] 8004b90: f507 7300 add.w r3, r7, #512 ; 0x200 8004b94: f5a3 7380 sub.w r3, r3, #256 ; 0x100 8004b98: 681b ldr r3, [r3, #0] 8004b9a: fa93 f2a3 rbit r2, r3 8004b9e: f507 7300 add.w r3, r7, #512 ; 0x200 8004ba2: f5a3 7382 sub.w r3, r3, #260 ; 0x104 8004ba6: 601a str r2, [r3, #0] 8004ba8: f507 7300 add.w r3, r7, #512 ; 0x200 8004bac: f5a3 7384 sub.w r3, r3, #264 ; 0x108 8004bb0: 2202 movs r2, #2 8004bb2: 601a str r2, [r3, #0] 8004bb4: f507 7300 add.w r3, r7, #512 ; 0x200 8004bb8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 8004bbc: 681b ldr r3, [r3, #0] 8004bbe: fa93 f2a3 rbit r2, r3 8004bc2: f507 7300 add.w r3, r7, #512 ; 0x200 8004bc6: f5a3 7386 sub.w r3, r3, #268 ; 0x10c 8004bca: 601a str r2, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004bcc: 4b88 ldr r3, [pc, #544] ; (8004df0 ) 8004bce: 6a5a ldr r2, [r3, #36] ; 0x24 8004bd0: f507 7300 add.w r3, r7, #512 ; 0x200 8004bd4: f5a3 7388 sub.w r3, r3, #272 ; 0x110 8004bd8: 2102 movs r1, #2 8004bda: 6019 str r1, [r3, #0] 8004bdc: f507 7300 add.w r3, r7, #512 ; 0x200 8004be0: f5a3 7388 sub.w r3, r3, #272 ; 0x110 8004be4: 681b ldr r3, [r3, #0] 8004be6: fa93 f1a3 rbit r1, r3 8004bea: f507 7300 add.w r3, r7, #512 ; 0x200 8004bee: f5a3 738a sub.w r3, r3, #276 ; 0x114 8004bf2: 6019 str r1, [r3, #0] return result; 8004bf4: f507 7300 add.w r3, r7, #512 ; 0x200 8004bf8: f5a3 738a sub.w r3, r3, #276 ; 0x114 8004bfc: 681b ldr r3, [r3, #0] 8004bfe: fab3 f383 clz r3, r3 8004c02: b2db uxtb r3, r3 8004c04: f043 0360 orr.w r3, r3, #96 ; 0x60 8004c08: b2db uxtb r3, r3 8004c0a: f003 031f and.w r3, r3, #31 8004c0e: 2101 movs r1, #1 8004c10: fa01 f303 lsl.w r3, r1, r3 8004c14: 4013 ands r3, r2 8004c16: 2b00 cmp r3, #0 8004c18: d0a0 beq.n 8004b5c 8004c1a: e08d b.n 8004d38 8004c1c: f507 7300 add.w r3, r7, #512 ; 0x200 8004c20: f5a3 738c sub.w r3, r3, #280 ; 0x118 8004c24: 2201 movs r2, #1 8004c26: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004c28: f507 7300 add.w r3, r7, #512 ; 0x200 8004c2c: f5a3 738c sub.w r3, r3, #280 ; 0x118 8004c30: 681b ldr r3, [r3, #0] 8004c32: fa93 f2a3 rbit r2, r3 8004c36: f507 7300 add.w r3, r7, #512 ; 0x200 8004c3a: f5a3 738e sub.w r3, r3, #284 ; 0x11c 8004c3e: 601a str r2, [r3, #0] return result; 8004c40: f507 7300 add.w r3, r7, #512 ; 0x200 8004c44: f5a3 738e sub.w r3, r3, #284 ; 0x11c 8004c48: 681b ldr r3, [r3, #0] } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004c4a: fab3 f383 clz r3, r3 8004c4e: b2db uxtb r3, r3 8004c50: 461a mov r2, r3 8004c52: 4b68 ldr r3, [pc, #416] ; (8004df4 ) 8004c54: 4413 add r3, r2 8004c56: 009b lsls r3, r3, #2 8004c58: 461a mov r2, r3 8004c5a: 2300 movs r3, #0 8004c5c: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004c5e: f7fd fb01 bl 8002264 8004c62: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004c66: e00a b.n 8004c7e { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8004c68: f7fd fafc bl 8002264 8004c6c: 4602 mov r2, r0 8004c6e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8004c72: 1ad3 subs r3, r2, r3 8004c74: 2b02 cmp r3, #2 8004c76: d902 bls.n 8004c7e { return HAL_TIMEOUT; 8004c78: 2303 movs r3, #3 8004c7a: f000 bc55 b.w 8005528 8004c7e: f507 7300 add.w r3, r7, #512 ; 0x200 8004c82: f5a3 7390 sub.w r3, r3, #288 ; 0x120 8004c86: 2202 movs r2, #2 8004c88: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004c8a: f507 7300 add.w r3, r7, #512 ; 0x200 8004c8e: f5a3 7390 sub.w r3, r3, #288 ; 0x120 8004c92: 681b ldr r3, [r3, #0] 8004c94: fa93 f2a3 rbit r2, r3 8004c98: f507 7300 add.w r3, r7, #512 ; 0x200 8004c9c: f5a3 7392 sub.w r3, r3, #292 ; 0x124 8004ca0: 601a str r2, [r3, #0] 8004ca2: f507 7300 add.w r3, r7, #512 ; 0x200 8004ca6: f5a3 7394 sub.w r3, r3, #296 ; 0x128 8004caa: 2202 movs r2, #2 8004cac: 601a str r2, [r3, #0] 8004cae: f507 7300 add.w r3, r7, #512 ; 0x200 8004cb2: f5a3 7394 sub.w r3, r3, #296 ; 0x128 8004cb6: 681b ldr r3, [r3, #0] 8004cb8: fa93 f2a3 rbit r2, r3 8004cbc: f507 7300 add.w r3, r7, #512 ; 0x200 8004cc0: f5a3 7396 sub.w r3, r3, #300 ; 0x12c 8004cc4: 601a str r2, [r3, #0] 8004cc6: f507 7300 add.w r3, r7, #512 ; 0x200 8004cca: f5a3 7398 sub.w r3, r3, #304 ; 0x130 8004cce: 2202 movs r2, #2 8004cd0: 601a str r2, [r3, #0] 8004cd2: f507 7300 add.w r3, r7, #512 ; 0x200 8004cd6: f5a3 7398 sub.w r3, r3, #304 ; 0x130 8004cda: 681b ldr r3, [r3, #0] 8004cdc: fa93 f2a3 rbit r2, r3 8004ce0: f507 7300 add.w r3, r7, #512 ; 0x200 8004ce4: f5a3 739a sub.w r3, r3, #308 ; 0x134 8004ce8: 601a str r2, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004cea: 4b41 ldr r3, [pc, #260] ; (8004df0 ) 8004cec: 6a5a ldr r2, [r3, #36] ; 0x24 8004cee: f507 7300 add.w r3, r7, #512 ; 0x200 8004cf2: f5a3 739c sub.w r3, r3, #312 ; 0x138 8004cf6: 2102 movs r1, #2 8004cf8: 6019 str r1, [r3, #0] 8004cfa: f507 7300 add.w r3, r7, #512 ; 0x200 8004cfe: f5a3 739c sub.w r3, r3, #312 ; 0x138 8004d02: 681b ldr r3, [r3, #0] 8004d04: fa93 f1a3 rbit r1, r3 8004d08: f507 7300 add.w r3, r7, #512 ; 0x200 8004d0c: f5a3 739e sub.w r3, r3, #316 ; 0x13c 8004d10: 6019 str r1, [r3, #0] return result; 8004d12: f507 7300 add.w r3, r7, #512 ; 0x200 8004d16: f5a3 739e sub.w r3, r3, #316 ; 0x13c 8004d1a: 681b ldr r3, [r3, #0] 8004d1c: fab3 f383 clz r3, r3 8004d20: b2db uxtb r3, r3 8004d22: f043 0360 orr.w r3, r3, #96 ; 0x60 8004d26: b2db uxtb r3, r3 8004d28: f003 031f and.w r3, r3, #31 8004d2c: 2101 movs r1, #1 8004d2e: fa01 f303 lsl.w r3, r1, r3 8004d32: 4013 ands r3, r2 8004d34: 2b00 cmp r3, #0 8004d36: d197 bne.n 8004c68 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8004d38: f507 7300 add.w r3, r7, #512 ; 0x200 8004d3c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8004d40: 681b ldr r3, [r3, #0] 8004d42: 681b ldr r3, [r3, #0] 8004d44: f003 0304 and.w r3, r3, #4 8004d48: 2b00 cmp r3, #0 8004d4a: f000 81a1 beq.w 8005090 { FlagStatus pwrclkchanged = RESET; 8004d4e: 2300 movs r3, #0 8004d50: f887 31ff strb.w r3, [r7, #511] ; 0x1ff /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004d54: 4b26 ldr r3, [pc, #152] ; (8004df0 ) 8004d56: 69db ldr r3, [r3, #28] 8004d58: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8004d5c: 2b00 cmp r3, #0 8004d5e: d116 bne.n 8004d8e { __HAL_RCC_PWR_CLK_ENABLE(); 8004d60: 4b23 ldr r3, [pc, #140] ; (8004df0 ) 8004d62: 69db ldr r3, [r3, #28] 8004d64: 4a22 ldr r2, [pc, #136] ; (8004df0 ) 8004d66: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8004d6a: 61d3 str r3, [r2, #28] 8004d6c: 4b20 ldr r3, [pc, #128] ; (8004df0 ) 8004d6e: 69db ldr r3, [r3, #28] 8004d70: f003 5280 and.w r2, r3, #268435456 ; 0x10000000 8004d74: f507 7300 add.w r3, r7, #512 ; 0x200 8004d78: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8 8004d7c: 601a str r2, [r3, #0] 8004d7e: f507 7300 add.w r3, r7, #512 ; 0x200 8004d82: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8 8004d86: 681b ldr r3, [r3, #0] pwrclkchanged = SET; 8004d88: 2301 movs r3, #1 8004d8a: f887 31ff strb.w r3, [r7, #511] ; 0x1ff } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004d8e: 4b1a ldr r3, [pc, #104] ; (8004df8 ) 8004d90: 681b ldr r3, [r3, #0] 8004d92: f403 7380 and.w r3, r3, #256 ; 0x100 8004d96: 2b00 cmp r3, #0 8004d98: d11a bne.n 8004dd0 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8004d9a: 4b17 ldr r3, [pc, #92] ; (8004df8 ) 8004d9c: 681b ldr r3, [r3, #0] 8004d9e: 4a16 ldr r2, [pc, #88] ; (8004df8 ) 8004da0: f443 7380 orr.w r3, r3, #256 ; 0x100 8004da4: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004da6: f7fd fa5d bl 8002264 8004daa: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004dae: e009 b.n 8004dc4 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004db0: f7fd fa58 bl 8002264 8004db4: 4602 mov r2, r0 8004db6: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8004dba: 1ad3 subs r3, r2, r3 8004dbc: 2b64 cmp r3, #100 ; 0x64 8004dbe: d901 bls.n 8004dc4 { return HAL_TIMEOUT; 8004dc0: 2303 movs r3, #3 8004dc2: e3b1 b.n 8005528 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004dc4: 4b0c ldr r3, [pc, #48] ; (8004df8 ) 8004dc6: 681b ldr r3, [r3, #0] 8004dc8: f403 7380 and.w r3, r3, #256 ; 0x100 8004dcc: 2b00 cmp r3, #0 8004dce: d0ef beq.n 8004db0 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004dd0: f507 7300 add.w r3, r7, #512 ; 0x200 8004dd4: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8004dd8: 681b ldr r3, [r3, #0] 8004dda: 68db ldr r3, [r3, #12] 8004ddc: 2b01 cmp r3, #1 8004dde: d10d bne.n 8004dfc 8004de0: 4b03 ldr r3, [pc, #12] ; (8004df0 ) 8004de2: 6a1b ldr r3, [r3, #32] 8004de4: 4a02 ldr r2, [pc, #8] ; (8004df0 ) 8004de6: f043 0301 orr.w r3, r3, #1 8004dea: 6213 str r3, [r2, #32] 8004dec: e03c b.n 8004e68 8004dee: bf00 nop 8004df0: 40021000 .word 0x40021000 8004df4: 10908120 .word 0x10908120 8004df8: 40007000 .word 0x40007000 8004dfc: f507 7300 add.w r3, r7, #512 ; 0x200 8004e00: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8004e04: 681b ldr r3, [r3, #0] 8004e06: 68db ldr r3, [r3, #12] 8004e08: 2b00 cmp r3, #0 8004e0a: d10c bne.n 8004e26 8004e0c: 4bc1 ldr r3, [pc, #772] ; (8005114 ) 8004e0e: 6a1b ldr r3, [r3, #32] 8004e10: 4ac0 ldr r2, [pc, #768] ; (8005114 ) 8004e12: f023 0301 bic.w r3, r3, #1 8004e16: 6213 str r3, [r2, #32] 8004e18: 4bbe ldr r3, [pc, #760] ; (8005114 ) 8004e1a: 6a1b ldr r3, [r3, #32] 8004e1c: 4abd ldr r2, [pc, #756] ; (8005114 ) 8004e1e: f023 0304 bic.w r3, r3, #4 8004e22: 6213 str r3, [r2, #32] 8004e24: e020 b.n 8004e68 8004e26: f507 7300 add.w r3, r7, #512 ; 0x200 8004e2a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8004e2e: 681b ldr r3, [r3, #0] 8004e30: 68db ldr r3, [r3, #12] 8004e32: 2b05 cmp r3, #5 8004e34: d10c bne.n 8004e50 8004e36: 4bb7 ldr r3, [pc, #732] ; (8005114 ) 8004e38: 6a1b ldr r3, [r3, #32] 8004e3a: 4ab6 ldr r2, [pc, #728] ; (8005114 ) 8004e3c: f043 0304 orr.w r3, r3, #4 8004e40: 6213 str r3, [r2, #32] 8004e42: 4bb4 ldr r3, [pc, #720] ; (8005114 ) 8004e44: 6a1b ldr r3, [r3, #32] 8004e46: 4ab3 ldr r2, [pc, #716] ; (8005114 ) 8004e48: f043 0301 orr.w r3, r3, #1 8004e4c: 6213 str r3, [r2, #32] 8004e4e: e00b b.n 8004e68 8004e50: 4bb0 ldr r3, [pc, #704] ; (8005114 ) 8004e52: 6a1b ldr r3, [r3, #32] 8004e54: 4aaf ldr r2, [pc, #700] ; (8005114 ) 8004e56: f023 0301 bic.w r3, r3, #1 8004e5a: 6213 str r3, [r2, #32] 8004e5c: 4bad ldr r3, [pc, #692] ; (8005114 ) 8004e5e: 6a1b ldr r3, [r3, #32] 8004e60: 4aac ldr r2, [pc, #688] ; (8005114 ) 8004e62: f023 0304 bic.w r3, r3, #4 8004e66: 6213 str r3, [r2, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8004e68: f507 7300 add.w r3, r7, #512 ; 0x200 8004e6c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8004e70: 681b ldr r3, [r3, #0] 8004e72: 68db ldr r3, [r3, #12] 8004e74: 2b00 cmp r3, #0 8004e76: f000 8081 beq.w 8004f7c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004e7a: f7fd f9f3 bl 8002264 8004e7e: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004e82: e00b b.n 8004e9c { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8004e84: f7fd f9ee bl 8002264 8004e88: 4602 mov r2, r0 8004e8a: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8004e8e: 1ad3 subs r3, r2, r3 8004e90: f241 3288 movw r2, #5000 ; 0x1388 8004e94: 4293 cmp r3, r2 8004e96: d901 bls.n 8004e9c { return HAL_TIMEOUT; 8004e98: 2303 movs r3, #3 8004e9a: e345 b.n 8005528 8004e9c: f507 7300 add.w r3, r7, #512 ; 0x200 8004ea0: f5a3 73a0 sub.w r3, r3, #320 ; 0x140 8004ea4: 2202 movs r2, #2 8004ea6: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004ea8: f507 7300 add.w r3, r7, #512 ; 0x200 8004eac: f5a3 73a0 sub.w r3, r3, #320 ; 0x140 8004eb0: 681b ldr r3, [r3, #0] 8004eb2: fa93 f2a3 rbit r2, r3 8004eb6: f507 7300 add.w r3, r7, #512 ; 0x200 8004eba: f5a3 73a2 sub.w r3, r3, #324 ; 0x144 8004ebe: 601a str r2, [r3, #0] 8004ec0: f507 7300 add.w r3, r7, #512 ; 0x200 8004ec4: f5a3 73a4 sub.w r3, r3, #328 ; 0x148 8004ec8: 2202 movs r2, #2 8004eca: 601a str r2, [r3, #0] 8004ecc: f507 7300 add.w r3, r7, #512 ; 0x200 8004ed0: f5a3 73a4 sub.w r3, r3, #328 ; 0x148 8004ed4: 681b ldr r3, [r3, #0] 8004ed6: fa93 f2a3 rbit r2, r3 8004eda: f507 7300 add.w r3, r7, #512 ; 0x200 8004ede: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c 8004ee2: 601a str r2, [r3, #0] return result; 8004ee4: f507 7300 add.w r3, r7, #512 ; 0x200 8004ee8: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c 8004eec: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004eee: fab3 f383 clz r3, r3 8004ef2: b2db uxtb r3, r3 8004ef4: 095b lsrs r3, r3, #5 8004ef6: b2db uxtb r3, r3 8004ef8: f043 0302 orr.w r3, r3, #2 8004efc: b2db uxtb r3, r3 8004efe: 2b02 cmp r3, #2 8004f00: d102 bne.n 8004f08 8004f02: 4b84 ldr r3, [pc, #528] ; (8005114 ) 8004f04: 6a1b ldr r3, [r3, #32] 8004f06: e013 b.n 8004f30 8004f08: f507 7300 add.w r3, r7, #512 ; 0x200 8004f0c: f5a3 73a8 sub.w r3, r3, #336 ; 0x150 8004f10: 2202 movs r2, #2 8004f12: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004f14: f507 7300 add.w r3, r7, #512 ; 0x200 8004f18: f5a3 73a8 sub.w r3, r3, #336 ; 0x150 8004f1c: 681b ldr r3, [r3, #0] 8004f1e: fa93 f2a3 rbit r2, r3 8004f22: f507 7300 add.w r3, r7, #512 ; 0x200 8004f26: f5a3 73aa sub.w r3, r3, #340 ; 0x154 8004f2a: 601a str r2, [r3, #0] 8004f2c: 4b79 ldr r3, [pc, #484] ; (8005114 ) 8004f2e: 6a5b ldr r3, [r3, #36] ; 0x24 8004f30: f507 7200 add.w r2, r7, #512 ; 0x200 8004f34: f5a2 72ac sub.w r2, r2, #344 ; 0x158 8004f38: 2102 movs r1, #2 8004f3a: 6011 str r1, [r2, #0] 8004f3c: f507 7200 add.w r2, r7, #512 ; 0x200 8004f40: f5a2 72ac sub.w r2, r2, #344 ; 0x158 8004f44: 6812 ldr r2, [r2, #0] 8004f46: fa92 f1a2 rbit r1, r2 8004f4a: f507 7200 add.w r2, r7, #512 ; 0x200 8004f4e: f5a2 72ae sub.w r2, r2, #348 ; 0x15c 8004f52: 6011 str r1, [r2, #0] return result; 8004f54: f507 7200 add.w r2, r7, #512 ; 0x200 8004f58: f5a2 72ae sub.w r2, r2, #348 ; 0x15c 8004f5c: 6812 ldr r2, [r2, #0] 8004f5e: fab2 f282 clz r2, r2 8004f62: b2d2 uxtb r2, r2 8004f64: f042 0240 orr.w r2, r2, #64 ; 0x40 8004f68: b2d2 uxtb r2, r2 8004f6a: f002 021f and.w r2, r2, #31 8004f6e: 2101 movs r1, #1 8004f70: fa01 f202 lsl.w r2, r1, r2 8004f74: 4013 ands r3, r2 8004f76: 2b00 cmp r3, #0 8004f78: d084 beq.n 8004e84 8004f7a: e07f b.n 800507c } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004f7c: f7fd f972 bl 8002264 8004f80: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004f84: e00b b.n 8004f9e { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8004f86: f7fd f96d bl 8002264 8004f8a: 4602 mov r2, r0 8004f8c: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8004f90: 1ad3 subs r3, r2, r3 8004f92: f241 3288 movw r2, #5000 ; 0x1388 8004f96: 4293 cmp r3, r2 8004f98: d901 bls.n 8004f9e { return HAL_TIMEOUT; 8004f9a: 2303 movs r3, #3 8004f9c: e2c4 b.n 8005528 8004f9e: f507 7300 add.w r3, r7, #512 ; 0x200 8004fa2: f5a3 73b0 sub.w r3, r3, #352 ; 0x160 8004fa6: 2202 movs r2, #2 8004fa8: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004faa: f507 7300 add.w r3, r7, #512 ; 0x200 8004fae: f5a3 73b0 sub.w r3, r3, #352 ; 0x160 8004fb2: 681b ldr r3, [r3, #0] 8004fb4: fa93 f2a3 rbit r2, r3 8004fb8: f507 7300 add.w r3, r7, #512 ; 0x200 8004fbc: f5a3 73b2 sub.w r3, r3, #356 ; 0x164 8004fc0: 601a str r2, [r3, #0] 8004fc2: f507 7300 add.w r3, r7, #512 ; 0x200 8004fc6: f5a3 73b4 sub.w r3, r3, #360 ; 0x168 8004fca: 2202 movs r2, #2 8004fcc: 601a str r2, [r3, #0] 8004fce: f507 7300 add.w r3, r7, #512 ; 0x200 8004fd2: f5a3 73b4 sub.w r3, r3, #360 ; 0x168 8004fd6: 681b ldr r3, [r3, #0] 8004fd8: fa93 f2a3 rbit r2, r3 8004fdc: f507 7300 add.w r3, r7, #512 ; 0x200 8004fe0: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c 8004fe4: 601a str r2, [r3, #0] return result; 8004fe6: f507 7300 add.w r3, r7, #512 ; 0x200 8004fea: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c 8004fee: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004ff0: fab3 f383 clz r3, r3 8004ff4: b2db uxtb r3, r3 8004ff6: 095b lsrs r3, r3, #5 8004ff8: b2db uxtb r3, r3 8004ffa: f043 0302 orr.w r3, r3, #2 8004ffe: b2db uxtb r3, r3 8005000: 2b02 cmp r3, #2 8005002: d102 bne.n 800500a 8005004: 4b43 ldr r3, [pc, #268] ; (8005114 ) 8005006: 6a1b ldr r3, [r3, #32] 8005008: e013 b.n 8005032 800500a: f507 7300 add.w r3, r7, #512 ; 0x200 800500e: f5a3 73b8 sub.w r3, r3, #368 ; 0x170 8005012: 2202 movs r2, #2 8005014: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005016: f507 7300 add.w r3, r7, #512 ; 0x200 800501a: f5a3 73b8 sub.w r3, r3, #368 ; 0x170 800501e: 681b ldr r3, [r3, #0] 8005020: fa93 f2a3 rbit r2, r3 8005024: f507 7300 add.w r3, r7, #512 ; 0x200 8005028: f5a3 73ba sub.w r3, r3, #372 ; 0x174 800502c: 601a str r2, [r3, #0] 800502e: 4b39 ldr r3, [pc, #228] ; (8005114 ) 8005030: 6a5b ldr r3, [r3, #36] ; 0x24 8005032: f507 7200 add.w r2, r7, #512 ; 0x200 8005036: f5a2 72bc sub.w r2, r2, #376 ; 0x178 800503a: 2102 movs r1, #2 800503c: 6011 str r1, [r2, #0] 800503e: f507 7200 add.w r2, r7, #512 ; 0x200 8005042: f5a2 72bc sub.w r2, r2, #376 ; 0x178 8005046: 6812 ldr r2, [r2, #0] 8005048: fa92 f1a2 rbit r1, r2 800504c: f507 7200 add.w r2, r7, #512 ; 0x200 8005050: f5a2 72be sub.w r2, r2, #380 ; 0x17c 8005054: 6011 str r1, [r2, #0] return result; 8005056: f507 7200 add.w r2, r7, #512 ; 0x200 800505a: f5a2 72be sub.w r2, r2, #380 ; 0x17c 800505e: 6812 ldr r2, [r2, #0] 8005060: fab2 f282 clz r2, r2 8005064: b2d2 uxtb r2, r2 8005066: f042 0240 orr.w r2, r2, #64 ; 0x40 800506a: b2d2 uxtb r2, r2 800506c: f002 021f and.w r2, r2, #31 8005070: 2101 movs r1, #1 8005072: fa01 f202 lsl.w r2, r1, r2 8005076: 4013 ands r3, r2 8005078: 2b00 cmp r3, #0 800507a: d184 bne.n 8004f86 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 800507c: f897 31ff ldrb.w r3, [r7, #511] ; 0x1ff 8005080: 2b01 cmp r3, #1 8005082: d105 bne.n 8005090 { __HAL_RCC_PWR_CLK_DISABLE(); 8005084: 4b23 ldr r3, [pc, #140] ; (8005114 ) 8005086: 69db ldr r3, [r3, #28] 8005088: 4a22 ldr r2, [pc, #136] ; (8005114 ) 800508a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800508e: 61d3 str r3, [r2, #28] } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8005090: f507 7300 add.w r3, r7, #512 ; 0x200 8005094: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8005098: 681b ldr r3, [r3, #0] 800509a: 69db ldr r3, [r3, #28] 800509c: 2b00 cmp r3, #0 800509e: f000 8242 beq.w 8005526 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80050a2: 4b1c ldr r3, [pc, #112] ; (8005114 ) 80050a4: 685b ldr r3, [r3, #4] 80050a6: f003 030c and.w r3, r3, #12 80050aa: 2b08 cmp r3, #8 80050ac: f000 8213 beq.w 80054d6 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80050b0: f507 7300 add.w r3, r7, #512 ; 0x200 80050b4: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80050b8: 681b ldr r3, [r3, #0] 80050ba: 69db ldr r3, [r3, #28] 80050bc: 2b02 cmp r3, #2 80050be: f040 8162 bne.w 8005386 80050c2: f507 7300 add.w r3, r7, #512 ; 0x200 80050c6: f5a3 73c0 sub.w r3, r3, #384 ; 0x180 80050ca: f04f 7280 mov.w r2, #16777216 ; 0x1000000 80050ce: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80050d0: f507 7300 add.w r3, r7, #512 ; 0x200 80050d4: f5a3 73c0 sub.w r3, r3, #384 ; 0x180 80050d8: 681b ldr r3, [r3, #0] 80050da: fa93 f2a3 rbit r2, r3 80050de: f507 7300 add.w r3, r7, #512 ; 0x200 80050e2: f5a3 73c2 sub.w r3, r3, #388 ; 0x184 80050e6: 601a str r2, [r3, #0] return result; 80050e8: f507 7300 add.w r3, r7, #512 ; 0x200 80050ec: f5a3 73c2 sub.w r3, r3, #388 ; 0x184 80050f0: 681b ldr r3, [r3, #0] #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); #endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80050f2: fab3 f383 clz r3, r3 80050f6: b2db uxtb r3, r3 80050f8: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 80050fc: f503 1384 add.w r3, r3, #1081344 ; 0x108000 8005100: 009b lsls r3, r3, #2 8005102: 461a mov r2, r3 8005104: 2300 movs r3, #0 8005106: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005108: f7fd f8ac bl 8002264 800510c: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005110: e00c b.n 800512c 8005112: bf00 nop 8005114: 40021000 .word 0x40021000 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8005118: f7fd f8a4 bl 8002264 800511c: 4602 mov r2, r0 800511e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8005122: 1ad3 subs r3, r2, r3 8005124: 2b02 cmp r3, #2 8005126: d901 bls.n 800512c { return HAL_TIMEOUT; 8005128: 2303 movs r3, #3 800512a: e1fd b.n 8005528 800512c: f507 7300 add.w r3, r7, #512 ; 0x200 8005130: f5a3 73c4 sub.w r3, r3, #392 ; 0x188 8005134: f04f 7200 mov.w r2, #33554432 ; 0x2000000 8005138: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800513a: f507 7300 add.w r3, r7, #512 ; 0x200 800513e: f5a3 73c4 sub.w r3, r3, #392 ; 0x188 8005142: 681b ldr r3, [r3, #0] 8005144: fa93 f2a3 rbit r2, r3 8005148: f507 7300 add.w r3, r7, #512 ; 0x200 800514c: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c 8005150: 601a str r2, [r3, #0] return result; 8005152: f507 7300 add.w r3, r7, #512 ; 0x200 8005156: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c 800515a: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800515c: fab3 f383 clz r3, r3 8005160: b2db uxtb r3, r3 8005162: 095b lsrs r3, r3, #5 8005164: b2db uxtb r3, r3 8005166: f043 0301 orr.w r3, r3, #1 800516a: b2db uxtb r3, r3 800516c: 2b01 cmp r3, #1 800516e: d102 bne.n 8005176 8005170: 4bb0 ldr r3, [pc, #704] ; (8005434 ) 8005172: 681b ldr r3, [r3, #0] 8005174: e027 b.n 80051c6 8005176: f507 7300 add.w r3, r7, #512 ; 0x200 800517a: f5a3 73c8 sub.w r3, r3, #400 ; 0x190 800517e: f04f 7200 mov.w r2, #33554432 ; 0x2000000 8005182: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005184: f507 7300 add.w r3, r7, #512 ; 0x200 8005188: f5a3 73c8 sub.w r3, r3, #400 ; 0x190 800518c: 681b ldr r3, [r3, #0] 800518e: fa93 f2a3 rbit r2, r3 8005192: f507 7300 add.w r3, r7, #512 ; 0x200 8005196: f5a3 73ca sub.w r3, r3, #404 ; 0x194 800519a: 601a str r2, [r3, #0] 800519c: f507 7300 add.w r3, r7, #512 ; 0x200 80051a0: f5a3 73cc sub.w r3, r3, #408 ; 0x198 80051a4: f04f 7200 mov.w r2, #33554432 ; 0x2000000 80051a8: 601a str r2, [r3, #0] 80051aa: f507 7300 add.w r3, r7, #512 ; 0x200 80051ae: f5a3 73cc sub.w r3, r3, #408 ; 0x198 80051b2: 681b ldr r3, [r3, #0] 80051b4: fa93 f2a3 rbit r2, r3 80051b8: f507 7300 add.w r3, r7, #512 ; 0x200 80051bc: f5a3 73ce sub.w r3, r3, #412 ; 0x19c 80051c0: 601a str r2, [r3, #0] 80051c2: 4b9c ldr r3, [pc, #624] ; (8005434 ) 80051c4: 6a5b ldr r3, [r3, #36] ; 0x24 80051c6: f507 7200 add.w r2, r7, #512 ; 0x200 80051ca: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0 80051ce: f04f 7100 mov.w r1, #33554432 ; 0x2000000 80051d2: 6011 str r1, [r2, #0] 80051d4: f507 7200 add.w r2, r7, #512 ; 0x200 80051d8: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0 80051dc: 6812 ldr r2, [r2, #0] 80051de: fa92 f1a2 rbit r1, r2 80051e2: f507 7200 add.w r2, r7, #512 ; 0x200 80051e6: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4 80051ea: 6011 str r1, [r2, #0] return result; 80051ec: f507 7200 add.w r2, r7, #512 ; 0x200 80051f0: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4 80051f4: 6812 ldr r2, [r2, #0] 80051f6: fab2 f282 clz r2, r2 80051fa: b2d2 uxtb r2, r2 80051fc: f042 0220 orr.w r2, r2, #32 8005200: b2d2 uxtb r2, r2 8005202: f002 021f and.w r2, r2, #31 8005206: 2101 movs r1, #1 8005208: fa01 f202 lsl.w r2, r1, r2 800520c: 4013 ands r3, r2 800520e: 2b00 cmp r3, #0 8005210: d182 bne.n 8005118 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); #else /* Configure the main PLL clock source and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8005212: 4b88 ldr r3, [pc, #544] ; (8005434 ) 8005214: 685b ldr r3, [r3, #4] 8005216: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 800521a: f507 7300 add.w r3, r7, #512 ; 0x200 800521e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8005222: 681b ldr r3, [r3, #0] 8005224: 6a59 ldr r1, [r3, #36] ; 0x24 8005226: f507 7300 add.w r3, r7, #512 ; 0x200 800522a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 800522e: 681b ldr r3, [r3, #0] 8005230: 6a1b ldr r3, [r3, #32] 8005232: 430b orrs r3, r1 8005234: 497f ldr r1, [pc, #508] ; (8005434 ) 8005236: 4313 orrs r3, r2 8005238: 604b str r3, [r1, #4] 800523a: f507 7300 add.w r3, r7, #512 ; 0x200 800523e: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8 8005242: f04f 7280 mov.w r2, #16777216 ; 0x1000000 8005246: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005248: f507 7300 add.w r3, r7, #512 ; 0x200 800524c: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8 8005250: 681b ldr r3, [r3, #0] 8005252: fa93 f2a3 rbit r2, r3 8005256: f507 7300 add.w r3, r7, #512 ; 0x200 800525a: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac 800525e: 601a str r2, [r3, #0] return result; 8005260: f507 7300 add.w r3, r7, #512 ; 0x200 8005264: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac 8005268: 681b ldr r3, [r3, #0] RCC_OscInitStruct->PLL.PLLMUL); #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800526a: fab3 f383 clz r3, r3 800526e: b2db uxtb r3, r3 8005270: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 8005274: f503 1384 add.w r3, r3, #1081344 ; 0x108000 8005278: 009b lsls r3, r3, #2 800527a: 461a mov r2, r3 800527c: 2301 movs r3, #1 800527e: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005280: f7fc fff0 bl 8002264 8005284: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005288: e009 b.n 800529e { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 800528a: f7fc ffeb bl 8002264 800528e: 4602 mov r2, r0 8005290: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 8005294: 1ad3 subs r3, r2, r3 8005296: 2b02 cmp r3, #2 8005298: d901 bls.n 800529e { return HAL_TIMEOUT; 800529a: 2303 movs r3, #3 800529c: e144 b.n 8005528 800529e: f507 7300 add.w r3, r7, #512 ; 0x200 80052a2: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0 80052a6: f04f 7200 mov.w r2, #33554432 ; 0x2000000 80052aa: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80052ac: f507 7300 add.w r3, r7, #512 ; 0x200 80052b0: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0 80052b4: 681b ldr r3, [r3, #0] 80052b6: fa93 f2a3 rbit r2, r3 80052ba: f507 7300 add.w r3, r7, #512 ; 0x200 80052be: f5a3 73da sub.w r3, r3, #436 ; 0x1b4 80052c2: 601a str r2, [r3, #0] return result; 80052c4: f507 7300 add.w r3, r7, #512 ; 0x200 80052c8: f5a3 73da sub.w r3, r3, #436 ; 0x1b4 80052cc: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80052ce: fab3 f383 clz r3, r3 80052d2: b2db uxtb r3, r3 80052d4: 095b lsrs r3, r3, #5 80052d6: b2db uxtb r3, r3 80052d8: f043 0301 orr.w r3, r3, #1 80052dc: b2db uxtb r3, r3 80052de: 2b01 cmp r3, #1 80052e0: d102 bne.n 80052e8 80052e2: 4b54 ldr r3, [pc, #336] ; (8005434 ) 80052e4: 681b ldr r3, [r3, #0] 80052e6: e027 b.n 8005338 80052e8: f507 7300 add.w r3, r7, #512 ; 0x200 80052ec: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8 80052f0: f04f 7200 mov.w r2, #33554432 ; 0x2000000 80052f4: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80052f6: f507 7300 add.w r3, r7, #512 ; 0x200 80052fa: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8 80052fe: 681b ldr r3, [r3, #0] 8005300: fa93 f2a3 rbit r2, r3 8005304: f507 7300 add.w r3, r7, #512 ; 0x200 8005308: f5a3 73de sub.w r3, r3, #444 ; 0x1bc 800530c: 601a str r2, [r3, #0] 800530e: f507 7300 add.w r3, r7, #512 ; 0x200 8005312: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0 8005316: f04f 7200 mov.w r2, #33554432 ; 0x2000000 800531a: 601a str r2, [r3, #0] 800531c: f507 7300 add.w r3, r7, #512 ; 0x200 8005320: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0 8005324: 681b ldr r3, [r3, #0] 8005326: fa93 f2a3 rbit r2, r3 800532a: f507 7300 add.w r3, r7, #512 ; 0x200 800532e: f5a3 73e2 sub.w r3, r3, #452 ; 0x1c4 8005332: 601a str r2, [r3, #0] 8005334: 4b3f ldr r3, [pc, #252] ; (8005434 ) 8005336: 6a5b ldr r3, [r3, #36] ; 0x24 8005338: f507 7200 add.w r2, r7, #512 ; 0x200 800533c: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8 8005340: f04f 7100 mov.w r1, #33554432 ; 0x2000000 8005344: 6011 str r1, [r2, #0] 8005346: f507 7200 add.w r2, r7, #512 ; 0x200 800534a: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8 800534e: 6812 ldr r2, [r2, #0] 8005350: fa92 f1a2 rbit r1, r2 8005354: f507 7200 add.w r2, r7, #512 ; 0x200 8005358: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc 800535c: 6011 str r1, [r2, #0] return result; 800535e: f507 7200 add.w r2, r7, #512 ; 0x200 8005362: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc 8005366: 6812 ldr r2, [r2, #0] 8005368: fab2 f282 clz r2, r2 800536c: b2d2 uxtb r2, r2 800536e: f042 0220 orr.w r2, r2, #32 8005372: b2d2 uxtb r2, r2 8005374: f002 021f and.w r2, r2, #31 8005378: 2101 movs r1, #1 800537a: fa01 f202 lsl.w r2, r1, r2 800537e: 4013 ands r3, r2 8005380: 2b00 cmp r3, #0 8005382: d082 beq.n 800528a 8005384: e0cf b.n 8005526 8005386: f507 7300 add.w r3, r7, #512 ; 0x200 800538a: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0 800538e: f04f 7280 mov.w r2, #16777216 ; 0x1000000 8005392: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005394: f507 7300 add.w r3, r7, #512 ; 0x200 8005398: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0 800539c: 681b ldr r3, [r3, #0] 800539e: fa93 f2a3 rbit r2, r3 80053a2: f507 7300 add.w r3, r7, #512 ; 0x200 80053a6: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4 80053aa: 601a str r2, [r3, #0] return result; 80053ac: f507 7300 add.w r3, r7, #512 ; 0x200 80053b0: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4 80053b4: 681b ldr r3, [r3, #0] } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80053b6: fab3 f383 clz r3, r3 80053ba: b2db uxtb r3, r3 80053bc: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 80053c0: f503 1384 add.w r3, r3, #1081344 ; 0x108000 80053c4: 009b lsls r3, r3, #2 80053c6: 461a mov r2, r3 80053c8: 2300 movs r3, #0 80053ca: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80053cc: f7fc ff4a bl 8002264 80053d0: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80053d4: e009 b.n 80053ea { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80053d6: f7fc ff45 bl 8002264 80053da: 4602 mov r2, r0 80053dc: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 80053e0: 1ad3 subs r3, r2, r3 80053e2: 2b02 cmp r3, #2 80053e4: d901 bls.n 80053ea { return HAL_TIMEOUT; 80053e6: 2303 movs r3, #3 80053e8: e09e b.n 8005528 80053ea: f507 7300 add.w r3, r7, #512 ; 0x200 80053ee: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8 80053f2: f04f 7200 mov.w r2, #33554432 ; 0x2000000 80053f6: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80053f8: f507 7300 add.w r3, r7, #512 ; 0x200 80053fc: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8 8005400: 681b ldr r3, [r3, #0] 8005402: fa93 f2a3 rbit r2, r3 8005406: f507 7300 add.w r3, r7, #512 ; 0x200 800540a: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc 800540e: 601a str r2, [r3, #0] return result; 8005410: f507 7300 add.w r3, r7, #512 ; 0x200 8005414: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc 8005418: 681b ldr r3, [r3, #0] while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800541a: fab3 f383 clz r3, r3 800541e: b2db uxtb r3, r3 8005420: 095b lsrs r3, r3, #5 8005422: b2db uxtb r3, r3 8005424: f043 0301 orr.w r3, r3, #1 8005428: b2db uxtb r3, r3 800542a: 2b01 cmp r3, #1 800542c: d104 bne.n 8005438 800542e: 4b01 ldr r3, [pc, #4] ; (8005434 ) 8005430: 681b ldr r3, [r3, #0] 8005432: e029 b.n 8005488 8005434: 40021000 .word 0x40021000 8005438: f507 7300 add.w r3, r7, #512 ; 0x200 800543c: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0 8005440: f04f 7200 mov.w r2, #33554432 ; 0x2000000 8005444: 601a str r2, [r3, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005446: f507 7300 add.w r3, r7, #512 ; 0x200 800544a: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0 800544e: 681b ldr r3, [r3, #0] 8005450: fa93 f2a3 rbit r2, r3 8005454: f507 7300 add.w r3, r7, #512 ; 0x200 8005458: f5a3 73f2 sub.w r3, r3, #484 ; 0x1e4 800545c: 601a str r2, [r3, #0] 800545e: f507 7300 add.w r3, r7, #512 ; 0x200 8005462: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8 8005466: f04f 7200 mov.w r2, #33554432 ; 0x2000000 800546a: 601a str r2, [r3, #0] 800546c: f507 7300 add.w r3, r7, #512 ; 0x200 8005470: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8 8005474: 681b ldr r3, [r3, #0] 8005476: fa93 f2a3 rbit r2, r3 800547a: f507 7300 add.w r3, r7, #512 ; 0x200 800547e: f5a3 73f6 sub.w r3, r3, #492 ; 0x1ec 8005482: 601a str r2, [r3, #0] 8005484: 4b2b ldr r3, [pc, #172] ; (8005534 ) 8005486: 6a5b ldr r3, [r3, #36] ; 0x24 8005488: f507 7200 add.w r2, r7, #512 ; 0x200 800548c: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0 8005490: f04f 7100 mov.w r1, #33554432 ; 0x2000000 8005494: 6011 str r1, [r2, #0] 8005496: f507 7200 add.w r2, r7, #512 ; 0x200 800549a: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0 800549e: 6812 ldr r2, [r2, #0] 80054a0: fa92 f1a2 rbit r1, r2 80054a4: f507 7200 add.w r2, r7, #512 ; 0x200 80054a8: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4 80054ac: 6011 str r1, [r2, #0] return result; 80054ae: f507 7200 add.w r2, r7, #512 ; 0x200 80054b2: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4 80054b6: 6812 ldr r2, [r2, #0] 80054b8: fab2 f282 clz r2, r2 80054bc: b2d2 uxtb r2, r2 80054be: f042 0220 orr.w r2, r2, #32 80054c2: b2d2 uxtb r2, r2 80054c4: f002 021f and.w r2, r2, #31 80054c8: 2101 movs r1, #1 80054ca: fa01 f202 lsl.w r2, r1, r2 80054ce: 4013 ands r3, r2 80054d0: 2b00 cmp r3, #0 80054d2: d180 bne.n 80053d6 80054d4: e027 b.n 8005526 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80054d6: f507 7300 add.w r3, r7, #512 ; 0x200 80054da: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 80054de: 681b ldr r3, [r3, #0] 80054e0: 69db ldr r3, [r3, #28] 80054e2: 2b01 cmp r3, #1 80054e4: d101 bne.n 80054ea { return HAL_ERROR; 80054e6: 2301 movs r3, #1 80054e8: e01e b.n 8005528 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 80054ea: 4b12 ldr r3, [pc, #72] ; (8005534 ) 80054ec: 685b ldr r3, [r3, #4] 80054ee: f8c7 31f4 str.w r3, [r7, #500] ; 0x1f4 pll_config2 = RCC->CFGR2; if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) #else if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80054f2: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4 80054f6: f403 3280 and.w r2, r3, #65536 ; 0x10000 80054fa: f507 7300 add.w r3, r7, #512 ; 0x200 80054fe: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 8005502: 681b ldr r3, [r3, #0] 8005504: 6a1b ldr r3, [r3, #32] 8005506: 429a cmp r2, r3 8005508: d10b bne.n 8005522 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 800550a: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4 800550e: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8005512: f507 7300 add.w r3, r7, #512 ; 0x200 8005516: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc 800551a: 681b ldr r3, [r3, #0] 800551c: 6a5b ldr r3, [r3, #36] ; 0x24 if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800551e: 429a cmp r2, r3 8005520: d001 beq.n 8005526 #endif { return HAL_ERROR; 8005522: 2301 movs r3, #1 8005524: e000 b.n 8005528 } } } } return HAL_OK; 8005526: 2300 movs r3, #0 } 8005528: 4618 mov r0, r3 800552a: f507 7700 add.w r7, r7, #512 ; 0x200 800552e: 46bd mov sp, r7 8005530: bd80 pop {r7, pc} 8005532: bf00 nop 8005534: 40021000 .word 0x40021000 08005538 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8005538: b580 push {r7, lr} 800553a: b09e sub sp, #120 ; 0x78 800553c: af00 add r7, sp, #0 800553e: 6078 str r0, [r7, #4] 8005540: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 8005542: 2300 movs r3, #0 8005544: 677b str r3, [r7, #116] ; 0x74 /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8005546: 687b ldr r3, [r7, #4] 8005548: 2b00 cmp r3, #0 800554a: d101 bne.n 8005550 { return HAL_ERROR; 800554c: 2301 movs r3, #1 800554e: e162 b.n 8005816 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8005550: 4b90 ldr r3, [pc, #576] ; (8005794 ) 8005552: 681b ldr r3, [r3, #0] 8005554: f003 0307 and.w r3, r3, #7 8005558: 683a ldr r2, [r7, #0] 800555a: 429a cmp r2, r3 800555c: d910 bls.n 8005580 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800555e: 4b8d ldr r3, [pc, #564] ; (8005794 ) 8005560: 681b ldr r3, [r3, #0] 8005562: f023 0207 bic.w r2, r3, #7 8005566: 498b ldr r1, [pc, #556] ; (8005794 ) 8005568: 683b ldr r3, [r7, #0] 800556a: 4313 orrs r3, r2 800556c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 800556e: 4b89 ldr r3, [pc, #548] ; (8005794 ) 8005570: 681b ldr r3, [r3, #0] 8005572: f003 0307 and.w r3, r3, #7 8005576: 683a ldr r2, [r7, #0] 8005578: 429a cmp r2, r3 800557a: d001 beq.n 8005580 { return HAL_ERROR; 800557c: 2301 movs r3, #1 800557e: e14a b.n 8005816 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8005580: 687b ldr r3, [r7, #4] 8005582: 681b ldr r3, [r3, #0] 8005584: f003 0302 and.w r3, r3, #2 8005588: 2b00 cmp r3, #0 800558a: d008 beq.n 800559e { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800558c: 4b82 ldr r3, [pc, #520] ; (8005798 ) 800558e: 685b ldr r3, [r3, #4] 8005590: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8005594: 687b ldr r3, [r7, #4] 8005596: 689b ldr r3, [r3, #8] 8005598: 497f ldr r1, [pc, #508] ; (8005798 ) 800559a: 4313 orrs r3, r2 800559c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800559e: 687b ldr r3, [r7, #4] 80055a0: 681b ldr r3, [r3, #0] 80055a2: f003 0301 and.w r3, r3, #1 80055a6: 2b00 cmp r3, #0 80055a8: f000 80dc beq.w 8005764 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80055ac: 687b ldr r3, [r7, #4] 80055ae: 685b ldr r3, [r3, #4] 80055b0: 2b01 cmp r3, #1 80055b2: d13c bne.n 800562e 80055b4: f44f 3300 mov.w r3, #131072 ; 0x20000 80055b8: 673b str r3, [r7, #112] ; 0x70 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80055ba: 6f3b ldr r3, [r7, #112] ; 0x70 80055bc: fa93 f3a3 rbit r3, r3 80055c0: 66fb str r3, [r7, #108] ; 0x6c return result; 80055c2: 6efb ldr r3, [r7, #108] ; 0x6c { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80055c4: fab3 f383 clz r3, r3 80055c8: b2db uxtb r3, r3 80055ca: 095b lsrs r3, r3, #5 80055cc: b2db uxtb r3, r3 80055ce: f043 0301 orr.w r3, r3, #1 80055d2: b2db uxtb r3, r3 80055d4: 2b01 cmp r3, #1 80055d6: d102 bne.n 80055de 80055d8: 4b6f ldr r3, [pc, #444] ; (8005798 ) 80055da: 681b ldr r3, [r3, #0] 80055dc: e00f b.n 80055fe 80055de: f44f 3300 mov.w r3, #131072 ; 0x20000 80055e2: 66bb str r3, [r7, #104] ; 0x68 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80055e4: 6ebb ldr r3, [r7, #104] ; 0x68 80055e6: fa93 f3a3 rbit r3, r3 80055ea: 667b str r3, [r7, #100] ; 0x64 80055ec: f44f 3300 mov.w r3, #131072 ; 0x20000 80055f0: 663b str r3, [r7, #96] ; 0x60 80055f2: 6e3b ldr r3, [r7, #96] ; 0x60 80055f4: fa93 f3a3 rbit r3, r3 80055f8: 65fb str r3, [r7, #92] ; 0x5c 80055fa: 4b67 ldr r3, [pc, #412] ; (8005798 ) 80055fc: 6a5b ldr r3, [r3, #36] ; 0x24 80055fe: f44f 3200 mov.w r2, #131072 ; 0x20000 8005602: 65ba str r2, [r7, #88] ; 0x58 8005604: 6dba ldr r2, [r7, #88] ; 0x58 8005606: fa92 f2a2 rbit r2, r2 800560a: 657a str r2, [r7, #84] ; 0x54 return result; 800560c: 6d7a ldr r2, [r7, #84] ; 0x54 800560e: fab2 f282 clz r2, r2 8005612: b2d2 uxtb r2, r2 8005614: f042 0220 orr.w r2, r2, #32 8005618: b2d2 uxtb r2, r2 800561a: f002 021f and.w r2, r2, #31 800561e: 2101 movs r1, #1 8005620: fa01 f202 lsl.w r2, r1, r2 8005624: 4013 ands r3, r2 8005626: 2b00 cmp r3, #0 8005628: d17b bne.n 8005722 { return HAL_ERROR; 800562a: 2301 movs r3, #1 800562c: e0f3 b.n 8005816 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800562e: 687b ldr r3, [r7, #4] 8005630: 685b ldr r3, [r3, #4] 8005632: 2b02 cmp r3, #2 8005634: d13c bne.n 80056b0 8005636: f04f 7300 mov.w r3, #33554432 ; 0x2000000 800563a: 653b str r3, [r7, #80] ; 0x50 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800563c: 6d3b ldr r3, [r7, #80] ; 0x50 800563e: fa93 f3a3 rbit r3, r3 8005642: 64fb str r3, [r7, #76] ; 0x4c return result; 8005644: 6cfb ldr r3, [r7, #76] ; 0x4c { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005646: fab3 f383 clz r3, r3 800564a: b2db uxtb r3, r3 800564c: 095b lsrs r3, r3, #5 800564e: b2db uxtb r3, r3 8005650: f043 0301 orr.w r3, r3, #1 8005654: b2db uxtb r3, r3 8005656: 2b01 cmp r3, #1 8005658: d102 bne.n 8005660 800565a: 4b4f ldr r3, [pc, #316] ; (8005798 ) 800565c: 681b ldr r3, [r3, #0] 800565e: e00f b.n 8005680 8005660: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8005664: 64bb str r3, [r7, #72] ; 0x48 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005666: 6cbb ldr r3, [r7, #72] ; 0x48 8005668: fa93 f3a3 rbit r3, r3 800566c: 647b str r3, [r7, #68] ; 0x44 800566e: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8005672: 643b str r3, [r7, #64] ; 0x40 8005674: 6c3b ldr r3, [r7, #64] ; 0x40 8005676: fa93 f3a3 rbit r3, r3 800567a: 63fb str r3, [r7, #60] ; 0x3c 800567c: 4b46 ldr r3, [pc, #280] ; (8005798 ) 800567e: 6a5b ldr r3, [r3, #36] ; 0x24 8005680: f04f 7200 mov.w r2, #33554432 ; 0x2000000 8005684: 63ba str r2, [r7, #56] ; 0x38 8005686: 6bba ldr r2, [r7, #56] ; 0x38 8005688: fa92 f2a2 rbit r2, r2 800568c: 637a str r2, [r7, #52] ; 0x34 return result; 800568e: 6b7a ldr r2, [r7, #52] ; 0x34 8005690: fab2 f282 clz r2, r2 8005694: b2d2 uxtb r2, r2 8005696: f042 0220 orr.w r2, r2, #32 800569a: b2d2 uxtb r2, r2 800569c: f002 021f and.w r2, r2, #31 80056a0: 2101 movs r1, #1 80056a2: fa01 f202 lsl.w r2, r1, r2 80056a6: 4013 ands r3, r2 80056a8: 2b00 cmp r3, #0 80056aa: d13a bne.n 8005722 { return HAL_ERROR; 80056ac: 2301 movs r3, #1 80056ae: e0b2 b.n 8005816 80056b0: 2302 movs r3, #2 80056b2: 633b str r3, [r7, #48] ; 0x30 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80056b4: 6b3b ldr r3, [r7, #48] ; 0x30 80056b6: fa93 f3a3 rbit r3, r3 80056ba: 62fb str r3, [r7, #44] ; 0x2c return result; 80056bc: 6afb ldr r3, [r7, #44] ; 0x2c } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80056be: fab3 f383 clz r3, r3 80056c2: b2db uxtb r3, r3 80056c4: 095b lsrs r3, r3, #5 80056c6: b2db uxtb r3, r3 80056c8: f043 0301 orr.w r3, r3, #1 80056cc: b2db uxtb r3, r3 80056ce: 2b01 cmp r3, #1 80056d0: d102 bne.n 80056d8 80056d2: 4b31 ldr r3, [pc, #196] ; (8005798 ) 80056d4: 681b ldr r3, [r3, #0] 80056d6: e00d b.n 80056f4 80056d8: 2302 movs r3, #2 80056da: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80056dc: 6abb ldr r3, [r7, #40] ; 0x28 80056de: fa93 f3a3 rbit r3, r3 80056e2: 627b str r3, [r7, #36] ; 0x24 80056e4: 2302 movs r3, #2 80056e6: 623b str r3, [r7, #32] 80056e8: 6a3b ldr r3, [r7, #32] 80056ea: fa93 f3a3 rbit r3, r3 80056ee: 61fb str r3, [r7, #28] 80056f0: 4b29 ldr r3, [pc, #164] ; (8005798 ) 80056f2: 6a5b ldr r3, [r3, #36] ; 0x24 80056f4: 2202 movs r2, #2 80056f6: 61ba str r2, [r7, #24] 80056f8: 69ba ldr r2, [r7, #24] 80056fa: fa92 f2a2 rbit r2, r2 80056fe: 617a str r2, [r7, #20] return result; 8005700: 697a ldr r2, [r7, #20] 8005702: fab2 f282 clz r2, r2 8005706: b2d2 uxtb r2, r2 8005708: f042 0220 orr.w r2, r2, #32 800570c: b2d2 uxtb r2, r2 800570e: f002 021f and.w r2, r2, #31 8005712: 2101 movs r1, #1 8005714: fa01 f202 lsl.w r2, r1, r2 8005718: 4013 ands r3, r2 800571a: 2b00 cmp r3, #0 800571c: d101 bne.n 8005722 { return HAL_ERROR; 800571e: 2301 movs r3, #1 8005720: e079 b.n 8005816 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8005722: 4b1d ldr r3, [pc, #116] ; (8005798 ) 8005724: 685b ldr r3, [r3, #4] 8005726: f023 0203 bic.w r2, r3, #3 800572a: 687b ldr r3, [r7, #4] 800572c: 685b ldr r3, [r3, #4] 800572e: 491a ldr r1, [pc, #104] ; (8005798 ) 8005730: 4313 orrs r3, r2 8005732: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005734: f7fc fd96 bl 8002264 8005738: 6778 str r0, [r7, #116] ; 0x74 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800573a: e00a b.n 8005752 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800573c: f7fc fd92 bl 8002264 8005740: 4602 mov r2, r0 8005742: 6f7b ldr r3, [r7, #116] ; 0x74 8005744: 1ad3 subs r3, r2, r3 8005746: f241 3288 movw r2, #5000 ; 0x1388 800574a: 4293 cmp r3, r2 800574c: d901 bls.n 8005752 { return HAL_TIMEOUT; 800574e: 2303 movs r3, #3 8005750: e061 b.n 8005816 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8005752: 4b11 ldr r3, [pc, #68] ; (8005798 ) 8005754: 685b ldr r3, [r3, #4] 8005756: f003 020c and.w r2, r3, #12 800575a: 687b ldr r3, [r7, #4] 800575c: 685b ldr r3, [r3, #4] 800575e: 009b lsls r3, r3, #2 8005760: 429a cmp r2, r3 8005762: d1eb bne.n 800573c } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8005764: 4b0b ldr r3, [pc, #44] ; (8005794 ) 8005766: 681b ldr r3, [r3, #0] 8005768: f003 0307 and.w r3, r3, #7 800576c: 683a ldr r2, [r7, #0] 800576e: 429a cmp r2, r3 8005770: d214 bcs.n 800579c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8005772: 4b08 ldr r3, [pc, #32] ; (8005794 ) 8005774: 681b ldr r3, [r3, #0] 8005776: f023 0207 bic.w r2, r3, #7 800577a: 4906 ldr r1, [pc, #24] ; (8005794 ) 800577c: 683b ldr r3, [r7, #0] 800577e: 4313 orrs r3, r2 8005780: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8005782: 4b04 ldr r3, [pc, #16] ; (8005794 ) 8005784: 681b ldr r3, [r3, #0] 8005786: f003 0307 and.w r3, r3, #7 800578a: 683a ldr r2, [r7, #0] 800578c: 429a cmp r2, r3 800578e: d005 beq.n 800579c { return HAL_ERROR; 8005790: 2301 movs r3, #1 8005792: e040 b.n 8005816 8005794: 40022000 .word 0x40022000 8005798: 40021000 .word 0x40021000 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800579c: 687b ldr r3, [r7, #4] 800579e: 681b ldr r3, [r3, #0] 80057a0: f003 0304 and.w r3, r3, #4 80057a4: 2b00 cmp r3, #0 80057a6: d008 beq.n 80057ba { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80057a8: 4b1d ldr r3, [pc, #116] ; (8005820 ) 80057aa: 685b ldr r3, [r3, #4] 80057ac: f423 62e0 bic.w r2, r3, #1792 ; 0x700 80057b0: 687b ldr r3, [r7, #4] 80057b2: 68db ldr r3, [r3, #12] 80057b4: 491a ldr r1, [pc, #104] ; (8005820 ) 80057b6: 4313 orrs r3, r2 80057b8: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80057ba: 687b ldr r3, [r7, #4] 80057bc: 681b ldr r3, [r3, #0] 80057be: f003 0308 and.w r3, r3, #8 80057c2: 2b00 cmp r3, #0 80057c4: d009 beq.n 80057da { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 80057c6: 4b16 ldr r3, [pc, #88] ; (8005820 ) 80057c8: 685b ldr r3, [r3, #4] 80057ca: f423 5260 bic.w r2, r3, #14336 ; 0x3800 80057ce: 687b ldr r3, [r7, #4] 80057d0: 691b ldr r3, [r3, #16] 80057d2: 00db lsls r3, r3, #3 80057d4: 4912 ldr r1, [pc, #72] ; (8005820 ) 80057d6: 4313 orrs r3, r2 80057d8: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 80057da: f000 f829 bl 8005830 80057de: 4601 mov r1, r0 80057e0: 4b0f ldr r3, [pc, #60] ; (8005820 ) 80057e2: 685b ldr r3, [r3, #4] 80057e4: f003 03f0 and.w r3, r3, #240 ; 0xf0 80057e8: 22f0 movs r2, #240 ; 0xf0 80057ea: 613a str r2, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80057ec: 693a ldr r2, [r7, #16] 80057ee: fa92 f2a2 rbit r2, r2 80057f2: 60fa str r2, [r7, #12] return result; 80057f4: 68fa ldr r2, [r7, #12] 80057f6: fab2 f282 clz r2, r2 80057fa: b2d2 uxtb r2, r2 80057fc: 40d3 lsrs r3, r2 80057fe: 4a09 ldr r2, [pc, #36] ; (8005824 ) 8005800: 5cd3 ldrb r3, [r2, r3] 8005802: fa21 f303 lsr.w r3, r1, r3 8005806: 4a08 ldr r2, [pc, #32] ; (8005828 ) 8005808: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (uwTickPrio); 800580a: 4b08 ldr r3, [pc, #32] ; (800582c ) 800580c: 681b ldr r3, [r3, #0] 800580e: 4618 mov r0, r3 8005810: f7fc fce4 bl 80021dc return HAL_OK; 8005814: 2300 movs r3, #0 } 8005816: 4618 mov r0, r3 8005818: 3778 adds r7, #120 ; 0x78 800581a: 46bd mov sp, r7 800581c: bd80 pop {r7, pc} 800581e: bf00 nop 8005820: 40021000 .word 0x40021000 8005824: 080064e0 .word 0x080064e0 8005828: 20000008 .word 0x20000008 800582c: 2000000c .word 0x2000000c 08005830 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8005830: b480 push {r7} 8005832: b08b sub sp, #44 ; 0x2c 8005834: af00 add r7, sp, #0 uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8005836: 2300 movs r3, #0 8005838: 61fb str r3, [r7, #28] 800583a: 2300 movs r3, #0 800583c: 61bb str r3, [r7, #24] 800583e: 2300 movs r3, #0 8005840: 627b str r3, [r7, #36] ; 0x24 8005842: 2300 movs r3, #0 8005844: 617b str r3, [r7, #20] uint32_t sysclockfreq = 0U; 8005846: 2300 movs r3, #0 8005848: 623b str r3, [r7, #32] tmpreg = RCC->CFGR; 800584a: 4b29 ldr r3, [pc, #164] ; (80058f0 ) 800584c: 685b ldr r3, [r3, #4] 800584e: 61fb str r3, [r7, #28] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8005850: 69fb ldr r3, [r7, #28] 8005852: f003 030c and.w r3, r3, #12 8005856: 2b04 cmp r3, #4 8005858: d002 beq.n 8005860 800585a: 2b08 cmp r3, #8 800585c: d003 beq.n 8005866 800585e: e03c b.n 80058da { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8005860: 4b24 ldr r3, [pc, #144] ; (80058f4 ) 8005862: 623b str r3, [r7, #32] break; 8005864: e03c b.n 80058e0 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; 8005866: 69fb ldr r3, [r7, #28] 8005868: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 800586c: f44f 1270 mov.w r2, #3932160 ; 0x3c0000 8005870: 60ba str r2, [r7, #8] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005872: 68ba ldr r2, [r7, #8] 8005874: fa92 f2a2 rbit r2, r2 8005878: 607a str r2, [r7, #4] return result; 800587a: 687a ldr r2, [r7, #4] 800587c: fab2 f282 clz r2, r2 8005880: b2d2 uxtb r2, r2 8005882: 40d3 lsrs r3, r2 8005884: 4a1c ldr r2, [pc, #112] ; (80058f8 ) 8005886: 5cd3 ldrb r3, [r2, r3] 8005888: 617b str r3, [r7, #20] prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)]; 800588a: 4b19 ldr r3, [pc, #100] ; (80058f0 ) 800588c: 6adb ldr r3, [r3, #44] ; 0x2c 800588e: f003 030f and.w r3, r3, #15 8005892: 220f movs r2, #15 8005894: 613a str r2, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005896: 693a ldr r2, [r7, #16] 8005898: fa92 f2a2 rbit r2, r2 800589c: 60fa str r2, [r7, #12] return result; 800589e: 68fa ldr r2, [r7, #12] 80058a0: fab2 f282 clz r2, r2 80058a4: b2d2 uxtb r2, r2 80058a6: 40d3 lsrs r3, r2 80058a8: 4a14 ldr r2, [pc, #80] ; (80058fc ) 80058aa: 5cd3 ldrb r3, [r2, r3] 80058ac: 61bb str r3, [r7, #24] #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) 80058ae: 69fb ldr r3, [r7, #28] 80058b0: f403 3380 and.w r3, r3, #65536 ; 0x10000 80058b4: 2b00 cmp r3, #0 80058b6: d008 beq.n 80058ca { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 80058b8: 4a0e ldr r2, [pc, #56] ; (80058f4 ) 80058ba: 69bb ldr r3, [r7, #24] 80058bc: fbb2 f2f3 udiv r2, r2, r3 80058c0: 697b ldr r3, [r7, #20] 80058c2: fb02 f303 mul.w r3, r2, r3 80058c6: 627b str r3, [r7, #36] ; 0x24 80058c8: e004 b.n 80058d4 } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 80058ca: 697b ldr r3, [r7, #20] 80058cc: 4a0c ldr r2, [pc, #48] ; (8005900 ) 80058ce: fb02 f303 mul.w r3, r2, r3 80058d2: 627b str r3, [r7, #36] ; 0x24 { /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); } #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ sysclockfreq = pllclk; 80058d4: 6a7b ldr r3, [r7, #36] ; 0x24 80058d6: 623b str r3, [r7, #32] break; 80058d8: e002 b.n 80058e0 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80058da: 4b0a ldr r3, [pc, #40] ; (8005904 ) 80058dc: 623b str r3, [r7, #32] break; 80058de: bf00 nop } } return sysclockfreq; 80058e0: 6a3b ldr r3, [r7, #32] } 80058e2: 4618 mov r0, r3 80058e4: 372c adds r7, #44 ; 0x2c 80058e6: 46bd mov sp, r7 80058e8: f85d 7b04 ldr.w r7, [sp], #4 80058ec: 4770 bx lr 80058ee: bf00 nop 80058f0: 40021000 .word 0x40021000 80058f4: 00f42400 .word 0x00f42400 80058f8: 080064f0 .word 0x080064f0 80058fc: 08006500 .word 0x08006500 8005900: 003d0900 .word 0x003d0900 8005904: 007a1200 .word 0x007a1200 08005908 : * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8005908: b580 push {r7, lr} 800590a: b092 sub sp, #72 ; 0x48 800590c: af00 add r7, sp, #0 800590e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8005910: 2300 movs r3, #0 8005912: 643b str r3, [r7, #64] ; 0x40 uint32_t temp_reg = 0U; 8005914: 2300 movs r3, #0 8005916: 63fb str r3, [r7, #60] ; 0x3c FlagStatus pwrclkchanged = RESET; 8005918: 2300 movs r3, #0 800591a: f887 3047 strb.w r3, [r7, #71] ; 0x47 /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 800591e: 687b ldr r3, [r7, #4] 8005920: 681b ldr r3, [r3, #0] 8005922: f403 3380 and.w r3, r3, #65536 ; 0x10000 8005926: 2b00 cmp r3, #0 8005928: f000 80d4 beq.w 8005ad4 /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 800592c: 4b4e ldr r3, [pc, #312] ; (8005a68 ) 800592e: 69db ldr r3, [r3, #28] 8005930: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8005934: 2b00 cmp r3, #0 8005936: d10e bne.n 8005956 { __HAL_RCC_PWR_CLK_ENABLE(); 8005938: 4b4b ldr r3, [pc, #300] ; (8005a68 ) 800593a: 69db ldr r3, [r3, #28] 800593c: 4a4a ldr r2, [pc, #296] ; (8005a68 ) 800593e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8005942: 61d3 str r3, [r2, #28] 8005944: 4b48 ldr r3, [pc, #288] ; (8005a68 ) 8005946: 69db ldr r3, [r3, #28] 8005948: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800594c: 60bb str r3, [r7, #8] 800594e: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8005950: 2301 movs r3, #1 8005952: f887 3047 strb.w r3, [r7, #71] ; 0x47 } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005956: 4b45 ldr r3, [pc, #276] ; (8005a6c ) 8005958: 681b ldr r3, [r3, #0] 800595a: f403 7380 and.w r3, r3, #256 ; 0x100 800595e: 2b00 cmp r3, #0 8005960: d118 bne.n 8005994 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8005962: 4b42 ldr r3, [pc, #264] ; (8005a6c ) 8005964: 681b ldr r3, [r3, #0] 8005966: 4a41 ldr r2, [pc, #260] ; (8005a6c ) 8005968: f443 7380 orr.w r3, r3, #256 ; 0x100 800596c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800596e: f7fc fc79 bl 8002264 8005972: 6438 str r0, [r7, #64] ; 0x40 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005974: e008 b.n 8005988 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8005976: f7fc fc75 bl 8002264 800597a: 4602 mov r2, r0 800597c: 6c3b ldr r3, [r7, #64] ; 0x40 800597e: 1ad3 subs r3, r2, r3 8005980: 2b64 cmp r3, #100 ; 0x64 8005982: d901 bls.n 8005988 { return HAL_TIMEOUT; 8005984: 2303 movs r3, #3 8005986: e14b b.n 8005c20 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005988: 4b38 ldr r3, [pc, #224] ; (8005a6c ) 800598a: 681b ldr r3, [r3, #0] 800598c: f403 7380 and.w r3, r3, #256 ; 0x100 8005990: 2b00 cmp r3, #0 8005992: d0f0 beq.n 8005976 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8005994: 4b34 ldr r3, [pc, #208] ; (8005a68 ) 8005996: 6a1b ldr r3, [r3, #32] 8005998: f403 7340 and.w r3, r3, #768 ; 0x300 800599c: 63fb str r3, [r7, #60] ; 0x3c if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 800599e: 6bfb ldr r3, [r7, #60] ; 0x3c 80059a0: 2b00 cmp r3, #0 80059a2: f000 8084 beq.w 8005aae 80059a6: 687b ldr r3, [r7, #4] 80059a8: 685b ldr r3, [r3, #4] 80059aa: f403 7340 and.w r3, r3, #768 ; 0x300 80059ae: 6bfa ldr r2, [r7, #60] ; 0x3c 80059b0: 429a cmp r2, r3 80059b2: d07c beq.n 8005aae { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80059b4: 4b2c ldr r3, [pc, #176] ; (8005a68 ) 80059b6: 6a1b ldr r3, [r3, #32] 80059b8: f423 7340 bic.w r3, r3, #768 ; 0x300 80059bc: 63fb str r3, [r7, #60] ; 0x3c 80059be: f44f 3380 mov.w r3, #65536 ; 0x10000 80059c2: 633b str r3, [r7, #48] ; 0x30 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80059c4: 6b3b ldr r3, [r7, #48] ; 0x30 80059c6: fa93 f3a3 rbit r3, r3 80059ca: 62fb str r3, [r7, #44] ; 0x2c return result; 80059cc: 6afb ldr r3, [r7, #44] ; 0x2c /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80059ce: fab3 f383 clz r3, r3 80059d2: b2db uxtb r3, r3 80059d4: 461a mov r2, r3 80059d6: 4b26 ldr r3, [pc, #152] ; (8005a70 ) 80059d8: 4413 add r3, r2 80059da: 009b lsls r3, r3, #2 80059dc: 461a mov r2, r3 80059de: 2301 movs r3, #1 80059e0: 6013 str r3, [r2, #0] 80059e2: f44f 3380 mov.w r3, #65536 ; 0x10000 80059e6: 63bb str r3, [r7, #56] ; 0x38 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80059e8: 6bbb ldr r3, [r7, #56] ; 0x38 80059ea: fa93 f3a3 rbit r3, r3 80059ee: 637b str r3, [r7, #52] ; 0x34 return result; 80059f0: 6b7b ldr r3, [r7, #52] ; 0x34 __HAL_RCC_BACKUPRESET_RELEASE(); 80059f2: fab3 f383 clz r3, r3 80059f6: b2db uxtb r3, r3 80059f8: 461a mov r2, r3 80059fa: 4b1d ldr r3, [pc, #116] ; (8005a70 ) 80059fc: 4413 add r3, r2 80059fe: 009b lsls r3, r3, #2 8005a00: 461a mov r2, r3 8005a02: 2300 movs r3, #0 8005a04: 6013 str r3, [r2, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8005a06: 4a18 ldr r2, [pc, #96] ; (8005a68 ) 8005a08: 6bfb ldr r3, [r7, #60] ; 0x3c 8005a0a: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8005a0c: 6bfb ldr r3, [r7, #60] ; 0x3c 8005a0e: f003 0301 and.w r3, r3, #1 8005a12: 2b00 cmp r3, #0 8005a14: d04b beq.n 8005aae { /* Get Start Tick */ tickstart = HAL_GetTick(); 8005a16: f7fc fc25 bl 8002264 8005a1a: 6438 str r0, [r7, #64] ; 0x40 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005a1c: e00a b.n 8005a34 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005a1e: f7fc fc21 bl 8002264 8005a22: 4602 mov r2, r0 8005a24: 6c3b ldr r3, [r7, #64] ; 0x40 8005a26: 1ad3 subs r3, r2, r3 8005a28: f241 3288 movw r2, #5000 ; 0x1388 8005a2c: 4293 cmp r3, r2 8005a2e: d901 bls.n 8005a34 { return HAL_TIMEOUT; 8005a30: 2303 movs r3, #3 8005a32: e0f5 b.n 8005c20 8005a34: 2302 movs r3, #2 8005a36: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005a38: 6abb ldr r3, [r7, #40] ; 0x28 8005a3a: fa93 f3a3 rbit r3, r3 8005a3e: 627b str r3, [r7, #36] ; 0x24 8005a40: 2302 movs r3, #2 8005a42: 623b str r3, [r7, #32] 8005a44: 6a3b ldr r3, [r7, #32] 8005a46: fa93 f3a3 rbit r3, r3 8005a4a: 61fb str r3, [r7, #28] return result; 8005a4c: 69fb ldr r3, [r7, #28] while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005a4e: fab3 f383 clz r3, r3 8005a52: b2db uxtb r3, r3 8005a54: 095b lsrs r3, r3, #5 8005a56: b2db uxtb r3, r3 8005a58: f043 0302 orr.w r3, r3, #2 8005a5c: b2db uxtb r3, r3 8005a5e: 2b02 cmp r3, #2 8005a60: d108 bne.n 8005a74 8005a62: 4b01 ldr r3, [pc, #4] ; (8005a68 ) 8005a64: 6a1b ldr r3, [r3, #32] 8005a66: e00d b.n 8005a84 8005a68: 40021000 .word 0x40021000 8005a6c: 40007000 .word 0x40007000 8005a70: 10908100 .word 0x10908100 8005a74: 2302 movs r3, #2 8005a76: 61bb str r3, [r7, #24] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005a78: 69bb ldr r3, [r7, #24] 8005a7a: fa93 f3a3 rbit r3, r3 8005a7e: 617b str r3, [r7, #20] 8005a80: 4b69 ldr r3, [pc, #420] ; (8005c28 ) 8005a82: 6a5b ldr r3, [r3, #36] ; 0x24 8005a84: 2202 movs r2, #2 8005a86: 613a str r2, [r7, #16] 8005a88: 693a ldr r2, [r7, #16] 8005a8a: fa92 f2a2 rbit r2, r2 8005a8e: 60fa str r2, [r7, #12] return result; 8005a90: 68fa ldr r2, [r7, #12] 8005a92: fab2 f282 clz r2, r2 8005a96: b2d2 uxtb r2, r2 8005a98: f042 0240 orr.w r2, r2, #64 ; 0x40 8005a9c: b2d2 uxtb r2, r2 8005a9e: f002 021f and.w r2, r2, #31 8005aa2: 2101 movs r1, #1 8005aa4: fa01 f202 lsl.w r2, r1, r2 8005aa8: 4013 ands r3, r2 8005aaa: 2b00 cmp r3, #0 8005aac: d0b7 beq.n 8005a1e } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8005aae: 4b5e ldr r3, [pc, #376] ; (8005c28 ) 8005ab0: 6a1b ldr r3, [r3, #32] 8005ab2: f423 7240 bic.w r2, r3, #768 ; 0x300 8005ab6: 687b ldr r3, [r7, #4] 8005ab8: 685b ldr r3, [r3, #4] 8005aba: 495b ldr r1, [pc, #364] ; (8005c28 ) 8005abc: 4313 orrs r3, r2 8005abe: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8005ac0: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 8005ac4: 2b01 cmp r3, #1 8005ac6: d105 bne.n 8005ad4 { __HAL_RCC_PWR_CLK_DISABLE(); 8005ac8: 4b57 ldr r3, [pc, #348] ; (8005c28 ) 8005aca: 69db ldr r3, [r3, #28] 8005acc: 4a56 ldr r2, [pc, #344] ; (8005c28 ) 8005ace: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8005ad2: 61d3 str r3, [r2, #28] } } /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8005ad4: 687b ldr r3, [r7, #4] 8005ad6: 681b ldr r3, [r3, #0] 8005ad8: f003 0301 and.w r3, r3, #1 8005adc: 2b00 cmp r3, #0 8005ade: d008 beq.n 8005af2 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8005ae0: 4b51 ldr r3, [pc, #324] ; (8005c28 ) 8005ae2: 6b1b ldr r3, [r3, #48] ; 0x30 8005ae4: f023 0203 bic.w r2, r3, #3 8005ae8: 687b ldr r3, [r7, #4] 8005aea: 689b ldr r3, [r3, #8] 8005aec: 494e ldr r1, [pc, #312] ; (8005c28 ) 8005aee: 4313 orrs r3, r2 8005af0: 630b str r3, [r1, #48] ; 0x30 } #if defined(RCC_CFGR3_USART2SW) /*----------------------------- USART2 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 8005af2: 687b ldr r3, [r7, #4] 8005af4: 681b ldr r3, [r3, #0] 8005af6: f003 0302 and.w r3, r3, #2 8005afa: 2b00 cmp r3, #0 8005afc: d008 beq.n 8005b10 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8005afe: 4b4a ldr r3, [pc, #296] ; (8005c28 ) 8005b00: 6b1b ldr r3, [r3, #48] ; 0x30 8005b02: f423 3240 bic.w r2, r3, #196608 ; 0x30000 8005b06: 687b ldr r3, [r7, #4] 8005b08: 68db ldr r3, [r3, #12] 8005b0a: 4947 ldr r1, [pc, #284] ; (8005c28 ) 8005b0c: 4313 orrs r3, r2 8005b0e: 630b str r3, [r1, #48] ; 0x30 } #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) /*------------------------------ USART3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 8005b10: 687b ldr r3, [r7, #4] 8005b12: 681b ldr r3, [r3, #0] 8005b14: f003 0304 and.w r3, r3, #4 8005b18: 2b00 cmp r3, #0 8005b1a: d008 beq.n 8005b2e { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 8005b1c: 4b42 ldr r3, [pc, #264] ; (8005c28 ) 8005b1e: 6b1b ldr r3, [r3, #48] ; 0x30 8005b20: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 8005b24: 687b ldr r3, [r7, #4] 8005b26: 691b ldr r3, [r3, #16] 8005b28: 493f ldr r1, [pc, #252] ; (8005c28 ) 8005b2a: 4313 orrs r3, r2 8005b2c: 630b str r3, [r1, #48] ; 0x30 } #endif /* RCC_CFGR3_USART3SW */ /*------------------------------ I2C1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8005b2e: 687b ldr r3, [r7, #4] 8005b30: 681b ldr r3, [r3, #0] 8005b32: f003 0320 and.w r3, r3, #32 8005b36: 2b00 cmp r3, #0 8005b38: d008 beq.n 8005b4c { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8005b3a: 4b3b ldr r3, [pc, #236] ; (8005c28 ) 8005b3c: 6b1b ldr r3, [r3, #48] ; 0x30 8005b3e: f023 0210 bic.w r2, r3, #16 8005b42: 687b ldr r3, [r7, #4] 8005b44: 69db ldr r3, [r3, #28] 8005b46: 4938 ldr r1, [pc, #224] ; (8005c28 ) 8005b48: 4313 orrs r3, r2 8005b4a: 630b str r3, [r1, #48] ; 0x30 #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) /*------------------------------ USB Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8005b4c: 687b ldr r3, [r7, #4] 8005b4e: 681b ldr r3, [r3, #0] 8005b50: f403 3300 and.w r3, r3, #131072 ; 0x20000 8005b54: 2b00 cmp r3, #0 8005b56: d008 beq.n 8005b6a { /* Check the parameters */ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); 8005b58: 4b33 ldr r3, [pc, #204] ; (8005c28 ) 8005b5a: 685b ldr r3, [r3, #4] 8005b5c: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 8005b60: 687b ldr r3, [r7, #4] 8005b62: 6b1b ldr r3, [r3, #48] ; 0x30 8005b64: 4930 ldr r1, [pc, #192] ; (8005c28 ) 8005b66: 4313 orrs r3, r2 8005b68: 604b str r3, [r1, #4] || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) /*------------------------------ I2C2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 8005b6a: 687b ldr r3, [r7, #4] 8005b6c: 681b ldr r3, [r3, #0] 8005b6e: f003 0340 and.w r3, r3, #64 ; 0x40 8005b72: 2b00 cmp r3, #0 8005b74: d008 beq.n 8005b88 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 8005b76: 4b2c ldr r3, [pc, #176] ; (8005c28 ) 8005b78: 6b1b ldr r3, [r3, #48] ; 0x30 8005b7a: f023 0220 bic.w r2, r3, #32 8005b7e: 687b ldr r3, [r7, #4] 8005b80: 6a1b ldr r3, [r3, #32] 8005b82: 4929 ldr r1, [pc, #164] ; (8005c28 ) 8005b84: 4313 orrs r3, r2 8005b86: 630b str r3, [r1, #48] ; 0x30 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) /*------------------------------ UART4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 8005b88: 687b ldr r3, [r7, #4] 8005b8a: 681b ldr r3, [r3, #0] 8005b8c: f003 0308 and.w r3, r3, #8 8005b90: 2b00 cmp r3, #0 8005b92: d008 beq.n 8005ba6 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 8005b94: 4b24 ldr r3, [pc, #144] ; (8005c28 ) 8005b96: 6b1b ldr r3, [r3, #48] ; 0x30 8005b98: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8005b9c: 687b ldr r3, [r7, #4] 8005b9e: 695b ldr r3, [r3, #20] 8005ba0: 4921 ldr r1, [pc, #132] ; (8005c28 ) 8005ba2: 4313 orrs r3, r2 8005ba4: 630b str r3, [r1, #48] ; 0x30 } /*------------------------------ UART5 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) 8005ba6: 687b ldr r3, [r7, #4] 8005ba8: 681b ldr r3, [r3, #0] 8005baa: f003 0310 and.w r3, r3, #16 8005bae: 2b00 cmp r3, #0 8005bb0: d008 beq.n 8005bc4 { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); 8005bb2: 4b1d ldr r3, [pc, #116] ; (8005c28 ) 8005bb4: 6b1b ldr r3, [r3, #48] ; 0x30 8005bb6: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 8005bba: 687b ldr r3, [r7, #4] 8005bbc: 699b ldr r3, [r3, #24] 8005bbe: 491a ldr r1, [pc, #104] ; (8005c28 ) 8005bc0: 4313 orrs r3, r2 8005bc2: 630b str r3, [r1, #48] ; 0x30 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ I2S Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) 8005bc4: 687b ldr r3, [r7, #4] 8005bc6: 681b ldr r3, [r3, #0] 8005bc8: f403 7300 and.w r3, r3, #512 ; 0x200 8005bcc: 2b00 cmp r3, #0 8005bce: d008 beq.n 8005be2 { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 8005bd0: 4b15 ldr r3, [pc, #84] ; (8005c28 ) 8005bd2: 685b ldr r3, [r3, #4] 8005bd4: f423 0200 bic.w r2, r3, #8388608 ; 0x800000 8005bd8: 687b ldr r3, [r7, #4] 8005bda: 6a9b ldr r3, [r3, #40] ; 0x28 8005bdc: 4912 ldr r1, [pc, #72] ; (8005c28 ) 8005bde: 4313 orrs r3, r2 8005be0: 604b str r3, [r1, #4] #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) 8005be2: 687b ldr r3, [r7, #4] 8005be4: 681b ldr r3, [r3, #0] 8005be6: f003 0380 and.w r3, r3, #128 ; 0x80 8005bea: 2b00 cmp r3, #0 8005bec: d008 beq.n 8005c00 { /* Check the parameters */ assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 8005bee: 4b0e ldr r3, [pc, #56] ; (8005c28 ) 8005bf0: 6adb ldr r3, [r3, #44] ; 0x2c 8005bf2: f423 72f8 bic.w r2, r3, #496 ; 0x1f0 8005bf6: 687b ldr r3, [r7, #4] 8005bf8: 6a5b ldr r3, [r3, #36] ; 0x24 8005bfa: 490b ldr r1, [pc, #44] ; (8005c28 ) 8005bfc: 4313 orrs r3, r2 8005bfe: 62cb str r3, [r1, #44] ; 0x2c || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ TIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) 8005c00: 687b ldr r3, [r7, #4] 8005c02: 681b ldr r3, [r3, #0] 8005c04: f403 5380 and.w r3, r3, #4096 ; 0x1000 8005c08: 2b00 cmp r3, #0 8005c0a: d008 beq.n 8005c1e { /* Check the parameters */ assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); /* Configure the TIM1 clock source */ __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); 8005c0c: 4b06 ldr r3, [pc, #24] ; (8005c28 ) 8005c0e: 6b1b ldr r3, [r3, #48] ; 0x30 8005c10: f423 7280 bic.w r2, r3, #256 ; 0x100 8005c14: 687b ldr r3, [r7, #4] 8005c16: 6adb ldr r3, [r3, #44] ; 0x2c 8005c18: 4903 ldr r1, [pc, #12] ; (8005c28 ) 8005c1a: 4313 orrs r3, r2 8005c1c: 630b str r3, [r1, #48] ; 0x30 __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); } #endif /* STM32F303xE || STM32F398xx */ return HAL_OK; 8005c1e: 2300 movs r3, #0 } 8005c20: 4618 mov r0, r3 8005c22: 3748 adds r7, #72 ; 0x48 8005c24: 46bd mov sp, r7 8005c26: bd80 pop {r7, pc} 8005c28: 40021000 .word 0x40021000 08005c2c : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 8005c2c: b580 push {r7, lr} 8005c2e: b084 sub sp, #16 8005c30: af00 add r7, sp, #0 8005c32: 6078 str r0, [r7, #4] uint32_t frxth; /* Check the SPI handle allocation */ if (hspi == NULL) 8005c34: 687b ldr r3, [r7, #4] 8005c36: 2b00 cmp r3, #0 8005c38: d101 bne.n 8005c3e { return HAL_ERROR; 8005c3a: 2301 movs r3, #1 8005c3c: e09d b.n 8005d7a assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 8005c3e: 687b ldr r3, [r7, #4] 8005c40: 6a5b ldr r3, [r3, #36] ; 0x24 8005c42: 2b00 cmp r3, #0 8005c44: d108 bne.n 8005c58 { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 8005c46: 687b ldr r3, [r7, #4] 8005c48: 685b ldr r3, [r3, #4] 8005c4a: f5b3 7f82 cmp.w r3, #260 ; 0x104 8005c4e: d009 beq.n 8005c64 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8005c50: 687b ldr r3, [r7, #4] 8005c52: 2200 movs r2, #0 8005c54: 61da str r2, [r3, #28] 8005c56: e005 b.n 8005c64 else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 8005c58: 687b ldr r3, [r7, #4] 8005c5a: 2200 movs r2, #0 8005c5c: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 8005c5e: 687b ldr r3, [r7, #4] 8005c60: 2200 movs r2, #0 8005c62: 615a str r2, [r3, #20] { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8005c64: 687b ldr r3, [r7, #4] 8005c66: 2200 movs r2, #0 8005c68: 629a str r2, [r3, #40] ; 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 8005c6a: 687b ldr r3, [r7, #4] 8005c6c: f893 305d ldrb.w r3, [r3, #93] ; 0x5d 8005c70: b2db uxtb r3, r3 8005c72: 2b00 cmp r3, #0 8005c74: d106 bne.n 8005c84 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 8005c76: 687b ldr r3, [r7, #4] 8005c78: 2200 movs r2, #0 8005c7a: f883 205c strb.w r2, [r3, #92] ; 0x5c /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 8005c7e: 6878 ldr r0, [r7, #4] 8005c80: f7fc f9e4 bl 800204c #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 8005c84: 687b ldr r3, [r7, #4] 8005c86: 2202 movs r2, #2 8005c88: f883 205d strb.w r2, [r3, #93] ; 0x5d /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8005c8c: 687b ldr r3, [r7, #4] 8005c8e: 681b ldr r3, [r3, #0] 8005c90: 681a ldr r2, [r3, #0] 8005c92: 687b ldr r3, [r7, #4] 8005c94: 681b ldr r3, [r3, #0] 8005c96: f022 0240 bic.w r2, r2, #64 ; 0x40 8005c9a: 601a str r2, [r3, #0] /* Align by default the rs fifo threshold on the data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8005c9c: 687b ldr r3, [r7, #4] 8005c9e: 68db ldr r3, [r3, #12] 8005ca0: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 8005ca4: d902 bls.n 8005cac { frxth = SPI_RXFIFO_THRESHOLD_HF; 8005ca6: 2300 movs r3, #0 8005ca8: 60fb str r3, [r7, #12] 8005caa: e002 b.n 8005cb2 } else { frxth = SPI_RXFIFO_THRESHOLD_QF; 8005cac: f44f 5380 mov.w r3, #4096 ; 0x1000 8005cb0: 60fb str r3, [r7, #12] } /* CRC calculation is valid only for 16Bit and 8 Bit */ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) 8005cb2: 687b ldr r3, [r7, #4] 8005cb4: 68db ldr r3, [r3, #12] 8005cb6: f5b3 6f70 cmp.w r3, #3840 ; 0xf00 8005cba: d007 beq.n 8005ccc 8005cbc: 687b ldr r3, [r7, #4] 8005cbe: 68db ldr r3, [r3, #12] 8005cc0: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 8005cc4: d002 beq.n 8005ccc { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8005cc6: 687b ldr r3, [r7, #4] 8005cc8: 2200 movs r2, #0 8005cca: 629a str r2, [r3, #40] ; 0x28 } /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 8005ccc: 687b ldr r3, [r7, #4] 8005cce: 685b ldr r3, [r3, #4] 8005cd0: f403 7282 and.w r2, r3, #260 ; 0x104 8005cd4: 687b ldr r3, [r7, #4] 8005cd6: 689b ldr r3, [r3, #8] 8005cd8: f403 4304 and.w r3, r3, #33792 ; 0x8400 8005cdc: 431a orrs r2, r3 8005cde: 687b ldr r3, [r7, #4] 8005ce0: 691b ldr r3, [r3, #16] 8005ce2: f003 0302 and.w r3, r3, #2 8005ce6: 431a orrs r2, r3 8005ce8: 687b ldr r3, [r7, #4] 8005cea: 695b ldr r3, [r3, #20] 8005cec: f003 0301 and.w r3, r3, #1 8005cf0: 431a orrs r2, r3 8005cf2: 687b ldr r3, [r7, #4] 8005cf4: 699b ldr r3, [r3, #24] 8005cf6: f403 7300 and.w r3, r3, #512 ; 0x200 8005cfa: 431a orrs r2, r3 8005cfc: 687b ldr r3, [r7, #4] 8005cfe: 69db ldr r3, [r3, #28] 8005d00: f003 0338 and.w r3, r3, #56 ; 0x38 8005d04: 431a orrs r2, r3 8005d06: 687b ldr r3, [r7, #4] 8005d08: 6a1b ldr r3, [r3, #32] 8005d0a: f003 0380 and.w r3, r3, #128 ; 0x80 8005d0e: ea42 0103 orr.w r1, r2, r3 8005d12: 687b ldr r3, [r7, #4] 8005d14: 6a9b ldr r3, [r3, #40] ; 0x28 8005d16: f403 5200 and.w r2, r3, #8192 ; 0x2000 8005d1a: 687b ldr r3, [r7, #4] 8005d1c: 681b ldr r3, [r3, #0] 8005d1e: 430a orrs r2, r1 8005d20: 601a str r2, [r3, #0] } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | 8005d22: 687b ldr r3, [r7, #4] 8005d24: 699b ldr r3, [r3, #24] 8005d26: 0c1b lsrs r3, r3, #16 8005d28: f003 0204 and.w r2, r3, #4 8005d2c: 687b ldr r3, [r7, #4] 8005d2e: 6a5b ldr r3, [r3, #36] ; 0x24 8005d30: f003 0310 and.w r3, r3, #16 8005d34: 431a orrs r2, r3 8005d36: 687b ldr r3, [r7, #4] 8005d38: 6b5b ldr r3, [r3, #52] ; 0x34 8005d3a: f003 0308 and.w r3, r3, #8 8005d3e: 431a orrs r2, r3 8005d40: 687b ldr r3, [r7, #4] 8005d42: 68db ldr r3, [r3, #12] 8005d44: f403 6370 and.w r3, r3, #3840 ; 0xf00 8005d48: ea42 0103 orr.w r1, r2, r3 8005d4c: 68fb ldr r3, [r7, #12] 8005d4e: f403 5280 and.w r2, r3, #4096 ; 0x1000 8005d52: 687b ldr r3, [r7, #4] 8005d54: 681b ldr r3, [r3, #0] 8005d56: 430a orrs r2, r1 8005d58: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 8005d5a: 687b ldr r3, [r7, #4] 8005d5c: 681b ldr r3, [r3, #0] 8005d5e: 69da ldr r2, [r3, #28] 8005d60: 687b ldr r3, [r7, #4] 8005d62: 681b ldr r3, [r3, #0] 8005d64: f422 6200 bic.w r2, r2, #2048 ; 0x800 8005d68: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8005d6a: 687b ldr r3, [r7, #4] 8005d6c: 2200 movs r2, #0 8005d6e: 661a str r2, [r3, #96] ; 0x60 hspi->State = HAL_SPI_STATE_READY; 8005d70: 687b ldr r3, [r7, #4] 8005d72: 2201 movs r2, #1 8005d74: f883 205d strb.w r2, [r3, #93] ; 0x5d return HAL_OK; 8005d78: 2300 movs r3, #0 } 8005d7a: 4618 mov r0, r3 8005d7c: 3710 adds r7, #16 8005d7e: 46bd mov sp, r7 8005d80: bd80 pop {r7, pc} 08005d82 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { 8005d82: b580 push {r7, lr} 8005d84: b08a sub sp, #40 ; 0x28 8005d86: af00 add r7, sp, #0 8005d88: 60f8 str r0, [r7, #12] 8005d8a: 60b9 str r1, [r7, #8] 8005d8c: 607a str r2, [r7, #4] 8005d8e: 807b strh r3, [r7, #2] __IO uint8_t * ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; 8005d90: 2301 movs r3, #1 8005d92: 627b str r3, [r7, #36] ; 0x24 HAL_StatusTypeDef errorcode = HAL_OK; 8005d94: 2300 movs r3, #0 8005d96: f887 3023 strb.w r3, [r7, #35] ; 0x23 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); 8005d9a: 68fb ldr r3, [r7, #12] 8005d9c: f893 305c ldrb.w r3, [r3, #92] ; 0x5c 8005da0: 2b01 cmp r3, #1 8005da2: d101 bne.n 8005da8 8005da4: 2302 movs r3, #2 8005da6: e1fb b.n 80061a0 8005da8: 68fb ldr r3, [r7, #12] 8005daa: 2201 movs r2, #1 8005dac: f883 205c strb.w r2, [r3, #92] ; 0x5c /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8005db0: f7fc fa58 bl 8002264 8005db4: 61f8 str r0, [r7, #28] /* Init temporary variables */ tmp_state = hspi->State; 8005db6: 68fb ldr r3, [r7, #12] 8005db8: f893 305d ldrb.w r3, [r3, #93] ; 0x5d 8005dbc: 76fb strb r3, [r7, #27] tmp_mode = hspi->Init.Mode; 8005dbe: 68fb ldr r3, [r7, #12] 8005dc0: 685b ldr r3, [r3, #4] 8005dc2: 617b str r3, [r7, #20] initial_TxXferCount = Size; 8005dc4: 887b ldrh r3, [r7, #2] 8005dc6: 827b strh r3, [r7, #18] initial_RxXferCount = Size; 8005dc8: 887b ldrh r3, [r7, #2] 8005dca: 823b strh r3, [r7, #16] #if (USE_SPI_CRC != 0U) spi_cr1 = READ_REG(hspi->Instance->CR1); spi_cr2 = READ_REG(hspi->Instance->CR2); #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ 8005dcc: 7efb ldrb r3, [r7, #27] 8005dce: 2b01 cmp r3, #1 8005dd0: d00e beq.n 8005df0 8005dd2: 697b ldr r3, [r7, #20] 8005dd4: f5b3 7f82 cmp.w r3, #260 ; 0x104 8005dd8: d106 bne.n 8005de8 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) 8005dda: 68fb ldr r3, [r7, #12] 8005ddc: 689b ldr r3, [r3, #8] 8005dde: 2b00 cmp r3, #0 8005de0: d102 bne.n 8005de8 8005de2: 7efb ldrb r3, [r7, #27] 8005de4: 2b04 cmp r3, #4 8005de6: d003 beq.n 8005df0 { errorcode = HAL_BUSY; 8005de8: 2302 movs r3, #2 8005dea: f887 3023 strb.w r3, [r7, #35] ; 0x23 goto error; 8005dee: e1cd b.n 800618c } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 8005df0: 68bb ldr r3, [r7, #8] 8005df2: 2b00 cmp r3, #0 8005df4: d005 beq.n 8005e02 8005df6: 687b ldr r3, [r7, #4] 8005df8: 2b00 cmp r3, #0 8005dfa: d002 beq.n 8005e02 8005dfc: 887b ldrh r3, [r7, #2] 8005dfe: 2b00 cmp r3, #0 8005e00: d103 bne.n 8005e0a { errorcode = HAL_ERROR; 8005e02: 2301 movs r3, #1 8005e04: f887 3023 strb.w r3, [r7, #35] ; 0x23 goto error; 8005e08: e1c0 b.n 800618c } /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 8005e0a: 68fb ldr r3, [r7, #12] 8005e0c: f893 305d ldrb.w r3, [r3, #93] ; 0x5d 8005e10: b2db uxtb r3, r3 8005e12: 2b04 cmp r3, #4 8005e14: d003 beq.n 8005e1e { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 8005e16: 68fb ldr r3, [r7, #12] 8005e18: 2205 movs r2, #5 8005e1a: f883 205d strb.w r2, [r3, #93] ; 0x5d } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8005e1e: 68fb ldr r3, [r7, #12] 8005e20: 2200 movs r2, #0 8005e22: 661a str r2, [r3, #96] ; 0x60 hspi->pRxBuffPtr = (uint8_t *)pRxData; 8005e24: 68fb ldr r3, [r7, #12] 8005e26: 687a ldr r2, [r7, #4] 8005e28: 641a str r2, [r3, #64] ; 0x40 hspi->RxXferCount = Size; 8005e2a: 68fb ldr r3, [r7, #12] 8005e2c: 887a ldrh r2, [r7, #2] 8005e2e: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 hspi->RxXferSize = Size; 8005e32: 68fb ldr r3, [r7, #12] 8005e34: 887a ldrh r2, [r7, #2] 8005e36: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 hspi->pTxBuffPtr = (uint8_t *)pTxData; 8005e3a: 68fb ldr r3, [r7, #12] 8005e3c: 68ba ldr r2, [r7, #8] 8005e3e: 639a str r2, [r3, #56] ; 0x38 hspi->TxXferCount = Size; 8005e40: 68fb ldr r3, [r7, #12] 8005e42: 887a ldrh r2, [r7, #2] 8005e44: 87da strh r2, [r3, #62] ; 0x3e hspi->TxXferSize = Size; 8005e46: 68fb ldr r3, [r7, #12] 8005e48: 887a ldrh r2, [r7, #2] 8005e4a: 879a strh r2, [r3, #60] ; 0x3c /*Init field not used in handle to zero */ hspi->RxISR = NULL; 8005e4c: 68fb ldr r3, [r7, #12] 8005e4e: 2200 movs r2, #0 8005e50: 64da str r2, [r3, #76] ; 0x4c hspi->TxISR = NULL; 8005e52: 68fb ldr r3, [r7, #12] 8005e54: 2200 movs r2, #0 8005e56: 651a str r2, [r3, #80] ; 0x50 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) 8005e58: 68fb ldr r3, [r7, #12] 8005e5a: 68db ldr r3, [r3, #12] 8005e5c: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 8005e60: d802 bhi.n 8005e68 8005e62: 8a3b ldrh r3, [r7, #16] 8005e64: 2b01 cmp r3, #1 8005e66: d908 bls.n 8005e7a { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 8005e68: 68fb ldr r3, [r7, #12] 8005e6a: 681b ldr r3, [r3, #0] 8005e6c: 685a ldr r2, [r3, #4] 8005e6e: 68fb ldr r3, [r7, #12] 8005e70: 681b ldr r3, [r3, #0] 8005e72: f422 5280 bic.w r2, r2, #4096 ; 0x1000 8005e76: 605a str r2, [r3, #4] 8005e78: e007 b.n 8005e8a } else { /* Set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 8005e7a: 68fb ldr r3, [r7, #12] 8005e7c: 681b ldr r3, [r3, #0] 8005e7e: 685a ldr r2, [r3, #4] 8005e80: 68fb ldr r3, [r7, #12] 8005e82: 681b ldr r3, [r3, #0] 8005e84: f442 5280 orr.w r2, r2, #4096 ; 0x1000 8005e88: 605a str r2, [r3, #4] } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8005e8a: 68fb ldr r3, [r7, #12] 8005e8c: 681b ldr r3, [r3, #0] 8005e8e: 681b ldr r3, [r3, #0] 8005e90: f003 0340 and.w r3, r3, #64 ; 0x40 8005e94: 2b40 cmp r3, #64 ; 0x40 8005e96: d007 beq.n 8005ea8 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8005e98: 68fb ldr r3, [r7, #12] 8005e9a: 681b ldr r3, [r3, #0] 8005e9c: 681a ldr r2, [r3, #0] 8005e9e: 68fb ldr r3, [r7, #12] 8005ea0: 681b ldr r3, [r3, #0] 8005ea2: f042 0240 orr.w r2, r2, #64 ; 0x40 8005ea6: 601a str r2, [r3, #0] } /* Transmit and Receive data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8005ea8: 68fb ldr r3, [r7, #12] 8005eaa: 68db ldr r3, [r3, #12] 8005eac: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 8005eb0: d97c bls.n 8005fac { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8005eb2: 68fb ldr r3, [r7, #12] 8005eb4: 685b ldr r3, [r3, #4] 8005eb6: 2b00 cmp r3, #0 8005eb8: d002 beq.n 8005ec0 8005eba: 8a7b ldrh r3, [r7, #18] 8005ebc: 2b01 cmp r3, #1 8005ebe: d169 bne.n 8005f94 { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 8005ec0: 68fb ldr r3, [r7, #12] 8005ec2: 6b9b ldr r3, [r3, #56] ; 0x38 8005ec4: 881a ldrh r2, [r3, #0] 8005ec6: 68fb ldr r3, [r7, #12] 8005ec8: 681b ldr r3, [r3, #0] 8005eca: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8005ecc: 68fb ldr r3, [r7, #12] 8005ece: 6b9b ldr r3, [r3, #56] ; 0x38 8005ed0: 1c9a adds r2, r3, #2 8005ed2: 68fb ldr r3, [r7, #12] 8005ed4: 639a str r2, [r3, #56] ; 0x38 hspi->TxXferCount--; 8005ed6: 68fb ldr r3, [r7, #12] 8005ed8: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005eda: b29b uxth r3, r3 8005edc: 3b01 subs r3, #1 8005ede: b29a uxth r2, r3 8005ee0: 68fb ldr r3, [r7, #12] 8005ee2: 87da strh r2, [r3, #62] ; 0x3e } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8005ee4: e056 b.n 8005f94 { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 8005ee6: 68fb ldr r3, [r7, #12] 8005ee8: 681b ldr r3, [r3, #0] 8005eea: 689b ldr r3, [r3, #8] 8005eec: f003 0302 and.w r3, r3, #2 8005ef0: 2b02 cmp r3, #2 8005ef2: d11b bne.n 8005f2c 8005ef4: 68fb ldr r3, [r7, #12] 8005ef6: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005ef8: b29b uxth r3, r3 8005efa: 2b00 cmp r3, #0 8005efc: d016 beq.n 8005f2c 8005efe: 6a7b ldr r3, [r7, #36] ; 0x24 8005f00: 2b01 cmp r3, #1 8005f02: d113 bne.n 8005f2c { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 8005f04: 68fb ldr r3, [r7, #12] 8005f06: 6b9b ldr r3, [r3, #56] ; 0x38 8005f08: 881a ldrh r2, [r3, #0] 8005f0a: 68fb ldr r3, [r7, #12] 8005f0c: 681b ldr r3, [r3, #0] 8005f0e: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8005f10: 68fb ldr r3, [r7, #12] 8005f12: 6b9b ldr r3, [r3, #56] ; 0x38 8005f14: 1c9a adds r2, r3, #2 8005f16: 68fb ldr r3, [r7, #12] 8005f18: 639a str r2, [r3, #56] ; 0x38 hspi->TxXferCount--; 8005f1a: 68fb ldr r3, [r7, #12] 8005f1c: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005f1e: b29b uxth r3, r3 8005f20: 3b01 subs r3, #1 8005f22: b29a uxth r2, r3 8005f24: 68fb ldr r3, [r7, #12] 8005f26: 87da strh r2, [r3, #62] ; 0x3e /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 8005f28: 2300 movs r3, #0 8005f2a: 627b str r3, [r7, #36] ; 0x24 } #endif /* USE_SPI_CRC */ } /* Check RXNE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 8005f2c: 68fb ldr r3, [r7, #12] 8005f2e: 681b ldr r3, [r3, #0] 8005f30: 689b ldr r3, [r3, #8] 8005f32: f003 0301 and.w r3, r3, #1 8005f36: 2b01 cmp r3, #1 8005f38: d11c bne.n 8005f74 8005f3a: 68fb ldr r3, [r7, #12] 8005f3c: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 8005f40: b29b uxth r3, r3 8005f42: 2b00 cmp r3, #0 8005f44: d016 beq.n 8005f74 { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 8005f46: 68fb ldr r3, [r7, #12] 8005f48: 681b ldr r3, [r3, #0] 8005f4a: 68da ldr r2, [r3, #12] 8005f4c: 68fb ldr r3, [r7, #12] 8005f4e: 6c1b ldr r3, [r3, #64] ; 0x40 8005f50: b292 uxth r2, r2 8005f52: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 8005f54: 68fb ldr r3, [r7, #12] 8005f56: 6c1b ldr r3, [r3, #64] ; 0x40 8005f58: 1c9a adds r2, r3, #2 8005f5a: 68fb ldr r3, [r7, #12] 8005f5c: 641a str r2, [r3, #64] ; 0x40 hspi->RxXferCount--; 8005f5e: 68fb ldr r3, [r7, #12] 8005f60: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 8005f64: b29b uxth r3, r3 8005f66: 3b01 subs r3, #1 8005f68: b29a uxth r2, r3 8005f6a: 68fb ldr r3, [r7, #12] 8005f6c: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 8005f70: 2301 movs r3, #1 8005f72: 627b str r3, [r7, #36] ; 0x24 } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) 8005f74: f7fc f976 bl 8002264 8005f78: 4602 mov r2, r0 8005f7a: 69fb ldr r3, [r7, #28] 8005f7c: 1ad3 subs r3, r2, r3 8005f7e: 6b3a ldr r2, [r7, #48] ; 0x30 8005f80: 429a cmp r2, r3 8005f82: d807 bhi.n 8005f94 8005f84: 6b3b ldr r3, [r7, #48] ; 0x30 8005f86: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8005f8a: d003 beq.n 8005f94 { errorcode = HAL_TIMEOUT; 8005f8c: 2303 movs r3, #3 8005f8e: f887 3023 strb.w r3, [r7, #35] ; 0x23 goto error; 8005f92: e0fb b.n 800618c while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8005f94: 68fb ldr r3, [r7, #12] 8005f96: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005f98: b29b uxth r3, r3 8005f9a: 2b00 cmp r3, #0 8005f9c: d1a3 bne.n 8005ee6 8005f9e: 68fb ldr r3, [r7, #12] 8005fa0: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 8005fa4: b29b uxth r3, r3 8005fa6: 2b00 cmp r3, #0 8005fa8: d19d bne.n 8005ee6 8005faa: e0df b.n 800616c } } /* Transmit and Receive data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8005fac: 68fb ldr r3, [r7, #12] 8005fae: 685b ldr r3, [r3, #4] 8005fb0: 2b00 cmp r3, #0 8005fb2: d003 beq.n 8005fbc 8005fb4: 8a7b ldrh r3, [r7, #18] 8005fb6: 2b01 cmp r3, #1 8005fb8: f040 80cb bne.w 8006152 { if (hspi->TxXferCount > 1U) 8005fbc: 68fb ldr r3, [r7, #12] 8005fbe: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005fc0: b29b uxth r3, r3 8005fc2: 2b01 cmp r3, #1 8005fc4: d912 bls.n 8005fec { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 8005fc6: 68fb ldr r3, [r7, #12] 8005fc8: 6b9b ldr r3, [r3, #56] ; 0x38 8005fca: 881a ldrh r2, [r3, #0] 8005fcc: 68fb ldr r3, [r7, #12] 8005fce: 681b ldr r3, [r3, #0] 8005fd0: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8005fd2: 68fb ldr r3, [r7, #12] 8005fd4: 6b9b ldr r3, [r3, #56] ; 0x38 8005fd6: 1c9a adds r2, r3, #2 8005fd8: 68fb ldr r3, [r7, #12] 8005fda: 639a str r2, [r3, #56] ; 0x38 hspi->TxXferCount -= 2U; 8005fdc: 68fb ldr r3, [r7, #12] 8005fde: 8fdb ldrh r3, [r3, #62] ; 0x3e 8005fe0: b29b uxth r3, r3 8005fe2: 3b02 subs r3, #2 8005fe4: b29a uxth r2, r3 8005fe6: 68fb ldr r3, [r7, #12] 8005fe8: 87da strh r2, [r3, #62] ; 0x3e 8005fea: e0b2 b.n 8006152 } else { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); 8005fec: 68fb ldr r3, [r7, #12] 8005fee: 6b9a ldr r2, [r3, #56] ; 0x38 8005ff0: 68fb ldr r3, [r7, #12] 8005ff2: 681b ldr r3, [r3, #0] 8005ff4: 330c adds r3, #12 8005ff6: 7812 ldrb r2, [r2, #0] 8005ff8: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 8005ffa: 68fb ldr r3, [r7, #12] 8005ffc: 6b9b ldr r3, [r3, #56] ; 0x38 8005ffe: 1c5a adds r2, r3, #1 8006000: 68fb ldr r3, [r7, #12] 8006002: 639a str r2, [r3, #56] ; 0x38 hspi->TxXferCount--; 8006004: 68fb ldr r3, [r7, #12] 8006006: 8fdb ldrh r3, [r3, #62] ; 0x3e 8006008: b29b uxth r3, r3 800600a: 3b01 subs r3, #1 800600c: b29a uxth r2, r3 800600e: 68fb ldr r3, [r7, #12] 8006010: 87da strh r2, [r3, #62] ; 0x3e } } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8006012: e09e b.n 8006152 { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 8006014: 68fb ldr r3, [r7, #12] 8006016: 681b ldr r3, [r3, #0] 8006018: 689b ldr r3, [r3, #8] 800601a: f003 0302 and.w r3, r3, #2 800601e: 2b02 cmp r3, #2 8006020: d134 bne.n 800608c 8006022: 68fb ldr r3, [r7, #12] 8006024: 8fdb ldrh r3, [r3, #62] ; 0x3e 8006026: b29b uxth r3, r3 8006028: 2b00 cmp r3, #0 800602a: d02f beq.n 800608c 800602c: 6a7b ldr r3, [r7, #36] ; 0x24 800602e: 2b01 cmp r3, #1 8006030: d12c bne.n 800608c { if (hspi->TxXferCount > 1U) 8006032: 68fb ldr r3, [r7, #12] 8006034: 8fdb ldrh r3, [r3, #62] ; 0x3e 8006036: b29b uxth r3, r3 8006038: 2b01 cmp r3, #1 800603a: d912 bls.n 8006062 { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 800603c: 68fb ldr r3, [r7, #12] 800603e: 6b9b ldr r3, [r3, #56] ; 0x38 8006040: 881a ldrh r2, [r3, #0] 8006042: 68fb ldr r3, [r7, #12] 8006044: 681b ldr r3, [r3, #0] 8006046: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8006048: 68fb ldr r3, [r7, #12] 800604a: 6b9b ldr r3, [r3, #56] ; 0x38 800604c: 1c9a adds r2, r3, #2 800604e: 68fb ldr r3, [r7, #12] 8006050: 639a str r2, [r3, #56] ; 0x38 hspi->TxXferCount -= 2U; 8006052: 68fb ldr r3, [r7, #12] 8006054: 8fdb ldrh r3, [r3, #62] ; 0x3e 8006056: b29b uxth r3, r3 8006058: 3b02 subs r3, #2 800605a: b29a uxth r2, r3 800605c: 68fb ldr r3, [r7, #12] 800605e: 87da strh r2, [r3, #62] ; 0x3e 8006060: e012 b.n 8006088 } else { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); 8006062: 68fb ldr r3, [r7, #12] 8006064: 6b9a ldr r2, [r3, #56] ; 0x38 8006066: 68fb ldr r3, [r7, #12] 8006068: 681b ldr r3, [r3, #0] 800606a: 330c adds r3, #12 800606c: 7812 ldrb r2, [r2, #0] 800606e: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 8006070: 68fb ldr r3, [r7, #12] 8006072: 6b9b ldr r3, [r3, #56] ; 0x38 8006074: 1c5a adds r2, r3, #1 8006076: 68fb ldr r3, [r7, #12] 8006078: 639a str r2, [r3, #56] ; 0x38 hspi->TxXferCount--; 800607a: 68fb ldr r3, [r7, #12] 800607c: 8fdb ldrh r3, [r3, #62] ; 0x3e 800607e: b29b uxth r3, r3 8006080: 3b01 subs r3, #1 8006082: b29a uxth r2, r3 8006084: 68fb ldr r3, [r7, #12] 8006086: 87da strh r2, [r3, #62] ; 0x3e } /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 8006088: 2300 movs r3, #0 800608a: 627b str r3, [r7, #36] ; 0x24 } #endif /* USE_SPI_CRC */ } /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 800608c: 68fb ldr r3, [r7, #12] 800608e: 681b ldr r3, [r3, #0] 8006090: 689b ldr r3, [r3, #8] 8006092: f003 0301 and.w r3, r3, #1 8006096: 2b01 cmp r3, #1 8006098: d148 bne.n 800612c 800609a: 68fb ldr r3, [r7, #12] 800609c: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 80060a0: b29b uxth r3, r3 80060a2: 2b00 cmp r3, #0 80060a4: d042 beq.n 800612c { if (hspi->RxXferCount > 1U) 80060a6: 68fb ldr r3, [r7, #12] 80060a8: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 80060ac: b29b uxth r3, r3 80060ae: 2b01 cmp r3, #1 80060b0: d923 bls.n 80060fa { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 80060b2: 68fb ldr r3, [r7, #12] 80060b4: 681b ldr r3, [r3, #0] 80060b6: 68da ldr r2, [r3, #12] 80060b8: 68fb ldr r3, [r7, #12] 80060ba: 6c1b ldr r3, [r3, #64] ; 0x40 80060bc: b292 uxth r2, r2 80060be: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 80060c0: 68fb ldr r3, [r7, #12] 80060c2: 6c1b ldr r3, [r3, #64] ; 0x40 80060c4: 1c9a adds r2, r3, #2 80060c6: 68fb ldr r3, [r7, #12] 80060c8: 641a str r2, [r3, #64] ; 0x40 hspi->RxXferCount -= 2U; 80060ca: 68fb ldr r3, [r7, #12] 80060cc: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 80060d0: b29b uxth r3, r3 80060d2: 3b02 subs r3, #2 80060d4: b29a uxth r2, r3 80060d6: 68fb ldr r3, [r7, #12] 80060d8: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 if (hspi->RxXferCount <= 1U) 80060dc: 68fb ldr r3, [r7, #12] 80060de: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 80060e2: b29b uxth r3, r3 80060e4: 2b01 cmp r3, #1 80060e6: d81f bhi.n 8006128 { /* Set RX Fifo threshold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 80060e8: 68fb ldr r3, [r7, #12] 80060ea: 681b ldr r3, [r3, #0] 80060ec: 685a ldr r2, [r3, #4] 80060ee: 68fb ldr r3, [r7, #12] 80060f0: 681b ldr r3, [r3, #0] 80060f2: f442 5280 orr.w r2, r2, #4096 ; 0x1000 80060f6: 605a str r2, [r3, #4] 80060f8: e016 b.n 8006128 } } else { (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; 80060fa: 68fb ldr r3, [r7, #12] 80060fc: 681b ldr r3, [r3, #0] 80060fe: f103 020c add.w r2, r3, #12 8006102: 68fb ldr r3, [r7, #12] 8006104: 6c1b ldr r3, [r3, #64] ; 0x40 8006106: 7812 ldrb r2, [r2, #0] 8006108: b2d2 uxtb r2, r2 800610a: 701a strb r2, [r3, #0] hspi->pRxBuffPtr++; 800610c: 68fb ldr r3, [r7, #12] 800610e: 6c1b ldr r3, [r3, #64] ; 0x40 8006110: 1c5a adds r2, r3, #1 8006112: 68fb ldr r3, [r7, #12] 8006114: 641a str r2, [r3, #64] ; 0x40 hspi->RxXferCount--; 8006116: 68fb ldr r3, [r7, #12] 8006118: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 800611c: b29b uxth r3, r3 800611e: 3b01 subs r3, #1 8006120: b29a uxth r2, r3 8006122: 68fb ldr r3, [r7, #12] 8006124: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 } /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 8006128: 2301 movs r3, #1 800612a: 627b str r3, [r7, #36] ; 0x24 } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) 800612c: f7fc f89a bl 8002264 8006130: 4602 mov r2, r0 8006132: 69fb ldr r3, [r7, #28] 8006134: 1ad3 subs r3, r2, r3 8006136: 6b3a ldr r2, [r7, #48] ; 0x30 8006138: 429a cmp r2, r3 800613a: d803 bhi.n 8006144 800613c: 6b3b ldr r3, [r7, #48] ; 0x30 800613e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8006142: d102 bne.n 800614a 8006144: 6b3b ldr r3, [r7, #48] ; 0x30 8006146: 2b00 cmp r3, #0 8006148: d103 bne.n 8006152 { errorcode = HAL_TIMEOUT; 800614a: 2303 movs r3, #3 800614c: f887 3023 strb.w r3, [r7, #35] ; 0x23 goto error; 8006150: e01c b.n 800618c while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8006152: 68fb ldr r3, [r7, #12] 8006154: 8fdb ldrh r3, [r3, #62] ; 0x3e 8006156: b29b uxth r3, r3 8006158: 2b00 cmp r3, #0 800615a: f47f af5b bne.w 8006014 800615e: 68fb ldr r3, [r7, #12] 8006160: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 8006164: b29b uxth r3, r3 8006166: 2b00 cmp r3, #0 8006168: f47f af54 bne.w 8006014 errorcode = HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 800616c: 69fa ldr r2, [r7, #28] 800616e: 6b39 ldr r1, [r7, #48] ; 0x30 8006170: 68f8 ldr r0, [r7, #12] 8006172: f000 f937 bl 80063e4 8006176: 4603 mov r3, r0 8006178: 2b00 cmp r3, #0 800617a: d006 beq.n 800618a { errorcode = HAL_ERROR; 800617c: 2301 movs r3, #1 800617e: f887 3023 strb.w r3, [r7, #35] ; 0x23 hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 8006182: 68fb ldr r3, [r7, #12] 8006184: 2220 movs r2, #32 8006186: 661a str r2, [r3, #96] ; 0x60 8006188: e000 b.n 800618c } error : 800618a: bf00 nop hspi->State = HAL_SPI_STATE_READY; 800618c: 68fb ldr r3, [r7, #12] 800618e: 2201 movs r2, #1 8006190: f883 205d strb.w r2, [r3, #93] ; 0x5d __HAL_UNLOCK(hspi); 8006194: 68fb ldr r3, [r7, #12] 8006196: 2200 movs r2, #0 8006198: f883 205c strb.w r2, [r3, #92] ; 0x5c return errorcode; 800619c: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 } 80061a0: 4618 mov r0, r3 80061a2: 3728 adds r7, #40 ; 0x28 80061a4: 46bd mov sp, r7 80061a6: bd80 pop {r7, pc} 080061a8 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { 80061a8: b580 push {r7, lr} 80061aa: b088 sub sp, #32 80061ac: af00 add r7, sp, #0 80061ae: 60f8 str r0, [r7, #12] 80061b0: 60b9 str r1, [r7, #8] 80061b2: 603b str r3, [r7, #0] 80061b4: 4613 mov r3, r2 80061b6: 71fb strb r3, [r7, #7] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 80061b8: f7fc f854 bl 8002264 80061bc: 4602 mov r2, r0 80061be: 6abb ldr r3, [r7, #40] ; 0x28 80061c0: 1a9b subs r3, r3, r2 80061c2: 683a ldr r2, [r7, #0] 80061c4: 4413 add r3, r2 80061c6: 61fb str r3, [r7, #28] tmp_tickstart = HAL_GetTick(); 80061c8: f7fc f84c bl 8002264 80061cc: 61b8 str r0, [r7, #24] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); 80061ce: 4b39 ldr r3, [pc, #228] ; (80062b4 ) 80061d0: 681b ldr r3, [r3, #0] 80061d2: 015b lsls r3, r3, #5 80061d4: 0d1b lsrs r3, r3, #20 80061d6: 69fa ldr r2, [r7, #28] 80061d8: fb02 f303 mul.w r3, r2, r3 80061dc: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 80061de: e054 b.n 800628a { if (Timeout != HAL_MAX_DELAY) 80061e0: 683b ldr r3, [r7, #0] 80061e2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80061e6: d050 beq.n 800628a { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 80061e8: f7fc f83c bl 8002264 80061ec: 4602 mov r2, r0 80061ee: 69bb ldr r3, [r7, #24] 80061f0: 1ad3 subs r3, r2, r3 80061f2: 69fa ldr r2, [r7, #28] 80061f4: 429a cmp r2, r3 80061f6: d902 bls.n 80061fe 80061f8: 69fb ldr r3, [r7, #28] 80061fa: 2b00 cmp r3, #0 80061fc: d13d bne.n 800627a /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 80061fe: 68fb ldr r3, [r7, #12] 8006200: 681b ldr r3, [r3, #0] 8006202: 685a ldr r2, [r3, #4] 8006204: 68fb ldr r3, [r7, #12] 8006206: 681b ldr r3, [r3, #0] 8006208: f022 02e0 bic.w r2, r2, #224 ; 0xe0 800620c: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800620e: 68fb ldr r3, [r7, #12] 8006210: 685b ldr r3, [r3, #4] 8006212: f5b3 7f82 cmp.w r3, #260 ; 0x104 8006216: d111 bne.n 800623c 8006218: 68fb ldr r3, [r7, #12] 800621a: 689b ldr r3, [r3, #8] 800621c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8006220: d004 beq.n 800622c || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 8006222: 68fb ldr r3, [r7, #12] 8006224: 689b ldr r3, [r3, #8] 8006226: f5b3 6f80 cmp.w r3, #1024 ; 0x400 800622a: d107 bne.n 800623c { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800622c: 68fb ldr r3, [r7, #12] 800622e: 681b ldr r3, [r3, #0] 8006230: 681a ldr r2, [r3, #0] 8006232: 68fb ldr r3, [r7, #12] 8006234: 681b ldr r3, [r3, #0] 8006236: f022 0240 bic.w r2, r2, #64 ; 0x40 800623a: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 800623c: 68fb ldr r3, [r7, #12] 800623e: 6a9b ldr r3, [r3, #40] ; 0x28 8006240: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8006244: d10f bne.n 8006266 { SPI_RESET_CRC(hspi); 8006246: 68fb ldr r3, [r7, #12] 8006248: 681b ldr r3, [r3, #0] 800624a: 681a ldr r2, [r3, #0] 800624c: 68fb ldr r3, [r7, #12] 800624e: 681b ldr r3, [r3, #0] 8006250: f422 5200 bic.w r2, r2, #8192 ; 0x2000 8006254: 601a str r2, [r3, #0] 8006256: 68fb ldr r3, [r7, #12] 8006258: 681b ldr r3, [r3, #0] 800625a: 681a ldr r2, [r3, #0] 800625c: 68fb ldr r3, [r7, #12] 800625e: 681b ldr r3, [r3, #0] 8006260: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8006264: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 8006266: 68fb ldr r3, [r7, #12] 8006268: 2201 movs r2, #1 800626a: f883 205d strb.w r2, [r3, #93] ; 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 800626e: 68fb ldr r3, [r7, #12] 8006270: 2200 movs r2, #0 8006272: f883 205c strb.w r2, [r3, #92] ; 0x5c return HAL_TIMEOUT; 8006276: 2303 movs r3, #3 8006278: e017 b.n 80062aa } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if(count == 0U) 800627a: 697b ldr r3, [r7, #20] 800627c: 2b00 cmp r3, #0 800627e: d101 bne.n 8006284 { tmp_timeout = 0U; 8006280: 2300 movs r3, #0 8006282: 61fb str r3, [r7, #28] } count--; 8006284: 697b ldr r3, [r7, #20] 8006286: 3b01 subs r3, #1 8006288: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 800628a: 68fb ldr r3, [r7, #12] 800628c: 681b ldr r3, [r3, #0] 800628e: 689a ldr r2, [r3, #8] 8006290: 68bb ldr r3, [r7, #8] 8006292: 4013 ands r3, r2 8006294: 68ba ldr r2, [r7, #8] 8006296: 429a cmp r2, r3 8006298: bf0c ite eq 800629a: 2301 moveq r3, #1 800629c: 2300 movne r3, #0 800629e: b2db uxtb r3, r3 80062a0: 461a mov r2, r3 80062a2: 79fb ldrb r3, [r7, #7] 80062a4: 429a cmp r2, r3 80062a6: d19b bne.n 80061e0 } } return HAL_OK; 80062a8: 2300 movs r3, #0 } 80062aa: 4618 mov r0, r3 80062ac: 3720 adds r7, #32 80062ae: 46bd mov sp, r7 80062b0: bd80 pop {r7, pc} 80062b2: bf00 nop 80062b4: 20000008 .word 0x20000008 080062b8 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { 80062b8: b580 push {r7, lr} 80062ba: b08a sub sp, #40 ; 0x28 80062bc: af00 add r7, sp, #0 80062be: 60f8 str r0, [r7, #12] 80062c0: 60b9 str r1, [r7, #8] 80062c2: 607a str r2, [r7, #4] 80062c4: 603b str r3, [r7, #0] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; __IO uint8_t * ptmpreg8; __IO uint8_t tmpreg8 = 0; 80062c6: 2300 movs r3, #0 80062c8: 75fb strb r3, [r7, #23] /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 80062ca: f7fb ffcb bl 8002264 80062ce: 4602 mov r2, r0 80062d0: 6b3b ldr r3, [r7, #48] ; 0x30 80062d2: 1a9b subs r3, r3, r2 80062d4: 683a ldr r2, [r7, #0] 80062d6: 4413 add r3, r2 80062d8: 627b str r3, [r7, #36] ; 0x24 tmp_tickstart = HAL_GetTick(); 80062da: f7fb ffc3 bl 8002264 80062de: 6238 str r0, [r7, #32] /* Initialize the 8bit temporary pointer */ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; 80062e0: 68fb ldr r3, [r7, #12] 80062e2: 681b ldr r3, [r3, #0] 80062e4: 330c adds r3, #12 80062e6: 61fb str r3, [r7, #28] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); 80062e8: 4b3d ldr r3, [pc, #244] ; (80063e0 ) 80062ea: 681a ldr r2, [r3, #0] 80062ec: 4613 mov r3, r2 80062ee: 009b lsls r3, r3, #2 80062f0: 4413 add r3, r2 80062f2: 00da lsls r2, r3, #3 80062f4: 1ad3 subs r3, r2, r3 80062f6: 0d1b lsrs r3, r3, #20 80062f8: 6a7a ldr r2, [r7, #36] ; 0x24 80062fa: fb02 f303 mul.w r3, r2, r3 80062fe: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 8006300: e060 b.n 80063c4 { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) 8006302: 68bb ldr r3, [r7, #8] 8006304: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 8006308: d107 bne.n 800631a 800630a: 687b ldr r3, [r7, #4] 800630c: 2b00 cmp r3, #0 800630e: d104 bne.n 800631a { /* Flush Data Register by a blank read */ tmpreg8 = *ptmpreg8; 8006310: 69fb ldr r3, [r7, #28] 8006312: 781b ldrb r3, [r3, #0] 8006314: b2db uxtb r3, r3 8006316: 75fb strb r3, [r7, #23] /* To avoid GCC warning */ UNUSED(tmpreg8); 8006318: 7dfb ldrb r3, [r7, #23] } if (Timeout != HAL_MAX_DELAY) 800631a: 683b ldr r3, [r7, #0] 800631c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8006320: d050 beq.n 80063c4 { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 8006322: f7fb ff9f bl 8002264 8006326: 4602 mov r2, r0 8006328: 6a3b ldr r3, [r7, #32] 800632a: 1ad3 subs r3, r2, r3 800632c: 6a7a ldr r2, [r7, #36] ; 0x24 800632e: 429a cmp r2, r3 8006330: d902 bls.n 8006338 8006332: 6a7b ldr r3, [r7, #36] ; 0x24 8006334: 2b00 cmp r3, #0 8006336: d13d bne.n 80063b4 /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 8006338: 68fb ldr r3, [r7, #12] 800633a: 681b ldr r3, [r3, #0] 800633c: 685a ldr r2, [r3, #4] 800633e: 68fb ldr r3, [r7, #12] 8006340: 681b ldr r3, [r3, #0] 8006342: f022 02e0 bic.w r2, r2, #224 ; 0xe0 8006346: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 8006348: 68fb ldr r3, [r7, #12] 800634a: 685b ldr r3, [r3, #4] 800634c: f5b3 7f82 cmp.w r3, #260 ; 0x104 8006350: d111 bne.n 8006376 8006352: 68fb ldr r3, [r7, #12] 8006354: 689b ldr r3, [r3, #8] 8006356: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800635a: d004 beq.n 8006366 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800635c: 68fb ldr r3, [r7, #12] 800635e: 689b ldr r3, [r3, #8] 8006360: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8006364: d107 bne.n 8006376 { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8006366: 68fb ldr r3, [r7, #12] 8006368: 681b ldr r3, [r3, #0] 800636a: 681a ldr r2, [r3, #0] 800636c: 68fb ldr r3, [r7, #12] 800636e: 681b ldr r3, [r3, #0] 8006370: f022 0240 bic.w r2, r2, #64 ; 0x40 8006374: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 8006376: 68fb ldr r3, [r7, #12] 8006378: 6a9b ldr r3, [r3, #40] ; 0x28 800637a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800637e: d10f bne.n 80063a0 { SPI_RESET_CRC(hspi); 8006380: 68fb ldr r3, [r7, #12] 8006382: 681b ldr r3, [r3, #0] 8006384: 681a ldr r2, [r3, #0] 8006386: 68fb ldr r3, [r7, #12] 8006388: 681b ldr r3, [r3, #0] 800638a: f422 5200 bic.w r2, r2, #8192 ; 0x2000 800638e: 601a str r2, [r3, #0] 8006390: 68fb ldr r3, [r7, #12] 8006392: 681b ldr r3, [r3, #0] 8006394: 681a ldr r2, [r3, #0] 8006396: 68fb ldr r3, [r7, #12] 8006398: 681b ldr r3, [r3, #0] 800639a: f442 5200 orr.w r2, r2, #8192 ; 0x2000 800639e: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 80063a0: 68fb ldr r3, [r7, #12] 80063a2: 2201 movs r2, #1 80063a4: f883 205d strb.w r2, [r3, #93] ; 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 80063a8: 68fb ldr r3, [r7, #12] 80063aa: 2200 movs r2, #0 80063ac: f883 205c strb.w r2, [r3, #92] ; 0x5c return HAL_TIMEOUT; 80063b0: 2303 movs r3, #3 80063b2: e010 b.n 80063d6 } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if(count == 0U) 80063b4: 69bb ldr r3, [r7, #24] 80063b6: 2b00 cmp r3, #0 80063b8: d101 bne.n 80063be { tmp_timeout = 0U; 80063ba: 2300 movs r3, #0 80063bc: 627b str r3, [r7, #36] ; 0x24 } count--; 80063be: 69bb ldr r3, [r7, #24] 80063c0: 3b01 subs r3, #1 80063c2: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 80063c4: 68fb ldr r3, [r7, #12] 80063c6: 681b ldr r3, [r3, #0] 80063c8: 689a ldr r2, [r3, #8] 80063ca: 68bb ldr r3, [r7, #8] 80063cc: 4013 ands r3, r2 80063ce: 687a ldr r2, [r7, #4] 80063d0: 429a cmp r2, r3 80063d2: d196 bne.n 8006302 } } return HAL_OK; 80063d4: 2300 movs r3, #0 } 80063d6: 4618 mov r0, r3 80063d8: 3728 adds r7, #40 ; 0x28 80063da: 46bd mov sp, r7 80063dc: bd80 pop {r7, pc} 80063de: bf00 nop 80063e0: 20000008 .word 0x20000008 080063e4 : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 80063e4: b580 push {r7, lr} 80063e6: b086 sub sp, #24 80063e8: af02 add r7, sp, #8 80063ea: 60f8 str r0, [r7, #12] 80063ec: 60b9 str r1, [r7, #8] 80063ee: 607a str r2, [r7, #4] /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 80063f0: 687b ldr r3, [r7, #4] 80063f2: 9300 str r3, [sp, #0] 80063f4: 68bb ldr r3, [r7, #8] 80063f6: 2200 movs r2, #0 80063f8: f44f 51c0 mov.w r1, #6144 ; 0x1800 80063fc: 68f8 ldr r0, [r7, #12] 80063fe: f7ff ff5b bl 80062b8 8006402: 4603 mov r3, r0 8006404: 2b00 cmp r3, #0 8006406: d007 beq.n 8006418 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8006408: 68fb ldr r3, [r7, #12] 800640a: 6e1b ldr r3, [r3, #96] ; 0x60 800640c: f043 0220 orr.w r2, r3, #32 8006410: 68fb ldr r3, [r7, #12] 8006412: 661a str r2, [r3, #96] ; 0x60 return HAL_TIMEOUT; 8006414: 2303 movs r3, #3 8006416: e027 b.n 8006468 } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 8006418: 687b ldr r3, [r7, #4] 800641a: 9300 str r3, [sp, #0] 800641c: 68bb ldr r3, [r7, #8] 800641e: 2200 movs r2, #0 8006420: 2180 movs r1, #128 ; 0x80 8006422: 68f8 ldr r0, [r7, #12] 8006424: f7ff fec0 bl 80061a8 8006428: 4603 mov r3, r0 800642a: 2b00 cmp r3, #0 800642c: d007 beq.n 800643e { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800642e: 68fb ldr r3, [r7, #12] 8006430: 6e1b ldr r3, [r3, #96] ; 0x60 8006432: f043 0220 orr.w r2, r3, #32 8006436: 68fb ldr r3, [r7, #12] 8006438: 661a str r2, [r3, #96] ; 0x60 return HAL_TIMEOUT; 800643a: 2303 movs r3, #3 800643c: e014 b.n 8006468 } /* Control if the RX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 800643e: 687b ldr r3, [r7, #4] 8006440: 9300 str r3, [sp, #0] 8006442: 68bb ldr r3, [r7, #8] 8006444: 2200 movs r2, #0 8006446: f44f 61c0 mov.w r1, #1536 ; 0x600 800644a: 68f8 ldr r0, [r7, #12] 800644c: f7ff ff34 bl 80062b8 8006450: 4603 mov r3, r0 8006452: 2b00 cmp r3, #0 8006454: d007 beq.n 8006466 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8006456: 68fb ldr r3, [r7, #12] 8006458: 6e1b ldr r3, [r3, #96] ; 0x60 800645a: f043 0220 orr.w r2, r3, #32 800645e: 68fb ldr r3, [r7, #12] 8006460: 661a str r2, [r3, #96] ; 0x60 return HAL_TIMEOUT; 8006462: 2303 movs r3, #3 8006464: e000 b.n 8006468 } return HAL_OK; 8006466: 2300 movs r3, #0 } 8006468: 4618 mov r0, r3 800646a: 3710 adds r7, #16 800646c: 46bd mov sp, r7 800646e: bd80 pop {r7, pc} 08006470 <__libc_init_array>: 8006470: b570 push {r4, r5, r6, lr} 8006472: 4d0d ldr r5, [pc, #52] ; (80064a8 <__libc_init_array+0x38>) 8006474: 4c0d ldr r4, [pc, #52] ; (80064ac <__libc_init_array+0x3c>) 8006476: 1b64 subs r4, r4, r5 8006478: 10a4 asrs r4, r4, #2 800647a: 2600 movs r6, #0 800647c: 42a6 cmp r6, r4 800647e: d109 bne.n 8006494 <__libc_init_array+0x24> 8006480: 4d0b ldr r5, [pc, #44] ; (80064b0 <__libc_init_array+0x40>) 8006482: 4c0c ldr r4, [pc, #48] ; (80064b4 <__libc_init_array+0x44>) 8006484: f000 f820 bl 80064c8 <_init> 8006488: 1b64 subs r4, r4, r5 800648a: 10a4 asrs r4, r4, #2 800648c: 2600 movs r6, #0 800648e: 42a6 cmp r6, r4 8006490: d105 bne.n 800649e <__libc_init_array+0x2e> 8006492: bd70 pop {r4, r5, r6, pc} 8006494: f855 3b04 ldr.w r3, [r5], #4 8006498: 4798 blx r3 800649a: 3601 adds r6, #1 800649c: e7ee b.n 800647c <__libc_init_array+0xc> 800649e: f855 3b04 ldr.w r3, [r5], #4 80064a2: 4798 blx r3 80064a4: 3601 adds r6, #1 80064a6: e7f2 b.n 800648e <__libc_init_array+0x1e> 80064a8: 08006510 .word 0x08006510 80064ac: 08006510 .word 0x08006510 80064b0: 08006510 .word 0x08006510 80064b4: 08006514 .word 0x08006514 080064b8 : 80064b8: 4402 add r2, r0 80064ba: 4603 mov r3, r0 80064bc: 4293 cmp r3, r2 80064be: d100 bne.n 80064c2 80064c0: 4770 bx lr 80064c2: f803 1b01 strb.w r1, [r3], #1 80064c6: e7f9 b.n 80064bc 080064c8 <_init>: 80064c8: b5f8 push {r3, r4, r5, r6, r7, lr} 80064ca: bf00 nop 80064cc: bcf8 pop {r3, r4, r5, r6, r7} 80064ce: bc08 pop {r3} 80064d0: 469e mov lr, r3 80064d2: 4770 bx lr 080064d4 <_fini>: 80064d4: b5f8 push {r3, r4, r5, r6, r7, lr} 80064d6: bf00 nop 80064d8: bcf8 pop {r3, r4, r5, r6, r7} 80064da: bc08 pop {r3} 80064dc: 469e mov lr, r3 80064de: 4770 bx lr