ARM GAS /tmp/ccq9ydWK.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "Testbench.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Core/Src/Testbench.c" 20 .section .text.canTestSendTemperatures,"ax",%progbits 21 .align 1 22 .global canTestSendTemperatures 23 .syntax unified 24 .thumb 25 .thumb_func 27 canTestSendTemperatures: 28 .LVL0: 29 .LFB130: 1:Core/Src/Testbench.c **** /* 2:Core/Src/Testbench.c **** * Testbench.c 3:Core/Src/Testbench.c **** * 4:Core/Src/Testbench.c **** * Created on: 13.03.2023 5:Core/Src/Testbench.c **** * Author: david 6:Core/Src/Testbench.c **** */ 7:Core/Src/Testbench.c **** 8:Core/Src/Testbench.c **** #include "Testbench.h" 9:Core/Src/Testbench.c **** #include "AMS_CAN.h" 10:Core/Src/Testbench.c **** #include "common_defs.h" 11:Core/Src/Testbench.c **** #include "AMS_CAN.h" 12:Core/Src/Testbench.c **** #include "AMS_HighLevel.h" 13:Core/Src/Testbench.c **** #include "stm32f3xx.h" 14:Core/Src/Testbench.c **** #include "stm32f3xx_hal.h" 15:Core/Src/Testbench.c **** #include "stm32f3xx_hal_can.h" 16:Core/Src/Testbench.c **** #include 17:Core/Src/Testbench.c **** #include "ADBMS_Abstraction.h" 18:Core/Src/Testbench.c **** #include "main.h" 19:Core/Src/Testbench.c **** 20:Core/Src/Testbench.c **** 21:Core/Src/Testbench.c **** void canTestSendTemperatures(uint16_t* data){ 30 .loc 1 21 45 view -0 31 .cfi_startproc 32 @ args = 0, pretend = 0, frame = 40 33 @ frame_needed = 0, uses_anonymous_args = 0 34 .loc 1 21 45 is_stmt 0 view .LVU1 35 0000 00B5 push {lr} 36 .cfi_def_cfa_offset 4 37 .cfi_offset 14, -4 ARM GAS /tmp/ccq9ydWK.s page 2 38 0002 8BB0 sub sp, sp, #44 39 .cfi_def_cfa_offset 48 22:Core/Src/Testbench.c **** static CAN_TxHeaderTypeDef header; 40 .loc 1 22 2 is_stmt 1 view .LVU2 23:Core/Src/Testbench.c **** 24:Core/Src/Testbench.c **** header.IDE = CAN_ID_STD; 41 .loc 1 24 2 view .LVU3 42 .loc 1 24 13 is_stmt 0 view .LVU4 43 0004 3B4A ldr r2, .L17 44 0006 0023 movs r3, #0 45 0008 9360 str r3, [r2, #8] 25:Core/Src/Testbench.c **** header.DLC = 8; 46 .loc 1 25 2 is_stmt 1 view .LVU5 47 .loc 1 25 13 is_stmt 0 view .LVU6 48 000a 0821 movs r1, #8 49 000c 1161 str r1, [r2, #16] 26:Core/Src/Testbench.c **** header.RTR = CAN_RTR_DATA; 50 .loc 1 26 2 is_stmt 1 view .LVU7 51 .loc 1 26 13 is_stmt 0 view .LVU8 52 000e D360 str r3, [r2, #12] 27:Core/Src/Testbench.c **** header.TransmitGlobalTime = DISABLE; 53 .loc 1 27 2 is_stmt 1 view .LVU9 54 .loc 1 27 28 is_stmt 0 view .LVU10 55 0010 1375 strb r3, [r2, #20] 28:Core/Src/Testbench.c **** uint8_t buffer[24]; 56 .loc 1 28 2 is_stmt 1 view .LVU11 29:Core/Src/Testbench.c **** uint8_t tmp[8]; 57 .loc 1 29 2 view .LVU12 30:Core/Src/Testbench.c **** 31:Core/Src/Testbench.c **** for(int i = 0; i < 12; i++){ 58 .loc 1 31 2 view .LVU13 59 .LBB2: 60 .loc 1 31 6 view .LVU14 61 .LVL1: 62 .loc 1 31 2 is_stmt 0 view .LVU15 63 0012 0EE0 b .L2 64 .LVL2: 65 .L3: 32:Core/Src/Testbench.c **** buffer[((i*2)+1)] = data[i] >> 8; 66 .loc 1 32 3 is_stmt 1 discriminator 3 view .LVU16 67 .loc 1 32 27 is_stmt 0 discriminator 3 view .LVU17 68 0014 30F813C0 ldrh ip, [r0, r3, lsl #1] 69 .loc 1 32 13 discriminator 3 view .LVU18 70 0018 5A00 lsls r2, r3, #1 71 .loc 1 32 21 discriminator 3 view .LVU19 72 001a 02F12901 add r1, r2, #41 73 001e 6944 add r1, sp, r1 74 0020 4FEA1C2E lsr lr, ip, #8 75 0024 01F818EC strb lr, [r1, #-24] 33:Core/Src/Testbench.c **** buffer[(i*2)] = data[i]; 76 .loc 1 33 3 is_stmt 1 discriminator 3 view .LVU20 77 .loc 1 33 17 is_stmt 0 discriminator 3 view .LVU21 78 0028 2832 adds r2, r2, #40 79 002a 6A44 add r2, sp, r2 80 002c 02F818CC strb ip, [r2, #-24] 31:Core/Src/Testbench.c **** buffer[((i*2)+1)] = data[i] >> 8; 81 .loc 1 31 26 is_stmt 1 discriminator 3 view .LVU22 ARM GAS /tmp/ccq9ydWK.s page 3 82 0030 0133 adds r3, r3, #1 83 .LVL3: 84 .L2: 31:Core/Src/Testbench.c **** buffer[((i*2)+1)] = data[i] >> 8; 85 .loc 1 31 19 discriminator 1 view .LVU23 86 0032 0B2B cmp r3, #11 87 0034 EEDD ble .L3 88 .LBE2: 89 .LBB3: 34:Core/Src/Testbench.c **** } 35:Core/Src/Testbench.c **** 36:Core/Src/Testbench.c **** for(int i = 0; i < 8; i++){ 90 .loc 1 36 10 is_stmt 0 view .LVU24 91 0036 0023 movs r3, #0 92 .LVL4: 93 .loc 1 36 10 view .LVU25 94 0038 07E0 b .L4 95 .LVL5: 96 .L5: 37:Core/Src/Testbench.c **** tmp[i] = buffer[i]; 97 .loc 1 37 3 is_stmt 1 discriminator 3 view .LVU26 98 .loc 1 37 18 is_stmt 0 discriminator 3 view .LVU27 99 003a 03F12802 add r2, r3, #40 100 003e 6A44 add r2, sp, r2 101 0040 12F8181C ldrb r1, [r2, #-24] @ zero_extendqisi2 102 .loc 1 37 10 discriminator 3 view .LVU28 103 0044 02F8201C strb r1, [r2, #-32] 36:Core/Src/Testbench.c **** tmp[i] = buffer[i]; 104 .loc 1 36 25 is_stmt 1 discriminator 3 view .LVU29 105 0048 0133 adds r3, r3, #1 106 .LVL6: 107 .L4: 36:Core/Src/Testbench.c **** tmp[i] = buffer[i]; 108 .loc 1 36 19 discriminator 1 view .LVU30 109 004a 072B cmp r3, #7 110 004c F5DD ble .L5 111 .LBE3: 38:Core/Src/Testbench.c **** } 39:Core/Src/Testbench.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { 112 .loc 1 39 2 view .LVU31 113 .loc 1 39 6 is_stmt 0 view .LVU32 114 004e 0A22 movs r2, #10 115 0050 0121 movs r1, #1 116 0052 294B ldr r3, .L17+4 117 .LVL7: 118 .loc 1 39 6 view .LVU33 119 0054 1868 ldr r0, [r3] 120 .LVL8: 121 .loc 1 39 6 view .LVU34 122 0056 FFF7FEFF bl ams_can_wait_for_free_mailboxes 123 .LVL9: 124 .loc 1 39 5 view .LVU35 125 005a 10B1 cbz r0, .L14 126 .L6: 127 .LBB4: 36:Core/Src/Testbench.c **** tmp[i] = buffer[i]; 128 .loc 1 36 10 discriminator 1 view .LVU36 ARM GAS /tmp/ccq9ydWK.s page 4 129 005c 0823 movs r3, #8 130 005e 0022 movs r2, #0 131 0060 13E0 b .L7 132 .L14: 133 .LBE4: 134 .LBB5: 40:Core/Src/Testbench.c **** uint32_t mailbox; 135 .loc 1 40 3 is_stmt 1 view .LVU37 41:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); 136 .loc 1 41 3 view .LVU38 137 0062 01AB add r3, sp, #4 138 0064 02AA add r2, sp, #8 139 0066 2349 ldr r1, .L17 140 0068 2348 ldr r0, .L17+4 141 006a 0068 ldr r0, [r0] 142 006c FFF7FEFF bl HAL_CAN_AddTxMessage 143 .LVL10: 144 0070 F4E7 b .L6 145 .LVL11: 146 .L8: 147 .loc 1 41 3 is_stmt 0 view .LVU39 148 .LBE5: 149 .LBB6: 42:Core/Src/Testbench.c **** } 43:Core/Src/Testbench.c **** 44:Core/Src/Testbench.c **** int m = 0; 45:Core/Src/Testbench.c **** for(int i = 8; i < 16; i++){ 46:Core/Src/Testbench.c **** tmp[m] = buffer[i]; 150 .loc 1 46 3 is_stmt 1 discriminator 3 view .LVU40 151 .loc 1 46 18 is_stmt 0 discriminator 3 view .LVU41 152 0072 03F12801 add r1, r3, #40 153 0076 6944 add r1, sp, r1 154 0078 11F8180C ldrb r0, [r1, #-24] @ zero_extendqisi2 155 .loc 1 46 10 discriminator 3 view .LVU42 156 007c 02F12801 add r1, r2, #40 157 0080 6944 add r1, sp, r1 158 0082 01F8200C strb r0, [r1, #-32] 47:Core/Src/Testbench.c **** m++; 159 .loc 1 47 3 is_stmt 1 discriminator 3 view .LVU43 160 .loc 1 47 4 is_stmt 0 discriminator 3 view .LVU44 161 0086 0132 adds r2, r2, #1 162 .LVL12: 45:Core/Src/Testbench.c **** tmp[m] = buffer[i]; 163 .loc 1 45 26 is_stmt 1 discriminator 3 view .LVU45 164 0088 0133 adds r3, r3, #1 165 .LVL13: 166 .L7: 45:Core/Src/Testbench.c **** tmp[m] = buffer[i]; 167 .loc 1 45 19 discriminator 1 view .LVU46 168 008a 0F2B cmp r3, #15 169 008c F1DD ble .L8 170 .LBE6: 48:Core/Src/Testbench.c **** } 49:Core/Src/Testbench.c **** 50:Core/Src/Testbench.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { 171 .loc 1 50 2 view .LVU47 172 .loc 1 50 6 is_stmt 0 view .LVU48 ARM GAS /tmp/ccq9ydWK.s page 5 173 008e 0A22 movs r2, #10 174 .LVL14: 175 .loc 1 50 6 view .LVU49 176 0090 0121 movs r1, #1 177 0092 194B ldr r3, .L17+4 178 .LVL15: 179 .loc 1 50 6 view .LVU50 180 0094 1868 ldr r0, [r3] 181 0096 FFF7FEFF bl ams_can_wait_for_free_mailboxes 182 .LVL16: 183 .loc 1 50 5 view .LVU51 184 009a 10B1 cbz r0, .L15 185 .L9: 186 .LBB7: 36:Core/Src/Testbench.c **** tmp[i] = buffer[i]; 187 .loc 1 36 10 discriminator 1 view .LVU52 188 009c 1023 movs r3, #16 189 009e 0022 movs r2, #0 190 00a0 13E0 b .L10 191 .L15: 192 .LBE7: 193 .LBB8: 51:Core/Src/Testbench.c **** uint32_t mailbox; 194 .loc 1 51 3 is_stmt 1 view .LVU53 52:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); 195 .loc 1 52 3 view .LVU54 196 00a2 01AB add r3, sp, #4 197 00a4 02AA add r2, sp, #8 198 00a6 1349 ldr r1, .L17 199 00a8 1348 ldr r0, .L17+4 200 00aa 0068 ldr r0, [r0] 201 00ac FFF7FEFF bl HAL_CAN_AddTxMessage 202 .LVL17: 203 00b0 F4E7 b .L9 204 .LVL18: 205 .L11: 206 .loc 1 52 3 is_stmt 0 view .LVU55 207 .LBE8: 208 .LBB9: 53:Core/Src/Testbench.c **** } 54:Core/Src/Testbench.c **** m = 0; 55:Core/Src/Testbench.c **** for(int i = 16; i < 24; i++){ 56:Core/Src/Testbench.c **** tmp[m] = buffer[i]; 209 .loc 1 56 3 is_stmt 1 discriminator 3 view .LVU56 210 .loc 1 56 18 is_stmt 0 discriminator 3 view .LVU57 211 00b2 03F12801 add r1, r3, #40 212 00b6 6944 add r1, sp, r1 213 00b8 11F8180C ldrb r0, [r1, #-24] @ zero_extendqisi2 214 .loc 1 56 10 discriminator 3 view .LVU58 215 00bc 02F12801 add r1, r2, #40 216 00c0 6944 add r1, sp, r1 217 00c2 01F8200C strb r0, [r1, #-32] 57:Core/Src/Testbench.c **** m++; 218 .loc 1 57 3 is_stmt 1 discriminator 3 view .LVU59 219 .loc 1 57 4 is_stmt 0 discriminator 3 view .LVU60 220 00c6 0132 adds r2, r2, #1 221 .LVL19: ARM GAS /tmp/ccq9ydWK.s page 6 55:Core/Src/Testbench.c **** tmp[m] = buffer[i]; 222 .loc 1 55 27 is_stmt 1 discriminator 3 view .LVU61 223 00c8 0133 adds r3, r3, #1 224 .LVL20: 225 .L10: 55:Core/Src/Testbench.c **** tmp[m] = buffer[i]; 226 .loc 1 55 20 discriminator 1 view .LVU62 227 00ca 172B cmp r3, #23 228 00cc F1DD ble .L11 229 .LBE9: 58:Core/Src/Testbench.c **** } 59:Core/Src/Testbench.c **** 60:Core/Src/Testbench.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { 230 .loc 1 60 2 view .LVU63 231 .loc 1 60 6 is_stmt 0 view .LVU64 232 00ce 0A22 movs r2, #10 233 .LVL21: 234 .loc 1 60 6 view .LVU65 235 00d0 0121 movs r1, #1 236 00d2 094B ldr r3, .L17+4 237 .LVL22: 238 .loc 1 60 6 view .LVU66 239 00d4 1868 ldr r0, [r3] 240 00d6 FFF7FEFF bl ams_can_wait_for_free_mailboxes 241 .LVL23: 242 .loc 1 60 5 view .LVU67 243 00da 10B1 cbz r0, .L16 244 .L1: 61:Core/Src/Testbench.c **** uint32_t mailbox; 62:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); 63:Core/Src/Testbench.c **** } 64:Core/Src/Testbench.c **** } 245 .loc 1 64 1 view .LVU68 246 00dc 0BB0 add sp, sp, #44 247 .cfi_remember_state 248 .cfi_def_cfa_offset 4 249 @ sp needed 250 00de 5DF804FB ldr pc, [sp], #4 251 .L16: 252 .cfi_restore_state 253 .LBB10: 61:Core/Src/Testbench.c **** uint32_t mailbox; 254 .loc 1 61 3 is_stmt 1 view .LVU69 62:Core/Src/Testbench.c **** } 255 .loc 1 62 3 view .LVU70 256 00e2 01AB add r3, sp, #4 257 00e4 02AA add r2, sp, #8 258 00e6 0349 ldr r1, .L17 259 00e8 0348 ldr r0, .L17+4 260 00ea 0068 ldr r0, [r0] 261 00ec FFF7FEFF bl HAL_CAN_AddTxMessage 262 .LVL24: 263 .LBE10: 264 .loc 1 64 1 is_stmt 0 view .LVU71 265 00f0 F4E7 b .L1 266 .L18: 267 00f2 00BF .align 2 ARM GAS /tmp/ccq9ydWK.s page 7 268 .L17: 269 00f4 00000000 .word header.1 270 00f8 00000000 .word ams_can_handle 271 .cfi_endproc 272 .LFE130: 274 .section .text.canTestSendAnswer,"ax",%progbits 275 .align 1 276 .global canTestSendAnswer 277 .syntax unified 278 .thumb 279 .thumb_func 281 canTestSendAnswer: 282 .LVL25: 283 .LFB131: 65:Core/Src/Testbench.c **** 66:Core/Src/Testbench.c **** void canTestSendAnswer(uint8_t* data){ 284 .loc 1 66 38 is_stmt 1 view -0 285 .cfi_startproc 286 @ args = 0, pretend = 0, frame = 8 287 @ frame_needed = 0, uses_anonymous_args = 0 288 .loc 1 66 38 is_stmt 0 view .LVU73 289 0000 10B5 push {r4, lr} 290 .cfi_def_cfa_offset 8 291 .cfi_offset 4, -8 292 .cfi_offset 14, -4 293 0002 82B0 sub sp, sp, #8 294 .cfi_def_cfa_offset 16 295 0004 0446 mov r4, r0 67:Core/Src/Testbench.c **** static CAN_TxHeaderTypeDef header; 296 .loc 1 67 2 is_stmt 1 view .LVU74 68:Core/Src/Testbench.c **** 69:Core/Src/Testbench.c **** header.IDE = CAN_ID_STD; 297 .loc 1 69 2 view .LVU75 298 .loc 1 69 13 is_stmt 0 view .LVU76 299 0006 0C4B ldr r3, .L23 300 0008 0021 movs r1, #0 301 000a 9960 str r1, [r3, #8] 70:Core/Src/Testbench.c **** header.DLC = 8; 302 .loc 1 70 2 is_stmt 1 view .LVU77 303 .loc 1 70 13 is_stmt 0 view .LVU78 304 000c 0822 movs r2, #8 305 000e 1A61 str r2, [r3, #16] 71:Core/Src/Testbench.c **** header.RTR = CAN_RTR_DATA; 306 .loc 1 71 2 is_stmt 1 view .LVU79 307 .loc 1 71 13 is_stmt 0 view .LVU80 308 0010 D960 str r1, [r3, #12] 72:Core/Src/Testbench.c **** header.TransmitGlobalTime = DISABLE; 309 .loc 1 72 2 is_stmt 1 view .LVU81 310 .loc 1 72 28 is_stmt 0 view .LVU82 311 0012 1975 strb r1, [r3, #20] 73:Core/Src/Testbench.c **** 74:Core/Src/Testbench.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, 312 .loc 1 74 4 is_stmt 1 view .LVU83 313 .loc 1 74 8 is_stmt 0 view .LVU84 314 0014 0A22 movs r2, #10 315 0016 0121 movs r1, #1 316 0018 084B ldr r3, .L23+4 ARM GAS /tmp/ccq9ydWK.s page 8 317 001a 1868 ldr r0, [r3] 318 .LVL26: 319 .loc 1 74 8 view .LVU85 320 001c FFF7FEFF bl ams_can_wait_for_free_mailboxes 321 .LVL27: 322 .loc 1 74 7 view .LVU86 323 0020 08B1 cbz r0, .L22 324 .L19: 75:Core/Src/Testbench.c **** CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { 76:Core/Src/Testbench.c **** uint32_t mailbox; 77:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); 78:Core/Src/Testbench.c **** } 79:Core/Src/Testbench.c **** } 325 .loc 1 79 1 view .LVU87 326 0022 02B0 add sp, sp, #8 327 .cfi_remember_state 328 .cfi_def_cfa_offset 8 329 @ sp needed 330 0024 10BD pop {r4, pc} 331 .LVL28: 332 .L22: 333 .cfi_restore_state 334 .LBB11: 76:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); 335 .loc 1 76 3 is_stmt 1 view .LVU88 77:Core/Src/Testbench.c **** } 336 .loc 1 77 3 view .LVU89 337 0026 01AB add r3, sp, #4 338 0028 2246 mov r2, r4 339 002a 0349 ldr r1, .L23 340 002c 0348 ldr r0, .L23+4 341 002e 0068 ldr r0, [r0] 342 0030 FFF7FEFF bl HAL_CAN_AddTxMessage 343 .LVL29: 344 .LBE11: 345 .loc 1 79 1 is_stmt 0 view .LVU90 346 0034 F5E7 b .L19 347 .L24: 348 0036 00BF .align 2 349 .L23: 350 0038 00000000 .word header.0 351 003c 00000000 .word ams_can_handle 352 .cfi_endproc 353 .LFE131: 355 .section .text.resetData,"ax",%progbits 356 .align 1 357 .global resetData 358 .syntax unified 359 .thumb 360 .thumb_func 362 resetData: 363 .LVL30: 364 .LFB132: 80:Core/Src/Testbench.c **** 81:Core/Src/Testbench.c **** void resetData(uint8_t* data){ 365 .loc 1 81 30 is_stmt 1 view -0 366 .cfi_startproc ARM GAS /tmp/ccq9ydWK.s page 9 367 @ args = 0, pretend = 0, frame = 0 368 @ frame_needed = 0, uses_anonymous_args = 0 369 @ link register save eliminated. 82:Core/Src/Testbench.c **** for(int i = 0; i < 8; i++){ 370 .loc 1 82 2 view .LVU92 371 .LBB12: 372 .loc 1 82 6 view .LVU93 373 .loc 1 82 10 is_stmt 0 view .LVU94 374 0000 0023 movs r3, #0 375 .loc 1 82 2 view .LVU95 376 0002 02E0 b .L26 377 .LVL31: 378 .L27: 83:Core/Src/Testbench.c **** data[0] = 0; 379 .loc 1 83 3 is_stmt 1 discriminator 3 view .LVU96 380 .loc 1 83 11 is_stmt 0 discriminator 3 view .LVU97 381 0004 0022 movs r2, #0 382 0006 0270 strb r2, [r0] 82:Core/Src/Testbench.c **** for(int i = 0; i < 8; i++){ 383 .loc 1 82 25 is_stmt 1 discriminator 3 view .LVU98 384 0008 0133 adds r3, r3, #1 385 .LVL32: 386 .L26: 82:Core/Src/Testbench.c **** for(int i = 0; i < 8; i++){ 387 .loc 1 82 19 discriminator 1 view .LVU99 388 000a 072B cmp r3, #7 389 000c FADD ble .L27 390 .LBE12: 84:Core/Src/Testbench.c **** } 85:Core/Src/Testbench.c **** 86:Core/Src/Testbench.c **** } 391 .loc 1 86 1 is_stmt 0 view .LVU100 392 000e 7047 bx lr 393 .cfi_endproc 394 .LFE132: 396 .section .text.readTemperatures,"ax",%progbits 397 .align 1 398 .global readTemperatures 399 .syntax unified 400 .thumb 401 .thumb_func 403 readTemperatures: 404 .LFB133: 87:Core/Src/Testbench.c **** void readTemperatures(){ 405 .loc 1 87 24 is_stmt 1 view -0 406 .cfi_startproc 407 @ args = 0, pretend = 0, frame = 24 408 @ frame_needed = 0, uses_anonymous_args = 0 409 0000 10B5 push {r4, lr} 410 .cfi_def_cfa_offset 8 411 .cfi_offset 4, -8 412 .cfi_offset 14, -4 413 0002 86B0 sub sp, sp, #24 414 .cfi_def_cfa_offset 32 88:Core/Src/Testbench.c **** uint8_t last_error = 0; 415 .loc 1 88 2 view .LVU102 416 .LVL33: ARM GAS /tmp/ccq9ydWK.s page 10 89:Core/Src/Testbench.c **** int N_SENSORS = 12; 417 .loc 1 89 2 view .LVU103 90:Core/Src/Testbench.c **** uint16_t temperatures[N_SENSORS]; 418 .loc 1 90 2 view .LVU104 91:Core/Src/Testbench.c **** for (int i = 0; i < N_SENSORS; i++) { 419 .loc 1 91 2 view .LVU105 420 .LBB13: 421 .loc 1 91 7 view .LVU106 422 .loc 1 91 11 is_stmt 0 view .LVU107 423 0004 0024 movs r4, #0 424 .loc 1 91 2 view .LVU108 425 0006 00E0 b .L29 426 .LVL34: 427 .L30: 428 .loc 1 91 34 is_stmt 1 discriminator 2 view .LVU109 429 0008 0134 adds r4, r4, #1 430 .LVL35: 431 .L29: 432 .loc 1 91 20 discriminator 1 view .LVU110 433 000a 0B2C cmp r4, #11 434 000c 0CDC bgt .L33 92:Core/Src/Testbench.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { 435 .loc 1 92 10 view .LVU111 436 .LBB14: 437 .loc 1 92 14 is_stmt 0 view .LVU112 438 000e 0DEB4401 add r1, sp, r4, lsl #1 439 0012 2046 mov r0, r4 440 0014 FFF7FEFF bl sensor_read 441 .LVL36: 442 .loc 1 92 13 view .LVU113 443 0018 0028 cmp r0, #0 444 001a F5D0 beq .L30 445 .LBB15: 93:Core/Src/Testbench.c **** sensor_init(i); 446 .loc 1 93 12 is_stmt 1 view .LVU114 447 001c 2046 mov r0, r4 448 001e FFF7FEFF bl sensor_init 449 .LVL37: 94:Core/Src/Testbench.c **** last_error = HAL_GetTick(); 450 .loc 1 94 12 view .LVU115 451 .loc 1 94 25 is_stmt 0 view .LVU116 452 0022 FFF7FEFF bl HAL_GetTick 453 .LVL38: 454 0026 EFE7 b .L30 455 .L33: 456 .LBE15: 457 .LBE14: 458 .LBE13: 95:Core/Src/Testbench.c **** } 96:Core/Src/Testbench.c **** } 97:Core/Src/Testbench.c **** canTestSendTemperatures(temperatures); 459 .loc 1 97 2 is_stmt 1 view .LVU117 460 0028 6846 mov r0, sp 461 002a FFF7FEFF bl canTestSendTemperatures 462 .LVL39: 98:Core/Src/Testbench.c **** } 463 .loc 1 98 1 is_stmt 0 view .LVU118 ARM GAS /tmp/ccq9ydWK.s page 11 464 002e 06B0 add sp, sp, #24 465 .cfi_def_cfa_offset 8 466 .LVL40: 467 .loc 1 98 1 view .LVU119 468 @ sp needed 469 0030 10BD pop {r4, pc} 470 .loc 1 98 1 view .LVU120 471 .cfi_endproc 472 .LFE133: 474 .section .text.testLoop,"ax",%progbits 475 .align 1 476 .global testLoop 477 .syntax unified 478 .thumb 479 .thumb_func 481 testLoop: 482 .LVL41: 483 .LFB134: 99:Core/Src/Testbench.c **** 100:Core/Src/Testbench.c **** void testLoop(uint8_t* data){ 484 .loc 1 100 29 is_stmt 1 view -0 485 .cfi_startproc 486 @ args = 0, pretend = 0, frame = 0 487 @ frame_needed = 0, uses_anonymous_args = 0 488 .loc 1 100 29 is_stmt 0 view .LVU122 489 0000 38B5 push {r3, r4, r5, lr} 490 .cfi_def_cfa_offset 16 491 .cfi_offset 3, -16 492 .cfi_offset 4, -12 493 .cfi_offset 5, -8 494 .cfi_offset 14, -4 495 0002 0546 mov r5, r0 101:Core/Src/Testbench.c **** uint8_t action = data[0]; 496 .loc 1 101 2 is_stmt 1 view .LVU123 497 .loc 1 101 10 is_stmt 0 view .LVU124 498 0004 0378 ldrb r3, [r0] @ zero_extendqisi2 499 .LVL42: 102:Core/Src/Testbench.c **** switch(action){ 500 .loc 1 102 2 is_stmt 1 view .LVU125 501 0006 013B subs r3, r3, #1 502 0008 042B cmp r3, #4 503 000a 0AD8 bhi .L35 504 000c DFE803F0 tbb [pc, r3] 505 .L37: 506 0010 03 .byte (.L41-.L37)/2 507 0011 0D .byte (.L40-.L37)/2 508 0012 16 .byte (.L39-.L37)/2 509 0013 1D .byte (.L38-.L37)/2 510 0014 48 .byte (.L36-.L37)/2 511 0015 00 .p2align 1 512 .L41: 103:Core/Src/Testbench.c **** case CAN_TEST: 104:Core/Src/Testbench.c **** HAL_Delay(100); 513 .loc 1 104 4 view .LVU126 514 0016 6420 movs r0, #100 515 .LVL43: 516 .loc 1 104 4 is_stmt 0 view .LVU127 ARM GAS /tmp/ccq9ydWK.s page 12 517 0018 FFF7FEFF bl HAL_Delay 518 .LVL44: 105:Core/Src/Testbench.c **** canTestSendAnswer(data); 519 .loc 1 105 4 is_stmt 1 view .LVU128 520 001c 2846 mov r0, r5 521 001e FFF7FEFF bl canTestSendAnswer 522 .LVL45: 106:Core/Src/Testbench.c **** break; 523 .loc 1 106 4 view .LVU129 524 .L35: 107:Core/Src/Testbench.c **** case VOLTAGE_TEST: 108:Core/Src/Testbench.c **** HAL_Delay(100); 109:Core/Src/Testbench.c **** amsReadCellVoltages(&module); 110:Core/Src/Testbench.c **** ams_can_send_heartbeat(); 111:Core/Src/Testbench.c **** break; 112:Core/Src/Testbench.c **** case TEMP_TEST: 113:Core/Src/Testbench.c **** HAL_Delay(1000); 114:Core/Src/Testbench.c **** readTemperatures(); 115:Core/Src/Testbench.c **** break; 116:Core/Src/Testbench.c **** case EPROM_TEST: 117:Core/Src/Testbench.c **** HAL_Delay(1000); 118:Core/Src/Testbench.c **** for(uint16_t i = 1; i < 9; i++ ){ 119:Core/Src/Testbench.c **** if(i == 4){ 120:Core/Src/Testbench.c **** writeeeprom(i*3, 0x42); 121:Core/Src/Testbench.c **** }else{ 122:Core/Src/Testbench.c **** writeeeprom(i*3, 0x69); 123:Core/Src/Testbench.c **** } 124:Core/Src/Testbench.c **** } 125:Core/Src/Testbench.c **** 126:Core/Src/Testbench.c **** HAL_Delay(1000); 127:Core/Src/Testbench.c **** for(uint16_t i = 1; i < 9; i++ ){ 128:Core/Src/Testbench.c **** data[i-1] = readeeprom(i*3); 129:Core/Src/Testbench.c **** } 130:Core/Src/Testbench.c **** canTestSendAnswer(data); 131:Core/Src/Testbench.c **** break; 132:Core/Src/Testbench.c **** case BALANCING_TEST: 133:Core/Src/Testbench.c **** HAL_Delay(1000); 134:Core/Src/Testbench.c **** for(int i = 0; i < 17; i++){ 135:Core/Src/Testbench.c **** amsConfigBalancing(0x00001<